	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mt76x02_phy_set_txpower        ## -- Begin function mt76x02_phy_set_txpower
	.p2align	4, 0x90
_mt76x02_phy_set_txpower:               ## @mt76x02_phy_set_txpower
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %ecx
	movq	%rdi, %rbx
	movq	_MT_TX_ALC_CFG_0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MT_TX_ALC_CFG_0_CH_INIT_0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_mt76_rmw_field
	movl	(%r15), %esi
	movq	_MT_TX_ALC_CFG_0_CH_INIT_1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %ecx
	callq	_mt76_rmw_field
	movq	_MT_TX_PWR_CFG_0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	24(%rbx), %rax
	movq	32(%rbx), %rcx
	movl	(%rcx), %edi
	movl	8(%rcx), %esi
	movl	(%rax), %edx
	movl	8(%rax), %ecx
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_1@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	8(%rbx), %rax
	movq	24(%rbx), %rcx
	movl	16(%rcx), %edi
	movl	24(%rcx), %esi
	movl	(%rax), %edx
	movl	8(%rax), %ecx
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_2@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	8(%rbx), %rax
	movl	16(%rax), %edi
	movl	24(%rax), %esi
	movl	32(%rax), %edx
	movl	40(%rax), %ecx
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_3@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%rbx), %rax
	movq	8(%rbx), %rcx
	movl	48(%rcx), %edi
	movl	56(%rcx), %esi
	movl	(%rax), %edx
	movl	8(%rax), %ecx
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_4@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%rbx), %rax
	movl	16(%rax), %edi
	movl	24(%rax), %esi
	xorl	%edx, %edx
	xorl	%ecx, %ecx
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_7@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	24(%rbx), %rax
	movl	28(%rax), %edi
	movq	8(%rbx), %rax
	movq	16(%rbx), %rcx
	movl	28(%rax), %edx
	movl	32(%rcx), %esi
	movl	36(%rcx), %ecx
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_8@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	8(%rbx), %rax
	movq	16(%rbx), %rcx
	movl	56(%rax), %edi
	movl	32(%rcx), %edx
	movl	36(%rcx), %ecx
	xorl	%esi, %esi
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_TX_PWR_CFG_9@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	(%rbx), %rax
	movq	8(%rbx), %rcx
	movl	28(%rcx), %edi
	movl	32(%rax), %edx
	movl	36(%rax), %ecx
	xorl	%esi, %esi
	callq	_mt76x02_tx_power_mask
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mt76_wr                        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MT_TX_ALC_CFG_0,4,2            ## @MT_TX_ALC_CFG_0
	.comm	_MT_TX_ALC_CFG_0_CH_INIT_0,4,2  ## @MT_TX_ALC_CFG_0_CH_INIT_0
	.comm	_MT_TX_ALC_CFG_0_CH_INIT_1,4,2  ## @MT_TX_ALC_CFG_0_CH_INIT_1
	.comm	_MT_TX_PWR_CFG_0,4,2            ## @MT_TX_PWR_CFG_0
	.comm	_MT_TX_PWR_CFG_1,4,2            ## @MT_TX_PWR_CFG_1
	.comm	_MT_TX_PWR_CFG_2,4,2            ## @MT_TX_PWR_CFG_2
	.comm	_MT_TX_PWR_CFG_3,4,2            ## @MT_TX_PWR_CFG_3
	.comm	_MT_TX_PWR_CFG_4,4,2            ## @MT_TX_PWR_CFG_4
	.comm	_MT_TX_PWR_CFG_7,4,2            ## @MT_TX_PWR_CFG_7
	.comm	_MT_TX_PWR_CFG_8,4,2            ## @MT_TX_PWR_CFG_8
	.comm	_MT_TX_PWR_CFG_9,4,2            ## @MT_TX_PWR_CFG_9
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mt76x02_phy_set_txpower        ; -- Begin function mt76x02_phy_set_txpower
	.p2align	2
_mt76x02_phy_set_txpower:               ; @mt76x02_phy_set_txpower
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x3, x1
	mov	x19, x0
Lloh0:
	adrp	x21, _MT_TX_ALC_CFG_0@GOTPAGE
Lloh1:
	ldr	x21, [x21, _MT_TX_ALC_CFG_0@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh2:
	adrp	x8, _MT_TX_ALC_CFG_0_CH_INIT_0@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MT_TX_ALC_CFG_0_CH_INIT_0@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	bl	_mt76_rmw_field
	ldr	w1, [x21]
Lloh5:
	adrp	x8, _MT_TX_ALC_CFG_0_CH_INIT_1@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MT_TX_ALC_CFG_0_CH_INIT_1@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x20
	bl	_mt76_rmw_field
Lloh8:
	adrp	x8, _MT_TX_PWR_CFG_0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MT_TX_PWR_CFG_0@GOTPAGEOFF]
Lloh10:
	ldr	w20, [x8]
	ldp	x9, x8, [x19, #24]
	ldr	w0, [x8]
	ldr	w1, [x8, #8]
	ldr	w2, [x9]
	ldr	w3, [x9, #8]
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh11:
	adrp	x8, _MT_TX_PWR_CFG_1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MT_TX_PWR_CFG_1@GOTPAGEOFF]
Lloh13:
	ldr	w20, [x8]
	ldr	x8, [x19, #24]
	ldr	w0, [x8, #16]
	ldr	w1, [x8, #24]
	ldr	x8, [x19, #8]
	ldr	w2, [x8]
	ldr	w3, [x8, #8]
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh14:
	adrp	x8, _MT_TX_PWR_CFG_2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MT_TX_PWR_CFG_2@GOTPAGEOFF]
Lloh16:
	ldr	w20, [x8]
	ldr	x8, [x19, #8]
	ldr	w0, [x8, #16]
	ldr	w1, [x8, #24]
	ldr	w2, [x8, #32]
	ldr	w3, [x8, #40]
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh17:
	adrp	x8, _MT_TX_PWR_CFG_3@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MT_TX_PWR_CFG_3@GOTPAGEOFF]
Lloh19:
	ldr	w20, [x8]
	ldp	x9, x8, [x19]
	ldr	w0, [x8, #48]
	ldr	w1, [x8, #56]
	ldr	w2, [x9]
	ldr	w3, [x9, #8]
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh20:
	adrp	x8, _MT_TX_PWR_CFG_4@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MT_TX_PWR_CFG_4@GOTPAGEOFF]
Lloh22:
	ldr	w20, [x8]
	ldr	x8, [x19]
	ldr	w0, [x8, #16]
	ldr	w1, [x8, #24]
	mov	w2, #0
	mov	w3, #0
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh23:
	adrp	x8, _MT_TX_PWR_CFG_7@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MT_TX_PWR_CFG_7@GOTPAGEOFF]
Lloh25:
	ldr	w20, [x8]
	ldr	x8, [x19, #24]
	ldr	w0, [x8, #28]
	ldp	x9, x8, [x19, #8]
	ldr	w2, [x9, #28]
	ldp	w1, w3, [x8, #32]
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh26:
	adrp	x8, _MT_TX_PWR_CFG_8@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MT_TX_PWR_CFG_8@GOTPAGEOFF]
Lloh28:
	ldr	w20, [x8]
	ldp	x8, x9, [x19, #8]
	ldr	w0, [x8, #56]
	ldp	w2, w3, [x9, #32]
	mov	w1, #0
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh29:
	adrp	x8, _MT_TX_PWR_CFG_9@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MT_TX_PWR_CFG_9@GOTPAGEOFF]
Lloh31:
	ldr	w20, [x8]
	ldp	x9, x8, [x19]
	ldr	w0, [x8, #28]
	ldp	w2, w3, [x9, #32]
	mov	w1, #0
	bl	_mt76x02_tx_power_mask
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mt76_wr
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_MT_TX_ALC_CFG_0,4,2            ; @MT_TX_ALC_CFG_0
	.comm	_MT_TX_ALC_CFG_0_CH_INIT_0,4,2  ; @MT_TX_ALC_CFG_0_CH_INIT_0
	.comm	_MT_TX_ALC_CFG_0_CH_INIT_1,4,2  ; @MT_TX_ALC_CFG_0_CH_INIT_1
	.comm	_MT_TX_PWR_CFG_0,4,2            ; @MT_TX_PWR_CFG_0
	.comm	_MT_TX_PWR_CFG_1,4,2            ; @MT_TX_PWR_CFG_1
	.comm	_MT_TX_PWR_CFG_2,4,2            ; @MT_TX_PWR_CFG_2
	.comm	_MT_TX_PWR_CFG_3,4,2            ; @MT_TX_PWR_CFG_3
	.comm	_MT_TX_PWR_CFG_4,4,2            ; @MT_TX_PWR_CFG_4
	.comm	_MT_TX_PWR_CFG_7,4,2            ; @MT_TX_PWR_CFG_7
	.comm	_MT_TX_PWR_CFG_8,4,2            ; @MT_TX_PWR_CFG_8
	.comm	_MT_TX_PWR_CFG_9,4,2            ; @MT_TX_PWR_CFG_9
.subsections_via_symbols
