	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function artpec6_pcie_set_nfts
_artpec6_pcie_set_nfts:                 ## @artpec6_pcie_set_nfts
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	_ARTPEC7@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_1
## %bb.2:
	movq	8(%rdi), %r14
	movq	_ACK_F_ASPM_CTRL_OFF@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_ACK_N_FTS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$180, %edi
	callq	_ACK_N_FTS
	orl	%eax, %ebx
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_FAST_TRAINING_SEQ_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$180, %edi
	callq	_FAST_TRAINING_SEQ
	orl	%eax, %ebx
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dw_pcie_writel_dbi             ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ARTPEC7,8,3                    ## @ARTPEC7
	.comm	_ACK_F_ASPM_CTRL_OFF,4,2        ## @ACK_F_ASPM_CTRL_OFF
	.comm	_ACK_N_FTS_MASK,4,2             ## @ACK_N_FTS_MASK
	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,4,2 ## @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_FAST_TRAINING_SEQ_MASK,4,2     ## @FAST_TRAINING_SEQ_MASK
	.no_dead_strip	_artpec6_pcie_set_nfts
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function artpec6_pcie_set_nfts
_artpec6_pcie_set_nfts:                 ; @artpec6_pcie_set_nfts
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _ARTPEC7@GOTPAGE
Lloh1:
	ldr	x9, [x9, _ARTPEC7@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	ldr	x19, [x0, #8]
Lloh3:
	adrp	x20, _ACK_F_ASPM_CTRL_OFF@GOTPAGE
Lloh4:
	ldr	x20, [x20, _ACK_F_ASPM_CTRL_OFF@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh5:
	adrp	x8, _ACK_N_FTS_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ACK_N_FTS_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #180
	bl	_ACK_N_FTS
	orr	w2, w21, w0
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
Lloh8:
	adrp	x20, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGE
Lloh9:
	ldr	x20, [x20, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh10:
	adrp	x8, _FAST_TRAINING_SEQ_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _FAST_TRAINING_SEQ_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #180
	bl	_FAST_TRAINING_SEQ
	orr	w2, w21, w0
	ldr	w1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_dw_pcie_writel_dbi
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_ARTPEC7,8,3                    ; @ARTPEC7
	.comm	_ACK_F_ASPM_CTRL_OFF,4,2        ; @ACK_F_ASPM_CTRL_OFF
	.comm	_ACK_N_FTS_MASK,4,2             ; @ACK_N_FTS_MASK
	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,4,2 ; @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_FAST_TRAINING_SEQ_MASK,4,2     ; @FAST_TRAINING_SEQ_MASK
	.no_dead_strip	_artpec6_pcie_set_nfts
.subsections_via_symbols
