	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function artpec6_pcie_deassert_core_reset
_artpec6_pcie_deassert_core_reset:      ## @artpec6_pcie_deassert_core_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_PCIECFG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_artpec6_pcie_readl
	movl	(%rbx), %ecx
	cmpl	$128, %ecx
	je	LBB0_3
## %bb.1:
	cmpl	$129, %ecx
	jne	LBB0_4
## %bb.2:
	movq	_PCIECFG_CORE_RESET_REQ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
	jmp	LBB0_4
LBB0_3:
	movq	_PCIECFG_NOC_RESET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, %eax
LBB0_4:
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_artpec6_pcie_writel
	movl	$100, %edi
	movl	$200, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_usleep_range                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIECFG,4,2                    ## @PCIECFG
	.comm	_PCIECFG_CORE_RESET_REQ,4,2     ## @PCIECFG_CORE_RESET_REQ
	.comm	_PCIECFG_NOC_RESET,4,2          ## @PCIECFG_NOC_RESET
	.no_dead_strip	_artpec6_pcie_deassert_core_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function artpec6_pcie_deassert_core_reset
_artpec6_pcie_deassert_core_reset:      ; @artpec6_pcie_deassert_core_reset
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x20, _PCIECFG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCIECFG@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_artpec6_pcie_readl
	mov	x2, x0
	ldr	w8, [x19]
	cmp	w8, #128
	b.eq	LBB0_3
; %bb.1:
	cmp	w8, #129
	b.ne	LBB0_4
; %bb.2:
Lloh2:
	adrp	x8, _PCIECFG_CORE_RESET_REQ@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIECFG_CORE_RESET_REQ@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w2, w2, w8
	b	LBB0_4
LBB0_3:
Lloh5:
	adrp	x8, _PCIECFG_NOC_RESET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCIECFG_NOC_RESET@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	orr	w2, w8, w2
LBB0_4:
	ldr	w1, [x20]
	mov	x0, x19
	bl	_artpec6_pcie_writel
	mov	w0, #100
	mov	w1, #200
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_usleep_range
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIECFG,4,2                    ; @PCIECFG
	.comm	_PCIECFG_CORE_RESET_REQ,4,2     ; @PCIECFG_CORE_RESET_REQ
	.comm	_PCIECFG_NOC_RESET,4,2          ; @PCIECFG_NOC_RESET
	.no_dead_strip	_artpec6_pcie_deassert_core_reset
.subsections_via_symbols
