	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rtl8723bu_init_statistics
_rtl8723bu_init_statistics:             ## @rtl8723bu_init_statistics
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_REG_NHM_TIMER_8723B@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	$2, %rsi
	movl	$10000, %edx                    ## imm = 0x2710
	callq	_rtl8xxxu_write16
	movq	_REG_NHM_TH9_TH10_8723B@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	addq	$2, %rsi
	movq	%r12, %rdi
	movl	$65535, %edx                    ## imm = 0xFFFF
	callq	_rtl8xxxu_write16
	movq	_REG_NHM_TH3_TO_TH0_8723B@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r12, %rdi
	movl	$-174, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_NHM_TH7_TO_TH4_8723B@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r12, %rdi
	movl	$-1, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_IQK@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	orl	$255, %eax
	movq	(%rbx), %rsi
	movq	%r12, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	movq	(%r13), %rsi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movl	%eax, %r14d
	movl	$8, %edi
	callq	_BIT
	movl	%eax, %r15d
	movl	$9, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$10, %edi
	callq	_BIT
	orl	%r15d, %ebx
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movq	(%r13), %rsi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_OFDM0_FA_RSTC@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_BIT
	orl	%eax, %ebx
	movq	(%r14), %rsi
	movq	%r12, %rdi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rtl8xxxu_write32               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_NHM_TIMER_8723B,8,3        ## @REG_NHM_TIMER_8723B
	.comm	_REG_NHM_TH9_TH10_8723B,8,3     ## @REG_NHM_TH9_TH10_8723B
	.comm	_REG_NHM_TH3_TO_TH0_8723B,8,3   ## @REG_NHM_TH3_TO_TH0_8723B
	.comm	_REG_NHM_TH7_TO_TH4_8723B,8,3   ## @REG_NHM_TH7_TO_TH4_8723B
	.comm	_REG_FPGA0_IQK,8,3              ## @REG_FPGA0_IQK
	.comm	_REG_OFDM0_FA_RSTC,8,3          ## @REG_OFDM0_FA_RSTC
	.no_dead_strip	_rtl8723bu_init_statistics
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rtl8723bu_init_statistics
_rtl8723bu_init_statistics:             ; @rtl8723bu_init_statistics
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _REG_NHM_TIMER_8723B@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REG_NHM_TIMER_8723B@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	add	x1, x8, #2
	mov	w2, #10000
	bl	_rtl8xxxu_write16
Lloh3:
	adrp	x23, _REG_NHM_TH9_TH10_8723B@GOTPAGE
Lloh4:
	ldr	x23, [x23, _REG_NHM_TH9_TH10_8723B@GOTPAGEOFF]
	ldr	x8, [x23]
	add	x1, x8, #2
	mov	x0, x19
	mov	w2, #65535
	bl	_rtl8xxxu_write16
Lloh5:
	adrp	x8, _REG_NHM_TH3_TO_TH0_8723B@GOTPAGE
Lloh6:
	ldr	x8, [x8, _REG_NHM_TH3_TO_TH0_8723B@GOTPAGEOFF]
Lloh7:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #-174
	bl	_rtl8xxxu_write32
Lloh8:
	adrp	x8, _REG_NHM_TH7_TO_TH4_8723B@GOTPAGE
Lloh9:
	ldr	x8, [x8, _REG_NHM_TH7_TO_TH4_8723B@GOTPAGEOFF]
Lloh10:
	ldr	x1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_rtl8xxxu_write32
Lloh11:
	adrp	x20, _REG_FPGA0_IQK@GOTPAGE
Lloh12:
	ldr	x20, [x20, _REG_FPGA0_IQK@GOTPAGEOFF]
	ldr	x1, [x20]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	orr	w2, w0, #0xff
	ldr	x1, [x20]
	mov	x0, x19
	bl	_rtl8xxxu_write32
	ldr	x1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	mov	x20, x0
	mov	w0, #8
	bl	_BIT
	mov	x21, x0
	mov	w0, #9
	bl	_BIT
	mov	x22, x0
	mov	w0, #10
	bl	_BIT
	orr	w8, w21, w20
	orr	w8, w8, w22
	orr	w2, w8, w0
	ldr	x1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_write32
Lloh13:
	adrp	x21, _REG_OFDM0_FA_RSTC@GOTPAGE
Lloh14:
	ldr	x21, [x21, _REG_OFDM0_FA_RSTC@GOTPAGEOFF]
	ldr	x1, [x21]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	mov	x20, x0
	mov	w0, #7
	bl	_BIT
	orr	w2, w0, w20
	ldr	x1, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_rtl8xxxu_write32
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_NHM_TIMER_8723B,8,3        ; @REG_NHM_TIMER_8723B
	.comm	_REG_NHM_TH9_TH10_8723B,8,3     ; @REG_NHM_TH9_TH10_8723B
	.comm	_REG_NHM_TH3_TO_TH0_8723B,8,3   ; @REG_NHM_TH3_TO_TH0_8723B
	.comm	_REG_NHM_TH7_TO_TH4_8723B,8,3   ; @REG_NHM_TH7_TO_TH4_8723B
	.comm	_REG_FPGA0_IQK,8,3              ; @REG_FPGA0_IQK
	.comm	_REG_OFDM0_FA_RSTC,8,3          ; @REG_OFDM0_FA_RSTC
	.no_dead_strip	_rtl8723bu_init_statistics
.subsections_via_symbols
