	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rockchip_pcie_init_port        ## -- Begin function rockchip_pcie_init_port
	.p2align	4, 0x90
_rockchip_pcie_init_port:               ## @rockchip_pcie_init_port
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	56(%rdi), %r14
	movl	48(%rdi), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_3
## %bb.1:
	movl	%eax, %r12d
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_2
LBB0_3:
	movl	44(%r15), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %r12d
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_2
LBB0_5:
	movl	52(%r15), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_6
## %bb.8:
	movl	%eax, %r12d
	leaq	L_.str.2(%rip), %rsi
LBB0_2:
	movq	%r14, %rdi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	_dev_err
LBB0_54:
	movl	%r12d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movq	_MAX_LANE_NUM@GOTPCREL(%rip), %rbx
	cmpl	$0, (%rbx)
	jle	LBB0_7
## %bb.9:
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movl	(%rax,%r13,4), %edi
	callq	_phy_init
	testl	%eax, %eax
	jne	LBB0_11
## %bb.12:                              ##   in Loop: Header=BB0_10 Depth=1
	incq	%r13
	movslq	(%rbx), %rax
	cmpq	%rax, %r13
	jl	LBB0_10
	jmp	LBB0_13
LBB0_7:
	xorl	%r13d, %r13d
LBB0_13:
	movl	24(%r15), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_16
## %bb.14:
	movl	%eax, %r12d
	leaq	L_.str.4(%rip), %rsi
	jmp	LBB0_15
LBB0_11:
	movl	%eax, %r12d
	leaq	L_.str.3(%rip), %rsi
	movq	%r14, %rdi
	movl	%r13d, %edx
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	_dev_err
	testl	%r13d, %r13d
	jne	LBB0_52
	jmp	LBB0_54
LBB0_16:
	movl	20(%r15), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_18
## %bb.17:
	movl	%eax, %r12d
	leaq	L_.str.5(%rip), %rsi
	jmp	LBB0_15
LBB0_18:
	movl	28(%r15), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_20
## %bb.19:
	movl	%eax, %r12d
	leaq	L_.str.6(%rip), %rsi
	jmp	LBB0_15
LBB0_20:
	movl	16(%r15), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_22
## %bb.21:
	movl	%eax, %r12d
	leaq	L_.str.7(%rip), %rsi
	jmp	LBB0_15
LBB0_22:
	movl	$10, %edi
	callq	_udelay
	movl	52(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_24
## %bb.23:
	movl	%eax, %r12d
	leaq	L_.str.8(%rip), %rsi
	jmp	LBB0_15
LBB0_24:
	movl	48(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_26
## %bb.25:
	movl	%eax, %r12d
	leaq	L_.str.9(%rip), %rsi
	jmp	LBB0_15
LBB0_26:
	movl	44(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_28
## %bb.27:
	movl	%eax, %r12d
	leaq	L_.str.10(%rip), %rsi
LBB0_15:
	movq	%r14, %rdi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	_dev_err
	testl	%r13d, %r13d
	je	LBB0_54
LBB0_52:
	movslq	%r13d, %rbx
	decq	%rbx
	.p2align	4, 0x90
LBB0_53:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movl	(%rax,%rbx,4), %edi
	callq	_phy_exit
	decq	%rbx
	decl	%r13d
	jne	LBB0_53
	jmp	LBB0_54
LBB0_28:
	cmpl	$2, (%r15)
	jne	LBB0_29
## %bb.30:
	movq	_PCIE_CLIENT_GEN_SEL_2@GOTPCREL(%rip), %rax
	jmp	LBB0_31
LBB0_29:
	movq	_PCIE_CLIENT_GEN_SEL_1@GOTPCREL(%rip), %rax
LBB0_31:
	movl	(%rax), %esi
	movq	_PCIE_CLIENT_CONFIG@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_rockchip_pcie_write
	movq	_PCIE_CLIENT_LINK_TRAIN_ENABLE@GOTPCREL(%rip), %rax
	movq	_PCIE_CLIENT_ARI_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	orl	(%rax), %r13d
	movl	40(%r15), %edi
	callq	_PCIE_CLIENT_CONF_LANE_NUM
	orl	%eax, %r13d
	movq	_PCIE_CLIENT_CONF_DISABLE@GOTPCREL(%rip), %rax
	movq	_PCIE_CLIENT_CONF_ENABLE@GOTPCREL(%rip), %rcx
	movq	_PCIE_CLIENT_MODE_EP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_PCIE_CLIENT_MODE_RC@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	orl	(%rax), %edx
	orl	(%rcx), %esi
	cmpq	$0, 32(%r15)
	cmovel	%edx, %esi
	orl	%r13d, %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_rockchip_pcie_write
	cmpl	$0, (%rbx)
	jle	LBB0_32
## %bb.33:
	xorl	%r13d, %r13d
LBB0_34:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movl	(%rax,%r13,4), %edi
	callq	_phy_power_on
	testl	%eax, %eax
	jne	LBB0_35
## %bb.36:                              ##   in Loop: Header=BB0_34 Depth=1
	incq	%r13
	movslq	(%rbx), %rax
	cmpq	%rax, %r13
	jl	LBB0_34
	jmp	LBB0_37
LBB0_32:
	xorl	%r13d, %r13d
LBB0_37:
	movl	28(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_39
## %bb.38:
	movl	%eax, %r12d
	leaq	L_.str.12(%rip), %rsi
	jmp	LBB0_46
LBB0_35:
	movl	%eax, %r12d
	leaq	L_.str.11(%rip), %rsi
	movq	%r14, %rdi
	movl	%r13d, %edx
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_47
LBB0_39:
	movl	24(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_41
## %bb.40:
	movl	%eax, %r12d
	leaq	L_.str.13(%rip), %rsi
	jmp	LBB0_46
LBB0_41:
	movl	20(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_43
## %bb.42:
	movl	%eax, %r12d
	leaq	L_.str.14(%rip), %rsi
	jmp	LBB0_46
LBB0_43:
	movl	16(%r15), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_44
## %bb.45:
	movl	%eax, %r12d
	leaq	L_.str.15(%rip), %rsi
LBB0_46:
	movq	%r14, %rdi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	_dev_err
LBB0_47:
	testl	%r13d, %r13d
	je	LBB0_50
## %bb.48:
	movl	%r13d, %r14d
LBB0_49:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movl	-4(%rax,%r14,4), %edi
	callq	_phy_power_off
	decq	%r14
	jne	LBB0_49
LBB0_50:
	movl	(%rbx), %r13d
	testl	%r13d, %r13d
	jne	LBB0_52
	jmp	LBB0_54
LBB0_44:
	xorl	%r12d, %r12d
	jmp	LBB0_54
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"assert aclk_rst err %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"assert pclk_rst err %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"assert pm_rst err %d\n"

	.comm	_MAX_LANE_NUM,4,2               ## @MAX_LANE_NUM
L_.str.3:                               ## @.str.3
	.asciz	"init phy%d err %d\n"

L_.str.4:                               ## @.str.4
	.asciz	"assert core_rst err %d\n"

L_.str.5:                               ## @.str.5
	.asciz	"assert mgmt_rst err %d\n"

L_.str.6:                               ## @.str.6
	.asciz	"assert mgmt_sticky_rst err %d\n"

L_.str.7:                               ## @.str.7
	.asciz	"assert pipe_rst err %d\n"

L_.str.8:                               ## @.str.8
	.asciz	"deassert pm_rst err %d\n"

L_.str.9:                               ## @.str.9
	.asciz	"deassert aclk_rst err %d\n"

L_.str.10:                              ## @.str.10
	.asciz	"deassert pclk_rst err %d\n"

	.comm	_PCIE_CLIENT_GEN_SEL_2,4,2      ## @PCIE_CLIENT_GEN_SEL_2
	.comm	_PCIE_CLIENT_CONFIG,4,2         ## @PCIE_CLIENT_CONFIG
	.comm	_PCIE_CLIENT_GEN_SEL_1,4,2      ## @PCIE_CLIENT_GEN_SEL_1
	.comm	_PCIE_CLIENT_LINK_TRAIN_ENABLE,4,2 ## @PCIE_CLIENT_LINK_TRAIN_ENABLE
	.comm	_PCIE_CLIENT_ARI_ENABLE,4,2     ## @PCIE_CLIENT_ARI_ENABLE
	.comm	_PCIE_CLIENT_CONF_ENABLE,4,2    ## @PCIE_CLIENT_CONF_ENABLE
	.comm	_PCIE_CLIENT_MODE_RC,4,2        ## @PCIE_CLIENT_MODE_RC
	.comm	_PCIE_CLIENT_CONF_DISABLE,4,2   ## @PCIE_CLIENT_CONF_DISABLE
	.comm	_PCIE_CLIENT_MODE_EP,4,2        ## @PCIE_CLIENT_MODE_EP
L_.str.11:                              ## @.str.11
	.asciz	"power on phy%d err %d\n"

L_.str.12:                              ## @.str.12
	.asciz	"deassert mgmt_sticky_rst err %d\n"

L_.str.13:                              ## @.str.13
	.asciz	"deassert core_rst err %d\n"

L_.str.14:                              ## @.str.14
	.asciz	"deassert mgmt_rst err %d\n"

L_.str.15:                              ## @.str.15
	.asciz	"deassert pipe_rst err %d\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rockchip_pcie_init_port        ; -- Begin function rockchip_pcie_init_port
	.p2align	2
_rockchip_pcie_init_port:               ; @rockchip_pcie_init_port
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x20, [x0, #56]
	ldr	w0, [x0, #48]
	bl	_reset_control_assert
	cbz	w0, LBB0_2
; %bb.1:
	mov	x21, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_6
LBB0_2:
	ldr	w0, [x19, #44]
	bl	_reset_control_assert
	cbz	w0, LBB0_4
; %bb.3:
	mov	x21, x0
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_6
LBB0_4:
	ldr	w0, [x19, #52]
	bl	_reset_control_assert
	cbz	w0, LBB0_8
; %bb.5:
	mov	x21, x0
Lloh4:
	adrp	x1, l_.str.2@PAGE
Lloh5:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_6:
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
LBB0_7:
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_8:
Lloh6:
	adrp	x23, _MAX_LANE_NUM@GOTPAGE
Lloh7:
	ldr	x23, [x23, _MAX_LANE_NUM@GOTPAGEOFF]
	ldr	w8, [x23]
	cmp	w8, #1
	b.lt	LBB0_12
; %bb.9:
	mov	x22, #0
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x22, lsl #2]
	bl	_phy_init
	cbnz	w0, LBB0_15
; %bb.11:                               ;   in Loop: Header=BB0_10 Depth=1
	add	x22, x22, #1
	ldrsw	x8, [x23]
	cmp	x22, x8
	b.lt	LBB0_10
	b	LBB0_13
LBB0_12:
	mov	w22, #0
LBB0_13:
	ldr	w0, [x19, #24]
	bl	_reset_control_assert
	cbz	w0, LBB0_16
; %bb.14:
	mov	x21, x0
Lloh8:
	adrp	x1, l_.str.4@PAGE
Lloh9:
	add	x1, x1, l_.str.4@PAGEOFF
	b	LBB0_28
LBB0_15:
	mov	x21, x0
	str	x21, [sp]
Lloh10:
	adrp	x1, l_.str.3@PAGE
Lloh11:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x20
	mov	x2, x22
	bl	_dev_err
	cbnz	w22, LBB0_29
	b	LBB0_7
LBB0_16:
	ldr	w0, [x19, #20]
	bl	_reset_control_assert
	cbz	w0, LBB0_18
; %bb.17:
	mov	x21, x0
Lloh12:
	adrp	x1, l_.str.5@PAGE
Lloh13:
	add	x1, x1, l_.str.5@PAGEOFF
	b	LBB0_28
LBB0_18:
	ldr	w0, [x19, #28]
	bl	_reset_control_assert
	cbz	w0, LBB0_20
; %bb.19:
	mov	x21, x0
Lloh14:
	adrp	x1, l_.str.6@PAGE
Lloh15:
	add	x1, x1, l_.str.6@PAGEOFF
	b	LBB0_28
LBB0_20:
	ldr	w0, [x19, #16]
	bl	_reset_control_assert
	cbz	w0, LBB0_22
; %bb.21:
	mov	x21, x0
Lloh16:
	adrp	x1, l_.str.7@PAGE
Lloh17:
	add	x1, x1, l_.str.7@PAGEOFF
	b	LBB0_28
LBB0_22:
	mov	w0, #10
	bl	_udelay
	ldr	w0, [x19, #52]
	bl	_reset_control_deassert
	cbz	w0, LBB0_24
; %bb.23:
	mov	x21, x0
Lloh18:
	adrp	x1, l_.str.8@PAGE
Lloh19:
	add	x1, x1, l_.str.8@PAGEOFF
	b	LBB0_28
LBB0_24:
	ldr	w0, [x19, #48]
	bl	_reset_control_deassert
	cbz	w0, LBB0_26
; %bb.25:
	mov	x21, x0
Lloh20:
	adrp	x1, l_.str.9@PAGE
Lloh21:
	add	x1, x1, l_.str.9@PAGEOFF
	b	LBB0_28
LBB0_26:
	ldr	w0, [x19, #44]
	bl	_reset_control_deassert
	cbz	w0, LBB0_31
; %bb.27:
	mov	x21, x0
Lloh22:
	adrp	x1, l_.str.10@PAGE
Lloh23:
	add	x1, x1, l_.str.10@PAGEOFF
LBB0_28:
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
	cbz	w22, LBB0_7
LBB0_29:
	mov	x8, x22
	sbfiz	x8, x8, #2, #32
	sub	x20, x8, #4
LBB0_30:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x20]
	bl	_phy_exit
	sub	x20, x20, #4
	sub	w22, w22, #1
	cbnz	w22, LBB0_30
	b	LBB0_7
LBB0_31:
	ldr	w8, [x19]
Lloh24:
	adrp	x9, _PCIE_CLIENT_GEN_SEL_2@GOTPAGE
Lloh25:
	ldr	x9, [x9, _PCIE_CLIENT_GEN_SEL_2@GOTPAGEOFF]
Lloh26:
	adrp	x10, _PCIE_CLIENT_GEN_SEL_1@GOTPAGE
Lloh27:
	ldr	x10, [x10, _PCIE_CLIENT_GEN_SEL_1@GOTPAGEOFF]
	cmp	w8, #2
	csel	x8, x9, x10, eq
	ldr	w1, [x8]
Lloh28:
	adrp	x21, _PCIE_CLIENT_CONFIG@GOTPAGE
Lloh29:
	ldr	x21, [x21, _PCIE_CLIENT_CONFIG@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_rockchip_pcie_write
Lloh30:
	adrp	x8, _PCIE_CLIENT_LINK_TRAIN_ENABLE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PCIE_CLIENT_LINK_TRAIN_ENABLE@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	adrp	x9, _PCIE_CLIENT_ARI_ENABLE@GOTPAGE
Lloh34:
	ldr	x9, [x9, _PCIE_CLIENT_ARI_ENABLE@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w22, w9, w8
	ldr	w0, [x19, #40]
	bl	_PCIE_CLIENT_CONF_LANE_NUM
	orr	w8, w22, w0
	ldr	x9, [x19, #32]
Lloh36:
	adrp	x10, _PCIE_CLIENT_CONF_DISABLE@GOTPAGE
Lloh37:
	ldr	x10, [x10, _PCIE_CLIENT_CONF_DISABLE@GOTPAGEOFF]
Lloh38:
	ldr	w10, [x10]
Lloh39:
	adrp	x11, _PCIE_CLIENT_CONF_ENABLE@GOTPAGE
Lloh40:
	ldr	x11, [x11, _PCIE_CLIENT_CONF_ENABLE@GOTPAGEOFF]
Lloh41:
	ldr	w11, [x11]
Lloh42:
	adrp	x12, _PCIE_CLIENT_MODE_EP@GOTPAGE
Lloh43:
	ldr	x12, [x12, _PCIE_CLIENT_MODE_EP@GOTPAGEOFF]
Lloh44:
	ldr	w12, [x12]
Lloh45:
	adrp	x13, _PCIE_CLIENT_MODE_RC@GOTPAGE
Lloh46:
	ldr	x13, [x13, _PCIE_CLIENT_MODE_RC@GOTPAGEOFF]
Lloh47:
	ldr	w13, [x13]
	orr	w10, w12, w10
	orr	w11, w13, w11
	cmp	x9, #0
	csel	w9, w10, w11, eq
	orr	w1, w8, w9
	ldr	w2, [x21]
	mov	x0, x19
	bl	_rockchip_pcie_write
	ldr	w8, [x23]
	cmp	w8, #1
	b.lt	LBB0_35
; %bb.32:
	mov	x22, #0
LBB0_33:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x22, lsl #2]
	bl	_phy_power_on
	cbnz	w0, LBB0_38
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=1
	add	x22, x22, #1
	ldrsw	x8, [x23]
	cmp	x22, x8
	b.lt	LBB0_33
	b	LBB0_36
LBB0_35:
	mov	w22, #0
LBB0_36:
	ldr	w0, [x19, #28]
	bl	_reset_control_deassert
	cbz	w0, LBB0_39
; %bb.37:
	mov	x21, x0
Lloh48:
	adrp	x1, l_.str.12@PAGE
Lloh49:
	add	x1, x1, l_.str.12@PAGEOFF
	b	LBB0_45
LBB0_38:
	mov	x21, x0
	str	x21, [sp]
Lloh50:
	adrp	x1, l_.str.11@PAGE
Lloh51:
	add	x1, x1, l_.str.11@PAGEOFF
	mov	x0, x20
	mov	x2, x22
	bl	_dev_err
                                        ; kill: def $w21 killed $w21 killed $x21 def $x21
	b	LBB0_46
LBB0_39:
	ldr	w0, [x19, #24]
	bl	_reset_control_deassert
	cbz	w0, LBB0_41
; %bb.40:
	mov	x21, x0
Lloh52:
	adrp	x1, l_.str.13@PAGE
Lloh53:
	add	x1, x1, l_.str.13@PAGEOFF
	b	LBB0_45
LBB0_41:
	ldr	w0, [x19, #20]
	bl	_reset_control_deassert
	cbz	w0, LBB0_43
; %bb.42:
	mov	x21, x0
Lloh54:
	adrp	x1, l_.str.14@PAGE
Lloh55:
	add	x1, x1, l_.str.14@PAGEOFF
	b	LBB0_45
LBB0_43:
	ldr	w0, [x19, #16]
	bl	_reset_control_deassert
	mov	x21, x0
	cbz	w0, LBB0_7
; %bb.44:
Lloh56:
	adrp	x1, l_.str.15@PAGE
Lloh57:
	add	x1, x1, l_.str.15@PAGEOFF
LBB0_45:
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
LBB0_46:
	cbz	w22, LBB0_49
; %bb.47:
	mov	w8, w22
	lsl	x8, x8, #2
	sub	x20, x8, #4
LBB0_48:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x20]
	bl	_phy_power_off
	sub	x20, x20, #4
	cmn	x20, #4
	b.ne	LBB0_48
LBB0_49:
	ldr	w22, [x23]
	cbnz	w22, LBB0_29
	b	LBB0_7
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpAdd	Lloh48, Lloh49
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpAdd	Lloh52, Lloh53
	.loh AdrpAdd	Lloh54, Lloh55
	.loh AdrpAdd	Lloh56, Lloh57
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"assert aclk_rst err %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"assert pclk_rst err %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"assert pm_rst err %d\n"

	.comm	_MAX_LANE_NUM,4,2               ; @MAX_LANE_NUM
l_.str.3:                               ; @.str.3
	.asciz	"init phy%d err %d\n"

l_.str.4:                               ; @.str.4
	.asciz	"assert core_rst err %d\n"

l_.str.5:                               ; @.str.5
	.asciz	"assert mgmt_rst err %d\n"

l_.str.6:                               ; @.str.6
	.asciz	"assert mgmt_sticky_rst err %d\n"

l_.str.7:                               ; @.str.7
	.asciz	"assert pipe_rst err %d\n"

l_.str.8:                               ; @.str.8
	.asciz	"deassert pm_rst err %d\n"

l_.str.9:                               ; @.str.9
	.asciz	"deassert aclk_rst err %d\n"

l_.str.10:                              ; @.str.10
	.asciz	"deassert pclk_rst err %d\n"

	.comm	_PCIE_CLIENT_GEN_SEL_2,4,2      ; @PCIE_CLIENT_GEN_SEL_2
	.comm	_PCIE_CLIENT_CONFIG,4,2         ; @PCIE_CLIENT_CONFIG
	.comm	_PCIE_CLIENT_GEN_SEL_1,4,2      ; @PCIE_CLIENT_GEN_SEL_1
	.comm	_PCIE_CLIENT_LINK_TRAIN_ENABLE,4,2 ; @PCIE_CLIENT_LINK_TRAIN_ENABLE
	.comm	_PCIE_CLIENT_ARI_ENABLE,4,2     ; @PCIE_CLIENT_ARI_ENABLE
	.comm	_PCIE_CLIENT_CONF_ENABLE,4,2    ; @PCIE_CLIENT_CONF_ENABLE
	.comm	_PCIE_CLIENT_MODE_RC,4,2        ; @PCIE_CLIENT_MODE_RC
	.comm	_PCIE_CLIENT_CONF_DISABLE,4,2   ; @PCIE_CLIENT_CONF_DISABLE
	.comm	_PCIE_CLIENT_MODE_EP,4,2        ; @PCIE_CLIENT_MODE_EP
l_.str.11:                              ; @.str.11
	.asciz	"power on phy%d err %d\n"

l_.str.12:                              ; @.str.12
	.asciz	"deassert mgmt_sticky_rst err %d\n"

l_.str.13:                              ; @.str.13
	.asciz	"deassert core_rst err %d\n"

l_.str.14:                              ; @.str.14
	.asciz	"deassert mgmt_rst err %d\n"

l_.str.15:                              ; @.str.15
	.asciz	"deassert pipe_rst err %d\n"

.subsections_via_symbols
