	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rockchip_pcie_cfg_configuration_accesses ## -- Begin function rockchip_pcie_cfg_configuration_accesses
	.p2align	4, 0x90
_rockchip_pcie_cfg_configuration_accesses: ## @rockchip_pcie_cfg_configuration_accesses
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_PCIE_RC_BAR_CONF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_rockchip_pcie_write
	movq	_RC_REGION_0_ADDR_TRANS_L@GOTPCREL(%rip), %rax
	movq	_RC_REGION_0_PASS_BITS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	addl	(%rax), %esi
	movq	_PCIE_CORE_OB_REGION_ADDR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rockchip_pcie_write
	movq	_RC_REGION_0_ADDR_TRANS_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_CORE_OB_REGION_ADDR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_rockchip_pcie_write
	movq	_PCIE_CORE_OB_REGION_DESC0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_rockchip_pcie_read
	movq	_RC_REGION_0_TYPE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	orl	%r14d, %esi
	orl	$8388608, %esi                  ## imm = 0x800000
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_rockchip_pcie_write
	movq	_PCIE_CORE_OB_REGION_DESC1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rockchip_pcie_write            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_RC_BAR_CONF,4,2           ## @PCIE_RC_BAR_CONF
	.comm	_RC_REGION_0_ADDR_TRANS_L,4,2   ## @RC_REGION_0_ADDR_TRANS_L
	.comm	_RC_REGION_0_PASS_BITS,4,2      ## @RC_REGION_0_PASS_BITS
	.comm	_PCIE_CORE_OB_REGION_ADDR0,4,2  ## @PCIE_CORE_OB_REGION_ADDR0
	.comm	_RC_REGION_0_ADDR_TRANS_H,4,2   ## @RC_REGION_0_ADDR_TRANS_H
	.comm	_PCIE_CORE_OB_REGION_ADDR1,4,2  ## @PCIE_CORE_OB_REGION_ADDR1
	.comm	_PCIE_CORE_OB_REGION_DESC0,4,2  ## @PCIE_CORE_OB_REGION_DESC0
	.comm	_RC_REGION_0_TYPE_MASK,4,2      ## @RC_REGION_0_TYPE_MASK
	.comm	_PCIE_CORE_OB_REGION_DESC1,4,2  ## @PCIE_CORE_OB_REGION_DESC1
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rockchip_pcie_cfg_configuration_accesses ; -- Begin function rockchip_pcie_cfg_configuration_accesses
	.p2align	2
_rockchip_pcie_cfg_configuration_accesses: ; @rockchip_pcie_cfg_configuration_accesses
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x8, _PCIE_RC_BAR_CONF@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_RC_BAR_CONF@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_rockchip_pcie_write
Lloh3:
	adrp	x8, _RC_REGION_0_ADDR_TRANS_L@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RC_REGION_0_ADDR_TRANS_L@GOTPAGEOFF]
Lloh5:
	adrp	x9, _RC_REGION_0_PASS_BITS@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RC_REGION_0_PASS_BITS@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	ldr	w9, [x9]
	add	w1, w9, w8
Lloh9:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR0@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_rockchip_pcie_write
Lloh12:
	adrp	x8, _RC_REGION_0_ADDR_TRANS_H@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RC_REGION_0_ADDR_TRANS_H@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR1@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR1@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_rockchip_pcie_write
Lloh18:
	adrp	x21, _PCIE_CORE_OB_REGION_DESC0@GOTPAGE
Lloh19:
	ldr	x21, [x21, _PCIE_CORE_OB_REGION_DESC0@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rockchip_pcie_read
Lloh20:
	adrp	x8, _RC_REGION_0_TYPE_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RC_REGION_0_TYPE_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	bic	w8, w0, w8
	orr	w8, w8, w19
	orr	w1, w8, #0x800000
	ldr	w2, [x21]
	mov	x0, x20
	bl	_rockchip_pcie_write
Lloh23:
	adrp	x8, _PCIE_CORE_OB_REGION_DESC1@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_DESC1@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x20
	mov	w1, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_rockchip_pcie_write
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_RC_BAR_CONF,4,2           ; @PCIE_RC_BAR_CONF
	.comm	_RC_REGION_0_ADDR_TRANS_L,4,2   ; @RC_REGION_0_ADDR_TRANS_L
	.comm	_RC_REGION_0_PASS_BITS,4,2      ; @RC_REGION_0_PASS_BITS
	.comm	_PCIE_CORE_OB_REGION_ADDR0,4,2  ; @PCIE_CORE_OB_REGION_ADDR0
	.comm	_RC_REGION_0_ADDR_TRANS_H,4,2   ; @RC_REGION_0_ADDR_TRANS_H
	.comm	_PCIE_CORE_OB_REGION_ADDR1,4,2  ; @PCIE_CORE_OB_REGION_ADDR1
	.comm	_PCIE_CORE_OB_REGION_DESC0,4,2  ; @PCIE_CORE_OB_REGION_DESC0
	.comm	_RC_REGION_0_TYPE_MASK,4,2      ; @RC_REGION_0_TYPE_MASK
	.comm	_PCIE_CORE_OB_REGION_DESC1,4,2  ; @PCIE_CORE_OB_REGION_DESC1
.subsections_via_symbols
