	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ltq_vrx200_pcie_phy_common_setup
_ltq_vrx200_pcie_phy_common_setup:      ## @ltq_vrx200_pcie_phy_common_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	callq	_phy_get_drvdata
	movq	%rax, %rbx
	movl	(%rax), %edi
	movq	_PCIE_PHY_PLL_A_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$4622, %edx                     ## imm = 0x120E
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_PLL_A_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$14807, %edx                    ## imm = 0x39D7
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_PLL_A_CTRL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2304, %edx                     ## imm = 0x900
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_RX1_EI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$4, %edx
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_RX1_A_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$26627, %edx                    ## imm = 0x6803
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX1_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_PHY_TX1_CTRL1_FORCE_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX1_A_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1798, %edx                     ## imm = 0x706
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX1_CTRL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$8191, %edx                     ## imm = 0x1FFF
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX1_A_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2064, %edx                     ## imm = 0x810
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX2_A_CTRL2@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movl	$32512, %edx                    ## imm = 0x7F00
	movl	$18176, %ecx                    ## imm = 0x4700
	callq	_regmap_update_bits
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX1_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$11776, %edx                    ## imm = 0x2E00
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_TX2_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$12438, %edx                    ## imm = 0x3096
	callq	_regmap_write
	movl	(%rbx), %edi
	movl	(%r14), %esi
	movl	$18183, %edx                    ## imm = 0x4707
	callq	_regmap_write
	movl	(%rbx), %edi
	movq	_PCIE_PHY_RX1_CDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$565, %edx                      ## imm = 0x235
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_regmap_write                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_PHY_PLL_A_CTRL1,4,2       ## @PCIE_PHY_PLL_A_CTRL1
	.comm	_PCIE_PHY_PLL_A_CTRL2,4,2       ## @PCIE_PHY_PLL_A_CTRL2
	.comm	_PCIE_PHY_PLL_A_CTRL3,4,2       ## @PCIE_PHY_PLL_A_CTRL3
	.comm	_PCIE_PHY_RX1_EI,4,2            ## @PCIE_PHY_RX1_EI
	.comm	_PCIE_PHY_RX1_A_CTRL,4,2        ## @PCIE_PHY_RX1_A_CTRL
	.comm	_PCIE_PHY_TX1_CTRL1,4,2         ## @PCIE_PHY_TX1_CTRL1
	.comm	_PCIE_PHY_TX1_CTRL1_FORCE_EN,4,2 ## @PCIE_PHY_TX1_CTRL1_FORCE_EN
	.comm	_PCIE_PHY_TX1_A_CTRL2,4,2       ## @PCIE_PHY_TX1_A_CTRL2
	.comm	_PCIE_PHY_TX1_CTRL3,4,2         ## @PCIE_PHY_TX1_CTRL3
	.comm	_PCIE_PHY_TX1_A_CTRL1,4,2       ## @PCIE_PHY_TX1_A_CTRL1
	.comm	_PCIE_PHY_TX2_A_CTRL2,4,2       ## @PCIE_PHY_TX2_A_CTRL2
	.comm	_PCIE_PHY_TX1_CTRL2,4,2         ## @PCIE_PHY_TX1_CTRL2
	.comm	_PCIE_PHY_TX2_CTRL2,4,2         ## @PCIE_PHY_TX2_CTRL2
	.comm	_PCIE_PHY_RX1_CDR,4,2           ## @PCIE_PHY_RX1_CDR
	.no_dead_strip	_ltq_vrx200_pcie_phy_common_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ltq_vrx200_pcie_phy_common_setup
_ltq_vrx200_pcie_phy_common_setup:      ; @ltq_vrx200_pcie_phy_common_setup
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	bl	_phy_get_drvdata
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL1@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL1@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #4622
	bl	_regmap_write
	ldr	w0, [x19]
Lloh3:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL2@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL2@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	w2, #14807
	bl	_regmap_write
	ldr	w0, [x19]
Lloh6:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL3@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL3@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	w2, #2304
	bl	_regmap_write
	ldr	w0, [x19]
Lloh9:
	adrp	x8, _PCIE_PHY_RX1_EI@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCIE_PHY_RX1_EI@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	w2, #4
	bl	_regmap_write
	ldr	w0, [x19]
Lloh12:
	adrp	x8, _PCIE_PHY_RX1_A_CTRL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PCIE_PHY_RX1_A_CTRL@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	w2, #26627
	bl	_regmap_write
	ldr	w0, [x19]
Lloh15:
	adrp	x8, _PCIE_PHY_TX1_CTRL1@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCIE_PHY_TX1_CTRL1@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
Lloh18:
	adrp	x8, _PCIE_PHY_TX1_CTRL1_FORCE_EN@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PCIE_PHY_TX1_CTRL1_FORCE_EN@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh21:
	adrp	x8, _PCIE_PHY_TX1_A_CTRL2@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PCIE_PHY_TX1_A_CTRL2@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	w2, #1798
	bl	_regmap_write
	ldr	w0, [x19]
Lloh24:
	adrp	x8, _PCIE_PHY_TX1_CTRL3@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PCIE_PHY_TX1_CTRL3@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	w2, #8191
	bl	_regmap_write
	ldr	w0, [x19]
Lloh27:
	adrp	x8, _PCIE_PHY_TX1_A_CTRL1@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PCIE_PHY_TX1_A_CTRL1@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	w2, #2064
	bl	_regmap_write
	ldr	w0, [x19]
Lloh30:
	adrp	x20, _PCIE_PHY_TX2_A_CTRL2@GOTPAGE
Lloh31:
	ldr	x20, [x20, _PCIE_PHY_TX2_A_CTRL2@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	w2, #32512
	mov	w3, #18176
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh32:
	adrp	x8, _PCIE_PHY_TX1_CTRL2@GOTPAGE
Lloh33:
	ldr	x8, [x8, _PCIE_PHY_TX1_CTRL2@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	w2, #11776
	bl	_regmap_write
	ldr	w0, [x19]
Lloh35:
	adrp	x8, _PCIE_PHY_TX2_CTRL2@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PCIE_PHY_TX2_CTRL2@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	w2, #12438
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x20]
	mov	w2, #18183
	bl	_regmap_write
	ldr	w0, [x19]
Lloh38:
	adrp	x8, _PCIE_PHY_RX1_CDR@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PCIE_PHY_RX1_CDR@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	mov	w2, #565
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_regmap_write
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_PHY_PLL_A_CTRL1,4,2       ; @PCIE_PHY_PLL_A_CTRL1
	.comm	_PCIE_PHY_PLL_A_CTRL2,4,2       ; @PCIE_PHY_PLL_A_CTRL2
	.comm	_PCIE_PHY_PLL_A_CTRL3,4,2       ; @PCIE_PHY_PLL_A_CTRL3
	.comm	_PCIE_PHY_RX1_EI,4,2            ; @PCIE_PHY_RX1_EI
	.comm	_PCIE_PHY_RX1_A_CTRL,4,2        ; @PCIE_PHY_RX1_A_CTRL
	.comm	_PCIE_PHY_TX1_CTRL1,4,2         ; @PCIE_PHY_TX1_CTRL1
	.comm	_PCIE_PHY_TX1_CTRL1_FORCE_EN,4,2 ; @PCIE_PHY_TX1_CTRL1_FORCE_EN
	.comm	_PCIE_PHY_TX1_A_CTRL2,4,2       ; @PCIE_PHY_TX1_A_CTRL2
	.comm	_PCIE_PHY_TX1_CTRL3,4,2         ; @PCIE_PHY_TX1_CTRL3
	.comm	_PCIE_PHY_TX1_A_CTRL1,4,2       ; @PCIE_PHY_TX1_A_CTRL1
	.comm	_PCIE_PHY_TX2_A_CTRL2,4,2       ; @PCIE_PHY_TX2_A_CTRL2
	.comm	_PCIE_PHY_TX1_CTRL2,4,2         ; @PCIE_PHY_TX1_CTRL2
	.comm	_PCIE_PHY_TX2_CTRL2,4,2         ; @PCIE_PHY_TX2_CTRL2
	.comm	_PCIE_PHY_RX1_CDR,4,2           ; @PCIE_PHY_RX1_CDR
	.no_dead_strip	_ltq_vrx200_pcie_phy_common_setup
.subsections_via_symbols
