	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function e1000_oem_bits_config_ich8lan
_e1000_oem_bits_config_ich8lan:         ## @e1000_oem_bits_config_ich8lan
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	24(%rdi), %rax
	movq	_e1000_pchlan@GOTPCREL(%rip), %r13
	cmpq	(%r13), %rax
	jge	LBB0_2
## %bb.1:
	xorl	%ebx, %ebx
	jmp	LBB0_24
LBB0_2:
	movl	%esi, %r14d
	movq	%rdi, %r12
	callq	*16(%rdi)
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	LBB0_24
## %bb.3:
	movq	24(%r12), %rax
	cmpq	(%r13), %rax
	jne	LBB0_6
## %bb.4:
	movq	_EXTCNF_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_er32
	movq	_E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	jne	LBB0_5
LBB0_6:
	movq	_FEXTNVM@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_er32
	movq	_E1000_FEXTNVM_SW_CONFIG_ICH8M@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_5
## %bb.7:
	movq	_PHY_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_er32
	movl	%eax, %r15d
	movq	_HV_OEM_BITS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	callq	_e1e_rphy_locked
	movq	%rax, %rbx
	testq	%rax, %rax
	jne	LBB0_23
## %bb.8:
	movq	_HV_OEM_BITS@GOTPCREL(%rip), %rbx
	movq	_HV_OEM_BITS_GBE_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_HV_OEM_BITS_LPLU@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, %edx
	orl	%ecx, %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	_E1000_PHY_CTRL_GBE_DISABLE@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	testl	%r14d, %r14d
	je	LBB0_14
## %bb.9:
	testl	%r15d, %esi
	je	LBB0_11
## %bb.10:
	orl	%ecx, %edx
	movl	%edx, -44(%rbp)
LBB0_11:
	movq	_E1000_PHY_CTRL_D0A_LPLU@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_19
## %bb.12:
	orl	%eax, %edx
	movl	%edx, -44(%rbp)
	jmp	LBB0_19
LBB0_5:
	xorl	%ebx, %ebx
	jmp	LBB0_23
LBB0_14:
	movq	_E1000_PHY_CTRL_NOND0A_GBE_DISABLE@GOTPCREL(%rip), %rdi
	orl	(%rdi), %esi
	testl	%r15d, %esi
	je	LBB0_16
## %bb.15:
	orl	%ecx, %edx
	movl	%edx, -44(%rbp)
LBB0_16:
	movq	_E1000_PHY_CTRL_D0A_LPLU@GOTPCREL(%rip), %rcx
	movq	_E1000_PHY_CTRL_NOND0A_LPLU@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	orl	(%rcx), %esi
	testl	%r15d, %esi
	je	LBB0_18
## %bb.17:
	orl	%eax, %edx
	movl	%edx, -44(%rbp)
LBB0_18:
	movq	24(%r12), %rax
	cmpq	(%r13), %rax
	je	LBB0_22
LBB0_19:
	movq	%r12, %rdi
	callq	*8(%r12)
	testl	%eax, %eax
	je	LBB0_21
## %bb.20:
	movl	-44(%rbp), %edx
	jmp	LBB0_22
LBB0_21:
	movq	_HV_OEM_BITS_RESTART_AN@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
LBB0_22:
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_e1e_wphy_locked
	movq	%rax, %rbx
LBB0_23:
	movq	%r12, %rdi
	callq	*(%r12)
LBB0_24:
	movq	%rbx, %rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_e1000_pchlan,8,3               ## @e1000_pchlan
	.comm	_EXTCNF_CTRL,4,2                ## @EXTCNF_CTRL
	.comm	_E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE,4,2 ## @E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
	.comm	_FEXTNVM,4,2                    ## @FEXTNVM
	.comm	_E1000_FEXTNVM_SW_CONFIG_ICH8M,4,2 ## @E1000_FEXTNVM_SW_CONFIG_ICH8M
	.comm	_PHY_CTRL,4,2                   ## @PHY_CTRL
	.comm	_HV_OEM_BITS,4,2                ## @HV_OEM_BITS
	.comm	_HV_OEM_BITS_GBE_DIS,4,2        ## @HV_OEM_BITS_GBE_DIS
	.comm	_HV_OEM_BITS_LPLU,4,2           ## @HV_OEM_BITS_LPLU
	.comm	_E1000_PHY_CTRL_GBE_DISABLE,4,2 ## @E1000_PHY_CTRL_GBE_DISABLE
	.comm	_E1000_PHY_CTRL_D0A_LPLU,4,2    ## @E1000_PHY_CTRL_D0A_LPLU
	.comm	_E1000_PHY_CTRL_NOND0A_GBE_DISABLE,4,2 ## @E1000_PHY_CTRL_NOND0A_GBE_DISABLE
	.comm	_E1000_PHY_CTRL_NOND0A_LPLU,4,2 ## @E1000_PHY_CTRL_NOND0A_LPLU
	.comm	_HV_OEM_BITS_RESTART_AN,4,2     ## @HV_OEM_BITS_RESTART_AN
	.no_dead_strip	_e1000_oem_bits_config_ich8lan
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function e1000_oem_bits_config_ich8lan
_e1000_oem_bits_config_ich8lan:         ; @e1000_oem_bits_config_ich8lan
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	x8, [x0, #24]
Lloh0:
	adrp	x23, _e1000_pchlan@GOTPAGE
Lloh1:
	ldr	x23, [x23, _e1000_pchlan@GOTPAGEOFF]
	ldr	x9, [x23]
	cmp	x8, x9
	b.ge	LBB0_2
; %bb.1:
	mov	x22, #0
	b	LBB0_23
LBB0_2:
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0, #16]
	blr	x8
	mov	x22, x0
	cbnz	x0, LBB0_23
; %bb.3:
	ldr	x8, [x19, #24]
	ldr	x9, [x23]
	cmp	x8, x9
	b.ne	LBB0_5
; %bb.4:
Lloh2:
	adrp	x8, _EXTCNF_CTRL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EXTCNF_CTRL@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	bl	_er32
Lloh5:
	adrp	x8, _E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	tst	w8, w0
	b.ne	LBB0_12
LBB0_5:
Lloh8:
	adrp	x8, _FEXTNVM@GOTPAGE
Lloh9:
	ldr	x8, [x8, _FEXTNVM@GOTPAGEOFF]
Lloh10:
	ldr	w0, [x8]
	bl	_er32
Lloh11:
	adrp	x8, _E1000_FEXTNVM_SW_CONFIG_ICH8M@GOTPAGE
Lloh12:
	ldr	x8, [x8, _E1000_FEXTNVM_SW_CONFIG_ICH8M@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_12
; %bb.6:
Lloh14:
	adrp	x8, _PHY_CTRL@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PHY_CTRL@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_er32
	mov	x21, x0
Lloh17:
	adrp	x24, _HV_OEM_BITS@GOTPAGE
Lloh18:
	ldr	x24, [x24, _HV_OEM_BITS@GOTPAGEOFF]
	ldr	w1, [x24]
	add	x2, sp, #12
	mov	x0, x19
	bl	_e1e_rphy_locked
	mov	x22, x0
	cbnz	x0, LBB0_22
; %bb.7:
Lloh19:
	adrp	x8, _HV_OEM_BITS_GBE_DIS@GOTPAGE
Lloh20:
	ldr	x8, [x8, _HV_OEM_BITS_GBE_DIS@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x8]
Lloh22:
	adrp	x8, _HV_OEM_BITS_LPLU@GOTPAGE
Lloh23:
	ldr	x8, [x8, _HV_OEM_BITS_LPLU@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	orr	w10, w8, w9
	ldr	w11, [sp, #12]
	bic	w2, w11, w10
	str	w2, [sp, #12]
Lloh25:
	adrp	x10, _E1000_PHY_CTRL_GBE_DISABLE@GOTPAGE
Lloh26:
	ldr	x10, [x10, _E1000_PHY_CTRL_GBE_DISABLE@GOTPAGEOFF]
Lloh27:
	ldr	w10, [x10]
	cbz	w20, LBB0_13
; %bb.8:
	tst	w10, w21
	b.eq	LBB0_10
; %bb.9:
	orr	w2, w2, w9
	str	w2, [sp, #12]
LBB0_10:
Lloh28:
	adrp	x9, _E1000_PHY_CTRL_D0A_LPLU@GOTPAGE
Lloh29:
	ldr	x9, [x9, _E1000_PHY_CTRL_D0A_LPLU@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	tst	w9, w21
	b.eq	LBB0_18
; %bb.11:
	orr	w8, w2, w8
	str	w8, [sp, #12]
	b	LBB0_18
LBB0_12:
	mov	x22, #0
	b	LBB0_22
LBB0_13:
Lloh31:
	adrp	x11, _E1000_PHY_CTRL_NOND0A_GBE_DISABLE@GOTPAGE
Lloh32:
	ldr	x11, [x11, _E1000_PHY_CTRL_NOND0A_GBE_DISABLE@GOTPAGEOFF]
Lloh33:
	ldr	w11, [x11]
	orr	w10, w11, w10
	tst	w10, w21
	b.eq	LBB0_15
; %bb.14:
	orr	w2, w2, w9
	str	w2, [sp, #12]
LBB0_15:
Lloh34:
	adrp	x9, _E1000_PHY_CTRL_D0A_LPLU@GOTPAGE
Lloh35:
	ldr	x9, [x9, _E1000_PHY_CTRL_D0A_LPLU@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
Lloh37:
	adrp	x10, _E1000_PHY_CTRL_NOND0A_LPLU@GOTPAGE
Lloh38:
	ldr	x10, [x10, _E1000_PHY_CTRL_NOND0A_LPLU@GOTPAGEOFF]
Lloh39:
	ldr	w10, [x10]
	orr	w9, w10, w9
	tst	w9, w21
	b.eq	LBB0_17
; %bb.16:
	orr	w2, w2, w8
	str	w2, [sp, #12]
LBB0_17:
	ldr	x8, [x19, #24]
	ldr	x9, [x23]
	cmp	x8, x9
	b.eq	LBB0_21
LBB0_18:
	ldr	x8, [x19, #8]
	mov	x0, x19
	blr	x8
	cbz	w0, LBB0_20
; %bb.19:
	ldr	w2, [sp, #12]
	b	LBB0_21
LBB0_20:
Lloh40:
	adrp	x8, _HV_OEM_BITS_RESTART_AN@GOTPAGE
Lloh41:
	ldr	x8, [x8, _HV_OEM_BITS_RESTART_AN@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
LBB0_21:
	ldr	w1, [x24]
	mov	x0, x19
	bl	_e1e_wphy_locked
	mov	x22, x0
LBB0_22:
	ldr	x8, [x19]
	mov	x0, x19
	blr	x8
LBB0_23:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.cfi_endproc
                                        ; -- End function
	.comm	_e1000_pchlan,8,3               ; @e1000_pchlan
	.comm	_EXTCNF_CTRL,4,2                ; @EXTCNF_CTRL
	.comm	_E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE,4,2 ; @E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE
	.comm	_FEXTNVM,4,2                    ; @FEXTNVM
	.comm	_E1000_FEXTNVM_SW_CONFIG_ICH8M,4,2 ; @E1000_FEXTNVM_SW_CONFIG_ICH8M
	.comm	_PHY_CTRL,4,2                   ; @PHY_CTRL
	.comm	_HV_OEM_BITS,4,2                ; @HV_OEM_BITS
	.comm	_HV_OEM_BITS_GBE_DIS,4,2        ; @HV_OEM_BITS_GBE_DIS
	.comm	_HV_OEM_BITS_LPLU,4,2           ; @HV_OEM_BITS_LPLU
	.comm	_E1000_PHY_CTRL_GBE_DISABLE,4,2 ; @E1000_PHY_CTRL_GBE_DISABLE
	.comm	_E1000_PHY_CTRL_D0A_LPLU,4,2    ; @E1000_PHY_CTRL_D0A_LPLU
	.comm	_E1000_PHY_CTRL_NOND0A_GBE_DISABLE,4,2 ; @E1000_PHY_CTRL_NOND0A_GBE_DISABLE
	.comm	_E1000_PHY_CTRL_NOND0A_LPLU,4,2 ; @E1000_PHY_CTRL_NOND0A_LPLU
	.comm	_HV_OEM_BITS_RESTART_AN,4,2     ; @HV_OEM_BITS_RESTART_AN
	.no_dead_strip	_e1000_oem_bits_config_ich8lan
.subsections_via_symbols
