	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function qcom_pcie_init_1_0_0
_qcom_pcie_init_1_0_0:                  ## @qcom_pcie_init_1_0_0
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	(%rax), %r15
	movl	16(%rdi), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	jmp	LBB0_18
LBB0_2:
	movl	20(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_5
## %bb.3:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	jmp	LBB0_4
LBB0_5:
	movl	24(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_8
## %bb.6:
	movl	%eax, %ebx
	leaq	L_.str.2(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	jmp	LBB0_7
LBB0_8:
	movl	28(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_11
## %bb.9:
	movl	%eax, %ebx
	leaq	L_.str.3(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	jmp	LBB0_10
LBB0_11:
	movl	32(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_14
## %bb.12:
	movl	%eax, %ebx
	leaq	L_.str.4(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	jmp	LBB0_13
LBB0_14:
	movl	36(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_16
## %bb.15:
	movl	%eax, %ebx
	leaq	L_.str.5(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	movl	32(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_13:
	movl	28(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_10:
	movl	24(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_7:
	movl	20(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_4:
	movl	16(%r14), %edi
	callq	_reset_control_assert
LBB0_18:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	movq	_PCIE20_PARF_DBI_BASE_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r14), %rsi
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_writel
	movq	_CONFIG_PCI_MSI@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_IS_ENABLED
	testq	%rax, %rax
	je	LBB0_18
## %bb.17:
	movq	_PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_readl
	movl	%eax, %r15d
	movl	$31, %edi
	callq	_BIT
	orl	%eax, %r15d
	movq	(%r12), %rsi
	addq	(%r14), %rsi
	movl	%r15d, %edi
	callq	_writel
	jmp	LBB0_18
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"cannot deassert core reset\n"

L_.str.1:                               ## @.str.1
	.asciz	"cannot prepare/enable aux clock\n"

L_.str.2:                               ## @.str.2
	.asciz	"cannot prepare/enable iface clock\n"

L_.str.3:                               ## @.str.3
	.asciz	"cannot prepare/enable master_bus clock\n"

L_.str.4:                               ## @.str.4
	.asciz	"cannot prepare/enable slave_bus clock\n"

L_.str.5:                               ## @.str.5
	.asciz	"cannot enable vdda regulator\n"

	.comm	_PCIE20_PARF_DBI_BASE_ADDR,8,3  ## @PCIE20_PARF_DBI_BASE_ADDR
	.comm	_CONFIG_PCI_MSI,4,2             ## @CONFIG_PCI_MSI
	.comm	_PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,8,3 ## @PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT
	.no_dead_strip	_qcom_pcie_init_1_0_0
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function qcom_pcie_init_1_0_0
_qcom_pcie_init_1_0_0:                  ; @qcom_pcie_init_1_0_0
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x21, [x8]
	ldr	w0, [x0, #16]
	bl	_reset_control_deassert
	cbz	w0, LBB0_2
; %bb.1:
	mov	x20, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	b	LBB0_16
LBB0_2:
	ldr	w0, [x19, #20]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_4
; %bb.3:
	mov	x20, x0
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	b	LBB0_15
LBB0_4:
	ldr	w0, [x19, #24]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_6
; %bb.5:
	mov	x20, x0
Lloh4:
	adrp	x1, l_.str.2@PAGE
Lloh5:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	b	LBB0_14
LBB0_6:
	ldr	w0, [x19, #28]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_8
; %bb.7:
	mov	x20, x0
Lloh6:
	adrp	x1, l_.str.3@PAGE
Lloh7:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	b	LBB0_13
LBB0_8:
	ldr	w0, [x19, #32]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_10
; %bb.9:
	mov	x20, x0
Lloh8:
	adrp	x1, l_.str.4@PAGE
Lloh9:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	b	LBB0_12
LBB0_10:
	ldr	w0, [x19, #36]
	bl	_regulator_enable
	cbz	w0, LBB0_17
; %bb.11:
	mov	x20, x0
Lloh10:
	adrp	x1, l_.str.5@PAGE
Lloh11:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	ldr	w0, [x19, #32]
	bl	_clk_disable_unprepare
LBB0_12:
	ldr	w0, [x19, #28]
	bl	_clk_disable_unprepare
LBB0_13:
	ldr	w0, [x19, #24]
	bl	_clk_disable_unprepare
LBB0_14:
	ldr	w0, [x19, #20]
	bl	_clk_disable_unprepare
LBB0_15:
	ldr	w0, [x19, #16]
	bl	_reset_control_assert
LBB0_16:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_17:
	ldr	x8, [x19]
Lloh12:
	adrp	x9, _PCIE20_PARF_DBI_BASE_ADDR@GOTPAGE
Lloh13:
	ldr	x9, [x9, _PCIE20_PARF_DBI_BASE_ADDR@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh15:
	adrp	x8, _CONFIG_PCI_MSI@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CONFIG_PCI_MSI@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	bl	_IS_ENABLED
	cbz	x0, LBB0_19
; %bb.18:
	ldr	x8, [x19]
Lloh18:
	adrp	x21, _PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT@GOTPAGE
Lloh19:
	ldr	x21, [x21, _PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	mov	x20, x0
	mov	w0, #31
	bl	_BIT
	orr	w0, w0, w20
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
LBB0_19:
	mov	w20, #0
	b	LBB0_16
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"cannot deassert core reset\n"

l_.str.1:                               ; @.str.1
	.asciz	"cannot prepare/enable aux clock\n"

l_.str.2:                               ; @.str.2
	.asciz	"cannot prepare/enable iface clock\n"

l_.str.3:                               ; @.str.3
	.asciz	"cannot prepare/enable master_bus clock\n"

l_.str.4:                               ; @.str.4
	.asciz	"cannot prepare/enable slave_bus clock\n"

l_.str.5:                               ; @.str.5
	.asciz	"cannot enable vdda regulator\n"

	.comm	_PCIE20_PARF_DBI_BASE_ADDR,8,3  ; @PCIE20_PARF_DBI_BASE_ADDR
	.comm	_CONFIG_PCI_MSI,4,2             ; @CONFIG_PCI_MSI
	.comm	_PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,8,3 ; @PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT
	.no_dead_strip	_qcom_pcie_init_1_0_0
.subsections_via_symbols
