	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_double_vlan_add
_mvpp2_prs_double_vlan_add:             ## @mvpp2_prs_double_vlan_add
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movl	%esi, %ebx
	movq	%rdi, %r15
	leaq	-48(%rbp), %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%r12d, %edx
	callq	_mvpp2_prs_double_vlan_find
	testl	%eax, %eax
	js	LBB0_4
## %bb.1:
	leaq	-48(%rbp), %rsi
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_mvpp2_prs_init_from_hw
LBB0_2:
	leaq	-48(%rbp), %rbx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_mvpp2_prs_tcam_port_map_set
	movq	%r15, %rdi
	movq	%rbx, %rsi
	callq	_mvpp2_prs_hw_write
	xorl	%eax, %eax
LBB0_3:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movl	%ebx, -64(%rbp)                 ## 4-byte Spill
	movl	%r12d, -68(%rbp)                ## 4-byte Spill
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	testl	%eax, %eax
	js	LBB0_3
## %bb.5:
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	callq	_mvpp2_prs_double_vlan_ai_free_get
	testl	%eax, %eax
	js	LBB0_3
## %bb.6:
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	(%rbx), %ecx
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	%eax, %ecx
	movl	%r14d, -60(%rbp)                ## 4-byte Spill
	jle	LBB0_9
LBB0_7:
	movl	-52(%rbp), %eax                 ## 4-byte Reload
	cmpl	%ecx, %eax
	jge	LBB0_16
## %bb.8:
	leaq	-48(%rbp), %r13
	movq	%r13, %rdi
	xorl	%esi, %esi
	movl	%eax, %ebx
	movl	$4, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_VLAN@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%r13, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -48(%rbp)
	movq	(%r15), %rax
	movl	-56(%rbp), %r12d                ## 4-byte Reload
	movslq	%r12d, %rcx
	movl	$1, (%rax,%rcx,4)
	movzwl	-64(%rbp), %edx                 ## 2-byte Folded Reload
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movzwl	-68(%rbp), %edx                 ## 2-byte Folded Reload
	movq	%r13, %rdi
	movl	$4, %esi
	callq	_mvpp2_prs_match_etype
	movq	(%r14), %rsi
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_VLAN_TAG_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_RI_VLAN_DOUBLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_VLAN_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_DBL_VLAN_AI_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	%r12d, %esi
	movq	_MVPP2_PRS_SRAM_AI_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_ai_update
	movl	-48(%rbp), %esi
	movq	(%r14), %rdx
	movl	-60(%rbp), %r14d                ## 4-byte Reload
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	jmp	LBB0_2
LBB0_9:
	movslq	%ecx, %rbx
	movq	%rbx, %r14
	shlq	$4, %r14
	orq	$8, %r14
	movq	_MVPP2_PRS_LU_VLAN@GOTPCREL(%rip), %r13
	jmp	LBB0_11
	.p2align	4, 0x90
LBB0_10:                                ##   in Loop: Header=BB0_11 Depth=1
	leaq	1(%rbx), %rcx
	movslq	%eax, %rdx
	addq	$16, %r14
	cmpq	%rdx, %rbx
	movq	%rcx, %rbx
	jge	LBB0_7
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rcx
	cmpl	$0, (%rcx,%r14)
	je	LBB0_10
## %bb.12:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	-8(%rcx,%r14), %rcx
	cmpq	(%r13), %rcx
	jne	LBB0_10
## %bb.13:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	%r15, %rdi
	leaq	-48(%rbp), %r12
	movq	%r12, %rsi
	movl	%ebx, %edx
	callq	_mvpp2_prs_init_from_hw
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_ri_get
	movq	_MVPP2_PRS_RI_VLAN_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_MVPP2_PRS_RI_VLAN_SINGLE@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_18
## %bb.14:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	_MVPP2_PRS_RI_VLAN_TRIPLE@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_18
## %bb.15:                              ##   in Loop: Header=BB0_11 Depth=1
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_10
LBB0_16:
	movq	_ERANGE@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_3
LBB0_18:
	movq	%rbx, %rcx
	jmp	LBB0_7
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ## @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ## @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_VLAN,8,3          ## @MVPP2_PRS_LU_VLAN
	.comm	_MVPP2_PRS_RI_VLAN_MASK,4,2     ## @MVPP2_PRS_RI_VLAN_MASK
	.comm	_MVPP2_PRS_RI_VLAN_SINGLE,4,2   ## @MVPP2_PRS_RI_VLAN_SINGLE
	.comm	_MVPP2_PRS_RI_VLAN_TRIPLE,4,2   ## @MVPP2_PRS_RI_VLAN_TRIPLE
	.comm	_ERANGE,4,2                     ## @ERANGE
	.comm	_MVPP2_VLAN_TAG_LEN,4,2         ## @MVPP2_VLAN_TAG_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_RI_VLAN_DOUBLE,4,2   ## @MVPP2_PRS_RI_VLAN_DOUBLE
	.comm	_MVPP2_PRS_DBL_VLAN_AI_BIT,4,2  ## @MVPP2_PRS_DBL_VLAN_AI_BIT
	.comm	_MVPP2_PRS_SRAM_AI_MASK,4,2     ## @MVPP2_PRS_SRAM_AI_MASK
	.no_dead_strip	_mvpp2_prs_double_vlan_add
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_double_vlan_add
_mvpp2_prs_double_vlan_add:             ; @mvpp2_prs_double_vlan_add
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x3
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	mov	x0, x19
	mov	x1, x22
	mov	x2, x21
	bl	_mvpp2_prs_double_vlan_find
	tbnz	w0, #31, LBB0_4
; %bb.1:
	mov	x2, x0
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_init_from_hw
LBB0_2:
	add	x0, sp, #8
	mov	x1, x20
	bl	_mvpp2_prs_tcam_port_map_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	mov	w24, #0
LBB0_3:
	mov	x0, x24
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_4:
Lloh0:
	adrp	x25, _MVPP2_PE_FIRST_FREE_TID@GOTPAGE
Lloh1:
	ldr	x25, [x25, _MVPP2_PE_FIRST_FREE_TID@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh2:
	adrp	x28, _MVPP2_PE_LAST_FREE_TID@GOTPAGE
Lloh3:
	ldr	x28, [x28, _MVPP2_PE_LAST_FREE_TID@GOTPAGEOFF]
	ldr	w2, [x28]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x24, x0
	tbnz	w0, #31, LBB0_3
; %bb.5:
	mov	x0, x19
	bl	_mvpp2_prs_double_vlan_ai_free_get
	mov	x23, x0
	tbnz	w0, #31, LBB0_13
; %bb.6:
	ldr	w9, [x25]
	ldr	w8, [x28]
Lloh4:
	adrp	x26, _MVPP2_PRS_LU_VLAN@GOTPAGE
Lloh5:
	ldr	x26, [x26, _MVPP2_PRS_LU_VLAN@GOTPAGEOFF]
	cmp	w9, w8
	b.gt	LBB0_15
; %bb.7:
                                        ; kill: def $w9 killed $w9 killed $x9 def $x9
	sxtw	x25, w9
	lsl	x27, x25, #4
	b	LBB0_9
LBB0_8:                                 ;   in Loop: Header=BB0_9 Depth=1
	add	x9, x25, #1
	add	x27, x27, #16
	cmp	x25, w8, sxtw
	mov	x25, x9
	b.ge	LBB0_15
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x9, [x19, #8]
	add	x10, x9, x27
	ldr	w10, [x10, #8]
	cbz	w10, LBB0_8
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	ldr	x9, [x9, x27]
	ldr	x10, [x26]
	cmp	x9, x10
	b.ne	LBB0_8
; %bb.11:                               ;   in Loop: Header=BB0_9 Depth=1
	add	x1, sp, #8
	mov	x0, x19
	mov	x2, x25
	bl	_mvpp2_prs_init_from_hw
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_get
Lloh6:
	adrp	x8, _MVPP2_PRS_RI_VLAN_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MVPP2_PRS_RI_VLAN_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh9:
	adrp	x9, _MVPP2_PRS_RI_VLAN_SINGLE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MVPP2_PRS_RI_VLAN_SINGLE@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _MVPP2_PRS_RI_VLAN_TRIPLE@GOTPAGE
Lloh13:
	ldr	x10, [x10, _MVPP2_PRS_RI_VLAN_TRIPLE@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	cmp	w8, w9
	ccmp	w8, w10, #4, ne
	b.eq	LBB0_14
; %bb.12:                               ;   in Loop: Header=BB0_9 Depth=1
	ldr	w8, [x28]
	b	LBB0_8
LBB0_13:
	mov	x24, x23
	b	LBB0_3
LBB0_14:
	mov	x9, x25
LBB0_15:
	cmp	w24, w9
	b.ge	LBB0_17
; %bb.16:
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	x1, [x26]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
	str	w24, [sp, #8]
	ldr	x8, [x19]
	mov	w9, #1
	str	w9, [x8, w23, sxtw #2]
	add	x0, sp, #8
	mov	w1, #0
	mov	x2, x22
	bl	_mvpp2_prs_match_etype
	add	x0, sp, #8
	mov	w1, #4
	mov	x2, x21
	bl	_mvpp2_prs_match_etype
	ldr	x1, [x26]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh15:
	adrp	x8, _MVPP2_VLAN_TAG_LEN@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MVPP2_VLAN_TAG_LEN@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
Lloh18:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_shift_set
Lloh21:
	adrp	x8, _MVPP2_PRS_RI_VLAN_DOUBLE@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MVPP2_PRS_RI_VLAN_DOUBLE@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
Lloh24:
	adrp	x8, _MVPP2_PRS_RI_VLAN_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MVPP2_PRS_RI_VLAN_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
Lloh27:
	adrp	x8, _MVPP2_PRS_DBL_VLAN_AI_BIT@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MVPP2_PRS_DBL_VLAN_AI_BIT@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	orr	w1, w8, w23
Lloh30:
	adrp	x8, _MVPP2_PRS_SRAM_AI_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_AI_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ai_update
	ldr	w1, [sp, #8]
	ldr	x2, [x26]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	b	LBB0_2
LBB0_17:
Lloh33:
	adrp	x8, _ERANGE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _ERANGE@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	neg	w24, w8
	b	LBB0_3
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ; @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ; @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_VLAN,8,3          ; @MVPP2_PRS_LU_VLAN
	.comm	_MVPP2_PRS_RI_VLAN_MASK,4,2     ; @MVPP2_PRS_RI_VLAN_MASK
	.comm	_MVPP2_PRS_RI_VLAN_SINGLE,4,2   ; @MVPP2_PRS_RI_VLAN_SINGLE
	.comm	_MVPP2_PRS_RI_VLAN_TRIPLE,4,2   ; @MVPP2_PRS_RI_VLAN_TRIPLE
	.comm	_ERANGE,4,2                     ; @ERANGE
	.comm	_MVPP2_VLAN_TAG_LEN,4,2         ; @MVPP2_VLAN_TAG_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_RI_VLAN_DOUBLE,4,2   ; @MVPP2_PRS_RI_VLAN_DOUBLE
	.comm	_MVPP2_PRS_DBL_VLAN_AI_BIT,4,2  ; @MVPP2_PRS_DBL_VLAN_AI_BIT
	.comm	_MVPP2_PRS_SRAM_AI_MASK,4,2     ; @MVPP2_PRS_SRAM_AI_MASK
	.no_dead_strip	_mvpp2_prs_double_vlan_add
.subsections_via_symbols
