	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function il3945_irq_tasklet
_il3945_irq_tasklet:                    ## @il3945_irq_tasklet
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	leaq	40(%rdi), %r12
	movq	%r12, %rdi
	callq	_spin_lock_irqsave
	movq	_CSR_INT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	__il_rd
	movl	%eax, %r13d
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	__il_wr
	movq	_CSR_FH_INT_STATUS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	__il_rd
	movl	%eax, %r14d
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	__il_wr
	movq	%r12, %rdi
	callq	_spin_unlock_irqrestore
	movq	_CSR39_FH_INT_RX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_CSR_INT_BIT_FH_RX@GOTPCREL(%rip), %rax
	andl	%r14d, %ebx
	je	LBB0_2
## %bb.1:
	movl	(%rax), %ebx
LBB0_2:
	orl	%r13d, %ebx
	movq	_CSR39_FH_INT_TX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CSR_INT_BIT_FH_TX@GOTPCREL(%rip), %rcx
	andl	%r14d, %eax
	je	LBB0_4
## %bb.3:
	movl	(%rcx), %eax
LBB0_4:
	orl	%eax, %ebx
	movq	_CSR_INT_BIT_HW_ERR@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_5
## %bb.20:
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_IL_ERR
	movq	%r15, %rdi
	callq	_il_disable_interrupts
	incl	36(%r15)
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_il_irq_handle_error            ## TAILCALL
LBB0_5:
	movq	_CSR_INT_BIT_SCD@GOTPCREL(%rip), %rax
	movq	_CSR_INT_BIT_ALIVE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %ebx
	movq	_CSR_INT_BIT_SW_ERR@GOTPCREL(%rip), %r13
	testl	%ebx, (%r13)
	je	LBB0_6
## %bb.7:
	leaq	L_.str.1(%rip), %rdi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	_IL_ERR
	incl	24(%r15)
	movq	%r15, %rdi
	callq	_il_irq_handle_error
	movl	(%r13), %r13d
	jmp	LBB0_8
LBB0_6:
	xorl	%r13d, %r13d
LBB0_8:
	movq	_CSR_INT_BIT_WAKEUP@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_10
## %bb.9:
	leaq	L_.str.2(%rip), %rdi
	xorl	%eax, %eax
	callq	_D_ISR
	leaq	56(%r15), %rsi
	movq	%r15, %rdi
	callq	_il_rx_queue_update_write_ptr
	movq	%r12, %rdi
	callq	_spin_lock_irqsave
	movq	48(%r15), %rsi
	movq	%r15, %rdi
	callq	_il_txq_update_write_ptr
	movq	48(%r15), %rsi
	addq	$4, %rsi
	movq	%r15, %rdi
	callq	_il_txq_update_write_ptr
	movq	48(%r15), %rsi
	addq	$8, %rsi
	movq	%r15, %rdi
	callq	_il_txq_update_write_ptr
	movq	48(%r15), %rsi
	addq	$12, %rsi
	movq	%r15, %rdi
	callq	_il_txq_update_write_ptr
	movq	48(%r15), %rsi
	addq	$16, %rsi
	movq	%r15, %rdi
	callq	_il_txq_update_write_ptr
	movq	%r12, %rdi
	callq	_spin_unlock_irqrestore
	incl	20(%r15)
	movq	_CSR_INT_BIT_WAKEUP@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
LBB0_10:
	movq	_CSR_INT_BIT_SW_RX@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	movq	_CSR_INT_BIT_FH_RX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	testl	%ebx, %eax
	je	LBB0_12
## %bb.11:
	movq	%r15, %rdi
	callq	_il3945_rx_handle
	incl	16(%r15)
	movq	_CSR_INT_BIT_FH_RX@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	orl	(%r12), %r13d
LBB0_12:
	movq	_CSR_INT_BIT_FH_TX@GOTPCREL(%rip), %rcx
	testl	%ebx, (%rcx)
	je	LBB0_14
## %bb.13:
	leaq	L_.str.3(%rip), %rdi
	xorl	%eax, %eax
	movq	%rcx, %r12
	callq	_D_ISR
	incl	12(%r15)
	movq	_CSR_FH_INT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$64, %edx
	callq	__il_wr
	movq	_FH39_SRVC_CHNL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_FH39_TCSR_CREDIT
	movq	%r15, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_il_wr
	orl	(%r12), %r13d
LBB0_14:
	notl	%r13d
	andl	%ebx, %r13d
	je	LBB0_16
## %bb.15:
	leaq	L_.str.4(%rip), %rdi
	movl	%r13d, %esi
	xorl	%eax, %eax
	callq	_IL_ERR
	incl	8(%r15)
LBB0_16:
	movl	(%r15), %eax
	notl	%eax
	andl	%eax, %ebx
	je	LBB0_18
## %bb.17:
	leaq	L_.str.5(%rip), %rdi
	movl	%ebx, %esi
	callq	_IL_WARN
	leaq	L_.str.6(%rip), %rdi
	movl	%r14d, %esi
	callq	_IL_WARN
LBB0_18:
	movq	_S_INT_ENABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	4(%r15), %rsi
	callq	_test_bit
	testq	%rax, %rax
	je	LBB0_19
## %bb.21:
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_il_enable_interrupts           ## TAILCALL
LBB0_19:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CSR_INT,4,2                    ## @CSR_INT
	.comm	_CSR_FH_INT_STATUS,4,2          ## @CSR_FH_INT_STATUS
	.comm	_CSR39_FH_INT_RX_MASK,4,2       ## @CSR39_FH_INT_RX_MASK
	.comm	_CSR_INT_BIT_FH_RX,4,2          ## @CSR_INT_BIT_FH_RX
	.comm	_CSR39_FH_INT_TX_MASK,4,2       ## @CSR39_FH_INT_TX_MASK
	.comm	_CSR_INT_BIT_FH_TX,4,2          ## @CSR_INT_BIT_FH_TX
	.comm	_CSR_INT_BIT_HW_ERR,4,2         ## @CSR_INT_BIT_HW_ERR
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Hardware error detected.  Restarting.\n"

	.comm	_CSR_INT_BIT_SCD,4,2            ## @CSR_INT_BIT_SCD
	.comm	_CSR_INT_BIT_ALIVE,4,2          ## @CSR_INT_BIT_ALIVE
	.comm	_CSR_INT_BIT_SW_ERR,4,2         ## @CSR_INT_BIT_SW_ERR
L_.str.1:                               ## @.str.1
	.asciz	"Microcode SW error detected. Restarting 0x%X.\n"

	.comm	_CSR_INT_BIT_WAKEUP,4,2         ## @CSR_INT_BIT_WAKEUP
L_.str.2:                               ## @.str.2
	.asciz	"Wakeup interrupt\n"

	.comm	_CSR_INT_BIT_SW_RX,4,2          ## @CSR_INT_BIT_SW_RX
L_.str.3:                               ## @.str.3
	.asciz	"Tx interrupt\n"

	.comm	_FH39_SRVC_CHNL,4,2             ## @FH39_SRVC_CHNL
L_.str.4:                               ## @.str.4
	.asciz	"Unhandled INTA bits 0x%08x\n"

L_.str.5:                               ## @.str.5
	.asciz	"Disabled INTA bits 0x%08x were pending\n"

L_.str.6:                               ## @.str.6
	.asciz	"   with inta_fh = 0x%08x\n"

	.comm	_S_INT_ENABLED,4,2              ## @S_INT_ENABLED
	.comm	_CSR_INT_MASK,4,2               ## @CSR_INT_MASK
	.comm	_IL_DL_ISR,4,2                  ## @IL_DL_ISR
	.no_dead_strip	_il3945_irq_tasklet
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function il3945_irq_tasklet
_il3945_irq_tasklet:                    ; @il3945_irq_tasklet
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	add	x21, x0, #40
	mov	x0, x21
	bl	_spin_lock_irqsave
Lloh0:
	adrp	x20, _CSR_INT@GOTPAGE
Lloh1:
	ldr	x20, [x20, _CSR_INT@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	__il_rd
	mov	x22, x0
	ldr	w1, [x20]
	mov	x0, x19
	mov	x2, x22
	bl	__il_wr
Lloh2:
	adrp	x23, _CSR_FH_INT_STATUS@GOTPAGE
Lloh3:
	ldr	x23, [x23, _CSR_FH_INT_STATUS@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	__il_rd
	mov	x20, x0
	ldr	w1, [x23]
	mov	x0, x19
	mov	x2, x20
	bl	__il_wr
	mov	x0, x21
	bl	_spin_unlock_irqrestore
Lloh4:
	adrp	x8, _CSR39_FH_INT_RX_MASK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CSR39_FH_INT_RX_MASK@GOTPAGEOFF]
Lloh6:
	adrp	x26, _CSR_INT_BIT_FH_RX@GOTPAGE
Lloh7:
	ldr	x26, [x26, _CSR_INT_BIT_FH_RX@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	w9, [x26]
	tst	w8, w20
	csel	w8, wzr, w9, eq
Lloh9:
	adrp	x9, _CSR39_FH_INT_TX_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CSR39_FH_INT_TX_MASK@GOTPAGEOFF]
	orr	w8, w8, w22
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x24, _CSR_INT_BIT_FH_TX@GOTPAGE
Lloh13:
	ldr	x24, [x24, _CSR_INT_BIT_FH_TX@GOTPAGEOFF]
	ldr	w10, [x24]
	tst	w9, w20
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh14:
	adrp	x9, _CSR_INT_BIT_HW_ERR@GOTPAGE
Lloh15:
	ldr	x9, [x9, _CSR_INT_BIT_HW_ERR@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	tst	w8, w9
	b.eq	LBB0_2
; %bb.1:
Lloh17:
	adrp	x0, l_.str@PAGE
Lloh18:
	add	x0, x0, l_.str@PAGEOFF
	bl	_IL_ERR
	mov	x0, x19
	bl	_il_disable_interrupts
	ldr	w8, [x19, #36]
	add	w8, w8, #1
	str	w8, [x19, #36]
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_il_irq_handle_error
LBB0_2:
Lloh19:
	adrp	x9, _CSR_INT_BIT_SCD@GOTPAGE
Lloh20:
	ldr	x9, [x9, _CSR_INT_BIT_SCD@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
Lloh22:
	adrp	x10, _CSR_INT_BIT_ALIVE@GOTPAGE
Lloh23:
	ldr	x10, [x10, _CSR_INT_BIT_ALIVE@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	orr	w9, w10, w9
	bic	w22, w8, w9
Lloh25:
	adrp	x25, _CSR_INT_BIT_SW_ERR@GOTPAGE
Lloh26:
	ldr	x25, [x25, _CSR_INT_BIT_SW_ERR@GOTPAGEOFF]
	ldr	w8, [x25]
	tst	w22, w8
	b.eq	LBB0_4
; %bb.3:
	str	x22, [sp]
Lloh27:
	adrp	x0, l_.str.1@PAGE
Lloh28:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_IL_ERR
	ldr	w8, [x19, #24]
	add	w8, w8, #1
	str	w8, [x19, #24]
	mov	x0, x19
	bl	_il_irq_handle_error
	ldr	w25, [x25]
	b	LBB0_5
LBB0_4:
	mov	w25, #0
LBB0_5:
Lloh29:
	adrp	x27, _CSR_INT_BIT_WAKEUP@GOTPAGE
Lloh30:
	ldr	x27, [x27, _CSR_INT_BIT_WAKEUP@GOTPAGEOFF]
	ldr	w8, [x27]
	tst	w8, w22
	b.eq	LBB0_7
; %bb.6:
Lloh31:
	adrp	x0, l_.str.2@PAGE
Lloh32:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_D_ISR
	add	x1, x19, #56
	mov	x0, x19
	bl	_il_rx_queue_update_write_ptr
	mov	x0, x21
	bl	_spin_lock_irqsave
	ldr	x1, [x19, #48]
	mov	x0, x19
	bl	_il_txq_update_write_ptr
	ldr	x8, [x19, #48]
	add	x1, x8, #4
	mov	x0, x19
	bl	_il_txq_update_write_ptr
	ldr	x8, [x19, #48]
	add	x1, x8, #8
	mov	x0, x19
	bl	_il_txq_update_write_ptr
	ldr	x8, [x19, #48]
	add	x1, x8, #12
	mov	x0, x19
	bl	_il_txq_update_write_ptr
	ldr	x8, [x19, #48]
	add	x1, x8, #16
	mov	x0, x19
	bl	_il_txq_update_write_ptr
	mov	x0, x21
	bl	_spin_unlock_irqrestore
	ldr	w8, [x19, #20]
	add	w8, w8, #1
	str	w8, [x19, #20]
	ldr	w8, [x27]
	orr	w25, w8, w25
LBB0_7:
	ldr	w8, [x26]
Lloh33:
	adrp	x21, _CSR_INT_BIT_SW_RX@GOTPAGE
Lloh34:
	ldr	x21, [x21, _CSR_INT_BIT_SW_RX@GOTPAGEOFF]
	ldr	w9, [x21]
	orr	w8, w9, w8
	tst	w8, w22
	b.eq	LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_il3945_rx_handle
	ldr	w8, [x19, #16]
	add	w8, w8, #1
	str	w8, [x19, #16]
	ldr	w8, [x26]
	ldr	w9, [x21]
	orr	w8, w8, w25
	orr	w25, w8, w9
LBB0_9:
	ldr	w8, [x24]
	tst	w8, w22
	b.eq	LBB0_11
; %bb.10:
Lloh35:
	adrp	x0, l_.str.3@PAGE
Lloh36:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_D_ISR
	ldr	w8, [x19, #12]
	add	w8, w8, #1
	str	w8, [x19, #12]
	ldr	w1, [x23]
	mov	x0, x19
	mov	w2, #64
	bl	__il_wr
Lloh37:
	adrp	x8, _FH39_SRVC_CHNL@GOTPAGE
Lloh38:
	ldr	x8, [x8, _FH39_SRVC_CHNL@GOTPAGEOFF]
Lloh39:
	ldr	w0, [x8]
	bl	_FH39_TCSR_CREDIT
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_il_wr
	ldr	w8, [x24]
	orr	w25, w8, w25
LBB0_11:
	bics	w8, w22, w25
	b.eq	LBB0_13
; %bb.12:
	str	x8, [sp]
Lloh40:
	adrp	x0, l_.str.4@PAGE
Lloh41:
	add	x0, x0, l_.str.4@PAGEOFF
	bl	_IL_ERR
	ldr	w8, [x19, #8]
	add	w8, w8, #1
	str	w8, [x19, #8]
LBB0_13:
	ldr	w8, [x19]
	bics	w1, w22, w8
	b.eq	LBB0_15
; %bb.14:
Lloh42:
	adrp	x0, l_.str.5@PAGE
Lloh43:
	add	x0, x0, l_.str.5@PAGEOFF
	bl	_IL_WARN
Lloh44:
	adrp	x0, l_.str.6@PAGE
Lloh45:
	add	x0, x0, l_.str.6@PAGEOFF
	mov	x1, x20
	bl	_IL_WARN
LBB0_15:
Lloh46:
	adrp	x8, _S_INT_ENABLED@GOTPAGE
Lloh47:
	ldr	x8, [x8, _S_INT_ENABLED@GOTPAGEOFF]
Lloh48:
	ldr	w0, [x8]
	add	x1, x19, #4
	bl	_test_bit
	cbz	x0, LBB0_17
; %bb.16:
	mov	x0, x19
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_il_enable_interrupts
LBB0_17:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh8
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpAdd	Lloh44, Lloh45
	.loh AdrpAdd	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.cfi_endproc
                                        ; -- End function
	.comm	_CSR_INT,4,2                    ; @CSR_INT
	.comm	_CSR_FH_INT_STATUS,4,2          ; @CSR_FH_INT_STATUS
	.comm	_CSR39_FH_INT_RX_MASK,4,2       ; @CSR39_FH_INT_RX_MASK
	.comm	_CSR_INT_BIT_FH_RX,4,2          ; @CSR_INT_BIT_FH_RX
	.comm	_CSR39_FH_INT_TX_MASK,4,2       ; @CSR39_FH_INT_TX_MASK
	.comm	_CSR_INT_BIT_FH_TX,4,2          ; @CSR_INT_BIT_FH_TX
	.comm	_CSR_INT_BIT_HW_ERR,4,2         ; @CSR_INT_BIT_HW_ERR
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Hardware error detected.  Restarting.\n"

	.comm	_CSR_INT_BIT_SCD,4,2            ; @CSR_INT_BIT_SCD
	.comm	_CSR_INT_BIT_ALIVE,4,2          ; @CSR_INT_BIT_ALIVE
	.comm	_CSR_INT_BIT_SW_ERR,4,2         ; @CSR_INT_BIT_SW_ERR
l_.str.1:                               ; @.str.1
	.asciz	"Microcode SW error detected. Restarting 0x%X.\n"

	.comm	_CSR_INT_BIT_WAKEUP,4,2         ; @CSR_INT_BIT_WAKEUP
l_.str.2:                               ; @.str.2
	.asciz	"Wakeup interrupt\n"

	.comm	_CSR_INT_BIT_SW_RX,4,2          ; @CSR_INT_BIT_SW_RX
l_.str.3:                               ; @.str.3
	.asciz	"Tx interrupt\n"

	.comm	_FH39_SRVC_CHNL,4,2             ; @FH39_SRVC_CHNL
l_.str.4:                               ; @.str.4
	.asciz	"Unhandled INTA bits 0x%08x\n"

l_.str.5:                               ; @.str.5
	.asciz	"Disabled INTA bits 0x%08x were pending\n"

l_.str.6:                               ; @.str.6
	.asciz	"   with inta_fh = 0x%08x\n"

	.comm	_S_INT_ENABLED,4,2              ; @S_INT_ENABLED
	.comm	_CSR_INT_MASK,4,2               ; @CSR_INT_MASK
	.comm	_IL_DL_ISR,4,2                  ; @IL_DL_ISR
	.no_dead_strip	_il3945_irq_tasklet
.subsections_via_symbols
