	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dra7xx_pcie_configure_two_lane
_dra7xx_pcie_configure_two_lane:        ## @dra7xx_pcie_configure_two_lane
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r12
	movq	(%rdi), %rbx
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	callq	_syscon_regmap_lookup_by_phandle
	movq	%rax, %r15
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_3
## %bb.1:
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_2
LBB0_3:
	leaq	L_.str(%rip), %rsi
	leaq	-36(%rbp), %rcx
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_of_property_read_u32_index
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	leaq	L_.str.2(%rip), %rsi
LBB0_2:
	movq	%r12, %rdi
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_6:
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	_PCIE_B0_B1_TSYNCEN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	orl	%ecx, %r14d
	movq	_PCIE_B1C0_MODE_SEL@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movl	-36(%rbp), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_regmap_update_bits
	xorl	%eax, %eax
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"ti,syscon-lane-sel"

L_.str.1:                               ## @.str.1
	.asciz	"unable to get ti,syscon-lane-sel\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
L_.str.2:                               ## @.str.2
	.asciz	"couldn't get lane selection reg offset\n"

	.comm	_PCIE_B0_B1_TSYNCEN,4,2         ## @PCIE_B0_B1_TSYNCEN
	.comm	_PCIE_B1C0_MODE_SEL,4,2         ## @PCIE_B1C0_MODE_SEL
	.no_dead_strip	_dra7xx_pcie_configure_two_lane
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dra7xx_pcie_configure_two_lane
_dra7xx_pcie_configure_two_lane:        ; @dra7xx_pcie_configure_two_lane
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	ldr	x22, [x0]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x22
	bl	_syscon_regmap_lookup_by_phandle
	mov	x21, x0
	bl	_IS_ERR
	cbz	x0, LBB0_2
; %bb.1:
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_4
LBB0_2:
Lloh4:
	adrp	x1, l_.str@PAGE
Lloh5:
	add	x1, x1, l_.str@PAGEOFF
	add	x3, sp, #12
	mov	x0, x22
	mov	w2, #1
	bl	_of_property_read_u32_index
	cbz	x0, LBB0_6
; %bb.3:
Lloh6:
	adrp	x1, l_.str.2@PAGE
Lloh7:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_4:
	mov	x0, x19
	bl	_dev_err
Lloh8:
	adrp	x8, _EINVAL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_5:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_6:
Lloh11:
	adrp	x8, _PCIE_B0_B1_TSYNCEN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PCIE_B0_B1_TSYNCEN@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	orr	w2, w8, w20
Lloh14:
	adrp	x9, _PCIE_B1C0_MODE_SEL@GOTPAGE
Lloh15:
	ldr	x9, [x9, _PCIE_B1C0_MODE_SEL@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w3, w9, w8
	ldr	w1, [sp, #12]
	mov	x0, x21
	bl	_regmap_update_bits
	mov	w0, #0
	b	LBB0_5
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"ti,syscon-lane-sel"

l_.str.1:                               ; @.str.1
	.asciz	"unable to get ti,syscon-lane-sel\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
l_.str.2:                               ; @.str.2
	.asciz	"couldn't get lane selection reg offset\n"

	.comm	_PCIE_B0_B1_TSYNCEN,4,2         ; @PCIE_B0_B1_TSYNCEN
	.comm	_PCIE_B1C0_MODE_SEL,4,2         ; @PCIE_B1C0_MODE_SEL
	.no_dead_strip	_dra7xx_pcie_configure_two_lane
.subsections_via_symbols
