	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rockchip_pcie_prog_ib_atu
_rockchip_pcie_prog_ib_atu:             ## @rockchip_pcie_prog_ib_atu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %eax
                                        ## kill: def $edx killed $edx def $rdx
	movq	_MAX_AXI_IB_ROOTPORT_REGION_NUM@GOTPCREL(%rip), %rcx
	cmpl	%esi, (%rcx)
	jl	LBB0_1
## %bb.2:
	movq	%rdi, %rbx
	leal	1(%rdx), %ecx
	movq	_MIN_AXI_ADDR_BITS_PASSED@GOTPCREL(%rip), %rdi
	cmpl	(%rdi), %ecx
	jl	LBB0_1
## %bb.3:
	cmpl	$64, %edx
	jl	LBB0_4
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	movl	%r8d, %r14d
	movq	_IB_ROOT_PORT_REG_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_PCIE_CORE_IB_REGION_ADDR0_NUM_BITS@GOTPCREL(%rip), %rcx
	andl	(%rcx), %edx
	shll	$8, %eax
	movq	_PCIE_CORE_IB_REGION_ADDR0_LO_ADDR@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	orl	%edx, %eax
	movq	_PCIE_RP_IB_ADDR0@GOTPCREL(%rip), %rcx
	movslq	%esi, %r15
	movq	(%rcx), %rdx
	addq	%r15, %rdx
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_rockchip_pcie_write
	movq	_PCIE_RP_IB_ADDR1@GOTPCREL(%rip), %rax
	addq	(%rax), %r15
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rdx
	callq	_rockchip_pcie_write
	xorl	%eax, %eax
	jmp	LBB0_5
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX_AXI_IB_ROOTPORT_REGION_NUM,4,2 ## @MAX_AXI_IB_ROOTPORT_REGION_NUM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_MIN_AXI_ADDR_BITS_PASSED,4,2   ## @MIN_AXI_ADDR_BITS_PASSED
	.comm	_IB_ROOT_PORT_REG_SIZE_SHIFT,4,2 ## @IB_ROOT_PORT_REG_SIZE_SHIFT
	.comm	_PCIE_CORE_IB_REGION_ADDR0_NUM_BITS,4,2 ## @PCIE_CORE_IB_REGION_ADDR0_NUM_BITS
	.comm	_PCIE_CORE_IB_REGION_ADDR0_LO_ADDR,4,2 ## @PCIE_CORE_IB_REGION_ADDR0_LO_ADDR
	.comm	_PCIE_RP_IB_ADDR0,8,3           ## @PCIE_RP_IB_ADDR0
	.comm	_PCIE_RP_IB_ADDR1,8,3           ## @PCIE_RP_IB_ADDR1
	.no_dead_strip	_rockchip_pcie_prog_ib_atu
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rockchip_pcie_prog_ib_atu
_rockchip_pcie_prog_ib_atu:             ; @rockchip_pcie_prog_ib_atu
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
Lloh0:
	adrp	x8, _MAX_AXI_IB_ROOTPORT_REGION_NUM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MAX_AXI_IB_ROOTPORT_REGION_NUM@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w1
	b.lt	LBB0_3
; %bb.1:
	add	w8, w2, #1
Lloh3:
	adrp	x9, _MIN_AXI_ADDR_BITS_PASSED@GOTPAGE
Lloh4:
	ldr	x9, [x9, _MIN_AXI_ADDR_BITS_PASSED@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.lt	LBB0_3
; %bb.2:
	cmp	w2, #64
	b.lt	LBB0_5
LBB0_3:
Lloh6:
	adrp	x8, _EINVAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_5:
	mov	x19, x4
	mov	x20, x0
Lloh9:
	adrp	x8, _IB_ROOT_PORT_REG_SIZE_SHIFT@GOTPAGE
Lloh10:
	ldr	x8, [x8, _IB_ROOT_PORT_REG_SIZE_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	lsl	w8, w1, w8
Lloh12:
	adrp	x9, _PCIE_CORE_IB_REGION_ADDR0_NUM_BITS@GOTPAGE
Lloh13:
	ldr	x9, [x9, _PCIE_CORE_IB_REGION_ADDR0_NUM_BITS@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	and	w9, w9, w2
Lloh15:
	adrp	x10, _PCIE_CORE_IB_REGION_ADDR0_LO_ADDR@GOTPAGE
Lloh16:
	ldr	x10, [x10, _PCIE_CORE_IB_REGION_ADDR0_LO_ADDR@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	and	w10, w10, w3, lsl #8
	orr	w1, w10, w9
Lloh18:
	adrp	x9, _PCIE_RP_IB_ADDR0@GOTPAGE
Lloh19:
	ldr	x9, [x9, _PCIE_RP_IB_ADDR0@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	sxtw	x21, w8
	add	x2, x9, x21
	bl	_rockchip_pcie_write
Lloh21:
	adrp	x8, _PCIE_RP_IB_ADDR1@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PCIE_RP_IB_ADDR1@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
	add	x2, x8, x21
	mov	x0, x20
	mov	x1, x19
	bl	_rockchip_pcie_write
	mov	w0, #0
	b	LBB0_4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX_AXI_IB_ROOTPORT_REGION_NUM,4,2 ; @MAX_AXI_IB_ROOTPORT_REGION_NUM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_MIN_AXI_ADDR_BITS_PASSED,4,2   ; @MIN_AXI_ADDR_BITS_PASSED
	.comm	_IB_ROOT_PORT_REG_SIZE_SHIFT,4,2 ; @IB_ROOT_PORT_REG_SIZE_SHIFT
	.comm	_PCIE_CORE_IB_REGION_ADDR0_NUM_BITS,4,2 ; @PCIE_CORE_IB_REGION_ADDR0_NUM_BITS
	.comm	_PCIE_CORE_IB_REGION_ADDR0_LO_ADDR,4,2 ; @PCIE_CORE_IB_REGION_ADDR0_LO_ADDR
	.comm	_PCIE_RP_IB_ADDR0,8,3           ; @PCIE_RP_IB_ADDR0
	.comm	_PCIE_RP_IB_ADDR1,8,3           ; @PCIE_RP_IB_ADDR1
	.no_dead_strip	_rockchip_pcie_prog_ib_atu
.subsections_via_symbols
