	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos_pcie_establish_link
_exynos_pcie_establish_link:            ## @exynos_pcie_establish_link
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	16(%rdi), %r14
	movq	(%r14), %r15
	movq	%r14, %rdi
	callq	_dw_pcie_link_up
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
LBB0_4:
	xorl	%eax, %eax
	jmp	LBB0_5
LBB0_2:
	leaq	8(%r14), %r15
	movq	%rbx, %rdi
	callq	_exynos_pcie_assert_core_reset
	movl	(%rbx), %edi
	callq	_phy_reset
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movq	_PCIE_PWR_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$1, %esi
	callq	_exynos_pcie_writel
	movl	(%rbx), %edi
	callq	_phy_power_on
	movl	(%rbx), %edi
	callq	_phy_init
	movq	%rbx, %rdi
	callq	_exynos_pcie_deassert_core_reset
	movq	%r15, %rdi
	callq	_dw_pcie_setup_rc
	movq	%rbx, %rdi
	callq	_exynos_pcie_assert_reset
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movq	_PCIE_ELBI_LTSSM_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_APP_LTSSM_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_exynos_pcie_writel
	movq	%r14, %rdi
	callq	_dw_pcie_wait_for_link
	testl	%eax, %eax
	je	LBB0_4
## %bb.3:
	movl	(%rbx), %edi
	callq	_phy_power_off
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Link already up\n"

	.comm	_PCIE_PWR_RESET,4,2             ## @PCIE_PWR_RESET
	.comm	_PCIE_ELBI_LTSSM_ENABLE,4,2     ## @PCIE_ELBI_LTSSM_ENABLE
	.comm	_PCIE_APP_LTSSM_ENABLE,4,2      ## @PCIE_APP_LTSSM_ENABLE
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.no_dead_strip	_exynos_pcie_establish_link
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos_pcie_establish_link
_exynos_pcie_establish_link:            ; @exynos_pcie_establish_link
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x20, [x0, #16]
	ldr	x21, [x20]
	mov	x0, x20
	bl	_dw_pcie_link_up
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x21
	bl	_dev_err
	mov	w0, #0
	b	LBB0_4
LBB0_2:
	add	x21, x20, #8
	mov	x0, x19
	bl	_exynos_pcie_assert_core_reset
	ldr	w0, [x19]
	bl	_phy_reset
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
Lloh2:
	adrp	x8, _PCIE_PWR_RESET@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_PWR_RESET@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w1, #1
	bl	_exynos_pcie_writel
	ldr	w0, [x19]
	bl	_phy_power_on
	ldr	w0, [x19]
	bl	_phy_init
	mov	x0, x19
	bl	_exynos_pcie_deassert_core_reset
	mov	x0, x21
	bl	_dw_pcie_setup_rc
	mov	x0, x19
	bl	_exynos_pcie_assert_reset
	ldr	x8, [x19, #8]
	ldr	w0, [x8]
Lloh5:
	adrp	x8, _PCIE_ELBI_LTSSM_ENABLE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCIE_ELBI_LTSSM_ENABLE@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
Lloh8:
	adrp	x8, _PCIE_APP_LTSSM_ENABLE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PCIE_APP_LTSSM_ENABLE@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	bl	_exynos_pcie_writel
	mov	x0, x20
	bl	_dw_pcie_wait_for_link
	cbz	w0, LBB0_4
; %bb.3:
	ldr	w0, [x19]
	bl	_phy_power_off
Lloh11:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh12:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Link already up\n"

	.comm	_PCIE_PWR_RESET,4,2             ; @PCIE_PWR_RESET
	.comm	_PCIE_ELBI_LTSSM_ENABLE,4,2     ; @PCIE_ELBI_LTSSM_ENABLE
	.comm	_PCIE_APP_LTSSM_ENABLE,4,2      ; @PCIE_APP_LTSSM_ENABLE
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.no_dead_strip	_exynos_pcie_establish_link
.subsections_via_symbols
