	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function slic_ds26522_init_configure
_slic_ds26522_init_configure:           ## @slic_ds26522_init_configure
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_DS26522_GTCCR_ADDR@GOTPCREL(%rip), %rax
	movq	_DS26522_GTCCR_BPREFSEL_REFCLKIN@GOTPCREL(%rip), %rcx
	movq	_DS26522_GTCCR_BFREQSEL_2048KHZ@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	(%rax), %rsi
	movq	_DS26522_GTCCR_FREQSEL_2048KHZ@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_slic_write
	movq	_DS26522_GTCR2_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_DS26522_GTCR2_TSSYNCOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	_DS26522_GFCR_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_DS26522_GFCR_BPCLK_2048KHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	_DS26522_GTCR1_ADDR@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	movq	_DS26522_GTCR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	_DS26522_GLSRR_ADDR@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	_DS26522_GLSRR_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	_DS26522_GFSRR_ADDR@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	movq	_DS26522_GFSRR_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movl	$100, %edi
	movl	$120, %esi
	callq	_usleep_range
	movq	(%r12), %rsi
	movq	_DS26522_GLSRR_NORMAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	(%rbx), %rsi
	movq	_DS26522_GFSRR_NORMAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	_DS26522_RMMR_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_DS26522_RMMR_SFTRST@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movq	_DS26522_TMMR_ADDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_DS26522_TMMR_SFTRST@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_slic_write
	movl	$100, %edi
	movl	$120, %esi
	callq	_usleep_range
	movq	_DS26522_RF_ADDR_START@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	_DS26522_RF_ADDR_END@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rbx
	jg	LBB0_2
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_slic_write
	leaq	1(%rbx), %rax
	cmpq	(%r12), %rbx
	movq	%rax, %rbx
	jl	LBB0_1
LBB0_2:
	movq	_DS26522_TF_ADDR_START@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	_DS26522_TF_ADDR_END@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rbx
	jg	LBB0_4
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_slic_write
	leaq	1(%rbx), %rax
	cmpq	(%r12), %rbx
	movq	%rax, %rbx
	jl	LBB0_3
LBB0_4:
	movq	_DS26522_LIU_ADDR_START@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	_DS26522_LIU_ADDR_END@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rbx
	jg	LBB0_6
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_slic_write
	leaq	1(%rbx), %rax
	cmpq	(%r12), %rbx
	movq	%rax, %rbx
	jl	LBB0_5
LBB0_6:
	movq	_DS26522_BERT_ADDR_START@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	_DS26522_BERT_ADDR_END@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rbx
	jg	LBB0_8
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_slic_write
	leaq	1(%rbx), %rax
	cmpq	(%r12), %rbx
	movq	%rax, %rbx
	jl	LBB0_7
LBB0_8:
	movq	%r14, %rdi
	callq	_ds26522_e1_spec_config
	movq	(%r15), %rsi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_slic_write
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_DS26522_GTCCR_ADDR,8,3         ## @DS26522_GTCCR_ADDR
	.comm	_DS26522_GTCCR_BPREFSEL_REFCLKIN,4,2 ## @DS26522_GTCCR_BPREFSEL_REFCLKIN
	.comm	_DS26522_GTCCR_BFREQSEL_2048KHZ,4,2 ## @DS26522_GTCCR_BFREQSEL_2048KHZ
	.comm	_DS26522_GTCCR_FREQSEL_2048KHZ,4,2 ## @DS26522_GTCCR_FREQSEL_2048KHZ
	.comm	_DS26522_GTCR2_ADDR,8,3         ## @DS26522_GTCR2_ADDR
	.comm	_DS26522_GTCR2_TSSYNCOUT,4,2    ## @DS26522_GTCR2_TSSYNCOUT
	.comm	_DS26522_GFCR_ADDR,8,3          ## @DS26522_GFCR_ADDR
	.comm	_DS26522_GFCR_BPCLK_2048KHZ,4,2 ## @DS26522_GFCR_BPCLK_2048KHZ
	.comm	_DS26522_GTCR1_ADDR,8,3         ## @DS26522_GTCR1_ADDR
	.comm	_DS26522_GTCR1,4,2              ## @DS26522_GTCR1
	.comm	_DS26522_GLSRR_ADDR,8,3         ## @DS26522_GLSRR_ADDR
	.comm	_DS26522_GLSRR_RESET,4,2        ## @DS26522_GLSRR_RESET
	.comm	_DS26522_GFSRR_ADDR,8,3         ## @DS26522_GFSRR_ADDR
	.comm	_DS26522_GFSRR_RESET,4,2        ## @DS26522_GFSRR_RESET
	.comm	_DS26522_GLSRR_NORMAL,4,2       ## @DS26522_GLSRR_NORMAL
	.comm	_DS26522_GFSRR_NORMAL,4,2       ## @DS26522_GFSRR_NORMAL
	.comm	_DS26522_RMMR_ADDR,8,3          ## @DS26522_RMMR_ADDR
	.comm	_DS26522_RMMR_SFTRST,4,2        ## @DS26522_RMMR_SFTRST
	.comm	_DS26522_TMMR_ADDR,8,3          ## @DS26522_TMMR_ADDR
	.comm	_DS26522_TMMR_SFTRST,4,2        ## @DS26522_TMMR_SFTRST
	.comm	_DS26522_RF_ADDR_START,8,3      ## @DS26522_RF_ADDR_START
	.comm	_DS26522_RF_ADDR_END,8,3        ## @DS26522_RF_ADDR_END
	.comm	_DS26522_TF_ADDR_START,8,3      ## @DS26522_TF_ADDR_START
	.comm	_DS26522_TF_ADDR_END,8,3        ## @DS26522_TF_ADDR_END
	.comm	_DS26522_LIU_ADDR_START,8,3     ## @DS26522_LIU_ADDR_START
	.comm	_DS26522_LIU_ADDR_END,8,3       ## @DS26522_LIU_ADDR_END
	.comm	_DS26522_BERT_ADDR_START,8,3    ## @DS26522_BERT_ADDR_START
	.comm	_DS26522_BERT_ADDR_END,8,3      ## @DS26522_BERT_ADDR_END
	.no_dead_strip	_slic_ds26522_init_configure
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function slic_ds26522_init_configure
_slic_ds26522_init_configure:           ; @slic_ds26522_init_configure
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _DS26522_GTCCR_ADDR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _DS26522_GTCCR_ADDR@GOTPAGEOFF]
Lloh2:
	ldr	x1, [x8]
Lloh3:
	adrp	x8, _DS26522_GTCCR_BPREFSEL_REFCLKIN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DS26522_GTCCR_BPREFSEL_REFCLKIN@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _DS26522_GTCCR_BFREQSEL_2048KHZ@GOTPAGE
Lloh7:
	ldr	x9, [x9, _DS26522_GTCCR_BFREQSEL_2048KHZ@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh9:
	adrp	x9, _DS26522_GTCCR_FREQSEL_2048KHZ@GOTPAGE
Lloh10:
	ldr	x9, [x9, _DS26522_GTCCR_FREQSEL_2048KHZ@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w2, w8, w9
	bl	_slic_write
Lloh12:
	adrp	x8, _DS26522_GTCR2_ADDR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DS26522_GTCR2_ADDR@GOTPAGEOFF]
Lloh14:
	ldr	x1, [x8]
Lloh15:
	adrp	x8, _DS26522_GTCR2_TSSYNCOUT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DS26522_GTCR2_TSSYNCOUT@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
Lloh18:
	adrp	x8, _DS26522_GFCR_ADDR@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DS26522_GFCR_ADDR@GOTPAGEOFF]
Lloh20:
	ldr	x1, [x8]
Lloh21:
	adrp	x8, _DS26522_GFCR_BPCLK_2048KHZ@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DS26522_GFCR_BPCLK_2048KHZ@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
Lloh24:
	adrp	x21, _DS26522_GTCR1_ADDR@GOTPAGE
Lloh25:
	ldr	x21, [x21, _DS26522_GTCR1_ADDR@GOTPAGEOFF]
	ldr	x1, [x21]
Lloh26:
	adrp	x8, _DS26522_GTCR1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _DS26522_GTCR1@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
Lloh29:
	adrp	x20, _DS26522_GLSRR_ADDR@GOTPAGE
Lloh30:
	ldr	x20, [x20, _DS26522_GLSRR_ADDR@GOTPAGEOFF]
	ldr	x1, [x20]
Lloh31:
	adrp	x8, _DS26522_GLSRR_RESET@GOTPAGE
Lloh32:
	ldr	x8, [x8, _DS26522_GLSRR_RESET@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
Lloh34:
	adrp	x22, _DS26522_GFSRR_ADDR@GOTPAGE
Lloh35:
	ldr	x22, [x22, _DS26522_GFSRR_ADDR@GOTPAGEOFF]
	ldr	x1, [x22]
Lloh36:
	adrp	x8, _DS26522_GFSRR_RESET@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DS26522_GFSRR_RESET@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
	mov	w0, #100
	mov	w1, #120
	bl	_usleep_range
	ldr	x1, [x20]
Lloh39:
	adrp	x8, _DS26522_GLSRR_NORMAL@GOTPAGE
Lloh40:
	ldr	x8, [x8, _DS26522_GLSRR_NORMAL@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
	ldr	x1, [x22]
Lloh42:
	adrp	x8, _DS26522_GFSRR_NORMAL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _DS26522_GFSRR_NORMAL@GOTPAGEOFF]
Lloh44:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
Lloh45:
	adrp	x8, _DS26522_RMMR_ADDR@GOTPAGE
Lloh46:
	ldr	x8, [x8, _DS26522_RMMR_ADDR@GOTPAGEOFF]
Lloh47:
	ldr	x1, [x8]
Lloh48:
	adrp	x8, _DS26522_RMMR_SFTRST@GOTPAGE
Lloh49:
	ldr	x8, [x8, _DS26522_RMMR_SFTRST@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
Lloh51:
	adrp	x8, _DS26522_TMMR_ADDR@GOTPAGE
Lloh52:
	ldr	x8, [x8, _DS26522_TMMR_ADDR@GOTPAGEOFF]
Lloh53:
	ldr	x1, [x8]
Lloh54:
	adrp	x8, _DS26522_TMMR_SFTRST@GOTPAGE
Lloh55:
	ldr	x8, [x8, _DS26522_TMMR_SFTRST@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_slic_write
	mov	w0, #100
	mov	w1, #120
	bl	_usleep_range
Lloh57:
	adrp	x8, _DS26522_RF_ADDR_START@GOTPAGE
Lloh58:
	ldr	x8, [x8, _DS26522_RF_ADDR_START@GOTPAGEOFF]
Lloh59:
	ldr	x20, [x8]
Lloh60:
	adrp	x22, _DS26522_RF_ADDR_END@GOTPAGE
Lloh61:
	ldr	x22, [x22, _DS26522_RF_ADDR_END@GOTPAGEOFF]
	ldr	x8, [x22]
	cmp	x20, x8
	b.gt	LBB0_2
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_slic_write
	add	x8, x20, #1
	ldr	x9, [x22]
	cmp	x20, x9
	mov	x20, x8
	b.lt	LBB0_1
LBB0_2:
Lloh62:
	adrp	x8, _DS26522_TF_ADDR_START@GOTPAGE
Lloh63:
	ldr	x8, [x8, _DS26522_TF_ADDR_START@GOTPAGEOFF]
Lloh64:
	ldr	x20, [x8]
Lloh65:
	adrp	x22, _DS26522_TF_ADDR_END@GOTPAGE
Lloh66:
	ldr	x22, [x22, _DS26522_TF_ADDR_END@GOTPAGEOFF]
	ldr	x8, [x22]
	cmp	x20, x8
	b.gt	LBB0_4
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_slic_write
	add	x8, x20, #1
	ldr	x9, [x22]
	cmp	x20, x9
	mov	x20, x8
	b.lt	LBB0_3
LBB0_4:
Lloh67:
	adrp	x8, _DS26522_LIU_ADDR_START@GOTPAGE
Lloh68:
	ldr	x8, [x8, _DS26522_LIU_ADDR_START@GOTPAGEOFF]
Lloh69:
	ldr	x20, [x8]
Lloh70:
	adrp	x22, _DS26522_LIU_ADDR_END@GOTPAGE
Lloh71:
	ldr	x22, [x22, _DS26522_LIU_ADDR_END@GOTPAGEOFF]
	ldr	x8, [x22]
	cmp	x20, x8
	b.gt	LBB0_6
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_slic_write
	add	x8, x20, #1
	ldr	x9, [x22]
	cmp	x20, x9
	mov	x20, x8
	b.lt	LBB0_5
LBB0_6:
Lloh72:
	adrp	x8, _DS26522_BERT_ADDR_START@GOTPAGE
Lloh73:
	ldr	x8, [x8, _DS26522_BERT_ADDR_START@GOTPAGEOFF]
Lloh74:
	ldr	x20, [x8]
Lloh75:
	adrp	x22, _DS26522_BERT_ADDR_END@GOTPAGE
Lloh76:
	ldr	x22, [x22, _DS26522_BERT_ADDR_END@GOTPAGEOFF]
	ldr	x8, [x22]
	cmp	x20, x8
	b.gt	LBB0_8
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_slic_write
	add	x8, x20, #1
	ldr	x9, [x22]
	cmp	x20, x9
	mov	x20, x8
	b.lt	LBB0_7
LBB0_8:
	mov	x0, x19
	bl	_ds26522_e1_spec_config
	ldr	x1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_slic_write
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.cfi_endproc
                                        ; -- End function
	.comm	_DS26522_GTCCR_ADDR,8,3         ; @DS26522_GTCCR_ADDR
	.comm	_DS26522_GTCCR_BPREFSEL_REFCLKIN,4,2 ; @DS26522_GTCCR_BPREFSEL_REFCLKIN
	.comm	_DS26522_GTCCR_BFREQSEL_2048KHZ,4,2 ; @DS26522_GTCCR_BFREQSEL_2048KHZ
	.comm	_DS26522_GTCCR_FREQSEL_2048KHZ,4,2 ; @DS26522_GTCCR_FREQSEL_2048KHZ
	.comm	_DS26522_GTCR2_ADDR,8,3         ; @DS26522_GTCR2_ADDR
	.comm	_DS26522_GTCR2_TSSYNCOUT,4,2    ; @DS26522_GTCR2_TSSYNCOUT
	.comm	_DS26522_GFCR_ADDR,8,3          ; @DS26522_GFCR_ADDR
	.comm	_DS26522_GFCR_BPCLK_2048KHZ,4,2 ; @DS26522_GFCR_BPCLK_2048KHZ
	.comm	_DS26522_GTCR1_ADDR,8,3         ; @DS26522_GTCR1_ADDR
	.comm	_DS26522_GTCR1,4,2              ; @DS26522_GTCR1
	.comm	_DS26522_GLSRR_ADDR,8,3         ; @DS26522_GLSRR_ADDR
	.comm	_DS26522_GLSRR_RESET,4,2        ; @DS26522_GLSRR_RESET
	.comm	_DS26522_GFSRR_ADDR,8,3         ; @DS26522_GFSRR_ADDR
	.comm	_DS26522_GFSRR_RESET,4,2        ; @DS26522_GFSRR_RESET
	.comm	_DS26522_GLSRR_NORMAL,4,2       ; @DS26522_GLSRR_NORMAL
	.comm	_DS26522_GFSRR_NORMAL,4,2       ; @DS26522_GFSRR_NORMAL
	.comm	_DS26522_RMMR_ADDR,8,3          ; @DS26522_RMMR_ADDR
	.comm	_DS26522_RMMR_SFTRST,4,2        ; @DS26522_RMMR_SFTRST
	.comm	_DS26522_TMMR_ADDR,8,3          ; @DS26522_TMMR_ADDR
	.comm	_DS26522_TMMR_SFTRST,4,2        ; @DS26522_TMMR_SFTRST
	.comm	_DS26522_RF_ADDR_START,8,3      ; @DS26522_RF_ADDR_START
	.comm	_DS26522_RF_ADDR_END,8,3        ; @DS26522_RF_ADDR_END
	.comm	_DS26522_TF_ADDR_START,8,3      ; @DS26522_TF_ADDR_START
	.comm	_DS26522_TF_ADDR_END,8,3        ; @DS26522_TF_ADDR_END
	.comm	_DS26522_LIU_ADDR_START,8,3     ; @DS26522_LIU_ADDR_START
	.comm	_DS26522_LIU_ADDR_END,8,3       ; @DS26522_LIU_ADDR_END
	.comm	_DS26522_BERT_ADDR_START,8,3    ; @DS26522_BERT_ADDR_START
	.comm	_DS26522_BERT_ADDR_END,8,3      ; @DS26522_BERT_ADDR_END
	.no_dead_strip	_slic_ds26522_init_configure
.subsections_via_symbols
