	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_ctxt_info_init        ## -- Begin function iwl_pcie_ctxt_info_init
	.p2align	4, 0x90
_iwl_pcie_ctxt_info_init:               ## @iwl_pcie_ctxt_info_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %r15
	callq	_IWL_TRANS_GET_PCIE_TRANS
	movq	%rax, %r13
	movl	(%r15), %edi
	leaq	16(%rax), %rbx
	movq	_GFP_KERNEL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	$80, %esi
	movq	%rbx, %rdx
	callq	_dma_alloc_coherent
	testq	%rax, %rax
	je	LBB0_1
## %bb.2:
	movq	%rax, %r14
	movq	$0, 72(%rax)
	movq	_CSR_HW_REV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	movl	%eax, %edi
	callq	_cpu_to_le16
	movq	%rax, 64(%r14)
	movl	$20, %edi
	callq	_cpu_to_le16
	movq	%rax, 56(%r14)
	movl	(%r13), %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, -56(%rbp)                 ## 8-byte Spill
	jae	LBB0_3
## %bb.4:
	cltq
	leaq	l_switch.table.iwl_pcie_ctxt_info_init(%rip), %rcx
	movq	(%rcx,%rax,8), %rax
	jmp	LBB0_5
LBB0_1:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_10
LBB0_3:
	movl	$1, %edi
	callq	_WARN_ON
	movq	_IWL_CTXT_INFO_RB_SIZE_4K@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %r12d
	movq	_MQ_RX_TABLE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RX_QUEUE_CB_SIZE
	xorl	%edi, %edi
	cmpl	$16, %eax
	setge	%dil
	callq	_BUILD_BUG_ON
	movq	_IWL_CTXT_INFO_TFD_FORMAT_LONG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_MQ_RX_TABLE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_RX_QUEUE_CB_SIZE
	movq	_IWL_CTXT_INFO_RB_CB_SIZE_POS@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	movq	_IWL_CTXT_INFO_RB_SIZE_POS@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r12d
	orl	%ebx, %r12d
	orl	%eax, %r12d
	movl	%r12d, %edi
	callq	_cpu_to_le32
	movl	%eax, 48(%r14)
	movq	40(%r13), %rax
	movl	8(%rax), %edi
	callq	_cpu_to_le64
	movq	%rax, 40(%r14)
	movq	40(%r13), %rax
	movl	4(%rax), %edi
	callq	_cpu_to_le64
	movq	%rax, 32(%r14)
	movq	40(%r13), %rax
	movl	(%rax), %edi
	callq	_cpu_to_le64
	movq	%rax, 24(%r14)
	movq	8(%r13), %rax
	movq	32(%r13), %rcx
	movq	(%rcx,%rax,8), %rax
	movl	(%rax), %edi
	callq	_cpu_to_le64
	movq	%rax, 16(%r14)
	movq	_IWL_CMD_QUEUE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_TFD_QUEUE_CB_SIZE
	movl	%eax, 8(%r14)
	movq	%r15, %rdi
	movq	-56(%rbp), %rsi                 ## 8-byte Reload
	movq	%r14, %rdx
	callq	_iwl_pcie_init_fw_sec
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %ebx
	movl	(%r15), %edi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %ecx
	movl	$80, %esi
	movq	%r14, %rdx
	callq	_dma_free_coherent
	jmp	LBB0_10
LBB0_7:
	movq	%r14, 24(%r13)
	movq	%r15, %rdi
	callq	_iwl_enable_fw_load_int_ctx_info
	movq	%r15, %rdi
	callq	_iwl_pcie_dbg_on
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	%r15, %rdi
	callq	_iwl_pcie_apply_destination
LBB0_9:
	movq	_CSR_CTXT_INFO_BA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_iwl_write64
	movq	_UREG_CPU_INIT_RUN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	_iwl_write_prph
	xorl	%ebx, %ebx
LBB0_10:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GFP_KERNEL,4,2                 ## @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_CSR_HW_REV,4,2                 ## @CSR_HW_REV
	.comm	_IWL_CTXT_INFO_RB_SIZE_2K,4,2   ## @IWL_CTXT_INFO_RB_SIZE_2K
	.comm	_IWL_CTXT_INFO_RB_SIZE_4K,4,2   ## @IWL_CTXT_INFO_RB_SIZE_4K
	.comm	_IWL_CTXT_INFO_RB_SIZE_8K,4,2   ## @IWL_CTXT_INFO_RB_SIZE_8K
	.comm	_IWL_CTXT_INFO_RB_SIZE_12K,4,2  ## @IWL_CTXT_INFO_RB_SIZE_12K
	.comm	_MQ_RX_TABLE_SIZE,4,2           ## @MQ_RX_TABLE_SIZE
	.comm	_IWL_CTXT_INFO_TFD_FORMAT_LONG,4,2 ## @IWL_CTXT_INFO_TFD_FORMAT_LONG
	.comm	_IWL_CTXT_INFO_RB_CB_SIZE_POS,4,2 ## @IWL_CTXT_INFO_RB_CB_SIZE_POS
	.comm	_IWL_CTXT_INFO_RB_SIZE_POS,4,2  ## @IWL_CTXT_INFO_RB_SIZE_POS
	.comm	_IWL_CMD_QUEUE_SIZE,4,2         ## @IWL_CMD_QUEUE_SIZE
	.comm	_CSR_CTXT_INFO_BA,4,2           ## @CSR_CTXT_INFO_BA
	.comm	_UREG_CPU_INIT_RUN,4,2          ## @UREG_CPU_INIT_RUN
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.iwl_pcie_ctxt_info_init
l_switch.table.iwl_pcie_ctxt_info_init:
	.quad	_IWL_CTXT_INFO_RB_SIZE_8K
	.quad	_IWL_CTXT_INFO_RB_SIZE_4K
	.quad	_IWL_CTXT_INFO_RB_SIZE_2K
	.quad	_IWL_CTXT_INFO_RB_SIZE_12K

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_ctxt_info_init        ; -- Begin function iwl_pcie_ctxt_info_init
	.p2align	2
_iwl_pcie_ctxt_info_init:               ; @iwl_pcie_ctxt_info_init
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x1
	mov	x19, x0
	bl	_IWL_TRANS_GET_PCIE_TRANS
	mov	x21, x0
	ldr	w0, [x19]
	add	x20, x21, #16
Lloh0:
	adrp	x8, _GFP_KERNEL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GFP_KERNEL@GOTPAGEOFF]
Lloh2:
	ldr	w3, [x8]
	mov	w1, #80
	mov	x2, x20
	bl	_dma_alloc_coherent
	cbz	x0, LBB0_3
; %bb.1:
	mov	x23, x0
	str	xzr, [x0, #72]
Lloh3:
	adrp	x8, _CSR_HW_REV@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CSR_HW_REV@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_iwl_read32
                                        ; kill: def $w0 killed $w0 killed $x0
	bl	_cpu_to_le16
	str	x0, [x23, #64]
	mov	w0, #20
	bl	_cpu_to_le16
	str	x0, [x23, #56]
	ldr	w8, [x21]
	sub	w8, w8, #128
	cmp	w8, #4
	b.hs	LBB0_4
; %bb.2:
Lloh6:
	adrp	x9, l_switch.table.iwl_pcie_ctxt_info_init@PAGE
Lloh7:
	add	x9, x9, l_switch.table.iwl_pcie_ctxt_info_init@PAGEOFF
	ldr	x8, [x9, w8, sxtw #3]
	b	LBB0_5
LBB0_3:
Lloh8:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh9:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	neg	w22, w8
	b	LBB0_10
LBB0_4:
	mov	w0, #1
	bl	_WARN_ON
Lloh11:
	adrp	x8, _IWL_CTXT_INFO_RB_SIZE_4K@GOTPAGE
Lloh12:
	ldr	x8, [x8, _IWL_CTXT_INFO_RB_SIZE_4K@GOTPAGEOFF]
LBB0_5:
	ldr	w24, [x8]
Lloh13:
	adrp	x25, _MQ_RX_TABLE_SIZE@GOTPAGE
Lloh14:
	ldr	x25, [x25, _MQ_RX_TABLE_SIZE@GOTPAGEOFF]
	ldr	w0, [x25]
	bl	_RX_QUEUE_CB_SIZE
	cmp	w0, #15
	cset	w0, gt
	bl	_BUILD_BUG_ON
Lloh15:
	adrp	x8, _IWL_CTXT_INFO_TFD_FORMAT_LONG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _IWL_CTXT_INFO_TFD_FORMAT_LONG@GOTPAGEOFF]
Lloh17:
	ldr	w26, [x8]
	ldr	w0, [x25]
	bl	_RX_QUEUE_CB_SIZE
Lloh18:
	adrp	x8, _IWL_CTXT_INFO_RB_CB_SIZE_POS@GOTPAGE
Lloh19:
	ldr	x8, [x8, _IWL_CTXT_INFO_RB_CB_SIZE_POS@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	lsl	w8, w0, w8
	orr	w8, w8, w26
Lloh21:
	adrp	x9, _IWL_CTXT_INFO_RB_SIZE_POS@GOTPAGE
Lloh22:
	ldr	x9, [x9, _IWL_CTXT_INFO_RB_SIZE_POS@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	lsl	w9, w24, w9
	orr	w0, w8, w9
	bl	_cpu_to_le32
	str	w0, [x23, #48]
	ldr	x8, [x21, #40]
	ldr	w0, [x8, #8]
	bl	_cpu_to_le64
	str	x0, [x23, #40]
	ldr	x8, [x21, #40]
	ldr	w0, [x8, #4]
	bl	_cpu_to_le64
	str	x0, [x23, #32]
	ldr	x8, [x21, #40]
	ldr	w0, [x8]
	bl	_cpu_to_le64
	str	x0, [x23, #24]
	ldr	x8, [x21, #32]
	ldr	x9, [x21, #8]
	ldr	x8, [x8, x9, lsl #3]
	ldr	w0, [x8]
	bl	_cpu_to_le64
	str	x0, [x23, #16]
Lloh24:
	adrp	x8, _IWL_CMD_QUEUE_SIZE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _IWL_CMD_QUEUE_SIZE@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	bl	_TFD_QUEUE_CB_SIZE
	str	w0, [x23, #8]
	mov	x0, x19
	mov	x1, x22
	mov	x2, x23
	bl	_iwl_pcie_init_fw_sec
	cbz	w0, LBB0_7
; %bb.6:
	mov	x22, x0
	ldr	w0, [x19]
	ldr	w3, [x20]
	mov	w1, #80
	mov	x2, x23
	bl	_dma_free_coherent
	b	LBB0_10
LBB0_7:
	str	x23, [x21, #24]
	mov	x0, x19
	bl	_iwl_enable_fw_load_int_ctx_info
	mov	x0, x19
	bl	_iwl_pcie_dbg_on
	cbz	x0, LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_iwl_pcie_apply_destination
LBB0_9:
Lloh27:
	adrp	x8, _CSR_CTXT_INFO_BA@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CSR_CTXT_INFO_BA@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_iwl_write64
Lloh30:
	adrp	x8, _UREG_CPU_INIT_RUN@GOTPAGE
Lloh31:
	ldr	x8, [x8, _UREG_CPU_INIT_RUN@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	bl	_iwl_write_prph
	mov	w22, #0
LBB0_10:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_GFP_KERNEL,4,2                 ; @GFP_KERNEL
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_CSR_HW_REV,4,2                 ; @CSR_HW_REV
	.comm	_IWL_CTXT_INFO_RB_SIZE_2K,4,2   ; @IWL_CTXT_INFO_RB_SIZE_2K
	.comm	_IWL_CTXT_INFO_RB_SIZE_4K,4,2   ; @IWL_CTXT_INFO_RB_SIZE_4K
	.comm	_IWL_CTXT_INFO_RB_SIZE_8K,4,2   ; @IWL_CTXT_INFO_RB_SIZE_8K
	.comm	_IWL_CTXT_INFO_RB_SIZE_12K,4,2  ; @IWL_CTXT_INFO_RB_SIZE_12K
	.comm	_MQ_RX_TABLE_SIZE,4,2           ; @MQ_RX_TABLE_SIZE
	.comm	_IWL_CTXT_INFO_TFD_FORMAT_LONG,4,2 ; @IWL_CTXT_INFO_TFD_FORMAT_LONG
	.comm	_IWL_CTXT_INFO_RB_CB_SIZE_POS,4,2 ; @IWL_CTXT_INFO_RB_CB_SIZE_POS
	.comm	_IWL_CTXT_INFO_RB_SIZE_POS,4,2  ; @IWL_CTXT_INFO_RB_SIZE_POS
	.comm	_IWL_CMD_QUEUE_SIZE,4,2         ; @IWL_CMD_QUEUE_SIZE
	.comm	_CSR_CTXT_INFO_BA,4,2           ; @CSR_CTXT_INFO_BA
	.comm	_UREG_CPU_INIT_RUN,4,2          ; @UREG_CPU_INIT_RUN
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.iwl_pcie_ctxt_info_init
l_switch.table.iwl_pcie_ctxt_info_init:
	.quad	_IWL_CTXT_INFO_RB_SIZE_8K
	.quad	_IWL_CTXT_INFO_RB_SIZE_4K
	.quad	_IWL_CTXT_INFO_RB_SIZE_2K
	.quad	_IWL_CTXT_INFO_RB_SIZE_12K

.subsections_via_symbols
