	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra210_hsic_phy_power_on
_tegra210_hsic_phy_power_on:            ## @tegra210_hsic_phy_power_on
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_phy_get_drvdata
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_to_hsic_lane
	movq	%rax, %r13
	movq	8(%rbx), %rdi
	callq	_to_hsic_pad
	movq	%rax, %r14
	movq	8(%rbx), %rax
	movq	(%rax), %r12
	movl	(%rbx), %r15d
	movq	%r12, %rdi
	callq	_to_tegra210_xusb_padctl
	movl	(%r14), %edi
	callq	_regulator_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_4
## %bb.1:
	movl	(%r13), %esi
	movq	_XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	%r15d, %edi
	callq	_XUSB_PADCTL_HSIC_PADX_CTL1
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	notl	%edx
	andl	%eax, %edx
	movl	4(%r13), %ebx
	shll	%cl, %ebx
	orl	%edx, %ebx
	movl	%r15d, %edi
	callq	_XUSB_PADCTL_HSIC_PADX_CTL1
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_padctl_writel
	movl	%r15d, %edi
	callq	_XUSB_PADCTL_HSIC_PADX_CTL2
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %bl
	movl	%ebx, %ecx
	shll	%cl, %esi
	movq	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %dl
	movl	%edx, %ecx
	shll	%cl, %edi
	orl	%esi, %edi
	movl	8(%r13), %esi
	movl	%ebx, %ecx
	shll	%cl, %esi
	movl	12(%r13), %ebx
	movl	%edx, %ecx
	shll	%cl, %ebx
	notl	%edi
	andl	%eax, %edi
	orl	%esi, %ebx
	orl	%edi, %ebx
	movl	%r15d, %edi
	callq	_XUSB_PADCTL_HSIC_PADX_CTL2
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_padctl_writel
	movl	%r15d, %edi
	callq	_XUSB_PADCTL_HSIC_PADX_CTL0
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0@GOTPCREL(%rip), %rdx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE@GOTPCREL(%rip), %rdx
	orl	(%rdx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0@GOTPCREL(%rip), %rax
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ebx
	orl	(%rax), %ebx
	orl	%ecx, %ebx
	movq	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r15d, %edi
	callq	_XUSB_PADCTL_HSIC_PADX_CTL0
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_padctl_writel
	movl	4(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_2
## %bb.3:
	movl	%eax, %ebx
	movl	(%r14), %edi
	callq	_regulator_disable
	jmp	LBB0_4
LBB0_2:
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %r8b
	movl	%r8d, %ecx
	shll	%cl, %esi
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %bl
	movl	%ebx, %ecx
	shll	%cl, %edi
	orl	%esi, %edi
	notl	%edi
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%r8d, %ecx
	shll	%cl, %edx
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%ebx, %ecx
	shll	%cl, %esi
	andl	%eax, %edi
	orl	%edx, %esi
	orl	%edi, %esi
	movl	(%r15), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	$1, %edi
	callq	_udelay
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	$50, %edi
	callq	_udelay
	movl	4(%r14), %edi
	callq	_clk_disable_unprepare
	xorl	%ebx, %ebx
LBB0_4:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL,4,2 ## @XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE,4,2 ## @XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK,4,2 ## @XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK
	.no_dead_strip	_tegra210_hsic_phy_power_on
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra210_hsic_phy_power_on
_tegra210_hsic_phy_power_on:            ; @tegra210_hsic_phy_power_on
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	bl	_phy_get_drvdata
	mov	x21, x0
	bl	_to_hsic_lane
	mov	x22, x0
	ldr	x0, [x21, #8]
	bl	_to_hsic_pad
	mov	x19, x0
	ldr	x8, [x21, #8]
	ldr	x20, [x8]
	ldr	w21, [x21]
	mov	x0, x20
	bl	_to_tegra210_xusb_padctl
	ldr	w0, [x19]
	bl	_regulator_enable
	mov	x23, x0
	cbnz	w0, LBB0_4
; %bb.1:
	ldr	w1, [x22]
Lloh0:
	adrp	x8, _XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_padctl_writel
	mov	x0, x21
	bl	_XUSB_PADCTL_HSIC_PADX_CTL1
	mov	x1, x0
	mov	x0, x20
	bl	_padctl_readl
Lloh3:
	adrp	x8, _XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
	ldr	w10, [x22, #4]
	lsl	w9, w10, w9
	orr	w23, w8, w9
	mov	x0, x21
	bl	_XUSB_PADCTL_HSIC_PADX_CTL1
	mov	x2, x0
	mov	x0, x20
	mov	x1, x23
	bl	_padctl_writel
	mov	x0, x21
	bl	_XUSB_PADCTL_HSIC_PADX_CTL2
	mov	x1, x0
	mov	x0, x20
	bl	_padctl_readl
Lloh9:
	adrp	x8, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK@GOTPAGEOFF]
Lloh11:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT@GOTPAGE
Lloh12:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
Lloh14:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh15:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
Lloh18:
	adrp	x11, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT@GOTPAGE
Lloh19:
	ldr	x11, [x11, _XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT@GOTPAGEOFF]
Lloh20:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w8, w10, w8
	bic	w8, w0, w8
	ldp	w10, w12, [x22, #8]
	lsl	w9, w10, w9
	lsl	w10, w12, w11
	orr	w9, w10, w9
	orr	w22, w9, w8
	mov	x0, x21
	bl	_XUSB_PADCTL_HSIC_PADX_CTL2
	mov	x2, x0
	mov	x0, x20
	mov	x1, x22
	bl	_padctl_writel
	mov	x0, x21
	bl	_XUSB_PADCTL_HSIC_PADX_CTL0
	mov	x1, x0
	mov	x0, x20
	bl	_padctl_readl
Lloh21:
	adrp	x8, _XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0@GOTPAGE
Lloh22:
	ldr	x8, [x8, _XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1@GOTPAGE
Lloh25:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE@GOTPAGE
Lloh28:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0@GOTPAGE
Lloh31:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh32:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh33:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1@GOTPAGE
Lloh34:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE@GOTPAGE
Lloh37:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
Lloh39:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0@GOTPAGE
Lloh40:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh41:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh42:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1@GOTPAGE
Lloh43:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh45:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE@GOTPAGE
Lloh46:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
Lloh48:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0@GOTPAGE
Lloh49:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh50:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh51:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1@GOTPAGE
Lloh52:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh54:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE@GOTPAGE
Lloh55:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	orr	w8, w8, w9
	bic	w8, w0, w8
Lloh57:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0@GOTPAGE
Lloh58:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
Lloh60:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1@GOTPAGE
Lloh61:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh63:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE@GOTPAGE
Lloh64:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE@GOTPAGEOFF]
Lloh65:
	ldr	w10, [x10]
	orr	w8, w9, w8
	orr	w22, w8, w10
	mov	x0, x21
	bl	_XUSB_PADCTL_HSIC_PADX_CTL0
	mov	x2, x0
	mov	x0, x20
	mov	x1, x22
	bl	_padctl_writel
	ldr	w0, [x19, #4]
	bl	_clk_prepare_enable
	mov	x23, x0
	cbz	w0, LBB0_3
; %bb.2:
	ldr	w0, [x19]
	bl	_regulator_disable
	b	LBB0_4
LBB0_3:
Lloh66:
	adrp	x21, _XUSB_PADCTL_HSIC_PAD_TRK_CTL@GOTPAGE
Lloh67:
	ldr	x21, [x21, _XUSB_PADCTL_HSIC_PAD_TRK_CTL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_padctl_readl
Lloh68:
	adrp	x8, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK@GOTPAGE
Lloh69:
	ldr	x8, [x8, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
Lloh71:
	adrp	x9, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT@GOTPAGE
Lloh72:
	ldr	x9, [x9, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh74:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK@GOTPAGE
Lloh75:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK@GOTPAGEOFF]
Lloh76:
	ldr	w10, [x10]
Lloh77:
	adrp	x11, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT@GOTPAGE
Lloh78:
	ldr	x11, [x11, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT@GOTPAGEOFF]
Lloh79:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w8, w10, w8
	bic	w8, w0, w8
Lloh80:
	adrp	x10, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL@GOTPAGE
Lloh81:
	ldr	x10, [x10, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL@GOTPAGEOFF]
Lloh82:
	ldr	w10, [x10]
Lloh83:
	adrp	x12, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL@GOTPAGE
Lloh84:
	ldr	x12, [x12, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL@GOTPAGEOFF]
	lsl	w9, w10, w9
Lloh85:
	ldr	w10, [x12]
	lsl	w10, w10, w11
	orr	w9, w10, w9
	orr	w1, w9, w8
	ldr	w2, [x21]
	mov	x0, x20
	bl	_padctl_writel
	mov	w0, #1
	bl	_udelay
	ldr	w1, [x21]
	mov	x0, x20
	bl	_padctl_readl
Lloh86:
	adrp	x8, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK@GOTPAGE
Lloh87:
	ldr	x8, [x8, _XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK@GOTPAGEOFF]
Lloh88:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x21]
	mov	x0, x20
	bl	_padctl_writel
	mov	w0, #50
	bl	_udelay
	ldr	w0, [x19, #4]
	bl	_clk_disable_unprepare
LBB0_4:
	mov	x0, x23
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh13
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh66, Lloh67
	.cfi_endproc
                                        ; -- End function
	.comm	_XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL,4,2 ; @XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1
	.comm	_XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE,4,2 ; @XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL
	.comm	_XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK,4,2 ; @XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK
	.no_dead_strip	_tegra210_hsic_phy_power_on
.subsections_via_symbols
