	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_ip4_init
_mvpp2_prs_ip4_init:                    ## @mvpp2_prs_ip4_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_IPPROTO_TCP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L4_TCP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MVPP2_PRS_RI_L4_PROTO_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	callq	_mvpp2_prs_ip4_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.1:
	movq	_IPPROTO_UDP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L4_UDP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r12), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_ip4_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.2:
	movq	_IPPROTO_IGMP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_MVPP2_PRS_RI_CPU_CODE_MASK@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_UDF3_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_ip4_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.3:
	movq	_MVPP2_PRS_L3_BROAD_CAST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_ip4_cast
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.4:
	movq	_MVPP2_PRS_L3_MULTI_CAST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_ip4_cast
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.5:
	leaq	-48(%rbp), %r15
	xorl	%ebx, %ebx
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PE_IP4_PROTO_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$12, %esi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_mvpp2_prs_sram_offset_set
	movq	_MVPP2_PRS_IPV4_DIP_AI_BIT@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r15, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_sram_ai_update
	movq	_MVPP2_PRS_RI_L4_OTHER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movl	(%r13), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movq	_MVPP2_PRS_PORT_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_mvpp2_prs_hw_write
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PE_IP4_ADDR_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_RI_L3_UCAST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_ADDR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_IPV4_DIP_AI_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	_mvpp2_prs_hw_write
LBB0_6:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IPPROTO_TCP,4,2                ## @IPPROTO_TCP
	.comm	_MVPP2_PRS_RI_L4_TCP,4,2        ## @MVPP2_PRS_RI_L4_TCP
	.comm	_MVPP2_PRS_RI_L4_PROTO_MASK,4,2 ## @MVPP2_PRS_RI_L4_PROTO_MASK
	.comm	_IPPROTO_UDP,4,2                ## @IPPROTO_UDP
	.comm	_MVPP2_PRS_RI_L4_UDP,4,2        ## @MVPP2_PRS_RI_L4_UDP
	.comm	_IPPROTO_IGMP,4,2               ## @IPPROTO_IGMP
	.comm	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC,4,2 ## @MVPP2_PRS_RI_CPU_CODE_RX_SPEC
	.comm	_MVPP2_PRS_RI_UDF3_RX_SPECIAL,4,2 ## @MVPP2_PRS_RI_UDF3_RX_SPECIAL
	.comm	_MVPP2_PRS_RI_CPU_CODE_MASK,4,2 ## @MVPP2_PRS_RI_CPU_CODE_MASK
	.comm	_MVPP2_PRS_RI_UDF3_MASK,4,2     ## @MVPP2_PRS_RI_UDF3_MASK
	.comm	_MVPP2_PRS_L3_BROAD_CAST,4,2    ## @MVPP2_PRS_L3_BROAD_CAST
	.comm	_MVPP2_PRS_L3_MULTI_CAST,4,2    ## @MVPP2_PRS_L3_MULTI_CAST
	.comm	_MVPP2_PRS_LU_IP4,4,2           ## @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PE_IP4_PROTO_UN,4,2      ## @MVPP2_PE_IP4_PROTO_UN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L4,4,2 ## @MVPP2_PRS_SRAM_UDF_TYPE_L4
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_PRS_IPV4_DIP_AI_BIT,4,2  ## @MVPP2_PRS_IPV4_DIP_AI_BIT
	.comm	_MVPP2_PRS_RI_L4_OTHER,4,2      ## @MVPP2_PRS_RI_L4_OTHER
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ## @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PE_IP4_ADDR_UN,4,2       ## @MVPP2_PE_IP4_ADDR_UN
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ## @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ## @MVPP2_PRS_SRAM_LU_GEN_BIT
	.comm	_MVPP2_PRS_RI_L3_UCAST,4,2      ## @MVPP2_PRS_RI_L3_UCAST
	.comm	_MVPP2_PRS_RI_L3_ADDR_MASK,4,2  ## @MVPP2_PRS_RI_L3_ADDR_MASK
	.no_dead_strip	_mvpp2_prs_ip4_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_ip4_init
_mvpp2_prs_ip4_init:                    ; @mvpp2_prs_ip4_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _IPPROTO_TCP@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IPPROTO_TCP@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _MVPP2_PRS_RI_L4_TCP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MVPP2_PRS_RI_L4_TCP@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
Lloh6:
	adrp	x20, _MVPP2_PRS_RI_L4_PROTO_MASK@GOTPAGE
Lloh7:
	ldr	x20, [x20, _MVPP2_PRS_RI_L4_PROTO_MASK@GOTPAGEOFF]
	ldr	w3, [x20]
	bl	_mvpp2_prs_ip4_proto
	cbnz	w0, LBB0_6
; %bb.1:
Lloh8:
	adrp	x8, _IPPROTO_UDP@GOTPAGE
Lloh9:
	ldr	x8, [x8, _IPPROTO_UDP@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
Lloh11:
	adrp	x8, _MVPP2_PRS_RI_L4_UDP@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MVPP2_PRS_RI_L4_UDP@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	ldr	w3, [x20]
	mov	x0, x19
	bl	_mvpp2_prs_ip4_proto
	cbnz	w0, LBB0_6
; %bb.2:
Lloh14:
	adrp	x8, _IPPROTO_IGMP@GOTPAGE
Lloh15:
	ldr	x8, [x8, _IPPROTO_IGMP@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
Lloh17:
	adrp	x8, _MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPAGE
Lloh21:
	ldr	x9, [x9, _MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
Lloh23:
	adrp	x10, _MVPP2_PRS_RI_CPU_CODE_MASK@GOTPAGE
Lloh24:
	ldr	x10, [x10, _MVPP2_PRS_RI_CPU_CODE_MASK@GOTPAGEOFF]
	orr	w2, w9, w8
Lloh25:
	ldr	w8, [x10]
Lloh26:
	adrp	x9, _MVPP2_PRS_RI_UDF3_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _MVPP2_PRS_RI_UDF3_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w3, w9, w8
	mov	x0, x19
	bl	_mvpp2_prs_ip4_proto
	cbnz	w0, LBB0_6
; %bb.3:
Lloh29:
	adrp	x8, _MVPP2_PRS_L3_BROAD_CAST@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MVPP2_PRS_L3_BROAD_CAST@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_ip4_cast
	cbnz	w0, LBB0_6
; %bb.4:
Lloh32:
	adrp	x8, _MVPP2_PRS_L3_MULTI_CAST@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MVPP2_PRS_L3_MULTI_CAST@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_ip4_cast
	cbnz	w0, LBB0_6
; %bb.5:
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh35:
	adrp	x21, _MVPP2_PRS_LU_IP4@GOTPAGE
Lloh36:
	ldr	x21, [x21, _MVPP2_PRS_LU_IP4@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
Lloh37:
	adrp	x8, _MVPP2_PE_IP4_PROTO_UN@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MVPP2_PE_IP4_PROTO_UN@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	ldr	w1, [x21]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh40:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh41:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	add	x0, sp, #8
	mov	w1, #12
	bl	_mvpp2_prs_sram_shift_set
Lloh43:
	adrp	x8, _MVPP2_PRS_SRAM_UDF_TYPE_L4@GOTPAGE
Lloh44:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_UDF_TYPE_L4@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGE
Lloh47:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGEOFF]
Lloh48:
	ldr	w3, [x8]
	add	x0, sp, #8
	mov	w2, #0
	bl	_mvpp2_prs_sram_offset_set
Lloh49:
	adrp	x22, _MVPP2_PRS_IPV4_DIP_AI_BIT@GOTPAGE
Lloh50:
	ldr	x22, [x22, _MVPP2_PRS_IPV4_DIP_AI_BIT@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_sram_ai_update
Lloh51:
	adrp	x8, _MVPP2_PRS_RI_L4_OTHER@GOTPAGE
Lloh52:
	ldr	x8, [x8, _MVPP2_PRS_RI_L4_OTHER@GOTPAGEOFF]
Lloh53:
	ldr	w1, [x8]
	ldr	w2, [x20]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
	ldr	w2, [x22]
	add	x0, sp, #8
	mov	w1, #0
	bl	_mvpp2_prs_tcam_ai_update
Lloh54:
	adrp	x20, _MVPP2_PRS_PORT_MASK@GOTPAGE
Lloh55:
	ldr	x20, [x20, _MVPP2_PRS_PORT_MASK@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	w1, [x21]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
Lloh56:
	adrp	x8, _MVPP2_PE_IP4_ADDR_UN@GOTPAGE
Lloh57:
	ldr	x8, [x8, _MVPP2_PE_IP4_ADDR_UN@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	str	w8, [sp, #8]
Lloh59:
	adrp	x8, _MVPP2_PRS_LU_FLOWS@GOTPAGE
Lloh60:
	ldr	x8, [x8, _MVPP2_PRS_LU_FLOWS@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh62:
	adrp	x8, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGE
Lloh63:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
	add	x0, sp, #8
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
Lloh65:
	adrp	x8, _MVPP2_PRS_RI_L3_UCAST@GOTPAGE
Lloh66:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_UCAST@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
Lloh68:
	adrp	x8, _MVPP2_PRS_RI_L3_ADDR_MASK@GOTPAGE
Lloh69:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_ADDR_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [x22]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_tcam_ai_update
	ldr	w1, [x20]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	mov	w0, #0
LBB0_6:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh35, Lloh36
	.cfi_endproc
                                        ; -- End function
	.comm	_IPPROTO_TCP,4,2                ; @IPPROTO_TCP
	.comm	_MVPP2_PRS_RI_L4_TCP,4,2        ; @MVPP2_PRS_RI_L4_TCP
	.comm	_MVPP2_PRS_RI_L4_PROTO_MASK,4,2 ; @MVPP2_PRS_RI_L4_PROTO_MASK
	.comm	_IPPROTO_UDP,4,2                ; @IPPROTO_UDP
	.comm	_MVPP2_PRS_RI_L4_UDP,4,2        ; @MVPP2_PRS_RI_L4_UDP
	.comm	_IPPROTO_IGMP,4,2               ; @IPPROTO_IGMP
	.comm	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC,4,2 ; @MVPP2_PRS_RI_CPU_CODE_RX_SPEC
	.comm	_MVPP2_PRS_RI_UDF3_RX_SPECIAL,4,2 ; @MVPP2_PRS_RI_UDF3_RX_SPECIAL
	.comm	_MVPP2_PRS_RI_CPU_CODE_MASK,4,2 ; @MVPP2_PRS_RI_CPU_CODE_MASK
	.comm	_MVPP2_PRS_RI_UDF3_MASK,4,2     ; @MVPP2_PRS_RI_UDF3_MASK
	.comm	_MVPP2_PRS_L3_BROAD_CAST,4,2    ; @MVPP2_PRS_L3_BROAD_CAST
	.comm	_MVPP2_PRS_L3_MULTI_CAST,4,2    ; @MVPP2_PRS_L3_MULTI_CAST
	.comm	_MVPP2_PRS_LU_IP4,4,2           ; @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PE_IP4_PROTO_UN,4,2      ; @MVPP2_PE_IP4_PROTO_UN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L4,4,2 ; @MVPP2_PRS_SRAM_UDF_TYPE_L4
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_PRS_IPV4_DIP_AI_BIT,4,2  ; @MVPP2_PRS_IPV4_DIP_AI_BIT
	.comm	_MVPP2_PRS_RI_L4_OTHER,4,2      ; @MVPP2_PRS_RI_L4_OTHER
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ; @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PE_IP4_ADDR_UN,4,2       ; @MVPP2_PE_IP4_ADDR_UN
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ; @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ; @MVPP2_PRS_SRAM_LU_GEN_BIT
	.comm	_MVPP2_PRS_RI_L3_UCAST,4,2      ; @MVPP2_PRS_RI_L3_UCAST
	.comm	_MVPP2_PRS_RI_L3_ADDR_MASK,4,2  ; @MVPP2_PRS_RI_L3_ADDR_MASK
	.no_dead_strip	_mvpp2_prs_ip4_init
.subsections_via_symbols
