	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function get_port_device_capability
_get_port_device_capability:            ## @get_port_device_capability
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	16(%rdi), %edi
	callq	_pci_find_host_bridge
	movq	%rax, %r15
	xorl	%r14d, %r14d
	cmpq	$0, 8(%rbx)
	je	LBB0_4
## %bb.1:
	movq	_pcie_ports_native@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	jne	LBB0_3
## %bb.2:
	cmpq	$0, 16(%r15)
	je	LBB0_4
LBB0_3:
	movq	_PCIE_PORT_SERVICE_HP@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_PCI_EXP_SLTCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCI_EXP_SLTCTL_CCIE@GOTPCREL(%rip), %rax
	movq	_PCI_EXP_SLTCTL_HPIE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_pcie_capability_clear_word
LBB0_4:
	movq	%rbx, %rdi
	callq	_pci_pcie_type
	movq	_PCI_EXP_TYPE_ROOT_PORT@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rax
	jne	LBB0_8
## %bb.5:
	movq	_pcie_ports_native@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	jne	LBB0_7
## %bb.6:
	cmpq	$0, (%r15)
	je	LBB0_8
LBB0_7:
	movq	_PCIE_PORT_SERVICE_PME@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_pcie_pme_interrupt_enable
LBB0_8:
	movq	_PCI_EXT_CAP_ID_DPC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_pci_find_ext_capability
	testq	%rax, %rax
	je	LBB0_12
## %bb.9:
	xorl	%eax, %eax
	callq	_pci_aer_available
	testq	%rax, %rax
	je	LBB0_12
## %bb.10:
	movq	_PCIE_PORT_SERVICE_AER@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_12
## %bb.11:
	movq	_PCIE_PORT_SERVICE_DPC@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
LBB0_12:
	movq	%rbx, %rdi
	callq	_pci_pcie_type
	movq	_PCI_EXP_TYPE_DOWNSTREAM@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_14
## %bb.13:
	movq	%rbx, %rdi
	callq	_pci_pcie_type
	cmpq	(%r12), %rax
	jne	LBB0_15
LBB0_14:
	movq	_PCIE_PORT_SERVICE_BWNOTIF@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
LBB0_15:
	movl	%r14d, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_pcie_ports_native,8,3          ## @pcie_ports_native
	.comm	_PCIE_PORT_SERVICE_HP,4,2       ## @PCIE_PORT_SERVICE_HP
	.comm	_PCI_EXP_SLTCTL,4,2             ## @PCI_EXP_SLTCTL
	.comm	_PCI_EXP_SLTCTL_CCIE,4,2        ## @PCI_EXP_SLTCTL_CCIE
	.comm	_PCI_EXP_SLTCTL_HPIE,4,2        ## @PCI_EXP_SLTCTL_HPIE
	.comm	_PCI_EXP_TYPE_ROOT_PORT,8,3     ## @PCI_EXP_TYPE_ROOT_PORT
	.comm	_PCIE_PORT_SERVICE_PME,4,2      ## @PCIE_PORT_SERVICE_PME
	.comm	_PCI_EXT_CAP_ID_DPC,4,2         ## @PCI_EXT_CAP_ID_DPC
	.comm	_PCIE_PORT_SERVICE_AER,4,2      ## @PCIE_PORT_SERVICE_AER
	.comm	_PCIE_PORT_SERVICE_DPC,4,2      ## @PCIE_PORT_SERVICE_DPC
	.comm	_PCI_EXP_TYPE_DOWNSTREAM,8,3    ## @PCI_EXP_TYPE_DOWNSTREAM
	.comm	_PCIE_PORT_SERVICE_BWNOTIF,4,2  ## @PCIE_PORT_SERVICE_BWNOTIF
	.no_dead_strip	_get_port_device_capability
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function get_port_device_capability
_get_port_device_capability:            ; @get_port_device_capability
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w0, [x0, #16]
	bl	_pci_find_host_bridge
	mov	x21, x0
	ldr	x8, [x19, #8]
Lloh0:
	adrp	x23, _pcie_ports_native@GOTPAGE
Lloh1:
	ldr	x23, [x23, _pcie_ports_native@GOTPAGEOFF]
	cbz	x8, LBB0_4
; %bb.1:
	ldr	x8, [x23]
	cbnz	x8, LBB0_3
; %bb.2:
	ldr	x8, [x21, #16]
	cbz	x8, LBB0_4
LBB0_3:
Lloh2:
	adrp	x8, _PCIE_PORT_SERVICE_HP@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_PORT_SERVICE_HP@GOTPAGEOFF]
Lloh4:
	ldr	w20, [x8]
Lloh5:
	adrp	x8, _PCI_EXP_SLTCTL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCI_EXP_SLTCTL@GOTPAGEOFF]
Lloh7:
	adrp	x9, _PCI_EXP_SLTCTL_CCIE@GOTPAGE
Lloh8:
	ldr	x9, [x9, _PCI_EXP_SLTCTL_CCIE@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
Lloh10:
	ldr	w8, [x9]
Lloh11:
	adrp	x9, _PCI_EXP_SLTCTL_HPIE@GOTPAGE
Lloh12:
	ldr	x9, [x9, _PCI_EXP_SLTCTL_HPIE@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_pcie_capability_clear_word
	b	LBB0_5
LBB0_4:
	mov	w20, #0
LBB0_5:
	mov	x0, x19
	bl	_pci_pcie_type
Lloh14:
	adrp	x22, _PCI_EXP_TYPE_ROOT_PORT@GOTPAGE
Lloh15:
	ldr	x22, [x22, _PCI_EXP_TYPE_ROOT_PORT@GOTPAGEOFF]
	ldr	x8, [x22]
	cmp	x0, x8
	b.ne	LBB0_9
; %bb.6:
	ldr	x8, [x23]
	cbnz	x8, LBB0_8
; %bb.7:
	ldr	x8, [x21]
	cbz	x8, LBB0_9
LBB0_8:
Lloh16:
	adrp	x8, _PCIE_PORT_SERVICE_PME@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PCIE_PORT_SERVICE_PME@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	orr	w20, w8, w20
	mov	x0, x19
	mov	w1, #0
	bl	_pcie_pme_interrupt_enable
LBB0_9:
Lloh19:
	adrp	x8, _PCI_EXT_CAP_ID_DPC@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PCI_EXT_CAP_ID_DPC@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_pci_find_ext_capability
	cbz	x0, LBB0_13
; %bb.10:
	bl	_pci_aer_available
	cbz	x0, LBB0_13
; %bb.11:
Lloh22:
	adrp	x8, _PCIE_PORT_SERVICE_AER@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PCIE_PORT_SERVICE_AER@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_13
; %bb.12:
Lloh25:
	adrp	x8, _PCIE_PORT_SERVICE_DPC@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PCIE_PORT_SERVICE_DPC@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_13:
	mov	x0, x19
	bl	_pci_pcie_type
Lloh28:
	adrp	x8, _PCI_EXP_TYPE_DOWNSTREAM@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PCI_EXP_TYPE_DOWNSTREAM@GOTPAGEOFF]
Lloh30:
	ldr	x8, [x8]
	cmp	x0, x8
	b.eq	LBB0_15
; %bb.14:
	mov	x0, x19
	bl	_pci_pcie_type
	ldr	x8, [x22]
	cmp	x0, x8
	b.ne	LBB0_16
LBB0_15:
Lloh31:
	adrp	x8, _PCIE_PORT_SERVICE_BWNOTIF@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PCIE_PORT_SERVICE_BWNOTIF@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_16:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh9
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.cfi_endproc
                                        ; -- End function
	.comm	_pcie_ports_native,8,3          ; @pcie_ports_native
	.comm	_PCIE_PORT_SERVICE_HP,4,2       ; @PCIE_PORT_SERVICE_HP
	.comm	_PCI_EXP_SLTCTL,4,2             ; @PCI_EXP_SLTCTL
	.comm	_PCI_EXP_SLTCTL_CCIE,4,2        ; @PCI_EXP_SLTCTL_CCIE
	.comm	_PCI_EXP_SLTCTL_HPIE,4,2        ; @PCI_EXP_SLTCTL_HPIE
	.comm	_PCI_EXP_TYPE_ROOT_PORT,8,3     ; @PCI_EXP_TYPE_ROOT_PORT
	.comm	_PCIE_PORT_SERVICE_PME,4,2      ; @PCIE_PORT_SERVICE_PME
	.comm	_PCI_EXT_CAP_ID_DPC,4,2         ; @PCI_EXT_CAP_ID_DPC
	.comm	_PCIE_PORT_SERVICE_AER,4,2      ; @PCIE_PORT_SERVICE_AER
	.comm	_PCIE_PORT_SERVICE_DPC,4,2      ; @PCIE_PORT_SERVICE_DPC
	.comm	_PCI_EXP_TYPE_DOWNSTREAM,8,3    ; @PCI_EXP_TYPE_DOWNSTREAM
	.comm	_PCIE_PORT_SERVICE_BWNOTIF,4,2  ; @PCIE_PORT_SERVICE_BWNOTIF
	.no_dead_strip	_get_port_device_capability
.subsections_via_symbols
