	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ltq_vrx200_pcie_phy_apply_workarounds
_ltq_vrx200_pcie_phy_apply_workarounds: ## @ltq_vrx200_pcie_phy_apply_workarounds
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_phy_get_drvdata
	movq	%rax, %r15
	leaq	_ltq_vrx200_pcie_phy_apply_workarounds.slices(%rip), %r14
	movq	%r14, %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_3
## %bb.1:
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	movl	(%r14,%rbx,8), %r13d
	movl	4(%r14,%rbx,8), %r12d
	movl	%r12d, %esi
	movl	%r13d, %edx
	movl	%r13d, %ecx
	callq	_regmap_update_bits
	movl	$1, %edi
	callq	_udelay
	movl	(%r15), %edi
	movl	%r12d, %esi
	movl	%r13d, %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	incq	%rbx
	movq	%r14, %rdi
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %rbx
	jl	LBB0_2
LBB0_3:
	movl	$5, %ebx
	movq	_PCIE_PHY_TX2_MOD3@GOTPCREL(%rip), %r13
	movq	_PCIE_PHY_TX1_MOD2@GOTPCREL(%rip), %r12
	movq	_PCIE_PHY_TX1_MOD3@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edi
	movq	_PCIE_PHY_TX2_MOD1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$8190, %edx                     ## imm = 0x1FFE
	callq	_regmap_write
	movl	(%r15), %edi
	movq	_PCIE_PHY_TX2_MOD2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$65534, %edx                    ## imm = 0xFFFE
	callq	_regmap_write
	movl	(%r15), %edi
	movl	(%r13), %esi
	movl	$1537, %edx                     ## imm = 0x601
	callq	_regmap_write
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movl	(%r15), %edi
	movl	(%r13), %esi
	movl	$1, %edx
	callq	_regmap_write
	movl	(%r15), %edi
	movq	_PCIE_PHY_TX1_MOD1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$8190, %edx                     ## imm = 0x1FFE
	callq	_regmap_write
	movl	(%r15), %edi
	movl	(%r12), %esi
	movl	$65534, %edx                    ## imm = 0xFFFE
	callq	_regmap_write
	movl	(%r15), %edi
	movl	(%r14), %esi
	movl	$1537, %edx                     ## imm = 0x601
	callq	_regmap_write
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movl	(%r15), %edi
	movl	(%r14), %esi
	movl	$1, %edx
	callq	_regmap_write
	decl	%ebx
	jne	LBB0_4
## %bb.5:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__const
	.p2align	4                               ## @ltq_vrx200_pcie_phy_apply_workarounds.slices
_ltq_vrx200_pcie_phy_apply_workarounds.slices:
	.long	130                             ## 0x82
	.long	131                             ## 0x83
	.long	128                             ## 0x80
	.long	129                             ## 0x81
	.long	132                             ## 0x84
	.long	133                             ## 0x85

	.comm	_PCIE_PHY_TX2_MOD1,4,2          ## @PCIE_PHY_TX2_MOD1
	.comm	_PCIE_PHY_TX2_MOD2,4,2          ## @PCIE_PHY_TX2_MOD2
	.comm	_PCIE_PHY_TX2_MOD3,4,2          ## @PCIE_PHY_TX2_MOD3
	.comm	_PCIE_PHY_TX1_MOD1,4,2          ## @PCIE_PHY_TX1_MOD1
	.comm	_PCIE_PHY_TX1_MOD2,4,2          ## @PCIE_PHY_TX1_MOD2
	.comm	_PCIE_PHY_TX1_MOD3,4,2          ## @PCIE_PHY_TX1_MOD3
	.no_dead_strip	_ltq_vrx200_pcie_phy_apply_workarounds
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ltq_vrx200_pcie_phy_apply_workarounds
_ltq_vrx200_pcie_phy_apply_workarounds: ; @ltq_vrx200_pcie_phy_apply_workarounds
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	bl	_phy_get_drvdata
	mov	x19, x0
Lloh0:
	adrp	x0, _ltq_vrx200_pcie_phy_apply_workarounds.slices@PAGE
Lloh1:
	add	x0, x0, _ltq_vrx200_pcie_phy_apply_workarounds.slices@PAGEOFF
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_3
; %bb.1:
	mov	x23, #0
Lloh2:
	adrp	x24, _ltq_vrx200_pcie_phy_apply_workarounds.slices@PAGE+4
Lloh3:
	add	x24, x24, _ltq_vrx200_pcie_phy_apply_workarounds.slices@PAGEOFF+4
Lloh4:
	adrp	x20, _ltq_vrx200_pcie_phy_apply_workarounds.slices@PAGE
Lloh5:
	add	x20, x20, _ltq_vrx200_pcie_phy_apply_workarounds.slices@PAGEOFF
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x19]
	ldp	w22, w21, [x24, #-4]
	mov	x1, x21
	mov	x2, x22
	mov	x3, x22
	bl	_regmap_update_bits
	mov	w0, #1
	bl	_udelay
	ldr	w0, [x19]
	mov	x1, x21
	mov	x2, x22
	mov	w3, #0
	bl	_regmap_update_bits
	add	x23, x23, #1
	mov	x0, x20
	bl	_ARRAY_SIZE
	add	x24, x24, #8
	cmp	x23, w0, sxtw
	b.lt	LBB0_2
LBB0_3:
	mov	w20, #5
Lloh6:
	adrp	x21, _PCIE_PHY_TX2_MOD1@GOTPAGE
Lloh7:
	ldr	x21, [x21, _PCIE_PHY_TX2_MOD1@GOTPAGEOFF]
Lloh8:
	adrp	x22, _PCIE_PHY_TX2_MOD2@GOTPAGE
Lloh9:
	ldr	x22, [x22, _PCIE_PHY_TX2_MOD2@GOTPAGEOFF]
Lloh10:
	adrp	x23, _PCIE_PHY_TX2_MOD3@GOTPAGE
Lloh11:
	ldr	x23, [x23, _PCIE_PHY_TX2_MOD3@GOTPAGEOFF]
Lloh12:
	adrp	x24, _PCIE_PHY_TX1_MOD1@GOTPAGE
Lloh13:
	ldr	x24, [x24, _PCIE_PHY_TX1_MOD1@GOTPAGEOFF]
Lloh14:
	adrp	x25, _PCIE_PHY_TX1_MOD2@GOTPAGE
Lloh15:
	ldr	x25, [x25, _PCIE_PHY_TX1_MOD2@GOTPAGEOFF]
Lloh16:
	adrp	x26, _PCIE_PHY_TX1_MOD3@GOTPAGE
Lloh17:
	ldr	x26, [x26, _PCIE_PHY_TX1_MOD3@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x19]
	ldr	w1, [x21]
	mov	w2, #8190
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x22]
	mov	w2, #65534
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	w2, #1537
	bl	_regmap_write
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	ldr	w0, [x19]
	ldr	w1, [x23]
	mov	w2, #1
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x24]
	mov	w2, #8190
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x25]
	mov	w2, #65534
	bl	_regmap_write
	ldr	w0, [x19]
	ldr	w1, [x26]
	mov	w2, #1537
	bl	_regmap_write
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	ldr	w0, [x19]
	ldr	w1, [x26]
	mov	w2, #1
	bl	_regmap_write
	subs	w20, w20, #1
	b.ne	LBB0_4
; %bb.5:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__const
	.p2align	2                               ; @ltq_vrx200_pcie_phy_apply_workarounds.slices
_ltq_vrx200_pcie_phy_apply_workarounds.slices:
	.long	130                             ; 0x82
	.long	131                             ; 0x83
	.long	128                             ; 0x80
	.long	129                             ; 0x81
	.long	132                             ; 0x84
	.long	133                             ; 0x85

	.comm	_PCIE_PHY_TX2_MOD1,4,2          ; @PCIE_PHY_TX2_MOD1
	.comm	_PCIE_PHY_TX2_MOD2,4,2          ; @PCIE_PHY_TX2_MOD2
	.comm	_PCIE_PHY_TX2_MOD3,4,2          ; @PCIE_PHY_TX2_MOD3
	.comm	_PCIE_PHY_TX1_MOD1,4,2          ; @PCIE_PHY_TX1_MOD1
	.comm	_PCIE_PHY_TX1_MOD2,4,2          ; @PCIE_PHY_TX1_MOD2
	.comm	_PCIE_PHY_TX1_MOD3,4,2          ; @PCIE_PHY_TX1_MOD3
	.no_dead_strip	_ltq_vrx200_pcie_phy_apply_workarounds
.subsections_via_symbols
