	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlx5_fpga_ipsec_enable_supported_caps
_mlx5_fpga_ipsec_enable_supported_caps: ## @mlx5_fpga_ipsec_enable_supported_caps
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	callq	_mlx5_fpga_ipsec_device_caps
	movq	_MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	je	LBB0_2
## %bb.1:
	movq	_MLX5_FPGA_IPSEC_CAP_NO_TRAILER@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_2:
	movq	%rbx, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_mlx5_fpga_ipsec_set_caps       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER,4,2 ## @MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER
	.comm	_MLX5_FPGA_IPSEC_CAP_NO_TRAILER,4,2 ## @MLX5_FPGA_IPSEC_CAP_NO_TRAILER
	.no_dead_strip	_mlx5_fpga_ipsec_enable_supported_caps
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlx5_fpga_ipsec_enable_supported_caps
_mlx5_fpga_ipsec_enable_supported_caps: ; @mlx5_fpga_ipsec_enable_supported_caps
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_mlx5_fpga_ipsec_device_caps
Lloh0:
	adrp	x8, _MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER@GOTPAGEOFF]
Lloh2:
	adrp	x9, _MLX5_FPGA_IPSEC_CAP_NO_TRAILER@GOTPAGE
Lloh3:
	ldr	x9, [x9, _MLX5_FPGA_IPSEC_CAP_NO_TRAILER@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w1, wzr, w9, eq
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_mlx5_fpga_ipsec_set_caps
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER,4,2 ; @MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER
	.comm	_MLX5_FPGA_IPSEC_CAP_NO_TRAILER,4,2 ; @MLX5_FPGA_IPSEC_CAP_NO_TRAILER
	.no_dead_strip	_mlx5_fpga_ipsec_enable_supported_caps
.subsections_via_symbols
