	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pci_read_bases
_pci_read_bases:                        ## @pci_read_bases
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpq	$0, 24(%rdi)
	jne	LBB0_6
## %bb.1:
	movq	%rdi, %r12
	cmpq	$0, 16(%rdi)
	je	LBB0_2
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movl	%esi, %r15d
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	testl	%esi, %esi
	je	LBB0_5
## %bb.3:
	xorl	%ebx, %ebx
	movq	_PCI_BASE_ADDRESS_0@GOTPCREL(%rip), %r13
	movq	_pci_bar_unknown@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edx
	shlq	$2, %rdx
	addq	8(%r12), %rdx
	leal	(,%rbx,4), %ecx
	addl	(%r13), %ecx
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	___pci_read_base
	addl	%eax, %ebx
	incl	%ebx
	cmpl	%r15d, %ebx
	jb	LBB0_4
LBB0_5:
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	testl	%ecx, %ecx
	je	LBB0_6
## %bb.7:
	movq	8(%r12), %rax
	movq	_PCI_ROM_RESOURCE@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdi
	movl	%ecx, (%r12)
	movq	_IORESOURCE_MEM@GOTPCREL(%rip), %rdx
	movq	_IORESOURCE_PREFETCH@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	orl	(%rdx), %esi
	movq	_IORESOURCE_READONLY@GOTPCREL(%rip), %rdx
	orl	(%rdx), %esi
	movq	_IORESOURCE_SIZEALIGN@GOTPCREL(%rip), %rdx
	orl	(%rdx), %esi
	leaq	(%rax,%rdi,4), %rdx
	movl	%esi, (%rax,%rdi,4)
	movq	_pci_bar_mem32@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	___pci_read_base                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_BASE_ADDRESS_0,4,2         ## @PCI_BASE_ADDRESS_0
	.comm	_pci_bar_unknown,4,2            ## @pci_bar_unknown
	.comm	_PCI_ROM_RESOURCE,8,3           ## @PCI_ROM_RESOURCE
	.comm	_IORESOURCE_MEM,4,2             ## @IORESOURCE_MEM
	.comm	_IORESOURCE_PREFETCH,4,2        ## @IORESOURCE_PREFETCH
	.comm	_IORESOURCE_READONLY,4,2        ## @IORESOURCE_READONLY
	.comm	_IORESOURCE_SIZEALIGN,4,2       ## @IORESOURCE_SIZEALIGN
	.comm	_pci_bar_mem32,4,2              ## @pci_bar_mem32
	.no_dead_strip	_pci_read_bases
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pci_read_bases
_pci_read_bases:                        ; @pci_read_bases
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	x8, [x0, #24]
	cbnz	x8, LBB0_2
; %bb.1:
	mov	x20, x0
	ldr	x8, [x0, #16]
	cbz	x8, LBB0_3
LBB0_2:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_3:
	mov	x19, x2
	mov	x21, x1
	cbz	w1, LBB0_6
; %bb.4:
	mov	w22, #0
Lloh0:
	adrp	x23, _PCI_BASE_ADDRESS_0@GOTPAGE
Lloh1:
	ldr	x23, [x23, _PCI_BASE_ADDRESS_0@GOTPAGEOFF]
Lloh2:
	adrp	x24, _pci_bar_unknown@GOTPAGE
Lloh3:
	ldr	x24, [x24, _pci_bar_unknown@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #8]
	add	x2, x8, w22, uxtw #2
	ldr	w8, [x23]
	add	w3, w8, w22, lsl #2
	ldr	w1, [x24]
	mov	x0, x20
	bl	___pci_read_base
	add	w8, w22, w0
	add	w22, w8, #1
	cmp	w22, w21
	b.lo	LBB0_5
LBB0_6:
	cbz	w19, LBB0_2
; %bb.7:
	ldr	x8, [x20, #8]
Lloh4:
	adrp	x9, _PCI_ROM_RESOURCE@GOTPAGE
Lloh5:
	ldr	x9, [x9, _PCI_ROM_RESOURCE@GOTPAGEOFF]
Lloh6:
	ldr	x9, [x9]
	add	x2, x8, x9, lsl #2
	str	w19, [x20]
Lloh7:
	adrp	x8, _IORESOURCE_MEM@GOTPAGE
Lloh8:
	ldr	x8, [x8, _IORESOURCE_MEM@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _IORESOURCE_PREFETCH@GOTPAGE
Lloh11:
	ldr	x9, [x9, _IORESOURCE_PREFETCH@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh13:
	adrp	x9, _IORESOURCE_READONLY@GOTPAGE
Lloh14:
	ldr	x9, [x9, _IORESOURCE_READONLY@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh16:
	adrp	x9, _IORESOURCE_SIZEALIGN@GOTPAGE
Lloh17:
	ldr	x9, [x9, _IORESOURCE_SIZEALIGN@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh19:
	adrp	x9, _pci_bar_mem32@GOTPAGE
Lloh20:
	ldr	x9, [x9, _pci_bar_mem32@GOTPAGEOFF]
	str	w8, [x2]
Lloh21:
	ldr	w1, [x9]
	mov	x0, x20
	mov	x3, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	___pci_read_base
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_BASE_ADDRESS_0,4,2         ; @PCI_BASE_ADDRESS_0
	.comm	_pci_bar_unknown,4,2            ; @pci_bar_unknown
	.comm	_PCI_ROM_RESOURCE,8,3           ; @PCI_ROM_RESOURCE
	.comm	_IORESOURCE_MEM,4,2             ; @IORESOURCE_MEM
	.comm	_IORESOURCE_PREFETCH,4,2        ; @IORESOURCE_PREFETCH
	.comm	_IORESOURCE_READONLY,4,2        ; @IORESOURCE_READONLY
	.comm	_IORESOURCE_SIZEALIGN,4,2       ; @IORESOURCE_SIZEALIGN
	.comm	_pci_bar_mem32,4,2              ; @pci_bar_mem32
	.no_dead_strip	_pci_read_bases
.subsections_via_symbols
