	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_port_check_link
_tegra_pcie_port_check_link:            ## @tegra_pcie_port_check_link
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	16(%rdi), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_RP_PRIV_MISC@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r14), %rdi
	callq	_readl
	movq	_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdi
	notq	%rdi
	andq	%rax, %rdi
	movq	_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT@GOTPCREL(%rip), %rax
	orq	(%rax), %rdi
	movq	(%rbx), %rsi
	addq	(%r14), %rsi
	callq	_writel
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_RP_VEND_XP@GOTPCREL(%rip), %r12
	movq	_RP_VEND_XP_DL_UP@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testq	%rax, (%r13)
	jne	LBB0_3
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	decl	%r15d
	jne	LBB0_1
	jmp	LBB0_7
LBB0_3:
	testl	%r15d, %r15d
	je	LBB0_7
## %bb.4:
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	_RP_LINK_CONTROL_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testq	%rax, (%r15)
	jne	LBB0_27
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	decl	%ebx
	jne	LBB0_5
	jmp	LBB0_8
LBB0_7:
	movl	8(%r14), %edx
	leaq	L_.str(%rip), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dev_dbg
LBB0_8:
	movq	%r14, %rdi
	callq	_tegra_pcie_port_reset
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	.p2align	4, 0x90
LBB0_9:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testq	%rax, (%r13)
	jne	LBB0_11
## %bb.10:                              ##   in Loop: Header=BB0_9 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	decl	%ebx
	jne	LBB0_9
	jmp	LBB0_15
LBB0_11:
	testl	%ebx, %ebx
	je	LBB0_15
## %bb.12:
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	_RP_LINK_CONTROL_STATUS@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testq	%rax, (%r15)
	jne	LBB0_27
## %bb.14:                              ##   in Loop: Header=BB0_13 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	decl	%ebx
	jne	LBB0_13
	jmp	LBB0_16
LBB0_15:
	movl	8(%r14), %edx
	leaq	L_.str(%rip), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dev_dbg
LBB0_16:
	movq	%r14, %rdi
	callq	_tegra_pcie_port_reset
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r12), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testq	%rax, (%r13)
	jne	LBB0_19
## %bb.18:                              ##   in Loop: Header=BB0_17 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	decl	%ebx
	jne	LBB0_17
	jmp	LBB0_23
LBB0_19:
	testl	%ebx, %ebx
	je	LBB0_23
## %bb.20:
	movq	_TEGRA_PCIE_LINKUP_TIMEOUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RP_LINK_CONTROL_STATUS@GOTPCREL(%rip), %r15
	movq	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_21:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rdi
	addq	(%r14), %rdi
	callq	_readl
	testq	%rax, (%r12)
	jne	LBB0_27
## %bb.22:                              ##   in Loop: Header=BB0_21 Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	decl	%ebx
	jne	LBB0_21
	jmp	LBB0_24
LBB0_23:
	movl	8(%r14), %edx
	leaq	L_.str(%rip), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dev_dbg
LBB0_24:
	movq	%r14, %rdi
	callq	_tegra_pcie_port_reset
	xorl	%eax, %eax
	jmp	LBB0_28
LBB0_27:
	movl	$1, %eax
LBB0_28:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RP_PRIV_MISC,8,3               ## @RP_PRIV_MISC
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT,8,3 ## @RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT,8,3 ## @RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
	.comm	_TEGRA_PCIE_LINKUP_TIMEOUT,4,2  ## @TEGRA_PCIE_LINKUP_TIMEOUT
	.comm	_RP_VEND_XP,8,3                 ## @RP_VEND_XP
	.comm	_RP_VEND_XP_DL_UP,8,3           ## @RP_VEND_XP_DL_UP
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"link %u down, retrying\n"

	.comm	_RP_LINK_CONTROL_STATUS,8,3     ## @RP_LINK_CONTROL_STATUS
	.comm	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE,8,3 ## @RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
	.no_dead_strip	_tegra_pcie_port_check_link
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_port_check_link
_tegra_pcie_port_check_link:            ; @tegra_pcie_port_check_link
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x8, [x0, #16]
	ldr	x20, [x8]
	ldr	x8, [x0]
Lloh0:
	adrp	x21, _RP_PRIV_MISC@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RP_PRIV_MISC@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh2:
	adrp	x8, _RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
Lloh5:
	adrp	x9, _RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT@GOTPAGEOFF]
	bic	x8, x0, x8
Lloh7:
	ldr	x9, [x9]
	orr	x0, x8, x9
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
Lloh8:
	adrp	x21, _TEGRA_PCIE_LINKUP_TIMEOUT@GOTPAGE
Lloh9:
	ldr	x21, [x21, _TEGRA_PCIE_LINKUP_TIMEOUT@GOTPAGEOFF]
	ldr	w24, [x21]
Lloh10:
	adrp	x22, _RP_VEND_XP@GOTPAGE
Lloh11:
	ldr	x22, [x22, _RP_VEND_XP@GOTPAGEOFF]
Lloh12:
	adrp	x23, _RP_VEND_XP_DL_UP@GOTPAGE
Lloh13:
	ldr	x23, [x23, _RP_VEND_XP_DL_UP@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	ldr	x8, [x23]
	tst	x8, x0
	b.ne	LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	subs	w24, w24, #1
	b.ne	LBB0_1
	b	LBB0_7
LBB0_3:
	cbz	w24, LBB0_7
; %bb.4:
	ldr	w24, [x21]
Lloh14:
	adrp	x25, _RP_LINK_CONTROL_STATUS@GOTPAGE
Lloh15:
	ldr	x25, [x25, _RP_LINK_CONTROL_STATUS@GOTPAGEOFF]
Lloh16:
	adrp	x26, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGE
Lloh17:
	ldr	x26, [x26, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x9, [x25]
	add	x0, x9, x8
	bl	_readl
	ldr	x8, [x26]
	tst	x8, x0
	b.ne	LBB0_25
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	subs	w24, w24, #1
	b.ne	LBB0_5
	b	LBB0_8
LBB0_7:
	ldr	w2, [x19, #8]
Lloh18:
	adrp	x1, l_.str@PAGE
Lloh19:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_dev_dbg
LBB0_8:
	mov	x0, x19
	bl	_tegra_pcie_port_reset
	ldr	w24, [x21]
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	ldr	x8, [x23]
	tst	x8, x0
	b.ne	LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_9 Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	subs	w24, w24, #1
	b.ne	LBB0_9
	b	LBB0_15
LBB0_11:
	cbz	w24, LBB0_15
; %bb.12:
	ldr	w24, [x21]
Lloh20:
	adrp	x25, _RP_LINK_CONTROL_STATUS@GOTPAGE
Lloh21:
	ldr	x25, [x25, _RP_LINK_CONTROL_STATUS@GOTPAGEOFF]
Lloh22:
	adrp	x26, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGE
Lloh23:
	ldr	x26, [x26, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGEOFF]
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x9, [x25]
	add	x0, x9, x8
	bl	_readl
	ldr	x8, [x26]
	tst	x8, x0
	b.ne	LBB0_25
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	subs	w24, w24, #1
	b.ne	LBB0_13
	b	LBB0_16
LBB0_15:
	ldr	w2, [x19, #8]
Lloh24:
	adrp	x1, l_.str@PAGE
Lloh25:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_dev_dbg
LBB0_16:
	mov	x0, x19
	bl	_tegra_pcie_port_reset
	ldr	w24, [x21]
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x9, [x22]
	add	x0, x9, x8
	bl	_readl
	ldr	x8, [x23]
	tst	x8, x0
	b.ne	LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	subs	w24, w24, #1
	b.ne	LBB0_17
	b	LBB0_23
LBB0_19:
	cbz	w24, LBB0_23
; %bb.20:
	ldr	w20, [x21]
Lloh26:
	adrp	x21, _RP_LINK_CONTROL_STATUS@GOTPAGE
Lloh27:
	ldr	x21, [x21, _RP_LINK_CONTROL_STATUS@GOTPAGEOFF]
Lloh28:
	adrp	x22, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGE
Lloh29:
	ldr	x22, [x22, _RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE@GOTPAGEOFF]
LBB0_21:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	x8, [x22]
	tst	x8, x0
	b.ne	LBB0_25
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	subs	w20, w20, #1
	b.ne	LBB0_21
	b	LBB0_24
LBB0_23:
	ldr	w2, [x19, #8]
Lloh30:
	adrp	x1, l_.str@PAGE
Lloh31:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_dev_dbg
LBB0_24:
	mov	x0, x19
	bl	_tegra_pcie_port_reset
	mov	w0, #0
	b	LBB0_26
LBB0_25:
	mov	w0, #1
LBB0_26:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpAdd	Lloh30, Lloh31
	.cfi_endproc
                                        ; -- End function
	.comm	_RP_PRIV_MISC,8,3               ; @RP_PRIV_MISC
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT,8,3 ; @RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
	.comm	_RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT,8,3 ; @RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
	.comm	_TEGRA_PCIE_LINKUP_TIMEOUT,4,2  ; @TEGRA_PCIE_LINKUP_TIMEOUT
	.comm	_RP_VEND_XP,8,3                 ; @RP_VEND_XP
	.comm	_RP_VEND_XP_DL_UP,8,3           ; @RP_VEND_XP_DL_UP
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"link %u down, retrying\n"

	.comm	_RP_LINK_CONTROL_STATUS,8,3     ; @RP_LINK_CONTROL_STATUS
	.comm	_RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE,8,3 ; @RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
	.no_dead_strip	_tegra_pcie_port_check_link
.subsections_via_symbols
