	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pcie_enable_interrupt          ## -- Begin function pcie_enable_interrupt
	.p2align	4, 0x90
_pcie_enable_interrupt:                 ## @pcie_enable_interrupt
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_PCI_EXP_SLTCTL_HPIE@GOTPCREL(%rip), %rax
	movq	_PCI_EXP_SLTCTL_DLLSCE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movl	%edx, %esi
	popq	%rbp
	jmp	_pcie_write_cmd                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_EXP_SLTCTL_HPIE,4,2        ## @PCI_EXP_SLTCTL_HPIE
	.comm	_PCI_EXP_SLTCTL_DLLSCE,4,2      ## @PCI_EXP_SLTCTL_DLLSCE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pcie_enable_interrupt          ; -- Begin function pcie_enable_interrupt
	.p2align	2
_pcie_enable_interrupt:                 ; @pcie_enable_interrupt
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _PCI_EXP_SLTCTL_HPIE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_EXP_SLTCTL_HPIE@GOTPAGEOFF]
Lloh2:
	adrp	x9, _PCI_EXP_SLTCTL_DLLSCE@GOTPAGE
Lloh3:
	ldr	x9, [x9, _PCI_EXP_SLTCTL_DLLSCE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	ldr	w9, [x9]
	orr	w1, w9, w8
	mov	x2, x1
	b	_pcie_write_cmd
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_EXP_SLTCTL_HPIE,4,2        ; @PCI_EXP_SLTCTL_HPIE
	.comm	_PCI_EXP_SLTCTL_DLLSCE,4,2      ; @PCI_EXP_SLTCTL_DLLSCE
.subsections_via_symbols
