	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pci_bridge_d3_possible         ## -- Begin function pci_bridge_d3_possible
	.p2align	4, 0x90
_pci_bridge_d3_possible:                ## @pci_bridge_d3_possible
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_pci_is_pcie
	testl	%eax, %eax
	je	LBB0_11
## %bb.1:
	movq	%rbx, %rdi
	callq	_pci_pcie_type
	addl	$-128, %eax
	cmpl	$2, %eax
	ja	LBB0_11
## %bb.2:
	movq	_pci_bridge_d3_disable@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	je	LBB0_3
LBB0_11:
	xorl	%r14d, %r14d
LBB0_12:
	movl	%r14d, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_3:
	cmpl	$0, (%rbx)
	je	LBB0_5
## %bb.4:
	movq	%rbx, %rdi
	callq	_pciehp_is_native
	testl	%eax, %eax
	je	LBB0_11
LBB0_5:
	movq	_pci_bridge_d3_force@GOTPCREL(%rip), %rax
	movl	$1, %r14d
	cmpl	$0, (%rax)
	jne	LBB0_12
## %bb.6:
	cmpl	$0, 4(%rbx)
	jne	LBB0_12
## %bb.7:
	movq	%rbx, %rdi
	callq	_platform_pci_bridge_d3
	testl	%eax, %eax
	jne	LBB0_12
## %bb.8:
	cmpl	$0, (%rbx)
	jne	LBB0_11
## %bb.9:
	movq	_bridge_d3_blacklist@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_dmi_check_system
	testl	%eax, %eax
	jne	LBB0_11
## %bb.10:
	xorl	%eax, %eax
	callq	_dmi_get_bios_year
	cmpl	$2014, %eax                     ## imm = 0x7DE
	jle	LBB0_11
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_pci_bridge_d3_disable,4,2      ## @pci_bridge_d3_disable
	.comm	_pci_bridge_d3_force,4,2        ## @pci_bridge_d3_force
	.comm	_bridge_d3_blacklist,4,2        ## @bridge_d3_blacklist
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pci_bridge_d3_possible         ; -- Begin function pci_bridge_d3_possible
	.p2align	2
_pci_bridge_d3_possible:                ; @pci_bridge_d3_possible
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_pci_is_pcie
	cbz	w0, LBB0_4
; %bb.1:
	mov	x0, x19
	bl	_pci_pcie_type
	sub	w8, w0, #128
	cmp	w8, #2
	b.hi	LBB0_3
; %bb.2:
Lloh0:
	adrp	x8, _pci_bridge_d3_disable@GOTPAGE
Lloh1:
	ldr	x8, [x8, _pci_bridge_d3_disable@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cbz	w8, LBB0_5
LBB0_3:
	mov	w0, #0
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_5:
	ldr	w8, [x19]
	cbz	w8, LBB0_7
; %bb.6:
	mov	x0, x19
	bl	_pciehp_is_native
	cbz	w0, LBB0_4
LBB0_7:
Lloh3:
	adrp	x8, _pci_bridge_d3_force@GOTPAGE
Lloh4:
	ldr	x8, [x8, _pci_bridge_d3_force@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	cbnz	w8, LBB0_10
; %bb.8:
	ldr	w8, [x19, #4]
	cbnz	w8, LBB0_10
; %bb.9:
	mov	x0, x19
	bl	_platform_pci_bridge_d3
	cbz	w0, LBB0_11
LBB0_10:
	mov	w0, #1
	b	LBB0_4
LBB0_11:
	ldr	w8, [x19]
	cbnz	w8, LBB0_3
; %bb.12:
Lloh6:
	adrp	x8, _bridge_d3_blacklist@GOTPAGE
Lloh7:
	ldr	x8, [x8, _bridge_d3_blacklist@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_dmi_check_system
	cbnz	w0, LBB0_3
; %bb.13:
	bl	_dmi_get_bios_year
	cmp	w0, #2014
	b.le	LBB0_3
	b	LBB0_10
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_pci_bridge_d3_disable,4,2      ; @pci_bridge_d3_disable
	.comm	_pci_bridge_d3_force,4,2        ; @pci_bridge_d3_force
	.comm	_bridge_d3_blacklist,4,2        ; @bridge_d3_blacklist
.subsections_via_symbols
