	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra210_sata_uphy_enable
_tegra210_sata_uphy_enable:             ## @tegra210_sata_uphy_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r12
	movl	(%rdi), %edi
	callq	_to_sata_pad
	movq	%rax, %r14
	movq	(%rax), %rax
	testq	%rax, %rax
	jle	LBB0_2
## %bb.1:
	incq	%rax
	movq	%rax, (%r14)
	xorl	%ebx, %ebx
	jmp	LBB0_34
LBB0_2:
	movl	8(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	js	LBB0_3
## %bb.4:
	movl	12(%r14), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	js	LBB0_5
## %bb.6:
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rax, %rbx
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	shll	%cl, %esi
	notl	%edx
	andl	%eax, %edx
	orl	%edx, %esi
	movl	(%rbx), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL5@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	shll	%cl, %esi
	notl	%edx
	andl	%eax, %edx
	orl	%edx, %esi
	movl	(%rbx), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL1@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r13), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %dl
	movl	%edx, %ecx
	shll	%cl, %esi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	orl	%esi, %edi
	notl	%edi
	andl	%eax, %edi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	testl	%r15d, %r15d
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL@GOTPCREL(%rip), %rax
	cmoveq	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN@GOTPCREL(%rip), %rax
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL@GOTPCREL(%rip), %rbx
	cmoveq	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL@GOTPCREL(%rip), %rbx
	movl	(%rax), %eax
	movl	%edx, %ecx
	shll	%cl, %esi
	notl	%eax
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	%edi, %esi
	andl	%eax, %esi
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT@GOTPCREL(%rip), %rdx
	movb	(%rdx), %dl
	shll	%cl, %esi
	movl	%edx, %ecx
	shll	%cl, %edi
	orl	%esi, %edi
	movl	(%rbx), %esi
	shll	%cl, %esi
	notl	%edi
	andl	%eax, %edi
	orl	%edi, %esi
	movl	(%r13), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL4@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	_jiffies@GOTPCREL(%rip), %r15
	movq	(%r15), %r13
	movl	$100, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %rbx
	addq	%r13, %rbx
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_10
## %bb.7:
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	testl	%eax, (%r13)
	jne	LBB0_10
## %bb.9:                               ##   in Loop: Header=BB0_8 Depth=1
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	jne	LBB0_8
LBB0_10:
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	jne	LBB0_32
## %bb.11:
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movq	(%r15), %r13
	movl	$100, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %rbx
	addq	%r13, %rbx
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_15
## %bb.12:
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	testl	%eax, (%r13)
	je	LBB0_15
## %bb.14:                              ##   in Loop: Header=BB0_13 Depth=1
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	jne	LBB0_13
LBB0_15:
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	jne	LBB0_32
## %bb.16:
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	(%r15), %r13
	movl	$100, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %rbx
	addq	%r13, %rbx
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_20
## %bb.17:
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	testl	%eax, (%r13)
	jne	LBB0_20
## %bb.19:                              ##   in Loop: Header=BB0_18 Depth=1
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	jne	LBB0_18
LBB0_20:
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	jne	LBB0_32
## %bb.21:
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_padctl_writel
	movq	(%r15), %r13
	movl	$100, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %rbx
	addq	%r13, %rbx
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_25
## %bb.22:
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE@GOTPCREL(%rip), %r13
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	testl	%eax, (%r13)
	jne	LBB0_25
## %bb.24:                              ##   in Loop: Header=BB0_23 Depth=1
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	jne	LBB0_23
LBB0_25:
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	jne	LBB0_32
## %bb.26:
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movq	(%r15), %r13
	movl	$100, %edi
	callq	_msecs_to_jiffies
	movq	%rax, %rbx
	addq	%r13, %rbx
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	je	LBB0_30
## %bb.27:
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE@GOTPCREL(%rip), %r13
LBB0_28:                                ## =>This Inner Loop Header: Depth=1
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	testl	%eax, (%r13)
	je	LBB0_30
## %bb.29:                              ##   in Loop: Header=BB0_28 Depth=1
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_before
	testq	%rax, %rax
	jne	LBB0_28
LBB0_30:
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	callq	_time_after_eq
	testq	%rax, %rax
	je	LBB0_31
LBB0_32:
	movq	_ETIMEDOUT@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	movl	12(%r14), %edi
	callq	_reset_control_assert
	jmp	LBB0_33
LBB0_3:
	movl	%eax, %ebx
	jmp	LBB0_34
LBB0_5:
	movl	%eax, %ebx
LBB0_33:
	movl	8(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_34:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_31:
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_tegra210_sata_pll_hw_control_enable
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL1@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movq	_XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r15), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_padctl_readl
	movq	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r13), %edx
	movq	%r12, %rdi
	callq	_padctl_writel
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	xorl	%eax, %eax
	callq	_tegra210_sata_pll_hw_sequence_start
	incq	(%r14)
	jmp	LBB0_34
	.cfi_endproc
                                        ## -- End function
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL2,4,2 ## @XUSB_PADCTL_UPHY_PLL_S0_CTL2
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL5,4,2 ## @XUSB_PADCTL_UPHY_PLL_S0_CTL5
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL1,4,2 ## @XUSB_PADCTL_UPHY_PLL_S0_CTL1
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL8,4,2 ## @XUSB_PADCTL_UPHY_PLL_S0_CTL8
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL4,4,2 ## @XUSB_PADCTL_UPHY_PLL_S0_CTL4
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE
	.comm	_ETIMEDOUT,4,2                  ## @ETIMEDOUT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE,4,2 ## @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE
	.no_dead_strip	_tegra210_sata_uphy_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra210_sata_uphy_enable
_tegra210_sata_uphy_enable:             ; @tegra210_sata_uphy_enable
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x20, x0
	ldr	w0, [x0]
	bl	_to_sata_pad
	mov	x19, x0
	ldr	x8, [x0]
	cmp	x8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	w22, #0
LBB0_2:
	add	x8, x8, #1
	str	x8, [x19]
	b	LBB0_34
LBB0_3:
	ldr	w0, [x19, #8]
	bl	_clk_prepare_enable
	tbnz	w0, #31, LBB0_31
; %bb.4:
	ldr	w0, [x19, #12]
	bl	_reset_control_deassert
	tbnz	w0, #31, LBB0_32
; %bb.5:
Lloh0:
	adrp	x22, _XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPAGE
Lloh1:
	ldr	x22, [x22, _XUSB_PADCTL_UPHY_PLL_S0_CTL2@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
Lloh2:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT@GOTPAGE
Lloh6:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
Lloh8:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL@GOTPAGE
Lloh9:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	lsl	w9, w10, w9
	orr	w1, w8, w9
	ldr	w2, [x22]
	mov	x0, x20
	bl	_padctl_writel
Lloh11:
	adrp	x23, _XUSB_PADCTL_UPHY_PLL_S0_CTL5@GOTPAGE
Lloh12:
	ldr	x23, [x23, _XUSB_PADCTL_UPHY_PLL_S0_CTL5@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh13:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT@GOTPAGE
Lloh17:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
Lloh19:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL@GOTPAGE
Lloh20:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL@GOTPAGEOFF]
Lloh21:
	ldr	w10, [x10]
	lsl	w9, w10, w9
	orr	w1, w8, w9
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
Lloh22:
	adrp	x23, _XUSB_PADCTL_UPHY_PLL_S0_CTL1@GOTPAGE
Lloh23:
	ldr	x23, [x23, _XUSB_PADCTL_UPHY_PLL_S0_CTL1@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh24:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD@GOTPAGE
Lloh25:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
Lloh27:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD@GOTPAGE
Lloh28:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x22]
	mov	x0, x20
	bl	_padctl_writel
Lloh30:
	adrp	x24, _XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPAGE
Lloh31:
	ldr	x24, [x24, _XUSB_PADCTL_UPHY_PLL_S0_CTL8@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
Lloh32:
	adrp	x27, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD@GOTPAGE
Lloh33:
	ldr	x27, [x27, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD@GOTPAGEOFF]
	ldr	w8, [x27]
	orr	w1, w8, w0
	ldr	w2, [x24]
	mov	x0, x20
	bl	_padctl_writel
Lloh34:
	adrp	x28, _XUSB_PADCTL_UPHY_PLL_S0_CTL4@GOTPAGE
Lloh35:
	ldr	x28, [x28, _XUSB_PADCTL_UPHY_PLL_S0_CTL4@GOTPAGEOFF]
	ldr	w1, [x28]
	mov	x0, x20
	bl	_padctl_readl
Lloh36:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK@GOTPAGE
Lloh37:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK@GOTPAGEOFF]
Lloh38:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT@GOTPAGE
Lloh39:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh42:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK@GOTPAGE
Lloh43:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
Lloh45:
	adrp	x11, _XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT@GOTPAGE
Lloh46:
	ldr	x11, [x11, _XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT@GOTPAGEOFF]
Lloh47:
	ldr	w11, [x11]
	lsl	w10, w10, w11
	orr	w8, w10, w8
	bic	w8, w0, w8
Lloh48:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN@GOTPAGE
Lloh49:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
	orr	w8, w8, w10
Lloh51:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL@GOTPAGE
Lloh52:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL@GOTPAGEOFF]
Lloh53:
	adrp	x11, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL@GOTPAGE
Lloh54:
	ldr	x11, [x11, _XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL@GOTPAGEOFF]
	cmp	w21, #0
	csel	x10, x10, x11, eq
	ldr	w10, [x10]
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh55:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN@GOTPAGE
Lloh56:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	bic	w1, w8, w9
	ldr	w2, [x28]
Lloh58:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL@GOTPAGE
Lloh59:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL@GOTPAGEOFF]
Lloh60:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL@GOTPAGE
Lloh61:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL@GOTPAGEOFF]
	csel	x21, x8, x9, eq
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh62:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK@GOTPAGE
Lloh63:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
Lloh65:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT@GOTPAGE
Lloh66:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT@GOTPAGEOFF]
Lloh67:
	ldr	w9, [x9]
Lloh68:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK@GOTPAGE
Lloh69:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK@GOTPAGEOFF]
	lsl	w8, w8, w9
Lloh70:
	ldr	w9, [x10]
Lloh71:
	adrp	x10, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT@GOTPAGE
Lloh72:
	ldr	x10, [x10, _XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT@GOTPAGEOFF]
Lloh73:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w8, w9, w8
	bic	w8, w0, w8
	ldr	w9, [x21]
	lsl	w9, w9, w10
	orr	w1, w9, w8
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh74:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ@GOTPAGE
Lloh75:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ@GOTPAGEOFF]
Lloh76:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh77:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK@GOTPAGE
Lloh78:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
Lloh80:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT@GOTPAGE
Lloh81:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT@GOTPAGEOFF]
Lloh82:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w1, w0, w8
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	w1, [x28]
	mov	x0, x20
	bl	_padctl_readl
Lloh83:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN@GOTPAGE
Lloh84:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN@GOTPAGEOFF]
Lloh85:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x28]
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
Lloh86:
	adrp	x25, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN@GOTPAGE
Lloh87:
	ldr	x25, [x25, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN@GOTPAGEOFF]
	ldr	w8, [x25]
	orr	w1, w8, w0
	ldr	w2, [x22]
	mov	x0, x20
	bl	_padctl_writel
Lloh88:
	adrp	x28, _jiffies@GOTPAGE
Lloh89:
	ldr	x28, [x28, _jiffies@GOTPAGEOFF]
	ldr	x21, [x28]
	mov	w0, #100
	bl	_msecs_to_jiffies
	add	x21, x0, x21
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_9
; %bb.6:
Lloh90:
	adrp	x26, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE@GOTPAGE
Lloh91:
	ldr	x26, [x26, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE@GOTPAGEOFF]
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x26]
	tst	w8, w0
	b.ne	LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=1
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbnz	x0, LBB0_7
LBB0_9:
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_after_eq
	cbnz	x0, LBB0_30
; %bb.10:
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x25]
	bic	w1, w0, w8
	ldr	w2, [x22]
	mov	x0, x20
	bl	_padctl_writel
	ldr	x21, [x28]
	mov	w0, #100
	bl	_msecs_to_jiffies
	add	x21, x0, x21
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_14
; %bb.11:
Lloh92:
	adrp	x25, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE@GOTPAGE
Lloh93:
	ldr	x25, [x25, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE@GOTPAGEOFF]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x25]
	tst	w8, w0
	b.eq	LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbnz	x0, LBB0_12
LBB0_14:
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_after_eq
	cbnz	x0, LBB0_30
; %bb.15:
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh94:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE@GOTPAGE
Lloh95:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE@GOTPAGEOFF]
Lloh96:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
	ldr	x21, [x28]
	mov	w0, #100
	bl	_msecs_to_jiffies
	add	x21, x0, x21
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_19
; %bb.16:
Lloh97:
	adrp	x25, _XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS@GOTPAGE
Lloh98:
	ldr	x25, [x25, _XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS@GOTPAGEOFF]
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x25]
	tst	w8, w0
	b.ne	LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbnz	x0, LBB0_17
LBB0_19:
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_after_eq
	cbnz	x0, LBB0_30
; %bb.20:
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
Lloh99:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN@GOTPAGE
Lloh100:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN@GOTPAGEOFF]
	mov	x26, x8
	ldr	w8, [x8]
Lloh101:
	adrp	x9, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN@GOTPAGE
Lloh102:
	ldr	x9, [x9, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN@GOTPAGEOFF]
Lloh103:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w1, w8, w9
	ldr	w2, [x24]
	mov	x0, x20
	bl	_padctl_writel
	ldr	x21, [x28]
	mov	w0, #100
	bl	_msecs_to_jiffies
	add	x21, x0, x21
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_24
; %bb.21:
Lloh104:
	adrp	x25, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE@GOTPAGE
Lloh105:
	ldr	x25, [x25, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE@GOTPAGEOFF]
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x25]
	tst	w8, w0
	b.ne	LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbnz	x0, LBB0_22
LBB0_24:
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_after_eq
	cbnz	x0, LBB0_30
; %bb.25:
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x26]
	bic	w1, w0, w8
	ldr	w2, [x24]
	mov	x0, x20
	bl	_padctl_writel
	ldr	x21, [x28]
	mov	w0, #100
	bl	_msecs_to_jiffies
	add	x21, x0, x21
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbz	x0, LBB0_29
; %bb.26:
Lloh106:
	adrp	x25, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE@GOTPAGE
Lloh107:
	ldr	x25, [x25, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE@GOTPAGEOFF]
LBB0_27:                                ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x25]
	tst	w8, w0
	b.eq	LBB0_29
; %bb.28:                               ;   in Loop: Header=BB0_27 Depth=1
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_before
	cbnz	x0, LBB0_27
LBB0_29:
	ldr	x0, [x28]
	mov	x1, x21
	bl	_time_after_eq
	cbz	x0, LBB0_35
LBB0_30:
Lloh108:
	adrp	x8, _ETIMEDOUT@GOTPAGE
Lloh109:
	ldr	x8, [x8, _ETIMEDOUT@GOTPAGEOFF]
Lloh110:
	ldr	w8, [x8]
	neg	w22, w8
	ldr	w0, [x19, #12]
	bl	_reset_control_assert
	b	LBB0_33
LBB0_31:
	mov	x22, x0
	b	LBB0_34
LBB0_32:
	mov	x22, x0
LBB0_33:
	ldr	w0, [x19, #8]
	bl	_clk_disable_unprepare
LBB0_34:
	mov	x0, x22
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_35:
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
Lloh111:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN@GOTPAGE
Lloh112:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN@GOTPAGEOFF]
Lloh113:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x24]
	mov	x0, x20
	bl	_padctl_writel
	bl	_tegra210_sata_pll_hw_control_enable
	ldr	w1, [x23]
	mov	x0, x20
	bl	_padctl_readl
Lloh114:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD@GOTPAGE
Lloh115:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD@GOTPAGEOFF]
Lloh116:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x23]
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x22]
	mov	x0, x20
	bl	_padctl_readl
Lloh117:
	adrp	x8, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD@GOTPAGE
Lloh118:
	ldr	x8, [x8, _XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD@GOTPAGEOFF]
Lloh119:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x22]
	mov	x0, x20
	bl	_padctl_writel
	ldr	w1, [x24]
	mov	x0, x20
	bl	_padctl_readl
	ldr	w8, [x27]
	bic	w1, w0, w8
	ldr	w2, [x24]
	mov	x0, x20
	bl	_padctl_writel
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
	bl	_tegra210_sata_pll_hw_sequence_start
	mov	w22, #0
	ldr	x8, [x19]
	b	LBB0_2
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh40
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGot	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGot	Lloh99, Lloh100
	.loh AdrpLdrGot	Lloh104, Lloh105
	.loh AdrpLdrGot	Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.cfi_endproc
                                        ; -- End function
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL2,4,2 ; @XUSB_PADCTL_UPHY_PLL_S0_CTL2
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL5,4,2 ; @XUSB_PADCTL_UPHY_PLL_S0_CTL5
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL1,4,2 ; @XUSB_PADCTL_UPHY_PLL_S0_CTL1
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL8,4,2 ; @XUSB_PADCTL_UPHY_PLL_S0_CTL8
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD
	.comm	_XUSB_PADCTL_UPHY_PLL_S0_CTL4,4,2 ; @XUSB_PADCTL_UPHY_PLL_S0_CTL4
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE
	.comm	_ETIMEDOUT,4,2                  ; @ETIMEDOUT
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN
	.comm	_XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE,4,2 ; @XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE
	.no_dead_strip	_tegra210_sata_uphy_enable
.subsections_via_symbols
