	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_e1000e_get_bus_info_pcie       ## -- Begin function e1000e_get_bus_info_pcie
	.p2align	4, 0x90
_e1000e_get_bus_info_pcie:              ## @e1000e_get_bus_info_pcie
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	(%rdi), %rax
	movq	(%rax), %rdi
	movl	(%rdi), %esi
	testl	%esi, %esi
	je	LBB0_1
## %bb.2:
	movq	_PCIE_LINK_STATUS@GOTPCREL(%rip), %rax
	addl	(%rax), %esi
	leaq	-12(%rbp), %rdx
	callq	_pci_read_config_word
	movq	_PCIE_LINK_WIDTH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	-12(%rbp), %eax
	movq	_PCIE_LINK_WIDTH_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	jmp	LBB0_3
LBB0_1:
	movq	_e1000_bus_width_unknown@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_3:
	movl	%eax, 8(%rbx)
	movq	%rbx, %rdi
	callq	*16(%rbx)
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_e1000_bus_width_unknown,4,2    ## @e1000_bus_width_unknown
	.comm	_PCIE_LINK_STATUS,4,2           ## @PCIE_LINK_STATUS
	.comm	_PCIE_LINK_WIDTH_MASK,4,2       ## @PCIE_LINK_WIDTH_MASK
	.comm	_PCIE_LINK_WIDTH_SHIFT,4,2      ## @PCIE_LINK_WIDTH_SHIFT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_e1000e_get_bus_info_pcie       ; -- Begin function e1000e_get_bus_info_pcie
	.p2align	2
_e1000e_get_bus_info_pcie:              ; @e1000e_get_bus_info_pcie
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x8, [x0]
	ldr	x0, [x8]
	ldr	w8, [x0]
	cbz	w8, LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, _PCIE_LINK_STATUS@GOTPAGE
Lloh1:
	ldr	x9, [x9, _PCIE_LINK_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	add	w1, w9, w8
	add	x2, sp, #12
	bl	_pci_read_config_word
	ldr	w8, [sp, #12]
Lloh3:
	adrp	x9, _PCIE_LINK_WIDTH_MASK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PCIE_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	and	w8, w9, w8
Lloh6:
	adrp	x9, _PCIE_LINK_WIDTH_SHIFT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PCIE_LINK_WIDTH_SHIFT@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	asr	w8, w8, w9
	b	LBB0_3
LBB0_2:
Lloh9:
	adrp	x8, _e1000_bus_width_unknown@GOTPAGE
Lloh10:
	ldr	x8, [x8, _e1000_bus_width_unknown@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
LBB0_3:
	str	w8, [x19, #8]
	ldr	x8, [x19, #16]
	mov	x0, x19
	blr	x8
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_e1000_bus_width_unknown,4,2    ; @e1000_bus_width_unknown
	.comm	_PCIE_LINK_STATUS,4,2           ; @PCIE_LINK_STATUS
	.comm	_PCIE_LINK_WIDTH_MASK,4,2       ; @PCIE_LINK_WIDTH_MASK
	.comm	_PCIE_LINK_WIDTH_SHIFT,4,2      ; @PCIE_LINK_WIDTH_SHIFT
.subsections_via_symbols
