	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos4x12_isol
_exynos4x12_isol:                       ## @exynos4x12_isol
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	(%rdi), %rax
	movl	(%rax), %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_1
## %bb.2:
	movq	8(%rdi), %rcx
	cltq
	leaq	l_switch.table.exynos4x12_isol(%rip), %rdx
	movq	(%rdx,%rax,8), %rdi
	leaq	l_switch.table.exynos4x12_isol.1(%rip), %rdx
	movq	(%rdx,%rax,8), %rax
	movl	(%rax), %edx
	movl	(%rdi), %eax
	movl	(%rcx), %edi
	xorl	%ecx, %ecx
	testl	%esi, %esi
	cmovel	%edx, %ecx
	movl	%eax, %esi
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
LBB0_1:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EXYNOS_4x12_USB_ISOL_OFFSET,4,2 ## @EXYNOS_4x12_USB_ISOL_OFFSET
	.comm	_EXYNOS_4x12_USB_ISOL_OTG,4,2   ## @EXYNOS_4x12_USB_ISOL_OTG
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET,4,2 ## @EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC0,4,2 ## @EXYNOS_4x12_USB_ISOL_HSIC0
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET,4,2 ## @EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC1,4,2 ## @EXYNOS_4x12_USB_ISOL_HSIC1
	.no_dead_strip	_exynos4x12_isol
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.exynos4x12_isol
l_switch.table.exynos4x12_isol:
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET
	.quad	_EXYNOS_4x12_USB_ISOL_OFFSET
	.quad	_EXYNOS_4x12_USB_ISOL_OFFSET

	.p2align	3                               ## @switch.table.exynos4x12_isol.1
l_switch.table.exynos4x12_isol.1:
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC1
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC0
	.quad	_EXYNOS_4x12_USB_ISOL_OTG
	.quad	_EXYNOS_4x12_USB_ISOL_OTG

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos4x12_isol
_exynos4x12_isol:                       ; @exynos4x12_isol
	.cfi_startproc
; %bb.0:
	ldr	x8, [x0]
	ldr	w8, [x8]
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_2
; %bb.1:
	sbfiz	x8, x8, #3, #32
Lloh0:
	adrp	x9, l_switch.table.exynos4x12_isol@PAGE
Lloh1:
	add	x9, x9, l_switch.table.exynos4x12_isol@PAGEOFF
	ldr	x9, [x9, x8]
Lloh2:
	adrp	x10, l_switch.table.exynos4x12_isol.1@PAGE
Lloh3:
	add	x10, x10, l_switch.table.exynos4x12_isol.1@PAGEOFF
	ldr	x11, [x0, #8]
	ldr	x8, [x10, x8]
	ldr	w2, [x8]
	ldr	w8, [x9]
	ldr	w0, [x11]
	cmp	w1, #0
	csel	w3, w2, wzr, eq
	mov	x1, x8
	b	_regmap_update_bits
LBB0_2:
	ret
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_EXYNOS_4x12_USB_ISOL_OFFSET,4,2 ; @EXYNOS_4x12_USB_ISOL_OFFSET
	.comm	_EXYNOS_4x12_USB_ISOL_OTG,4,2   ; @EXYNOS_4x12_USB_ISOL_OTG
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET,4,2 ; @EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC0,4,2 ; @EXYNOS_4x12_USB_ISOL_HSIC0
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET,4,2 ; @EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET
	.comm	_EXYNOS_4x12_USB_ISOL_HSIC1,4,2 ; @EXYNOS_4x12_USB_ISOL_HSIC1
	.no_dead_strip	_exynos4x12_isol
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.exynos4x12_isol
l_switch.table.exynos4x12_isol:
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET
	.quad	_EXYNOS_4x12_USB_ISOL_OFFSET
	.quad	_EXYNOS_4x12_USB_ISOL_OFFSET

	.p2align	3                               ; @switch.table.exynos4x12_isol.1
l_switch.table.exynos4x12_isol.1:
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC1
	.quad	_EXYNOS_4x12_USB_ISOL_HSIC0
	.quad	_EXYNOS_4x12_USB_ISOL_OTG
	.quad	_EXYNOS_4x12_USB_ISOL_OTG

.subsections_via_symbols
