	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath10k_pci_warm_reset_clear_lf
_ath10k_pci_warm_reset_clear_lf:        ## @ath10k_pci_warm_reset_clear_lf
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_RTC_SOC_BASE_ADDRESS@GOTPCREL(%rip), %r14
	movq	_SOC_LF_TIMER_CONTROL0_ADDRESS@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	addq	(%r14), %rsi
	callq	_ath10k_pci_read32
	movq	(%r15), %rsi
	addq	(%r14), %rsi
	movq	_SOC_LF_TIMER_CONTROL0_ENABLE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath10k_pci_write32             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RTC_SOC_BASE_ADDRESS,8,3       ## @RTC_SOC_BASE_ADDRESS
	.comm	_SOC_LF_TIMER_CONTROL0_ADDRESS,8,3 ## @SOC_LF_TIMER_CONTROL0_ADDRESS
	.comm	_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,4,2 ## @SOC_LF_TIMER_CONTROL0_ENABLE_MASK
	.no_dead_strip	_ath10k_pci_warm_reset_clear_lf
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath10k_pci_warm_reset_clear_lf
_ath10k_pci_warm_reset_clear_lf:        ; @ath10k_pci_warm_reset_clear_lf
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _RTC_SOC_BASE_ADDRESS@GOTPAGE
Lloh1:
	ldr	x20, [x20, _RTC_SOC_BASE_ADDRESS@GOTPAGEOFF]
	ldr	x8, [x20]
Lloh2:
	adrp	x21, _SOC_LF_TIMER_CONTROL0_ADDRESS@GOTPAGE
Lloh3:
	ldr	x21, [x21, _SOC_LF_TIMER_CONTROL0_ADDRESS@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_ath10k_pci_read32
	ldr	x8, [x20]
	ldr	x9, [x21]
Lloh4:
	adrp	x10, _SOC_LF_TIMER_CONTROL0_ENABLE_MASK@GOTPAGE
Lloh5:
	ldr	x10, [x10, _SOC_LF_TIMER_CONTROL0_ENABLE_MASK@GOTPAGEOFF]
	add	x1, x9, x8
Lloh6:
	ldr	w8, [x10]
	bic	w2, w0, w8
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ath10k_pci_write32
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_RTC_SOC_BASE_ADDRESS,8,3       ; @RTC_SOC_BASE_ADDRESS
	.comm	_SOC_LF_TIMER_CONTROL0_ADDRESS,8,3 ; @SOC_LF_TIMER_CONTROL0_ADDRESS
	.comm	_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,4,2 ; @SOC_LF_TIMER_CONTROL0_ENABLE_MASK
	.no_dead_strip	_ath10k_pci_warm_reset_clear_lf
.subsections_via_symbols
