	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function atmel_gpio_irq_set_type
_atmel_gpio_irq_set_type:               ## @atmel_gpio_irq_set_type
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %rbx
	callq	_irq_data_get_irq_chip_data
	movq	%rax, %r13
	movq	(%rax), %rax
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	(%rbx), %rcx
	movq	(%rax,%rcx,8), %r14
	movq	_ATMEL_PIO_MSKR@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	(%r14), %ebx
	movl	4(%r14), %edi
	callq	_BIT
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_atmel_gpio_write
	movl	(%r14), %esi
	movq	_ATMEL_PIO_CFGR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, -48(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	callq	_atmel_gpio_read
	addl	$-129, %r15d
	cmpl	$5, %r15d
	jae	LBB0_1
## %bb.2:
	movl	%eax, %r12d
	movq	_ATMEL_PIO_CFGR_EVTSEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r12d
	movslq	%r15d, %rax
	leaq	l_switch.table.atmel_gpio_irq_set_type(%rip), %rcx
	movq	(%rcx,%rax,8), %rcx
	leaq	l_switch.table.atmel_gpio_irq_set_type.1(%rip), %rdx
	movq	%rbx, %r15
	movq	(%rdx,%rax,8), %rbx
	movl	(%rcx), %esi
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_irq_set_handler_locked
	orl	(%rbx), %r12d
	movl	(%r14), %esi
	movl	(%r15), %edx
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r12d, %ecx
	callq	_atmel_gpio_write
	xorl	%eax, %eax
	jmp	LBB0_3
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_3:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ATMEL_PIO_MSKR,4,2             ## @ATMEL_PIO_MSKR
	.comm	_ATMEL_PIO_CFGR,4,2             ## @ATMEL_PIO_CFGR
	.comm	_ATMEL_PIO_CFGR_EVTSEL_MASK,4,2 ## @ATMEL_PIO_CFGR_EVTSEL_MASK
	.comm	_handle_edge_irq,4,2            ## @handle_edge_irq
	.comm	_ATMEL_PIO_CFGR_EVTSEL_RISING,4,2 ## @ATMEL_PIO_CFGR_EVTSEL_RISING
	.comm	_ATMEL_PIO_CFGR_EVTSEL_FALLING,4,2 ## @ATMEL_PIO_CFGR_EVTSEL_FALLING
	.comm	_ATMEL_PIO_CFGR_EVTSEL_BOTH,4,2 ## @ATMEL_PIO_CFGR_EVTSEL_BOTH
	.comm	_handle_level_irq,4,2           ## @handle_level_irq
	.comm	_ATMEL_PIO_CFGR_EVTSEL_LOW,4,2  ## @ATMEL_PIO_CFGR_EVTSEL_LOW
	.comm	_ATMEL_PIO_CFGR_EVTSEL_HIGH,4,2 ## @ATMEL_PIO_CFGR_EVTSEL_HIGH
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_atmel_gpio_irq_set_type
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.atmel_gpio_irq_set_type
l_switch.table.atmel_gpio_irq_set_type:
	.quad	_handle_level_irq
	.quad	_handle_level_irq
	.quad	_handle_edge_irq
	.quad	_handle_edge_irq
	.quad	_handle_edge_irq

	.p2align	3                               ## @switch.table.atmel_gpio_irq_set_type.1
l_switch.table.atmel_gpio_irq_set_type.1:
	.quad	_ATMEL_PIO_CFGR_EVTSEL_LOW
	.quad	_ATMEL_PIO_CFGR_EVTSEL_HIGH
	.quad	_ATMEL_PIO_CFGR_EVTSEL_RISING
	.quad	_ATMEL_PIO_CFGR_EVTSEL_FALLING
	.quad	_ATMEL_PIO_CFGR_EVTSEL_BOTH

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function atmel_gpio_irq_set_type
_atmel_gpio_irq_set_type:               ; @atmel_gpio_irq_set_type
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x1
	mov	x20, x0
	bl	_irq_data_get_irq_chip_data
	mov	x19, x0
	ldr	x8, [x0]
	ldr	x9, [x20]
	ldr	x24, [x8, x9, lsl #3]
Lloh0:
	adrp	x8, _ATMEL_PIO_MSKR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ATMEL_PIO_MSKR@GOTPAGEOFF]
Lloh2:
	ldr	w22, [x8]
	ldp	w23, w0, [x24]
	bl	_BIT
	mov	x3, x0
	mov	x0, x19
	mov	x1, x23
	mov	x2, x22
	bl	_atmel_gpio_write
	ldr	w1, [x24]
Lloh3:
	adrp	x22, _ATMEL_PIO_CFGR@GOTPAGE
Lloh4:
	ldr	x22, [x22, _ATMEL_PIO_CFGR@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_atmel_gpio_read
	sub	w8, w21, #129
	cmp	w8, #5
	b.hs	LBB0_2
; %bb.1:
Lloh5:
	adrp	x9, _ATMEL_PIO_CFGR_EVTSEL_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _ATMEL_PIO_CFGR_EVTSEL_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	sbfiz	x8, x8, #3, #32
Lloh8:
	adrp	x10, l_switch.table.atmel_gpio_irq_set_type@PAGE
Lloh9:
	add	x10, x10, l_switch.table.atmel_gpio_irq_set_type@PAGEOFF
	ldr	x10, [x10, x8]
	bic	w21, w0, w9
Lloh10:
	adrp	x9, l_switch.table.atmel_gpio_irq_set_type.1@PAGE
Lloh11:
	add	x9, x9, l_switch.table.atmel_gpio_irq_set_type.1@PAGEOFF
	ldr	x23, [x9, x8]
	ldr	w1, [x10]
	mov	x0, x20
	bl	_irq_set_handler_locked
	ldr	w8, [x23]
	orr	w3, w8, w21
	ldr	w1, [x24]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_atmel_gpio_write
	mov	w0, #0
	b	LBB0_3
LBB0_2:
Lloh12:
	adrp	x8, _EINVAL@GOTPAGE
Lloh13:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_3:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_ATMEL_PIO_MSKR,4,2             ; @ATMEL_PIO_MSKR
	.comm	_ATMEL_PIO_CFGR,4,2             ; @ATMEL_PIO_CFGR
	.comm	_ATMEL_PIO_CFGR_EVTSEL_MASK,4,2 ; @ATMEL_PIO_CFGR_EVTSEL_MASK
	.comm	_handle_edge_irq,4,2            ; @handle_edge_irq
	.comm	_ATMEL_PIO_CFGR_EVTSEL_RISING,4,2 ; @ATMEL_PIO_CFGR_EVTSEL_RISING
	.comm	_ATMEL_PIO_CFGR_EVTSEL_FALLING,4,2 ; @ATMEL_PIO_CFGR_EVTSEL_FALLING
	.comm	_ATMEL_PIO_CFGR_EVTSEL_BOTH,4,2 ; @ATMEL_PIO_CFGR_EVTSEL_BOTH
	.comm	_handle_level_irq,4,2           ; @handle_level_irq
	.comm	_ATMEL_PIO_CFGR_EVTSEL_LOW,4,2  ; @ATMEL_PIO_CFGR_EVTSEL_LOW
	.comm	_ATMEL_PIO_CFGR_EVTSEL_HIGH,4,2 ; @ATMEL_PIO_CFGR_EVTSEL_HIGH
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_atmel_gpio_irq_set_type
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.atmel_gpio_irq_set_type
l_switch.table.atmel_gpio_irq_set_type:
	.quad	_handle_level_irq
	.quad	_handle_level_irq
	.quad	_handle_edge_irq
	.quad	_handle_edge_irq
	.quad	_handle_edge_irq

	.p2align	3                               ; @switch.table.atmel_gpio_irq_set_type.1
l_switch.table.atmel_gpio_irq_set_type.1:
	.quad	_ATMEL_PIO_CFGR_EVTSEL_LOW
	.quad	_ATMEL_PIO_CFGR_EVTSEL_HIGH
	.quad	_ATMEL_PIO_CFGR_EVTSEL_RISING
	.quad	_ATMEL_PIO_CFGR_EVTSEL_FALLING
	.quad	_ATMEL_PIO_CFGR_EVTSEL_BOTH

.subsections_via_symbols
