	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlx5_fpga_conn_connect
_mlx5_fpga_conn_connect:                ## @mlx5_fpga_conn_connect
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %r14
	movq	_fpga_qpc@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	movq	_state@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	_MLX5_FPGA_QPC_STATE_ACTIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	callq	_MLX5_SET
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movl	4(%rbx), %esi
	movq	_MLX5_FPGA_QPC_STATE@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%rbx, %rcx
	callq	_mlx5_fpga_modify_qp
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %r15d
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_mlx5_fpga_err
	jmp	LBB0_16
LBB0_2:
	movq	%rbx, %rdi
	callq	_mlx5_fpga_conn_reset_qp
	testl	%eax, %eax
	je	LBB0_5
## %bb.3:
	movl	%eax, %r15d
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_4
LBB0_5:
	movq	%rbx, %rdi
	callq	_mlx5_fpga_conn_init_qp
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %r15d
	leaq	L_.str.2(%rip), %rsi
LBB0_4:
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_mlx5_fpga_err
LBB0_14:
	movq	_fpga_qpc@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	(%rbx), %esi
	movl	(%r13), %edx
	movq	_MLX5_FPGA_QPC_STATE_INIT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	callq	_MLX5_SET
	movq	8(%rbx), %rax
	movl	(%rax), %edi
	movl	4(%rbx), %esi
	movl	(%r12), %edx
	movq	%rbx, %rcx
	callq	_mlx5_fpga_modify_qp
	testl	%eax, %eax
	je	LBB0_16
## %bb.15:
	leaq	L_.str.5(%rip), %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_mlx5_fpga_err
LBB0_16:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movl	$1, 16(%rbx)
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	callq	_mlx5_fpga_conn_post_recv_buf
	testl	%eax, %eax
	je	LBB0_8
## %bb.9:
	movq	%rbx, %rdi
	callq	_mlx5_fpga_conn_rtr_qp
	testl	%eax, %eax
	je	LBB0_11
## %bb.10:
	movl	%eax, %r15d
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_13
LBB0_11:
	movq	%rbx, %rdi
	callq	_mlx5_fpga_conn_rts_qp
	testl	%eax, %eax
	je	LBB0_17
## %bb.12:
	movl	%eax, %r15d
	leaq	L_.str.4(%rip), %rsi
LBB0_13:
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_mlx5_fpga_err
	movq	%rbx, %rdi
	callq	_mlx5_fpga_conn_free_recv_bufs
	jmp	LBB0_14
LBB0_17:
	xorl	%r15d, %r15d
	jmp	LBB0_16
	.cfi_endproc
                                        ## -- End function
	.comm	_fpga_qpc,4,2                   ## @fpga_qpc
	.comm	_state,4,2                      ## @state
	.comm	_MLX5_FPGA_QPC_STATE_ACTIVE,4,2 ## @MLX5_FPGA_QPC_STATE_ACTIVE
	.comm	_MLX5_FPGA_QPC_STATE,4,2        ## @MLX5_FPGA_QPC_STATE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to activate FPGA RC QP: %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to change QP state to reset\n"

L_.str.2:                               ## @.str.2
	.asciz	"Failed to modify QP from RESET to INIT\n"

L_.str.3:                               ## @.str.3
	.asciz	"Failed to change QP state from INIT to RTR\n"

L_.str.4:                               ## @.str.4
	.asciz	"Failed to change QP state from RTR to RTS\n"

	.comm	_MLX5_FPGA_QPC_STATE_INIT,4,2   ## @MLX5_FPGA_QPC_STATE_INIT
L_.str.5:                               ## @.str.5
	.asciz	"Failed to revert FPGA QP to INIT\n"

	.no_dead_strip	_mlx5_fpga_conn_connect
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlx5_fpga_conn_connect
_mlx5_fpga_conn_connect:                ; @mlx5_fpga_conn_connect
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	ldr	x19, [x0, #8]
Lloh0:
	adrp	x22, _fpga_qpc@GOTPAGE
Lloh1:
	ldr	x22, [x22, _fpga_qpc@GOTPAGEOFF]
	ldr	w0, [x22]
	ldr	w1, [x20]
Lloh2:
	adrp	x23, _state@GOTPAGE
Lloh3:
	ldr	x23, [x23, _state@GOTPAGEOFF]
	ldr	w2, [x23]
Lloh4:
	adrp	x8, _MLX5_FPGA_QPC_STATE_ACTIVE@GOTPAGE
Lloh5:
	ldr	x8, [x8, _MLX5_FPGA_QPC_STATE_ACTIVE@GOTPAGEOFF]
Lloh6:
	ldr	w3, [x8]
	bl	_MLX5_SET
	ldr	x8, [x20, #8]
	ldr	w0, [x8]
	ldr	w1, [x20, #4]
Lloh7:
	adrp	x24, _MLX5_FPGA_QPC_STATE@GOTPAGE
Lloh8:
	ldr	x24, [x24, _MLX5_FPGA_QPC_STATE@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x3, x20
	bl	_mlx5_fpga_modify_qp
	cbz	w0, LBB0_2
; %bb.1:
	mov	x21, x0
	str	x21, [sp]
Lloh9:
	adrp	x1, l_.str@PAGE
Lloh10:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_9
LBB0_2:
	mov	x0, x20
	bl	_mlx5_fpga_conn_reset_qp
	cbz	w0, LBB0_4
; %bb.3:
	mov	x21, x0
Lloh11:
	adrp	x1, l_.str.1@PAGE
Lloh12:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_6
LBB0_4:
	mov	x0, x20
	bl	_mlx5_fpga_conn_init_qp
	cbz	w0, LBB0_11
; %bb.5:
	mov	x21, x0
Lloh13:
	adrp	x1, l_.str.2@PAGE
Lloh14:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_6:
	mov	x0, x19
	bl	_mlx5_fpga_err
LBB0_7:
	ldr	w0, [x22]
	ldr	w1, [x20]
	ldr	w2, [x23]
Lloh15:
	adrp	x8, _MLX5_FPGA_QPC_STATE_INIT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MLX5_FPGA_QPC_STATE_INIT@GOTPAGEOFF]
Lloh17:
	ldr	w3, [x8]
	bl	_MLX5_SET
	ldr	x8, [x20, #8]
	ldr	w0, [x8]
	ldr	w1, [x20, #4]
	ldr	w2, [x24]
	mov	x3, x20
	bl	_mlx5_fpga_modify_qp
	cbz	w0, LBB0_10
; %bb.8:
Lloh18:
	adrp	x1, l_.str.5@PAGE
Lloh19:
	add	x1, x1, l_.str.5@PAGEOFF
LBB0_9:
	mov	x0, x19
	bl	_mlx5_fpga_err
LBB0_10:
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_11:
	mov	w8, #1
	str	w8, [x20, #16]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	bl	_mlx5_fpga_conn_post_recv_buf
	cbz	w0, LBB0_12
; %bb.13:
	mov	x0, x20
	bl	_mlx5_fpga_conn_rtr_qp
	cbz	w0, LBB0_15
; %bb.14:
	mov	x21, x0
Lloh20:
	adrp	x1, l_.str.3@PAGE
Lloh21:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_17
LBB0_15:
	mov	x0, x20
	bl	_mlx5_fpga_conn_rts_qp
	mov	x21, x0
	cbz	w0, LBB0_10
; %bb.16:
Lloh22:
	adrp	x1, l_.str.4@PAGE
Lloh23:
	add	x1, x1, l_.str.4@PAGEOFF
LBB0_17:
	mov	x0, x19
	bl	_mlx5_fpga_err
	mov	x0, x20
	bl	_mlx5_fpga_conn_free_recv_bufs
	b	LBB0_7
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_fpga_qpc,4,2                   ; @fpga_qpc
	.comm	_state,4,2                      ; @state
	.comm	_MLX5_FPGA_QPC_STATE_ACTIVE,4,2 ; @MLX5_FPGA_QPC_STATE_ACTIVE
	.comm	_MLX5_FPGA_QPC_STATE,4,2        ; @MLX5_FPGA_QPC_STATE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to activate FPGA RC QP: %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to change QP state to reset\n"

l_.str.2:                               ; @.str.2
	.asciz	"Failed to modify QP from RESET to INIT\n"

l_.str.3:                               ; @.str.3
	.asciz	"Failed to change QP state from INIT to RTR\n"

l_.str.4:                               ; @.str.4
	.asciz	"Failed to change QP state from RTR to RTS\n"

	.comm	_MLX5_FPGA_QPC_STATE_INIT,4,2   ; @MLX5_FPGA_QPC_STATE_INIT
l_.str.5:                               ; @.str.5
	.asciz	"Failed to revert FPGA QP to INIT\n"

	.no_dead_strip	_mlx5_fpga_conn_connect
.subsections_via_symbols
