	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlx5_is_fpga_ipsec_rule
_mlx5_is_fpga_ipsec_rule:               ## @mlx5_is_fpga_ipsec_rule
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r15
	movq	%rdx, %r12
	movl	%esi, %r13d
	movq	%rdi, %rbx
	callq	_mlx5_accel_ipsec_device_caps
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	_mlx5_fs_is_outer_ipv6_flow
	movq	_MLX5_MATCH_OUTER_HEADERS@GOTPCREL(%rip), %rcx
	xorl	%r14d, %r14d
	testl	%r13d, (%rcx)
	je	LBB0_12
## %bb.1:
	movl	%eax, %r13d
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_mlx5_fs_is_outer_udp_flow
	testq	%rax, %rax
	jne	LBB0_12
## %bb.2:
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_mlx5_fs_is_outer_tcp_flow
	testq	%rax, %rax
	jne	LBB0_12
## %bb.3:
	movq	%r12, %rdi
	callq	_mlx5_fs_is_vxlan_flow
	testq	%rax, %rax
	jne	LBB0_12
## %bb.4:
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	_mlx5_fs_is_outer_ipv4_flow
	testq	%rax, %rax
	movl	%r13d, %ecx
	jne	LBB0_6
## %bb.5:
	testl	%ecx, %ecx
	je	LBB0_12
LBB0_6:
	movq	_MLX5_ACCEL_IPSEC_CAP_DEVICE@GOTPCREL(%rip), %rax
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	testl	%edx, (%rax)
	je	LBB0_12
## %bb.7:
	movq	_MLX5_ACCEL_IPSEC_CAP_ESP@GOTPCREL(%rip), %rax
	testl	%edx, (%rax)
	jne	LBB0_9
## %bb.8:
	movq	%r12, %rdi
	callq	_mlx5_fs_is_outer_ipsec_flow
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	movl	%r13d, %ecx
	testq	%rax, %rax
	jne	LBB0_12
LBB0_9:
	movq	_MLX5_ACCEL_IPSEC_CAP_IPV6@GOTPCREL(%rip), %rax
	testl	%edx, (%rax)
	jne	LBB0_11
## %bb.10:
	testl	%ecx, %ecx
	jne	LBB0_12
LBB0_11:
	movq	%rbx, %rdi
	movq	%r12, %rsi
	movq	%r15, %rdx
	callq	_validate_fpga_full_mask
	xorl	%r14d, %r14d
	testl	%eax, %eax
	setne	%r14b
LBB0_12:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX5_MATCH_OUTER_HEADERS,4,2   ## @MLX5_MATCH_OUTER_HEADERS
	.comm	_MLX5_ACCEL_IPSEC_CAP_DEVICE,4,2 ## @MLX5_ACCEL_IPSEC_CAP_DEVICE
	.comm	_MLX5_ACCEL_IPSEC_CAP_ESP,4,2   ## @MLX5_ACCEL_IPSEC_CAP_ESP
	.comm	_MLX5_ACCEL_IPSEC_CAP_IPV6,4,2  ## @MLX5_ACCEL_IPSEC_CAP_IPV6
	.no_dead_strip	_mlx5_is_fpga_ipsec_rule
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlx5_is_fpga_ipsec_rule
_mlx5_is_fpga_ipsec_rule:               ; @mlx5_is_fpga_ipsec_rule
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x3
	mov	x20, x2
	mov	x24, x1
	mov	x21, x0
	bl	_mlx5_accel_ipsec_device_caps
	mov	x22, x0
	mov	x0, x21
	mov	x1, x20
	mov	x2, x19
	bl	_mlx5_fs_is_outer_ipv6_flow
Lloh0:
	adrp	x8, _MLX5_MATCH_OUTER_HEADERS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLX5_MATCH_OUTER_HEADERS@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	tst	w8, w24
	b.eq	LBB0_12
; %bb.1:
	mov	x23, x0
	mov	x0, x20
	mov	x1, x19
	bl	_mlx5_fs_is_outer_udp_flow
	cbnz	x0, LBB0_12
; %bb.2:
	mov	x0, x20
	mov	x1, x19
	bl	_mlx5_fs_is_outer_tcp_flow
	cbnz	x0, LBB0_12
; %bb.3:
	mov	x0, x20
	bl	_mlx5_fs_is_vxlan_flow
	cbnz	x0, LBB0_12
; %bb.4:
	mov	x0, x21
	mov	x1, x20
	mov	x2, x19
	bl	_mlx5_fs_is_outer_ipv4_flow
	cbnz	x0, LBB0_6
; %bb.5:
	cbz	w23, LBB0_12
LBB0_6:
Lloh3:
	adrp	x8, _MLX5_ACCEL_IPSEC_CAP_DEVICE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MLX5_ACCEL_IPSEC_CAP_DEVICE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_12
; %bb.7:
Lloh6:
	adrp	x8, _MLX5_ACCEL_IPSEC_CAP_ESP@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MLX5_ACCEL_IPSEC_CAP_ESP@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_11
LBB0_8:
Lloh9:
	adrp	x8, _MLX5_ACCEL_IPSEC_CAP_IPV6@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MLX5_ACCEL_IPSEC_CAP_IPV6@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	tst	w8, w22
	b.ne	LBB0_10
; %bb.9:
	cbnz	w23, LBB0_12
LBB0_10:
	mov	x0, x21
	mov	x1, x20
	mov	x2, x19
	bl	_validate_fpga_full_mask
	cmp	w0, #0
	cset	w0, ne
	b	LBB0_13
LBB0_11:
	mov	x0, x20
	bl	_mlx5_fs_is_outer_ipsec_flow
	cbz	x0, LBB0_8
LBB0_12:
	mov	w0, #0
LBB0_13:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX5_MATCH_OUTER_HEADERS,4,2   ; @MLX5_MATCH_OUTER_HEADERS
	.comm	_MLX5_ACCEL_IPSEC_CAP_DEVICE,4,2 ; @MLX5_ACCEL_IPSEC_CAP_DEVICE
	.comm	_MLX5_ACCEL_IPSEC_CAP_ESP,4,2   ; @MLX5_ACCEL_IPSEC_CAP_ESP
	.comm	_MLX5_ACCEL_IPSEC_CAP_IPV6,4,2  ; @MLX5_ACCEL_IPSEC_CAP_IPV6
	.no_dead_strip	_mlx5_is_fpga_ipsec_rule
.subsections_via_symbols
