	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function i40e_enable_misc_int_causes
_i40e_enable_misc_int_causes:           ## @i40e_enable_misc_int_causes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	leaq	4(%rdi), %rbx
	movq	_I40E_PFINT_ICR0_ENA@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_wr32
	movq	_I40E_PFINT_ICR0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_rd32
	movq	_I40E_PFINT_ICR0_ENA_ECC_ERR_MASK@GOTPCREL(%rip), %rax
	movq	_I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_I40E_PFINT_ICR0_ENA_GRST_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_I40E_PFINT_ICR0_ENA_GPIO_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_I40E_PFINT_ICR0_ENA_HMC_ERR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_I40E_PFINT_ICR0_ENA_VFLR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_I40E_PFINT_ICR0_ENA_ADMINQ_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%r14), %eax
	movq	_I40E_FLAG_IWARP_ENABLED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%eax, %ecx
	je	LBB0_2
## %bb.1:
	movq	_I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_2:
	orl	%ecx, %edx
	movq	_I40E_FLAG_PTP@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	je	LBB0_4
## %bb.3:
	movq	_I40E_PFINT_ICR0_ENA_TIMESYNC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_4:
	orl	%eax, %edx
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_wr32
	movq	_I40E_PFINT_DYN_CTL0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK@GOTPCREL(%rip), %rax
	movq	_I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_wr32
	movq	_I40E_PFINT_STAT_CTL0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_wr32                           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_I40E_PFINT_ICR0_ENA,4,2        ## @I40E_PFINT_ICR0_ENA
	.comm	_I40E_PFINT_ICR0,4,2            ## @I40E_PFINT_ICR0
	.comm	_I40E_PFINT_ICR0_ENA_ECC_ERR_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_ECC_ERR_MASK
	.comm	_I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
	.comm	_I40E_PFINT_ICR0_ENA_GRST_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_GRST_MASK
	.comm	_I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK
	.comm	_I40E_PFINT_ICR0_ENA_GPIO_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_GPIO_MASK
	.comm	_I40E_PFINT_ICR0_ENA_HMC_ERR_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_HMC_ERR_MASK
	.comm	_I40E_PFINT_ICR0_ENA_VFLR_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_VFLR_MASK
	.comm	_I40E_PFINT_ICR0_ENA_ADMINQ_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_ADMINQ_MASK
	.comm	_I40E_FLAG_IWARP_ENABLED,4,2    ## @I40E_FLAG_IWARP_ENABLED
	.comm	_I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK
	.comm	_I40E_FLAG_PTP,4,2              ## @I40E_FLAG_PTP
	.comm	_I40E_PFINT_ICR0_ENA_TIMESYNC_MASK,4,2 ## @I40E_PFINT_ICR0_ENA_TIMESYNC_MASK
	.comm	_I40E_PFINT_DYN_CTL0,4,2        ## @I40E_PFINT_DYN_CTL0
	.comm	_I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK,4,2 ## @I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK
	.comm	_I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK,4,2 ## @I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK
	.comm	_I40E_PFINT_STAT_CTL0,4,2       ## @I40E_PFINT_STAT_CTL0
	.no_dead_strip	_i40e_enable_misc_int_causes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function i40e_enable_misc_int_causes
_i40e_enable_misc_int_causes:           ; @i40e_enable_misc_int_causes
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	add	x19, x0, #4
Lloh0:
	adrp	x21, _I40E_PFINT_ICR0_ENA@GOTPAGE
Lloh1:
	ldr	x21, [x21, _I40E_PFINT_ICR0_ENA@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_wr32
Lloh2:
	adrp	x8, _I40E_PFINT_ICR0@GOTPAGE
Lloh3:
	ldr	x8, [x8, _I40E_PFINT_ICR0@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_rd32
Lloh5:
	adrp	x8, _I40E_PFINT_ICR0_ENA_ECC_ERR_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _I40E_PFINT_ICR0_ENA_ECC_ERR_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK@GOTPAGE
Lloh9:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh11:
	adrp	x9, _I40E_PFINT_ICR0_ENA_GRST_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_GRST_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh14:
	adrp	x9, _I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK@GOTPAGE
Lloh15:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh17:
	adrp	x9, _I40E_PFINT_ICR0_ENA_GPIO_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_GPIO_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh20:
	adrp	x9, _I40E_PFINT_ICR0_ENA_HMC_ERR_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_HMC_ERR_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh23:
	adrp	x9, _I40E_PFINT_ICR0_ENA_VFLR_MASK@GOTPAGE
Lloh24:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_VFLR_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh26:
	adrp	x9, _I40E_PFINT_ICR0_ENA_ADMINQ_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _I40E_PFINT_ICR0_ENA_ADMINQ_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh29:
	adrp	x9, _I40E_FLAG_IWARP_ENABLED@GOTPAGE
Lloh30:
	ldr	x9, [x9, _I40E_FLAG_IWARP_ENABLED@GOTPAGEOFF]
	ldr	w10, [x20]
Lloh31:
	ldr	w9, [x9]
Lloh32:
	adrp	x11, _I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK@GOTPAGE
Lloh33:
	ldr	x11, [x11, _I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w11, [x11]
	tst	w9, w10
	csel	w9, wzr, w11, eq
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _I40E_FLAG_PTP@GOTPAGE
Lloh36:
	ldr	x9, [x9, _I40E_FLAG_PTP@GOTPAGEOFF]
Lloh37:
	adrp	x11, _I40E_PFINT_ICR0_ENA_TIMESYNC_MASK@GOTPAGE
Lloh38:
	ldr	x11, [x11, _I40E_PFINT_ICR0_ENA_TIMESYNC_MASK@GOTPAGEOFF]
Lloh39:
	ldr	w9, [x9]
Lloh40:
	ldr	w11, [x11]
	tst	w9, w10
	csel	w9, wzr, w11, eq
	orr	w2, w8, w9
	ldr	w1, [x21]
	mov	x0, x19
	bl	_wr32
Lloh41:
	adrp	x8, _I40E_PFINT_DYN_CTL0@GOTPAGE
Lloh42:
	ldr	x8, [x8, _I40E_PFINT_DYN_CTL0@GOTPAGEOFF]
Lloh43:
	adrp	x9, _I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK@GOTPAGE
Lloh44:
	ldr	x9, [x9, _I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	ldr	w8, [x9]
Lloh47:
	adrp	x9, _I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK@GOTPAGE
Lloh48:
	ldr	x9, [x9, _I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_wr32
Lloh50:
	adrp	x8, _I40E_PFINT_STAT_CTL0@GOTPAGE
Lloh51:
	ldr	x8, [x8, _I40E_PFINT_STAT_CTL0@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_wr32
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh45
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh39
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_I40E_PFINT_ICR0_ENA,4,2        ; @I40E_PFINT_ICR0_ENA
	.comm	_I40E_PFINT_ICR0,4,2            ; @I40E_PFINT_ICR0
	.comm	_I40E_PFINT_ICR0_ENA_ECC_ERR_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_ECC_ERR_MASK
	.comm	_I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
	.comm	_I40E_PFINT_ICR0_ENA_GRST_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_GRST_MASK
	.comm	_I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK
	.comm	_I40E_PFINT_ICR0_ENA_GPIO_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_GPIO_MASK
	.comm	_I40E_PFINT_ICR0_ENA_HMC_ERR_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_HMC_ERR_MASK
	.comm	_I40E_PFINT_ICR0_ENA_VFLR_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_VFLR_MASK
	.comm	_I40E_PFINT_ICR0_ENA_ADMINQ_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_ADMINQ_MASK
	.comm	_I40E_FLAG_IWARP_ENABLED,4,2    ; @I40E_FLAG_IWARP_ENABLED
	.comm	_I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK
	.comm	_I40E_FLAG_PTP,4,2              ; @I40E_FLAG_PTP
	.comm	_I40E_PFINT_ICR0_ENA_TIMESYNC_MASK,4,2 ; @I40E_PFINT_ICR0_ENA_TIMESYNC_MASK
	.comm	_I40E_PFINT_DYN_CTL0,4,2        ; @I40E_PFINT_DYN_CTL0
	.comm	_I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK,4,2 ; @I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK
	.comm	_I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK,4,2 ; @I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK
	.comm	_I40E_PFINT_STAT_CTL0,4,2       ; @I40E_PFINT_STAT_CTL0
	.no_dead_strip	_i40e_enable_misc_int_causes
.subsections_via_symbols
