	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function igb_set_pcie_completion_timeout
_igb_set_pcie_completion_timeout:       ## @igb_set_pcie_completion_timeout
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_E1000_GCR@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_rd32
	movl	%eax, %ebx
	movq	_E1000_GCR_CMPL_TMOUT_MASK@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_2
LBB0_7:
	xorl	%r15d, %r15d
	jmp	LBB0_8
LBB0_2:
	movq	_E1000_GCR_CAP_VER2@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_6
## %bb.3:
	movq	_PCIE_DEVICE_CONTROL2@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	leaq	-44(%rbp), %rdx
	movq	%r14, %rdi
	callq	_igb_read_pcie_cap_reg
	testq	%rax, %rax
	jne	LBB0_5
## %bb.4:
	movq	_PCIE_DEVICE_CONTROL2_16ms@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -44(%rbp)
	movl	(%r13), %esi
	leaq	-44(%rbp), %rdx
	movq	%r14, %rdi
	callq	_igb_write_pcie_cap_reg
LBB0_5:
	movq	%rax, %r15
LBB0_8:
	movq	_E1000_GCR_CMPL_TMOUT_RESEND@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%esi
	andl	%ebx, %esi
	movl	(%r12), %edi
	callq	_wr32
	movq	%r15, %rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movq	_E1000_GCR_CMPL_TMOUT_10ms@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, %ebx
	jmp	LBB0_7
	.cfi_endproc
                                        ## -- End function
	.comm	_E1000_GCR,4,2                  ## @E1000_GCR
	.comm	_E1000_GCR_CMPL_TMOUT_MASK,4,2  ## @E1000_GCR_CMPL_TMOUT_MASK
	.comm	_E1000_GCR_CAP_VER2,4,2         ## @E1000_GCR_CAP_VER2
	.comm	_E1000_GCR_CMPL_TMOUT_10ms,4,2  ## @E1000_GCR_CMPL_TMOUT_10ms
	.comm	_PCIE_DEVICE_CONTROL2,4,2       ## @PCIE_DEVICE_CONTROL2
	.comm	_PCIE_DEVICE_CONTROL2_16ms,4,2  ## @PCIE_DEVICE_CONTROL2_16ms
	.comm	_E1000_GCR_CMPL_TMOUT_RESEND,4,2 ## @E1000_GCR_CMPL_TMOUT_RESEND
	.no_dead_strip	_igb_set_pcie_completion_timeout
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function igb_set_pcie_completion_timeout
_igb_set_pcie_completion_timeout:       ; @igb_set_pcie_completion_timeout
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
Lloh0:
	adrp	x22, _E1000_GCR@GOTPAGE
Lloh1:
	ldr	x22, [x22, _E1000_GCR@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_rd32
	mov	x19, x0
Lloh2:
	adrp	x8, _E1000_GCR_CMPL_TMOUT_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _E1000_GCR_CMPL_TMOUT_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
	mov	x21, #0
	b	LBB0_7
LBB0_2:
Lloh5:
	adrp	x8, _E1000_GCR_CAP_VER2@GOTPAGE
Lloh6:
	ldr	x8, [x8, _E1000_GCR_CAP_VER2@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	tst	w8, w19
	b.eq	LBB0_6
; %bb.3:
Lloh8:
	adrp	x23, _PCIE_DEVICE_CONTROL2@GOTPAGE
Lloh9:
	ldr	x23, [x23, _PCIE_DEVICE_CONTROL2@GOTPAGEOFF]
	ldr	w1, [x23]
	add	x2, sp, #12
	mov	x0, x20
	bl	_igb_read_pcie_cap_reg
	cbnz	x0, LBB0_5
; %bb.4:
Lloh10:
	adrp	x8, _PCIE_DEVICE_CONTROL2_16ms@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PCIE_DEVICE_CONTROL2_16ms@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
	ldr	w1, [x23]
	add	x2, sp, #12
	mov	x0, x20
	bl	_igb_write_pcie_cap_reg
LBB0_5:
	mov	x21, x0
	b	LBB0_7
LBB0_6:
	mov	x21, #0
Lloh13:
	adrp	x8, _E1000_GCR_CMPL_TMOUT_10ms@GOTPAGE
Lloh14:
	ldr	x8, [x8, _E1000_GCR_CMPL_TMOUT_10ms@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	orr	w19, w8, w19
LBB0_7:
Lloh16:
	adrp	x8, _E1000_GCR_CMPL_TMOUT_RESEND@GOTPAGE
Lloh17:
	ldr	x8, [x8, _E1000_GCR_CMPL_TMOUT_RESEND@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	bic	w1, w19, w8
	ldr	w0, [x22]
	bl	_wr32
	mov	x0, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.cfi_endproc
                                        ; -- End function
	.comm	_E1000_GCR,4,2                  ; @E1000_GCR
	.comm	_E1000_GCR_CMPL_TMOUT_MASK,4,2  ; @E1000_GCR_CMPL_TMOUT_MASK
	.comm	_E1000_GCR_CAP_VER2,4,2         ; @E1000_GCR_CAP_VER2
	.comm	_E1000_GCR_CMPL_TMOUT_10ms,4,2  ; @E1000_GCR_CMPL_TMOUT_10ms
	.comm	_PCIE_DEVICE_CONTROL2,4,2       ; @PCIE_DEVICE_CONTROL2
	.comm	_PCIE_DEVICE_CONTROL2_16ms,4,2  ; @PCIE_DEVICE_CONTROL2_16ms
	.comm	_E1000_GCR_CMPL_TMOUT_RESEND,4,2 ; @E1000_GCR_CMPL_TMOUT_RESEND
	.no_dead_strip	_igb_set_pcie_completion_timeout
.subsections_via_symbols
