	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pcie_capability_reg_implemented
_pcie_capability_reg_implemented:       ## @pcie_capability_reg_implemented
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movl	%esi, %ebx
	movq	%rdi, %r14
	callq	_pci_is_pcie
	movl	%eax, %ecx
	xorl	%eax, %eax
	testl	%ecx, %ecx
	je	LBB0_7
## %bb.1:
	addl	$-128, %ebx
	cmpl	$17, %ebx
	ja	LBB0_7
## %bb.2:
	movl	$1, %eax
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rbx,4), %rdx
	addq	%rcx, %rdx
	jmpq	*%rdx
LBB0_6:
	movq	%r14, %rdi
	callq	_pcie_cap_version
	movl	%eax, %ecx
	xorl	%eax, %eax
	cmpl	$2, %ecx
	setge	%al
LBB0_7:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_4:
	movq	%r14, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_pcie_cap_has_sltctl            ## TAILCALL
LBB0_5:
	movq	%r14, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_pcie_cap_has_rtctl             ## TAILCALL
LBB0_3:
	movq	%r14, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_pcie_cap_has_lnkctl            ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
LJTI0_0:
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_4
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_6
	.long	L0_0_set_3
	.long	L0_0_set_6
	.long	L0_0_set_3
	.long	L0_0_set_6
	.long	L0_0_set_3
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_6
	.long	L0_0_set_7
	.long	L0_0_set_6
	.long	L0_0_set_7
	.end_data_region
                                        ## -- End function
	.no_dead_strip	_pcie_capability_reg_implemented
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pcie_capability_reg_implemented
_pcie_capability_reg_implemented:       ; @pcie_capability_reg_implemented
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x1
	mov	x19, x0
	bl	_pci_is_pcie
	cbz	w0, LBB0_4
; %bb.1:
	sub	w8, w20, #128
	cmp	w8, #17
	b.hi	LBB0_8
; %bb.2:
	mov	w0, #1
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_3
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_3:
	mov	x0, x19
	bl	_pcie_cap_version
	cmp	w0, #1
	cset	w0, gt
LBB0_4:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_5:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_pcie_cap_has_sltctl
LBB0_6:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_pcie_cap_has_rtctl
LBB0_7:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_pcie_cap_has_lnkctl
LBB0_8:
	mov	w0, #0
	b	LBB0_4
	.loh AdrpAdd	Lloh0, Lloh1
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_5-LBB0_3)>>2
	.byte	(LBB0_5-LBB0_3)>>2
	.byte	(LBB0_5-LBB0_3)>>2
	.byte	(LBB0_6-LBB0_3)>>2
	.byte	(LBB0_6-LBB0_3)>>2
	.byte	(LBB0_6-LBB0_3)>>2
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_7-LBB0_3)>>2
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_7-LBB0_3)>>2
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_7-LBB0_3)>>2
	.byte	(LBB0_4-LBB0_3)>>2
	.byte	(LBB0_4-LBB0_3)>>2
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_4-LBB0_3)>>2
	.byte	(LBB0_3-LBB0_3)>>2
	.byte	(LBB0_4-LBB0_3)>>2
                                        ; -- End function
	.no_dead_strip	_pcie_capability_reg_implemented
.subsections_via_symbols
