	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pch_gbe_phy_tx_clk_delay
_pch_gbe_phy_tx_clk_delay:              ## @pch_gbe_phy_tx_clk_delay
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_pch_gbe_hw_to_adapter
	movl	(%r15), %edx
	movl	(%rax), %edi
	cmpl	$128, %edx
	jne	LBB0_6
## %bb.1:
	movq	%rax, %r14
	leaq	L_.str(%rip), %rsi
	callq	_netdev_dbg
	movq	_PHY_AR8031_DBG_OFF@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-28(%rbp), %rdx
	movq	%r15, %rdi
	callq	_pch_gbe_phy_read_reg_miic
	movl	(%rbx), %esi
	movq	_PHY_AR8031_SERDES@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_pch_gbe_phy_write_reg_miic
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_4
## %bb.2:
	movq	_PHY_AR8031_DBG_DAT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-28(%rbp), %rdx
	movq	%r15, %rdi
	callq	_pch_gbe_phy_read_reg_miic
	movq	_PHY_AR8031_SERDES_TX_CLK_DLY@GOTPCREL(%rip), %rax
	movl	-28(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -28(%rbp)
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_pch_gbe_phy_write_reg_miic
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_3
LBB0_4:
	movl	(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	xorl	%eax, %eax
	callq	_netdev_err
	jmp	LBB0_5
LBB0_6:
	leaq	L_.str.1(%rip), %rsi
	xorl	%ebx, %ebx
	xorl	%eax, %eax
	callq	_netdev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
LBB0_5:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	xorl	%ebx, %ebx
	jmp	LBB0_5
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Configuring AR803X PHY for 2ns TX clock delay\n"

	.comm	_PHY_AR8031_DBG_OFF,4,2         ## @PHY_AR8031_DBG_OFF
	.comm	_PHY_AR8031_SERDES,4,2          ## @PHY_AR8031_SERDES
	.comm	_PHY_AR8031_DBG_DAT,4,2         ## @PHY_AR8031_DBG_DAT
	.comm	_PHY_AR8031_SERDES_TX_CLK_DLY,4,2 ## @PHY_AR8031_SERDES_TX_CLK_DLY
L_.str.1:                               ## @.str.1
	.asciz	"Unknown PHY (%x), could not set TX clock delay\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
L_.str.2:                               ## @.str.2
	.asciz	"Could not configure tx clock delay for PHY\n"

	.no_dead_strip	_pch_gbe_phy_tx_clk_delay
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pch_gbe_phy_tx_clk_delay
_pch_gbe_phy_tx_clk_delay:              ; @pch_gbe_phy_tx_clk_delay
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	bl	_pch_gbe_hw_to_adapter
	mov	x19, x0
	ldr	w8, [x20]
	ldr	w0, [x0]
	cmp	w8, #128
	b.ne	LBB0_4
; %bb.1:
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_netdev_dbg
Lloh2:
	adrp	x21, _PHY_AR8031_DBG_OFF@GOTPAGE
Lloh3:
	ldr	x21, [x21, _PHY_AR8031_DBG_OFF@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x20
	bl	_pch_gbe_phy_read_reg_miic
	ldr	w1, [x21]
Lloh4:
	adrp	x8, _PHY_AR8031_SERDES@GOTPAGE
Lloh5:
	ldr	x8, [x8, _PHY_AR8031_SERDES@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_pch_gbe_phy_write_reg_miic
	mov	x21, x0
	cbnz	w0, LBB0_3
; %bb.2:
Lloh7:
	adrp	x21, _PHY_AR8031_DBG_DAT@GOTPAGE
Lloh8:
	ldr	x21, [x21, _PHY_AR8031_DBG_DAT@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x20
	bl	_pch_gbe_phy_read_reg_miic
Lloh9:
	adrp	x8, _PHY_AR8031_SERDES_TX_CLK_DLY@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PHY_AR8031_SERDES_TX_CLK_DLY@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_pch_gbe_phy_write_reg_miic
	mov	x21, x0
	cbz	w0, LBB0_5
LBB0_3:
	ldr	w0, [x19]
Lloh12:
	adrp	x1, l_.str.2@PAGE
Lloh13:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_netdev_err
	b	LBB0_5
LBB0_4:
	str	x8, [sp]
Lloh14:
	adrp	x1, l_.str.1@PAGE
Lloh15:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_netdev_err
Lloh16:
	adrp	x8, _EINVAL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	neg	w21, w8
LBB0_5:
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh14, Lloh15
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Configuring AR803X PHY for 2ns TX clock delay\n"

	.comm	_PHY_AR8031_DBG_OFF,4,2         ; @PHY_AR8031_DBG_OFF
	.comm	_PHY_AR8031_SERDES,4,2          ; @PHY_AR8031_SERDES
	.comm	_PHY_AR8031_DBG_DAT,4,2         ; @PHY_AR8031_DBG_DAT
	.comm	_PHY_AR8031_SERDES_TX_CLK_DLY,4,2 ; @PHY_AR8031_SERDES_TX_CLK_DLY
l_.str.1:                               ; @.str.1
	.asciz	"Unknown PHY (%x), could not set TX clock delay\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
l_.str.2:                               ; @.str.2
	.asciz	"Could not configure tx clock delay for PHY\n"

	.no_dead_strip	_pch_gbe_phy_tx_clk_delay
.subsections_via_symbols
