	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_phy_sata_cfg_cmu_core
_xgene_phy_sata_cfg_cmu_core:           ## @xgene_phy_sata_cfg_cmu_core
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, -48(%rbp)                 ## 4-byte Spill
	movl	%esi, %r13d
	movq	%rdi, %r14
	movq	_REF_CMU@GOTPCREL(%rip), %rax
	cmpl	%esi, (%rax)
	jne	LBB0_2
## %bb.1:
	movq	_CMU_REG34@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movl	$7, %esi
	callq	_CMU_REG34_VCO_CAL_VTH_LO_MAX_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$12, %esi
	callq	_CMU_REG34_VCO_CAL_VTH_HI_MAX_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$3, %esi
	callq	_CMU_REG34_VCO_CAL_VTH_LO_MIN_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$8, %esi
	callq	_CMU_REG34_VCO_CAL_VTH_HI_MIN_SET
	movl	%eax, -44(%rbp)
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
LBB0_2:
	movq	_CMU_REG0@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movq	_REF_CMU@GOTPCREL(%rip), %rbx
	cmpl	%r13d, (%rbx)
	setne	%al
	movq	_preA3Chip@GOTPCREL(%rip), %r12
	cmpq	$0, (%r12)
	sete	%cl
	movl	-44(%rbp), %edi
	andb	%al, %cl
	movzbl	%cl, %eax
	leal	(%rax,%rax,2), %esi
	orl	$4, %esi
	callq	_CMU_REG0_CAL_COUNT_RESOL_SET
	movl	%eax, -44(%rbp)
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG1@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	leaq	-44(%rbp), %rcx
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG1_PLL_CP_SET
	cmpl	%r13d, (%rbx)
	movl	%eax, -44(%rbp)
	sete	%cl
	cmpq	$0, (%r12)
	setne	%dl
	orb	%cl, %dl
	movzbl	%dl, %ecx
	leal	(%rcx,%rcx), %esi
	addl	$3, %esi
	movl	%eax, %edi
	callq	_CMU_REG1_PLL_CP_SEL_SET
	movl	%eax, -44(%rbp)
	xorl	%esi, %esi
	cmpl	%r13d, (%rbx)
	setne	%sil
	movl	%eax, %edi
	callq	_CMU_REG1_PLL_MANUALCAL_SET
	movl	%eax, -44(%rbp)
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	cmpl	%r13d, (%rbx)
	je	LBB0_4
## %bb.3:
	movq	_CMU_REG5@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CMU_REG5_PLL_RESETB_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_clrbits
LBB0_4:
	movq	_CMU_REG2@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movq	_REF_CMU@GOTPCREL(%rip), %rax
	cmpl	%r13d, (%rax)
	jne	LBB0_6
## %bb.5:
	movl	$10, %esi
	callq	_CMU_REG2_PLL_LFRES_SET
	movl	%eax, -44(%rbp)
	movq	_REFDIV_VAL_100M@GOTPCREL(%rip), %rbx
	movq	_FBDIV_VAL_100M@GOTPCREL(%rip), %rcx
	jmp	LBB0_7
LBB0_6:
	movl	$3, %esi
	callq	_CMU_REG2_PLL_LFRES_SET
	movl	%eax, -44(%rbp)
	movq	_CLK_EXT_DIFF@GOTPCREL(%rip), %rcx
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	cmpl	%edx, (%rcx)
	movq	_FBDIV_VAL_100M@GOTPCREL(%rip), %rcx
	cmoveq	_FBDIV_VAL_50M@GOTPCREL(%rip), %rcx
	movq	_REFDIV_VAL_100M@GOTPCREL(%rip), %rbx
	cmoveq	_REFDIV_VAL_50M@GOTPCREL(%rip), %rbx
LBB0_7:
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_CMU_REG2_PLL_FBDIV_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %esi
	movl	%eax, %edi
	callq	_CMU_REG2_PLL_REFDIV_SET
	movl	%eax, -44(%rbp)
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movq	_REF_CMU@GOTPCREL(%rip), %rax
	cmpl	%r13d, (%rax)
	jne	LBB0_9
## %bb.8:
	movl	$3, %esi
	callq	_CMU_REG3_VCOVARSEL_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_CMU_REG3_VCO_MOMSEL_INIT_SET
	movq	_preA3Chip@GOTPCREL(%rip), %r15
	jmp	LBB0_10
LBB0_9:
	movl	$15, %esi
	callq	_CMU_REG3_VCOVARSEL_SET
	movl	%eax, -44(%rbp)
	xorl	%ecx, %ecx
	movq	_preA3Chip@GOTPCREL(%rip), %r15
	cmpq	$0, (%r15)
	sete	%cl
	leal	(%rcx,%rcx,4), %esi
	addl	$21, %esi
	movl	%eax, %edi
	callq	_CMU_REG3_VCO_MOMSEL_INIT_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$21, %esi
	callq	_CMU_REG3_VCO_MANMOMSEL_SET
LBB0_10:
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG26@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	leaq	-44(%rbp), %r12
	movq	%r14, %rdi
	movl	%r13d, %esi
	movq	%r12, %rcx
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_CMU_REG26_FORCE_PLL_LOCK_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG5@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movq	%r12, %rcx
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movl	$3, %esi
	callq	_CMU_REG5_PLL_LFSMCAP_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$3, %esi
	callq	_CMU_REG5_PLL_LFCAP_SET
	movl	%eax, -44(%rbp)
	movq	_REF_CMU@GOTPCREL(%rip), %rcx
	cmpl	%r13d, (%rcx)
	sete	%cl
	cmpq	$0, (%r15)
	sete	%dl
	orb	%cl, %dl
	movzbl	%dl, %ecx
	leal	(%rcx,%rcx,2), %esi
	orl	$4, %esi
	movl	%eax, %edi
	callq	_CMU_REG5_PLL_LOCK_RESOLUTION_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG6@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	leaq	-44(%rbp), %rcx
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	cmpq	$0, (%r15)
	sete	%sil
	addl	%esi, %esi
	callq	_CMU_REG6_PLL_VREGTRIM_SET
	movl	%eax, -44(%rbp)
	xorl	%esi, %esi
	cmpq	$0, (%r15)
	setne	%sil
	movl	%eax, %edi
	callq	_CMU_REG6_MAN_PVT_CAL_SET
	movl	%eax, -44(%rbp)
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_PHY_CMU@GOTPCREL(%rip), %rax
	cmpl	%r13d, (%rax)
	movq	%r15, %rbx
	jne	LBB0_15
## %bb.11:
	movq	_CMU_REG9@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movq	_CMU_REG9_WORD_LEN_20BIT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_CMU_REG9_TX_WORD_MODE_CH1_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %esi
	movq	_preA3Chip@GOTPCREL(%rip), %rbx
	movl	%eax, %edi
	callq	_CMU_REG9_TX_WORD_MODE_CH0_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_CMU_REG9_PLL_POST_DIVBY2_SET
	movl	%eax, -44(%rbp)
	cmpq	$0, (%rbx)
	jne	LBB0_13
## %bb.12:
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_CMU_REG9_VBG_BYPASSB_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_CMU_REG9_IGEN_BYPASS_SET
	movl	%eax, -44(%rbp)
LBB0_13:
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	cmpq	$0, (%rbx)
	jne	LBB0_15
## %bb.14:
	movq	_CMU_REG10@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG10_VREG_REFSEL_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	_preA3Chip@GOTPCREL(%rip), %rbx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
LBB0_15:
	movq	_CMU_REG16@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-44(%rbp), %rcx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_CMU_REG16_BYPASS_PLL_LOCK_SET
	movl	%eax, -44(%rbp)
	movq	_REF_CMU@GOTPCREL(%rip), %rcx
	cmpl	%r13d, (%rcx)
	setne	%cl
	cmpq	$0, (%rbx)
	sete	%dl
	andb	%cl, %dl
	movzbl	%dl, %ecx
	leal	(%rcx,%rcx,2), %esi
	orl	$4, %esi
	movl	%eax, %edi
	callq	_CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET
	movl	%eax, -44(%rbp)
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	%rbx, %r15
	movq	_CMU_REG30@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	leaq	-44(%rbp), %rcx
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_CMU_REG30_PCIE_MODE_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$3, %esi
	callq	_CMU_REG30_LOCK_COUNT_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG31@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	$15, %ecx
	callq	_cmu_wr
	movq	_CMU_REG32@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	leaq	-44(%rbp), %rcx
	callq	_cmu_rd
	movl	-44(%rbp), %edi
	movl	$3, %esi
	callq	_CMU_REG32_PVT_CAL_WAIT_SEL_SET
	movq	_REF_CMU@GOTPCREL(%rip), %rbx
	cmpl	%r13d, (%rbx)
	movl	%eax, -44(%rbp)
	sete	%cl
	cmpq	$0, (%r15)
	setne	%dl
	orb	%cl, %dl
	movzbl	%dl, %ecx
	leal	(%rcx,%rcx), %esi
	incl	%esi
	movl	%eax, %edi
	callq	_CMU_REG32_IREF_ADJ_SET
	movl	%eax, -44(%rbp)
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	cmpq	$0, (%r15)
	movl	$36135, %ecx                    ## imm = 0x8D27
	movl	$34620, %eax                    ## imm = 0x873C
	cmovel	%eax, %ecx
	cmpl	%r13d, (%rbx)
	cmovel	%eax, %ecx
	movq	_CMU_REG34@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_cmu_wr
	movq	_CMU_REG37@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	$61455, %ecx                    ## imm = 0xF00F
	callq	_cmu_wr
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_REF_CMU,4,2                    ## @REF_CMU
	.comm	_CMU_REG34,4,2                  ## @CMU_REG34
	.comm	_CMU_REG0,4,2                   ## @CMU_REG0
	.comm	_preA3Chip,8,3                  ## @preA3Chip
	.comm	_CMU_REG1,4,2                   ## @CMU_REG1
	.comm	_CMU_REG5,4,2                   ## @CMU_REG5
	.comm	_CMU_REG5_PLL_RESETB_MASK,4,2   ## @CMU_REG5_PLL_RESETB_MASK
	.comm	_CMU_REG2,4,2                   ## @CMU_REG2
	.comm	_CLK_EXT_DIFF,4,2               ## @CLK_EXT_DIFF
	.comm	_FBDIV_VAL_100M,4,2             ## @FBDIV_VAL_100M
	.comm	_REFDIV_VAL_100M,4,2            ## @REFDIV_VAL_100M
	.comm	_FBDIV_VAL_50M,4,2              ## @FBDIV_VAL_50M
	.comm	_REFDIV_VAL_50M,4,2             ## @REFDIV_VAL_50M
	.comm	_CMU_REG3,4,2                   ## @CMU_REG3
	.comm	_CMU_REG26,4,2                  ## @CMU_REG26
	.comm	_CMU_REG6,4,2                   ## @CMU_REG6
	.comm	_PHY_CMU,4,2                    ## @PHY_CMU
	.comm	_CMU_REG9,4,2                   ## @CMU_REG9
	.comm	_CMU_REG9_WORD_LEN_20BIT,4,2    ## @CMU_REG9_WORD_LEN_20BIT
	.comm	_CMU_REG10,4,2                  ## @CMU_REG10
	.comm	_CMU_REG16,4,2                  ## @CMU_REG16
	.comm	_CMU_REG30,4,2                  ## @CMU_REG30
	.comm	_CMU_REG31,4,2                  ## @CMU_REG31
	.comm	_CMU_REG32,4,2                  ## @CMU_REG32
	.comm	_CMU_REG37,4,2                  ## @CMU_REG37
	.no_dead_strip	_xgene_phy_sata_cfg_cmu_core
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_phy_sata_cfg_cmu_core
_xgene_phy_sata_cfg_cmu_core:           ; @xgene_phy_sata_cfg_cmu_core
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x2
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x23, _REF_CMU@GOTPAGE
Lloh1:
	ldr	x23, [x23, _REF_CMU@GOTPAGEOFF]
	ldr	w8, [x23]
Lloh2:
	adrp	x22, _CMU_REG34@GOTPAGE
Lloh3:
	ldr	x22, [x22, _CMU_REG34@GOTPAGEOFF]
	cmp	w8, w1
	b.ne	LBB0_2
; %bb.1:
	ldr	w2, [x22]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #7
	bl	_CMU_REG34_VCO_CAL_VTH_LO_MAX_SET
	str	w0, [sp, #12]
	mov	w1, #12
	bl	_CMU_REG34_VCO_CAL_VTH_HI_MAX_SET
	str	w0, [sp, #12]
	mov	w1, #3
	bl	_CMU_REG34_VCO_CAL_VTH_LO_MIN_SET
	str	w0, [sp, #12]
	mov	w1, #8
	bl	_CMU_REG34_VCO_CAL_VTH_HI_MIN_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
LBB0_2:
Lloh4:
	adrp	x25, _CMU_REG0@GOTPAGE
Lloh5:
	ldr	x25, [x25, _CMU_REG0@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w8, [x23]
Lloh6:
	adrp	x24, _preA3Chip@GOTPAGE
Lloh7:
	ldr	x24, [x24, _preA3Chip@GOTPAGEOFF]
	ldr	x9, [x24]
	cmp	x9, #0
	ccmp	w8, w19, #4, eq
	ldr	w0, [sp, #12]
	mov	w8, #7
	mov	w9, #4
	csel	w1, w9, w8, eq
	bl	_CMU_REG0_CAL_COUNT_RESOL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh8:
	adrp	x25, _CMU_REG1@GOTPAGE
Lloh9:
	ldr	x25, [x25, _CMU_REG1@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG1_PLL_CP_SET
	str	w0, [sp, #12]
	ldr	w8, [x23]
	ldr	x9, [x24]
	cmp	x9, #0
	ccmp	w8, w19, #4, eq
	mov	w8, #3
	mov	w9, #5
	csel	w1, w9, w8, eq
	bl	_CMU_REG1_PLL_CP_SEL_SET
	str	w0, [sp, #12]
	ldr	w8, [x23]
	cmp	w8, w19
	cset	w1, ne
	bl	_CMU_REG1_PLL_MANUALCAL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
	ldr	w8, [x23]
Lloh10:
	adrp	x25, _CMU_REG5@GOTPAGE
Lloh11:
	ldr	x25, [x25, _CMU_REG5@GOTPAGEOFF]
	cmp	w8, w19
	b.eq	LBB0_4
; %bb.3:
	ldr	w2, [x25]
Lloh12:
	adrp	x8, _CMU_REG5_PLL_RESETB_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CMU_REG5_PLL_RESETB_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_clrbits
LBB0_4:
Lloh15:
	adrp	x26, _CMU_REG2@GOTPAGE
Lloh16:
	ldr	x26, [x26, _CMU_REG2@GOTPAGEOFF]
	ldr	w2, [x26]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w8, [x23]
	ldr	w0, [sp, #12]
	cmp	w8, w19
	b.ne	LBB0_6
; %bb.5:
	mov	w1, #10
	bl	_CMU_REG2_PLL_LFRES_SET
	str	w0, [sp, #12]
Lloh17:
	adrp	x21, _REFDIV_VAL_100M@GOTPAGE
Lloh18:
	ldr	x21, [x21, _REFDIV_VAL_100M@GOTPAGEOFF]
Lloh19:
	adrp	x8, _FBDIV_VAL_100M@GOTPAGE
Lloh20:
	ldr	x8, [x8, _FBDIV_VAL_100M@GOTPAGEOFF]
	b	LBB0_7
LBB0_6:
	mov	w1, #3
	bl	_CMU_REG2_PLL_LFRES_SET
	str	w0, [sp, #12]
Lloh21:
	adrp	x8, _CLK_EXT_DIFF@GOTPAGE
Lloh22:
	ldr	x8, [x8, _CLK_EXT_DIFF@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _FBDIV_VAL_100M@GOTPAGE
Lloh25:
	ldr	x9, [x9, _FBDIV_VAL_100M@GOTPAGEOFF]
Lloh26:
	adrp	x10, _FBDIV_VAL_50M@GOTPAGE
Lloh27:
	ldr	x10, [x10, _FBDIV_VAL_50M@GOTPAGEOFF]
	cmp	w8, w21
	csel	x8, x10, x9, eq
Lloh28:
	adrp	x9, _REFDIV_VAL_100M@GOTPAGE
Lloh29:
	ldr	x9, [x9, _REFDIV_VAL_100M@GOTPAGEOFF]
Lloh30:
	adrp	x10, _REFDIV_VAL_50M@GOTPAGE
Lloh31:
	ldr	x10, [x10, _REFDIV_VAL_50M@GOTPAGEOFF]
	csel	x21, x10, x9, eq
LBB0_7:
	ldr	w1, [x8]
	bl	_CMU_REG2_PLL_FBDIV_SET
	str	w0, [sp, #12]
	ldr	w1, [x21]
	bl	_CMU_REG2_PLL_REFDIV_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x26]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh32:
	adrp	x21, _CMU_REG3@GOTPAGE
Lloh33:
	ldr	x21, [x21, _CMU_REG3@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w8, [x23]
	ldr	w0, [sp, #12]
	cmp	w8, w19
	b.ne	LBB0_9
; %bb.8:
	mov	w1, #3
	bl	_CMU_REG3_VCOVARSEL_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_CMU_REG3_VCO_MOMSEL_INIT_SET
	b	LBB0_10
LBB0_9:
	mov	w1, #15
	bl	_CMU_REG3_VCOVARSEL_SET
	str	w0, [sp, #12]
	ldr	x8, [x24]
	cmp	x8, #0
	mov	w8, #21
	mov	w9, #26
	csel	w1, w9, w8, eq
	bl	_CMU_REG3_VCO_MOMSEL_INIT_SET
	str	w0, [sp, #12]
	mov	w1, #21
	bl	_CMU_REG3_VCO_MANMOMSEL_SET
LBB0_10:
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh34:
	adrp	x21, _CMU_REG26@GOTPAGE
Lloh35:
	ldr	x21, [x21, _CMU_REG26@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_CMU_REG26_FORCE_PLL_LOCK_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w21, #3
	mov	w1, #3
	bl	_CMU_REG5_PLL_LFSMCAP_SET
	str	w0, [sp, #12]
	mov	w1, #3
	bl	_CMU_REG5_PLL_LFCAP_SET
	str	w0, [sp, #12]
	ldr	w8, [x23]
	ldr	x9, [x24]
	cmp	x9, #0
	ccmp	w8, w19, #4, ne
	mov	w26, #7
	mov	w27, #4
	csel	w1, w27, w26, ne
	bl	_CMU_REG5_PLL_LOCK_RESOLUTION_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh36:
	adrp	x25, _CMU_REG6@GOTPAGE
Lloh37:
	ldr	x25, [x25, _CMU_REG6@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	ldr	x8, [x24]
	cmp	x8, #0
	cset	w8, eq
	lsl	w1, w8, #1
	bl	_CMU_REG6_PLL_VREGTRIM_SET
	str	w0, [sp, #12]
	ldr	x8, [x24]
	cmp	x8, #0
	cset	w1, ne
	bl	_CMU_REG6_MAN_PVT_CAL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh38:
	adrp	x8, _PHY_CMU@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PHY_CMU@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	cmp	w8, w19
	b.ne	LBB0_15
; %bb.11:
Lloh41:
	adrp	x25, _CMU_REG9@GOTPAGE
Lloh42:
	ldr	x25, [x25, _CMU_REG9@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
Lloh43:
	adrp	x28, _CMU_REG9_WORD_LEN_20BIT@GOTPAGE
Lloh44:
	ldr	x28, [x28, _CMU_REG9_WORD_LEN_20BIT@GOTPAGEOFF]
	ldr	w1, [x28]
	bl	_CMU_REG9_TX_WORD_MODE_CH1_SET
	str	w0, [sp, #12]
	ldr	w1, [x28]
	bl	_CMU_REG9_TX_WORD_MODE_CH0_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG9_PLL_POST_DIVBY2_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	x8, [x24]
	cbnz	x8, LBB0_13
; %bb.12:
	mov	x0, x3
	mov	w1, #0
	bl	_CMU_REG9_VBG_BYPASSB_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_CMU_REG9_IGEN_BYPASS_SET
	mov	x3, x0
	str	w0, [sp, #12]
LBB0_13:
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
	ldr	x8, [x24]
	cbnz	x8, LBB0_15
; %bb.14:
Lloh45:
	adrp	x25, _CMU_REG10@GOTPAGE
Lloh46:
	ldr	x25, [x25, _CMU_REG10@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG10_VREG_REFSEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
LBB0_15:
Lloh47:
	adrp	x25, _CMU_REG16@GOTPAGE
Lloh48:
	ldr	x25, [x25, _CMU_REG16@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG16_CALIBRATION_DONE_OVERRIDE_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG16_BYPASS_PLL_LOCK_SET
	str	w0, [sp, #12]
	ldr	w8, [x23]
	ldr	x9, [x24]
	cmp	x9, #0
	ccmp	w8, w19, #4, eq
	csel	w1, w27, w26, eq
	bl	_CMU_REG16_VCOCAL_WAIT_BTW_CODE_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh49:
	adrp	x25, _CMU_REG30@GOTPAGE
Lloh50:
	ldr	x25, [x25, _CMU_REG30@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_CMU_REG30_PCIE_MODE_SET
	str	w0, [sp, #12]
	mov	w1, #3
	bl	_CMU_REG30_LOCK_COUNT_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh51:
	adrp	x8, _CMU_REG31@GOTPAGE
Lloh52:
	ldr	x8, [x8, _CMU_REG31@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w3, #15
	bl	_cmu_wr
Lloh54:
	adrp	x25, _CMU_REG32@GOTPAGE
Lloh55:
	ldr	x25, [x25, _CMU_REG32@GOTPAGEOFF]
	ldr	w2, [x25]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #3
	bl	_CMU_REG32_PVT_CAL_WAIT_SEL_SET
	str	w0, [sp, #12]
	ldr	w8, [x23]
	ldr	x9, [x24]
	cmp	x9, #0
	ccmp	w8, w19, #4, eq
	csinc	w1, w21, wzr, eq
	bl	_CMU_REG32_IREF_ADJ_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x25]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
	ldr	w8, [x23]
	ldr	x9, [x24]
	cmp	x9, #0
	ccmp	w8, w19, #4, ne
	mov	w8, #34620
	mov	w9, #36135
	csel	w3, w9, w8, ne
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh56:
	adrp	x8, _CMU_REG37@GOTPAGE
Lloh57:
	ldr	x8, [x8, _CMU_REG37@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x1, x19
	mov	w3, #61455
	bl	_cmu_wr
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.cfi_endproc
                                        ; -- End function
	.comm	_REF_CMU,4,2                    ; @REF_CMU
	.comm	_CMU_REG34,4,2                  ; @CMU_REG34
	.comm	_CMU_REG0,4,2                   ; @CMU_REG0
	.comm	_preA3Chip,8,3                  ; @preA3Chip
	.comm	_CMU_REG1,4,2                   ; @CMU_REG1
	.comm	_CMU_REG5,4,2                   ; @CMU_REG5
	.comm	_CMU_REG5_PLL_RESETB_MASK,4,2   ; @CMU_REG5_PLL_RESETB_MASK
	.comm	_CMU_REG2,4,2                   ; @CMU_REG2
	.comm	_CLK_EXT_DIFF,4,2               ; @CLK_EXT_DIFF
	.comm	_FBDIV_VAL_100M,4,2             ; @FBDIV_VAL_100M
	.comm	_REFDIV_VAL_100M,4,2            ; @REFDIV_VAL_100M
	.comm	_FBDIV_VAL_50M,4,2              ; @FBDIV_VAL_50M
	.comm	_REFDIV_VAL_50M,4,2             ; @REFDIV_VAL_50M
	.comm	_CMU_REG3,4,2                   ; @CMU_REG3
	.comm	_CMU_REG26,4,2                  ; @CMU_REG26
	.comm	_CMU_REG6,4,2                   ; @CMU_REG6
	.comm	_PHY_CMU,4,2                    ; @PHY_CMU
	.comm	_CMU_REG9,4,2                   ; @CMU_REG9
	.comm	_CMU_REG9_WORD_LEN_20BIT,4,2    ; @CMU_REG9_WORD_LEN_20BIT
	.comm	_CMU_REG10,4,2                  ; @CMU_REG10
	.comm	_CMU_REG16,4,2                  ; @CMU_REG16
	.comm	_CMU_REG30,4,2                  ; @CMU_REG30
	.comm	_CMU_REG31,4,2                  ; @CMU_REG31
	.comm	_CMU_REG32,4,2                  ; @CMU_REG32
	.comm	_CMU_REG37,4,2                  ; @CMU_REG37
	.no_dead_strip	_xgene_phy_sata_cfg_cmu_core
.subsections_via_symbols
