	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlxsw_sx_port_connector_port
_mlxsw_sx_port_connector_port:          ## @mlxsw_sx_port_connector_port
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPCREL(%rip), %rax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%edi, %ecx
	je	LBB0_2
## %bb.1:
	movq	_PORT_FIBRE@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_2:
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPCREL(%rip), %rax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%edi, %ecx
	je	LBB0_4
## %bb.3:
	movq	_PORT_DA@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_4:
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPCREL(%rip), %rax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%edi, %ecx
	jne	LBB0_5
## %bb.6:
	movq	_PORT_OTHER@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_5:
	movq	_PORT_NONE@GOTPCREL(%rip), %rax
LBB0_7:
	movl	(%rax), %eax
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_SGMII,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_SGMII
	.comm	_PORT_FIBRE,4,2                 ## @PORT_FIBRE
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4
	.comm	_PORT_DA,4,2                    ## @PORT_DA
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4
	.comm	_PORT_NONE,4,2                  ## @PORT_NONE
	.comm	_PORT_OTHER,4,2                 ## @PORT_OTHER
	.no_dead_strip	_mlxsw_sx_port_connector_port
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlxsw_sx_port_connector_port
_mlxsw_sx_port_connector_port:          ; @mlxsw_sx_port_connector_port
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPAGEOFF]
Lloh2:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPAGE
Lloh3:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
Lloh12:
	adrp	x8, _PORT_FIBRE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PORT_FIBRE@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	ret
LBB0_2:
Lloh15:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPAGE
Lloh19:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh21:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4@GOTPAGE
Lloh22:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w0
	b.eq	LBB0_4
; %bb.3:
Lloh24:
	adrp	x8, _PORT_DA@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PORT_DA@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	ret
LBB0_4:
Lloh27:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh33:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPAGE
Lloh34:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPAGE
Lloh37:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh39:
	adrp	x9, _PORT_NONE@GOTPAGE
Lloh40:
	ldr	x9, [x9, _PORT_NONE@GOTPAGEOFF]
Lloh41:
	adrp	x10, _PORT_OTHER@GOTPAGE
Lloh42:
	ldr	x10, [x10, _PORT_OTHER@GOTPAGEOFF]
	tst	w8, w0
	csel	x8, x10, x9, eq
	ldr	w0, [x8]
	ret
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_SGMII,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_SGMII
	.comm	_PORT_FIBRE,4,2                 ; @PORT_FIBRE
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4
	.comm	_PORT_DA,4,2                    ; @PORT_DA
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4
	.comm	_PORT_NONE,4,2                  ; @PORT_NONE
	.comm	_PORT_OTHER,4,2                 ; @PORT_OTHER
	.no_dead_strip	_mlxsw_sx_port_connector_port
.subsections_via_symbols
