	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rza1_pin_mux_single
_rza1_pin_mux_single:                   ## @rza1_pin_mux_single
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movq	(%rdi), %rbx
	movq	(%rsi), %r12
	leaq	(%rbx,%r12,4), %r15
	movl	8(%rsi), %r14d
	movl	12(%rsi), %r13d
	movl	16(%rsi), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_rza1_pin_reset
	movl	(%rbx,%r12,4), %edi
	movl	%r14d, %esi
	movl	%r13d, %edx
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	callq	_rza1_pinmux_get_flags
	movq	_MUX_FLAGS_BIDIR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %ebx
	andl	%eax, %ebx
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	orl	%edx, %ebx
	testl	%edx, %edx
	cmovel	%eax, %ebx
	testl	%ecx, %ebx
	je	LBB0_2
## %bb.1:
	movq	_RZA1_PBDC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	movl	$1, %ecx
	callq	_rza1_set_bit
LBB0_2:
	decl	%r13d
	movq	_RZA1_PFC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MUX_FUNC_PFC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	andl	%r13d, %ecx
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_rza1_set_bit
	movq	_RZA1_PFCE_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MUX_FUNC_PFCE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	andl	%r13d, %ecx
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_rza1_set_bit
	movq	_RZA1_PFCEA_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MUX_FUNC_PFCEA_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	movq	%r15, %rdi
	movl	%r14d, %edx
	movl	%r13d, %ecx
	callq	_rza1_set_bit
	movq	_MUX_FLAGS_SWIO_INPUT@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_MUX_FLAGS_SWIO_OUTPUT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%ecx, %eax
	testl	%ebx, %eax
	je	LBB0_4
## %bb.3:
	movq	_RZA1_PM_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	andl	%ebx, %ecx
	movq	%r15, %rdi
	movl	%r14d, %edx
	jmp	LBB0_5
LBB0_4:
	movq	_RZA1_PIPC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	movl	$1, %ecx
LBB0_5:
	callq	_rza1_set_bit
	movq	_RZA1_PMC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	movl	$1, %ecx
	callq	_rza1_set_bit
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MUX_FLAGS_BIDIR,4,2            ## @MUX_FLAGS_BIDIR
	.comm	_RZA1_PBDC_REG,4,2              ## @RZA1_PBDC_REG
	.comm	_RZA1_PFC_REG,4,2               ## @RZA1_PFC_REG
	.comm	_MUX_FUNC_PFC_MASK,4,2          ## @MUX_FUNC_PFC_MASK
	.comm	_RZA1_PFCE_REG,4,2              ## @RZA1_PFCE_REG
	.comm	_MUX_FUNC_PFCE_MASK,4,2         ## @MUX_FUNC_PFCE_MASK
	.comm	_RZA1_PFCEA_REG,4,2             ## @RZA1_PFCEA_REG
	.comm	_MUX_FUNC_PFCEA_MASK,4,2        ## @MUX_FUNC_PFCEA_MASK
	.comm	_MUX_FLAGS_SWIO_INPUT,4,2       ## @MUX_FLAGS_SWIO_INPUT
	.comm	_MUX_FLAGS_SWIO_OUTPUT,4,2      ## @MUX_FLAGS_SWIO_OUTPUT
	.comm	_RZA1_PM_REG,4,2                ## @RZA1_PM_REG
	.comm	_RZA1_PIPC_REG,4,2              ## @RZA1_PIPC_REG
	.comm	_RZA1_PMC_REG,4,2               ## @RZA1_PMC_REG
	.no_dead_strip	_rza1_pin_mux_single
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rza1_pin_mux_single
_rza1_pin_mux_single:                   ; @rza1_pin_mux_single
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x0
	ldr	x8, [x0]
	ldr	x9, [x1]
	add	x19, x8, x9, lsl #2
	ldp	w20, w21, [x1, #8]
	ldr	w23, [x1, #16]
	mov	x0, x19
	mov	x1, x20
	bl	_rza1_pin_reset
	ldr	w0, [x19]
	mov	x1, x20
	mov	x2, x21
	mov	x3, x22
	bl	_rza1_pinmux_get_flags
Lloh0:
	adrp	x8, _MUX_FLAGS_BIDIR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MUX_FLAGS_BIDIR@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	and	w9, w8, w0
	orr	w9, w9, w23
	cmp	w23, #0
	csel	w22, w0, w9, eq
	tst	w22, w8
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _RZA1_PBDC_REG@GOTPAGE
Lloh4:
	ldr	x8, [x8, _RZA1_PBDC_REG@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	mov	w3, #1
	bl	_rza1_set_bit
LBB0_2:
Lloh6:
	adrp	x8, _RZA1_PFC_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _RZA1_PFC_REG@GOTPAGEOFF]
	sub	w21, w21, #1
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _MUX_FUNC_PFC_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MUX_FUNC_PFC_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	and	w3, w8, w21
	mov	x0, x19
	mov	x2, x20
	bl	_rza1_set_bit
Lloh12:
	adrp	x8, _RZA1_PFCE_REG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _RZA1_PFCE_REG@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _MUX_FUNC_PFCE_MASK@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MUX_FUNC_PFCE_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	and	w3, w8, w21
	mov	x0, x19
	mov	x2, x20
	bl	_rza1_set_bit
Lloh18:
	adrp	x8, _RZA1_PFCEA_REG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _RZA1_PFCEA_REG@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _MUX_FUNC_PFCEA_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MUX_FUNC_PFCEA_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	and	w3, w8, w21
	mov	x0, x19
	mov	x2, x20
	bl	_rza1_set_bit
Lloh24:
	adrp	x8, _MUX_FLAGS_SWIO_INPUT@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MUX_FLAGS_SWIO_INPUT@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _MUX_FLAGS_SWIO_OUTPUT@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MUX_FLAGS_SWIO_OUTPUT@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w9, w9, w8
	tst	w9, w22
	b.eq	LBB0_4
; %bb.3:
Lloh30:
	adrp	x9, _RZA1_PM_REG@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RZA1_PM_REG@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x9]
	and	w3, w8, w22
	mov	x0, x19
	mov	x2, x20
	b	LBB0_5
LBB0_4:
Lloh33:
	adrp	x8, _RZA1_PIPC_REG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _RZA1_PIPC_REG@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	mov	w3, #1
LBB0_5:
	bl	_rza1_set_bit
Lloh36:
	adrp	x8, _RZA1_PMC_REG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _RZA1_PMC_REG@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	mov	w3, #1
	bl	_rza1_set_bit
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.cfi_endproc
                                        ; -- End function
	.comm	_MUX_FLAGS_BIDIR,4,2            ; @MUX_FLAGS_BIDIR
	.comm	_RZA1_PBDC_REG,4,2              ; @RZA1_PBDC_REG
	.comm	_RZA1_PFC_REG,4,2               ; @RZA1_PFC_REG
	.comm	_MUX_FUNC_PFC_MASK,4,2          ; @MUX_FUNC_PFC_MASK
	.comm	_RZA1_PFCE_REG,4,2              ; @RZA1_PFCE_REG
	.comm	_MUX_FUNC_PFCE_MASK,4,2         ; @MUX_FUNC_PFCE_MASK
	.comm	_RZA1_PFCEA_REG,4,2             ; @RZA1_PFCEA_REG
	.comm	_MUX_FUNC_PFCEA_MASK,4,2        ; @MUX_FUNC_PFCEA_MASK
	.comm	_MUX_FLAGS_SWIO_INPUT,4,2       ; @MUX_FLAGS_SWIO_INPUT
	.comm	_MUX_FLAGS_SWIO_OUTPUT,4,2      ; @MUX_FLAGS_SWIO_OUTPUT
	.comm	_RZA1_PM_REG,4,2                ; @RZA1_PM_REG
	.comm	_RZA1_PIPC_REG,4,2              ; @RZA1_PIPC_REG
	.comm	_RZA1_PMC_REG,4,2               ; @RZA1_PMC_REG
	.no_dead_strip	_rza1_pin_mux_single
.subsections_via_symbols
