	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_get_xbar_config
_tegra_pcie_get_xbar_config:            ## @tegra_pcie_get_xbar_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movl	%esi, %r12d
	movq	(%rdi), %r15
	movq	(%r15), %rbx
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	callq	_of_device_is_compatible
	testq	%rax, %rax
	je	LBB0_10
## %bb.1:
	cmpl	$65794, %r12d                   ## imm = 0x10102
	je	LBB0_5
## %bb.2:
	cmpl	$65793, %r12d                   ## imm = 0x10101
	je	LBB0_8
## %bb.3:
	cmpl	$65540, %r12d                   ## imm = 0x10004
	jne	LBB0_9
## %bb.4:
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_10:
	leaq	L_.str.5(%rip), %rsi
	movq	%rbx, %rdi
	callq	_of_device_is_compatible
	testq	%rax, %rax
	jne	LBB0_12
## %bb.11:
	leaq	L_.str.6(%rip), %rsi
	movq	%rbx, %rdi
	callq	_of_device_is_compatible
	testq	%rax, %rax
	je	LBB0_16
LBB0_12:
	cmpl	$258, %r12d                     ## imm = 0x102
	je	LBB0_15
## %bb.13:
	cmpl	$260, %r12d                     ## imm = 0x104
	jne	LBB0_28
## %bb.14:
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_5:
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_6
LBB0_8:
	leaq	L_.str.3(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_9:
	leaq	L_.str.4(%rip), %rsi
LBB0_6:
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_15:
	leaq	L_.str.7(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1@GOTPCREL(%rip), %rax
LBB0_7:
	movl	(%rax), %eax
	movl	%eax, (%r14)
	xorl	%eax, %eax
LBB0_29:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	leaq	L_.str.8(%rip), %rsi
	movq	%rbx, %rdi
	callq	_of_device_is_compatible
	testq	%rax, %rax
	je	LBB0_23
## %bb.17:
	cmpl	$131586, %r12d                  ## imm = 0x20202
	je	LBB0_21
## %bb.18:
	cmpl	$65796, %r12d                   ## imm = 0x10104
	je	LBB0_22
## %bb.19:
	cmpl	$516, %r12d                     ## imm = 0x204
	jne	LBB0_28
## %bb.20:
	leaq	L_.str.9(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_23:
	leaq	L_.str.12(%rip), %rsi
	movq	%rbx, %rdi
	callq	_of_device_is_compatible
	testq	%rax, %rax
	je	LBB0_28
## %bb.24:
	cmpl	$514, %r12d                     ## imm = 0x202
	je	LBB0_27
## %bb.25:
	cmpl	$4, %r12d
	jne	LBB0_28
## %bb.26:
	leaq	L_.str.13(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_28:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_29
LBB0_21:
	leaq	L_.str.10(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_22:
	leaq	L_.str.11(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411@GOTPCREL(%rip), %rax
	jmp	LBB0_7
LBB0_27:
	leaq	L_.str.14(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_info
	movq	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL@GOTPCREL(%rip), %rax
	jmp	LBB0_7
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"nvidia,tegra186-pcie"

L_.str.1:                               ## @.str.1
	.asciz	"4x1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401
L_.str.2:                               ## @.str.2
	.asciz	"2x1, 1X1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211
L_.str.3:                               ## @.str.3
	.asciz	"1x1, 1x1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111
L_.str.4:                               ## @.str.4
	.asciz	"wrong configuration updated in DT, switching to default 2x1, 1x1, 1x1 configuration\n"

L_.str.5:                               ## @.str.5
	.asciz	"nvidia,tegra124-pcie"

L_.str.6:                               ## @.str.6
	.asciz	"nvidia,tegra210-pcie"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1
L_.str.7:                               ## @.str.7
	.asciz	"2x1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1
L_.str.8:                               ## @.str.8
	.asciz	"nvidia,tegra30-pcie"

L_.str.9:                               ## @.str.9
	.asciz	"4x1, 2x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420
L_.str.10:                              ## @.str.10
	.asciz	"2x3 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222
L_.str.11:                              ## @.str.11
	.asciz	"4x1, 1x2 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411
L_.str.12:                              ## @.str.12
	.asciz	"nvidia,tegra20-pcie"

L_.str.13:                              ## @.str.13
	.asciz	"single-mode configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE
L_.str.14:                              ## @.str.14
	.asciz	"dual-mode configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL,4,2 ## @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	_tegra_pcie_get_xbar_config
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_get_xbar_config
_tegra_pcie_get_xbar_config:            ; @tegra_pcie_get_xbar_config
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x21, x1
	ldr	x20, [x0]
	ldr	x22, [x20]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x22
	bl	_of_device_is_compatible
	cbz	x0, LBB0_5
; %bb.1:
	mov	w8, #258
	movk	w8, #1, lsl #16
	cmp	w21, w8
	b.eq	LBB0_10
; %bb.2:
	mov	w8, #257
	movk	w8, #1, lsl #16
	cmp	w21, w8
	b.eq	LBB0_11
; %bb.3:
	mov	w8, #4
	movk	w8, #1, lsl #16
	cmp	w21, w8
	b.ne	LBB0_12
; %bb.4:
Lloh2:
	adrp	x1, l_.str.1@PAGE
Lloh3:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh4:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401@GOTPAGEOFF]
	b	LBB0_15
LBB0_5:
Lloh6:
	adrp	x1, l_.str.5@PAGE
Lloh7:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x22
	bl	_of_device_is_compatible
	cbnz	x0, LBB0_7
; %bb.6:
Lloh8:
	adrp	x1, l_.str.6@PAGE
Lloh9:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x22
	bl	_of_device_is_compatible
	cbz	x0, LBB0_17
LBB0_7:
	cmp	w21, #258
	b.eq	LBB0_14
; %bb.8:
	cmp	w21, #260
	b.ne	LBB0_26
; %bb.9:
Lloh10:
	adrp	x1, l_.str.1@PAGE
Lloh11:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh12:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1@GOTPAGEOFF]
	b	LBB0_15
LBB0_10:
Lloh14:
	adrp	x1, l_.str.2@PAGE
Lloh15:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_13
LBB0_11:
Lloh16:
	adrp	x1, l_.str.3@PAGE
Lloh17:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh18:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111@GOTPAGEOFF]
	b	LBB0_15
LBB0_12:
Lloh20:
	adrp	x1, l_.str.4@PAGE
Lloh21:
	add	x1, x1, l_.str.4@PAGEOFF
LBB0_13:
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh22:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211@GOTPAGE
Lloh23:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211@GOTPAGEOFF]
	b	LBB0_15
LBB0_14:
Lloh24:
	adrp	x1, l_.str.7@PAGE
Lloh25:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh26:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1@GOTPAGEOFF]
LBB0_15:
	ldr	w8, [x8]
	str	w8, [x19]
LBB0_16:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_17:
Lloh28:
	adrp	x1, l_.str.8@PAGE
Lloh29:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x22
	bl	_of_device_is_compatible
	cbz	x0, LBB0_22
; %bb.18:
	mov	w8, #514
	movk	w8, #2, lsl #16
	cmp	w21, w8
	b.eq	LBB0_27
; %bb.19:
	mov	w8, #260
	movk	w8, #1, lsl #16
	cmp	w21, w8
	b.eq	LBB0_28
; %bb.20:
	cmp	w21, #516
	b.ne	LBB0_26
; %bb.21:
Lloh30:
	adrp	x1, l_.str.9@PAGE
Lloh31:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh32:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420@GOTPAGEOFF]
	b	LBB0_15
LBB0_22:
Lloh34:
	adrp	x1, l_.str.12@PAGE
Lloh35:
	add	x1, x1, l_.str.12@PAGEOFF
	mov	x0, x22
	bl	_of_device_is_compatible
	cbz	x0, LBB0_26
; %bb.23:
	cmp	w21, #514
	b.eq	LBB0_29
; %bb.24:
	cmp	w21, #4
	b.ne	LBB0_26
; %bb.25:
Lloh36:
	adrp	x1, l_.str.13@PAGE
Lloh37:
	add	x1, x1, l_.str.13@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh38:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE@GOTPAGE
Lloh39:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE@GOTPAGEOFF]
	b	LBB0_15
LBB0_26:
Lloh40:
	adrp	x8, _EINVAL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_16
LBB0_27:
Lloh43:
	adrp	x1, l_.str.10@PAGE
Lloh44:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh45:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222@GOTPAGE
Lloh46:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222@GOTPAGEOFF]
	b	LBB0_15
LBB0_28:
Lloh47:
	adrp	x1, l_.str.11@PAGE
Lloh48:
	add	x1, x1, l_.str.11@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh49:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411@GOTPAGE
Lloh50:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411@GOTPAGEOFF]
	b	LBB0_15
LBB0_29:
Lloh51:
	adrp	x1, l_.str.14@PAGE
Lloh52:
	add	x1, x1, l_.str.14@PAGEOFF
	mov	x0, x20
	bl	_dev_info
	mov	w0, #0
Lloh53:
	adrp	x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL@GOTPAGEOFF]
	b	LBB0_15
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpAdd	Lloh30, Lloh31
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpAdd	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpAdd	Lloh51, Lloh52
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"nvidia,tegra186-pcie"

l_.str.1:                               ; @.str.1
	.asciz	"4x1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401
l_.str.2:                               ; @.str.2
	.asciz	"2x1, 1X1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211
l_.str.3:                               ; @.str.3
	.asciz	"1x1, 1x1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111
l_.str.4:                               ; @.str.4
	.asciz	"wrong configuration updated in DT, switching to default 2x1, 1x1, 1x1 configuration\n"

l_.str.5:                               ; @.str.5
	.asciz	"nvidia,tegra124-pcie"

l_.str.6:                               ; @.str.6
	.asciz	"nvidia,tegra210-pcie"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1
l_.str.7:                               ; @.str.7
	.asciz	"2x1, 1x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1
l_.str.8:                               ; @.str.8
	.asciz	"nvidia,tegra30-pcie"

l_.str.9:                               ; @.str.9
	.asciz	"4x1, 2x1 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420
l_.str.10:                              ; @.str.10
	.asciz	"2x3 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222
l_.str.11:                              ; @.str.11
	.asciz	"4x1, 1x2 configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411
l_.str.12:                              ; @.str.12
	.asciz	"nvidia,tegra20-pcie"

l_.str.13:                              ; @.str.13
	.asciz	"single-mode configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE
l_.str.14:                              ; @.str.14
	.asciz	"dual-mode configuration\n"

	.comm	_AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL,4,2 ; @AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	_tegra_pcie_get_xbar_config
.subsections_via_symbols
