	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function imx6_pcie_deassert_core_reset
_imx6_pcie_deassert_core_reset:         ## @imx6_pcie_deassert_core_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %rdi
	movq	64(%rbx), %rax
	movq	(%rax), %r14
	testq	%rdi, %rdi
	je	LBB0_5
## %bb.1:
	callq	_regulator_is_enabled
	testq	%rax, %rax
	je	LBB0_2
LBB0_5:
	movl	16(%rbx), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_11
## %bb.6:
	leaq	L_.str.1(%rip), %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_7
LBB0_11:
	movl	20(%rbx), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_14
## %bb.12:
	leaq	L_.str.2(%rip), %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_13
LBB0_2:
	movq	8(%rbx), %rdi
	callq	_regulator_enable
	testl	%eax, %eax
	je	LBB0_5
## %bb.3:
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_4
LBB0_14:
	movl	24(%rbx), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_17
## %bb.15:
	leaq	L_.str.3(%rip), %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_16
LBB0_17:
	movq	%rbx, %rdi
	callq	_imx6_pcie_enable_ref_clk
	testl	%eax, %eax
	je	LBB0_19
## %bb.18:
	leaq	L_.str.4(%rip), %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movl	24(%rbx), %edi
	callq	_clk_disable_unprepare
LBB0_16:
	movl	20(%rbx), %edi
	callq	_clk_disable_unprepare
LBB0_13:
	movl	16(%rbx), %edi
	callq	_clk_disable_unprepare
LBB0_7:
	movq	8(%rbx), %rdi
	testq	%rdi, %rdi
	je	LBB0_30
## %bb.8:
	callq	_regulator_is_enabled
	testq	%rax, %rax
	jle	LBB0_30
## %bb.9:
	movq	8(%rbx), %rdi
	callq	_regulator_disable
	testl	%eax, %eax
	je	LBB0_30
## %bb.10:
	leaq	L_.str.6(%rip), %rsi
LBB0_4:
	movq	%r14, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_dev_err                        ## TAILCALL
LBB0_19:
	movl	$200, %edi
	movl	$500, %esi                      ## imm = 0x1F4
	callq	_usleep_range
	movl	56(%rbx), %edi
	callq	_gpio_is_valid
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	movl	(%rbx), %esi
	movl	56(%rbx), %edi
	callq	_gpio_set_value_cansleep
	movl	$100, %edi
	callq	_msleep
	movl	56(%rbx), %edi
	xorl	%esi, %esi
	cmpl	$0, (%rbx)
	sete	%sil
	callq	_gpio_set_value_cansleep
LBB0_21:
	movq	48(%rbx), %rax
	movl	(%rax), %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_30
## %bb.22:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_23:
	movl	40(%rbx), %edi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_reset_control_deassert         ## TAILCALL
LBB0_30:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_24:
	movl	40(%rbx), %edi
	callq	_reset_control_deassert
	movq	32(%rbx), %rdi
	callq	_likely
	testl	%eax, %eax
	je	LBB0_26
## %bb.25:
	movq	_PCIE_PHY_CMN_REG4_DCC_FB_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PCIE_PHY_CMN_REG4@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	callq	_writel
	movq	_PCIE_PHY_CMN_REG24_RX_EQ_SEL@GOTPCREL(%rip), %rax
	movq	_PCIE_PHY_CMN_REG24_RX_EQ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	orl	(%rax), %edi
	movq	_PCIE_PHY_CMN_REG24@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	callq	_writel
	movq	_PCIE_PHY_CMN_REG26_ATT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_PCIE_PHY_CMN_REG26@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	32(%rbx), %rsi
	callq	_writel
	jmp	LBB0_27
LBB0_28:
	movl	28(%rbx), %edi
	movq	_IOMUXC_GPR5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX6SX_GPR5_PCIE_BTNRST_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
LBB0_29:
	movl	28(%rbx), %edi
	movq	_IOMUXC_GPR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX6Q_GPR1_PCIE_SW_RST@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	$200, %edi
	movl	$500, %esi                      ## imm = 0x1F4
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_usleep_range                   ## TAILCALL
LBB0_26:
	leaq	L_.str.5(%rip), %rsi
	movq	%r14, %rdi
	callq	_dev_warn
LBB0_27:
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_imx7d_pcie_wait_for_phy_pll_lock ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_24, LBB0_24-LJTI0_0
.set L0_0_set_28, LBB0_28-LJTI0_0
.set L0_0_set_29, LBB0_29-LJTI0_0
LJTI0_0:
	.long	L0_0_set_23
	.long	L0_0_set_24
	.long	L0_0_set_28
	.long	L0_0_set_29
	.end_data_region
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to enable vpcie regulator: %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"unable to enable pcie_phy clock\n"

L_.str.2:                               ## @.str.2
	.asciz	"unable to enable pcie_bus clock\n"

L_.str.3:                               ## @.str.3
	.asciz	"unable to enable pcie clock\n"

L_.str.4:                               ## @.str.4
	.asciz	"unable to enable pcie ref clock\n"

	.comm	_PCIE_PHY_CMN_REG4_DCC_FB_EN,4,2 ## @PCIE_PHY_CMN_REG4_DCC_FB_EN
	.comm	_PCIE_PHY_CMN_REG4,8,3          ## @PCIE_PHY_CMN_REG4
	.comm	_PCIE_PHY_CMN_REG24_RX_EQ_SEL,4,2 ## @PCIE_PHY_CMN_REG24_RX_EQ_SEL
	.comm	_PCIE_PHY_CMN_REG24_RX_EQ,4,2   ## @PCIE_PHY_CMN_REG24_RX_EQ
	.comm	_PCIE_PHY_CMN_REG24,8,3         ## @PCIE_PHY_CMN_REG24
	.comm	_PCIE_PHY_CMN_REG26_ATT_MODE,4,2 ## @PCIE_PHY_CMN_REG26_ATT_MODE
	.comm	_PCIE_PHY_CMN_REG26,8,3         ## @PCIE_PHY_CMN_REG26
L_.str.5:                               ## @.str.5
	.asciz	"Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"

	.comm	_IOMUXC_GPR5,4,2                ## @IOMUXC_GPR5
	.comm	_IMX6SX_GPR5_PCIE_BTNRST_RESET,4,2 ## @IMX6SX_GPR5_PCIE_BTNRST_RESET
	.comm	_IOMUXC_GPR1,4,2                ## @IOMUXC_GPR1
	.comm	_IMX6Q_GPR1_PCIE_SW_RST,4,2     ## @IMX6Q_GPR1_PCIE_SW_RST
L_.str.6:                               ## @.str.6
	.asciz	"failed to disable vpcie regulator: %d\n"

	.no_dead_strip	_imx6_pcie_deassert_core_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function imx6_pcie_deassert_core_reset
_imx6_pcie_deassert_core_reset:         ; @imx6_pcie_deassert_core_reset
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x8, [x0, #64]
	ldr	x20, [x8]
	ldr	x0, [x0, #8]
	cbz	x0, LBB0_2
; %bb.1:
	bl	_regulator_is_enabled
	cbz	x0, LBB0_6
LBB0_2:
	ldr	w0, [x19, #16]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_4
; %bb.3:
Lloh0:
	adrp	x1, l_.str.1@PAGE
Lloh1:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x20
	bl	_dev_err
	ldr	x0, [x19, #8]
	cbnz	x0, LBB0_14
	b	LBB0_18
LBB0_4:
	ldr	w0, [x19, #20]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_8
; %bb.5:
Lloh2:
	adrp	x1, l_.str.2@PAGE
Lloh3:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x20
	bl	_dev_err
	b	LBB0_13
LBB0_6:
	ldr	x0, [x19, #8]
	bl	_regulator_enable
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_2
; %bb.7:
	str	x0, [sp]
Lloh4:
	adrp	x1, l_.str@PAGE
Lloh5:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_17
LBB0_8:
	ldr	w0, [x19, #24]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_10
; %bb.9:
Lloh6:
	adrp	x1, l_.str.3@PAGE
Lloh7:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x20
	bl	_dev_err
	b	LBB0_12
LBB0_10:
	mov	x0, x19
	bl	_imx6_pcie_enable_ref_clk
	cbz	w0, LBB0_19
; %bb.11:
Lloh8:
	adrp	x1, l_.str.4@PAGE
Lloh9:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x20
	bl	_dev_err
	ldr	w0, [x19, #24]
	bl	_clk_disable_unprepare
LBB0_12:
	ldr	w0, [x19, #20]
	bl	_clk_disable_unprepare
LBB0_13:
	ldr	w0, [x19, #16]
	bl	_clk_disable_unprepare
	ldr	x0, [x19, #8]
	cbz	x0, LBB0_18
LBB0_14:
	bl	_regulator_is_enabled
	cmp	x0, #1
	b.lt	LBB0_18
; %bb.15:
	ldr	x0, [x19, #8]
	bl	_regulator_disable
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_18
; %bb.16:
	str	x0, [sp]
Lloh10:
	adrp	x1, l_.str.6@PAGE
Lloh11:
	add	x1, x1, l_.str.6@PAGEOFF
LBB0_17:
	mov	x0, x20
	bl	_dev_err
LBB0_18:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
LBB0_19:
	mov	w0, #200
	mov	w1, #500
	bl	_usleep_range
	ldr	w0, [x19, #56]
	bl	_gpio_is_valid
	cbz	x0, LBB0_21
; %bb.20:
	ldr	w0, [x19, #56]
	ldr	w1, [x19]
	bl	_gpio_set_value_cansleep
	mov	w0, #100
	bl	_msleep
	ldr	w0, [x19, #56]
	ldr	w8, [x19]
	cmp	w8, #0
	cset	w1, eq
	bl	_gpio_set_value_cansleep
LBB0_21:
	ldr	x8, [x19, #48]
	ldr	w8, [x8]
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_18
; %bb.22:
Lloh12:
	adrp	x9, lJTI0_0@PAGE
Lloh13:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_23
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_23:
	ldr	w0, [x19, #40]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_reset_control_deassert
LBB0_24:
	ldr	w0, [x19, #40]
	bl	_reset_control_deassert
	ldr	x0, [x19, #32]
	bl	_likely
	cbz	w0, LBB0_28
; %bb.25:
Lloh14:
	adrp	x8, _PCIE_PHY_CMN_REG4_DCC_FB_EN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PCIE_PHY_CMN_REG4_DCC_FB_EN@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	ldr	x8, [x19, #32]
Lloh17:
	adrp	x9, _PCIE_PHY_CMN_REG4@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PCIE_PHY_CMN_REG4@GOTPAGEOFF]
Lloh19:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh20:
	adrp	x8, _PCIE_PHY_CMN_REG24_RX_EQ_SEL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PCIE_PHY_CMN_REG24_RX_EQ_SEL@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
Lloh23:
	adrp	x9, _PCIE_PHY_CMN_REG24_RX_EQ@GOTPAGE
Lloh24:
	ldr	x9, [x9, _PCIE_PHY_CMN_REG24_RX_EQ@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w0, w9, w8
	ldr	x8, [x19, #32]
Lloh26:
	adrp	x9, _PCIE_PHY_CMN_REG24@GOTPAGE
Lloh27:
	ldr	x9, [x9, _PCIE_PHY_CMN_REG24@GOTPAGEOFF]
Lloh28:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
Lloh29:
	adrp	x8, _PCIE_PHY_CMN_REG26_ATT_MODE@GOTPAGE
Lloh30:
	ldr	x8, [x8, _PCIE_PHY_CMN_REG26_ATT_MODE@GOTPAGEOFF]
Lloh31:
	ldr	w0, [x8]
	ldr	x8, [x19, #32]
Lloh32:
	adrp	x9, _PCIE_PHY_CMN_REG26@GOTPAGE
Lloh33:
	ldr	x9, [x9, _PCIE_PHY_CMN_REG26@GOTPAGEOFF]
Lloh34:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel
	b	LBB0_29
LBB0_26:
	ldr	w0, [x19, #28]
Lloh35:
	adrp	x8, _IOMUXC_GPR5@GOTPAGE
Lloh36:
	ldr	x8, [x8, _IOMUXC_GPR5@GOTPAGEOFF]
Lloh37:
	adrp	x9, _IMX6SX_GPR5_PCIE_BTNRST_RESET@GOTPAGE
Lloh38:
	ldr	x9, [x9, _IMX6SX_GPR5_PCIE_BTNRST_RESET@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
Lloh40:
	ldr	w2, [x9]
	mov	w3, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_regmap_update_bits
LBB0_27:
	ldr	w0, [x19, #28]
Lloh41:
	adrp	x8, _IOMUXC_GPR1@GOTPAGE
Lloh42:
	ldr	x8, [x8, _IOMUXC_GPR1@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
Lloh44:
	adrp	x8, _IMX6Q_GPR1_PCIE_SW_RST@GOTPAGE
Lloh45:
	ldr	x8, [x8, _IMX6Q_GPR1_PCIE_SW_RST@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	mov	w0, #200
	mov	w1, #500
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_usleep_range
LBB0_28:
Lloh47:
	adrp	x1, l_.str.5@PAGE
Lloh48:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x20
	bl	_dev_warn
LBB0_29:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	b	_imx7d_pcie_wait_for_phy_pll_lock
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh39
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpAdd	Lloh47, Lloh48
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_23-LBB0_23)>>2
	.byte	(LBB0_24-LBB0_23)>>2
	.byte	(LBB0_26-LBB0_23)>>2
	.byte	(LBB0_27-LBB0_23)>>2
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to enable vpcie regulator: %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"unable to enable pcie_phy clock\n"

l_.str.2:                               ; @.str.2
	.asciz	"unable to enable pcie_bus clock\n"

l_.str.3:                               ; @.str.3
	.asciz	"unable to enable pcie clock\n"

l_.str.4:                               ; @.str.4
	.asciz	"unable to enable pcie ref clock\n"

	.comm	_PCIE_PHY_CMN_REG4_DCC_FB_EN,4,2 ; @PCIE_PHY_CMN_REG4_DCC_FB_EN
	.comm	_PCIE_PHY_CMN_REG4,8,3          ; @PCIE_PHY_CMN_REG4
	.comm	_PCIE_PHY_CMN_REG24_RX_EQ_SEL,4,2 ; @PCIE_PHY_CMN_REG24_RX_EQ_SEL
	.comm	_PCIE_PHY_CMN_REG24_RX_EQ,4,2   ; @PCIE_PHY_CMN_REG24_RX_EQ
	.comm	_PCIE_PHY_CMN_REG24,8,3         ; @PCIE_PHY_CMN_REG24
	.comm	_PCIE_PHY_CMN_REG26_ATT_MODE,4,2 ; @PCIE_PHY_CMN_REG26_ATT_MODE
	.comm	_PCIE_PHY_CMN_REG26,8,3         ; @PCIE_PHY_CMN_REG26
l_.str.5:                               ; @.str.5
	.asciz	"Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"

	.comm	_IOMUXC_GPR5,4,2                ; @IOMUXC_GPR5
	.comm	_IMX6SX_GPR5_PCIE_BTNRST_RESET,4,2 ; @IMX6SX_GPR5_PCIE_BTNRST_RESET
	.comm	_IOMUXC_GPR1,4,2                ; @IOMUXC_GPR1
	.comm	_IMX6Q_GPR1_PCIE_SW_RST,4,2     ; @IMX6Q_GPR1_PCIE_SW_RST
l_.str.6:                               ; @.str.6
	.asciz	"failed to disable vpcie regulator: %d\n"

	.no_dead_strip	_imx6_pcie_deassert_core_reset
.subsections_via_symbols
