	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function _il_set_rxon_ht
__il_set_rxon_ht:                       ## @_il_set_rxon_ht
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	cmpl	$0, 8(%rdi)
	je	LBB0_17
## %bb.1:
	movl	(%rbx), %edi
	movq	_RXON_FLG_HT_OPERATING_MODE_POS@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edi
	callq	_cpu_to_le32
	orl	24(%rbx), %eax
	movq	_RXON_FLG_CHANNEL_MODE_MSK@GOTPCREL(%rip), %rcx
	movq	_RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	%edx, 24(%rbx)
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_il_is_ht40_tx_allowed
	testq	%rax, %rax
	je	LBB0_13
## %bb.2:
	movl	(%rbx), %eax
	movq	_IEEE80211_HT_OP_MODE_PROTECTION_20MHZ@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_7
## %bb.3:
	movq	_RXON_FLG_CHANNEL_MODE_PURE_40@GOTPCREL(%rip), %rdx
	movl	4(%rbx), %ecx
	movl	24(%rbx), %eax
	orl	(%rdx), %eax
	movl	%eax, 24(%rbx)
	cmpl	$129, %ecx
	je	LBB0_6
## %bb.4:
	cmpl	$130, %ecx
	jne	LBB0_14
## %bb.5:
	movl	(%r14), %ecx
	notl	%ecx
	andl	%ecx, %eax
	movl	%eax, 24(%rbx)
	jmp	LBB0_14
LBB0_17:
	movq	_RXON_FLG_CHANNEL_MODE_MSK@GOTPCREL(%rip), %rax
	movq	_RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_RXON_FLG_HT40_PROT_MSK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_RXON_FLG_HT_PROT_MSK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, 24(%rbx)
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
LBB0_13:
	movq	_RXON_FLG_CHANNEL_MODE_LEGACY@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 24(%rbx)
	jmp	LBB0_14
LBB0_7:
	movl	4(%rbx), %eax
	cmpl	$129, %eax
	je	LBB0_10
## %bb.8:
	cmpl	$130, %eax
	jne	LBB0_12
## %bb.9:
	movl	(%r14), %eax
	notl	%eax
	andl	24(%rbx), %eax
	jmp	LBB0_11
LBB0_6:
	orl	(%r14), %eax
	movl	%eax, 24(%rbx)
	jmp	LBB0_14
LBB0_10:
	movl	24(%rbx), %eax
	orl	(%r14), %eax
LBB0_11:
	movq	_RXON_FLG_CHANNEL_MODE_MIXED@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, 24(%rbx)
	jmp	LBB0_14
LBB0_12:
	leaq	L_.str(%rip), %rdi
	callq	_IL_ERR
LBB0_14:
	movq	16(%rbx), %rax
	movq	(%rax), %rax
	testq	%rax, %rax
	je	LBB0_16
## %bb.15:
	movq	%rbx, %rdi
	callq	*%rax
LBB0_16:
	movl	24(%rbx), %edi
	callq	_le32_to_cpu
	movl	(%rbx), %edx
	movl	4(%rbx), %ecx
	leaq	L_.str.1(%rip), %rdi
	movl	%eax, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_D_ASSOC                        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RXON_FLG_CHANNEL_MODE_MSK,4,2  ## @RXON_FLG_CHANNEL_MODE_MSK
	.comm	_RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK,4,2 ## @RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
	.comm	_RXON_FLG_HT40_PROT_MSK,4,2     ## @RXON_FLG_HT40_PROT_MSK
	.comm	_RXON_FLG_HT_PROT_MSK,4,2       ## @RXON_FLG_HT_PROT_MSK
	.comm	_RXON_FLG_HT_OPERATING_MODE_POS,4,2 ## @RXON_FLG_HT_OPERATING_MODE_POS
	.comm	_IEEE80211_HT_OP_MODE_PROTECTION_20MHZ,4,2 ## @IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
	.comm	_RXON_FLG_CHANNEL_MODE_PURE_40,4,2 ## @RXON_FLG_CHANNEL_MODE_PURE_40
	.comm	_RXON_FLG_CHANNEL_MODE_MIXED,4,2 ## @RXON_FLG_CHANNEL_MODE_MIXED
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"invalid extension channel offset\n"

	.comm	_RXON_FLG_CHANNEL_MODE_LEGACY,4,2 ## @RXON_FLG_CHANNEL_MODE_LEGACY
L_.str.1:                               ## @.str.1
	.asciz	"rxon flags 0x%X operation mode :0x%X extension channel offset 0x%x\n"

	.no_dead_strip	__il_set_rxon_ht
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function _il_set_rxon_ht
__il_set_rxon_ht:                       ; @_il_set_rxon_ht
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	w8, [x0, #8]
	cbz	w8, LBB0_6
; %bb.1:
	ldr	w8, [x19]
Lloh0:
	adrp	x9, _RXON_FLG_HT_OPERATING_MODE_POS@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RXON_FLG_HT_OPERATING_MODE_POS@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	lsl	w0, w8, w9
	bl	_cpu_to_le32
	ldr	w8, [x19, #24]
	orr	w8, w8, w0
Lloh3:
	adrp	x9, _RXON_FLG_CHANNEL_MODE_MSK@GOTPAGE
Lloh4:
	ldr	x9, [x9, _RXON_FLG_CHANNEL_MODE_MSK@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x20, _RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK@GOTPAGE
Lloh7:
	ldr	x20, [x20, _RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK@GOTPAGEOFF]
	ldr	w10, [x20]
	orr	w9, w10, w9
	bic	w8, w8, w9
	str	w8, [x19, #24]
	mov	x0, x19
	mov	x1, #0
	bl	_il_is_ht40_tx_allowed
	cbz	x0, LBB0_7
; %bb.2:
	ldr	w8, [x19]
Lloh8:
	adrp	x9, _IEEE80211_HT_OP_MODE_PROTECTION_20MHZ@GOTPAGE
Lloh9:
	ldr	x9, [x9, _IEEE80211_HT_OP_MODE_PROTECTION_20MHZ@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	cmp	w8, w9
	b.ne	LBB0_8
; %bb.3:
Lloh11:
	adrp	x8, _RXON_FLG_CHANNEL_MODE_PURE_40@GOTPAGE
Lloh12:
	ldr	x8, [x8, _RXON_FLG_CHANNEL_MODE_PURE_40@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	ldr	w9, [x19, #24]
	orr	w8, w9, w8
	str	w8, [x19, #24]
	ldr	w9, [x19, #4]
	cmp	w9, #129
	b.eq	LBB0_11
; %bb.4:
	cmp	w9, #130
	b.ne	LBB0_16
; %bb.5:
	ldr	w9, [x20]
	bic	w8, w8, w9
	b	LBB0_15
LBB0_6:
Lloh14:
	adrp	x8, _RXON_FLG_CHANNEL_MODE_MSK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RXON_FLG_CHANNEL_MODE_MSK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh20:
	adrp	x9, _RXON_FLG_HT40_PROT_MSK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _RXON_FLG_HT40_PROT_MSK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
Lloh23:
	adrp	x10, _RXON_FLG_HT_PROT_MSK@GOTPAGE
Lloh24:
	ldr	x10, [x10, _RXON_FLG_HT_PROT_MSK@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh25:
	ldr	w9, [x10]
	orr	w8, w8, w9
	ldr	w9, [x19, #24]
	bic	w8, w9, w8
	str	w8, [x19, #24]
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_7:
Lloh26:
	adrp	x8, _RXON_FLG_CHANNEL_MODE_LEGACY@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RXON_FLG_CHANNEL_MODE_LEGACY@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	ldr	w9, [x19, #24]
	b	LBB0_14
LBB0_8:
	ldr	w8, [x19, #4]
	cmp	w8, #129
	b.eq	LBB0_12
; %bb.9:
	cmp	w8, #130
	b.ne	LBB0_19
; %bb.10:
	ldr	w8, [x20]
	ldr	w9, [x19, #24]
	bic	w8, w9, w8
	b	LBB0_13
LBB0_11:
	ldr	w9, [x20]
	b	LBB0_14
LBB0_12:
	ldr	w8, [x20]
	ldr	w9, [x19, #24]
	orr	w8, w9, w8
LBB0_13:
Lloh29:
	adrp	x9, _RXON_FLG_CHANNEL_MODE_MIXED@GOTPAGE
Lloh30:
	ldr	x9, [x9, _RXON_FLG_CHANNEL_MODE_MIXED@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
LBB0_14:
	orr	w8, w9, w8
LBB0_15:
	str	w8, [x19, #24]
LBB0_16:
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
	cbz	x8, LBB0_18
; %bb.17:
	mov	x0, x19
	blr	x8
LBB0_18:
	ldr	w0, [x19, #24]
	bl	_le32_to_cpu
	mov	x1, x0
	ldp	w2, w3, [x19]
Lloh32:
	adrp	x0, l_.str.1@PAGE
Lloh33:
	add	x0, x0, l_.str.1@PAGEOFF
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_D_ASSOC
LBB0_19:
Lloh34:
	adrp	x0, l_.str@PAGE
Lloh35:
	add	x0, x0, l_.str@PAGEOFF
	bl	_IL_ERR
	b	LBB0_16
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpAdd	Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_RXON_FLG_CHANNEL_MODE_MSK,4,2  ; @RXON_FLG_CHANNEL_MODE_MSK
	.comm	_RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK,4,2 ; @RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
	.comm	_RXON_FLG_HT40_PROT_MSK,4,2     ; @RXON_FLG_HT40_PROT_MSK
	.comm	_RXON_FLG_HT_PROT_MSK,4,2       ; @RXON_FLG_HT_PROT_MSK
	.comm	_RXON_FLG_HT_OPERATING_MODE_POS,4,2 ; @RXON_FLG_HT_OPERATING_MODE_POS
	.comm	_IEEE80211_HT_OP_MODE_PROTECTION_20MHZ,4,2 ; @IEEE80211_HT_OP_MODE_PROTECTION_20MHZ
	.comm	_RXON_FLG_CHANNEL_MODE_PURE_40,4,2 ; @RXON_FLG_CHANNEL_MODE_PURE_40
	.comm	_RXON_FLG_CHANNEL_MODE_MIXED,4,2 ; @RXON_FLG_CHANNEL_MODE_MIXED
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"invalid extension channel offset\n"

	.comm	_RXON_FLG_CHANNEL_MODE_LEGACY,4,2 ; @RXON_FLG_CHANNEL_MODE_LEGACY
l_.str.1:                               ; @.str.1
	.asciz	"rxon flags 0x%X operation mode :0x%X extension channel offset 0x%x\n"

	.no_dead_strip	__il_set_rxon_ht
.subsections_via_symbols
