	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dw_pcie_ep_set_bar
_dw_pcie_ep_set_bar:                    ## @dw_pcie_ep_set_bar
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %rbx
	callq	_epc_get_drvdata
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	_to_dw_pcie_from_ep
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movl	(%rbx), %esi
	movl	16(%rbx), %r15d
	movq	_PCI_BASE_ADDRESS_0@GOTPCREL(%rip), %rax
	leal	(,%rsi,4), %r14d
	movq	_PCI_BASE_ADDRESS_SPACE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%r15d, %ecx
	jne	LBB0_1
## %bb.2:
	movq	_DW_PCIE_AS_MEM@GOTPCREL(%rip), %rcx
	jmp	LBB0_3
LBB0_1:
	movq	_DW_PCIE_AS_IO@GOTPCREL(%rip), %rcx
LBB0_3:
	movq	8(%rbx), %r13
	addq	(%rax), %r14
	movl	(%rcx), %ecx
	movl	20(%rbx), %edx
	movq	%r12, %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_dw_pcie_ep_inbound_atu
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_7
## %bb.4:
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_dw_pcie_dbi_ro_wr_en
	decq	%r13
	movq	%r13, %rdi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi2
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	%r15d, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCI_BASE_ADDRESS_MEM_TYPE_64@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_6
## %bb.5:
	addq	$4, %r14
	movq	%r13, %rdi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi2
	movq	%rbx, %rdi
	movq	%r14, %rsi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
LBB0_6:
	movq	%rbx, %rdi
	callq	_dw_pcie_dbi_ro_wr_dis
LBB0_7:
	movl	%r12d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_BASE_ADDRESS_0,8,3         ## @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_SPACE,4,2     ## @PCI_BASE_ADDRESS_SPACE
	.comm	_DW_PCIE_AS_MEM,4,2             ## @DW_PCIE_AS_MEM
	.comm	_DW_PCIE_AS_IO,4,2              ## @DW_PCIE_AS_IO
	.comm	_PCI_BASE_ADDRESS_MEM_TYPE_64,4,2 ## @PCI_BASE_ADDRESS_MEM_TYPE_64
	.no_dead_strip	_dw_pcie_ep_set_bar
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dw_pcie_ep_set_bar
_dw_pcie_ep_set_bar:                    ; @dw_pcie_ep_set_bar
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x2
	bl	_epc_get_drvdata
	mov	x23, x0
	bl	_to_dw_pcie_from_ep
	mov	x19, x0
	ldr	w22, [x20]
	ldr	x24, [x20, #8]
Lloh0:
	adrp	x8, _PCI_BASE_ADDRESS_0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_0@GOTPAGEOFF]
Lloh2:
	ldr	x25, [x8]
Lloh3:
	adrp	x8, _PCI_BASE_ADDRESS_SPACE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_SPACE@GOTPAGEOFF]
Lloh5:
	adrp	x9, _DW_PCIE_AS_MEM@GOTPAGE
Lloh6:
	ldr	x9, [x9, _DW_PCIE_AS_MEM@GOTPAGEOFF]
Lloh7:
	adrp	x10, _DW_PCIE_AS_IO@GOTPAGE
Lloh8:
	ldr	x10, [x10, _DW_PCIE_AS_IO@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	ldp	w21, w2, [x20, #16]
	tst	w8, w21
	csel	x8, x9, x10, eq
	ldr	w3, [x8]
	mov	x0, x23
	mov	x1, x22
	bl	_dw_pcie_ep_inbound_atu
	mov	x20, x0
	cbnz	w0, LBB0_4
; %bb.1:
	lsl	w8, w22, #2
	add	x22, x25, x8
	mov	x0, x19
	bl	_dw_pcie_dbi_ro_wr_en
	sub	x23, x24, #1
	mov	x0, x23
	bl	_lower_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	bl	_dw_pcie_writel_dbi2
	mov	x0, x19
	mov	x1, x22
	mov	x2, x21
	bl	_dw_pcie_writel_dbi
Lloh10:
	adrp	x8, _PCI_BASE_ADDRESS_MEM_TYPE_64@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_MEM_TYPE_64@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_3
; %bb.2:
	add	x21, x22, #4
	mov	x0, x23
	bl	_upper_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_dw_pcie_writel_dbi2
	mov	x0, x19
	mov	x1, x21
	mov	w2, #0
	bl	_dw_pcie_writel_dbi
LBB0_3:
	mov	x0, x19
	bl	_dw_pcie_dbi_ro_wr_dis
LBB0_4:
	mov	x0, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh9
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_BASE_ADDRESS_0,8,3         ; @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_SPACE,4,2     ; @PCI_BASE_ADDRESS_SPACE
	.comm	_DW_PCIE_AS_MEM,4,2             ; @DW_PCIE_AS_MEM
	.comm	_DW_PCIE_AS_IO,4,2              ; @DW_PCIE_AS_IO
	.comm	_PCI_BASE_ADDRESS_MEM_TYPE_64,4,2 ; @PCI_BASE_ADDRESS_MEM_TYPE_64
	.no_dead_strip	_dw_pcie_ep_set_bar
.subsections_via_symbols
