	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iwl_pcie_map_rx_causes
_iwl_pcie_map_rx_causes:                ## @iwl_pcie_map_rx_causes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_IWL_TRANS_GET_PCIE_TRANS
	movq	%rax, %rbx
	movq	_IWL_SHARED_IRQ_FIRST_RSS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	(%rbx), %eax
	xorl	%r14d, %r14d
	negl	%eax
	sbbl	%r14d, %r14d
	xorl	%edi, %edi
	callq	_MSIX_FH_INT_CAUSES_Q
	movl	%eax, %edi
	callq	_BIT
	movl	%eax, %r12d
	cmpl	$2, (%r15)
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	jl	LBB0_3
## %bb.1:
	movl	$1, %ebx
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	_CSR_MSIX_RX_IVAR
	movl	%eax, %r13d
	leal	(%r14,%rbx), %edi
	callq	_MSIX_FH_INT_CAUSES_Q
	movq	%r15, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_iwl_write8
	movl	%ebx, %edi
	callq	_MSIX_FH_INT_CAUSES_Q
	movl	%eax, %edi
	callq	_BIT
	orl	%eax, %r12d
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_2
LBB0_3:
	movq	_CSR_MSIX_FH_INT_MASK_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%r12d
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_iwl_write32
	xorl	%edi, %edi
	callq	_MSIX_FH_INT_CAUSES_Q
	movq	_IWL_SHARED_IRQ_NON_RX@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	andl	(%r14), %ebx
	je	LBB0_5
## %bb.4:
	movq	_MSIX_NON_AUTO_CLEAR_CAUSE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
LBB0_5:
	orl	%eax, %ebx
	xorl	%edi, %edi
	callq	_CSR_MSIX_RX_IVAR
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_iwl_write8
	movq	_IWL_SHARED_IRQ_FIRST_RSS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_6
## %bb.7:
	movl	$1, %edi
	callq	_CSR_MSIX_RX_IVAR
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_iwl_write8                     ## TAILCALL
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IWL_SHARED_IRQ_FIRST_RSS,4,2   ## @IWL_SHARED_IRQ_FIRST_RSS
	.comm	_CSR_MSIX_FH_INT_MASK_AD,4,2    ## @CSR_MSIX_FH_INT_MASK_AD
	.comm	_IWL_SHARED_IRQ_NON_RX,4,2      ## @IWL_SHARED_IRQ_NON_RX
	.comm	_MSIX_NON_AUTO_CLEAR_CAUSE,4,2  ## @MSIX_NON_AUTO_CLEAR_CAUSE
	.no_dead_strip	_iwl_pcie_map_rx_causes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iwl_pcie_map_rx_causes
_iwl_pcie_map_rx_causes:                ; @iwl_pcie_map_rx_causes
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_IWL_TRANS_GET_PCIE_TRANS
	mov	x20, x0
	ldr	w8, [x0]
Lloh0:
	adrp	x24, _IWL_SHARED_IRQ_FIRST_RSS@GOTPAGE
Lloh1:
	ldr	x24, [x24, _IWL_SHARED_IRQ_FIRST_RSS@GOTPAGEOFF]
	ldr	w9, [x24]
	tst	w9, w8
	csetm	w25, ne
	mov	w0, #0
	bl	_MSIX_FH_INT_CAUSES_Q
	bl	_BIT
	mov	x21, x0
	ldr	w8, [x19]
	cmp	w8, #2
	b.lt	LBB0_3
; %bb.1:
	mov	w22, #1
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x22
	bl	_CSR_MSIX_RX_IVAR
	mov	x23, x0
	add	w0, w25, w22
	bl	_MSIX_FH_INT_CAUSES_Q
	mov	x2, x0
	mov	x0, x19
	mov	x1, x23
	bl	_iwl_write8
	mov	x0, x22
	bl	_MSIX_FH_INT_CAUSES_Q
	bl	_BIT
	orr	w21, w0, w21
	add	w22, w22, #1
	ldr	w8, [x19]
	cmp	w22, w8
	b.lt	LBB0_2
LBB0_3:
Lloh2:
	adrp	x8, _CSR_MSIX_FH_INT_MASK_AD@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CSR_MSIX_FH_INT_MASK_AD@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mvn	w2, w21
	mov	x0, x19
	bl	_iwl_write32
	mov	w0, #0
	bl	_MSIX_FH_INT_CAUSES_Q
	ldr	w8, [x20]
Lloh5:
	adrp	x9, _IWL_SHARED_IRQ_NON_RX@GOTPAGE
Lloh6:
	ldr	x9, [x9, _IWL_SHARED_IRQ_NON_RX@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
Lloh8:
	adrp	x10, _MSIX_NON_AUTO_CLEAR_CAUSE@GOTPAGE
Lloh9:
	ldr	x10, [x10, _MSIX_NON_AUTO_CLEAR_CAUSE@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	tst	w9, w8
	csel	w8, wzr, w10, eq
	orr	w21, w8, w0
	mov	w0, #0
	bl	_CSR_MSIX_RX_IVAR
	mov	x1, x0
	mov	x0, x19
	mov	x2, x21
	bl	_iwl_write8
	ldr	w8, [x20]
	ldr	w9, [x24]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.4:
	mov	w0, #1
	bl	_CSR_MSIX_RX_IVAR
	mov	x1, x0
	mov	x0, x19
	mov	x2, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_iwl_write8
LBB0_5:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_IWL_SHARED_IRQ_FIRST_RSS,4,2   ; @IWL_SHARED_IRQ_FIRST_RSS
	.comm	_CSR_MSIX_FH_INT_MASK_AD,4,2    ; @CSR_MSIX_FH_INT_MASK_AD
	.comm	_IWL_SHARED_IRQ_NON_RX,4,2      ; @IWL_SHARED_IRQ_NON_RX
	.comm	_MSIX_NON_AUTO_CLEAR_CAUSE,4,2  ; @MSIX_NON_AUTO_CLEAR_CAUSE
	.no_dead_strip	_iwl_pcie_map_rx_causes
.subsections_via_symbols
