	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvebu_pci_bridge_emul_init
_mvebu_pci_bridge_emul_init:            ## @mvebu_pci_bridge_emul_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rdi, %rbx
	movq	_PCI_VENDOR_ID_MARVELL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%rdi)
	movq	_PCIE_DEV_ID_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_mvebu_readl
	sarl	$16, %eax
	movl	%eax, 24(%rbx)
	movq	_PCIE_DEV_REV_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_mvebu_readl
	movzbl	%al, %eax
	movl	%eax, 28(%rbx)
	movq	%rbx, %rdi
	callq	_mvebu_has_ioport
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_PCI_IO_RANGE_TYPE_32@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 40(%rbx)
	movq	%rax, 32(%rbx)
LBB0_2:
	movl	$1, (%rbx)
	movq	%rbx, 16(%rbx)
	movq	_mvebu_pci_bridge_emul_ops@GOTPCREL(%rip), %rax
	movq	%rax, 8(%rbx)
	movq	_PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_pci_bridge_emul_init           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_VENDOR_ID_MARVELL,4,2      ## @PCI_VENDOR_ID_MARVELL
	.comm	_PCIE_DEV_ID_OFF,4,2            ## @PCIE_DEV_ID_OFF
	.comm	_PCIE_DEV_REV_OFF,4,2           ## @PCIE_DEV_REV_OFF
	.comm	_PCI_IO_RANGE_TYPE_32,8,3       ## @PCI_IO_RANGE_TYPE_32
	.comm	_mvebu_pci_bridge_emul_ops,4,2  ## @mvebu_pci_bridge_emul_ops
	.comm	_PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR,4,2 ## @PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR
	.no_dead_strip	_mvebu_pci_bridge_emul_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvebu_pci_bridge_emul_init
_mvebu_pci_bridge_emul_init:            ; @mvebu_pci_bridge_emul_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _PCI_VENDOR_ID_MARVELL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_VENDOR_ID_MARVELL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x0, #48]
Lloh3:
	adrp	x8, _PCIE_DEV_ID_OFF@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_DEV_ID_OFF@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_mvebu_readl
	asr	w8, w0, #16
	str	w8, [x19, #24]
Lloh6:
	adrp	x8, _PCIE_DEV_REV_OFF@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCIE_DEV_REV_OFF@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mvebu_readl
	and	w8, w0, #0xff
	str	w8, [x19, #28]
	mov	x0, x19
	bl	_mvebu_has_ioport
	cbz	x0, LBB0_2
; %bb.1:
Lloh9:
	adrp	x8, _PCI_IO_RANGE_TYPE_32@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCI_IO_RANGE_TYPE_32@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	stp	x8, x8, [x19, #32]
LBB0_2:
	mov	w8, #1
	str	w8, [x19]
Lloh12:
	adrp	x8, _mvebu_pci_bridge_emul_ops@GOTPAGE
Lloh13:
	ldr	x8, [x8, _mvebu_pci_bridge_emul_ops@GOTPAGEOFF]
	stp	x8, x19, [x19, #8]
Lloh14:
	adrp	x8, _PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_pci_bridge_emul_init
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_VENDOR_ID_MARVELL,4,2      ; @PCI_VENDOR_ID_MARVELL
	.comm	_PCIE_DEV_ID_OFF,4,2            ; @PCIE_DEV_ID_OFF
	.comm	_PCIE_DEV_REV_OFF,4,2           ; @PCIE_DEV_REV_OFF
	.comm	_PCI_IO_RANGE_TYPE_32,8,3       ; @PCI_IO_RANGE_TYPE_32
	.comm	_mvebu_pci_bridge_emul_ops,4,2  ; @mvebu_pci_bridge_emul_ops
	.comm	_PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR,4,2 ; @PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR
	.no_dead_strip	_mvebu_pci_bridge_emul_init
.subsections_via_symbols
