	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rockchip_pcie_prog_ep_ob_atu
_rockchip_pcie_prog_ep_ob_atu:          ## @rockchip_pcie_prog_ep_ob_atu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%r9, %r14
	movq	%r8, %r13
	movl	%ecx, %r12d
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movl	%esi, -56(%rbp)                 ## 4-byte Spill
	movq	%rdi, %rbx
	movq	16(%rbp), %rdi
	decq	%rdi
	callq	_fls64
	movl	$1, %edi
	movl	%eax, %ecx
	shlq	%cl, %rdi
	callq	_ilog2
	cmpl	$9, %eax
	movl	$8, %r15d
	cmovgel	%eax, %r15d
	movq	_AXI_WRAPPER_NOR_MSG@GOTPCREL(%rip), %rax
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	movq	(%rbx), %rcx
	subq	(%rcx), %r13
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	decl	%r15d
	movl	%r12d, %ebx
	cmpl	%r12d, %eax
	movl	$16, %r12d
	cmovnel	%r15d, %r12d
	movq	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPCREL(%rip), %rax
	cmoveq	%r13, %r14
	andl	(%rax), %r12d
	movq	%r13, -72(%rbp)                 ## 8-byte Spill
	movq	%r13, %rdi
	callq	_lower_32_bits
	movl	%eax, %r13d
	movq	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	orl	%r12d, %r13d
	movq	%r14, %rdi
	callq	_upper_32_bits
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movl	-56(%rbp), %edi                 ## 4-byte Reload
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN
	movl	%eax, %r14d
	orl	%ebx, %r14d
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0
	cmpl	%ebx, -52(%rbp)                 ## 4-byte Folded Reload
	jne	LBB0_2
## %bb.1:
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_DESC0
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_DESC1
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	-48(%rbp), %r14d                ## 4-byte Reload
	jmp	LBB0_3
LBB0_2:
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1
	movq	%r12, %rdi
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_DESC0
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_DESC1
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movq	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	movq	-72(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	callq	_lower_32_bits
	movl	%eax, %r13d
	movq	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	orl	%r15d, %r13d
	movq	%r14, %rdi
	callq	_upper_32_bits
	movl	%eax, %r14d
LBB0_3:
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1
	movq	%r12, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rockchip_pcie_write            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AXI_WRAPPER_NOR_MSG,4,2        ## @AXI_WRAPPER_NOR_MSG
	.comm	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS,4,2 ## @PCIE_CORE_OB_REGION_ADDR0_NUM_BITS
	.comm	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR,4,2 ## @PCIE_CORE_OB_REGION_ADDR0_LO_ADDR
	.no_dead_strip	_rockchip_pcie_prog_ep_ob_atu
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rockchip_pcie_prog_ep_ob_atu
_rockchip_pcie_prog_ep_ob_atu:          ; @rockchip_pcie_prog_ep_ob_atu
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x26, x5
	mov	x22, x4
	mov	x24, x3
	mov	x20, x2
	str	w1, [sp, #8]                    ; 4-byte Folded Spill
	mov	x19, x0
	sub	x0, x6, #1
	bl	_fls64
	mov	w8, #1
	lsl	x0, x8, x0
	bl	_ilog2
Lloh0:
	adrp	x8, _AXI_WRAPPER_NOR_MSG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AXI_WRAPPER_NOR_MSG@GOTPAGEOFF]
Lloh2:
	ldr	w28, [x8]
	mov	w8, #8
	cmp	w0, #8
	csel	w8, w0, w8, gt
	ldr	x9, [x19]
	ldr	x9, [x9]
	sub	x22, x22, x9
	sub	w21, w8, #1
Lloh3:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPAGEOFF]
Lloh5:
	ldr	w27, [x8]
	mov	x0, x22
	bl	_lower_32_bits
	mov	x25, x0
Lloh6:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPAGEOFF]
Lloh8:
	ldr	w23, [x8]
	cmp	w28, w24
	csel	x0, x22, x26, eq
	bl	_upper_32_bits
	str	w0, [sp, #12]                   ; 4-byte Folded Spill
	ldr	w0, [sp, #8]                    ; 4-byte Folded Reload
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN
	mov	x26, x0
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0
	mov	x2, x0
	mov	w8, #16
	cmp	w28, w24
	csel	w8, w8, w21, eq
	and	w8, w27, w8
	and	w9, w23, w25
	orr	w23, w9, w8
	orr	w24, w26, w24
	mov	x0, x19
	b.ne	LBB0_2
; %bb.1:
	mov	w1, #0
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_DESC0
	mov	x2, x0
	mov	x0, x19
	mov	x1, x24
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_DESC1
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_rockchip_pcie_write
	ldr	w21, [sp, #12]                  ; 4-byte Folded Reload
	b	LBB0_3
LBB0_2:
	mov	x1, x23
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1
	mov	x2, x0
	mov	x0, x19
	ldr	w1, [sp, #12]                   ; 4-byte Folded Reload
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_DESC0
	mov	x2, x0
	mov	x0, x19
	mov	x1, x24
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_DESC1
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_rockchip_pcie_write
Lloh9:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	and	w21, w8, w21
	mov	x0, x22
	bl	_lower_32_bits
Lloh12:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	and	w8, w8, w0
	orr	w23, w8, w21
	mov	x0, x22
	bl	_upper_32_bits
	mov	x21, x0
LBB0_3:
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0
	mov	x2, x0
	mov	x0, x19
	mov	x1, x23
	bl	_rockchip_pcie_write
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	b	_rockchip_pcie_write
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_AXI_WRAPPER_NOR_MSG,4,2        ; @AXI_WRAPPER_NOR_MSG
	.comm	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS,4,2 ; @PCIE_CORE_OB_REGION_ADDR0_NUM_BITS
	.comm	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR,4,2 ; @PCIE_CORE_OB_REGION_ADDR0_LO_ADDR
	.no_dead_strip	_rockchip_pcie_prog_ep_ob_atu
.subsections_via_symbols
