	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath9k_hw_init_pll
_ath9k_hw_init_pll:                     ## @ath9k_hw_init_pll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	callq	_ath9k_hw_compute_pll_control
	movl	%eax, %r14d
	movq	%r13, %rdi
	callq	_AR_SREV_9485
	testq	%rax, %rax
	jne	LBB0_2
## %bb.1:
	movq	%r13, %rdi
	callq	_AR_SREV_9565
	testq	%rax, %rax
	je	LBB0_3
LBB0_2:
	movq	_AR_CH0_BB_DPLL2@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_AR_CH0_BB_DPLL2_PLL_PWD@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_REG_RMW_FIELD
	movl	(%r15), %esi
	movq	_AR_CH0_DPLL2_KD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$64, %ecx
	callq	_REG_RMW_FIELD
	movl	(%r15), %esi
	movq	_AR_CH0_DPLL2_KI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$4, %ecx
	callq	_REG_RMW_FIELD
	movq	_AR_CH0_BB_DPLL1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR_CH0_BB_DPLL1_REFDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$5, %ecx
	callq	_REG_RMW_FIELD
	movl	(%rbx), %esi
	movq	_AR_CH0_BB_DPLL1_NINI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$88, %ecx
	callq	_REG_RMW_FIELD
	movl	(%rbx), %esi
	movq	_AR_CH0_BB_DPLL1_NFRAC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%ecx, %ecx
	callq	_REG_RMW_FIELD
	movl	(%r15), %esi
	movq	_AR_CH0_BB_DPLL2_OUTDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_REG_RMW_FIELD
	movl	(%r15), %esi
	movq	_AR_CH0_BB_DPLL2_LOCAL_PLL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_REG_RMW_FIELD
	movl	(%r15), %esi
	movq	_AR_CH0_BB_DPLL2_EN_NEGTRIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_REG_RMW_FIELD
	movq	_AR_CH0_BB_DPLL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_CH0_BB_DPLL3_PHASE_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$6, %ecx
	callq	_REG_RMW_FIELD
	movl	(%r15), %esi
	movl	(%r12), %edx
	movq	%r13, %rdi
	xorl	%ecx, %ecx
	callq	_REG_RMW_FIELD
LBB0_29:
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_udelay
LBB0_30:
	movq	%r13, %rdi
	callq	_AR_SREV_9565
	movl	%r14d, %edx
	orl	$262144, %edx                   ## imm = 0x40000
	testq	%rax, %rax
	cmovel	%r14d, %edx
	movq	_AR_RTC_PLL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_REG_WRITE
	movq	%r13, %rdi
	callq	_AR_SREV_9485
	testq	%rax, %rax
	jne	LBB0_34
## %bb.31:
	movq	%r13, %rdi
	callq	_AR_SREV_9340
	testq	%rax, %rax
	jne	LBB0_34
## %bb.32:
	movq	%r13, %rdi
	callq	_AR_SREV_9330
	testq	%rax, %rax
	jne	LBB0_34
## %bb.33:
	movq	%r13, %rdi
	callq	_AR_SREV_9550
	testq	%rax, %rax
	je	LBB0_35
LBB0_34:
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_udelay
LBB0_35:
	movq	%r13, %rdi
	callq	_AR_SREV_9271
	testq	%rax, %rax
	je	LBB0_37
## %bb.36:
	movl	$500, %edi                      ## imm = 0x1F4
	callq	_udelay
	movq	%r13, %rdi
	movl	$327744, %esi                   ## imm = 0x50040
	movl	$772, %edx                      ## imm = 0x304
	callq	_REG_WRITE
LBB0_37:
	movq	_RTC_PLL_SETTLE_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_udelay
	movq	_AR_RTC_SLEEP_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_RTC_FORCE_DERIVED_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WRITE                      ## TAILCALL
LBB0_3:
	movq	%r13, %rdi
	callq	_AR_SREV_9330
	testq	%rax, %rax
	je	LBB0_5
## %bb.4:
	xorl	%r15d, %r15d
	cmpq	$0, (%r13)
	sete	%r15b
	movl	$8939110, %eax                  ## imm = 0x886666
	movl	$14699069, %r12d                ## imm = 0xE04A3D
	cmovel	%eax, %r12d
	movl	%r15d, %edx
	shll	$24, %edx
	orl	$417869569, %edx                ## imm = 0x18E82F01
	shll	$5, %r15d
	orl	$29, %r15d
	movq	_AR_CH0_DDR_DPLL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_REG_WRITE
	movq	_AR_CH0_DDR_DPLL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_CH0_DPLL3_PHASE_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_REG_RMW_FIELD
	movq	_AR_RTC_PLL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_RTC_9300_PLL_BYPASS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%r14d, %edx
	movq	%r13, %rdi
	callq	_REG_WRITE
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_udelay
	movq	_AR_RTC_PLL_CONTROL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	%r12d, %edx
	callq	_REG_WRITE
	movq	_AR_CH0_BB_DPLL2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR_CH0_DPLL2_KD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r15d, %ecx
	callq	_REG_RMW_FIELD
	movl	(%rbx), %esi
	movq	_AR_CH0_DPLL2_KI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$6, %ecx
	callq	_REG_RMW_FIELD
	movq	_AR_CH0_BB_DPLL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_CH0_BB_DPLL3_PHASE_SHIFT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_REG_RMW_FIELD
	jmp	LBB0_30
LBB0_5:
	movq	%r13, %rdi
	callq	_AR_SREV_9340
	testq	%rax, %rax
	jne	LBB0_9
## %bb.6:
	movq	%r13, %rdi
	callq	_AR_SREV_9550
	testq	%rax, %rax
	jne	LBB0_9
## %bb.7:
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	testq	%rax, %rax
	jne	LBB0_9
## %bb.8:
	movq	%r13, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	je	LBB0_30
LBB0_9:
	movq	_AR_RTC_PLL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_RTC_9300_SOC_PLL_BYPASS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%r14d, %edx
	movq	%r13, %rdi
	callq	_REG_WRITE
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_udelay
	movq	_AR_PHY_PLL_MODE@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r13, %rdi
	movl	$65536, %edx                    ## imm = 0x10000
	callq	_REG_SET_BIT
	movl	$100, %edi
	callq	_udelay
	cmpq	$0, (%r13)
	je	LBB0_13
## %bb.10:
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	movl	$134217728, %ebx                ## imm = 0x8000000
	movl	$41938, %r15d                   ## imm = 0xA3D2
	movl	$7340032, -44(%rbp)             ## 4-byte Folded Spill
                                        ## imm = 0x700000
	testq	%rax, %rax
	jne	LBB0_17
## %bb.11:
	movq	%r13, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	jne	LBB0_17
## %bb.12:
	movl	$402653184, %ebx                ## imm = 0x18000000
	movl	$125829, %r15d                  ## imm = 0x1EB85
	movl	$22020096, -44(%rbp)            ## 4-byte Folded Spill
                                        ## imm = 0x1500000
	jmp	LBB0_17
LBB0_13:
	movq	%r13, %rdi
	callq	_AR_SREV_9340
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movl	$671088640, %ebx                ## imm = 0x28000000
	xorl	%r15d, %r15d
	movl	$23068672, -44(%rbp)            ## 4-byte Folded Spill
                                        ## imm = 0x1600000
	jmp	LBB0_17
LBB0_15:
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	movl	$134217728, %ebx                ## imm = 0x8000000
	movl	$157285, %r15d                  ## imm = 0x26665
	movl	$4456448, -44(%rbp)             ## 4-byte Folded Spill
                                        ## imm = 0x440000
	testq	%rax, %rax
	jne	LBB0_17
## %bb.16:
	movq	%r13, %rdi
	callq	_AR_SREV_9561
	xorl	%r15d, %r15d
	cmpq	$1, %rax
	adcl	$157285, %r15d                  ## imm = 0x26665
LBB0_17:
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	movl	(%r12), %esi
	movq	%r13, %rdi
	callq	_REG_READ
	movq	%r12, %rbx
	movl	%eax, %r12d
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	movl	$4194304, %ecx                  ## imm = 0x400000
	testq	%rax, %rax
	jne	LBB0_19
## %bb.18:
	movq	%r13, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	movl	$65536, %eax                    ## imm = 0x10000
	movl	$4194304, %ecx                  ## imm = 0x400000
	cmovel	%eax, %ecx
LBB0_19:
	orl	%ecx, %r12d
	movl	(%rbx), %esi
	movq	%r13, %rdi
	movl	%r12d, %edx
	callq	_REG_WRITE
	movl	$100, %edi
	callq	_udelay
	movq	_AR_PHY_PLL_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	-44(%rbp), %r15d                ## 4-byte Folded Reload
	orl	-48(%rbp), %r15d                ## 4-byte Folded Reload
	movq	%r13, %rdi
	movl	%r15d, %edx
	callq	_REG_WRITE
	movl	$100, %edi
	callq	_udelay
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_REG_READ
	movl	%eax, %r15d
	movq	%r13, %rdi
	callq	_AR_SREV_9340
	testq	%rax, %rax
	je	LBB0_21
## %bb.20:
	andl	$-2147016705, %r15d             ## imm = 0x80071FFF
	orl	$1354768384, %r15d              ## imm = 0x50C02000
LBB0_25:
	movl	%r15d, %edx
	jmp	LBB0_26
LBB0_21:
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	testq	%rax, %rax
	jne	LBB0_23
## %bb.22:
	movq	%r13, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	je	LBB0_24
LBB0_23:
	andl	$29364223, %r15d                ## imm = 0x1C00FFF
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	testq	%rax, %rax
	movl	$-737673216, %eax               ## imm = 0xD4080000
	movl	$-737648640, %edx               ## imm = 0xD4086000
	cmovel	%eax, %edx
	orl	%r15d, %edx
LBB0_26:
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_REG_WRITE
	movq	%r13, %rdi
	callq	_AR_SREV_9531
	movl	$-4194305, %r15d                ## imm = 0xFFBFFFFF
	testq	%rax, %rax
	jne	LBB0_28
## %bb.27:
	movq	%r13, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	movl	$-65537, %eax                   ## imm = 0xFFFEFFFF
	movl	$-4194305, %r15d                ## imm = 0xFFBFFFFF
	cmovel	%eax, %r15d
LBB0_28:
	movl	(%rbx), %r12d
	movq	%r13, %rdi
	movl	%r12d, %esi
	callq	_REG_READ
	andl	%eax, %r15d
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%r15d, %edx
	callq	_REG_WRITE
	jmp	LBB0_29
LBB0_24:
	andl	$466943, %r15d                  ## imm = 0x71FFF
	orl	$-754966528, %r15d              ## imm = 0xD3002000
	jmp	LBB0_25
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_CH0_BB_DPLL2,4,2            ## @AR_CH0_BB_DPLL2
	.comm	_AR_CH0_BB_DPLL2_PLL_PWD,4,2    ## @AR_CH0_BB_DPLL2_PLL_PWD
	.comm	_AR_CH0_DPLL2_KD,4,2            ## @AR_CH0_DPLL2_KD
	.comm	_AR_CH0_DPLL2_KI,4,2            ## @AR_CH0_DPLL2_KI
	.comm	_AR_CH0_BB_DPLL1,4,2            ## @AR_CH0_BB_DPLL1
	.comm	_AR_CH0_BB_DPLL1_REFDIV,4,2     ## @AR_CH0_BB_DPLL1_REFDIV
	.comm	_AR_CH0_BB_DPLL1_NINI,4,2       ## @AR_CH0_BB_DPLL1_NINI
	.comm	_AR_CH0_BB_DPLL1_NFRAC,4,2      ## @AR_CH0_BB_DPLL1_NFRAC
	.comm	_AR_CH0_BB_DPLL2_OUTDIV,4,2     ## @AR_CH0_BB_DPLL2_OUTDIV
	.comm	_AR_CH0_BB_DPLL2_LOCAL_PLL,4,2  ## @AR_CH0_BB_DPLL2_LOCAL_PLL
	.comm	_AR_CH0_BB_DPLL2_EN_NEGTRIG,4,2 ## @AR_CH0_BB_DPLL2_EN_NEGTRIG
	.comm	_AR_CH0_BB_DPLL3,4,2            ## @AR_CH0_BB_DPLL3
	.comm	_AR_CH0_BB_DPLL3_PHASE_SHIFT,4,2 ## @AR_CH0_BB_DPLL3_PHASE_SHIFT
	.comm	_AR_CH0_DDR_DPLL2,4,2           ## @AR_CH0_DDR_DPLL2
	.comm	_AR_CH0_DDR_DPLL3,4,2           ## @AR_CH0_DDR_DPLL3
	.comm	_AR_CH0_DPLL3_PHASE_SHIFT,4,2   ## @AR_CH0_DPLL3_PHASE_SHIFT
	.comm	_AR_RTC_PLL_CONTROL,4,2         ## @AR_RTC_PLL_CONTROL
	.comm	_AR_RTC_9300_PLL_BYPASS,4,2     ## @AR_RTC_9300_PLL_BYPASS
	.comm	_AR_RTC_PLL_CONTROL2,4,2        ## @AR_RTC_PLL_CONTROL2
	.comm	_AR_RTC_9300_SOC_PLL_BYPASS,4,2 ## @AR_RTC_9300_SOC_PLL_BYPASS
	.comm	_AR_PHY_PLL_MODE,4,2            ## @AR_PHY_PLL_MODE
	.comm	_AR_PHY_PLL_CONTROL,4,2         ## @AR_PHY_PLL_CONTROL
	.comm	_RTC_PLL_SETTLE_DELAY,4,2       ## @RTC_PLL_SETTLE_DELAY
	.comm	_AR_RTC_SLEEP_CLK,4,2           ## @AR_RTC_SLEEP_CLK
	.comm	_AR_RTC_FORCE_DERIVED_CLK,4,2   ## @AR_RTC_FORCE_DERIVED_CLK
	.no_dead_strip	_ath9k_hw_init_pll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath9k_hw_init_pll
_ath9k_hw_init_pll:                     ; @ath9k_hw_init_pll
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	bl	_ath9k_hw_compute_pll_control
	mov	x20, x0
	mov	x0, x19
	bl	_AR_SREV_9485
Lloh0:
	adrp	x23, _AR_RTC_PLL_CONTROL@GOTPAGE
Lloh1:
	ldr	x23, [x23, _AR_RTC_PLL_CONTROL@GOTPAGEOFF]
	cbnz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_AR_SREV_9565
	cbz	x0, LBB0_12
LBB0_2:
Lloh2:
	adrp	x21, _AR_CH0_BB_DPLL2@GOTPAGE
Lloh3:
	ldr	x21, [x21, _AR_CH0_BB_DPLL2@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh4:
	adrp	x22, _AR_CH0_BB_DPLL2_PLL_PWD@GOTPAGE
Lloh5:
	ldr	x22, [x22, _AR_CH0_BB_DPLL2_PLL_PWD@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x19
	mov	w3, #1
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
Lloh6:
	adrp	x8, _AR_CH0_DPLL2_KD@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AR_CH0_DPLL2_KD@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #64
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
Lloh9:
	adrp	x8, _AR_CH0_DPLL2_KI@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AR_CH0_DPLL2_KI@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #4
	bl	_REG_RMW_FIELD
Lloh12:
	adrp	x24, _AR_CH0_BB_DPLL1@GOTPAGE
Lloh13:
	ldr	x24, [x24, _AR_CH0_BB_DPLL1@GOTPAGEOFF]
	ldr	w1, [x24]
Lloh14:
	adrp	x8, _AR_CH0_BB_DPLL1_REFDIV@GOTPAGE
Lloh15:
	ldr	x8, [x8, _AR_CH0_BB_DPLL1_REFDIV@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #5
	bl	_REG_RMW_FIELD
	ldr	w1, [x24]
Lloh17:
	adrp	x8, _AR_CH0_BB_DPLL1_NINI@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AR_CH0_BB_DPLL1_NINI@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #88
	bl	_REG_RMW_FIELD
	ldr	w1, [x24]
Lloh20:
	adrp	x8, _AR_CH0_BB_DPLL1_NFRAC@GOTPAGE
Lloh21:
	ldr	x8, [x8, _AR_CH0_BB_DPLL1_NFRAC@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #0
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
Lloh23:
	adrp	x8, _AR_CH0_BB_DPLL2_OUTDIV@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AR_CH0_BB_DPLL2_OUTDIV@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #1
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
Lloh26:
	adrp	x8, _AR_CH0_BB_DPLL2_LOCAL_PLL@GOTPAGE
Lloh27:
	ldr	x8, [x8, _AR_CH0_BB_DPLL2_LOCAL_PLL@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #1
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
Lloh29:
	adrp	x8, _AR_CH0_BB_DPLL2_EN_NEGTRIG@GOTPAGE
Lloh30:
	ldr	x8, [x8, _AR_CH0_BB_DPLL2_EN_NEGTRIG@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #1
	bl	_REG_RMW_FIELD
Lloh32:
	adrp	x8, _AR_CH0_BB_DPLL3@GOTPAGE
Lloh33:
	ldr	x8, [x8, _AR_CH0_BB_DPLL3@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
Lloh35:
	adrp	x8, _AR_CH0_BB_DPLL3_PHASE_SHIFT@GOTPAGE
Lloh36:
	ldr	x8, [x8, _AR_CH0_BB_DPLL3_PHASE_SHIFT@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #6
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
	ldr	w2, [x22]
	mov	x0, x19
	mov	w3, #0
	bl	_REG_RMW_FIELD
LBB0_3:
	mov	w0, #1000
	bl	_udelay
LBB0_4:
	mov	x0, x19
	bl	_AR_SREV_9565
	orr	w8, w20, #0x40000
	cmp	x0, #0
	csel	w2, w20, w8, eq
	ldr	w1, [x23]
	mov	x0, x19
	bl	_REG_WRITE
	mov	x0, x19
	bl	_AR_SREV_9485
	cbnz	x0, LBB0_8
; %bb.5:
	mov	x0, x19
	bl	_AR_SREV_9340
	cbnz	x0, LBB0_8
; %bb.6:
	mov	x0, x19
	bl	_AR_SREV_9330
	cbnz	x0, LBB0_8
; %bb.7:
	mov	x0, x19
	bl	_AR_SREV_9550
	cbz	x0, LBB0_9
LBB0_8:
	mov	w0, #1000
	bl	_udelay
LBB0_9:
	mov	x0, x19
	bl	_AR_SREV_9271
	cbz	x0, LBB0_11
; %bb.10:
	mov	w0, #500
	bl	_udelay
	mov	x0, x19
	mov	w1, #64
	movk	w1, #5, lsl #16
	mov	w2, #772
	bl	_REG_WRITE
LBB0_11:
Lloh38:
	adrp	x8, _RTC_PLL_SETTLE_DELAY@GOTPAGE
Lloh39:
	ldr	x8, [x8, _RTC_PLL_SETTLE_DELAY@GOTPAGEOFF]
Lloh40:
	ldr	w0, [x8]
	bl	_udelay
Lloh41:
	adrp	x8, _AR_RTC_SLEEP_CLK@GOTPAGE
Lloh42:
	ldr	x8, [x8, _AR_RTC_SLEEP_CLK@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
Lloh44:
	adrp	x8, _AR_RTC_FORCE_DERIVED_CLK@GOTPAGE
Lloh45:
	ldr	x8, [x8, _AR_RTC_FORCE_DERIVED_CLK@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_REG_WRITE
LBB0_12:
	mov	x0, x19
	bl	_AR_SREV_9330
	cbz	x0, LBB0_14
; %bb.13:
	ldr	x8, [x19]
	cmp	x8, #0
	mov	w8, #12033
	movk	w8, #6376, lsl #16
	mov	w9, #12033
	movk	w9, #6632, lsl #16
	csel	w2, w9, w8, eq
	mov	w8, #19005
	movk	w8, #224, lsl #16
	mov	w9, #26214
	movk	w9, #136, lsl #16
	csel	w21, w9, w8, eq
	mov	w8, #29
	mov	w9, #61
	csel	w22, w9, w8, eq
Lloh47:
	adrp	x8, _AR_CH0_DDR_DPLL2@GOTPAGE
Lloh48:
	ldr	x8, [x8, _AR_CH0_DDR_DPLL2@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_WRITE
Lloh50:
	adrp	x8, _AR_CH0_DDR_DPLL3@GOTPAGE
Lloh51:
	ldr	x8, [x8, _AR_CH0_DDR_DPLL3@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
Lloh53:
	adrp	x8, _AR_CH0_DPLL3_PHASE_SHIFT@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AR_CH0_DPLL3_PHASE_SHIFT@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #1
	bl	_REG_RMW_FIELD
	ldr	w1, [x23]
Lloh56:
	adrp	x8, _AR_RTC_9300_PLL_BYPASS@GOTPAGE
Lloh57:
	ldr	x8, [x8, _AR_RTC_9300_PLL_BYPASS@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	orr	w2, w8, w20
	mov	x0, x19
	bl	_REG_WRITE
	mov	w0, #1000
	bl	_udelay
Lloh59:
	adrp	x8, _AR_RTC_PLL_CONTROL2@GOTPAGE
Lloh60:
	ldr	x8, [x8, _AR_RTC_PLL_CONTROL2@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WRITE
Lloh62:
	adrp	x21, _AR_CH0_BB_DPLL2@GOTPAGE
Lloh63:
	ldr	x21, [x21, _AR_CH0_BB_DPLL2@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh64:
	adrp	x8, _AR_CH0_DPLL2_KD@GOTPAGE
Lloh65:
	ldr	x8, [x8, _AR_CH0_DPLL2_KD@GOTPAGEOFF]
Lloh66:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x22
	bl	_REG_RMW_FIELD
	ldr	w1, [x21]
Lloh67:
	adrp	x8, _AR_CH0_DPLL2_KI@GOTPAGE
Lloh68:
	ldr	x8, [x8, _AR_CH0_DPLL2_KI@GOTPAGEOFF]
Lloh69:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #6
	bl	_REG_RMW_FIELD
Lloh70:
	adrp	x8, _AR_CH0_BB_DPLL3@GOTPAGE
Lloh71:
	ldr	x8, [x8, _AR_CH0_BB_DPLL3@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
Lloh73:
	adrp	x8, _AR_CH0_BB_DPLL3_PHASE_SHIFT@GOTPAGE
Lloh74:
	ldr	x8, [x8, _AR_CH0_BB_DPLL3_PHASE_SHIFT@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #1
	bl	_REG_RMW_FIELD
	b	LBB0_4
LBB0_14:
	mov	x0, x19
	bl	_AR_SREV_9340
	cbnz	x0, LBB0_18
; %bb.15:
	mov	x0, x19
	bl	_AR_SREV_9550
	cbnz	x0, LBB0_18
; %bb.16:
	mov	x0, x19
	bl	_AR_SREV_9531
	cbnz	x0, LBB0_18
; %bb.17:
	mov	x0, x19
	bl	_AR_SREV_9561
	cbz	x0, LBB0_4
LBB0_18:
	ldr	w1, [x23]
Lloh76:
	adrp	x8, _AR_RTC_9300_SOC_PLL_BYPASS@GOTPAGE
Lloh77:
	ldr	x8, [x8, _AR_RTC_9300_SOC_PLL_BYPASS@GOTPAGEOFF]
Lloh78:
	ldr	w8, [x8]
	orr	w2, w8, w20
	mov	x0, x19
	bl	_REG_WRITE
	mov	w0, #1000
	bl	_udelay
Lloh79:
	adrp	x22, _AR_PHY_PLL_MODE@GOTPAGE
Lloh80:
	ldr	x22, [x22, _AR_PHY_PLL_MODE@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	mov	w2, #65536
	bl	_REG_SET_BIT
	mov	w0, #100
	bl	_udelay
	ldr	x8, [x19]
	cbz	x8, LBB0_21
; %bb.19:
	mov	x0, x19
	bl	_AR_SREV_9531
	cbz	x0, LBB0_23
; %bb.20:
	mov	w25, #134217728
	mov	w24, #41938
	mov	w26, #7340032
	b	LBB0_27
LBB0_21:
	mov	x0, x19
	bl	_AR_SREV_9340
	cbz	x0, LBB0_24
; %bb.22:
	mov	w24, #0
	mov	w25, #671088640
	mov	w26, #23068672
	b	LBB0_27
LBB0_23:
	mov	x0, x19
	bl	_AR_SREV_9561
	mov	w8, #134217728
	mov	w9, #41938
	mov	w10, #7340032
	mov	w11, #402653184
	mov	w12, #60293
	movk	w12, #1, lsl #16
	mov	w13, #22020096
	cmp	x0, #0
	csel	w26, w10, w13, ne
	csel	w24, w9, w12, ne
	csel	w25, w8, w11, ne
	b	LBB0_27
LBB0_24:
	mov	w24, #26213
	movk	w24, #2, lsl #16
	mov	x0, x19
	bl	_AR_SREV_9531
	cbnz	x0, LBB0_26
; %bb.25:
	mov	x0, x19
	bl	_AR_SREV_9561
	cmp	x0, #0
	cinc	w24, w24, eq
LBB0_26:
	mov	w25, #134217728
	mov	w26, #4456448
LBB0_27:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_REG_READ
	mov	x21, x0
	mov	x0, x19
	bl	_AR_SREV_9531
	mov	w27, #4194304
	cbnz	x0, LBB0_29
; %bb.28:
	mov	x0, x19
	bl	_AR_SREV_9561
	cmp	x0, #0
	mov	w8, #65536
	csel	w27, w8, w27, eq
LBB0_29:
	orr	w2, w21, w27
	ldr	w1, [x22]
	mov	x0, x19
	bl	_REG_WRITE
	mov	w0, #100
	bl	_udelay
Lloh81:
	adrp	x8, _AR_PHY_PLL_CONTROL@GOTPAGE
Lloh82:
	ldr	x8, [x8, _AR_PHY_PLL_CONTROL@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	orr	w8, w24, w26
	orr	w2, w8, w25
	mov	x0, x19
	bl	_REG_WRITE
	mov	w0, #100
	bl	_udelay
	ldr	w1, [x22]
	mov	x0, x19
	bl	_REG_READ
	mov	x21, x0
	mov	x0, x19
	bl	_AR_SREV_9340
	cbz	x0, LBB0_32
; %bb.30:
	mov	w8, #8191
	movk	w8, #32775, lsl #16
	and	w8, w21, w8
	mov	w9, #8192
	movk	w9, #20672, lsl #16
LBB0_31:
	orr	w2, w8, w9
	b	LBB0_35
LBB0_32:
	mov	x0, x19
	bl	_AR_SREV_9531
	cbnz	x0, LBB0_34
; %bb.33:
	mov	x0, x19
	bl	_AR_SREV_9561
	cbz	x0, LBB0_38
LBB0_34:
	and	w8, w21, #0x1ffffff
	and	w21, w8, #0xffc00fff
	mov	x0, x19
	bl	_AR_SREV_9531
	mov	w8, #-737673216
	orr	w9, w8, #0x6000
	cmp	x0, #0
	csel	w8, w8, w9, eq
	orr	w2, w8, w21
LBB0_35:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_REG_WRITE
	mov	x0, x19
	bl	_AR_SREV_9531
	mov	w24, #-4194305
	cbnz	x0, LBB0_37
; %bb.36:
	mov	x0, x19
	bl	_AR_SREV_9561
	cmp	x0, #0
	mov	w8, #-65537
	csel	w24, w8, w24, eq
LBB0_37:
	ldr	w21, [x22]
	mov	x0, x19
	mov	x1, x21
	bl	_REG_READ
	and	w2, w0, w24
	mov	x0, x19
	mov	x1, x21
	bl	_REG_WRITE
	b	LBB0_3
LBB0_38:
	and	w8, w21, #0x7ffff
	and	w8, w8, #0xffff1fff
	mov	w9, #8192
	movk	w9, #54016, lsl #16
	b	LBB0_31
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_CH0_BB_DPLL2,4,2            ; @AR_CH0_BB_DPLL2
	.comm	_AR_CH0_BB_DPLL2_PLL_PWD,4,2    ; @AR_CH0_BB_DPLL2_PLL_PWD
	.comm	_AR_CH0_DPLL2_KD,4,2            ; @AR_CH0_DPLL2_KD
	.comm	_AR_CH0_DPLL2_KI,4,2            ; @AR_CH0_DPLL2_KI
	.comm	_AR_CH0_BB_DPLL1,4,2            ; @AR_CH0_BB_DPLL1
	.comm	_AR_CH0_BB_DPLL1_REFDIV,4,2     ; @AR_CH0_BB_DPLL1_REFDIV
	.comm	_AR_CH0_BB_DPLL1_NINI,4,2       ; @AR_CH0_BB_DPLL1_NINI
	.comm	_AR_CH0_BB_DPLL1_NFRAC,4,2      ; @AR_CH0_BB_DPLL1_NFRAC
	.comm	_AR_CH0_BB_DPLL2_OUTDIV,4,2     ; @AR_CH0_BB_DPLL2_OUTDIV
	.comm	_AR_CH0_BB_DPLL2_LOCAL_PLL,4,2  ; @AR_CH0_BB_DPLL2_LOCAL_PLL
	.comm	_AR_CH0_BB_DPLL2_EN_NEGTRIG,4,2 ; @AR_CH0_BB_DPLL2_EN_NEGTRIG
	.comm	_AR_CH0_BB_DPLL3,4,2            ; @AR_CH0_BB_DPLL3
	.comm	_AR_CH0_BB_DPLL3_PHASE_SHIFT,4,2 ; @AR_CH0_BB_DPLL3_PHASE_SHIFT
	.comm	_AR_CH0_DDR_DPLL2,4,2           ; @AR_CH0_DDR_DPLL2
	.comm	_AR_CH0_DDR_DPLL3,4,2           ; @AR_CH0_DDR_DPLL3
	.comm	_AR_CH0_DPLL3_PHASE_SHIFT,4,2   ; @AR_CH0_DPLL3_PHASE_SHIFT
	.comm	_AR_RTC_PLL_CONTROL,4,2         ; @AR_RTC_PLL_CONTROL
	.comm	_AR_RTC_9300_PLL_BYPASS,4,2     ; @AR_RTC_9300_PLL_BYPASS
	.comm	_AR_RTC_PLL_CONTROL2,4,2        ; @AR_RTC_PLL_CONTROL2
	.comm	_AR_RTC_9300_SOC_PLL_BYPASS,4,2 ; @AR_RTC_9300_SOC_PLL_BYPASS
	.comm	_AR_PHY_PLL_MODE,4,2            ; @AR_PHY_PLL_MODE
	.comm	_AR_PHY_PLL_CONTROL,4,2         ; @AR_PHY_PLL_CONTROL
	.comm	_RTC_PLL_SETTLE_DELAY,4,2       ; @RTC_PLL_SETTLE_DELAY
	.comm	_AR_RTC_SLEEP_CLK,4,2           ; @AR_RTC_SLEEP_CLK
	.comm	_AR_RTC_FORCE_DERIVED_CLK,4,2   ; @AR_RTC_FORCE_DERIVED_CLK
	.no_dead_strip	_ath9k_hw_init_pll
.subsections_via_symbols
