	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_reset_ict             ## -- Begin function iwl_pcie_reset_ict
	.p2align	4, 0x90
_iwl_pcie_reset_ict:                    ## @iwl_pcie_reset_ict
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_IWL_TRANS_GET_PCIE_TRANS
	cmpl	$0, 24(%rax)
	je	LBB0_1
## %bb.2:
	movq	%rax, %r12
	movq	%rax, %r14
	addq	$12, %r14
	movq	%r14, %rdi
	callq	_spin_lock
	movq	%r15, %rdi
	callq	__iwl_disable_interrupts
	movl	24(%r12), %edi
	movq	_ICT_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%esi, %esi
	callq	_memset
	movl	(%r12), %ebx
	movq	_ICT_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %ebx
	movq	_CSR_DRAM_INT_TBL_ENABLE@GOTPCREL(%rip), %rax
	movq	_CSR_DRAM_INIT_TBL_WRAP_CHECK@GOTPCREL(%rip), %rcx
	movq	_CSR_DRAM_INIT_TBL_WRITE_POINTER@GOTPCREL(%rip), %rdx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_IWL_DEBUG_ISR
	movq	_CSR_DRAM_INT_TBL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_iwl_write32
	movl	$1, 4(%r12)
	movq	$0, 16(%r12)
	movq	_CSR_INT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	8(%r12), %edx
	movq	%r15, %rdi
	callq	_iwl_write32
	movq	%r15, %rdi
	callq	__iwl_enable_interrupts
	movq	%r14, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_spin_unlock                    ## TAILCALL
LBB0_1:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ICT_SIZE,4,2                   ## @ICT_SIZE
	.comm	_ICT_SHIFT,4,2                  ## @ICT_SHIFT
	.comm	_CSR_DRAM_INT_TBL_ENABLE,4,2    ## @CSR_DRAM_INT_TBL_ENABLE
	.comm	_CSR_DRAM_INIT_TBL_WRAP_CHECK,4,2 ## @CSR_DRAM_INIT_TBL_WRAP_CHECK
	.comm	_CSR_DRAM_INIT_TBL_WRITE_POINTER,4,2 ## @CSR_DRAM_INIT_TBL_WRITE_POINTER
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"CSR_DRAM_INT_TBL_REG =0x%x\n"

	.comm	_CSR_DRAM_INT_TBL_REG,4,2       ## @CSR_DRAM_INT_TBL_REG
	.comm	_CSR_INT,4,2                    ## @CSR_INT
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_reset_ict             ; -- Begin function iwl_pcie_reset_ict
	.p2align	2
_iwl_pcie_reset_ict:                    ; @iwl_pcie_reset_ict
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_IWL_TRANS_GET_PCIE_TRANS
	ldr	w8, [x0, #24]
	cbz	w8, LBB0_2
; %bb.1:
	mov	x21, x0
	add	x20, x0, #12
	mov	x0, x20
	bl	_spin_lock
	mov	x0, x19
	bl	__iwl_disable_interrupts
	ldr	w0, [x21, #24]
Lloh0:
	adrp	x8, _ICT_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ICT_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	w1, #0
	bl	_memset
	ldr	w8, [x21]
Lloh3:
	adrp	x9, _ICT_SHIFT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _ICT_SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	asr	w8, w8, w9
Lloh6:
	adrp	x9, _CSR_DRAM_INT_TBL_ENABLE@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CSR_DRAM_INT_TBL_ENABLE@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	adrp	x10, _CSR_DRAM_INIT_TBL_WRAP_CHECK@GOTPAGE
Lloh10:
	ldr	x10, [x10, _CSR_DRAM_INIT_TBL_WRAP_CHECK@GOTPAGEOFF]
Lloh11:
	ldr	w10, [x10]
Lloh12:
	adrp	x11, _CSR_DRAM_INIT_TBL_WRITE_POINTER@GOTPAGE
Lloh13:
	ldr	x11, [x11, _CSR_DRAM_INIT_TBL_WRITE_POINTER@GOTPAGEOFF]
Lloh14:
	ldr	w11, [x11]
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w22, w8, w11
Lloh15:
	adrp	x1, l_.str@PAGE
Lloh16:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_IWL_DEBUG_ISR
Lloh17:
	adrp	x8, _CSR_DRAM_INT_TBL_REG@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CSR_DRAM_INT_TBL_REG@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_iwl_write32
	mov	w8, #1
	str	w8, [x21, #4]
	str	xzr, [x21, #16]
Lloh20:
	adrp	x8, _CSR_INT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _CSR_INT@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	ldr	w2, [x21, #8]
	mov	x0, x19
	bl	_iwl_write32
	mov	x0, x19
	bl	__iwl_enable_interrupts
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_spin_unlock
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_ICT_SIZE,4,2                   ; @ICT_SIZE
	.comm	_ICT_SHIFT,4,2                  ; @ICT_SHIFT
	.comm	_CSR_DRAM_INT_TBL_ENABLE,4,2    ; @CSR_DRAM_INT_TBL_ENABLE
	.comm	_CSR_DRAM_INIT_TBL_WRAP_CHECK,4,2 ; @CSR_DRAM_INIT_TBL_WRAP_CHECK
	.comm	_CSR_DRAM_INIT_TBL_WRITE_POINTER,4,2 ; @CSR_DRAM_INIT_TBL_WRITE_POINTER
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"CSR_DRAM_INT_TBL_REG =0x%x\n"

	.comm	_CSR_DRAM_INT_TBL_REG,4,2       ; @CSR_DRAM_INT_TBL_REG
	.comm	_CSR_INT,4,2                    ; @CSR_INT
.subsections_via_symbols
