	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function program_hpx_type0
_program_hpx_type0:                     ## @program_hpx_type0
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r14
	testq	%rsi, %rsi
	jne	LBB0_2
## %bb.1:
	movq	_pci_default_type0@GOTPCREL(%rip), %rbx
LBB0_2:
	movl	(%rbx), %edx
	cmpl	$2, %edx
	jl	LBB0_4
## %bb.3:
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	callq	_pci_warn
	movq	_pci_default_type0@GOTPCREL(%rip), %rbx
LBB0_4:
	movq	_PCI_CACHE_LINE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	32(%rbx), %edx
	movq	%r14, %rdi
	callq	_pci_write_config_byte
	movq	_PCI_LATENCY_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	16(%rbx), %edx
	movq	%r14, %rdi
	callq	_pci_write_config_byte
	movq	_PCI_COMMAND@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-28(%rbp), %rdx
	movq	%r14, %rdi
	callq	_pci_read_config_word
	cmpq	$0, 24(%rbx)
	je	LBB0_6
## %bb.5:
	movq	_PCI_COMMAND_SERR@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, -28(%rbp)
LBB0_6:
	cmpq	$0, 8(%rbx)
	je	LBB0_7
## %bb.8:
	movq	_PCI_COMMAND_PARITY@GOTPCREL(%rip), %rax
	movl	-28(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -28(%rbp)
	jmp	LBB0_9
LBB0_7:
	movl	-28(%rbp), %edx
LBB0_9:
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_pci_write_config_word
	movl	(%r14), %eax
	sarl	$8, %eax
	movq	_PCI_CLASS_BRIDGE_PCI@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_14
## %bb.10:
	movq	_PCI_SEC_LATENCY_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	16(%rbx), %edx
	movq	%r14, %rdi
	callq	_pci_write_config_byte
	movq	_PCI_BRIDGE_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-32(%rbp), %rdx
	movq	%r14, %rdi
	callq	_pci_read_config_word
	cmpq	$0, 8(%rbx)
	je	LBB0_11
## %bb.12:
	movq	_PCI_BRIDGE_CTL_PARITY@GOTPCREL(%rip), %rax
	movl	-32(%rbp), %edx
	orl	(%rax), %edx
	movl	%edx, -32(%rbp)
	jmp	LBB0_13
LBB0_11:
	movl	-32(%rbp), %edx
LBB0_13:
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_pci_write_config_word
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_pci_default_type0,40,3         ## @pci_default_type0
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCI settings rev %d not supported; using defaults\n"

	.comm	_PCI_CACHE_LINE_SIZE,4,2        ## @PCI_CACHE_LINE_SIZE
	.comm	_PCI_LATENCY_TIMER,4,2          ## @PCI_LATENCY_TIMER
	.comm	_PCI_COMMAND,4,2                ## @PCI_COMMAND
	.comm	_PCI_COMMAND_SERR,4,2           ## @PCI_COMMAND_SERR
	.comm	_PCI_COMMAND_PARITY,4,2         ## @PCI_COMMAND_PARITY
	.comm	_PCI_CLASS_BRIDGE_PCI,4,2       ## @PCI_CLASS_BRIDGE_PCI
	.comm	_PCI_SEC_LATENCY_TIMER,4,2      ## @PCI_SEC_LATENCY_TIMER
	.comm	_PCI_BRIDGE_CONTROL,4,2         ## @PCI_BRIDGE_CONTROL
	.comm	_PCI_BRIDGE_CTL_PARITY,4,2      ## @PCI_BRIDGE_CTL_PARITY
	.no_dead_strip	_program_hpx_type0
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function program_hpx_type0
_program_hpx_type0:                     ; @program_hpx_type0
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _pci_default_type0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _pci_default_type0@GOTPAGEOFF]
	cmp	x1, #0
	csel	x20, x8, x1, eq
	ldr	w2, [x20]
	cmp	w2, #2
	b.lt	LBB0_2
; %bb.1:
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_pci_warn
Lloh4:
	adrp	x20, _pci_default_type0@GOTPAGE
Lloh5:
	ldr	x20, [x20, _pci_default_type0@GOTPAGEOFF]
LBB0_2:
Lloh6:
	adrp	x8, _PCI_CACHE_LINE_SIZE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCI_CACHE_LINE_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	ldr	w2, [x20, #32]
	mov	x0, x19
	bl	_pci_write_config_byte
Lloh9:
	adrp	x8, _PCI_LATENCY_TIMER@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCI_LATENCY_TIMER@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	ldr	w2, [x20, #16]
	mov	x0, x19
	bl	_pci_write_config_byte
Lloh12:
	adrp	x21, _PCI_COMMAND@GOTPAGE
Lloh13:
	ldr	x21, [x21, _PCI_COMMAND@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_pci_read_config_word
	ldr	x8, [x20, #24]
	cbz	x8, LBB0_4
; %bb.3:
Lloh14:
	adrp	x8, _PCI_COMMAND_SERR@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PCI_COMMAND_SERR@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w8, w9, w8
	str	w8, [sp, #12]
LBB0_4:
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_6
; %bb.5:
Lloh17:
	adrp	x8, _PCI_COMMAND_PARITY@GOTPAGE
Lloh18:
	ldr	x8, [x8, _PCI_COMMAND_PARITY@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	orr	w2, w9, w8
	str	w2, [sp, #12]
	b	LBB0_7
LBB0_6:
	ldr	w2, [sp, #12]
LBB0_7:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_pci_write_config_word
	ldr	w8, [x19]
Lloh20:
	adrp	x9, _PCI_CLASS_BRIDGE_PCI@GOTPAGE
Lloh21:
	ldr	x9, [x9, _PCI_CLASS_BRIDGE_PCI@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	cmp	w9, w8, asr #8
	b.ne	LBB0_12
; %bb.8:
Lloh23:
	adrp	x8, _PCI_SEC_LATENCY_TIMER@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PCI_SEC_LATENCY_TIMER@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	ldr	w2, [x20, #16]
	mov	x0, x19
	bl	_pci_write_config_byte
Lloh26:
	adrp	x21, _PCI_BRIDGE_CONTROL@GOTPAGE
Lloh27:
	ldr	x21, [x21, _PCI_BRIDGE_CONTROL@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #8
	mov	x0, x19
	bl	_pci_read_config_word
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_10
; %bb.9:
Lloh28:
	adrp	x8, _PCI_BRIDGE_CTL_PARITY@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PCI_BRIDGE_CTL_PARITY@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	ldr	w9, [sp, #8]
	orr	w2, w9, w8
	str	w2, [sp, #8]
	b	LBB0_11
LBB0_10:
	ldr	w2, [sp, #8]
LBB0_11:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_pci_write_config_word
LBB0_12:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_pci_default_type0,40,3         ; @pci_default_type0
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCI settings rev %d not supported; using defaults\n"

	.comm	_PCI_CACHE_LINE_SIZE,4,2        ; @PCI_CACHE_LINE_SIZE
	.comm	_PCI_LATENCY_TIMER,4,2          ; @PCI_LATENCY_TIMER
	.comm	_PCI_COMMAND,4,2                ; @PCI_COMMAND
	.comm	_PCI_COMMAND_SERR,4,2           ; @PCI_COMMAND_SERR
	.comm	_PCI_COMMAND_PARITY,4,2         ; @PCI_COMMAND_PARITY
	.comm	_PCI_CLASS_BRIDGE_PCI,4,2       ; @PCI_CLASS_BRIDGE_PCI
	.comm	_PCI_SEC_LATENCY_TIMER,4,2      ; @PCI_SEC_LATENCY_TIMER
	.comm	_PCI_BRIDGE_CONTROL,4,2         ; @PCI_BRIDGE_CONTROL
	.comm	_PCI_BRIDGE_CTL_PARITY,4,2      ; @PCI_BRIDGE_CTL_PARITY
	.no_dead_strip	_program_hpx_type0
.subsections_via_symbols
