	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mvpp2_prs_mac_promisc_set      ## -- Begin function mvpp2_prs_mac_promisc_set
	.p2align	4, 0x90
_mvpp2_prs_mac_promisc_set:             ## @mvpp2_prs_mac_promisc_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r12d
	movl	%esi, %r15d
	movq	%rdi, %r14
	movq	_MVPP2_PRS_L2_UNI_CAST@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	cmpl	%edx, %eax
	jne	LBB0_1
## %bb.2:
	movq	_MVPP2_PE_MAC_UC_PROMISCUOUS@GOTPCREL(%rip), %rcx
	jmp	LBB0_3
LBB0_1:
	movq	_MVPP2_PE_MAC_MC_PROMISCUOUS@GOTPCREL(%rip), %rcx
LBB0_3:
	movslq	(%rcx), %r13
	movq	(%r14), %rcx
	cmpq	$0, (%rcx,%r13,8)
	je	LBB0_5
## %bb.4:
	leaq	-48(%rbp), %rsi
	movq	%r14, %rdi
	movl	%r13d, %edx
	callq	_mvpp2_prs_init_from_hw
	jmp	LBB0_6
LBB0_5:
	cmpl	%edx, %eax
	movq	_MVPP2_PRS_RI_L2_MCAST@GOTPCREL(%rip), %rax
	cmoveq	_MVPP2_PRS_RI_L2_UCAST@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_MVPP2_PRS_MCAST_VAL@GOTPCREL(%rip), %rax
	cmoveq	_MVPP2_PRS_UCAST_VAL@GOTPCREL(%rip), %rax
	movzbl	(%rax), %eax
	movl	%eax, -56(%rbp)                 ## 4-byte Spill
	movl	%r12d, %ebx
	leaq	-48(%rbp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_MAC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%r13d, -48(%rbp)
	movq	_MVPP2_PRS_LU_DSA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L2_CAST_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	-52(%rbp), %esi                 ## 4-byte Reload
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_CAST_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	-56(%rbp), %edx                 ## 4-byte Reload
	callq	_mvpp2_prs_tcam_data_byte_set
	movq	_ETH_ALEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%esi, %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	%r12, %rdi
	movl	%ebx, %r12d
	xorl	%esi, %esi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movq	_MVPP2_PRS_LU_MAC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
LBB0_6:
	leaq	-48(%rbp), %rbx
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%r12d, %edx
	callq	_mvpp2_prs_tcam_port_set
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_mvpp2_prs_hw_write
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PRS_L2_UNI_CAST,4,2      ## @MVPP2_PRS_L2_UNI_CAST
	.comm	_MVPP2_PRS_UCAST_VAL,1,0        ## @MVPP2_PRS_UCAST_VAL
	.comm	_MVPP2_PE_MAC_UC_PROMISCUOUS,4,2 ## @MVPP2_PE_MAC_UC_PROMISCUOUS
	.comm	_MVPP2_PRS_RI_L2_UCAST,4,2      ## @MVPP2_PRS_RI_L2_UCAST
	.comm	_MVPP2_PRS_MCAST_VAL,1,0        ## @MVPP2_PRS_MCAST_VAL
	.comm	_MVPP2_PE_MAC_MC_PROMISCUOUS,4,2 ## @MVPP2_PE_MAC_MC_PROMISCUOUS
	.comm	_MVPP2_PRS_RI_L2_MCAST,4,2      ## @MVPP2_PRS_RI_L2_MCAST
	.comm	_MVPP2_PRS_LU_MAC,4,2           ## @MVPP2_PRS_LU_MAC
	.comm	_MVPP2_PRS_LU_DSA,4,2           ## @MVPP2_PRS_LU_DSA
	.comm	_MVPP2_PRS_RI_L2_CAST_MASK,4,2  ## @MVPP2_PRS_RI_L2_CAST_MASK
	.comm	_MVPP2_PRS_CAST_MASK,4,2        ## @MVPP2_PRS_CAST_MASK
	.comm	_ETH_ALEN,4,2                   ## @ETH_ALEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mvpp2_prs_mac_promisc_set      ; -- Begin function mvpp2_prs_mac_promisc_set
	.p2align	2
_mvpp2_prs_mac_promisc_set:             ; @mvpp2_prs_mac_promisc_set
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x3
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _MVPP2_PRS_L2_UNI_CAST@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MVPP2_PRS_L2_UNI_CAST@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _MVPP2_PE_MAC_UC_PROMISCUOUS@GOTPAGE
Lloh4:
	ldr	x9, [x9, _MVPP2_PE_MAC_UC_PROMISCUOUS@GOTPAGEOFF]
Lloh5:
	adrp	x10, _MVPP2_PE_MAC_MC_PROMISCUOUS@GOTPAGE
Lloh6:
	ldr	x10, [x10, _MVPP2_PE_MAC_MC_PROMISCUOUS@GOTPAGEOFF]
	cmp	w8, w2
	csel	x9, x9, x10, eq
	ldrsw	x22, [x9]
	ldr	x9, [x0]
	ldr	x9, [x9, x22, lsl #3]
	cbz	x9, LBB0_2
; %bb.1:
	add	x1, sp, #8
	mov	x0, x19
	mov	x2, x22
	bl	_mvpp2_prs_init_from_hw
	b	LBB0_3
LBB0_2:
Lloh7:
	adrp	x9, _MVPP2_PRS_RI_L2_UCAST@GOTPAGE
Lloh8:
	ldr	x9, [x9, _MVPP2_PRS_RI_L2_UCAST@GOTPAGEOFF]
Lloh9:
	adrp	x10, _MVPP2_PRS_RI_L2_MCAST@GOTPAGE
Lloh10:
	ldr	x10, [x10, _MVPP2_PRS_RI_L2_MCAST@GOTPAGEOFF]
	cmp	w8, w2
	csel	x8, x9, x10, eq
	ldr	w23, [x8]
Lloh11:
	adrp	x8, _MVPP2_PRS_UCAST_VAL@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MVPP2_PRS_UCAST_VAL@GOTPAGEOFF]
Lloh13:
	adrp	x9, _MVPP2_PRS_MCAST_VAL@GOTPAGE
Lloh14:
	ldr	x9, [x9, _MVPP2_PRS_MCAST_VAL@GOTPAGEOFF]
	csel	x8, x8, x9, eq
	ldrb	w24, [x8]
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh15:
	adrp	x25, _MVPP2_PRS_LU_MAC@GOTPAGE
Lloh16:
	ldr	x25, [x25, _MVPP2_PRS_LU_MAC@GOTPAGEOFF]
	ldr	w1, [x25]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
	str	w22, [sp, #8]
Lloh17:
	adrp	x8, _MVPP2_PRS_LU_DSA@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MVPP2_PRS_LU_DSA@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh20:
	adrp	x8, _MVPP2_PRS_RI_L2_CAST_MASK@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MVPP2_PRS_RI_L2_CAST_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	add	x0, sp, #8
	mov	x1, x23
	bl	_mvpp2_prs_sram_ri_update
Lloh23:
	adrp	x8, _MVPP2_PRS_CAST_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MVPP2_PRS_CAST_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w3, [x8]
	add	x0, sp, #8
	mov	w1, #0
	mov	x2, x24
	bl	_mvpp2_prs_tcam_data_byte_set
Lloh26:
	adrp	x8, _ETH_ALEN@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ETH_ALEN@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	lsl	w1, w8, #1
Lloh29:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
Lloh31:
	ldr	w2, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_shift_set
	add	x0, sp, #8
	mov	w1, #0
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
LBB0_3:
	add	x0, sp, #8
	mov	x1, x21
	mov	x2, x20
	bl	_mvpp2_prs_tcam_port_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PRS_L2_UNI_CAST,4,2      ; @MVPP2_PRS_L2_UNI_CAST
	.comm	_MVPP2_PRS_UCAST_VAL,1,0        ; @MVPP2_PRS_UCAST_VAL
	.comm	_MVPP2_PE_MAC_UC_PROMISCUOUS,4,2 ; @MVPP2_PE_MAC_UC_PROMISCUOUS
	.comm	_MVPP2_PRS_RI_L2_UCAST,4,2      ; @MVPP2_PRS_RI_L2_UCAST
	.comm	_MVPP2_PRS_MCAST_VAL,1,0        ; @MVPP2_PRS_MCAST_VAL
	.comm	_MVPP2_PE_MAC_MC_PROMISCUOUS,4,2 ; @MVPP2_PE_MAC_MC_PROMISCUOUS
	.comm	_MVPP2_PRS_RI_L2_MCAST,4,2      ; @MVPP2_PRS_RI_L2_MCAST
	.comm	_MVPP2_PRS_LU_MAC,4,2           ; @MVPP2_PRS_LU_MAC
	.comm	_MVPP2_PRS_LU_DSA,4,2           ; @MVPP2_PRS_LU_DSA
	.comm	_MVPP2_PRS_RI_L2_CAST_MASK,4,2  ; @MVPP2_PRS_RI_L2_CAST_MASK
	.comm	_MVPP2_PRS_CAST_MASK,4,2        ; @MVPP2_PRS_CAST_MASK
	.comm	_ETH_ALEN,4,2                   ; @ETH_ALEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
.subsections_via_symbols
