	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_dw_parse_dt
_tegra_pcie_dw_parse_dt:                ## @tegra_pcie_dw_parse_dt
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	16(%rdi), %rax
	movq	(%rax), %r14
	leaq	52(%rdi), %rdx
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_u32
	testl	%eax, %eax
	js	LBB0_1
## %bb.2:
	leaq	48(%r15), %rdx
	leaq	L_.str.2(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_u32
	testl	%eax, %eax
	jns	LBB0_4
## %bb.3:
	movq	16(%r15), %rdi
	leaq	L_.str.3(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_info
LBB0_4:
	leaq	44(%r15), %rdx
	leaq	L_.str.4(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_u32
	testl	%eax, %eax
	jns	LBB0_6
## %bb.5:
	movq	16(%r15), %rdi
	leaq	L_.str.5(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_info
LBB0_6:
	leaq	40(%r15), %rdx
	leaq	L_.str.6(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_u32
	testl	%eax, %eax
	js	LBB0_7
## %bb.8:
	movq	%r14, %rdi
	callq	_of_pci_get_max_link_speed
	movl	%eax, 36(%r15)
	leaq	32(%r15), %rcx
	leaq	L_.str.8(%rip), %rsi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_of_property_read_u32_index
	testl	%eax, %eax
	je	LBB0_10
## %bb.9:
	movl	%eax, %ebx
	movq	16(%r15), %rdi
	leaq	L_.str.9(%rip), %rsi
	jmp	LBB0_12
LBB0_1:
	movl	%eax, %ebx
	movq	16(%r15), %rdi
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_info
	jmp	LBB0_16
LBB0_7:
	movl	%eax, %ebx
	movq	16(%r15), %rdi
	leaq	L_.str.7(%rip), %rsi
	jmp	LBB0_12
LBB0_10:
	leaq	L_.str.10(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_count_strings
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_11
## %bb.13:
	movl	%ebx, (%r15)
	leaq	L_.str.12(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_bool
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movl	$1, 4(%r15)
LBB0_15:
	movq	16(%r15), %rax
	movq	(%rax), %rdi
	leaq	L_.str.13(%rip), %rsi
	callq	_of_property_read_bool
	movq	%rax, 24(%r15)
	leaq	L_.str.14(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_bool
	movq	%rax, 8(%r15)
	xorl	%ebx, %ebx
	jmp	LBB0_16
LBB0_11:
	movq	16(%r15), %rdi
	leaq	L_.str.11(%rip), %rsi
LBB0_12:
	movl	%ebx, %edx
	callq	_dev_err
LBB0_16:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"nvidia,aspm-cmrt-us"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to read ASPM T_cmrt: %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"nvidia,aspm-pwr-on-t-us"

L_.str.3:                               ## @.str.3
	.asciz	"Failed to read ASPM Power On time: %d\n"

L_.str.4:                               ## @.str.4
	.asciz	"nvidia,aspm-l0s-entrance-latency-us"

L_.str.5:                               ## @.str.5
	.asciz	"Failed to read ASPM L0s Entrance latency: %d\n"

L_.str.6:                               ## @.str.6
	.asciz	"num-lanes"

L_.str.7:                               ## @.str.7
	.asciz	"Failed to read num-lanes: %d\n"

L_.str.8:                               ## @.str.8
	.asciz	"nvidia,bpmp"

L_.str.9:                               ## @.str.9
	.asciz	"Failed to read Controller-ID: %d\n"

L_.str.10:                              ## @.str.10
	.asciz	"phy-names"

L_.str.11:                              ## @.str.11
	.asciz	"Failed to find PHY entries: %d\n"

L_.str.12:                              ## @.str.12
	.asciz	"nvidia,update-fc-fixup"

L_.str.13:                              ## @.str.13
	.asciz	"supports-clkreq"

L_.str.14:                              ## @.str.14
	.asciz	"snps,enable-cdm-check"

	.no_dead_strip	_tegra_pcie_dw_parse_dt
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_dw_parse_dt
_tegra_pcie_dw_parse_dt:                ; @tegra_pcie_dw_parse_dt
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #16]
	ldr	x20, [x8]
	add	x2, x0, #52
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_u32
	tbnz	w0, #31, LBB0_8
; %bb.1:
	add	x2, x19, #48
Lloh2:
	adrp	x1, l_.str.2@PAGE
Lloh3:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_u32
	tbz	w0, #31, LBB0_3
; %bb.2:
	mov	x2, x0
	ldr	x0, [x19, #16]
Lloh4:
	adrp	x1, l_.str.3@PAGE
Lloh5:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_info
LBB0_3:
	add	x2, x19, #44
Lloh6:
	adrp	x1, l_.str.4@PAGE
Lloh7:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_u32
	tbz	w0, #31, LBB0_5
; %bb.4:
	mov	x2, x0
	ldr	x0, [x19, #16]
Lloh8:
	adrp	x1, l_.str.5@PAGE
Lloh9:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_info
LBB0_5:
	add	x2, x19, #40
Lloh10:
	adrp	x1, l_.str.6@PAGE
Lloh11:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_u32
	tbnz	w0, #31, LBB0_9
; %bb.6:
	mov	x0, x20
	bl	_of_pci_get_max_link_speed
	str	w0, [x19, #36]
	add	x3, x19, #32
Lloh12:
	adrp	x1, l_.str.8@PAGE
Lloh13:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x20
	mov	w2, #1
	bl	_of_property_read_u32_index
	cbz	w0, LBB0_10
; %bb.7:
	mov	x21, x0
	ldr	x0, [x19, #16]
Lloh14:
	adrp	x1, l_.str.9@PAGE
Lloh15:
	add	x1, x1, l_.str.9@PAGEOFF
	b	LBB0_15
LBB0_8:
	mov	x21, x0
	ldr	x0, [x19, #16]
Lloh16:
	adrp	x1, l_.str.1@PAGE
Lloh17:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x2, x21
	bl	_dev_info
	b	LBB0_16
LBB0_9:
	mov	x21, x0
	ldr	x0, [x19, #16]
Lloh18:
	adrp	x1, l_.str.7@PAGE
Lloh19:
	add	x1, x1, l_.str.7@PAGEOFF
	b	LBB0_15
LBB0_10:
Lloh20:
	adrp	x1, l_.str.10@PAGE
Lloh21:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x20
	bl	_of_property_count_strings
	mov	x21, x0
	tbnz	w0, #31, LBB0_14
; %bb.11:
	str	w21, [x19]
Lloh22:
	adrp	x1, l_.str.12@PAGE
Lloh23:
	add	x1, x1, l_.str.12@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_bool
	cbz	x0, LBB0_13
; %bb.12:
	mov	w8, #1
	str	w8, [x19, #4]
LBB0_13:
	ldr	x8, [x19, #16]
	ldr	x0, [x8]
Lloh24:
	adrp	x1, l_.str.13@PAGE
Lloh25:
	add	x1, x1, l_.str.13@PAGEOFF
	bl	_of_property_read_bool
	str	x0, [x19, #24]
Lloh26:
	adrp	x1, l_.str.14@PAGE
Lloh27:
	add	x1, x1, l_.str.14@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_bool
	mov	w21, #0
	str	x0, [x19, #8]
	b	LBB0_16
LBB0_14:
	ldr	x0, [x19, #16]
Lloh28:
	adrp	x1, l_.str.11@PAGE
Lloh29:
	add	x1, x1, l_.str.11@PAGEOFF
LBB0_15:
	mov	x2, x21
	bl	_dev_err
LBB0_16:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"nvidia,aspm-cmrt-us"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to read ASPM T_cmrt: %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"nvidia,aspm-pwr-on-t-us"

l_.str.3:                               ; @.str.3
	.asciz	"Failed to read ASPM Power On time: %d\n"

l_.str.4:                               ; @.str.4
	.asciz	"nvidia,aspm-l0s-entrance-latency-us"

l_.str.5:                               ; @.str.5
	.asciz	"Failed to read ASPM L0s Entrance latency: %d\n"

l_.str.6:                               ; @.str.6
	.asciz	"num-lanes"

l_.str.7:                               ; @.str.7
	.asciz	"Failed to read num-lanes: %d\n"

l_.str.8:                               ; @.str.8
	.asciz	"nvidia,bpmp"

l_.str.9:                               ; @.str.9
	.asciz	"Failed to read Controller-ID: %d\n"

l_.str.10:                              ; @.str.10
	.asciz	"phy-names"

l_.str.11:                              ; @.str.11
	.asciz	"Failed to find PHY entries: %d\n"

l_.str.12:                              ; @.str.12
	.asciz	"nvidia,update-fc-fixup"

l_.str.13:                              ; @.str.13
	.asciz	"supports-clkreq"

l_.str.14:                              ; @.str.14
	.asciz	"snps,enable-cdm-check"

	.no_dead_strip	_tegra_pcie_dw_parse_dt
.subsections_via_symbols
