	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function kirin_pcie_clk_ctrl
_kirin_pcie_clk_ctrl:                   ## @kirin_pcie_clk_ctrl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	testl	%esi, %esi
	je	LBB0_8
## %bb.1:
	movl	(%r14), %edi
	movq	_REF_CLK_FREQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_clk_set_rate
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_13
## %bb.2:
	movl	(%r14), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_13
## %bb.3:
	movl	4(%r14), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_12
## %bb.4:
	movl	8(%r14), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_11
## %bb.5:
	movl	12(%r14), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_10
## %bb.6:
	movl	16(%r14), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_9
## %bb.7:
	xorl	%ebx, %ebx
	jmp	LBB0_13
LBB0_8:
	movl	16(%r14), %edi
	callq	_clk_disable_unprepare
	xorl	%ebx, %ebx
LBB0_9:
	movl	12(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_10:
	movl	8(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_11:
	movl	4(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_12:
	movl	(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_13:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_REF_CLK_FREQ,4,2               ## @REF_CLK_FREQ
	.no_dead_strip	_kirin_pcie_clk_ctrl
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function kirin_pcie_clk_ctrl
_kirin_pcie_clk_ctrl:                   ; @kirin_pcie_clk_ctrl
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	cbz	w1, LBB0_7
; %bb.1:
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _REF_CLK_FREQ@GOTPAGE
Lloh1:
	ldr	x8, [x8, _REF_CLK_FREQ@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_clk_set_rate
	mov	x20, x0
	cbnz	w0, LBB0_12
; %bb.2:
	ldr	w0, [x19]
	bl	_clk_prepare_enable
	mov	x20, x0
	cbnz	w0, LBB0_12
; %bb.3:
	ldr	w0, [x19, #4]
	bl	_clk_prepare_enable
	mov	x20, x0
	cbnz	w0, LBB0_11
; %bb.4:
	ldr	w0, [x19, #8]
	bl	_clk_prepare_enable
	mov	x20, x0
	cbnz	w0, LBB0_10
; %bb.5:
	ldr	w0, [x19, #12]
	bl	_clk_prepare_enable
	mov	x20, x0
	cbnz	w0, LBB0_9
; %bb.6:
	ldr	w0, [x19, #16]
	bl	_clk_prepare_enable
	mov	x20, x0
	cbnz	w0, LBB0_8
	b	LBB0_12
LBB0_7:
	ldr	w0, [x19, #16]
	bl	_clk_disable_unprepare
	mov	w20, #0
LBB0_8:
	ldr	w0, [x19, #12]
	bl	_clk_disable_unprepare
LBB0_9:
	ldr	w0, [x19, #8]
	bl	_clk_disable_unprepare
LBB0_10:
	ldr	w0, [x19, #4]
	bl	_clk_disable_unprepare
LBB0_11:
	ldr	w0, [x19]
	bl	_clk_disable_unprepare
LBB0_12:
	mov	x0, x20
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_REF_CLK_FREQ,4,2               ; @REF_CLK_FREQ
	.no_dead_strip	_kirin_pcie_clk_ctrl
.subsections_via_symbols
