	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_sram_shift_set
_mvpp2_prs_sram_shift_set:              ## @mvpp2_prs_sram_shift_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r14d
	movl	%esi, %ebx
	movq	%rdi, %r15
	movq	_MVPP2_PRS_SRAM_SHIFT_SIGN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edx
	testl	%ebx, %ebx
	js	LBB0_1
## %bb.2:
	callq	_mvpp2_prs_sram_bits_clear
	jmp	LBB0_3
LBB0_1:
	callq	_mvpp2_prs_sram_bits_set
	negl	%ebx
LBB0_3:
	movq	_MVPP2_PRS_SRAM_SHIFT_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	movq	(%r15), %r12
	movq	_MVPP2_PRS_SRAM_SHIFT_OFFS@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_MVPP2_BIT_TO_WORD
	orl	%ebx, (%r12,%rax,4)
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_sram_bits_clear
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvpp2_prs_sram_bits_clear      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PRS_SRAM_SHIFT_SIGN_BIT,4,2 ## @MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
	.comm	_MVPP2_PRS_SRAM_SHIFT_MASK,4,2  ## @MVPP2_PRS_SRAM_SHIFT_MASK
	.comm	_MVPP2_PRS_SRAM_SHIFT_OFFS,4,2  ## @MVPP2_PRS_SRAM_SHIFT_OFFS
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
	.no_dead_strip	_mvpp2_prs_sram_shift_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_sram_shift_set
_mvpp2_prs_sram_shift_set:              ; @mvpp2_prs_sram_shift_set
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x2
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _MVPP2_PRS_SRAM_SHIFT_SIGN_BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_SHIFT_SIGN_BIT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #1
	tbnz	w21, #31, LBB0_2
; %bb.1:
	bl	_mvpp2_prs_sram_bits_clear
	b	LBB0_3
LBB0_2:
	bl	_mvpp2_prs_sram_bits_set
	neg	w21, w21
LBB0_3:
Lloh3:
	adrp	x8, _MVPP2_PRS_SRAM_SHIFT_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_SHIFT_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	and	w21, w8, w21
	ldr	x22, [x19]
Lloh6:
	adrp	x8, _MVPP2_PRS_SRAM_SHIFT_OFFS@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_SHIFT_OFFS@GOTPAGEOFF]
Lloh8:
	ldr	w0, [x8]
	bl	_MVPP2_BIT_TO_WORD
	lsl	x8, x0, #2
	ldr	w9, [x22, x8]
	orr	w9, w9, w21
	str	w9, [x22, x8]
Lloh9:
	adrp	x21, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS@GOTPAGE
Lloh10:
	ldr	x21, [x21, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh11:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_sram_bits_clear
	ldr	w1, [x21]
	mov	x0, x19
	mov	x2, x20
	bl	_mvpp2_prs_sram_bits_set
Lloh14:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mvpp2_prs_sram_bits_clear
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PRS_SRAM_SHIFT_SIGN_BIT,4,2 ; @MVPP2_PRS_SRAM_SHIFT_SIGN_BIT
	.comm	_MVPP2_PRS_SRAM_SHIFT_MASK,4,2  ; @MVPP2_PRS_SRAM_SHIFT_MASK
	.comm	_MVPP2_PRS_SRAM_SHIFT_OFFS,4,2  ; @MVPP2_PRS_SRAM_SHIFT_OFFS
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
	.no_dead_strip	_mvpp2_prs_sram_shift_set
.subsections_via_symbols
