	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_power_on
_tegra_pcie_power_on:                   ## @tegra_pcie_power_on
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	40(%rdi), %r14
	movq	32(%rdi), %r12
	movl	28(%rdi), %edi
	callq	_reset_control_assert
	movl	16(%rbx), %edi
	callq	_reset_control_assert
	movl	24(%rbx), %edi
	callq	_reset_control_assert
	cmpl	$0, (%r14)
	jne	LBB0_2
## %bb.1:
	movq	_TEGRA_POWERGATE_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_tegra_powergate_power_off
LBB0_2:
	movl	(%rbx), %esi
	movl	4(%rbx), %edi
	callq	_regulator_bulk_enable
	testl	%eax, %eax
	js	LBB0_3
## %bb.4:
	cmpl	$0, (%r14)
	jne	LBB0_10
	jmp	LBB0_5
LBB0_3:
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_dev_err
	cmpl	$0, (%r14)
	je	LBB0_5
LBB0_10:
	movl	8(%rbx), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	js	LBB0_11
## %bb.12:
	cmpq	$0, (%r12)
	je	LBB0_15
## %bb.13:
	movl	12(%rbx), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	js	LBB0_14
LBB0_15:
	movl	20(%rbx), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	js	LBB0_16
## %bb.23:
	movl	16(%rbx), %edi
	callq	_reset_control_deassert
	xorl	%r15d, %r15d
	jmp	LBB0_22
LBB0_5:
	movq	_TEGRA_POWERGATE_PCIE@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	callq	_tegra_powergate_power_on
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %r15d
	leaq	L_.str.1(%rip), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_dev_err
	jmp	LBB0_21
LBB0_11:
	movl	%eax, %r15d
	leaq	L_.str.3(%rip), %rsi
	jmp	LBB0_9
LBB0_7:
	movl	(%r13), %edi
	callq	_tegra_powergate_remove_clamping
	testl	%eax, %eax
	je	LBB0_10
## %bb.8:
	movl	%eax, %r15d
	leaq	L_.str.2(%rip), %rsi
LBB0_9:
	movq	%r14, %rdi
	movl	%r15d, %edx
	callq	_dev_err
	cmpl	$0, (%r14)
	jne	LBB0_21
LBB0_20:
	movq	_TEGRA_POWERGATE_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_tegra_powergate_power_off
LBB0_21:
	movl	(%rbx), %esi
	movl	4(%rbx), %edi
	callq	_regulator_bulk_disable
LBB0_22:
	movl	%r15d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	movl	%eax, %r15d
	leaq	L_.str.5(%rip), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_dev_err
	cmpq	$0, (%r12)
	je	LBB0_18
## %bb.17:
	movl	12(%rbx), %edi
	callq	_clk_disable_unprepare
	jmp	LBB0_18
LBB0_14:
	movl	%eax, %r15d
	leaq	L_.str.4(%rip), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_dev_err
LBB0_18:
	movl	8(%rbx), %edi
	callq	_clk_disable_unprepare
	cmpl	$0, (%r14)
	jne	LBB0_21
	jmp	LBB0_20
	.cfi_endproc
                                        ## -- End function
	.comm	_TEGRA_POWERGATE_PCIE,4,2       ## @TEGRA_POWERGATE_PCIE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to enable regulators: %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"failed to power ungate: %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"failed to remove clamp: %d\n"

L_.str.3:                               ## @.str.3
	.asciz	"failed to enable AFI clock: %d\n"

L_.str.4:                               ## @.str.4
	.asciz	"failed to enable CML clock: %d\n"

L_.str.5:                               ## @.str.5
	.asciz	"failed to enable PLLE clock: %d\n"

	.no_dead_strip	_tegra_pcie_power_on
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_power_on
_tegra_pcie_power_on:                   ; @tegra_pcie_power_on
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldp	x22, x20, [x0, #32]
	ldr	w0, [x0, #28]
	bl	_reset_control_assert
	ldr	w0, [x19, #16]
	bl	_reset_control_assert
	ldr	w0, [x19, #24]
	bl	_reset_control_assert
	ldr	w8, [x20]
	cbnz	w8, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _TEGRA_POWERGATE_PCIE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _TEGRA_POWERGATE_PCIE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_tegra_powergate_power_off
LBB0_2:
	ldp	w1, w0, [x19]
	bl	_regulator_bulk_enable
	tbnz	w0, #31, LBB0_4
; %bb.3:
	ldr	w8, [x20]
	cbnz	w8, LBB0_5
	b	LBB0_10
LBB0_4:
	mov	x2, x0
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_dev_err
	ldr	w8, [x20]
	cbz	w8, LBB0_10
LBB0_5:
	ldr	w0, [x19, #8]
	bl	_clk_prepare_enable
	tbnz	w0, #31, LBB0_12
; %bb.6:
	ldr	x8, [x22]
	cbz	x8, LBB0_8
; %bb.7:
	ldr	w0, [x19, #12]
	bl	_clk_prepare_enable
	tbnz	w0, #31, LBB0_21
LBB0_8:
	ldr	w0, [x19, #20]
	bl	_clk_prepare_enable
	tbnz	w0, #31, LBB0_19
; %bb.9:
	ldr	w0, [x19, #16]
	bl	_reset_control_deassert
	mov	w21, #0
	b	LBB0_18
LBB0_10:
Lloh5:
	adrp	x23, _TEGRA_POWERGATE_PCIE@GOTPAGE
Lloh6:
	ldr	x23, [x23, _TEGRA_POWERGATE_PCIE@GOTPAGEOFF]
	ldr	w0, [x23]
	bl	_tegra_powergate_power_on
	cbz	w0, LBB0_13
; %bb.11:
	mov	x21, x0
Lloh7:
	adrp	x1, l_.str.1@PAGE
Lloh8:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
	b	LBB0_17
LBB0_12:
	mov	x21, x0
Lloh9:
	adrp	x1, l_.str.3@PAGE
Lloh10:
	add	x1, x1, l_.str.3@PAGEOFF
	b	LBB0_15
LBB0_13:
	ldr	w0, [x23]
	bl	_tegra_powergate_remove_clamping
	cbz	w0, LBB0_5
; %bb.14:
	mov	x21, x0
Lloh11:
	adrp	x1, l_.str.2@PAGE
Lloh12:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_15:
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
	ldr	w8, [x20]
	cbnz	w8, LBB0_17
LBB0_16:
Lloh13:
	adrp	x8, _TEGRA_POWERGATE_PCIE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _TEGRA_POWERGATE_PCIE@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
	bl	_tegra_powergate_power_off
LBB0_17:
	ldp	w1, w0, [x19]
	bl	_regulator_bulk_disable
LBB0_18:
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_19:
	mov	x21, x0
Lloh16:
	adrp	x1, l_.str.5@PAGE
Lloh17:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
	ldr	x8, [x22]
	cbz	x8, LBB0_22
; %bb.20:
	ldr	w0, [x19, #12]
	bl	_clk_disable_unprepare
	b	LBB0_22
LBB0_21:
	mov	x21, x0
Lloh18:
	adrp	x1, l_.str.4@PAGE
Lloh19:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x20
	mov	x2, x21
	bl	_dev_err
LBB0_22:
	ldr	w0, [x19, #8]
	bl	_clk_disable_unprepare
	ldr	w8, [x20]
	cbnz	w8, LBB0_17
	b	LBB0_16
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpAdd	Lloh16, Lloh17
	.loh AdrpAdd	Lloh18, Lloh19
	.cfi_endproc
                                        ; -- End function
	.comm	_TEGRA_POWERGATE_PCIE,4,2       ; @TEGRA_POWERGATE_PCIE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to enable regulators: %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"failed to power ungate: %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"failed to remove clamp: %d\n"

l_.str.3:                               ; @.str.3
	.asciz	"failed to enable AFI clock: %d\n"

l_.str.4:                               ; @.str.4
	.asciz	"failed to enable CML clock: %d\n"

l_.str.5:                               ; @.str.5
	.asciz	"failed to enable PLLE clock: %d\n"

	.no_dead_strip	_tegra_pcie_power_on
.subsections_via_symbols
