	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function brcm_fet_config_init
_brcm_fet_config_init:                  ## @brcm_fet_config_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_MII_BMCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_BMCR_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_15
## %bb.1:
	movq	_MII_BRCM_FET_INTREG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_phy_read
	testl	%eax, %eax
	js	LBB0_15
## %bb.2:
	movq	_MII_BRCM_FET_IR_DUPLEX_EN@GOTPCREL(%rip), %rax
	movq	_MII_BRCM_FET_IR_SPEED_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_MII_BRCM_FET_IR_LINK_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_MII_BRCM_FET_IR_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_MII_BRCM_FET_IR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_15
## %bb.3:
	movq	_MII_BRCM_FET_BRCMTEST@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_phy_read
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_16
## %bb.4:
	movq	_MII_BRCM_FET_BT_SRE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%ebx, %edx
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_15
## %bb.5:
	movq	_MII_BRCM_FET_SHDW_AUXMODE4@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_phy_read
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_11
## %bb.6:
	movq	_MII_BRCM_FET_SHDW_AM4_LED_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	_MII_BRCM_FET_SHDW_AM4_LED_MODE1@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movl	(%r13), %esi
	movq	%r14, %rdi
	movl	%r15d, %edx
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_10
## %bb.7:
	movq	_MII_BRCM_FET_SHDW_MISCCTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_BRCM_FET_SHDW_MC_FAME@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_brcm_phy_setbits
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_11
## %bb.8:
	movq	_PHY_BRCM_AUTO_PWRDWN_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, (%r14)
	je	LBB0_11
## %bb.9:
	movq	_MII_BRCM_FET_SHDW_AUXSTAT2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_BRCM_FET_SHDW_AS2_APDE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_brcm_phy_setbits
LBB0_10:
	movl	%eax, %r15d
LBB0_11:
	movl	(%r12), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_phy_write
	movl	%eax, %ebx
	testl	%r15d, %r15d
	cmovnel	%r15d, %ebx
	jmp	LBB0_16
LBB0_15:
	movl	%eax, %ebx
LBB0_16:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MII_BMCR,4,2                   ## @MII_BMCR
	.comm	_BMCR_RESET,4,2                 ## @BMCR_RESET
	.comm	_MII_BRCM_FET_INTREG,4,2        ## @MII_BRCM_FET_INTREG
	.comm	_MII_BRCM_FET_IR_DUPLEX_EN,4,2  ## @MII_BRCM_FET_IR_DUPLEX_EN
	.comm	_MII_BRCM_FET_IR_SPEED_EN,4,2   ## @MII_BRCM_FET_IR_SPEED_EN
	.comm	_MII_BRCM_FET_IR_LINK_EN,4,2    ## @MII_BRCM_FET_IR_LINK_EN
	.comm	_MII_BRCM_FET_IR_ENABLE,4,2     ## @MII_BRCM_FET_IR_ENABLE
	.comm	_MII_BRCM_FET_IR_MASK,4,2       ## @MII_BRCM_FET_IR_MASK
	.comm	_MII_BRCM_FET_BRCMTEST,4,2      ## @MII_BRCM_FET_BRCMTEST
	.comm	_MII_BRCM_FET_BT_SRE,4,2        ## @MII_BRCM_FET_BT_SRE
	.comm	_MII_BRCM_FET_SHDW_AUXMODE4,4,2 ## @MII_BRCM_FET_SHDW_AUXMODE4
	.comm	_MII_BRCM_FET_SHDW_AM4_LED_MASK,4,2 ## @MII_BRCM_FET_SHDW_AM4_LED_MASK
	.comm	_MII_BRCM_FET_SHDW_AM4_LED_MODE1,4,2 ## @MII_BRCM_FET_SHDW_AM4_LED_MODE1
	.comm	_MII_BRCM_FET_SHDW_MISCCTRL,4,2 ## @MII_BRCM_FET_SHDW_MISCCTRL
	.comm	_MII_BRCM_FET_SHDW_MC_FAME,4,2  ## @MII_BRCM_FET_SHDW_MC_FAME
	.comm	_PHY_BRCM_AUTO_PWRDWN_ENABLE,4,2 ## @PHY_BRCM_AUTO_PWRDWN_ENABLE
	.comm	_MII_BRCM_FET_SHDW_AUXSTAT2,4,2 ## @MII_BRCM_FET_SHDW_AUXSTAT2
	.comm	_MII_BRCM_FET_SHDW_AS2_APDE,4,2 ## @MII_BRCM_FET_SHDW_AS2_APDE
	.no_dead_strip	_brcm_fet_config_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function brcm_fet_config_init
_brcm_fet_config_init:                  ; @brcm_fet_config_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _MII_BMCR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MII_BMCR@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _BMCR_RESET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _BMCR_RESET@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_phy_write
	tbnz	w0, #31, LBB0_12
; %bb.1:
Lloh6:
	adrp	x21, _MII_BRCM_FET_INTREG@GOTPAGE
Lloh7:
	ldr	x21, [x21, _MII_BRCM_FET_INTREG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_phy_read
	tbnz	w0, #31, LBB0_12
; %bb.2:
Lloh8:
	adrp	x8, _MII_BRCM_FET_IR_DUPLEX_EN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MII_BRCM_FET_IR_DUPLEX_EN@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x9, _MII_BRCM_FET_IR_SPEED_EN@GOTPAGE
Lloh12:
	ldr	x9, [x9, _MII_BRCM_FET_IR_SPEED_EN@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
Lloh14:
	adrp	x10, _MII_BRCM_FET_IR_LINK_EN@GOTPAGE
Lloh15:
	ldr	x10, [x10, _MII_BRCM_FET_IR_LINK_EN@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh16:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh17:
	adrp	x9, _MII_BRCM_FET_IR_ENABLE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _MII_BRCM_FET_IR_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh20:
	adrp	x9, _MII_BRCM_FET_IR_MASK@GOTPAGE
Lloh21:
	ldr	x9, [x9, _MII_BRCM_FET_IR_MASK@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	w1, [x21]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_12
; %bb.3:
Lloh23:
	adrp	x22, _MII_BRCM_FET_BRCMTEST@GOTPAGE
Lloh24:
	ldr	x22, [x22, _MII_BRCM_FET_BRCMTEST@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_phy_read
	mov	x20, x0
	tbnz	w0, #31, LBB0_13
; %bb.4:
Lloh25:
	adrp	x8, _MII_BRCM_FET_BT_SRE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _MII_BRCM_FET_BT_SRE@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	orr	w2, w8, w20
	ldr	w1, [x22]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_12
; %bb.5:
Lloh28:
	adrp	x23, _MII_BRCM_FET_SHDW_AUXMODE4@GOTPAGE
Lloh29:
	ldr	x23, [x23, _MII_BRCM_FET_SHDW_AUXMODE4@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_phy_read
	mov	x21, x0
	tbnz	w0, #31, LBB0_11
; %bb.6:
Lloh30:
	adrp	x8, _MII_BRCM_FET_SHDW_AM4_LED_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MII_BRCM_FET_SHDW_AM4_LED_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	bic	w8, w21, w8
Lloh33:
	adrp	x9, _MII_BRCM_FET_SHDW_AM4_LED_MODE1@GOTPAGE
Lloh34:
	ldr	x9, [x9, _MII_BRCM_FET_SHDW_AM4_LED_MODE1@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	w1, [x23]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_10
; %bb.7:
Lloh36:
	adrp	x8, _MII_BRCM_FET_SHDW_MISCCTRL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MII_BRCM_FET_SHDW_MISCCTRL@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x8, _MII_BRCM_FET_SHDW_MC_FAME@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MII_BRCM_FET_SHDW_MC_FAME@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_brcm_phy_setbits
	mov	x21, x0
	tbnz	w0, #31, LBB0_11
; %bb.8:
	ldr	w8, [x19]
Lloh42:
	adrp	x9, _PHY_BRCM_AUTO_PWRDWN_ENABLE@GOTPAGE
Lloh43:
	ldr	x9, [x9, _PHY_BRCM_AUTO_PWRDWN_ENABLE@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_11
; %bb.9:
Lloh45:
	adrp	x8, _MII_BRCM_FET_SHDW_AUXSTAT2@GOTPAGE
Lloh46:
	ldr	x8, [x8, _MII_BRCM_FET_SHDW_AUXSTAT2@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
Lloh48:
	adrp	x8, _MII_BRCM_FET_SHDW_AS2_APDE@GOTPAGE
Lloh49:
	ldr	x8, [x8, _MII_BRCM_FET_SHDW_AS2_APDE@GOTPAGEOFF]
Lloh50:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_brcm_phy_setbits
LBB0_10:
	mov	x21, x0
LBB0_11:
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_phy_write
	cmp	w21, #0
	csel	w20, w0, w21, eq
	b	LBB0_13
LBB0_12:
	mov	x20, x0
LBB0_13:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.cfi_endproc
                                        ; -- End function
	.comm	_MII_BMCR,4,2                   ; @MII_BMCR
	.comm	_BMCR_RESET,4,2                 ; @BMCR_RESET
	.comm	_MII_BRCM_FET_INTREG,4,2        ; @MII_BRCM_FET_INTREG
	.comm	_MII_BRCM_FET_IR_DUPLEX_EN,4,2  ; @MII_BRCM_FET_IR_DUPLEX_EN
	.comm	_MII_BRCM_FET_IR_SPEED_EN,4,2   ; @MII_BRCM_FET_IR_SPEED_EN
	.comm	_MII_BRCM_FET_IR_LINK_EN,4,2    ; @MII_BRCM_FET_IR_LINK_EN
	.comm	_MII_BRCM_FET_IR_ENABLE,4,2     ; @MII_BRCM_FET_IR_ENABLE
	.comm	_MII_BRCM_FET_IR_MASK,4,2       ; @MII_BRCM_FET_IR_MASK
	.comm	_MII_BRCM_FET_BRCMTEST,4,2      ; @MII_BRCM_FET_BRCMTEST
	.comm	_MII_BRCM_FET_BT_SRE,4,2        ; @MII_BRCM_FET_BT_SRE
	.comm	_MII_BRCM_FET_SHDW_AUXMODE4,4,2 ; @MII_BRCM_FET_SHDW_AUXMODE4
	.comm	_MII_BRCM_FET_SHDW_AM4_LED_MASK,4,2 ; @MII_BRCM_FET_SHDW_AM4_LED_MASK
	.comm	_MII_BRCM_FET_SHDW_AM4_LED_MODE1,4,2 ; @MII_BRCM_FET_SHDW_AM4_LED_MODE1
	.comm	_MII_BRCM_FET_SHDW_MISCCTRL,4,2 ; @MII_BRCM_FET_SHDW_MISCCTRL
	.comm	_MII_BRCM_FET_SHDW_MC_FAME,4,2  ; @MII_BRCM_FET_SHDW_MC_FAME
	.comm	_PHY_BRCM_AUTO_PWRDWN_ENABLE,4,2 ; @PHY_BRCM_AUTO_PWRDWN_ENABLE
	.comm	_MII_BRCM_FET_SHDW_AUXSTAT2,4,2 ; @MII_BRCM_FET_SHDW_AUXSTAT2
	.comm	_MII_BRCM_FET_SHDW_AS2_APDE,4,2 ; @MII_BRCM_FET_SHDW_AS2_APDE
	.no_dead_strip	_brcm_fet_config_init
.subsections_via_symbols
