	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dp83867_config_init
_dp83867_config_init:                   ## @dp83867_config_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %r12
	callq	_dp83867_of_init
	movl	%eax, %ebx
	testl	%eax, %eax
	je	LBB0_1
LBB0_22:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	cmpq	$0, 56(%r12)
	je	LBB0_3
## %bb.2:
	movq	_DP83867_DEVADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_DP83867_CFG4@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$7, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_phy_clear_bits_mmd
LBB0_3:
	movq	%r14, %rdi
	callq	_phy_interface_is_rgmii
	testq	%rax, %rax
	je	LBB0_7
## %bb.4:
	movq	_MII_DP83867_PHYCTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_phy_read
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_22
## %bb.5:
	movq	_DP83867_PHYCR_FIFO_DEPTH_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	movl	(%r12), %r13d
	movq	_DP83867_PHYCR_FIFO_DEPTH_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r13d
	orl	%ebx, %r13d
	movq	_DP83867_DEVADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP83867_STRAP_STS1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_read_mmd
	movq	_DP83867_STRAP_STS1_RESERVED@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_DP83867_PHYCR_RESERVED_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	%r15, %rsi
	xorl	%r15d, %r15d
	cmpl	$1, %eax
	movl	$0, %edx
	sbbl	%edx, %edx
	notl	%ecx
	orl	%ecx, %edx
	andl	%r13d, %edx
	movl	(%rsi), %esi
	movq	%r14, %rdi
	callq	_phy_write
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_22
## %bb.6:
	movq	_DP83867_DEVADDR@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_DP83867_RGMIICTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_read_mmd
	movq	_DP83867_RGMII_TX_CLK_DELAY_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_DP83867_RGMII_RX_CLK_DELAY_EN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	orl	%ecx, %esi
	movl	%esi, %edi
	notl	%edi
	andl	%eax, %edi
	movq	(%r14), %rbx
	movq	_PHY_INTERFACE_MODE_RGMII_ID@GOTPCREL(%rip), %r8
	orl	%eax, %esi
	cmpq	(%r8), %rbx
	cmovnel	%edi, %esi
	movq	_PHY_INTERFACE_MODE_RGMII_TXID@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rbx
	cmovnel	%r15d, %ecx
	movq	_PHY_INTERFACE_MODE_RGMII_RXID@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rbx
	cmovel	%edx, %r15d
	orl	%ecx, %r15d
	orl	%esi, %r15d
	movl	(%r13), %esi
	movq	_DP83867_RGMIICTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%r15d, %ecx
	callq	_phy_write_mmd
	movl	8(%r12), %eax
	movq	_DP83867_RGMII_TX_CLK_DELAY_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	orl	4(%r12), %eax
	movl	(%r13), %esi
	movq	_DP83867_RGMIIDCTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %ecx
	callq	_phy_write_mmd
LBB0_7:
	movq	16(%r12), %r8
	testq	%r8, %r8
	js	LBB0_9
## %bb.8:
	movq	_DP83867_DEVADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP83867_IO_MUX_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
                                        ## kill: def $r8d killed $r8d killed $r8
	callq	_phy_modify_mmd
LBB0_9:
	movq	(%r14), %rax
	movq	_PHY_INTERFACE_MODE_SGMII@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_13
## %bb.10:
	movq	_DP83867_DEVADDR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_DP83867_10M_SGMII_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DP83867_10M_SGMII_RATE_ADAPT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	xorl	%r8d, %r8d
	callq	_phy_modify_mmd
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_22
## %bb.11:
	movl	(%r15), %esi
	movq	_DP83867_CFG4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_DP83867_CFG4_SGMII_ANEG_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	_DP83867_CFG4_SGMII_ANEG_TIMER_16MS@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	movq	%r14, %rdi
	callq	_phy_modify_mmd
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_22
## %bb.12:
	movl	(%r15), %esi
	movq	_DP83867_SGMIICTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_phy_read_mmd
	movq	_DP83867_SGMII_TYPE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, %edx
	orl	%eax, %edx
	notl	%ecx
	andl	%eax, %ecx
	cmpq	$0, 48(%r12)
	cmovnel	%edx, %ecx
	movl	(%r15), %esi
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_phy_write_mmd
LBB0_13:
	movq	%r14, %rdi
	callq	_phy_interrupt_is_valid
	testq	%rax, %rax
	je	LBB0_15
## %bb.14:
	movq	_DP83867_CFG3@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_phy_read
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_BIT
	orl	%eax, %ebx
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_phy_write
LBB0_15:
	movq	24(%r12), %rax
	movq	_DP83867_PORT_MIRROING_KEEP@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_17
## %bb.16:
	movq	%r14, %rdi
	callq	_dp83867_config_port_mirroring
LBB0_17:
	cmpq	$0, 40(%r12)
	je	LBB0_18
## %bb.19:
	movq	_DP83867_IO_MUX_CFG_CLK_O_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	32(%r12), %esi
	movq	_DP83867_CLK_O_SEL_OFF@GOTPCREL(%rip), %rdi
	movq	_DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	%esi, %edx
	shll	%cl, %edx
	xorl	%ebx, %ebx
	movl	%eax, %r8d
	movl	$0, %ecx
	cmpl	(%rdi), %esi
	je	LBB0_21
## %bb.20:
	movq	_DP83867_IO_MUX_CFG_CLK_O_SEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%edx, %r8d
LBB0_21:
	orl	%eax, %ecx
	movq	_DP83867_DEVADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DP83867_IO_MUX_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_modify_mmd
	jmp	LBB0_22
LBB0_18:
	xorl	%ebx, %ebx
	jmp	LBB0_22
	.cfi_endproc
                                        ## -- End function
	.comm	_DP83867_DEVADDR,4,2            ## @DP83867_DEVADDR
	.comm	_DP83867_CFG4,4,2               ## @DP83867_CFG4
	.comm	_MII_DP83867_PHYCTRL,4,2        ## @MII_DP83867_PHYCTRL
	.comm	_DP83867_PHYCR_FIFO_DEPTH_MASK,4,2 ## @DP83867_PHYCR_FIFO_DEPTH_MASK
	.comm	_DP83867_PHYCR_FIFO_DEPTH_SHIFT,4,2 ## @DP83867_PHYCR_FIFO_DEPTH_SHIFT
	.comm	_DP83867_STRAP_STS1,4,2         ## @DP83867_STRAP_STS1
	.comm	_DP83867_STRAP_STS1_RESERVED,4,2 ## @DP83867_STRAP_STS1_RESERVED
	.comm	_DP83867_PHYCR_RESERVED_MASK,4,2 ## @DP83867_PHYCR_RESERVED_MASK
	.comm	_DP83867_RGMIICTL,4,2           ## @DP83867_RGMIICTL
	.comm	_DP83867_RGMII_TX_CLK_DELAY_EN,4,2 ## @DP83867_RGMII_TX_CLK_DELAY_EN
	.comm	_DP83867_RGMII_RX_CLK_DELAY_EN,4,2 ## @DP83867_RGMII_RX_CLK_DELAY_EN
	.comm	_PHY_INTERFACE_MODE_RGMII_ID,8,3 ## @PHY_INTERFACE_MODE_RGMII_ID
	.comm	_PHY_INTERFACE_MODE_RGMII_TXID,8,3 ## @PHY_INTERFACE_MODE_RGMII_TXID
	.comm	_PHY_INTERFACE_MODE_RGMII_RXID,8,3 ## @PHY_INTERFACE_MODE_RGMII_RXID
	.comm	_DP83867_RGMII_TX_CLK_DELAY_SHIFT,4,2 ## @DP83867_RGMII_TX_CLK_DELAY_SHIFT
	.comm	_DP83867_RGMIIDCTL,4,2          ## @DP83867_RGMIIDCTL
	.comm	_DP83867_IO_MUX_CFG,4,2         ## @DP83867_IO_MUX_CFG
	.comm	_DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,4,2 ## @DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK
	.comm	_PHY_INTERFACE_MODE_SGMII,8,3   ## @PHY_INTERFACE_MODE_SGMII
	.comm	_DP83867_10M_SGMII_CFG,4,2      ## @DP83867_10M_SGMII_CFG
	.comm	_DP83867_10M_SGMII_RATE_ADAPT_MASK,4,2 ## @DP83867_10M_SGMII_RATE_ADAPT_MASK
	.comm	_DP83867_CFG4_SGMII_ANEG_MASK,4,2 ## @DP83867_CFG4_SGMII_ANEG_MASK
	.comm	_DP83867_CFG4_SGMII_ANEG_TIMER_16MS,4,2 ## @DP83867_CFG4_SGMII_ANEG_TIMER_16MS
	.comm	_DP83867_SGMIICTL,4,2           ## @DP83867_SGMIICTL
	.comm	_DP83867_SGMII_TYPE,4,2         ## @DP83867_SGMII_TYPE
	.comm	_DP83867_CFG3,4,2               ## @DP83867_CFG3
	.comm	_DP83867_PORT_MIRROING_KEEP,8,3 ## @DP83867_PORT_MIRROING_KEEP
	.comm	_DP83867_IO_MUX_CFG_CLK_O_DISABLE,4,2 ## @DP83867_IO_MUX_CFG_CLK_O_DISABLE
	.comm	_DP83867_CLK_O_SEL_OFF,4,2      ## @DP83867_CLK_O_SEL_OFF
	.comm	_DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,4,2 ## @DP83867_IO_MUX_CFG_CLK_O_SEL_MASK
	.comm	_DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT,4,2 ## @DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT
	.no_dead_strip	_dp83867_config_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dp83867_config_init
_dp83867_config_init:                   ; @dp83867_config_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x23, [x0, #8]
	bl	_dp83867_of_init
	cbz	w0, LBB0_2
LBB0_1:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_2:
	ldr	x8, [x23, #56]
Lloh0:
	adrp	x22, _DP83867_DEVADDR@GOTPAGE
Lloh1:
	ldr	x22, [x22, _DP83867_DEVADDR@GOTPAGEOFF]
	cbz	x8, LBB0_4
; %bb.3:
	ldr	w20, [x22]
Lloh2:
	adrp	x8, _DP83867_CFG4@GOTPAGE
Lloh3:
	ldr	x8, [x8, _DP83867_CFG4@GOTPAGEOFF]
Lloh4:
	ldr	w21, [x8]
	mov	w0, #7
	bl	_BIT
	mov	x3, x0
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_phy_clear_bits_mmd
LBB0_4:
	mov	x0, x19
	bl	_phy_interface_is_rgmii
	cbz	x0, LBB0_8
; %bb.5:
Lloh5:
	adrp	x20, _MII_DP83867_PHYCTRL@GOTPAGE
Lloh6:
	ldr	x20, [x20, _MII_DP83867_PHYCTRL@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_phy_read
	tbnz	w0, #31, LBB0_1
; %bb.6:
Lloh7:
	adrp	x8, _DP83867_PHYCR_FIFO_DEPTH_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _DP83867_PHYCR_FIFO_DEPTH_MASK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x23]
Lloh10:
	adrp	x10, _DP83867_PHYCR_FIFO_DEPTH_SHIFT@GOTPAGE
Lloh11:
	ldr	x10, [x10, _DP83867_PHYCR_FIFO_DEPTH_SHIFT@GOTPAGEOFF]
Lloh12:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w21, w9, w8
	ldr	w1, [x22]
Lloh13:
	adrp	x8, _DP83867_STRAP_STS1@GOTPAGE
Lloh14:
	ldr	x8, [x8, _DP83867_STRAP_STS1@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_read_mmd
Lloh16:
	adrp	x8, _DP83867_STRAP_STS1_RESERVED@GOTPAGE
Lloh17:
	ldr	x8, [x8, _DP83867_STRAP_STS1_RESERVED@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	adrp	x9, _DP83867_PHYCR_RESERVED_MASK@GOTPAGE
Lloh20:
	ldr	x9, [x9, _DP83867_PHYCR_RESERVED_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	tst	w8, w0
	mov	w8, #-1
	csinv	w8, w8, w9, eq
	and	w2, w8, w21
	ldr	w1, [x20]
	mov	x0, x19
	bl	_phy_write
	cbnz	w0, LBB0_1
; %bb.7:
	ldr	w1, [x22]
Lloh22:
	adrp	x20, _DP83867_RGMIICTL@GOTPAGE
Lloh23:
	ldr	x20, [x20, _DP83867_RGMIICTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_phy_read_mmd
Lloh24:
	adrp	x8, _DP83867_RGMII_TX_CLK_DELAY_EN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DP83867_RGMII_TX_CLK_DELAY_EN@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _DP83867_RGMII_RX_CLK_DELAY_EN@GOTPAGE
Lloh28:
	ldr	x9, [x9, _DP83867_RGMII_RX_CLK_DELAY_EN@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w10, w9, w8
	bic	w11, w0, w10
	ldr	x12, [x19]
Lloh30:
	adrp	x13, _PHY_INTERFACE_MODE_RGMII_ID@GOTPAGE
Lloh31:
	ldr	x13, [x13, _PHY_INTERFACE_MODE_RGMII_ID@GOTPAGEOFF]
Lloh32:
	ldr	x13, [x13]
	orr	w10, w10, w0
	cmp	x12, x13
	csel	w10, w10, w11, eq
Lloh33:
	adrp	x11, _PHY_INTERFACE_MODE_RGMII_TXID@GOTPAGE
Lloh34:
	ldr	x11, [x11, _PHY_INTERFACE_MODE_RGMII_TXID@GOTPAGEOFF]
Lloh35:
	ldr	x11, [x11]
	cmp	x12, x11
	csel	w8, w8, wzr, eq
	orr	w8, w8, w10
Lloh36:
	adrp	x10, _PHY_INTERFACE_MODE_RGMII_RXID@GOTPAGE
Lloh37:
	ldr	x10, [x10, _PHY_INTERFACE_MODE_RGMII_RXID@GOTPAGEOFF]
Lloh38:
	ldr	x10, [x10]
	cmp	x12, x10
	csel	w9, w9, wzr, eq
	orr	w3, w8, w9
	ldr	w1, [x22]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_phy_write_mmd
	ldp	w8, w9, [x23, #4]
Lloh39:
	adrp	x10, _DP83867_RGMII_TX_CLK_DELAY_SHIFT@GOTPAGE
Lloh40:
	ldr	x10, [x10, _DP83867_RGMII_TX_CLK_DELAY_SHIFT@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w3, w9, w8
	ldr	w1, [x22]
Lloh42:
	adrp	x8, _DP83867_RGMIIDCTL@GOTPAGE
Lloh43:
	ldr	x8, [x8, _DP83867_RGMIIDCTL@GOTPAGEOFF]
Lloh44:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write_mmd
LBB0_8:
	ldr	x4, [x23, #16]
	tbnz	x4, #63, LBB0_10
; %bb.9:
	ldr	w1, [x22]
Lloh45:
	adrp	x8, _DP83867_IO_MUX_CFG@GOTPAGE
Lloh46:
	ldr	x8, [x8, _DP83867_IO_MUX_CFG@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
Lloh48:
	adrp	x8, _DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK@GOTPAGE
Lloh49:
	ldr	x8, [x8, _DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK@GOTPAGEOFF]
Lloh50:
	ldr	w3, [x8]
	mov	x0, x19
                                        ; kill: def $w4 killed $w4 killed $x4
	bl	_phy_modify_mmd
LBB0_10:
	ldr	x8, [x19]
Lloh51:
	adrp	x9, _PHY_INTERFACE_MODE_SGMII@GOTPAGE
Lloh52:
	ldr	x9, [x9, _PHY_INTERFACE_MODE_SGMII@GOTPAGEOFF]
Lloh53:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_14
; %bb.11:
	ldr	w1, [x22]
Lloh54:
	adrp	x8, _DP83867_10M_SGMII_CFG@GOTPAGE
Lloh55:
	ldr	x8, [x8, _DP83867_10M_SGMII_CFG@GOTPAGEOFF]
Lloh56:
	ldr	w2, [x8]
Lloh57:
	adrp	x8, _DP83867_10M_SGMII_RATE_ADAPT_MASK@GOTPAGE
Lloh58:
	ldr	x8, [x8, _DP83867_10M_SGMII_RATE_ADAPT_MASK@GOTPAGEOFF]
Lloh59:
	ldr	w3, [x8]
	mov	x0, x19
	mov	w4, #0
	bl	_phy_modify_mmd
	cbnz	w0, LBB0_1
; %bb.12:
	ldr	w1, [x22]
Lloh60:
	adrp	x8, _DP83867_CFG4@GOTPAGE
Lloh61:
	ldr	x8, [x8, _DP83867_CFG4@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
Lloh63:
	adrp	x8, _DP83867_CFG4_SGMII_ANEG_MASK@GOTPAGE
Lloh64:
	ldr	x8, [x8, _DP83867_CFG4_SGMII_ANEG_MASK@GOTPAGEOFF]
Lloh65:
	ldr	w3, [x8]
Lloh66:
	adrp	x8, _DP83867_CFG4_SGMII_ANEG_TIMER_16MS@GOTPAGE
Lloh67:
	ldr	x8, [x8, _DP83867_CFG4_SGMII_ANEG_TIMER_16MS@GOTPAGEOFF]
Lloh68:
	ldr	w4, [x8]
	mov	x0, x19
	bl	_phy_modify_mmd
	cbnz	w0, LBB0_1
; %bb.13:
	ldr	w1, [x22]
Lloh69:
	adrp	x20, _DP83867_SGMIICTL@GOTPAGE
Lloh70:
	ldr	x20, [x20, _DP83867_SGMIICTL@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_phy_read_mmd
	ldr	x8, [x23, #48]
Lloh71:
	adrp	x9, _DP83867_SGMII_TYPE@GOTPAGE
Lloh72:
	ldr	x9, [x9, _DP83867_SGMII_TYPE@GOTPAGEOFF]
Lloh73:
	ldr	w9, [x9]
	orr	w10, w9, w0
	bic	w9, w0, w9
	cmp	x8, #0
	csel	w3, w9, w10, eq
	ldr	w1, [x22]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_phy_write_mmd
LBB0_14:
	mov	x0, x19
	bl	_phy_interrupt_is_valid
	cbz	x0, LBB0_16
; %bb.15:
Lloh74:
	adrp	x21, _DP83867_CFG3@GOTPAGE
Lloh75:
	ldr	x21, [x21, _DP83867_CFG3@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_phy_read
	mov	x20, x0
	mov	w0, #7
	bl	_BIT
	orr	w2, w0, w20
	ldr	w1, [x21]
	mov	x0, x19
	bl	_phy_write
LBB0_16:
	ldr	x8, [x23, #24]
Lloh76:
	adrp	x9, _DP83867_PORT_MIRROING_KEEP@GOTPAGE
Lloh77:
	ldr	x9, [x9, _DP83867_PORT_MIRROING_KEEP@GOTPAGEOFF]
Lloh78:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_18
; %bb.17:
	mov	x0, x19
	bl	_dp83867_config_port_mirroring
LBB0_18:
	ldr	x8, [x23, #40]
	cbz	x8, LBB0_20
; %bb.19:
Lloh79:
	adrp	x8, _DP83867_IO_MUX_CFG_CLK_O_DISABLE@GOTPAGE
Lloh80:
	ldr	x8, [x8, _DP83867_IO_MUX_CFG_CLK_O_DISABLE@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
	ldr	w9, [x23, #32]
Lloh82:
	adrp	x10, _DP83867_CLK_O_SEL_OFF@GOTPAGE
Lloh83:
	ldr	x10, [x10, _DP83867_CLK_O_SEL_OFF@GOTPAGEOFF]
Lloh84:
	ldr	w10, [x10]
Lloh85:
	adrp	x11, _DP83867_IO_MUX_CFG_CLK_O_SEL_MASK@GOTPAGE
Lloh86:
	ldr	x11, [x11, _DP83867_IO_MUX_CFG_CLK_O_SEL_MASK@GOTPAGEOFF]
Lloh87:
	ldr	w11, [x11]
Lloh88:
	adrp	x12, _DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT@GOTPAGE
Lloh89:
	ldr	x12, [x12, _DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT@GOTPAGEOFF]
Lloh90:
	ldr	w12, [x12]
	lsl	w12, w9, w12
	cmp	w9, w10
	csel	w4, w8, w12, eq
	csel	w9, wzr, w11, eq
	orr	w3, w9, w8
	ldr	w1, [x22]
Lloh91:
	adrp	x8, _DP83867_IO_MUX_CFG@GOTPAGE
Lloh92:
	ldr	x8, [x8, _DP83867_IO_MUX_CFG@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_modify_mmd
LBB0_20:
	mov	w0, #0
	b	LBB0_1
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGot	Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.cfi_endproc
                                        ; -- End function
	.comm	_DP83867_DEVADDR,4,2            ; @DP83867_DEVADDR
	.comm	_DP83867_CFG4,4,2               ; @DP83867_CFG4
	.comm	_MII_DP83867_PHYCTRL,4,2        ; @MII_DP83867_PHYCTRL
	.comm	_DP83867_PHYCR_FIFO_DEPTH_MASK,4,2 ; @DP83867_PHYCR_FIFO_DEPTH_MASK
	.comm	_DP83867_PHYCR_FIFO_DEPTH_SHIFT,4,2 ; @DP83867_PHYCR_FIFO_DEPTH_SHIFT
	.comm	_DP83867_STRAP_STS1,4,2         ; @DP83867_STRAP_STS1
	.comm	_DP83867_STRAP_STS1_RESERVED,4,2 ; @DP83867_STRAP_STS1_RESERVED
	.comm	_DP83867_PHYCR_RESERVED_MASK,4,2 ; @DP83867_PHYCR_RESERVED_MASK
	.comm	_DP83867_RGMIICTL,4,2           ; @DP83867_RGMIICTL
	.comm	_DP83867_RGMII_TX_CLK_DELAY_EN,4,2 ; @DP83867_RGMII_TX_CLK_DELAY_EN
	.comm	_DP83867_RGMII_RX_CLK_DELAY_EN,4,2 ; @DP83867_RGMII_RX_CLK_DELAY_EN
	.comm	_PHY_INTERFACE_MODE_RGMII_ID,8,3 ; @PHY_INTERFACE_MODE_RGMII_ID
	.comm	_PHY_INTERFACE_MODE_RGMII_TXID,8,3 ; @PHY_INTERFACE_MODE_RGMII_TXID
	.comm	_PHY_INTERFACE_MODE_RGMII_RXID,8,3 ; @PHY_INTERFACE_MODE_RGMII_RXID
	.comm	_DP83867_RGMII_TX_CLK_DELAY_SHIFT,4,2 ; @DP83867_RGMII_TX_CLK_DELAY_SHIFT
	.comm	_DP83867_RGMIIDCTL,4,2          ; @DP83867_RGMIIDCTL
	.comm	_DP83867_IO_MUX_CFG,4,2         ; @DP83867_IO_MUX_CFG
	.comm	_DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,4,2 ; @DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK
	.comm	_PHY_INTERFACE_MODE_SGMII,8,3   ; @PHY_INTERFACE_MODE_SGMII
	.comm	_DP83867_10M_SGMII_CFG,4,2      ; @DP83867_10M_SGMII_CFG
	.comm	_DP83867_10M_SGMII_RATE_ADAPT_MASK,4,2 ; @DP83867_10M_SGMII_RATE_ADAPT_MASK
	.comm	_DP83867_CFG4_SGMII_ANEG_MASK,4,2 ; @DP83867_CFG4_SGMII_ANEG_MASK
	.comm	_DP83867_CFG4_SGMII_ANEG_TIMER_16MS,4,2 ; @DP83867_CFG4_SGMII_ANEG_TIMER_16MS
	.comm	_DP83867_SGMIICTL,4,2           ; @DP83867_SGMIICTL
	.comm	_DP83867_SGMII_TYPE,4,2         ; @DP83867_SGMII_TYPE
	.comm	_DP83867_CFG3,4,2               ; @DP83867_CFG3
	.comm	_DP83867_PORT_MIRROING_KEEP,8,3 ; @DP83867_PORT_MIRROING_KEEP
	.comm	_DP83867_IO_MUX_CFG_CLK_O_DISABLE,4,2 ; @DP83867_IO_MUX_CFG_CLK_O_DISABLE
	.comm	_DP83867_CLK_O_SEL_OFF,4,2      ; @DP83867_CLK_O_SEL_OFF
	.comm	_DP83867_IO_MUX_CFG_CLK_O_SEL_MASK,4,2 ; @DP83867_IO_MUX_CFG_CLK_O_SEL_MASK
	.comm	_DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT,4,2 ; @DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT
	.no_dead_strip	_dp83867_config_init
.subsections_via_symbols
