	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mlx4_QUERY_DEV_CAP             ## -- Begin function mlx4_QUERY_DEV_CAP
	.p2align	4, 0x90
_mlx4_QUERY_DEV_CAP:                    ## @mlx4_QUERY_DEV_CAP
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r12
	movl	$0, 256(%rsi)
	callq	_mlx4_alloc_cmd_mailbox
	movq	%rax, %r15
	movq	%rax, %rdi
	callq	_IS_ERR
	testq	%rax, %rax
	je	LBB0_1
## %bb.20:
	movq	%r15, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_PTR_ERR                        ## TAILCALL
LBB0_1:
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	(%r15), %r13
	movl	8(%r15), %edx
	movq	_MLX4_CMD_QUERY_DEV_CAP@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	movq	_MLX4_CMD_TIME_CLASS_A@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_MLX4_CMD_NATIVE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	%r12, %rdi
	xorl	%esi, %esi
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	pushq	%rbx
	pushq	%rax
	callq	_mlx4_cmd_box
	addq	$16, %rsp
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_19
## %bb.2:
	movq	%r12, -48(%rbp)                 ## 8-byte Spill
	movq	%r12, %rdi
	callq	_mlx4_is_mfunc
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	%r13, %rdi
	callq	_disable_unsupported_roce_caps
LBB0_4:
	movq	%r13, %rsi
	movl	$18, %edx
	callq	_MLX4_GET
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movl	$1, (%rbx)
	movq	%r13, %rsi
	movl	$19, %edx
	callq	_MLX4_GET
	movl	$1, 4(%rbx)
	movq	%r13, %rsi
	movl	$20, %edx
	callq	_MLX4_GET
	movl	$1, 8(%rbx)
	movq	%r13, %rsi
	movl	$21, %edx
	callq	_MLX4_GET
	movl	$1, 12(%rbx)
	movq	%r13, %rsi
	movl	$25, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$26, %edx
	callq	_MLX4_GET
	movl	$1, 20(%rbx)
	movq	%r13, %rsi
	movl	$27, %edx
	callq	_MLX4_GET
	movl	$1, 24(%rbx)
	movq	%r13, %rsi
	movl	$29, %edx
	callq	_MLX4_GET
	movl	$1, 28(%rbx)
	movq	%r13, %rsi
	movl	$30, %edx
	callq	_MLX4_GET
	movl	$1, 32(%rbx)
	movq	%r13, %rsi
	movl	$31, %edx
	callq	_MLX4_GET
	movl	$1, 36(%rbx)
	movq	%r13, %rsi
	movl	$32, %edx
	callq	_MLX4_GET
	movl	$1, 40(%rbx)
	movq	%r13, %rsi
	movl	$34, %edx
	callq	_MLX4_GET
	movl	$1, 44(%rbx)
	movq	%r13, %rsi
	movl	$38, %edx
	callq	_MLX4_GET
	movl	$0, 48(%rbx)
	movq	%r13, %rsi
	movl	$41, %edx
	callq	_MLX4_GET
	movl	$1, 52(%rbx)
	movq	%r13, %rsi
	movl	$43, %edx
	callq	_MLX4_GET
	movl	$1, 56(%rbx)
	movq	%r13, %rsi
	movl	$45, %edx
	callq	_MLX4_GET
	movl	$0, 60(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$46, %edx
	callq	_MLX4_GET
	movl	$0, 64(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$47, %edx
	callq	_MLX4_GET
	movl	$1, 68(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$53, %edx
	callq	_MLX4_GET
	movl	$0, 72(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$55, %edx
	callq	_MLX4_GET
	movl	$0, 76(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$56, %edx
	callq	_MLX4_GET
	movl	$1, 80(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$112, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$118, %edx
	callq	_MLX4_GET
	movl	$0, 84(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$52, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$116, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$119, %edx
	callq	_MLX4_GET
	movl	$0, 88(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$120, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$123, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$60, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$62, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$64, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$68, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$67, %edx
	callq	_MLX4_GET
	movq	104(%rbx), %rax
	movq	$0, 4(%rax)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$72, %edx
	callq	_MLX4_GET
	movl	$0, 112(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$73, %edx
	callq	_MLX4_GET
	movl	$1048576, 116(%rbx)             ## imm = 0x100000
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$75, %edx
	callq	_MLX4_GET
	movl	$1, 120(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$76, %edx
	callq	_MLX4_GET
	movl	$0, 124(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$81, %edx
	callq	_MLX4_GET
	movl	$0, 132(%rbx)
	movq	%r13, %rsi
	movl	$82, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$92, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$93, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$97, %edx
	callq	_MLX4_GET
	movl	$1, 140(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$98, %edx
	callq	_MLX4_GET
	movl	$0, 144(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$99, %edx
	callq	_MLX4_GET
	movl	$1, 148(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$100, %edx
	callq	_MLX4_GET
	movl	$0, 152(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$101, %edx
	callq	_MLX4_GET
	movl	$1, 156(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$102, %edx
	callq	_MLX4_GET
	movl	$0, 160(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$103, %edx
	callq	_MLX4_GET
	movl	$1, 164(%rbx)
	movq	%r13, %rsi
	movl	$128, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$130, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$132, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$134, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$136, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$138, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$140, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$142, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$144, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$146, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$16, %edx
	callq	_MLX4_GET
	movl	$1, 208(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$17, %edx
	callq	_MLX4_GET
	movl	$1, 212(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$51, %edx
	callq	_MLX4_GET
	movl	$0, 216(%rbx)
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$85, %edx
	callq	_MLX4_GET
	movl	$0, 220(%rbx)
	movq	%r13, %rsi
	movl	$86, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$122, %edx
	callq	_MLX4_GET
	movl	228(%rbx), %edi
	movq	%r13, %rsi
	movl	$148, %edx
	callq	_MLX4_GET
	movl	228(%rbx), %eax
	movq	_MLX4_FLAG_ROCE_V1_V2@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_6
## %bb.5:
	movq	_MLX4_DEV_CAP_FLAG2_ROCE_V1_V2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	%ecx, 256(%rbx)
LBB0_6:
	movq	_MLX4_FLAG_PORT_REMAP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.7:
	movq	_MLX4_DEV_CAP_FLAG2_PORT_REMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 256(%rbx)
LBB0_8:
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$148, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$150, %edx
	callq	_MLX4_GET
	movl	232(%rbx), %edi
	movq	%r13, %rsi
	movl	$152, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$156, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$156, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$157, %edx
	callq	_MLX4_GET
	xorl	%edi, %edi
	movq	%r13, %rsi
	movl	$158, %edx
	callq	_MLX4_GET
	movl	236(%rbx), %edi
	movq	%r13, %rsi
	movl	$160, %edx
	callq	_MLX4_GET
	movq	_MLX4_DEV_CAP_FLAG_COUNTERS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 96(%rbx)
	je	LBB0_10
## %bb.9:
	movl	240(%rbx), %edi
	movq	%r13, %rsi
	movl	$104, %edx
	callq	_MLX4_GET
LBB0_10:
	movq	%r13, %rsi
	movl	$176, %edx
	callq	_MLX4_GET
	movl	244(%rbx), %edi
	movq	%r13, %rsi
	movl	$168, %edx
	callq	_MLX4_GET
	movq	_MGM_QPN_MASK@GOTPCREL(%rip), %r14
	movl	(%r14), %eax
	andl	%eax, 244(%rbx)
	movl	248(%rbx), %edi
	movq	%r13, %rsi
	movl	$172, %edx
	callq	_MLX4_GET
	movl	(%r14), %eax
	andl	%eax, 248(%rbx)
	movq	%r13, %rsi
	movl	$204, %edx
	callq	_MLX4_GET
	movl	252(%rbx), %edi
	movq	%r13, %rsi
	movl	$228, %edx
	callq	_MLX4_GET
	movq	%r13, %rsi
	movl	$112, %edx
	callq	_MLX4_GET
	cmpl	$0, 76(%rbx)
	movq	-48(%rbp), %r12                 ## 8-byte Reload
	movq	%rbx, %r13
	jle	LBB0_15
## %bb.11:
	movl	$1, %ebx
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movq	264(%r13), %rdx
	addq	%rbx, %rdx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_mlx4_QUERY_PORT
	testl	%eax, %eax
	jne	LBB0_14
## %bb.12:                              ##   in Loop: Header=BB0_13 Depth=1
	leaq	1(%rbx), %rax
	movslq	76(%r13), %rcx
	cmpq	%rcx, %rbx
	movq	%rax, %rbx
	jl	LBB0_13
LBB0_15:
	cmpl	$0, 48(%r13)
	je	LBB0_16
## %bb.17:
	movq	_MLX4_DEV_CAP_FLAG2_SYS_EQS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 256(%r13)
	jmp	LBB0_18
LBB0_14:
	movl	%eax, %r14d
	jmp	LBB0_19
LBB0_16:
	movl	32(%r13), %esi
	movl	112(%r13), %edi
	shll	$2, %edi
	callq	_max
	movl	%eax, 32(%r13)
LBB0_18:
	xorl	%r14d, %r14d
	movq	-48(%rbp), %r12                 ## 8-byte Reload
LBB0_19:
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_mlx4_free_cmd_mailbox
	movl	%r14d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX4_CMD_QUERY_DEV_CAP,4,2     ## @MLX4_CMD_QUERY_DEV_CAP
	.comm	_MLX4_CMD_TIME_CLASS_A,4,2      ## @MLX4_CMD_TIME_CLASS_A
	.comm	_MLX4_CMD_NATIVE,4,2            ## @MLX4_CMD_NATIVE
	.comm	_MLX4_DEV_CAP_FLAG2_RSS_XOR,4,2 ## @MLX4_DEV_CAP_FLAG2_RSS_XOR
	.comm	_MLX4_DEV_CAP_FLAG2_RSS_TOP,4,2 ## @MLX4_DEV_CAP_FLAG2_RSS_TOP
	.comm	_MLX4_DEV_CAP_FLAG2_RSS,4,2     ## @MLX4_DEV_CAP_FLAG2_RSS
	.comm	_MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN,4,2 ## @MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN
	.comm	_MLX4_DEV_CAP_FLAG2_FS_EN,4,2   ## @MLX4_DEV_CAP_FLAG2_FS_EN
	.comm	_MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER,4,2 ## @MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER
	.comm	_MLX4_DEV_CAP_FLAG2_PORT_BEACON,4,2 ## @MLX4_DEV_CAP_FLAG2_PORT_BEACON
	.comm	_MLX4_DEV_CAP_FLAG2_DMFS_IPOIB,4,2 ## @MLX4_DEV_CAP_FLAG2_DMFS_IPOIB
	.comm	_MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT,4,2 ## @MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT
	.comm	_MLX4_DEV_CAP_FLAG2_QCN,4,2     ## @MLX4_DEV_CAP_FLAG2_QCN
	.comm	_MLX4_DEV_CAP_FLAG2_TS,4,2      ## @MLX4_DEV_CAP_FLAG2_TS
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_MLX4_DEV_CAP_FLAG2_USER_MAC_EN,4,2 ## @MLX4_DEV_CAP_FLAG2_USER_MAC_EN
	.comm	_MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP,4,2 ## @MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP
	.comm	_MLX4_DEV_CAP_FLAG2_QOS_VPP,4,2 ## @MLX4_DEV_CAP_FLAG2_QOS_VPP
	.comm	_MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL,4,2 ## @MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL
	.comm	_MLX4_DEV_CAP_FLAG2_CQE_STRIDE,4,2 ## @MLX4_DEV_CAP_FLAG2_CQE_STRIDE
	.comm	_MLX4_DEV_CAP_FLAG2_EQE_STRIDE,4,2 ## @MLX4_DEV_CAP_FLAG2_EQE_STRIDE
	.comm	_MLX4_FLAG_ROCE_V1_V2,4,2       ## @MLX4_FLAG_ROCE_V1_V2
	.comm	_MLX4_DEV_CAP_FLAG2_ROCE_V1_V2,4,2 ## @MLX4_DEV_CAP_FLAG2_ROCE_V1_V2
	.comm	_MLX4_FLAG_PORT_REMAP,4,2       ## @MLX4_FLAG_PORT_REMAP
	.comm	_MLX4_DEV_CAP_FLAG2_PORT_REMAP,4,2 ## @MLX4_DEV_CAP_FLAG2_PORT_REMAP
	.comm	_MLX4_DEV_CAP_FLAG2_CONFIG_DEV,4,2 ## @MLX4_DEV_CAP_FLAG2_CONFIG_DEV
	.comm	_MLX4_DEV_CAP_FLAG2_IGNORE_FCS,4,2 ## @MLX4_DEV_CAP_FLAG2_IGNORE_FCS
	.comm	_MLX4_DEV_CAP_FLAG2_PHV_EN,4,2  ## @MLX4_DEV_CAP_FLAG2_PHV_EN
	.comm	_MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN,4,2 ## @MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN
	.comm	_MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP,4,2 ## @MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP
	.comm	_MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT,4,2 ## @MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT
	.comm	_MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW,4,2 ## @MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW
	.comm	_MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT,4,2 ## @MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT
	.comm	_MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN,4,2 ## @MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
	.comm	_MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS,4,2 ## @MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
	.comm	_MLX4_DEV_CAP_FLAG2_ETS_CFG,4,2 ## @MLX4_DEV_CAP_FLAG2_ETS_CFG
	.comm	_MLX4_DEV_CAP_FLAG_COUNTERS,4,2 ## @MLX4_DEV_CAP_FLAG_COUNTERS
	.comm	_MLX4_DEV_CAP_FLAG2_MAD_DEMUX,4,2 ## @MLX4_DEV_CAP_FLAG2_MAD_DEMUX
	.comm	_MGM_QPN_MASK,4,2               ## @MGM_QPN_MASK
	.comm	_MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT,4,2 ## @MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT
	.comm	_MLX4_DEV_CAP_FLAG2_UPDATE_QP,4,2 ## @MLX4_DEV_CAP_FLAG2_UPDATE_QP
	.comm	_MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB,4,2 ## @MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB
	.comm	_MLX4_DEV_CAP_FLAG2_LB_SRC_CHK,4,2 ## @MLX4_DEV_CAP_FLAG2_LB_SRC_CHK
	.comm	_MLX4_DEV_CAP_FLAG2_VLAN_CONTROL,4,2 ## @MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
	.comm	_MLX4_DEV_CAP_FLAG2_FSM,4,2     ## @MLX4_DEV_CAP_FLAG2_FSM
	.comm	_MLX4_DEV_CAP_FLAG2_80_VFS,4,2  ## @MLX4_DEV_CAP_FLAG2_80_VFS
	.comm	_MLX4_DEV_CAP_FLAG2_SW_CQ_INIT,4,2 ## @MLX4_DEV_CAP_FLAG2_SW_CQ_INIT
	.comm	_MLX4_DEV_CAP_FLAG2_SYS_EQS,4,2 ## @MLX4_DEV_CAP_FLAG2_SYS_EQS
	.comm	_QUERY_DEV_CAP_ACK_DELAY_OFFSET,4,2 ## @QUERY_DEV_CAP_ACK_DELAY_OFFSET
	.comm	_QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_BF_OFFSET,4,2    ## @QUERY_DEV_CAP_BF_OFFSET
	.comm	_QUERY_DEV_CAP_BMME_FLAGS_OFFSET,4,2 ## @QUERY_DEV_CAP_BMME_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_CONFIG_DEV_OFFSET,4,2 ## @QUERY_DEV_CAP_CONFIG_DEV_OFFSET
	.comm	_QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE,4,2 ## @QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE
	.comm	_QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET,4,2 ## @QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
	.comm	_QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_DIAG_RPRT_PER_PORT,4,2 ## @QUERY_DEV_CAP_DIAG_RPRT_PER_PORT
	.comm	_QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET,4,2 ## @QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET
	.comm	_QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET,4,2 ## @QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET
	.comm	_QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_ECN_QCN_VER_OFFSET,4,2 ## @QUERY_DEV_CAP_ECN_QCN_VER_OFFSET
	.comm	_QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_ETH_BACKPL_OFFSET,4,2 ## @QUERY_DEV_CAP_ETH_BACKPL_OFFSET
	.comm	_QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET,4,2 ## @QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_EXT_FLAGS_OFFSET,4,2 ## @QUERY_DEV_CAP_EXT_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_FLAGS_OFFSET,4,2 ## @QUERY_DEV_CAP_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET,4,2 ## @QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET
	.comm	_QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET,4,2 ## @QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET
	.comm	_QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET,4,2 ## @QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
	.comm	_QUERY_DEV_CAP_FW_REASSIGN_MAC,4,2 ## @QUERY_DEV_CAP_FW_REASSIGN_MAC
	.comm	_QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET,4,2 ## @QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET
	.comm	_QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET,4,2 ## @QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET
	.comm	_QUERY_DEV_CAP_MAD_DEMUX_OFFSET,4,2 ## @QUERY_DEV_CAP_MAD_DEMUX_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_COUNTERS_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_COUNTERS_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_CQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_CQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_EQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_EQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_GSO_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_GSO_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_MCG_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_MCG_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_MPT_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_MPT_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_PD_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_PD_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_QP_MCG_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_QP_MCG_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_QP_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_QP_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_QP_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_QP_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_RDMA_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_RDMA_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_REQ_QP_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_REQ_QP_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_RES_QP_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_RES_QP_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SG_RQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_SG_RQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SG_SQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_SG_SQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SRQ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_SRQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_XRC_OFFSET,4,2 ## @QUERY_DEV_CAP_MAX_XRC_OFFSET
	.comm	_QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET,4,2 ## @QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET
	.comm	_QUERY_DEV_CAP_PAGE_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_PAGE_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_PHV_EN_OFFSET,4,2 ## @QUERY_DEV_CAP_PHV_EN_OFFSET
	.comm	_QUERY_DEV_CAP_PORT_BEACON_OFFSET,4,2 ## @QUERY_DEV_CAP_PORT_BEACON_OFFSET
	.comm	_QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET,4,2 ## @QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET
	.comm	_QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET,4,2 ## @QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET
	.comm	_QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET,4,2 ## @QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET
	.comm	_QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET,4,2 ## @QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET
	.comm	_QUERY_DEV_CAP_RATE_SUPPORT_OFFSET,4,2 ## @QUERY_DEV_CAP_RATE_SUPPORT_OFFSET
	.comm	_QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_RSS_OFFSET,4,2   ## @QUERY_DEV_CAP_RSS_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_CQ_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_CQ_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_EQ_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_EQ_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_LKEY_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_LKEY_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_MCG_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_MCG_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_MRW_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_MRW_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_MTT_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_MTT_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_PD_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_PD_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_QP_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_QP_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_SRQ_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_SRQ_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_UAR_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_UAR_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_XRC_OFFSET,4,2 ## @QUERY_DEV_CAP_RSVD_XRC_OFFSET
	.comm	_QUERY_DEV_CAP_RSZ_SRQ_OFFSET,4,2 ## @QUERY_DEV_CAP_RSZ_SRQ_OFFSET
	.comm	_QUERY_DEV_CAP_SL2VL_EVENT_OFFSET,4,2 ## @QUERY_DEV_CAP_SL2VL_EVENT_OFFSET
	.comm	_QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET,4,2 ## @QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET
	.comm	_QUERY_DEV_CAP_UAR_SZ_OFFSET,4,2 ## @QUERY_DEV_CAP_UAR_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_USER_MAC_EN_OFFSET,4,2 ## @QUERY_DEV_CAP_USER_MAC_EN_OFFSET
	.comm	_QUERY_DEV_CAP_VL_PORT_OFFSET,4,2 ## @QUERY_DEV_CAP_VL_PORT_OFFSET
	.comm	_QUERY_DEV_CAP_VXLAN,4,2        ## @QUERY_DEV_CAP_VXLAN
	.comm	_QUERY_DEV_CAP_WOL_OFFSET,4,2   ## @QUERY_DEV_CAP_WOL_OFFSET
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_mlx4_QUERY_DEV_CAP             ; -- Begin function mlx4_QUERY_DEV_CAP
	.p2align	2
_mlx4_QUERY_DEV_CAP:                    ; @mlx4_QUERY_DEV_CAP
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x1
	mov	x19, x0
	str	wzr, [x1, #256]
	bl	_mlx4_alloc_cmd_mailbox
	mov	x20, x0
	bl	_IS_ERR
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_PTR_ERR
LBB0_2:
	ldr	x22, [x20]
	ldr	w2, [x20, #8]
Lloh0:
	adrp	x8, _MLX4_CMD_QUERY_DEV_CAP@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLX4_CMD_QUERY_DEV_CAP@GOTPAGEOFF]
Lloh2:
	ldr	w5, [x8]
Lloh3:
	adrp	x8, _MLX4_CMD_TIME_CLASS_A@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MLX4_CMD_TIME_CLASS_A@GOTPAGEOFF]
Lloh5:
	ldr	w6, [x8]
Lloh6:
	adrp	x8, _MLX4_CMD_NATIVE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MLX4_CMD_NATIVE@GOTPAGEOFF]
Lloh8:
	ldr	w7, [x8]
	mov	x0, x19
	mov	w1, #0
	mov	w3, #0
	mov	w4, #0
	bl	_mlx4_cmd_box
	mov	x23, x0
	cbnz	w0, LBB0_19
; %bb.3:
	mov	x0, x19
	bl	_mlx4_is_mfunc
	cbz	x0, LBB0_5
; %bb.4:
	mov	x0, x22
	bl	_disable_unsupported_roce_caps
LBB0_5:
	mov	x1, x22
	mov	w2, #18
	bl	_MLX4_GET
	mov	w23, #1
	str	w23, [x21]
	mov	x1, x22
	mov	w2, #19
	bl	_MLX4_GET
	str	w23, [x21, #4]
	mov	x1, x22
	mov	w2, #20
	bl	_MLX4_GET
	str	w23, [x21, #8]
	mov	x1, x22
	mov	w2, #21
	bl	_MLX4_GET
	str	w23, [x21, #12]
	mov	x1, x22
	mov	w2, #25
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #26
	bl	_MLX4_GET
	str	w23, [x21, #20]
	mov	x1, x22
	mov	w2, #27
	bl	_MLX4_GET
	str	w23, [x21, #24]
	mov	x1, x22
	mov	w2, #29
	bl	_MLX4_GET
	str	w23, [x21, #28]
	mov	x1, x22
	mov	w2, #30
	bl	_MLX4_GET
	str	w23, [x21, #32]
	mov	x1, x22
	mov	w2, #31
	bl	_MLX4_GET
	str	w23, [x21, #36]
	mov	x1, x22
	mov	w2, #32
	bl	_MLX4_GET
	str	w23, [x21, #40]
	mov	x1, x22
	mov	w2, #34
	bl	_MLX4_GET
	str	w23, [x21, #44]
	mov	x1, x22
	mov	w2, #38
	bl	_MLX4_GET
	str	wzr, [x21, #48]
	mov	x1, x22
	mov	w2, #41
	bl	_MLX4_GET
	str	w23, [x21, #52]
	mov	x1, x22
	mov	w2, #43
	bl	_MLX4_GET
	str	w23, [x21, #56]
	mov	x1, x22
	mov	w2, #45
	bl	_MLX4_GET
	str	wzr, [x21, #60]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #46
	bl	_MLX4_GET
	str	wzr, [x21, #64]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #47
	bl	_MLX4_GET
	str	w23, [x21, #68]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #53
	bl	_MLX4_GET
	str	wzr, [x21, #72]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #55
	bl	_MLX4_GET
	str	wzr, [x21, #76]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #56
	bl	_MLX4_GET
	str	w23, [x21, #80]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #112
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #118
	bl	_MLX4_GET
	str	wzr, [x21, #84]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #52
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #116
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #119
	bl	_MLX4_GET
	str	wzr, [x21, #88]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #120
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #123
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #60
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #62
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #64
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #68
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #67
	bl	_MLX4_GET
	ldr	x8, [x21, #104]
	stp	wzr, wzr, [x8, #4]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #72
	bl	_MLX4_GET
	str	wzr, [x21, #112]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #73
	bl	_MLX4_GET
	mov	w8, #1048576
	str	w8, [x21, #116]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #75
	bl	_MLX4_GET
	str	w23, [x21, #120]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #76
	bl	_MLX4_GET
	str	wzr, [x21, #124]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #81
	bl	_MLX4_GET
	str	wzr, [x21, #132]
	mov	x1, x22
	mov	w2, #82
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #92
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #93
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #97
	bl	_MLX4_GET
	str	w23, [x21, #140]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #98
	bl	_MLX4_GET
	str	wzr, [x21, #144]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #99
	bl	_MLX4_GET
	str	w23, [x21, #148]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #100
	bl	_MLX4_GET
	str	wzr, [x21, #152]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #101
	bl	_MLX4_GET
	str	w23, [x21, #156]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #102
	bl	_MLX4_GET
	str	wzr, [x21, #160]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #103
	bl	_MLX4_GET
	str	w23, [x21, #164]
	mov	x1, x22
	mov	w2, #128
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #130
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #132
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #134
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #136
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #138
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #140
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #142
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #144
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #146
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #16
	bl	_MLX4_GET
	str	w23, [x21, #208]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #17
	bl	_MLX4_GET
	str	w23, [x21, #212]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #51
	bl	_MLX4_GET
	str	wzr, [x21, #216]
	mov	w0, #0
	mov	x1, x22
	mov	w2, #85
	bl	_MLX4_GET
	str	wzr, [x21, #220]
	mov	x1, x22
	mov	w2, #86
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #122
	bl	_MLX4_GET
	ldr	w0, [x21, #228]
	mov	x1, x22
	mov	w2, #148
	bl	_MLX4_GET
	ldr	w8, [x21, #228]
Lloh9:
	adrp	x9, _MLX4_FLAG_ROCE_V1_V2@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MLX4_FLAG_ROCE_V1_V2@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_7
; %bb.6:
Lloh12:
	adrp	x9, _MLX4_DEV_CAP_FLAG2_ROCE_V1_V2@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MLX4_DEV_CAP_FLAG2_ROCE_V1_V2@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	ldr	w10, [x21, #256]
	orr	w9, w10, w9
	str	w9, [x21, #256]
LBB0_7:
Lloh15:
	adrp	x9, _MLX4_FLAG_PORT_REMAP@GOTPAGE
Lloh16:
	ldr	x9, [x9, _MLX4_FLAG_PORT_REMAP@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_9
; %bb.8:
Lloh18:
	adrp	x8, _MLX4_DEV_CAP_FLAG2_PORT_REMAP@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MLX4_DEV_CAP_FLAG2_PORT_REMAP@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	ldr	w9, [x21, #256]
	orr	w8, w9, w8
	str	w8, [x21, #256]
LBB0_9:
	mov	w0, #0
	mov	x1, x22
	mov	w2, #148
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #150
	bl	_MLX4_GET
	ldr	w0, [x21, #232]
	mov	x1, x22
	mov	w2, #152
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #156
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #156
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #157
	bl	_MLX4_GET
	mov	w0, #0
	mov	x1, x22
	mov	w2, #158
	bl	_MLX4_GET
	ldr	w0, [x21, #236]
	mov	x1, x22
	mov	w2, #160
	bl	_MLX4_GET
	ldr	w8, [x21, #96]
Lloh21:
	adrp	x9, _MLX4_DEV_CAP_FLAG_COUNTERS@GOTPAGE
Lloh22:
	ldr	x9, [x9, _MLX4_DEV_CAP_FLAG_COUNTERS@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_11
; %bb.10:
	ldr	w0, [x21, #240]
	mov	x1, x22
	mov	w2, #104
	bl	_MLX4_GET
LBB0_11:
	mov	x1, x22
	mov	w2, #176
	bl	_MLX4_GET
	ldr	w0, [x21, #244]
	mov	x1, x22
	mov	w2, #168
	bl	_MLX4_GET
Lloh24:
	adrp	x23, _MGM_QPN_MASK@GOTPAGE
Lloh25:
	ldr	x23, [x23, _MGM_QPN_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	ldp	w9, w0, [x21, #244]
	and	w8, w9, w8
	str	w8, [x21, #244]
	mov	x1, x22
	mov	w2, #172
	bl	_MLX4_GET
	ldr	w8, [x23]
	ldr	w9, [x21, #248]
	and	w8, w9, w8
	str	w8, [x21, #248]
	mov	x1, x22
	mov	w2, #204
	bl	_MLX4_GET
	ldr	w0, [x21, #252]
	mov	x1, x22
	mov	w2, #228
	bl	_MLX4_GET
	mov	x1, x22
	mov	w2, #112
	bl	_MLX4_GET
	ldr	w8, [x21, #76]
	cmp	w8, #1
	b.lt	LBB0_15
; %bb.12:
	mov	w22, #1
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21, #264]
	add	x2, x22, x8
	mov	x0, x19
	mov	x1, x22
	bl	_mlx4_QUERY_PORT
	cbnz	w0, LBB0_17
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	add	x8, x22, #1
	ldrsw	x9, [x21, #76]
	cmp	x22, x9
	mov	x22, x8
	b.lt	LBB0_13
LBB0_15:
	ldr	w8, [x21, #48]
	cbz	w8, LBB0_18
; %bb.16:
	mov	w23, #0
Lloh26:
	adrp	x8, _MLX4_DEV_CAP_FLAG2_SYS_EQS@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MLX4_DEV_CAP_FLAG2_SYS_EQS@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	ldr	w9, [x21, #256]
	orr	w8, w9, w8
	str	w8, [x21, #256]
	b	LBB0_19
LBB0_17:
	mov	x23, x0
	b	LBB0_19
LBB0_18:
	ldr	w8, [x21, #112]
	lsl	w0, w8, #2
	ldr	w1, [x21, #32]
	bl	_max
	mov	w23, #0
	str	w0, [x21, #32]
LBB0_19:
	mov	x0, x19
	mov	x1, x20
	bl	_mlx4_free_cmd_mailbox
	mov	x0, x23
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX4_CMD_QUERY_DEV_CAP,4,2     ; @MLX4_CMD_QUERY_DEV_CAP
	.comm	_MLX4_CMD_TIME_CLASS_A,4,2      ; @MLX4_CMD_TIME_CLASS_A
	.comm	_MLX4_CMD_NATIVE,4,2            ; @MLX4_CMD_NATIVE
	.comm	_MLX4_DEV_CAP_FLAG2_RSS_XOR,4,2 ; @MLX4_DEV_CAP_FLAG2_RSS_XOR
	.comm	_MLX4_DEV_CAP_FLAG2_RSS_TOP,4,2 ; @MLX4_DEV_CAP_FLAG2_RSS_TOP
	.comm	_MLX4_DEV_CAP_FLAG2_RSS,4,2     ; @MLX4_DEV_CAP_FLAG2_RSS
	.comm	_MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN,4,2 ; @MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN
	.comm	_MLX4_DEV_CAP_FLAG2_FS_EN,4,2   ; @MLX4_DEV_CAP_FLAG2_FS_EN
	.comm	_MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER,4,2 ; @MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER
	.comm	_MLX4_DEV_CAP_FLAG2_PORT_BEACON,4,2 ; @MLX4_DEV_CAP_FLAG2_PORT_BEACON
	.comm	_MLX4_DEV_CAP_FLAG2_DMFS_IPOIB,4,2 ; @MLX4_DEV_CAP_FLAG2_DMFS_IPOIB
	.comm	_MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT,4,2 ; @MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT
	.comm	_MLX4_DEV_CAP_FLAG2_QCN,4,2     ; @MLX4_DEV_CAP_FLAG2_QCN
	.comm	_MLX4_DEV_CAP_FLAG2_TS,4,2      ; @MLX4_DEV_CAP_FLAG2_TS
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_MLX4_DEV_CAP_FLAG2_USER_MAC_EN,4,2 ; @MLX4_DEV_CAP_FLAG2_USER_MAC_EN
	.comm	_MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP,4,2 ; @MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP
	.comm	_MLX4_DEV_CAP_FLAG2_QOS_VPP,4,2 ; @MLX4_DEV_CAP_FLAG2_QOS_VPP
	.comm	_MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL,4,2 ; @MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL
	.comm	_MLX4_DEV_CAP_FLAG2_CQE_STRIDE,4,2 ; @MLX4_DEV_CAP_FLAG2_CQE_STRIDE
	.comm	_MLX4_DEV_CAP_FLAG2_EQE_STRIDE,4,2 ; @MLX4_DEV_CAP_FLAG2_EQE_STRIDE
	.comm	_MLX4_FLAG_ROCE_V1_V2,4,2       ; @MLX4_FLAG_ROCE_V1_V2
	.comm	_MLX4_DEV_CAP_FLAG2_ROCE_V1_V2,4,2 ; @MLX4_DEV_CAP_FLAG2_ROCE_V1_V2
	.comm	_MLX4_FLAG_PORT_REMAP,4,2       ; @MLX4_FLAG_PORT_REMAP
	.comm	_MLX4_DEV_CAP_FLAG2_PORT_REMAP,4,2 ; @MLX4_DEV_CAP_FLAG2_PORT_REMAP
	.comm	_MLX4_DEV_CAP_FLAG2_CONFIG_DEV,4,2 ; @MLX4_DEV_CAP_FLAG2_CONFIG_DEV
	.comm	_MLX4_DEV_CAP_FLAG2_IGNORE_FCS,4,2 ; @MLX4_DEV_CAP_FLAG2_IGNORE_FCS
	.comm	_MLX4_DEV_CAP_FLAG2_PHV_EN,4,2  ; @MLX4_DEV_CAP_FLAG2_PHV_EN
	.comm	_MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN,4,2 ; @MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN
	.comm	_MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP,4,2 ; @MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP
	.comm	_MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT,4,2 ; @MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT
	.comm	_MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW,4,2 ; @MLX4_DEV_CAP_FLAG2_DRIVER_VERSION_TO_FW
	.comm	_MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT,4,2 ; @MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT
	.comm	_MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN,4,2 ; @MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN
	.comm	_MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS,4,2 ; @MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS
	.comm	_MLX4_DEV_CAP_FLAG2_ETS_CFG,4,2 ; @MLX4_DEV_CAP_FLAG2_ETS_CFG
	.comm	_MLX4_DEV_CAP_FLAG_COUNTERS,4,2 ; @MLX4_DEV_CAP_FLAG_COUNTERS
	.comm	_MLX4_DEV_CAP_FLAG2_MAD_DEMUX,4,2 ; @MLX4_DEV_CAP_FLAG2_MAD_DEMUX
	.comm	_MGM_QPN_MASK,4,2               ; @MGM_QPN_MASK
	.comm	_MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT,4,2 ; @MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT
	.comm	_MLX4_DEV_CAP_FLAG2_UPDATE_QP,4,2 ; @MLX4_DEV_CAP_FLAG2_UPDATE_QP
	.comm	_MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB,4,2 ; @MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB
	.comm	_MLX4_DEV_CAP_FLAG2_LB_SRC_CHK,4,2 ; @MLX4_DEV_CAP_FLAG2_LB_SRC_CHK
	.comm	_MLX4_DEV_CAP_FLAG2_VLAN_CONTROL,4,2 ; @MLX4_DEV_CAP_FLAG2_VLAN_CONTROL
	.comm	_MLX4_DEV_CAP_FLAG2_FSM,4,2     ; @MLX4_DEV_CAP_FLAG2_FSM
	.comm	_MLX4_DEV_CAP_FLAG2_80_VFS,4,2  ; @MLX4_DEV_CAP_FLAG2_80_VFS
	.comm	_MLX4_DEV_CAP_FLAG2_SW_CQ_INIT,4,2 ; @MLX4_DEV_CAP_FLAG2_SW_CQ_INIT
	.comm	_MLX4_DEV_CAP_FLAG2_SYS_EQS,4,2 ; @MLX4_DEV_CAP_FLAG2_SYS_EQS
	.comm	_QUERY_DEV_CAP_ACK_DELAY_OFFSET,4,2 ; @QUERY_DEV_CAP_ACK_DELAY_OFFSET
	.comm	_QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_BF_OFFSET,4,2    ; @QUERY_DEV_CAP_BF_OFFSET
	.comm	_QUERY_DEV_CAP_BMME_FLAGS_OFFSET,4,2 ; @QUERY_DEV_CAP_BMME_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_CONFIG_DEV_OFFSET,4,2 ; @QUERY_DEV_CAP_CONFIG_DEV_OFFSET
	.comm	_QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE,4,2 ; @QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE
	.comm	_QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET,4,2 ; @QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET
	.comm	_QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_DIAG_RPRT_PER_PORT,4,2 ; @QUERY_DEV_CAP_DIAG_RPRT_PER_PORT
	.comm	_QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET,4,2 ; @QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET
	.comm	_QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET,4,2 ; @QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET
	.comm	_QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_ECN_QCN_VER_OFFSET,4,2 ; @QUERY_DEV_CAP_ECN_QCN_VER_OFFSET
	.comm	_QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_ETH_BACKPL_OFFSET,4,2 ; @QUERY_DEV_CAP_ETH_BACKPL_OFFSET
	.comm	_QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET,4,2 ; @QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_EXT_FLAGS_OFFSET,4,2 ; @QUERY_DEV_CAP_EXT_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_FLAGS_OFFSET,4,2 ; @QUERY_DEV_CAP_FLAGS_OFFSET
	.comm	_QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET,4,2 ; @QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET
	.comm	_QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET,4,2 ; @QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET
	.comm	_QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET,4,2 ; @QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET
	.comm	_QUERY_DEV_CAP_FW_REASSIGN_MAC,4,2 ; @QUERY_DEV_CAP_FW_REASSIGN_MAC
	.comm	_QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET,4,2 ; @QUERY_DEV_CAP_HEALTH_BUFFER_ADDRESS_OFFSET
	.comm	_QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET,4,2 ; @QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET
	.comm	_QUERY_DEV_CAP_MAD_DEMUX_OFFSET,4,2 ; @QUERY_DEV_CAP_MAD_DEMUX_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_COUNTERS_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_COUNTERS_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_CQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_CQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_EQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_EQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_GSO_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_GSO_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_MCG_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_MCG_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_MPT_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_MPT_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_PD_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_PD_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_QP_MCG_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_QP_MCG_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_QP_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_QP_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_QP_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_QP_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_RDMA_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_RDMA_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_REQ_QP_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_REQ_QP_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_RES_QP_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_RES_QP_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SG_RQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_SG_RQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SG_SQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_SG_SQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SRQ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_SRQ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_MAX_XRC_OFFSET,4,2 ; @QUERY_DEV_CAP_MAX_XRC_OFFSET
	.comm	_QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET,4,2 ; @QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET
	.comm	_QUERY_DEV_CAP_PAGE_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_PAGE_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_PHV_EN_OFFSET,4,2 ; @QUERY_DEV_CAP_PHV_EN_OFFSET
	.comm	_QUERY_DEV_CAP_PORT_BEACON_OFFSET,4,2 ; @QUERY_DEV_CAP_PORT_BEACON_OFFSET
	.comm	_QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET,4,2 ; @QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET
	.comm	_QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET,4,2 ; @QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET
	.comm	_QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET,4,2 ; @QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET
	.comm	_QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET,4,2 ; @QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET
	.comm	_QUERY_DEV_CAP_RATE_SUPPORT_OFFSET,4,2 ; @QUERY_DEV_CAP_RATE_SUPPORT_OFFSET
	.comm	_QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_RSS_OFFSET,4,2   ; @QUERY_DEV_CAP_RSS_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_CQ_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_CQ_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_EQ_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_EQ_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_LKEY_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_LKEY_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_MCG_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_MCG_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_MRW_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_MRW_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_MTT_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_MTT_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_PD_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_PD_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_QP_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_QP_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_SRQ_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_SRQ_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_UAR_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_UAR_OFFSET
	.comm	_QUERY_DEV_CAP_RSVD_XRC_OFFSET,4,2 ; @QUERY_DEV_CAP_RSVD_XRC_OFFSET
	.comm	_QUERY_DEV_CAP_RSZ_SRQ_OFFSET,4,2 ; @QUERY_DEV_CAP_RSZ_SRQ_OFFSET
	.comm	_QUERY_DEV_CAP_SL2VL_EVENT_OFFSET,4,2 ; @QUERY_DEV_CAP_SL2VL_EVENT_OFFSET
	.comm	_QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET,4,2 ; @QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET
	.comm	_QUERY_DEV_CAP_UAR_SZ_OFFSET,4,2 ; @QUERY_DEV_CAP_UAR_SZ_OFFSET
	.comm	_QUERY_DEV_CAP_USER_MAC_EN_OFFSET,4,2 ; @QUERY_DEV_CAP_USER_MAC_EN_OFFSET
	.comm	_QUERY_DEV_CAP_VL_PORT_OFFSET,4,2 ; @QUERY_DEV_CAP_VL_PORT_OFFSET
	.comm	_QUERY_DEV_CAP_VXLAN,4,2        ; @QUERY_DEV_CAP_VXLAN
	.comm	_QUERY_DEV_CAP_WOL_OFFSET,4,2   ; @QUERY_DEV_CAP_WOL_OFFSET
.subsections_via_symbols
