	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function artpec6_pcie_wait_for_phy_a7
_artpec6_pcie_wait_for_phy_a7:          ## @artpec6_pcie_wait_for_phy_a7
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	8(%rdi), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movl	$-50, %ebx
	movq	_NOCCFG@GOTPCREL(%rip), %r14
	movq	_NOCCFG_POWER_PCIE_IDLEACK@GOTPCREL(%rip), %r12
	movq	_NOCCFG_POWER_PCIE_IDLE@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_artpec6_pcie_readl
	incl	%ebx
	je	LBB0_3
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	movl	(%r13), %ecx
	orl	(%r12), %ecx
	testl	%eax, %ecx
	jne	LBB0_1
	jmp	LBB0_4
LBB0_3:
	leaq	L_.str(%rip), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dev_err
LBB0_4:
	movl	$-50, %r12d
	movq	_PHY_RX_ASIC_OUT@GOTPCREL(%rip), %r14
	movq	_PHY_RX_ASIC_OUT_ACK@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$2000, %esi                     ## imm = 0x7D0
	callq	_usleep_range
	movq	_PHY_TX_ASIC_OUT@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	(%r15), %rdi
	callq	_readw
	movl	%eax, %ebx
	movq	(%r14), %rdi
	addq	(%r15), %rdi
	callq	_readw
	incl	%r12d
	je	LBB0_8
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	movq	_PHY_TX_ASIC_OUT_TX_ACK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %ebx
	andl	(%r13), %eax
	orl	%ebx, %eax
	jne	LBB0_5
## %bb.7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	leaq	L_.str.1(%rip), %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dev_err                        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_NOCCFG,4,2                     ## @NOCCFG
	.comm	_NOCCFG_POWER_PCIE_IDLEACK,4,2  ## @NOCCFG_POWER_PCIE_IDLEACK
	.comm	_NOCCFG_POWER_PCIE_IDLE,4,2     ## @NOCCFG_POWER_PCIE_IDLE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PCIe clock manager did not leave idle state\n"

	.comm	_PHY_TX_ASIC_OUT,8,3            ## @PHY_TX_ASIC_OUT
	.comm	_PHY_RX_ASIC_OUT,8,3            ## @PHY_RX_ASIC_OUT
	.comm	_PHY_TX_ASIC_OUT_TX_ACK,4,2     ## @PHY_TX_ASIC_OUT_TX_ACK
	.comm	_PHY_RX_ASIC_OUT_ACK,4,2        ## @PHY_RX_ASIC_OUT_ACK
L_.str.1:                               ## @.str.1
	.asciz	"PHY did not enter Pn state\n"

	.no_dead_strip	_artpec6_pcie_wait_for_phy_a7
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function artpec6_pcie_wait_for_phy_a7
_artpec6_pcie_wait_for_phy_a7:          ; @artpec6_pcie_wait_for_phy_a7
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x0
	ldr	x8, [x0, #8]
	ldr	x19, [x8]
	mov	w21, #-50
Lloh0:
	adrp	x22, _NOCCFG@GOTPAGE
Lloh1:
	ldr	x22, [x22, _NOCCFG@GOTPAGEOFF]
Lloh2:
	adrp	x23, _NOCCFG_POWER_PCIE_IDLEACK@GOTPAGE
Lloh3:
	ldr	x23, [x23, _NOCCFG_POWER_PCIE_IDLEACK@GOTPAGEOFF]
Lloh4:
	adrp	x24, _NOCCFG_POWER_PCIE_IDLE@GOTPAGE
Lloh5:
	ldr	x24, [x24, _NOCCFG_POWER_PCIE_IDLE@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	ldr	w1, [x22]
	mov	x0, x20
	bl	_artpec6_pcie_readl
	adds	w21, w21, #1
	b.hs	LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	ldr	w8, [x23]
	ldr	w9, [x24]
	orr	w8, w9, w8
	tst	w8, w0
	b.ne	LBB0_1
	b	LBB0_4
LBB0_3:
Lloh6:
	adrp	x1, l_.str@PAGE
Lloh7:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dev_err
LBB0_4:
	mov	w22, #-50
Lloh8:
	adrp	x23, _PHY_TX_ASIC_OUT@GOTPAGE
Lloh9:
	ldr	x23, [x23, _PHY_TX_ASIC_OUT@GOTPAGEOFF]
Lloh10:
	adrp	x24, _PHY_RX_ASIC_OUT@GOTPAGE
Lloh11:
	ldr	x24, [x24, _PHY_RX_ASIC_OUT@GOTPAGEOFF]
Lloh12:
	adrp	x25, _PHY_TX_ASIC_OUT_TX_ACK@GOTPAGE
Lloh13:
	ldr	x25, [x25, _PHY_TX_ASIC_OUT_TX_ACK@GOTPAGEOFF]
Lloh14:
	adrp	x26, _PHY_RX_ASIC_OUT_ACK@GOTPAGE
Lloh15:
	ldr	x26, [x26, _PHY_RX_ASIC_OUT_ACK@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	mov	w0, #1000
	mov	w1, #2000
	bl	_usleep_range
	ldr	x8, [x20]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_readw
	mov	x21, x0
	ldr	x8, [x20]
	ldr	x9, [x24]
	add	x0, x9, x8
	bl	_readw
	adds	w22, w22, #1
	b.hs	LBB0_8
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [x25]
	and	w8, w8, w21
	ldr	w9, [x26]
	and	w9, w9, w0
	orr	w8, w8, w9
	cbnz	w8, LBB0_5
; %bb.7:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_8:
Lloh16:
	adrp	x1, l_.str.1@PAGE
Lloh17:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_dev_err
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpAdd	Lloh16, Lloh17
	.cfi_endproc
                                        ; -- End function
	.comm	_NOCCFG,4,2                     ; @NOCCFG
	.comm	_NOCCFG_POWER_PCIE_IDLEACK,4,2  ; @NOCCFG_POWER_PCIE_IDLEACK
	.comm	_NOCCFG_POWER_PCIE_IDLE,4,2     ; @NOCCFG_POWER_PCIE_IDLE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PCIe clock manager did not leave idle state\n"

	.comm	_PHY_TX_ASIC_OUT,8,3            ; @PHY_TX_ASIC_OUT
	.comm	_PHY_RX_ASIC_OUT,8,3            ; @PHY_RX_ASIC_OUT
	.comm	_PHY_TX_ASIC_OUT_TX_ACK,4,2     ; @PHY_TX_ASIC_OUT_TX_ACK
	.comm	_PHY_RX_ASIC_OUT_ACK,4,2        ; @PHY_RX_ASIC_OUT_ACK
l_.str.1:                               ; @.str.1
	.asciz	"PHY did not enter Pn state\n"

	.no_dead_strip	_artpec6_pcie_wait_for_phy_a7
.subsections_via_symbols
