	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function __dw_pcie_ep_reset_bar
___dw_pcie_ep_reset_bar:                ## @__dw_pcie_ep_reset_bar
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %ebx
	movq	%rdi, %r14
	movq	_PCI_BASE_ADDRESS_0@GOTPCREL(%rip), %rax
	shll	$2, %ebx
	addq	(%rax), %rbx
	callq	_dw_pcie_dbi_ro_wr_en
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi2
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCI_BASE_ADDRESS_MEM_TYPE_64@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_2
## %bb.1:
	addq	$4, %rbx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi2
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
LBB0_2:
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dw_pcie_dbi_ro_wr_dis          ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_BASE_ADDRESS_0,8,3         ## @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_MEM_TYPE_64,4,2 ## @PCI_BASE_ADDRESS_MEM_TYPE_64
	.no_dead_strip	___dw_pcie_ep_reset_bar
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function __dw_pcie_ep_reset_bar
___dw_pcie_ep_reset_bar:                ; @__dw_pcie_ep_reset_bar
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x19, x0
Lloh0:
	adrp	x8, _PCI_BASE_ADDRESS_0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_0@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	lsl	w9, w1, #2
	add	x20, x8, x9
	bl	_dw_pcie_dbi_ro_wr_en
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_dw_pcie_writel_dbi2
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_dw_pcie_writel_dbi
Lloh3:
	adrp	x8, _PCI_BASE_ADDRESS_MEM_TYPE_64@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_MEM_TYPE_64@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_2
; %bb.1:
	add	x20, x20, #4
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_dw_pcie_writel_dbi2
	mov	x0, x19
	mov	x1, x20
	mov	w2, #0
	bl	_dw_pcie_writel_dbi
LBB0_2:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_dw_pcie_dbi_ro_wr_dis
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_BASE_ADDRESS_0,8,3         ; @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_MEM_TYPE_64,4,2 ; @PCI_BASE_ADDRESS_MEM_TYPE_64
	.no_dead_strip	___dw_pcie_ep_reset_bar
.subsections_via_symbols
