	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos5_usbdrd_pipe3_set_refclk
_exynos5_usbdrd_pipe3_set_refclk:       ## @exynos5_usbdrd_pipe3_set_refclk
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	callq	_to_usbdrd_phy
	movq	%rax, %r14
	movq	_EXYNOS5_DRD_PHYCLKRST@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_PHYCLKRST_REFCLKSEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%eax, %ecx
	movq	_PHYCLKRST_REFCLKSEL_EXT_REFCLK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_PHYCLKRST_FSEL_PIPE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	notl	%ebx
	movq	_PHYCLKRST_MPLL_MULTIPLIER_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_PHYCLKRST_SSC_REFCLKSEL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	andl	%ecx, %ebx
	movl	(%r14), %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_9
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movq	_PHYCLKRST_MPLL_MULTIPLIER_50M_REF@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_9:
	movl	4(%r14), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_dbg
	jmp	LBB0_10
LBB0_5:
	movq	_PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_7:
	movq	_PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF@GOTPCREL(%rip), %rax
LBB0_3:
	orl	(%rax), %ebx
	xorl	%edi, %edi
	jmp	LBB0_4
LBB0_8:
	movq	_PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF@GOTPCREL(%rip), %rax
LBB0_6:
	orl	(%rax), %ebx
	movl	$136, %edi
LBB0_4:
	callq	_PHYCLKRST_SSC_REFCLKSEL
	orl	%eax, %ebx
LBB0_10:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_5
	.long	L0_0_set_7
	.long	L0_0_set_8
	.end_data_region
                                        ## -- End function
	.comm	_EXYNOS5_DRD_PHYCLKRST,8,3      ## @EXYNOS5_DRD_PHYCLKRST
	.comm	_PHYCLKRST_REFCLKSEL_MASK,4,2   ## @PHYCLKRST_REFCLKSEL_MASK
	.comm	_PHYCLKRST_REFCLKSEL_EXT_REFCLK,4,2 ## @PHYCLKRST_REFCLKSEL_EXT_REFCLK
	.comm	_PHYCLKRST_FSEL_PIPE_MASK,4,2   ## @PHYCLKRST_FSEL_PIPE_MASK
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_MASK,4,2 ## @PHYCLKRST_MPLL_MULTIPLIER_MASK
	.comm	_PHYCLKRST_SSC_REFCLKSEL_MASK,4,2 ## @PHYCLKRST_SSC_REFCLKSEL_MASK
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_50M_REF,4,2 ## @PHYCLKRST_MPLL_MULTIPLIER_50M_REF
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF,4,2 ## @PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF,4,2 ## @PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF,4,2 ## @PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"unsupported ref clk\n"

	.no_dead_strip	_exynos5_usbdrd_pipe3_set_refclk
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos5_usbdrd_pipe3_set_refclk
_exynos5_usbdrd_pipe3_set_refclk:       ; @exynos5_usbdrd_pipe3_set_refclk
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	bl	_to_usbdrd_phy
	mov	x20, x0
	ldr	x8, [x0, #8]
Lloh0:
	adrp	x9, _EXYNOS5_DRD_PHYCLKRST@GOTPAGE
Lloh1:
	ldr	x9, [x9, _EXYNOS5_DRD_PHYCLKRST@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_readl
Lloh3:
	adrp	x8, _PHYCLKRST_REFCLKSEL_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PHYCLKRST_REFCLKSEL_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _PHYCLKRST_REFCLKSEL_EXT_REFCLK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PHYCLKRST_REFCLKSEL_EXT_REFCLK@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _PHYCLKRST_FSEL_PIPE_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _PHYCLKRST_FSEL_PIPE_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _PHYCLKRST_MPLL_MULTIPLIER_MASK@GOTPAGE
Lloh13:
	ldr	x10, [x10, _PHYCLKRST_MPLL_MULTIPLIER_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	orn	w9, w10, w9
Lloh15:
	adrp	x10, _PHYCLKRST_SSC_REFCLKSEL_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _PHYCLKRST_SSC_REFCLKSEL_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w10, [x10]
	orr	w9, w9, w10
	and	w19, w9, w8
	ldr	w8, [x20]
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_3
; %bb.1:
Lloh18:
	adrp	x9, lJTI0_0@PAGE
Lloh19:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh20:
	adrp	x8, _PHYCLKRST_MPLL_MULTIPLIER_50M_REF@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PHYCLKRST_MPLL_MULTIPLIER_50M_REF@GOTPAGEOFF]
	b	LBB0_6
LBB0_3:
	ldr	w0, [x20, #4]
Lloh22:
	adrp	x1, l_.str@PAGE
Lloh23:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
	b	LBB0_10
LBB0_4:
Lloh24:
	adrp	x8, _PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF@GOTPAGEOFF]
	b	LBB0_8
LBB0_5:
Lloh26:
	adrp	x8, _PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF@GOTPAGE
Lloh27:
	ldr	x8, [x8, _PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF@GOTPAGEOFF]
LBB0_6:
	ldr	w20, [x8]
	mov	w0, #0
	b	LBB0_9
LBB0_7:
Lloh28:
	adrp	x8, _PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF@GOTPAGEOFF]
LBB0_8:
	ldr	w20, [x8]
	mov	w0, #136
LBB0_9:
	bl	_PHYCLKRST_SSC_REFCLKSEL
	orr	w8, w20, w19
	orr	w19, w8, w0
LBB0_10:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
                                        ; -- End function
	.comm	_EXYNOS5_DRD_PHYCLKRST,8,3      ; @EXYNOS5_DRD_PHYCLKRST
	.comm	_PHYCLKRST_REFCLKSEL_MASK,4,2   ; @PHYCLKRST_REFCLKSEL_MASK
	.comm	_PHYCLKRST_REFCLKSEL_EXT_REFCLK,4,2 ; @PHYCLKRST_REFCLKSEL_EXT_REFCLK
	.comm	_PHYCLKRST_FSEL_PIPE_MASK,4,2   ; @PHYCLKRST_FSEL_PIPE_MASK
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_MASK,4,2 ; @PHYCLKRST_MPLL_MULTIPLIER_MASK
	.comm	_PHYCLKRST_SSC_REFCLKSEL_MASK,4,2 ; @PHYCLKRST_SSC_REFCLKSEL_MASK
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_50M_REF,4,2 ; @PHYCLKRST_MPLL_MULTIPLIER_50M_REF
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF,4,2 ; @PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF,4,2 ; @PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF
	.comm	_PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF,4,2 ; @PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"unsupported ref clk\n"

	.no_dead_strip	_exynos5_usbdrd_pipe3_set_refclk
.subsections_via_symbols
