	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvebu_pcie_setup_hw
_mvebu_pcie_setup_hw:                   ## @mvebu_pcie_setup_hw
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_mvebu_pcie_setup_wins
	movq	_PCIE_CMD_OFF@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_mvebu_readl
	movq	_PCI_COMMAND_IO@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_PCI_COMMAND_MEMORY@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_PCI_COMMAND_MASTER@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edx
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_mvebu_writel
	movq	_PCIE_MASK_OFF@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_mvebu_readl
	movq	_PCIE_MASK_ENABLE_INTS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %edx
	movq	%rbx, %rdi
	movl	%eax, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_mvebu_writel                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_CMD_OFF,4,2               ## @PCIE_CMD_OFF
	.comm	_PCI_COMMAND_IO,4,2             ## @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,4,2         ## @PCI_COMMAND_MEMORY
	.comm	_PCI_COMMAND_MASTER,4,2         ## @PCI_COMMAND_MASTER
	.comm	_PCIE_MASK_OFF,4,2              ## @PCIE_MASK_OFF
	.comm	_PCIE_MASK_ENABLE_INTS,4,2      ## @PCIE_MASK_ENABLE_INTS
	.no_dead_strip	_mvebu_pcie_setup_hw
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvebu_pcie_setup_hw
_mvebu_pcie_setup_hw:                   ; @mvebu_pcie_setup_hw
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_mvebu_pcie_setup_wins
Lloh0:
	adrp	x20, _PCIE_CMD_OFF@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCIE_CMD_OFF@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_mvebu_readl
Lloh2:
	adrp	x8, _PCI_COMMAND_IO@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCI_COMMAND_IO@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh5:
	adrp	x9, _PCI_COMMAND_MEMORY@GOTPAGE
Lloh6:
	ldr	x9, [x9, _PCI_COMMAND_MEMORY@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh8:
	adrp	x9, _PCI_COMMAND_MASTER@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PCI_COMMAND_MASTER@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x20]
	mov	x0, x19
	bl	_mvebu_writel
Lloh11:
	adrp	x20, _PCIE_MASK_OFF@GOTPAGE
Lloh12:
	ldr	x20, [x20, _PCIE_MASK_OFF@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_mvebu_readl
Lloh13:
	adrp	x8, _PCIE_MASK_ENABLE_INTS@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PCIE_MASK_ENABLE_INTS@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_mvebu_writel
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_CMD_OFF,4,2               ; @PCIE_CMD_OFF
	.comm	_PCI_COMMAND_IO,4,2             ; @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,4,2         ; @PCI_COMMAND_MEMORY
	.comm	_PCI_COMMAND_MASTER,4,2         ; @PCI_COMMAND_MASTER
	.comm	_PCIE_MASK_OFF,4,2              ; @PCIE_MASK_OFF
	.comm	_PCIE_MASK_ENABLE_INTS,4,2      ; @PCIE_MASK_ENABLE_INTS
	.no_dead_strip	_mvebu_pcie_setup_hw
.subsections_via_symbols
