	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath9k_hw_init_interrupt_masks
_ath9k_hw_init_interrupt_masks:         ## @ath9k_hw_init_interrupt_masks
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_AR_IMR_TXERR@GOTPCREL(%rip), %rax
	movq	_AR_IMR_TXURN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r13d
	orl	(%rax), %r13d
	movq	%rdi, %r12
	movq	_AR_IMR_RXERR@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_AR_INTR_SYNC_DEFAULT@GOTPCREL(%rip), %rax
	movq	_AR_IMR_RXORN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %r13d
	movl	(%rax), %ebx
	movq	_AR_IMR_BCNMISC@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	callq	_AR_SREV_9340
	testq	%rax, %rax
	jne	LBB0_4
## %bb.1:
	movq	%r12, %rdi
	callq	_AR_SREV_9550
	testq	%rax, %rax
	jne	LBB0_4
## %bb.2:
	movq	%r12, %rdi
	callq	_AR_SREV_9531
	testq	%rax, %rax
	jne	LBB0_4
## %bb.3:
	movq	%r12, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	je	LBB0_5
LBB0_4:
	movq	_AR_INTR_SYNC_HOST1_FATAL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_5:
	movq	%r12, %rdi
	callq	_AR_SREV_9300_20_OR_LATER
	testq	%rax, %rax
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	je	LBB0_9
## %bb.6:
	movq	_AR_IMR_RXOK_HP@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	cmpq	$0, 24(%r12)
	jne	LBB0_7
## %bb.8:
	movq	_AR_IMR_RXOK_LP@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_9:
	cmpq	$0, 24(%r12)
	je	LBB0_10
LBB0_7:
	movq	_AR_IMR_RXINTM@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_AR_IMR_RXMINTR@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_AR_INTCFG_MSI_RXINTM@GOTPCREL(%rip), %rax
	movq	_AR_INTCFG_MSI_RXMINTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r14d
	orl	(%rax), %r14d
	cmpq	$0, 16(%r12)
	je	LBB0_14
LBB0_13:
	movq	_AR_IMR_TXINTM@GOTPCREL(%rip), %rax
	movq	_AR_IMR_TXMINTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_AR_INTCFG_MSI_TXINTM@GOTPCREL(%rip), %rax
	movq	_AR_INTCFG_MSI_TXMINTR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r15d
	orl	(%rax), %r15d
	jmp	LBB0_15
LBB0_10:
	movq	_AR_IMR_RXOK@GOTPCREL(%rip), %rax
LBB0_11:
	orl	(%rax), %r13d
	movq	_AR_INTCFG_MSI_RXOK@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	cmpq	$0, 16(%r12)
	jne	LBB0_13
LBB0_14:
	movq	_AR_IMR_TXOK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_AR_INTCFG_MSI_TXOK@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
LBB0_15:
	orl	%r13d, %ebx
	movq	%r12, %rdi
	callq	_ENABLE_REGWRITE_BUFFER
	movq	_AR_IMR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movq	_AR_IMR_S2_GTT@GOTPCREL(%rip), %rax
	movl	(%r12), %edx
	orl	(%rax), %edx
	movl	%edx, (%r12)
	movq	_AR_IMR_S2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_REG_WRITE
	cmpq	$0, 8(%r12)
	je	LBB0_17
## %bb.16:
	orl	%r14d, %r15d
	movq	_AR_PCIE_MSI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_REG_READ
	movq	_AR_PCIE_MSI_HW_DBI_WR_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	%eax, 4(%r12)
	movq	_AR_INTCFG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r12, %rdi
	movl	%r15d, %edx
	callq	_REG_WRITE
	movq	%r12, %rdi
	callq	_ath9k_hw_common
	movl	%eax, %r13d
	movq	_ANY@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_REG_READ
	leaq	L_.str(%rip), %rdx
	movl	%r13d, %edi
	movl	%ebx, %esi
	movl	%eax, %ecx
	movl	%r15d, %r8d
	callq	_ath_dbg
LBB0_17:
	movq	%r12, %rdi
	callq	_AR_SREV_9100
	testl	%eax, %eax
	jne	LBB0_19
## %bb.18:
	movq	_AR_INTR_SYNC_CAUSE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$-1, %edx
	callq	_REG_WRITE
	movq	_AR_INTR_SYNC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	callq	_REG_WRITE
	movq	_AR_INTR_SYNC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_REG_WRITE
LBB0_19:
	movq	%r12, %rdi
	callq	_REGWRITE_BUFFER_FLUSH
	movq	%r12, %rdi
	callq	_AR_SREV_9300_20_OR_LATER
	testq	%rax, %rax
	je	LBB0_20
## %bb.21:
	movq	_AR_INTR_PRIO_ASYNC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_REG_WRITE
	movq	_AR_INTR_PRIO_ASYNC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_REG_WRITE
	movq	_AR_INTR_PRIO_SYNC_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_REG_WRITE
	movq	_AR_INTR_PRIO_SYNC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	xorl	%edx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WRITE                      ## TAILCALL
LBB0_20:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_INTR_SYNC_DEFAULT,4,2       ## @AR_INTR_SYNC_DEFAULT
	.comm	_AR_IMR_TXERR,4,2               ## @AR_IMR_TXERR
	.comm	_AR_IMR_TXURN,4,2               ## @AR_IMR_TXURN
	.comm	_AR_IMR_RXERR,4,2               ## @AR_IMR_RXERR
	.comm	_AR_IMR_RXORN,4,2               ## @AR_IMR_RXORN
	.comm	_AR_IMR_BCNMISC,4,2             ## @AR_IMR_BCNMISC
	.comm	_AR_INTR_SYNC_HOST1_FATAL,4,2   ## @AR_INTR_SYNC_HOST1_FATAL
	.comm	_AR_IMR_RXOK_HP,4,2             ## @AR_IMR_RXOK_HP
	.comm	_AR_IMR_RXINTM,4,2              ## @AR_IMR_RXINTM
	.comm	_AR_IMR_RXMINTR,4,2             ## @AR_IMR_RXMINTR
	.comm	_AR_INTCFG_MSI_RXINTM,4,2       ## @AR_INTCFG_MSI_RXINTM
	.comm	_AR_INTCFG_MSI_RXMINTR,4,2      ## @AR_INTCFG_MSI_RXMINTR
	.comm	_AR_IMR_RXOK_LP,4,2             ## @AR_IMR_RXOK_LP
	.comm	_AR_INTCFG_MSI_RXOK,4,2         ## @AR_INTCFG_MSI_RXOK
	.comm	_AR_IMR_RXOK,4,2                ## @AR_IMR_RXOK
	.comm	_AR_IMR_TXINTM,4,2              ## @AR_IMR_TXINTM
	.comm	_AR_IMR_TXMINTR,4,2             ## @AR_IMR_TXMINTR
	.comm	_AR_INTCFG_MSI_TXINTM,4,2       ## @AR_INTCFG_MSI_TXINTM
	.comm	_AR_INTCFG_MSI_TXMINTR,4,2      ## @AR_INTCFG_MSI_TXMINTR
	.comm	_AR_IMR_TXOK,4,2                ## @AR_IMR_TXOK
	.comm	_AR_INTCFG_MSI_TXOK,4,2         ## @AR_INTCFG_MSI_TXOK
	.comm	_AR_IMR,4,2                     ## @AR_IMR
	.comm	_AR_IMR_S2_GTT,4,2              ## @AR_IMR_S2_GTT
	.comm	_AR_IMR_S2,4,2                  ## @AR_IMR_S2
	.comm	_AR_PCIE_MSI,4,2                ## @AR_PCIE_MSI
	.comm	_AR_PCIE_MSI_HW_DBI_WR_EN,4,2   ## @AR_PCIE_MSI_HW_DBI_WR_EN
	.comm	_AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64,4,2 ## @AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64
	.comm	_AR_INTCFG,4,2                  ## @AR_INTCFG
	.comm	_ANY,4,2                        ## @ANY
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"value of AR_INTCFG=0x%X, msi_cfg=0x%X\n"

	.comm	_AR_INTR_SYNC_CAUSE,4,2         ## @AR_INTR_SYNC_CAUSE
	.comm	_AR_INTR_SYNC_ENABLE,4,2        ## @AR_INTR_SYNC_ENABLE
	.comm	_AR_INTR_SYNC_MASK,4,2          ## @AR_INTR_SYNC_MASK
	.comm	_AR_INTR_PRIO_ASYNC_ENABLE,4,2  ## @AR_INTR_PRIO_ASYNC_ENABLE
	.comm	_AR_INTR_PRIO_ASYNC_MASK,4,2    ## @AR_INTR_PRIO_ASYNC_MASK
	.comm	_AR_INTR_PRIO_SYNC_ENABLE,4,2   ## @AR_INTR_PRIO_SYNC_ENABLE
	.comm	_AR_INTR_PRIO_SYNC_MASK,4,2     ## @AR_INTR_PRIO_SYNC_MASK
	.no_dead_strip	_ath9k_hw_init_interrupt_masks
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath9k_hw_init_interrupt_masks
_ath9k_hw_init_interrupt_masks:         ; @ath9k_hw_init_interrupt_masks
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _AR_INTR_SYNC_DEFAULT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AR_INTR_SYNC_DEFAULT@GOTPAGEOFF]
Lloh2:
	adrp	x9, _AR_IMR_TXERR@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AR_IMR_TXERR@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
Lloh5:
	adrp	x10, _AR_IMR_TXURN@GOTPAGE
Lloh6:
	ldr	x10, [x10, _AR_IMR_TXURN@GOTPAGEOFF]
Lloh7:
	ldr	w10, [x10]
	orr	w9, w10, w9
Lloh8:
	adrp	x10, _AR_IMR_RXERR@GOTPAGE
Lloh9:
	ldr	x10, [x10, _AR_IMR_RXERR@GOTPAGEOFF]
Lloh10:
	ldr	w10, [x10]
	orr	w9, w9, w10
Lloh11:
	adrp	x10, _AR_IMR_RXORN@GOTPAGE
Lloh12:
	ldr	x10, [x10, _AR_IMR_RXORN@GOTPAGEOFF]
Lloh13:
	ldr	w20, [x8]
Lloh14:
	ldr	w8, [x10]
	orr	w21, w9, w8
Lloh15:
	adrp	x8, _AR_IMR_BCNMISC@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AR_IMR_BCNMISC@GOTPAGEOFF]
Lloh17:
	ldr	w22, [x8]
	bl	_AR_SREV_9340
	cbnz	x0, LBB0_4
; %bb.1:
	mov	x0, x19
	bl	_AR_SREV_9550
	cbnz	x0, LBB0_4
; %bb.2:
	mov	x0, x19
	bl	_AR_SREV_9531
	cbnz	x0, LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_AR_SREV_9561
	cbz	x0, LBB0_5
LBB0_4:
Lloh18:
	adrp	x8, _AR_INTR_SYNC_HOST1_FATAL@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AR_INTR_SYNC_HOST1_FATAL@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	bic	w20, w20, w8
LBB0_5:
	orr	w21, w21, w22
	mov	x0, x19
	bl	_AR_SREV_9300_20_OR_LATER
	cbz	x0, LBB0_8
; %bb.6:
Lloh21:
	adrp	x8, _AR_IMR_RXOK_HP@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AR_IMR_RXOK_HP@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	orr	w8, w8, w21
	ldr	x9, [x19, #24]
	cbz	x9, LBB0_12
; %bb.7:
Lloh24:
	adrp	x9, _AR_IMR_RXINTM@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AR_IMR_RXINTM@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
Lloh27:
	adrp	x10, _AR_IMR_RXMINTR@GOTPAGE
Lloh28:
	ldr	x10, [x10, _AR_IMR_RXMINTR@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	orr	w8, w9, w8
Lloh30:
	adrp	x9, _AR_INTCFG_MSI_RXINTM@GOTPAGE
Lloh31:
	ldr	x9, [x9, _AR_INTCFG_MSI_RXINTM@GOTPAGEOFF]
	orr	w8, w8, w10
Lloh32:
	ldr	w9, [x9]
	b	LBB0_10
LBB0_8:
	ldr	x8, [x19, #24]
	cbz	x8, LBB0_13
; %bb.9:
Lloh33:
	adrp	x8, _AR_IMR_RXINTM@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AR_IMR_RXINTM@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
Lloh36:
	adrp	x9, _AR_IMR_RXMINTR@GOTPAGE
Lloh37:
	ldr	x9, [x9, _AR_IMR_RXMINTR@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w8, w8, w21
Lloh39:
	adrp	x10, _AR_INTCFG_MSI_RXINTM@GOTPAGE
Lloh40:
	ldr	x10, [x10, _AR_INTCFG_MSI_RXINTM@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh41:
	ldr	w9, [x10]
LBB0_10:
Lloh42:
	adrp	x10, _AR_INTCFG_MSI_RXMINTR@GOTPAGE
Lloh43:
	ldr	x10, [x10, _AR_INTCFG_MSI_RXMINTR@GOTPAGEOFF]
Lloh44:
	ldr	w10, [x10]
	orr	w22, w10, w9
	ldr	x9, [x19, #16]
	cbz	x9, LBB0_15
LBB0_11:
Lloh45:
	adrp	x9, _AR_IMR_TXINTM@GOTPAGE
Lloh46:
	ldr	x9, [x9, _AR_IMR_TXINTM@GOTPAGEOFF]
Lloh47:
	ldr	w9, [x9]
Lloh48:
	adrp	x10, _AR_IMR_TXMINTR@GOTPAGE
Lloh49:
	ldr	x10, [x10, _AR_IMR_TXMINTR@GOTPAGEOFF]
Lloh50:
	ldr	w10, [x10]
Lloh51:
	adrp	x11, _AR_INTCFG_MSI_TXINTM@GOTPAGE
Lloh52:
	ldr	x11, [x11, _AR_INTCFG_MSI_TXINTM@GOTPAGEOFF]
	orr	w9, w10, w9
Lloh53:
	ldr	w10, [x11]
Lloh54:
	adrp	x11, _AR_INTCFG_MSI_TXMINTR@GOTPAGE
Lloh55:
	ldr	x11, [x11, _AR_INTCFG_MSI_TXMINTR@GOTPAGEOFF]
Lloh56:
	ldr	w11, [x11]
	orr	w23, w11, w10
	b	LBB0_16
LBB0_12:
Lloh57:
	adrp	x9, _AR_IMR_RXOK_LP@GOTPAGE
Lloh58:
	ldr	x9, [x9, _AR_IMR_RXOK_LP@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w8, w9, w8
	b	LBB0_14
LBB0_13:
Lloh60:
	adrp	x8, _AR_IMR_RXOK@GOTPAGE
Lloh61:
	ldr	x8, [x8, _AR_IMR_RXOK@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	orr	w8, w8, w21
LBB0_14:
Lloh63:
	adrp	x9, _AR_INTCFG_MSI_RXOK@GOTPAGE
Lloh64:
	ldr	x9, [x9, _AR_INTCFG_MSI_RXOK@GOTPAGEOFF]
Lloh65:
	ldr	w22, [x9]
	ldr	x9, [x19, #16]
	cbnz	x9, LBB0_11
LBB0_15:
Lloh66:
	adrp	x9, _AR_IMR_TXOK@GOTPAGE
Lloh67:
	ldr	x9, [x9, _AR_IMR_TXOK@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
Lloh69:
	adrp	x10, _AR_INTCFG_MSI_TXOK@GOTPAGE
Lloh70:
	ldr	x10, [x10, _AR_INTCFG_MSI_TXOK@GOTPAGEOFF]
Lloh71:
	ldr	w23, [x10]
LBB0_16:
	orr	w21, w9, w8
	mov	x0, x19
	bl	_ENABLE_REGWRITE_BUFFER
Lloh72:
	adrp	x8, _AR_IMR@GOTPAGE
Lloh73:
	ldr	x8, [x8, _AR_IMR@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WRITE
Lloh75:
	adrp	x8, _AR_IMR_S2_GTT@GOTPAGE
Lloh76:
	ldr	x8, [x8, _AR_IMR_S2_GTT@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w2, w9, w8
	str	w2, [x19]
Lloh78:
	adrp	x8, _AR_IMR_S2@GOTPAGE
Lloh79:
	ldr	x8, [x8, _AR_IMR_S2@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_WRITE
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_18
; %bb.17:
	orr	w21, w23, w22
Lloh81:
	adrp	x8, _AR_PCIE_MSI@GOTPAGE
Lloh82:
	ldr	x8, [x8, _AR_PCIE_MSI@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_READ
Lloh84:
	adrp	x8, _AR_PCIE_MSI_HW_DBI_WR_EN@GOTPAGE
Lloh85:
	ldr	x8, [x8, _AR_PCIE_MSI_HW_DBI_WR_EN@GOTPAGEOFF]
Lloh86:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh87:
	adrp	x9, _AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64@GOTPAGE
Lloh88:
	ldr	x9, [x9, _AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	and	w8, w9, w8
	str	w8, [x19, #4]
Lloh90:
	adrp	x24, _AR_INTCFG@GOTPAGE
Lloh91:
	ldr	x24, [x24, _AR_INTCFG@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	mov	x2, x21
	bl	_REG_WRITE
	mov	x0, x19
	bl	_ath9k_hw_common
	mov	x22, x0
Lloh92:
	adrp	x8, _ANY@GOTPAGE
Lloh93:
	ldr	x8, [x8, _ANY@GOTPAGEOFF]
Lloh94:
	ldr	w23, [x8]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_REG_READ
	mov	x3, x0
Lloh95:
	adrp	x2, l_.str@PAGE
Lloh96:
	add	x2, x2, l_.str@PAGEOFF
	mov	x0, x22
	mov	x1, x23
	mov	x4, x21
	bl	_ath_dbg
LBB0_18:
	mov	x0, x19
	bl	_AR_SREV_9100
	cbnz	w0, LBB0_20
; %bb.19:
Lloh97:
	adrp	x8, _AR_INTR_SYNC_CAUSE@GOTPAGE
Lloh98:
	ldr	x8, [x8, _AR_INTR_SYNC_CAUSE@GOTPAGEOFF]
Lloh99:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	bl	_REG_WRITE
Lloh100:
	adrp	x8, _AR_INTR_SYNC_ENABLE@GOTPAGE
Lloh101:
	ldr	x8, [x8, _AR_INTR_SYNC_ENABLE@GOTPAGEOFF]
Lloh102:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_REG_WRITE
Lloh103:
	adrp	x8, _AR_INTR_SYNC_MASK@GOTPAGE
Lloh104:
	ldr	x8, [x8, _AR_INTR_SYNC_MASK@GOTPAGEOFF]
Lloh105:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WRITE
LBB0_20:
	mov	x0, x19
	bl	_REGWRITE_BUFFER_FLUSH
	mov	x0, x19
	bl	_AR_SREV_9300_20_OR_LATER
	cbz	x0, LBB0_22
; %bb.21:
Lloh106:
	adrp	x8, _AR_INTR_PRIO_ASYNC_ENABLE@GOTPAGE
Lloh107:
	ldr	x8, [x8, _AR_INTR_PRIO_ASYNC_ENABLE@GOTPAGEOFF]
Lloh108:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WRITE
Lloh109:
	adrp	x8, _AR_INTR_PRIO_ASYNC_MASK@GOTPAGE
Lloh110:
	ldr	x8, [x8, _AR_INTR_PRIO_ASYNC_MASK@GOTPAGEOFF]
Lloh111:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WRITE
Lloh112:
	adrp	x8, _AR_INTR_PRIO_SYNC_ENABLE@GOTPAGE
Lloh113:
	ldr	x8, [x8, _AR_INTR_PRIO_SYNC_ENABLE@GOTPAGEOFF]
Lloh114:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WRITE
Lloh115:
	adrp	x8, _AR_INTR_PRIO_SYNC_MASK@GOTPAGE
Lloh116:
	ldr	x8, [x8, _AR_INTR_PRIO_SYNC_MASK@GOTPAGEOFF]
Lloh117:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_REG_WRITE
LBB0_22:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh14
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh13
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpAdd	Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_INTR_SYNC_DEFAULT,4,2       ; @AR_INTR_SYNC_DEFAULT
	.comm	_AR_IMR_TXERR,4,2               ; @AR_IMR_TXERR
	.comm	_AR_IMR_TXURN,4,2               ; @AR_IMR_TXURN
	.comm	_AR_IMR_RXERR,4,2               ; @AR_IMR_RXERR
	.comm	_AR_IMR_RXORN,4,2               ; @AR_IMR_RXORN
	.comm	_AR_IMR_BCNMISC,4,2             ; @AR_IMR_BCNMISC
	.comm	_AR_INTR_SYNC_HOST1_FATAL,4,2   ; @AR_INTR_SYNC_HOST1_FATAL
	.comm	_AR_IMR_RXOK_HP,4,2             ; @AR_IMR_RXOK_HP
	.comm	_AR_IMR_RXINTM,4,2              ; @AR_IMR_RXINTM
	.comm	_AR_IMR_RXMINTR,4,2             ; @AR_IMR_RXMINTR
	.comm	_AR_INTCFG_MSI_RXINTM,4,2       ; @AR_INTCFG_MSI_RXINTM
	.comm	_AR_INTCFG_MSI_RXMINTR,4,2      ; @AR_INTCFG_MSI_RXMINTR
	.comm	_AR_IMR_RXOK_LP,4,2             ; @AR_IMR_RXOK_LP
	.comm	_AR_INTCFG_MSI_RXOK,4,2         ; @AR_INTCFG_MSI_RXOK
	.comm	_AR_IMR_RXOK,4,2                ; @AR_IMR_RXOK
	.comm	_AR_IMR_TXINTM,4,2              ; @AR_IMR_TXINTM
	.comm	_AR_IMR_TXMINTR,4,2             ; @AR_IMR_TXMINTR
	.comm	_AR_INTCFG_MSI_TXINTM,4,2       ; @AR_INTCFG_MSI_TXINTM
	.comm	_AR_INTCFG_MSI_TXMINTR,4,2      ; @AR_INTCFG_MSI_TXMINTR
	.comm	_AR_IMR_TXOK,4,2                ; @AR_IMR_TXOK
	.comm	_AR_INTCFG_MSI_TXOK,4,2         ; @AR_INTCFG_MSI_TXOK
	.comm	_AR_IMR,4,2                     ; @AR_IMR
	.comm	_AR_IMR_S2_GTT,4,2              ; @AR_IMR_S2_GTT
	.comm	_AR_IMR_S2,4,2                  ; @AR_IMR_S2
	.comm	_AR_PCIE_MSI,4,2                ; @AR_PCIE_MSI
	.comm	_AR_PCIE_MSI_HW_DBI_WR_EN,4,2   ; @AR_PCIE_MSI_HW_DBI_WR_EN
	.comm	_AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64,4,2 ; @AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64
	.comm	_AR_INTCFG,4,2                  ; @AR_INTCFG
	.comm	_ANY,4,2                        ; @ANY
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"value of AR_INTCFG=0x%X, msi_cfg=0x%X\n"

	.comm	_AR_INTR_SYNC_CAUSE,4,2         ; @AR_INTR_SYNC_CAUSE
	.comm	_AR_INTR_SYNC_ENABLE,4,2        ; @AR_INTR_SYNC_ENABLE
	.comm	_AR_INTR_SYNC_MASK,4,2          ; @AR_INTR_SYNC_MASK
	.comm	_AR_INTR_PRIO_ASYNC_ENABLE,4,2  ; @AR_INTR_PRIO_ASYNC_ENABLE
	.comm	_AR_INTR_PRIO_ASYNC_MASK,4,2    ; @AR_INTR_PRIO_ASYNC_MASK
	.comm	_AR_INTR_PRIO_SYNC_ENABLE,4,2   ; @AR_INTR_PRIO_SYNC_ENABLE
	.comm	_AR_INTR_PRIO_SYNC_MASK,4,2     ; @AR_INTR_PRIO_SYNC_MASK
	.no_dead_strip	_ath9k_hw_init_interrupt_masks
.subsections_via_symbols
