	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_phy_sata_cfg_lanes
_xgene_phy_sata_cfg_lanes:              ## @xgene_phy_sata_cfg_lanes
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_MAX_LANE@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jle	LBB0_10
## %bb.1:
	movq	%rdi, %r13
	xorl	%r14d, %r14d
	leaq	-44(%rbp), %r15
	movq	%rdi, -64(%rbp)                 ## 8-byte Spill
	jmp	LBB0_2
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_2 Depth=1
	xorl	%esi, %esi
	callq	_RXTX_REG145_RXES_ENA_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
LBB0_9:                                 ##   in Loop: Header=BB0_2 Depth=1
	callq	_RXTX_REG145_RXVWES_LATENA_SET
	movl	%eax, %ecx
	movq	%rbx, %r13
	movq	_RXTX_REG145@GOTPCREL(%rip), %rax
	movl	%ecx, -44(%rbp)
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_serdes_wr
	movq	_RXTX_REG148@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	$65535, %ecx                    ## imm = 0xFFFF
	callq	_serdes_wr
	movl	(%rbx), %edx
	addl	$2, %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	$65535, %ecx                    ## imm = 0xFFFF
	callq	_serdes_wr
	movl	(%rbx), %edx
	addl	$4, %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	$65535, %ecx                    ## imm = 0xFFFF
	callq	_serdes_wr
	movl	(%rbx), %edx
	addl	$6, %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	$65535, %ecx                    ## imm = 0xFFFF
	callq	_serdes_wr
	incq	%r14
	movq	_MAX_LANE@GOTPCREL(%rip), %rax
	movslq	(%rax), %rax
	cmpq	%rax, %r14
	jge	LBB0_10
LBB0_2:                                 ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_5 Depth 2
	movq	_RXTX_REG147@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	$6, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$16, %esi
	callq	_RXTX_REG0_CTLE_EQ_HR_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG0_CTLE_EQ_QR_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG0_CTLE_EQ_FR_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$7, %esi
	callq	_RXTX_REG1_RXACVCM_SET
	movl	%eax, -44(%rbp)
	movq	(%r13), %rcx
	movq	56(%r13), %rdx
	movslq	%r14d, %r12
	leaq	(%r12,%r12,2), %rdi
	movslq	(%rcx,%r14,4), %rcx
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	addq	%rdi, %rcx
	movl	(%rdx,%rcx,4), %esi
	movl	%eax, %edi
	callq	_RXTX_REG1_CTLE_EQ_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_RXTX_REG2_VTT_ENA_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_RXTX_REG2_VTT_SEL_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_RXTX_REG2_TX_FIFO_ENA_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG4@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movq	_CMU_REG9_WORD_LEN_20BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_RXTX_REG4_TX_WORD_MODE_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_preA3Chip@GOTPCREL(%rip), %rax
	cmpq	$0, (%rax)
	jne	LBB0_4
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_RXTX_REG1@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$2, %esi
	callq	_RXTX_REG1_RXVREG1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$2, %esi
	callq	_RXTX_REG1_RXIREF_ADJ_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
LBB0_4:                                 ##   in Loop: Header=BB0_2 Depth=1
	movq	_RXTX_REG5@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movq	(%r13), %rax
	movq	48(%r13), %rcx
	movslq	(%rax,%r14,4), %rax
	movslq	-56(%rbp), %r12                 ## 4-byte Folded Reload
	addq	%r12, %rax
	movl	(%rcx,%rax,4), %esi
	callq	_RXTX_REG5_TX_CN1_SET
	movl	%eax, -44(%rbp)
	movq	(%r13), %rcx
	movq	40(%r13), %rdx
	movslq	(%rcx,%r14,4), %rcx
	addq	%r12, %rcx
	movl	(%rdx,%rcx,4), %esi
	movl	%eax, %edi
	callq	_RXTX_REG5_TX_CP1_SET
	movl	%eax, -44(%rbp)
	movq	(%r13), %rcx
	movq	32(%r13), %rdx
	movslq	(%rcx,%r14,4), %rcx
	addq	%r12, %rcx
	movl	(%rdx,%rcx,4), %esi
	movl	%eax, %edi
	callq	_RXTX_REG5_TX_CN2_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG6@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movq	(%r13), %rax
	movq	24(%r13), %rcx
	movslq	(%rax,%r14,4), %rax
	movq	%r12, -72(%rbp)                 ## 8-byte Spill
	addq	%r12, %rax
	movl	(%rcx,%rax,4), %esi
	callq	_RXTX_REG6_TXAMP_CNTL_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_RXTX_REG6_TXAMP_ENA_SET
	movl	%eax, -44(%rbp)
	xorl	%r12d, %r12d
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG6_TX_IDLE_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG6_RX_BIST_RESYNC_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG6_RX_BIST_ERRCNT_RD_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG7@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_RXTX_REG7_BIST_ENA_RX_SET
	movl	%eax, -44(%rbp)
	movq	_CMU_REG9_WORD_LEN_20BIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_RXTX_REG7_RX_WORD_MODE_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG8@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_RXTX_REG8_CDR_LOOP_ENA_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG8_CDR_BYPASS_RXLOS_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_RXTX_REG8_SSC_ENABLE_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG8_SD_DISABLE_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$4, %esi
	callq	_RXTX_REG8_SD_VREF_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG11@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_RXTX_REG11_PHASE_ADJUST_LIMIT_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG12@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_RXTX_REG12_LATCH_OFF_ENA_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG12_SUMOS_ENABLE_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG12_RX_DET_TERM_ENABLE_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG26@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_RXTX_REG26_PERIOD_ERROR_LATCH_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_RXTX_REG26_BLWC_ENA_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG28@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	xorl	%ecx, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG31@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	xorl	%ecx, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG61@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$1, %esi
	callq	_RXTX_REG61_ISCAN_INBERT_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG61_LOADFREQ_SHIFT_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG62@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_RXTX_REG62_PERIOD_H1_QLATCH_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	movq	_RXTX_REG81@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_5:                                 ##   Parent Loop BB0_2 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movl	(%r15), %ebx
	addl	%r12d, %ebx
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	movq	-56(%rbp), %r13                 ## 8-byte Reload
	movl	%r13d, %esi
	movl	%ebx, %edx
	leaq	-44(%rbp), %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$14, %esi
	callq	_RXTX_REG89_MU_TH7_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$14, %esi
	callq	_RXTX_REG89_MU_TH8_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$14, %esi
	callq	_RXTX_REG89_MU_TH9_SET
	movl	%eax, -44(%rbp)
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	addl	$2, %r12d
	cmpl	$18, %r12d
	jne	LBB0_5
## %bb.6:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	_RXTX_REG96@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	movl	%r12d, %esi
	movl	%ebx, %edx
	leaq	-44(%rbp), %r14
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ2_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ3_SET
	movl	%eax, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	movl	(%r15), %ebx
	addl	$2, %ebx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ2_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ3_SET
	movl	%eax, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	movl	(%r15), %ebx
	addl	$4, %ebx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ2_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$16, %esi
	callq	_RXTX_REG96_MU_FREQ3_SET
	movl	%eax, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG99@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE2_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE3_SET
	movl	%eax, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	movl	(%r15), %ebx
	addl	$2, %ebx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE2_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE3_SET
	movl	%eax, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	movl	(%r15), %ebx
	addl	$4, %ebx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE1_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE2_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$7, %esi
	callq	_RXTX_REG99_MU_PHASE3_SET
	movl	%eax, -44(%rbp)
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG102@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_RXTX_REG102_FREQLOOP_LIMIT_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG114@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	$65504, %ecx                    ## imm = 0xFFE0
	callq	_serdes_wr
	movq	_RXTX_REG125@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movq	(%r13), %rax
	movq	16(%r13), %rcx
	movslq	(%rax,%r12,4), %rax
	movq	-72(%rbp), %rbx                 ## 8-byte Reload
	addq	%rbx, %rax
	movl	(%rcx,%rax,4), %esi
	callq	_RXTX_REG125_SIGN_PQ_SET
	movl	%eax, -44(%rbp)
	movq	(%r13), %rcx
	movq	8(%r13), %rdx
	movslq	(%rcx,%r12,4), %rcx
	addq	%rbx, %rcx
	movl	(%rdx,%rcx,4), %esi
	movl	%eax, %edi
	callq	_RXTX_REG125_PQ_REG_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_RXTX_REG125_PHZ_MANUAL_SET
	movl	%eax, -44(%rbp)
	movl	(%r15), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG127@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	xorl	%esi, %esi
	callq	_RXTX_REG127_LATCH_MAN_CAL_ENA_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG128@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$3, %esi
	callq	_RXTX_REG128_LATCH_CAL_WAIT_SEL_SET
	movl	%eax, -44(%rbp)
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %ecx
	callq	_serdes_wr
	movq	_RXTX_REG145@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rbx
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r14, %rcx
	callq	_serdes_rd
	movl	-44(%rbp), %edi
	movl	$3, %esi
	callq	_RXTX_REG145_RXDFE_CONFIG_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	xorl	%esi, %esi
	callq	_RXTX_REG145_TX_IDLE_SATA_SET
	movl	%eax, -44(%rbp)
	movq	_preA3Chip@GOTPCREL(%rip), %rcx
	cmpq	$0, (%rcx)
	movq	%r14, %r15
	movq	%r12, %r14
	movl	%eax, %edi
	je	LBB0_8
## %bb.7:                               ##   in Loop: Header=BB0_2 Depth=1
	movl	$1, %esi
	callq	_RXTX_REG145_RXES_ENA_SET
	movl	%eax, -44(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	jmp	LBB0_9
LBB0_10:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX_LANE,4,2                   ## @MAX_LANE
	.comm	_RXTX_REG147,4,2                ## @RXTX_REG147
	.comm	_RXTX_REG0,4,2                  ## @RXTX_REG0
	.comm	_RXTX_REG1,4,2                  ## @RXTX_REG1
	.comm	_RXTX_REG2,4,2                  ## @RXTX_REG2
	.comm	_RXTX_REG4,4,2                  ## @RXTX_REG4
	.comm	_CMU_REG9_WORD_LEN_20BIT,4,2    ## @CMU_REG9_WORD_LEN_20BIT
	.comm	_preA3Chip,8,3                  ## @preA3Chip
	.comm	_RXTX_REG5,4,2                  ## @RXTX_REG5
	.comm	_RXTX_REG6,4,2                  ## @RXTX_REG6
	.comm	_RXTX_REG7,4,2                  ## @RXTX_REG7
	.comm	_RXTX_REG8,4,2                  ## @RXTX_REG8
	.comm	_RXTX_REG11,4,2                 ## @RXTX_REG11
	.comm	_RXTX_REG12,4,2                 ## @RXTX_REG12
	.comm	_RXTX_REG26,4,2                 ## @RXTX_REG26
	.comm	_RXTX_REG28,4,2                 ## @RXTX_REG28
	.comm	_RXTX_REG31,4,2                 ## @RXTX_REG31
	.comm	_RXTX_REG61,4,2                 ## @RXTX_REG61
	.comm	_RXTX_REG62,4,2                 ## @RXTX_REG62
	.comm	_RXTX_REG81,4,2                 ## @RXTX_REG81
	.comm	_RXTX_REG96,4,2                 ## @RXTX_REG96
	.comm	_RXTX_REG99,4,2                 ## @RXTX_REG99
	.comm	_RXTX_REG102,4,2                ## @RXTX_REG102
	.comm	_RXTX_REG114,4,2                ## @RXTX_REG114
	.comm	_RXTX_REG125,4,2                ## @RXTX_REG125
	.comm	_RXTX_REG127,4,2                ## @RXTX_REG127
	.comm	_RXTX_REG128,4,2                ## @RXTX_REG128
	.comm	_RXTX_REG145,4,2                ## @RXTX_REG145
	.comm	_RXTX_REG148,4,2                ## @RXTX_REG148
	.no_dead_strip	_xgene_phy_sata_cfg_lanes
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_phy_sata_cfg_lanes
_xgene_phy_sata_cfg_lanes:              ; @xgene_phy_sata_cfg_lanes
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, _MAX_LANE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MAX_LANE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, #1
	b.lt	LBB0_10
; %bb.1:
	mov	x19, x0
	mov	x20, #0
Lloh3:
	adrp	x25, _CMU_REG9_WORD_LEN_20BIT@GOTPAGE
Lloh4:
	ldr	x25, [x25, _CMU_REG9_WORD_LEN_20BIT@GOTPAGEOFF]
Lloh5:
	adrp	x24, _preA3Chip@GOTPAGE
Lloh6:
	ldr	x24, [x24, _preA3Chip@GOTPAGEOFF]
Lloh7:
	adrp	x27, _RXTX_REG81@GOTPAGE
Lloh8:
	ldr	x27, [x27, _RXTX_REG81@GOTPAGEOFF]
Lloh9:
	adrp	x26, _RXTX_REG145@GOTPAGE
Lloh10:
	ldr	x26, [x26, _RXTX_REG145@GOTPAGEOFF]
	b	LBB0_4
LBB0_2:                                 ;   in Loop: Header=BB0_4 Depth=1
	mov	w1, #0
	bl	_RXTX_REG145_RXES_ENA_SET
	str	w0, [sp, #12]
	mov	w1, #0
LBB0_3:                                 ;   in Loop: Header=BB0_4 Depth=1
	bl	_RXTX_REG145_RXVWES_LATENA_SET
	mov	x3, x0
	mov	x25, x28
	str	w0, [sp, #12]
	ldr	w2, [x26]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh11:
	adrp	x21, _RXTX_REG148@GOTPAGE
Lloh12:
	ldr	x21, [x21, _RXTX_REG148@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #65535
	bl	_serdes_wr
	ldr	w8, [x21]
	add	w2, w8, #2
	mov	x0, x19
	mov	x1, x20
	mov	w3, #65535
	bl	_serdes_wr
	ldr	w8, [x21]
	add	w2, w8, #4
	mov	x0, x19
	mov	x1, x20
	mov	w3, #65535
	bl	_serdes_wr
	ldr	w8, [x21]
	add	w2, w8, #6
	mov	x0, x19
	mov	x1, x20
	mov	w3, #65535
	bl	_serdes_wr
	add	x20, x20, #1
Lloh13:
	adrp	x8, _MAX_LANE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _MAX_LANE@GOTPAGEOFF]
Lloh15:
	ldrsw	x8, [x8]
	cmp	x20, x8
	b.ge	LBB0_10
LBB0_4:                                 ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_7 Depth 2
Lloh16:
	adrp	x8, _RXTX_REG147@GOTPAGE
Lloh17:
	ldr	x8, [x8, _RXTX_REG147@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #6
	bl	_serdes_wr
Lloh19:
	adrp	x21, _RXTX_REG0@GOTPAGE
Lloh20:
	ldr	x21, [x21, _RXTX_REG0@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG0_CTLE_EQ_HR_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG0_CTLE_EQ_QR_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG0_CTLE_EQ_FR_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh21:
	adrp	x21, _RXTX_REG1@GOTPAGE
Lloh22:
	ldr	x21, [x21, _RXTX_REG1@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG1_RXACVCM_SET
	str	w0, [sp, #12]
	ldr	x8, [x19, #56]
	add	w22, w20, w20, lsl #1
	ldr	x9, [x19]
	ldr	w9, [x9, x20, lsl #2]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG1_CTLE_EQ_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh23:
	adrp	x21, _RXTX_REG2@GOTPAGE
Lloh24:
	ldr	x21, [x21, _RXTX_REG2@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG2_VTT_ENA_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG2_VTT_SEL_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG2_TX_FIFO_ENA_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh25:
	adrp	x21, _RXTX_REG4@GOTPAGE
Lloh26:
	ldr	x21, [x21, _RXTX_REG4@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	ldr	w1, [x25]
	bl	_RXTX_REG4_TX_WORD_MODE_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
	mov	x23, x24
	ldr	x8, [x24]
	cbnz	x8, LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
Lloh27:
	adrp	x21, _RXTX_REG1@GOTPAGE
Lloh28:
	ldr	x21, [x21, _RXTX_REG1@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #2
	bl	_RXTX_REG1_RXVREG1_SET
	str	w0, [sp, #12]
	mov	w1, #2
	bl	_RXTX_REG1_RXIREF_ADJ_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
LBB0_6:                                 ;   in Loop: Header=BB0_4 Depth=1
Lloh29:
	adrp	x21, _RXTX_REG5@GOTPAGE
Lloh30:
	ldr	x21, [x21, _RXTX_REG5@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	ldr	x8, [x19, #48]
	ldr	x9, [x19]
	lsl	x24, x20, #2
	ldr	w9, [x9, x24]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG5_TX_CN1_SET
	str	w0, [sp, #12]
	ldr	x8, [x19, #40]
	ldr	x9, [x19]
	ldr	w9, [x9, x24]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG5_TX_CP1_SET
	str	w0, [sp, #12]
	ldr	x8, [x19, #32]
	ldr	x9, [x19]
	ldr	w9, [x9, x24]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG5_TX_CN2_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh31:
	adrp	x21, _RXTX_REG6@GOTPAGE
Lloh32:
	ldr	x21, [x21, _RXTX_REG6@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	ldr	x8, [x19, #24]
	ldr	x9, [x19]
	ldr	w9, [x9, x24]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG6_TXAMP_CNTL_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG6_TXAMP_ENA_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG6_TX_IDLE_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG6_RX_BIST_RESYNC_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG6_RX_BIST_ERRCNT_RD_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh33:
	adrp	x21, _RXTX_REG7@GOTPAGE
Lloh34:
	ldr	x21, [x21, _RXTX_REG7@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG7_BIST_ENA_RX_SET
	str	w0, [sp, #12]
	mov	x28, x25
	ldr	w1, [x25]
	bl	_RXTX_REG7_RX_WORD_MODE_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh35:
	adrp	x21, _RXTX_REG8@GOTPAGE
Lloh36:
	ldr	x21, [x21, _RXTX_REG8@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG8_CDR_LOOP_ENA_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG8_CDR_BYPASS_RXLOS_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG8_SSC_ENABLE_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG8_SD_DISABLE_SET
	str	w0, [sp, #12]
	mov	w1, #4
	bl	_RXTX_REG8_SD_VREF_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh37:
	adrp	x21, _RXTX_REG11@GOTPAGE
Lloh38:
	ldr	x21, [x21, _RXTX_REG11@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG11_PHASE_ADJUST_LIMIT_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh39:
	adrp	x21, _RXTX_REG12@GOTPAGE
Lloh40:
	ldr	x21, [x21, _RXTX_REG12@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG12_LATCH_OFF_ENA_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG12_SUMOS_ENABLE_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG12_RX_DET_TERM_ENABLE_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh41:
	adrp	x21, _RXTX_REG26@GOTPAGE
Lloh42:
	ldr	x21, [x21, _RXTX_REG26@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG26_PERIOD_ERROR_LATCH_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG26_BLWC_ENA_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh43:
	adrp	x8, _RXTX_REG28@GOTPAGE
Lloh44:
	ldr	x8, [x8, _RXTX_REG28@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_serdes_wr
Lloh46:
	adrp	x8, _RXTX_REG31@GOTPAGE
Lloh47:
	ldr	x8, [x8, _RXTX_REG31@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_serdes_wr
Lloh49:
	adrp	x21, _RXTX_REG61@GOTPAGE
Lloh50:
	ldr	x21, [x21, _RXTX_REG61@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG61_ISCAN_INBERT_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG61_LOADFREQ_SHIFT_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh51:
	adrp	x21, _RXTX_REG62@GOTPAGE
Lloh52:
	ldr	x21, [x21, _RXTX_REG62@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG62_PERIOD_H1_QLATCH_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
	mov	w25, #0
LBB0_7:                                 ;   Parent Loop BB0_4 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	w8, [x27]
	add	w21, w25, w8
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #14
	bl	_RXTX_REG89_MU_TH7_SET
	str	w0, [sp, #12]
	mov	w1, #14
	bl	_RXTX_REG89_MU_TH8_SET
	str	w0, [sp, #12]
	mov	w1, #14
	bl	_RXTX_REG89_MU_TH9_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
	add	w25, w25, #2
	cmp	w25, #18
	b.ne	LBB0_7
; %bb.8:                                ;   in Loop: Header=BB0_4 Depth=1
Lloh53:
	adrp	x25, _RXTX_REG96@GOTPAGE
Lloh54:
	ldr	x25, [x25, _RXTX_REG96@GOTPAGEOFF]
	ldr	w21, [x25]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ1_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ2_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ3_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
	ldr	w8, [x25]
	add	w21, w8, #2
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ1_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ2_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ3_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
	ldr	w8, [x25]
	add	w21, w8, #4
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ1_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ2_SET
	str	w0, [sp, #12]
	mov	w1, #16
	bl	_RXTX_REG96_MU_FREQ3_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
Lloh55:
	adrp	x25, _RXTX_REG99@GOTPAGE
Lloh56:
	ldr	x25, [x25, _RXTX_REG99@GOTPAGEOFF]
	ldr	w21, [x25]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE1_SET
	str	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE2_SET
	str	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE3_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
	ldr	w8, [x25]
	add	w21, w8, #2
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE1_SET
	str	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE2_SET
	str	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE3_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
	ldr	w8, [x25]
	add	w21, w8, #4
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE1_SET
	str	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE2_SET
	str	w0, [sp, #12]
	mov	w1, #7
	bl	_RXTX_REG99_MU_PHASE3_SET
	mov	x3, x0
	str	w0, [sp, #12]
	mov	x0, x19
	mov	x1, x20
	mov	x2, x21
	bl	_serdes_wr
Lloh57:
	adrp	x21, _RXTX_REG102@GOTPAGE
Lloh58:
	ldr	x21, [x21, _RXTX_REG102@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG102_FREQLOOP_LIMIT_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh59:
	adrp	x8, _RXTX_REG114@GOTPAGE
Lloh60:
	ldr	x8, [x8, _RXTX_REG114@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #65504
	bl	_serdes_wr
Lloh62:
	adrp	x21, _RXTX_REG125@GOTPAGE
Lloh63:
	ldr	x21, [x21, _RXTX_REG125@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	ldr	x8, [x19, #16]
	ldr	x9, [x19]
	ldr	w9, [x9, x24]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG125_SIGN_PQ_SET
	str	w0, [sp, #12]
	ldp	x9, x8, [x19]
	ldr	w9, [x9, x24]
	add	w9, w9, w22
	ldr	w1, [x8, w9, sxtw #2]
	bl	_RXTX_REG125_PQ_REG_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_RXTX_REG125_PHZ_MANUAL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh64:
	adrp	x21, _RXTX_REG127@GOTPAGE
Lloh65:
	ldr	x21, [x21, _RXTX_REG127@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG127_LATCH_MAN_CAL_ENA_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
Lloh66:
	adrp	x21, _RXTX_REG128@GOTPAGE
Lloh67:
	ldr	x21, [x21, _RXTX_REG128@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #3
	bl	_RXTX_REG128_LATCH_CAL_WAIT_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_wr
	ldr	w2, [x26]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_serdes_rd
	ldr	w0, [sp, #12]
	mov	w1, #3
	bl	_RXTX_REG145_RXDFE_CONFIG_SET
	str	w0, [sp, #12]
	mov	w1, #0
	bl	_RXTX_REG145_TX_IDLE_SATA_SET
	str	w0, [sp, #12]
	mov	x24, x23
	ldr	x8, [x23]
	cbz	x8, LBB0_2
; %bb.9:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	w1, #1
	bl	_RXTX_REG145_RXES_ENA_SET
	str	w0, [sp, #12]
	mov	w1, #1
	b	LBB0_3
LBB0_10:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh53, Lloh54
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX_LANE,4,2                   ; @MAX_LANE
	.comm	_RXTX_REG147,4,2                ; @RXTX_REG147
	.comm	_RXTX_REG0,4,2                  ; @RXTX_REG0
	.comm	_RXTX_REG1,4,2                  ; @RXTX_REG1
	.comm	_RXTX_REG2,4,2                  ; @RXTX_REG2
	.comm	_RXTX_REG4,4,2                  ; @RXTX_REG4
	.comm	_CMU_REG9_WORD_LEN_20BIT,4,2    ; @CMU_REG9_WORD_LEN_20BIT
	.comm	_preA3Chip,8,3                  ; @preA3Chip
	.comm	_RXTX_REG5,4,2                  ; @RXTX_REG5
	.comm	_RXTX_REG6,4,2                  ; @RXTX_REG6
	.comm	_RXTX_REG7,4,2                  ; @RXTX_REG7
	.comm	_RXTX_REG8,4,2                  ; @RXTX_REG8
	.comm	_RXTX_REG11,4,2                 ; @RXTX_REG11
	.comm	_RXTX_REG12,4,2                 ; @RXTX_REG12
	.comm	_RXTX_REG26,4,2                 ; @RXTX_REG26
	.comm	_RXTX_REG28,4,2                 ; @RXTX_REG28
	.comm	_RXTX_REG31,4,2                 ; @RXTX_REG31
	.comm	_RXTX_REG61,4,2                 ; @RXTX_REG61
	.comm	_RXTX_REG62,4,2                 ; @RXTX_REG62
	.comm	_RXTX_REG81,4,2                 ; @RXTX_REG81
	.comm	_RXTX_REG96,4,2                 ; @RXTX_REG96
	.comm	_RXTX_REG99,4,2                 ; @RXTX_REG99
	.comm	_RXTX_REG102,4,2                ; @RXTX_REG102
	.comm	_RXTX_REG114,4,2                ; @RXTX_REG114
	.comm	_RXTX_REG125,4,2                ; @RXTX_REG125
	.comm	_RXTX_REG127,4,2                ; @RXTX_REG127
	.comm	_RXTX_REG128,4,2                ; @RXTX_REG128
	.comm	_RXTX_REG145,4,2                ; @RXTX_REG145
	.comm	_RXTX_REG148,4,2                ; @RXTX_REG148
	.no_dead_strip	_xgene_phy_sata_cfg_lanes
.subsections_via_symbols
