	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_etype_init
_mvpp2_prs_etype_init:                  ## @mvpp2_prs_etype_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.1:
	leaq	-56(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_ETH_P_PPP_SES@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_PPPOE_HDR_SIZE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_LU_PPPOE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_PPPOE_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_sram_ri_update
	movl	-56(%rbp), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$0, (%rcx,%rdx)
	movl	(%rbx), %ecx
	movq	%r15, %rdi
	movl	%ecx, %edx
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movl	(%r13), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.2:
	leaq	-56(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_ETH_P_ARP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_RI_L3_ARP@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movl	(%r13), %edx
	movl	(%rbx), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.3:
	leaq	-56(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_MVPP2_IP_LBDT_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_MVPP2_PRS_RI_CPU_CODE_MASK@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_UDF3_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %r13
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movq	_MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%rbx), %ecx
	movq	_MVPP2_PRS_RI_CPU_CODE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movl	(%r13), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.4:
	leaq	-56(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_ETH_P_IP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	movq	_MVPP2_PRS_IPV4_HEAD@GOTPCREL(%rip), %rcx
	movq	_MVPP2_PRS_IPV4_IHL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	(%rcx), %edx
	movq	_MVPP2_PRS_IPV4_HEAD_MASK@GOTPCREL(%rip), %rdi
	movq	_MVPP2_PRS_IPV4_IHL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	orl	(%rdi), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_data_byte_set
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L3_IP4@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	(%r13), %rsi
	addq	$4, %rsi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%r13), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %r13
	movq	(%r13), %rax
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$0, (%rcx,%rdx)
	movl	(%rbx), %edx
	movl	(%r12), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.5:
	movl	%ebx, -56(%rbp)
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MVPP2_PRS_IPV4_HEAD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MVPP2_PRS_IPV4_HEAD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	leaq	-56(%rbp), %r14
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_data_byte_set
	movq	-48(%rbp), %rax
	movq	_MVPP2_PRS_SRAM_RI_WORD@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	$0, (%rax,%rcx,4)
	movq	_MVPP2_PRS_SRAM_RI_CTRL_WORD@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	$0, (%rax,%rcx,4)
	movq	_MVPP2_PRS_RI_L3_IP4_OPT@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movl	-56(%rbp), %esi
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$0, (%rcx,%rdx)
	movl	(%r12), %edx
	movl	(%rbx), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.6:
	leaq	-56(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_ETH_P_IPV6@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rax
	movq	_MVPP2_MAX_L3_ADDR_SIZE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	leaq	8(%rax,%rcx), %rsi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_LU_IP6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L3_IP6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	(%rbx), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$0, (%rcx,%rdx)
	movq	_MVPP2_PRS_RI_L3_IP6@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r13), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PE_ETH_TYPE_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -56(%rbp)
	movq	_MVPP2_PRS_PORT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L3_UN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	_MVPP2_PRS_UDF_L2_DEF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	(%r15), %rcx
	movslq	-56(%rbp), %rsi
	movq	%rsi, %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movl	(%rbx), %edx
	movl	(%r13), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_ri_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	xorl	%ebx, %ebx
LBB0_7:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ## @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ## @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_L2,4,2            ## @MVPP2_PRS_LU_L2
	.comm	_ETH_P_PPP_SES,4,2              ## @ETH_P_PPP_SES
	.comm	_MVPP2_PPPOE_HDR_SIZE,8,3       ## @MVPP2_PPPOE_HDR_SIZE
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_LU_PPPOE,4,2         ## @MVPP2_PRS_LU_PPPOE
	.comm	_MVPP2_PRS_RI_PPPOE_MASK,4,2    ## @MVPP2_PRS_RI_PPPOE_MASK
	.comm	_MVPP2_PRS_UDF_L2_DEF,8,3       ## @MVPP2_PRS_UDF_L2_DEF
	.comm	_ETH_P_ARP,4,2                  ## @ETH_P_ARP
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ## @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ## @MVPP2_PRS_SRAM_LU_GEN_BIT
	.comm	_MVPP2_PRS_RI_L3_ARP,4,2        ## @MVPP2_PRS_RI_L3_ARP
	.comm	_MVPP2_PRS_RI_L3_PROTO_MASK,4,2 ## @MVPP2_PRS_RI_L3_PROTO_MASK
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L3,4,2 ## @MVPP2_PRS_SRAM_UDF_TYPE_L3
	.comm	_MVPP2_ETH_TYPE_LEN,8,3         ## @MVPP2_ETH_TYPE_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_IP_LBDT_TYPE,4,2         ## @MVPP2_IP_LBDT_TYPE
	.comm	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC,4,2 ## @MVPP2_PRS_RI_CPU_CODE_RX_SPEC
	.comm	_MVPP2_PRS_RI_UDF3_RX_SPECIAL,4,2 ## @MVPP2_PRS_RI_UDF3_RX_SPECIAL
	.comm	_MVPP2_PRS_RI_CPU_CODE_MASK,4,2 ## @MVPP2_PRS_RI_CPU_CODE_MASK
	.comm	_MVPP2_PRS_RI_UDF3_MASK,4,2     ## @MVPP2_PRS_RI_UDF3_MASK
	.comm	_ETH_P_IP,4,2                   ## @ETH_P_IP
	.comm	_MVPP2_PRS_IPV4_HEAD,4,2        ## @MVPP2_PRS_IPV4_HEAD
	.comm	_MVPP2_PRS_IPV4_IHL,4,2         ## @MVPP2_PRS_IPV4_IHL
	.comm	_MVPP2_PRS_IPV4_HEAD_MASK,4,2   ## @MVPP2_PRS_IPV4_HEAD_MASK
	.comm	_MVPP2_PRS_IPV4_IHL_MASK,4,2    ## @MVPP2_PRS_IPV4_IHL_MASK
	.comm	_MVPP2_PRS_LU_IP4,4,2           ## @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PRS_RI_L3_IP4,4,2        ## @MVPP2_PRS_RI_L3_IP4
	.comm	_MVPP2_PRS_SRAM_RI_WORD,8,3     ## @MVPP2_PRS_SRAM_RI_WORD
	.comm	_MVPP2_PRS_SRAM_RI_CTRL_WORD,8,3 ## @MVPP2_PRS_SRAM_RI_CTRL_WORD
	.comm	_MVPP2_PRS_RI_L3_IP4_OPT,4,2    ## @MVPP2_PRS_RI_L3_IP4_OPT
	.comm	_ETH_P_IPV6,4,2                 ## @ETH_P_IPV6
	.comm	_MVPP2_MAX_L3_ADDR_SIZE,8,3     ## @MVPP2_MAX_L3_ADDR_SIZE
	.comm	_MVPP2_PRS_LU_IP6,4,2           ## @MVPP2_PRS_LU_IP6
	.comm	_MVPP2_PRS_RI_L3_IP6,4,2        ## @MVPP2_PRS_RI_L3_IP6
	.comm	_MVPP2_PE_ETH_TYPE_UN,8,3       ## @MVPP2_PE_ETH_TYPE_UN
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ## @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PRS_RI_L3_UN,4,2         ## @MVPP2_PRS_RI_L3_UN
	.no_dead_strip	_mvpp2_prs_etype_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_etype_init
_mvpp2_prs_etype_init:                  ; @mvpp2_prs_etype_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x22, _MVPP2_PE_FIRST_FREE_TID@GOTPAGE
Lloh1:
	ldr	x22, [x22, _MVPP2_PE_FIRST_FREE_TID@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh2:
	adrp	x27, _MVPP2_PE_LAST_FREE_TID@GOTPAGE
Lloh3:
	ldr	x27, [x27, _MVPP2_PE_LAST_FREE_TID@GOTPAGEOFF]
	ldr	w2, [x27]
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.1:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
Lloh4:
	adrp	x21, _MVPP2_PRS_LU_L2@GOTPAGE
Lloh5:
	ldr	x21, [x21, _MVPP2_PRS_LU_L2@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh6:
	adrp	x8, _ETH_P_PPP_SES@GOTPAGE
Lloh7:
	ldr	x8, [x8, _ETH_P_PPP_SES@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
Lloh9:
	adrp	x8, _MVPP2_PPPOE_HDR_SIZE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MVPP2_PPPOE_HDR_SIZE@GOTPAGEOFF]
Lloh11:
	ldr	x1, [x8]
Lloh12:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_shift_set
Lloh15:
	adrp	x8, _MVPP2_PRS_LU_PPPOE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _MVPP2_PRS_LU_PPPOE@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh18:
	adrp	x20, _MVPP2_PRS_RI_PPPOE_MASK@GOTPAGE
Lloh19:
	ldr	x20, [x20, _MVPP2_PRS_RI_PPPOE_MASK@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, sp
	mov	x2, x1
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
Lloh20:
	adrp	x26, _MVPP2_PRS_UDF_L2_DEF@GOTPAGE
Lloh21:
	ldr	x26, [x26, _MVPP2_PRS_UDF_L2_DEF@GOTPAGEOFF]
	ldr	x8, [x26]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	str	wzr, [x9]
	ldr	w2, [x20]
	mov	x0, x19
	mov	x3, x2
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x22]
	ldr	w2, [x27]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.2:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh22:
	adrp	x8, _ETH_P_ARP@GOTPAGE
Lloh23:
	ldr	x8, [x8, _ETH_P_ARP@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
Lloh25:
	adrp	x24, _MVPP2_PRS_LU_FLOWS@GOTPAGE
Lloh26:
	ldr	x24, [x24, _MVPP2_PRS_LU_FLOWS@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh27:
	adrp	x28, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGE
Lloh28:
	ldr	x28, [x28, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGEOFF]
	ldr	w1, [x28]
	mov	w25, #1
	mov	x0, sp
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
Lloh29:
	adrp	x20, _MVPP2_PRS_RI_L3_ARP@GOTPAGE
Lloh30:
	ldr	x20, [x20, _MVPP2_PRS_RI_L3_ARP@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh31:
	adrp	x23, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGE
Lloh32:
	ldr	x23, [x23, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
Lloh33:
	adrp	x8, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
Lloh36:
	adrp	x8, _MVPP2_ETH_TYPE_LEN@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MVPP2_ETH_TYPE_LEN@GOTPAGEOFF]
Lloh38:
	ldr	x2, [x8]
Lloh39:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGEOFF]
Lloh41:
	ldr	w3, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	ldr	x8, [x26]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	str	w25, [x9]
	mov	x25, x22
	ldr	w2, [x20]
	ldr	w3, [x23]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x22]
	ldr	w2, [x27]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.3:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh42:
	adrp	x8, _MVPP2_IP_LBDT_TYPE@GOTPAGE
Lloh43:
	ldr	x8, [x8, _MVPP2_IP_LBDT_TYPE@GOTPAGEOFF]
Lloh44:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
	ldr	w1, [x24]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
	ldr	w1, [x28]
	mov	x0, sp
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
Lloh45:
	adrp	x20, _MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPAGE
Lloh46:
	ldr	x20, [x20, _MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPAGEOFF]
	ldr	w8, [x20]
Lloh47:
	adrp	x28, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGE
Lloh48:
	ldr	x28, [x28, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGEOFF]
	mov	x22, x21
Lloh49:
	adrp	x21, _MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPAGE
Lloh50:
	ldr	x21, [x21, _MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPAGEOFF]
	ldr	w9, [x21]
Lloh51:
	adrp	x24, _MVPP2_PRS_RI_CPU_CODE_MASK@GOTPAGE
Lloh52:
	ldr	x24, [x24, _MVPP2_PRS_RI_CPU_CODE_MASK@GOTPAGEOFF]
	orr	w1, w9, w8
	ldr	w8, [x24]
Lloh53:
	adrp	x23, _MVPP2_PRS_RI_UDF3_MASK@GOTPAGE
Lloh54:
	ldr	x23, [x23, _MVPP2_PRS_RI_UDF3_MASK@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w2, w9, w8
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [x28]
Lloh55:
	adrp	x8, _MVPP2_ETH_TYPE_LEN@GOTPAGE
Lloh56:
	ldr	x8, [x8, _MVPP2_ETH_TYPE_LEN@GOTPAGEOFF]
Lloh57:
	ldr	x2, [x8]
Lloh58:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGE
Lloh59:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGEOFF]
Lloh60:
	ldr	w3, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	ldr	x8, [x26]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	mov	w8, #1
	str	w8, [x9]
	ldr	w8, [x20]
	ldr	w9, [x21]
	orr	w2, w9, w8
	ldr	w8, [x24]
	ldr	w9, [x23]
	orr	w3, w9, w8
	mov	x0, x19
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x25]
Lloh61:
	adrp	x27, _MVPP2_PE_LAST_FREE_TID@GOTPAGE
Lloh62:
	ldr	x27, [x27, _MVPP2_PE_LAST_FREE_TID@GOTPAGEOFF]
	ldr	w2, [x27]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.4:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
Lloh63:
	adrp	x21, _MVPP2_PRS_LU_L2@GOTPAGE
Lloh64:
	ldr	x21, [x21, _MVPP2_PRS_LU_L2@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh65:
	adrp	x8, _ETH_P_IP@GOTPAGE
Lloh66:
	ldr	x8, [x8, _ETH_P_IP@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
Lloh68:
	adrp	x22, _MVPP2_ETH_TYPE_LEN@GOTPAGE
Lloh69:
	ldr	x22, [x22, _MVPP2_ETH_TYPE_LEN@GOTPAGEOFF]
	ldr	x1, [x22]
Lloh70:
	adrp	x8, _MVPP2_PRS_IPV4_HEAD@GOTPAGE
Lloh71:
	ldr	x8, [x8, _MVPP2_PRS_IPV4_HEAD@GOTPAGEOFF]
Lloh72:
	ldr	w8, [x8]
Lloh73:
	adrp	x9, _MVPP2_PRS_IPV4_IHL@GOTPAGE
Lloh74:
	ldr	x9, [x9, _MVPP2_PRS_IPV4_IHL@GOTPAGEOFF]
Lloh75:
	ldr	w9, [x9]
Lloh76:
	adrp	x26, _MVPP2_PRS_IPV4_HEAD_MASK@GOTPAGE
Lloh77:
	ldr	x26, [x26, _MVPP2_PRS_IPV4_HEAD_MASK@GOTPAGEOFF]
	orr	w2, w9, w8
	ldr	w8, [x26]
Lloh78:
	adrp	x9, _MVPP2_PRS_IPV4_IHL_MASK@GOTPAGE
Lloh79:
	ldr	x9, [x9, _MVPP2_PRS_IPV4_IHL_MASK@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	orr	w3, w9, w8
	mov	x0, sp
	bl	_mvpp2_prs_tcam_data_byte_set
Lloh81:
	adrp	x8, _MVPP2_PRS_LU_IP4@GOTPAGE
Lloh82:
	ldr	x8, [x8, _MVPP2_PRS_LU_IP4@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh84:
	adrp	x20, _MVPP2_PRS_RI_L3_IP4@GOTPAGE
Lloh85:
	ldr	x20, [x20, _MVPP2_PRS_RI_L3_IP4@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh86:
	adrp	x24, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGE
Lloh87:
	ldr	x24, [x24, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	ldr	x8, [x22]
	add	x1, x8, #4
Lloh88:
	adrp	x23, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh89:
	ldr	x23, [x23, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x0, sp
	bl	_mvpp2_prs_sram_shift_set
	ldr	w1, [x28]
	ldr	x2, [x22]
Lloh90:
	adrp	x22, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGE
Lloh91:
	ldr	x22, [x22, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
Lloh92:
	adrp	x8, _MVPP2_PRS_UDF_L2_DEF@GOTPAGE
Lloh93:
	ldr	x8, [x8, _MVPP2_PRS_UDF_L2_DEF@GOTPAGEOFF]
Lloh94:
	ldr	x8, [x8]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	str	wzr, [x9]
	ldr	w2, [x20]
	ldr	w3, [x24]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x25]
	ldr	w2, [x27]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.5:
	str	w20, [sp]
Lloh95:
	adrp	x8, _MVPP2_ETH_TYPE_LEN@GOTPAGE
Lloh96:
	ldr	x8, [x8, _MVPP2_ETH_TYPE_LEN@GOTPAGEOFF]
Lloh97:
	ldr	x1, [x8]
Lloh98:
	adrp	x8, _MVPP2_PRS_IPV4_HEAD@GOTPAGE
Lloh99:
	ldr	x8, [x8, _MVPP2_PRS_IPV4_HEAD@GOTPAGEOFF]
Lloh100:
	ldr	w2, [x8]
	ldr	w3, [x26]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_data_byte_set
	ldr	x8, [sp, #8]
Lloh101:
	adrp	x9, _MVPP2_PRS_SRAM_RI_WORD@GOTPAGE
Lloh102:
	ldr	x9, [x9, _MVPP2_PRS_SRAM_RI_WORD@GOTPAGEOFF]
Lloh103:
	ldr	x9, [x9]
	str	wzr, [x8, x9, lsl #2]
Lloh104:
	adrp	x9, _MVPP2_PRS_SRAM_RI_CTRL_WORD@GOTPAGE
Lloh105:
	ldr	x9, [x9, _MVPP2_PRS_SRAM_RI_CTRL_WORD@GOTPAGEOFF]
Lloh106:
	ldr	x9, [x9]
	str	wzr, [x8, x9, lsl #2]
Lloh107:
	adrp	x20, _MVPP2_PRS_RI_L3_IP4_OPT@GOTPAGE
Lloh108:
	ldr	x20, [x20, _MVPP2_PRS_RI_L3_IP4_OPT@GOTPAGEOFF]
	ldr	w1, [x20]
	ldr	w2, [x24]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
Lloh109:
	adrp	x26, _MVPP2_PRS_UDF_L2_DEF@GOTPAGE
Lloh110:
	ldr	x26, [x26, _MVPP2_PRS_UDF_L2_DEF@GOTPAGEOFF]
	ldr	x8, [x26]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	str	wzr, [x9]
	ldr	w2, [x20]
	ldr	w3, [x24]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x25]
	ldr	w2, [x27]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.6:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh111:
	adrp	x8, _ETH_P_IPV6@GOTPAGE
Lloh112:
	ldr	x8, [x8, _ETH_P_IPV6@GOTPAGEOFF]
Lloh113:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
Lloh114:
	adrp	x25, _MVPP2_ETH_TYPE_LEN@GOTPAGE
Lloh115:
	ldr	x25, [x25, _MVPP2_ETH_TYPE_LEN@GOTPAGEOFF]
	ldr	x8, [x25]
Lloh116:
	adrp	x9, _MVPP2_MAX_L3_ADDR_SIZE@GOTPAGE
Lloh117:
	ldr	x9, [x9, _MVPP2_MAX_L3_ADDR_SIZE@GOTPAGEOFF]
Lloh118:
	ldr	x9, [x9]
	add	x8, x8, x9
	add	x1, x8, #8
	ldr	w2, [x23]
	mov	x0, sp
	bl	_mvpp2_prs_sram_shift_set
Lloh119:
	adrp	x8, _MVPP2_PRS_LU_IP6@GOTPAGE
Lloh120:
	ldr	x8, [x8, _MVPP2_PRS_LU_IP6@GOTPAGEOFF]
Lloh121:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh122:
	adrp	x20, _MVPP2_PRS_RI_L3_IP6@GOTPAGE
Lloh123:
	ldr	x20, [x20, _MVPP2_PRS_RI_L3_IP6@GOTPAGEOFF]
	ldr	w1, [x20]
	ldr	w2, [x24]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	mov	x27, x22
Lloh124:
	adrp	x22, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGE
Lloh125:
	ldr	x22, [x22, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGEOFF]
	ldr	w1, [x22]
	ldr	x2, [x25]
	ldr	w3, [x27]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	ldr	x8, [x26]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	str	wzr, [x9]
	ldr	w2, [x20]
	ldr	w3, [x24]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
Lloh126:
	adrp	x8, _MVPP2_PE_ETH_TYPE_UN@GOTPAGE
Lloh127:
	ldr	x8, [x8, _MVPP2_PE_ETH_TYPE_UN@GOTPAGEOFF]
Lloh128:
	ldr	x8, [x8]
	str	w8, [sp]
Lloh129:
	adrp	x8, _MVPP2_PRS_PORT_MASK@GOTPAGE
Lloh130:
	ldr	x8, [x8, _MVPP2_PRS_PORT_MASK@GOTPAGEOFF]
Lloh131:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_port_map_set
Lloh132:
	adrp	x8, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGE
Lloh133:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGEOFF]
Lloh134:
	ldr	w1, [x8]
	mov	w20, #1
	mov	x0, sp
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
Lloh135:
	adrp	x8, _MVPP2_PRS_LU_FLOWS@GOTPAGE
Lloh136:
	ldr	x8, [x8, _MVPP2_PRS_LU_FLOWS@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh138:
	adrp	x23, _MVPP2_PRS_RI_L3_UN@GOTPAGE
Lloh139:
	ldr	x23, [x23, _MVPP2_PRS_RI_L3_UN@GOTPAGEOFF]
	ldr	w1, [x23]
	ldr	w2, [x24]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [x22]
	ldr	x2, [x25]
	ldr	w3, [x27]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	ldr	x8, [x26]
	ldr	x9, [x19]
	ldrsw	x1, [sp]
	add	x9, x9, x1, lsl #4
	str	x8, [x9, #8]
	str	w20, [x9]
	ldr	w2, [x23]
	ldr	w3, [x24]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_ri_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	mov	w20, #0
LBB0_7:
	mov	x0, x20
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGot	Lloh90, Lloh91
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh109, Lloh110
	.loh AdrpLdrGot	Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh101, Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh98, Lloh99, Lloh100
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGot	Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGot	Lloh124, Lloh125
	.loh AdrpLdrGot	Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGot	Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ; @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ; @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_L2,4,2            ; @MVPP2_PRS_LU_L2
	.comm	_ETH_P_PPP_SES,4,2              ; @ETH_P_PPP_SES
	.comm	_MVPP2_PPPOE_HDR_SIZE,8,3       ; @MVPP2_PPPOE_HDR_SIZE
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_LU_PPPOE,4,2         ; @MVPP2_PRS_LU_PPPOE
	.comm	_MVPP2_PRS_RI_PPPOE_MASK,4,2    ; @MVPP2_PRS_RI_PPPOE_MASK
	.comm	_MVPP2_PRS_UDF_L2_DEF,8,3       ; @MVPP2_PRS_UDF_L2_DEF
	.comm	_ETH_P_ARP,4,2                  ; @ETH_P_ARP
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ; @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ; @MVPP2_PRS_SRAM_LU_GEN_BIT
	.comm	_MVPP2_PRS_RI_L3_ARP,4,2        ; @MVPP2_PRS_RI_L3_ARP
	.comm	_MVPP2_PRS_RI_L3_PROTO_MASK,4,2 ; @MVPP2_PRS_RI_L3_PROTO_MASK
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L3,4,2 ; @MVPP2_PRS_SRAM_UDF_TYPE_L3
	.comm	_MVPP2_ETH_TYPE_LEN,8,3         ; @MVPP2_ETH_TYPE_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_IP_LBDT_TYPE,4,2         ; @MVPP2_IP_LBDT_TYPE
	.comm	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC,4,2 ; @MVPP2_PRS_RI_CPU_CODE_RX_SPEC
	.comm	_MVPP2_PRS_RI_UDF3_RX_SPECIAL,4,2 ; @MVPP2_PRS_RI_UDF3_RX_SPECIAL
	.comm	_MVPP2_PRS_RI_CPU_CODE_MASK,4,2 ; @MVPP2_PRS_RI_CPU_CODE_MASK
	.comm	_MVPP2_PRS_RI_UDF3_MASK,4,2     ; @MVPP2_PRS_RI_UDF3_MASK
	.comm	_ETH_P_IP,4,2                   ; @ETH_P_IP
	.comm	_MVPP2_PRS_IPV4_HEAD,4,2        ; @MVPP2_PRS_IPV4_HEAD
	.comm	_MVPP2_PRS_IPV4_IHL,4,2         ; @MVPP2_PRS_IPV4_IHL
	.comm	_MVPP2_PRS_IPV4_HEAD_MASK,4,2   ; @MVPP2_PRS_IPV4_HEAD_MASK
	.comm	_MVPP2_PRS_IPV4_IHL_MASK,4,2    ; @MVPP2_PRS_IPV4_IHL_MASK
	.comm	_MVPP2_PRS_LU_IP4,4,2           ; @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PRS_RI_L3_IP4,4,2        ; @MVPP2_PRS_RI_L3_IP4
	.comm	_MVPP2_PRS_SRAM_RI_WORD,8,3     ; @MVPP2_PRS_SRAM_RI_WORD
	.comm	_MVPP2_PRS_SRAM_RI_CTRL_WORD,8,3 ; @MVPP2_PRS_SRAM_RI_CTRL_WORD
	.comm	_MVPP2_PRS_RI_L3_IP4_OPT,4,2    ; @MVPP2_PRS_RI_L3_IP4_OPT
	.comm	_ETH_P_IPV6,4,2                 ; @ETH_P_IPV6
	.comm	_MVPP2_MAX_L3_ADDR_SIZE,8,3     ; @MVPP2_MAX_L3_ADDR_SIZE
	.comm	_MVPP2_PRS_LU_IP6,4,2           ; @MVPP2_PRS_LU_IP6
	.comm	_MVPP2_PRS_RI_L3_IP6,4,2        ; @MVPP2_PRS_RI_L3_IP6
	.comm	_MVPP2_PE_ETH_TYPE_UN,8,3       ; @MVPP2_PE_ETH_TYPE_UN
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ; @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PRS_RI_L3_UN,4,2         ; @MVPP2_PRS_RI_L3_UN
	.no_dead_strip	_mvpp2_prs_etype_init
.subsections_via_symbols
