	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_vid_init
_mvpp2_prs_vid_init:                    ## @mvpp2_prs_vid_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	leaq	-48(%rbp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_MVPP2_PE_VID_FLTR_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movq	_MVPP2_PRS_LU_VID@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PRS_EDSA_VID_AI_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movq	_MVPP2_VLAN_TAG_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_SRAM_AI_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_sram_ai_update
	movq	_MVPP2_PRS_LU_L2@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_PORT_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_mvpp2_prs_hw_write
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_MVPP2_PE_VID_EDSA_FLTR_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PRS_EDSA_VID_AI_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movq	_MVPP2_VLAN_TAG_EDSA_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_SRAM_AI_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_sram_ai_update
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_mvpp2_prs_hw_write
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PE_VID_FLTR_DEFAULT,4,2  ## @MVPP2_PE_VID_FLTR_DEFAULT
	.comm	_MVPP2_PRS_LU_VID,4,2           ## @MVPP2_PRS_LU_VID
	.comm	_MVPP2_PRS_EDSA_VID_AI_BIT,4,2  ## @MVPP2_PRS_EDSA_VID_AI_BIT
	.comm	_MVPP2_VLAN_TAG_LEN,4,2         ## @MVPP2_VLAN_TAG_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_SRAM_AI_MASK,4,2     ## @MVPP2_PRS_SRAM_AI_MASK
	.comm	_MVPP2_PRS_LU_L2,4,2            ## @MVPP2_PRS_LU_L2
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ## @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PE_VID_EDSA_FLTR_DEFAULT,4,2 ## @MVPP2_PE_VID_EDSA_FLTR_DEFAULT
	.comm	_MVPP2_VLAN_TAG_EDSA_LEN,4,2    ## @MVPP2_VLAN_TAG_EDSA_LEN
	.no_dead_strip	_mvpp2_prs_vid_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_vid_init
_mvpp2_prs_vid_init:                    ; @mvpp2_prs_vid_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh0:
	adrp	x8, _MVPP2_PE_VID_FLTR_DEFAULT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MVPP2_PE_VID_FLTR_DEFAULT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [sp, #8]
Lloh3:
	adrp	x20, _MVPP2_PRS_LU_VID@GOTPAGE
Lloh4:
	ldr	x20, [x20, _MVPP2_PRS_LU_VID@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
Lloh5:
	adrp	x21, _MVPP2_PRS_EDSA_VID_AI_BIT@GOTPAGE
Lloh6:
	ldr	x21, [x21, _MVPP2_PRS_EDSA_VID_AI_BIT@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x0, sp, #8
	mov	w1, #0
	bl	_mvpp2_prs_tcam_ai_update
Lloh7:
	adrp	x8, _MVPP2_VLAN_TAG_LEN@GOTPAGE
Lloh8:
	ldr	x8, [x8, _MVPP2_VLAN_TAG_LEN@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
Lloh10:
	adrp	x22, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh11:
	ldr	x22, [x22, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
	ldr	w2, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_shift_set
Lloh12:
	adrp	x23, _MVPP2_PRS_SRAM_AI_MASK@GOTPAGE
Lloh13:
	ldr	x23, [x23, _MVPP2_PRS_SRAM_AI_MASK@GOTPAGEOFF]
	ldr	w2, [x23]
	add	x0, sp, #8
	mov	w1, #0
	bl	_mvpp2_prs_sram_ai_update
Lloh14:
	adrp	x24, _MVPP2_PRS_LU_L2@GOTPAGE
Lloh15:
	ldr	x24, [x24, _MVPP2_PRS_LU_L2@GOTPAGEOFF]
	ldr	w1, [x24]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh16:
	adrp	x25, _MVPP2_PRS_PORT_MASK@GOTPAGE
Lloh17:
	ldr	x25, [x25, _MVPP2_PRS_PORT_MASK@GOTPAGEOFF]
	ldr	w1, [x25]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh18:
	adrp	x8, _MVPP2_PE_VID_EDSA_FLTR_DEFAULT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MVPP2_PE_VID_EDSA_FLTR_DEFAULT@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	ldr	w1, [x20]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
	ldr	w1, [x21]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_tcam_ai_update
Lloh21:
	adrp	x8, _MVPP2_VLAN_TAG_EDSA_LEN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MVPP2_VLAN_TAG_EDSA_LEN@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	ldr	w2, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_shift_set
	ldr	w2, [x23]
	add	x0, sp, #8
	mov	w1, #0
	bl	_mvpp2_prs_sram_ai_update
	ldr	w1, [x24]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
	ldr	w1, [x25]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x20]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PE_VID_FLTR_DEFAULT,4,2  ; @MVPP2_PE_VID_FLTR_DEFAULT
	.comm	_MVPP2_PRS_LU_VID,4,2           ; @MVPP2_PRS_LU_VID
	.comm	_MVPP2_PRS_EDSA_VID_AI_BIT,4,2  ; @MVPP2_PRS_EDSA_VID_AI_BIT
	.comm	_MVPP2_VLAN_TAG_LEN,4,2         ; @MVPP2_VLAN_TAG_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_SRAM_AI_MASK,4,2     ; @MVPP2_PRS_SRAM_AI_MASK
	.comm	_MVPP2_PRS_LU_L2,4,2            ; @MVPP2_PRS_LU_L2
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ; @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PE_VID_EDSA_FLTR_DEFAULT,4,2 ; @MVPP2_PE_VID_EDSA_FLTR_DEFAULT
	.comm	_MVPP2_VLAN_TAG_EDSA_LEN,4,2    ; @MVPP2_VLAN_TAG_EDSA_LEN
	.no_dead_strip	_mvpp2_prs_vid_init
.subsections_via_symbols
