	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rtl88e_dm_fast_ant_training
_rtl88e_dm_fast_ant_training:           ## @rtl88e_dm_fast_ant_training
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_rtl_priv
	movq	%rax, %r12
	movq	%r14, %rdi
	callq	_rtl_priv
	movq	%rax, %rdi
	callq	_rtl_dm
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	_FAT_TRAINING_STATE@GOTPCREL(%rip), %rbx
	cmpq	(%rbx), %rax
	jne	LBB0_22
## %bb.1:
	movq	8(%r15), %rbx
	movq	16(%r15), %r8
	movl	(%rbx), %ecx
	testl	%ecx, %ecx
	je	LBB0_2
## %bb.3:
	movq	24(%r15), %rax
	movl	(%rax), %eax
	cltd
	idivl	%ecx
	xorl	%edi, %edi
	xorl	%r13d, %r13d
	testl	%eax, %eax
	setle	%r13b
	movl	%eax, (%r8)
	cmovgl	%eax, %edi
	addl	%r13d, %r13d
	movl	$1, %edx
	jmp	LBB0_4
LBB0_22:
	movq	_FAT_NORMAL_STATE@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_23
## %bb.24:
	movq	%r14, %rdi
	callq	_rtl88e_set_next_mac_address_target
	movq	(%rbx), %rax
	movq	%rax, (%r15)
	movq	_DM_REG_TXAGC_A_1_MCS32_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$16, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_IGI_A_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$7, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movq	_jiffies@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	_RTL_WATCH_DOG_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_MSECS
	addq	%rax, %rbx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mod_timer                      ## TAILCALL
LBB0_2:
	movl	$0, (%r8)
	movl	$2, %r13d
	xorl	%edi, %edi
	xorl	%edx, %edx
LBB0_4:
	movl	4(%rbx), %esi
	xorl	%ecx, %ecx
	movl	$0, %eax
	testl	%esi, %esi
	je	LBB0_6
## %bb.5:
	movq	24(%r15), %rax
	movl	4(%rax), %eax
	cltd
	idivl	%esi
	movl	$1, %edx
LBB0_6:
	movl	%eax, 4(%r8)
	cmpl	%edi, %eax
	cmovgl	%eax, %edi
	movl	$1, %eax
	cmovgl	%eax, %r13d
	movl	8(%rbx), %esi
	testl	%esi, %esi
	je	LBB0_8
## %bb.7:
	movq	24(%r15), %rax
	movl	8(%rax), %eax
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	$1, %edx
LBB0_8:
	cmpl	%edi, %ecx
	cmovgl	%ecx, %edi
	movl	%ecx, 8(%r8)
	movl	$2, %eax
	cmovgl	%eax, %r13d
	movl	12(%rbx), %esi
	xorl	%ecx, %ecx
	movl	$0, %eax
	testl	%esi, %esi
	je	LBB0_10
## %bb.9:
	movq	24(%r15), %rax
	movl	12(%rax), %eax
	cltd
	idivl	%esi
	movl	$1, %edx
LBB0_10:
	movl	%eax, 12(%r8)
	cmpl	%edi, %eax
	cmovgl	%eax, %edi
	movl	$3, %eax
	cmovgl	%eax, %r13d
	movl	16(%rbx), %esi
	testl	%esi, %esi
	je	LBB0_12
## %bb.11:
	movq	24(%r15), %rax
	movl	16(%rax), %eax
	cltd
	idivl	%esi
	movl	%eax, %ecx
	movl	$1, %edx
LBB0_12:
	movl	%ecx, 16(%r8)
	cmpl	%edi, %ecx
	cmovgl	%ecx, %edi
	movl	$4, %eax
	cmovgl	%eax, %r13d
	movl	20(%rbx), %ecx
	testl	%ecx, %ecx
	je	LBB0_13
## %bb.14:
	movq	24(%r15), %rax
	movl	20(%rax), %eax
	cltd
	idivl	%ecx
	movl	$1, %edx
	jmp	LBB0_15
LBB0_13:
	xorl	%eax, %eax
LBB0_15:
	movl	%eax, 20(%r8)
	cmpl	%edi, %eax
	cmovgl	%eax, %edi
	movl	$5, %eax
	cmovgl	%eax, %r13d
	movl	24(%rbx), %ecx
	testl	%ecx, %ecx
	je	LBB0_18
## %bb.16:
	movq	24(%r15), %rax
	movl	24(%rax), %eax
	cltd
	idivl	%ecx
	movl	%eax, 24(%r8)
	jmp	LBB0_17
LBB0_18:
	movl	$0, 24(%r8)
	xorl	%eax, %eax
	testl	%edx, %edx
	je	LBB0_19
LBB0_17:
	cmpl	%edi, %eax
	movl	$6, %eax
	cmovgl	%eax, %r13d
	movq	_DM_REG_TXAGC_A_1_MCS32_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	$16, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_RX_ANT_CTRL_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	$8, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_BIT
	orl	%eax, %ebx
	movl	$6, %edi
	callq	_BIT
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	movl	%r13d, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_TX_ANT_CTRL_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$21, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	xorl	%edi, %edi
	callq	_BIT
	andl	%r13d, %eax
	movq	32(%r15), %rcx
	movq	40(%r15), %rdx
	movl	%eax, (%rcx,%rdx,4)
	movl	$1, %edi
	callq	_BIT
	andl	%r13d, %eax
	shrl	%eax
	movq	40(%r15), %rcx
	movq	48(%r15), %rdx
	movl	%eax, (%rdx,%rcx,4)
	movl	$2, %edi
	callq	_BIT
	andl	%r13d, %eax
	shrl	$2, %eax
	movq	40(%r15), %rcx
	movq	56(%r15), %rdx
	movl	%eax, (%rdx,%rcx,4)
	testl	%r13d, %r13d
	jne	LBB0_21
	jmp	LBB0_20
LBB0_19:
	movq	_DM_REG_TXAGC_A_1_MCS32_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$16, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
LBB0_20:
	movq	_DM_REG_IGI_A_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$7, %edi
	callq	_BIT
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
LBB0_21:
	movq	8(%r15), %rax
	movq	24(%r15), %rcx
	movl	$0, (%rcx)
	movl	$0, (%rax)
	movl	$0, 4(%rcx)
	movl	$0, 4(%rax)
	movl	$0, 8(%rcx)
	movl	$0, 8(%rax)
	movl	$0, 12(%rcx)
	movl	$0, 12(%rax)
	movl	$0, 16(%rcx)
	movl	$0, 16(%rax)
	movl	$0, 20(%rcx)
	movl	$0, 20(%rax)
	movl	$0, 24(%rcx)
	movl	$0, 24(%rax)
	movq	_FAT_NORMAL_STATE@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, (%r15)
LBB0_23:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_FAT_TRAINING_STATE,8,3         ## @FAT_TRAINING_STATE
	.comm	_DM_REG_TXAGC_A_1_MCS32_11N,4,2 ## @DM_REG_TXAGC_A_1_MCS32_11N
	.comm	_DM_REG_IGI_A_11N,4,2           ## @DM_REG_IGI_A_11N
	.comm	_DM_REG_RX_ANT_CTRL_11N,4,2     ## @DM_REG_RX_ANT_CTRL_11N
	.comm	_DM_REG_TX_ANT_CTRL_11N,4,2     ## @DM_REG_TX_ANT_CTRL_11N
	.comm	_FAT_NORMAL_STATE,8,3           ## @FAT_NORMAL_STATE
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_RTL_WATCH_DOG_TIME,4,2         ## @RTL_WATCH_DOG_TIME
	.no_dead_strip	_rtl88e_dm_fast_ant_training
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rtl88e_dm_fast_ant_training
_rtl88e_dm_fast_ant_training:           ; @rtl88e_dm_fast_ant_training
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_rtl_priv
	mov	x21, x0
	mov	x0, x19
	bl	_rtl_priv
	bl	_rtl_dm
	mov	x20, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x22, _FAT_TRAINING_STATE@GOTPAGE
Lloh1:
	ldr	x22, [x22, _FAT_TRAINING_STATE@GOTPAGEOFF]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_14
; %bb.1:
	ldp	x9, x8, [x20, #8]
	ldr	w10, [x9]
	cbz	w10, LBB0_16
; %bb.2:
	ldr	x11, [x20, #24]
	ldr	w11, [x11]
	sdiv	w10, w11, w10
	cmp	w10, #1
	cset	w12, lt
	str	w10, [x8]
	cmp	w10, #0
	csel	w11, w10, wzr, gt
	lsl	w12, w12, #1
	mov	w10, #1
	ldr	w13, [x9, #4]
	cbz	w13, LBB0_4
LBB0_3:
	ldr	x10, [x20, #24]
	ldr	w14, [x10, #4]
	mov	w10, #1
	sdiv	w13, w14, w13
LBB0_4:
	str	w13, [x8, #4]
	cmp	w13, w11
	csel	w13, w13, w11, gt
	csinc	w11, w12, wzr, le
	ldr	w12, [x9, #8]
	cbz	w12, LBB0_6
; %bb.5:
	ldr	x10, [x20, #24]
	ldr	w14, [x10, #8]
	mov	w10, #1
	sdiv	w12, w14, w12
LBB0_6:
	str	w12, [x8, #8]
	cmp	w12, w13
	csel	w12, w12, w13, gt
	mov	w13, #2
	csel	w11, w13, w11, gt
	ldr	w13, [x9, #12]
	cbz	w13, LBB0_8
; %bb.7:
	ldr	x10, [x20, #24]
	ldr	w14, [x10, #12]
	mov	w10, #1
	sdiv	w13, w14, w13
LBB0_8:
	str	w13, [x8, #12]
	cmp	w13, w12
	csel	w12, w13, w12, gt
	mov	w13, #3
	csel	w11, w13, w11, gt
	ldr	w13, [x9, #16]
	cbz	w13, LBB0_10
; %bb.9:
	ldr	x10, [x20, #24]
	ldr	w14, [x10, #16]
	mov	w10, #1
	sdiv	w13, w14, w13
LBB0_10:
	str	w13, [x8, #16]
	cmp	w13, w12
	csel	w12, w13, w12, gt
	mov	w13, #4
	csel	w11, w13, w11, gt
	ldr	w13, [x9, #20]
	cbz	w13, LBB0_12
; %bb.11:
	ldr	x10, [x20, #24]
	ldr	w14, [x10, #20]
	mov	w10, #1
	sdiv	w13, w14, w13
LBB0_12:
	str	w13, [x8, #20]
	cmp	w13, w12
	csel	w12, w13, w12, gt
	mov	w13, #5
	csel	w11, w13, w11, gt
	ldr	w9, [x9, #24]
	cbz	w9, LBB0_17
; %bb.13:
	ldr	x10, [x20, #24]
	ldr	w10, [x10, #24]
	sdiv	w9, w10, w9
	str	w9, [x8, #24]
	b	LBB0_18
LBB0_14:
Lloh2:
	adrp	x9, _FAT_NORMAL_STATE@GOTPAGE
Lloh3:
	ldr	x9, [x9, _FAT_NORMAL_STATE@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_22
; %bb.15:
	mov	x0, x19
	bl	_rtl88e_set_next_mac_address_target
	ldr	x8, [x22]
	str	x8, [x20]
Lloh5:
	adrp	x8, _DM_REG_TXAGC_A_1_MCS32_11N@GOTPAGE
Lloh6:
	ldr	x8, [x8, _DM_REG_TXAGC_A_1_MCS32_11N@GOTPAGEOFF]
Lloh7:
	ldr	w20, [x8]
	mov	w0, #16
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	bl	_rtl_set_bbreg
Lloh8:
	adrp	x8, _DM_REG_IGI_A_11N@GOTPAGE
Lloh9:
	ldr	x8, [x8, _DM_REG_IGI_A_11N@GOTPAGEOFF]
Lloh10:
	ldr	w20, [x8]
	mov	w0, #7
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	bl	_rtl_set_bbreg
Lloh11:
	adrp	x8, _jiffies@GOTPAGE
Lloh12:
	ldr	x8, [x8, _jiffies@GOTPAGEOFF]
Lloh13:
	ldr	x19, [x8]
Lloh14:
	adrp	x8, _RTL_WATCH_DOG_TIME@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RTL_WATCH_DOG_TIME@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	bl	_MSECS
	add	x1, x0, x19
	mov	x0, x21
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_mod_timer
LBB0_16:
	mov	w11, #0
	str	wzr, [x8]
	mov	w12, #2
	ldr	w13, [x9, #4]
	cbnz	w13, LBB0_3
	b	LBB0_4
LBB0_17:
	str	wzr, [x8, #24]
	cbz	w10, LBB0_19
LBB0_18:
	mov	w8, #6
	cmp	w9, w12
	csel	w21, w8, w11, gt
Lloh17:
	adrp	x8, _DM_REG_TXAGC_A_1_MCS32_11N@GOTPAGE
Lloh18:
	ldr	x8, [x8, _DM_REG_TXAGC_A_1_MCS32_11N@GOTPAGEOFF]
Lloh19:
	ldr	w22, [x8]
	mov	w0, #16
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	mov	w3, #0
	bl	_rtl_set_bbreg
Lloh20:
	adrp	x8, _DM_REG_RX_ANT_CTRL_11N@GOTPAGE
Lloh21:
	ldr	x8, [x8, _DM_REG_RX_ANT_CTRL_11N@GOTPAGEOFF]
Lloh22:
	ldr	w22, [x8]
	mov	w0, #8
	bl	_BIT
	mov	x23, x0
	mov	w0, #7
	bl	_BIT
	orr	w23, w0, w23
	mov	w0, #6
	bl	_BIT
	orr	w2, w23, w0
	mov	x0, x19
	mov	x1, x22
	mov	x3, x21
	bl	_rtl_set_bbreg
Lloh23:
	adrp	x8, _DM_REG_TX_ANT_CTRL_11N@GOTPAGE
Lloh24:
	ldr	x8, [x8, _DM_REG_TX_ANT_CTRL_11N@GOTPAGEOFF]
Lloh25:
	ldr	w22, [x8]
	mov	w0, #21
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	mov	w3, #1
	bl	_rtl_set_bbreg
	mov	w0, #0
	bl	_BIT
	and	w8, w0, w21
	ldp	x9, x10, [x20, #32]
	str	w8, [x9, x10, lsl #2]
	mov	w0, #1
	bl	_BIT
	and	w8, w0, w21
	lsr	w8, w8, #1
	ldp	x10, x9, [x20, #40]
	str	w8, [x9, x10, lsl #2]
	mov	w0, #2
	bl	_BIT
	and	w8, w0, w21
	lsr	w8, w8, #2
	ldr	x9, [x20, #56]
	ldr	x10, [x20, #40]
	str	w8, [x9, x10, lsl #2]
	cbnz	w21, LBB0_21
	b	LBB0_20
LBB0_19:
Lloh26:
	adrp	x8, _DM_REG_TXAGC_A_1_MCS32_11N@GOTPAGE
Lloh27:
	ldr	x8, [x8, _DM_REG_TXAGC_A_1_MCS32_11N@GOTPAGEOFF]
Lloh28:
	ldr	w21, [x8]
	mov	w0, #16
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	mov	w3, #0
	bl	_rtl_set_bbreg
LBB0_20:
Lloh29:
	adrp	x8, _DM_REG_IGI_A_11N@GOTPAGE
Lloh30:
	ldr	x8, [x8, _DM_REG_IGI_A_11N@GOTPAGEOFF]
Lloh31:
	ldr	w21, [x8]
	mov	w0, #7
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	mov	w3, #0
	bl	_rtl_set_bbreg
LBB0_21:
	ldr	x8, [x20, #24]
	ldr	x9, [x20, #8]
	str	wzr, [x8]
	str	wzr, [x9]
	str	wzr, [x8, #4]
	str	wzr, [x9, #4]
	str	wzr, [x8, #8]
	str	wzr, [x9, #8]
	str	wzr, [x8, #12]
	str	wzr, [x9, #12]
	str	wzr, [x8, #16]
	str	wzr, [x9, #16]
	str	wzr, [x8, #20]
	str	wzr, [x9, #20]
	str	wzr, [x8, #24]
	str	wzr, [x9, #24]
Lloh32:
	adrp	x8, _FAT_NORMAL_STATE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _FAT_NORMAL_STATE@GOTPAGEOFF]
Lloh34:
	ldr	x8, [x8]
	str	x8, [x20]
LBB0_22:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.cfi_endproc
                                        ; -- End function
	.comm	_FAT_TRAINING_STATE,8,3         ; @FAT_TRAINING_STATE
	.comm	_DM_REG_TXAGC_A_1_MCS32_11N,4,2 ; @DM_REG_TXAGC_A_1_MCS32_11N
	.comm	_DM_REG_IGI_A_11N,4,2           ; @DM_REG_IGI_A_11N
	.comm	_DM_REG_RX_ANT_CTRL_11N,4,2     ; @DM_REG_RX_ANT_CTRL_11N
	.comm	_DM_REG_TX_ANT_CTRL_11N,4,2     ; @DM_REG_TX_ANT_CTRL_11N
	.comm	_FAT_NORMAL_STATE,8,3           ; @FAT_NORMAL_STATE
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_RTL_WATCH_DOG_TIME,4,2         ; @RTL_WATCH_DOG_TIME
	.no_dead_strip	_rtl88e_dm_fast_ant_training
.subsections_via_symbols
