	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ar5008_hw_spur_mitigate
_ar5008_hw_spur_mitigate:               ## @ar5008_hw_spur_mitigate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_AR_NO_SPUR@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rsi, %rdi
	callq	_IS_CHAN_2GHZ
	movq	_AR_EEPROM_MODAL_SPURS@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_6
## %bb.1:
	movl	%eax, %r13d
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r12), %rax
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%r13d, %edx
	callq	*(%rax)
                                        ## kill: def $eax killed $eax def $rax
	movl	(%r15), %ecx
	cmpl	%eax, %ecx
	je	LBB0_7
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movl	(%rdx), %edx
	addl	%edx, %edx
	leal	(%rdx,%rdx,4), %edx
	subl	%edx, %eax
	leal	94(%rax), %edx
	cmpl	$188, %edx
	jbe	LBB0_9
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	incl	%ebx
	cmpl	(%r14), %ebx
	jl	LBB0_2
LBB0_7:
	movl	-44(%rbp), %ebx                 ## 4-byte Reload
	cmpl	%ebx, %ecx
	jne	LBB0_8
LBB0_10:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movl	(%r15), %ecx
	cmpl	%ebx, %ecx
	je	LBB0_10
LBB0_8:
	movl	%ebx, %eax
	shll	$5, %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	xorl	%edi, %edi
	callq	_AR_PHY_TIMING_CTRL4
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_REG_READ
	movl	%ebx, %r15d
	movl	%eax, %ebx
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI@GOTPCREL(%rip), %rax
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER@GOTPCREL(%rip), %rcx
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK@GOTPCREL(%rip), %rdx
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK@GOTPCREL(%rip), %rsi
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	xorl	%edi, %edi
	callq	_AR_PHY_TIMING_CTRL4
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movq	_AR_PHY_SPUR_REG_MASK_RATE_CNTL@GOTPCREL(%rip), %rax
	movq	_AR_PHY_SPUR_REG_ENABLE_MASK_PPM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_AR_PHY_SPUR_REG_MASK_RATE_SELECT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SPUR_RSSI_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AR_PHY_SPUR_REG_SPUR_RSSI_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	%eax, %ebx
	movq	_AR_PHY_SPUR_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movl	%r15d, %eax
	shll	$19, %eax
	cltq
	imulq	$1374389535, %rax, %r13         ## imm = 0x51EB851F
	movq	%r13, %rax
	shrq	$63, %rax
	sarq	$37, %r13
	addl	%eax, %r13d
	movq	_AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPCREL(%rip), %rax
	andl	(%rax), %r13d
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	callq	_IS_CHAN_2GHZ
	testl	%eax, %eax
	movl	$400, %eax                      ## imm = 0x190
	movl	$440, %ecx                      ## imm = 0x1B8
	cmovel	%eax, %ecx
	shll	$11, %r15d
	movl	%r15d, %eax
	cltd
	idivl	%ecx
	andl	$1023, %eax                     ## imm = 0x3FF
	movq	_AR_PHY_TIMING11_USE_SPUR_IN_AGC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	_AR_PHY_TIMING11_SPUR_FREQ_SD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_SM
	movl	%eax, %r15d
	movq	_AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r13d, %edi
	callq	_SM
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_AR_PHY_TIMING11@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ar5008_hw_cmn_spur_mitigate    ## TAILCALL
LBB0_9:
	movl	%eax, %ebx
	cmpl	%ebx, %ecx
	jne	LBB0_8
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_NO_SPUR,4,2                 ## @AR_NO_SPUR
	.comm	_AR_EEPROM_MODAL_SPURS,4,2      ## @AR_EEPROM_MODAL_SPURS
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_CNTL,4,2 ## @AR_PHY_SPUR_REG_MASK_RATE_CNTL
	.comm	_AR_PHY_SPUR_REG_ENABLE_MASK_PPM,4,2 ## @AR_PHY_SPUR_REG_ENABLE_MASK_PPM
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_SELECT,4,2 ## @AR_PHY_SPUR_REG_MASK_RATE_SELECT
	.comm	_AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI,4,2 ## @AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
	.comm	_SPUR_RSSI_THRESH,4,2           ## @SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG_SPUR_RSSI_THRESH,4,2 ## @AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG,4,2            ## @AR_PHY_SPUR_REG
	.comm	_AR_PHY_TIMING11_SPUR_DELTA_PHASE,4,2 ## @AR_PHY_TIMING11_SPUR_DELTA_PHASE
	.comm	_AR_PHY_TIMING11_USE_SPUR_IN_AGC,4,2 ## @AR_PHY_TIMING11_USE_SPUR_IN_AGC
	.comm	_AR_PHY_TIMING11_SPUR_FREQ_SD,4,2 ## @AR_PHY_TIMING11_SPUR_FREQ_SD
	.comm	_AR_PHY_TIMING11,4,2            ## @AR_PHY_TIMING11
	.no_dead_strip	_ar5008_hw_spur_mitigate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ar5008_hw_spur_mitigate
_ar5008_hw_spur_mitigate:               ; @ar5008_hw_spur_mitigate
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x24, _AR_NO_SPUR@GOTPAGE
Lloh1:
	ldr	x24, [x24, _AR_NO_SPUR@GOTPAGEOFF]
	ldr	w23, [x24]
	mov	x0, x1
	bl	_IS_CHAN_2GHZ
Lloh2:
	adrp	x25, _AR_EEPROM_MODAL_SPURS@GOTPAGE
Lloh3:
	ldr	x25, [x25, _AR_EEPROM_MODAL_SPURS@GOTPAGEOFF]
	ldr	w8, [x25]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.1:
	mov	x21, x0
	mov	w22, #0
	mov	w26, #-10
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20]
	ldr	x8, [x8]
	mov	x0, x20
	mov	x1, x22
	mov	x2, x21
	blr	x8
	ldr	w8, [x24]
	cmp	w8, w0
	b.eq	LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ldr	w9, [x19]
	madd	w9, w9, w26, w0
	add	w10, w9, #94
	cmp	w10, #188
	b.ls	LBB0_8
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	add	w22, w22, #1
	ldr	w9, [x25]
	cmp	w22, w9
	b.lt	LBB0_2
	b	LBB0_6
LBB0_5:
	ldr	w8, [x24]
LBB0_6:
	cmp	w8, w23
	b.ne	LBB0_9
LBB0_7:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_8:
	mov	x23, x9
	cmp	w8, w23
	b.eq	LBB0_7
LBB0_9:
	lsl	w21, w23, #5
	mov	w0, #0
	bl	_AR_PHY_TIMING_CTRL4
	mov	x1, x0
	mov	x0, x20
	bl	_REG_READ
Lloh4:
	adrp	x8, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI@GOTPAGE
Lloh5:
	ldr	x8, [x8, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI@GOTPAGEOFF]
Lloh6:
	adrp	x9, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	ldr	w9, [x9]
Lloh10:
	adrp	x10, _AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK@GOTPAGE
Lloh11:
	ldr	x10, [x10, _AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK@GOTPAGEOFF]
Lloh12:
	adrp	x11, _AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK@GOTPAGE
Lloh13:
	ldr	x11, [x11, _AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
Lloh15:
	ldr	w11, [x11]
	orr	w8, w8, w0
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w22, w8, w11
	mov	w0, #0
	bl	_AR_PHY_TIMING_CTRL4
	mov	x1, x0
	mov	x0, x20
	mov	x2, x22
	bl	_REG_WRITE
Lloh16:
	adrp	x8, _AR_PHY_SPUR_REG_MASK_RATE_CNTL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _AR_PHY_SPUR_REG_MASK_RATE_CNTL@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	adrp	x9, _AR_PHY_SPUR_REG_ENABLE_MASK_PPM@GOTPAGE
Lloh20:
	ldr	x9, [x9, _AR_PHY_SPUR_REG_ENABLE_MASK_PPM@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh22:
	adrp	x9, _AR_PHY_SPUR_REG_MASK_RATE_SELECT@GOTPAGE
Lloh23:
	ldr	x9, [x9, _AR_PHY_SPUR_REG_MASK_RATE_SELECT@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh25:
	adrp	x9, _AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI@GOTPAGE
Lloh26:
	ldr	x9, [x9, _AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w22, w8, w9
Lloh28:
	adrp	x8, _SPUR_RSSI_THRESH@GOTPAGE
Lloh29:
	ldr	x8, [x8, _SPUR_RSSI_THRESH@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
Lloh31:
	adrp	x8, _AR_PHY_SPUR_REG_SPUR_RSSI_THRESH@GOTPAGE
Lloh32:
	ldr	x8, [x8, _AR_PHY_SPUR_REG_SPUR_RSSI_THRESH@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	bl	_SM
	orr	w2, w22, w0
Lloh34:
	adrp	x8, _AR_PHY_SPUR_REG@GOTPAGE
Lloh35:
	ldr	x8, [x8, _AR_PHY_SPUR_REG@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_REG_WRITE
	lsl	w8, w23, #19
	mov	w9, #34079
	movk	w9, #20971, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #63
	asr	x8, x8, #37
Lloh37:
	adrp	x24, _AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPAGE
Lloh38:
	ldr	x24, [x24, _AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPAGEOFF]
	ldr	w10, [x24]
	add	w8, w8, w9
	and	w22, w10, w8
	mov	x0, x19
	bl	_IS_CHAN_2GHZ
	mov	w8, #440
	mov	w9, #400
	cmp	w0, #0
	csel	w8, w9, w8, eq
	lsl	w9, w23, #11
	sdiv	w8, w9, w8
	and	w0, w8, #0x3ff
Lloh39:
	adrp	x8, _AR_PHY_TIMING11_USE_SPUR_IN_AGC@GOTPAGE
Lloh40:
	ldr	x8, [x8, _AR_PHY_TIMING11_USE_SPUR_IN_AGC@GOTPAGEOFF]
Lloh41:
	ldr	w23, [x8]
Lloh42:
	adrp	x8, _AR_PHY_TIMING11_SPUR_FREQ_SD@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AR_PHY_TIMING11_SPUR_FREQ_SD@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	bl	_SM
	orr	w23, w0, w23
	ldr	w1, [x24]
	mov	x0, x22
	bl	_SM
	orr	w2, w23, w0
Lloh45:
	adrp	x8, _AR_PHY_TIMING11@GOTPAGE
Lloh46:
	ldr	x8, [x8, _AR_PHY_TIMING11@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_REG_WRITE
	mov	x0, x20
	mov	x1, x19
	mov	x2, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_ar5008_hw_cmn_spur_mitigate
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh14
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_NO_SPUR,4,2                 ; @AR_NO_SPUR
	.comm	_AR_EEPROM_MODAL_SPURS,4,2      ; @AR_EEPROM_MODAL_SPURS
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_CNTL,4,2 ; @AR_PHY_SPUR_REG_MASK_RATE_CNTL
	.comm	_AR_PHY_SPUR_REG_ENABLE_MASK_PPM,4,2 ; @AR_PHY_SPUR_REG_ENABLE_MASK_PPM
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_SELECT,4,2 ; @AR_PHY_SPUR_REG_MASK_RATE_SELECT
	.comm	_AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI,4,2 ; @AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
	.comm	_SPUR_RSSI_THRESH,4,2           ; @SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG_SPUR_RSSI_THRESH,4,2 ; @AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG,4,2            ; @AR_PHY_SPUR_REG
	.comm	_AR_PHY_TIMING11_SPUR_DELTA_PHASE,4,2 ; @AR_PHY_TIMING11_SPUR_DELTA_PHASE
	.comm	_AR_PHY_TIMING11_USE_SPUR_IN_AGC,4,2 ; @AR_PHY_TIMING11_USE_SPUR_IN_AGC
	.comm	_AR_PHY_TIMING11_SPUR_FREQ_SD,4,2 ; @AR_PHY_TIMING11_SPUR_FREQ_SD
	.comm	_AR_PHY_TIMING11,4,2            ; @AR_PHY_TIMING11
	.no_dead_strip	_ar5008_hw_spur_mitigate
.subsections_via_symbols
