	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlx5_fpga_ipsec_build_hw_xfrm
_mlx5_fpga_ipsec_build_hw_xfrm:         ## @mlx5_fpga_ipsec_build_hw_xfrm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %rbx
	movq	%rsi, %r14
	leaq	32(%rdx), %r15
	movq	32(%rsi), %rsi
	movl	16(%r14), %eax
	leal	7(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$3, %edx
	movq	%r15, %rdi
	callq	_memcpy
	cmpl	$128, 16(%r14)
	jne	LBB0_2
## %bb.1:
	movq	(%r15), %rdi
	subq	$-128, %rdi
	movq	32(%r14), %rsi
	movl	$16, %edx
	callq	_memcpy
LBB0_2:
	leaq	16(%rbx), %r15
	leaq	24(%rbx), %rdi
	leaq	24(%r14), %rsi
	movl	$4, %edx
	callq	_memcpy
	leaq	20(%r14), %rsi
	movq	%r15, %rdi
	movl	$4, %edx
	callq	_memcpy
	movl	(%r14), %edx
	movq	_MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED@GOTPCREL(%rip), %rax
	movq	_MLX5_FPGA_IPSEC_SA_ESN_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%edx, (%rax)
	je	LBB0_6
## %bb.3:
	orl	(%rbx), %ecx
	movl	%ecx, (%rbx)
	movq	_MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP@GOTPCREL(%rip), %rax
	andl	(%rax), %edx
	je	LBB0_5
## %bb.4:
	movq	_MLX5_FPGA_IPSEC_SA_ESN_OVERLAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_5:
	orl	%ecx, %edx
	movl	%edx, (%rbx)
	movl	12(%r14), %edi
	callq	_htonl
	jmp	LBB0_9
LBB0_6:
	notl	%ecx
	andl	(%rbx), %ecx
	movl	%ecx, (%rbx)
	movq	_MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP@GOTPCREL(%rip), %rax
	andl	(%rax), %edx
	xorl	%eax, %eax
	movl	$0, %esi
	cmpl	$-1, %edx
	je	LBB0_8
## %bb.7:
	movq	_MLX5_FPGA_IPSEC_SA_ESN_OVERLAP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %esi
LBB0_8:
	andl	%ecx, %esi
	movl	%esi, (%rbx)
LBB0_9:
	movq	%rax, 40(%rbx)
	movl	8(%r14), %edi
	callq	_htonl
	movq	%rax, 8(%rbx)
	movl	16(%r14), %eax
	cmpl	$128, %eax
	je	LBB0_10
## %bb.11:
	cmpl	$256, %eax                      ## imm = 0x100
	jne	LBB0_14
## %bb.12:
	movq	_MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_10:
	movq	_MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128@GOTPCREL(%rip), %rax
LBB0_13:
	movl	(%rax), %eax
	movl	%eax, 4(%rbx)
LBB0_14:
	movq	_MLX5_FPGA_IPSEC_SA_SA_VALID@GOTPCREL(%rip), %rax
	movq	_MLX5_FPGA_IPSEC_SA_SPI_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLX5_FPGA_IPSEC_SA_IP_ESP@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	orl	(%rbx), %ecx
	movl	%ecx, (%rbx)
	movq	_MLX5_ACCEL_ESP_ACTION_ENCRYPT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	4(%r14), %eax
	movq	_MLX5_FPGA_IPSEC_SA_DIR_SX@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%edx, %esi
	notl	%esi
	andl	%ecx, %esi
	orl	%edx, %ecx
	testl	%eax, %eax
	cmovel	%esi, %ecx
	movl	%ecx, (%rbx)
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED,4,2 ## @MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED
	.comm	_MLX5_FPGA_IPSEC_SA_ESN_EN,4,2  ## @MLX5_FPGA_IPSEC_SA_ESN_EN
	.comm	_MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP,4,2 ## @MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP
	.comm	_MLX5_FPGA_IPSEC_SA_ESN_OVERLAP,4,2 ## @MLX5_FPGA_IPSEC_SA_ESN_OVERLAP
	.comm	_MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128,4,2 ## @MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128
	.comm	_MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128,4,2 ## @MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128
	.comm	_MLX5_FPGA_IPSEC_SA_SA_VALID,4,2 ## @MLX5_FPGA_IPSEC_SA_SA_VALID
	.comm	_MLX5_FPGA_IPSEC_SA_SPI_EN,4,2  ## @MLX5_FPGA_IPSEC_SA_SPI_EN
	.comm	_MLX5_FPGA_IPSEC_SA_IP_ESP,4,2  ## @MLX5_FPGA_IPSEC_SA_IP_ESP
	.comm	_MLX5_ACCEL_ESP_ACTION_ENCRYPT,4,2 ## @MLX5_ACCEL_ESP_ACTION_ENCRYPT
	.comm	_MLX5_FPGA_IPSEC_SA_DIR_SX,4,2  ## @MLX5_FPGA_IPSEC_SA_DIR_SX
	.no_dead_strip	_mlx5_fpga_ipsec_build_hw_xfrm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlx5_fpga_ipsec_build_hw_xfrm
_mlx5_fpga_ipsec_build_hw_xfrm:         ; @mlx5_fpga_ipsec_build_hw_xfrm
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x20, x1
	add	x21, x2, #32
	ldr	x1, [x1, #32]
	ldr	w8, [x20, #16]
	add	w9, w8, #7
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w2, w8, #3
	mov	x0, x21
	bl	_memcpy
	ldr	w8, [x20, #16]
	cmp	w8, #128
	b.ne	LBB0_2
; %bb.1:
	ldr	x8, [x21]
	add	x0, x8, #128
	ldr	x1, [x20, #32]
	mov	w2, #16
	bl	_memcpy
LBB0_2:
	add	x21, x19, #16
	add	x0, x19, #24
	add	x1, x20, #24
	mov	w2, #4
	bl	_memcpy
	add	x1, x20, #20
	mov	x0, x21
	mov	w2, #4
	bl	_memcpy
Lloh0:
	adrp	x9, _MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED@GOTPAGEOFF]
	ldr	w8, [x20]
Lloh2:
	ldr	w10, [x9]
Lloh3:
	adrp	x9, _MLX5_FPGA_IPSEC_SA_ESN_EN@GOTPAGE
Lloh4:
	ldr	x9, [x9, _MLX5_FPGA_IPSEC_SA_ESN_EN@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	tst	w10, w8
	b.eq	LBB0_4
; %bb.3:
	ldr	w10, [x19]
	orr	w9, w10, w9
	str	w9, [x19]
Lloh6:
	adrp	x10, _MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP@GOTPAGE
Lloh7:
	ldr	x10, [x10, _MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP@GOTPAGEOFF]
Lloh8:
	ldr	w10, [x10]
Lloh9:
	adrp	x11, _MLX5_FPGA_IPSEC_SA_ESN_OVERLAP@GOTPAGE
Lloh10:
	ldr	x11, [x11, _MLX5_FPGA_IPSEC_SA_ESN_OVERLAP@GOTPAGEOFF]
Lloh11:
	ldr	w11, [x11]
	tst	w10, w8
	csel	w8, wzr, w11, eq
	orr	w8, w8, w9
	str	w8, [x19]
	ldr	w0, [x20, #12]
	bl	_htonl
	b	LBB0_5
LBB0_4:
	mov	x0, #0
	ldr	w10, [x19]
	bic	w9, w10, w9
	str	w9, [x19]
Lloh12:
	adrp	x10, _MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP@GOTPAGE
Lloh13:
	ldr	x10, [x10, _MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
Lloh15:
	adrp	x11, _MLX5_FPGA_IPSEC_SA_ESN_OVERLAP@GOTPAGE
Lloh16:
	ldr	x11, [x11, _MLX5_FPGA_IPSEC_SA_ESN_OVERLAP@GOTPAGEOFF]
	and	w8, w10, w8
Lloh17:
	ldr	w10, [x11]
	cmn	w8, #1
	csel	w8, wzr, w10, eq
	and	w8, w8, w9
	str	w8, [x19]
LBB0_5:
	str	x0, [x19, #40]
	ldr	w0, [x20, #8]
	bl	_htonl
	str	x0, [x19, #8]
	ldr	w8, [x20, #16]
	cmp	w8, #128
	b.eq	LBB0_8
; %bb.6:
	cmp	w8, #256
	b.ne	LBB0_10
; %bb.7:
Lloh18:
	adrp	x8, _MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128@GOTPAGEOFF]
	b	LBB0_9
LBB0_8:
Lloh20:
	adrp	x8, _MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128@GOTPAGEOFF]
LBB0_9:
	ldr	w8, [x8]
	str	w8, [x19, #4]
LBB0_10:
Lloh22:
	adrp	x8, _MLX5_FPGA_IPSEC_SA_SA_VALID@GOTPAGE
Lloh23:
	ldr	x8, [x8, _MLX5_FPGA_IPSEC_SA_SA_VALID@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
Lloh25:
	adrp	x9, _MLX5_FPGA_IPSEC_SA_SPI_EN@GOTPAGE
Lloh26:
	ldr	x9, [x9, _MLX5_FPGA_IPSEC_SA_SPI_EN@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
Lloh28:
	adrp	x10, _MLX5_FPGA_IPSEC_SA_IP_ESP@GOTPAGE
Lloh29:
	ldr	x10, [x10, _MLX5_FPGA_IPSEC_SA_IP_ESP@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh30:
	ldr	w9, [x10]
	orr	w8, w8, w9
	ldr	w9, [x19]
	orr	w8, w8, w9
	str	w8, [x19]
	ldr	w9, [x20, #4]
Lloh31:
	adrp	x10, _MLX5_ACCEL_ESP_ACTION_ENCRYPT@GOTPAGE
Lloh32:
	ldr	x10, [x10, _MLX5_ACCEL_ESP_ACTION_ENCRYPT@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
Lloh34:
	adrp	x11, _MLX5_FPGA_IPSEC_SA_DIR_SX@GOTPAGE
Lloh35:
	ldr	x11, [x11, _MLX5_FPGA_IPSEC_SA_DIR_SX@GOTPAGEOFF]
Lloh36:
	ldr	w11, [x11]
	bic	w12, w8, w11
	orr	w8, w11, w8
	tst	w10, w9
	csel	w8, w12, w8, eq
	str	w8, [x19]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED,4,2 ; @MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED
	.comm	_MLX5_FPGA_IPSEC_SA_ESN_EN,4,2  ; @MLX5_FPGA_IPSEC_SA_ESN_EN
	.comm	_MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP,4,2 ; @MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP
	.comm	_MLX5_FPGA_IPSEC_SA_ESN_OVERLAP,4,2 ; @MLX5_FPGA_IPSEC_SA_ESN_OVERLAP
	.comm	_MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128,4,2 ; @MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_128_AUTH_128
	.comm	_MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128,4,2 ; @MLX5_FPGA_IPSEC_SA_ENC_MODE_AES_GCM_256_AUTH_128
	.comm	_MLX5_FPGA_IPSEC_SA_SA_VALID,4,2 ; @MLX5_FPGA_IPSEC_SA_SA_VALID
	.comm	_MLX5_FPGA_IPSEC_SA_SPI_EN,4,2  ; @MLX5_FPGA_IPSEC_SA_SPI_EN
	.comm	_MLX5_FPGA_IPSEC_SA_IP_ESP,4,2  ; @MLX5_FPGA_IPSEC_SA_IP_ESP
	.comm	_MLX5_ACCEL_ESP_ACTION_ENCRYPT,4,2 ; @MLX5_ACCEL_ESP_ACTION_ENCRYPT
	.comm	_MLX5_FPGA_IPSEC_SA_DIR_SX,4,2  ; @MLX5_FPGA_IPSEC_SA_DIR_SX
	.no_dead_strip	_mlx5_fpga_ipsec_build_hw_xfrm
.subsections_via_symbols
