	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_pppoe_init
_mvpp2_prs_pppoe_init:                  ## @mvpp2_prs_pppoe_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_7
## %bb.1:
	leaq	-56(%rbp), %r13
	movq	%r13, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_PPPOE@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r13, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%r15d, -56(%rbp)
	movq	_PPP_IP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L3_IP4_OPT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	$4, %rsi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%rbx), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r13, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%r13, %rsi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %r13
	callq	_mvpp2_prs_hw_write
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %r15d
	testl	%eax, %eax
	js	LBB0_7
## %bb.2:
	movl	%r15d, -56(%rbp)
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MVPP2_PRS_IPV4_HEAD@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_IPV4_IHL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_MVPP2_PRS_IPV4_HEAD_MASK@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_IPV4_IHL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	leaq	-56(%rbp), %rbx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_tcam_data_byte_set
	movq	-48(%rbp), %rax
	movq	_MVPP2_PRS_SRAM_RI_WORD@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	$0, (%rax,%rcx,4)
	movq	_MVPP2_PRS_SRAM_RI_CTRL_WORD@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	$0, (%rax,%rcx,4)
	movq	_MVPP2_PRS_RI_L3_IP4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movl	-56(%rbp), %esi
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	_mvpp2_prs_hw_write
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_6
## %bb.3:
	movq	%r12, %r13
	leaq	-56(%rbp), %r12
	xorl	%r15d, %r15d
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_PPP_IPV6@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_match_etype
	movq	_MVPP2_PRS_LU_IP6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L3_IP6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rsi
	addq	$4, %rsi
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_shift_set
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%rbx), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	_mvpp2_prs_hw_write
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_6
## %bb.4:
	leaq	-56(%rbp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	$16, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_PPPOE@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r12, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -56(%rbp)
	movq	_MVPP2_PRS_RI_L3_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_ETH_TYPE_LEN@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r12, %rdi
	callq	_mvpp2_prs_sram_offset_set
	movl	-56(%rbp), %esi
	movl	(%r13), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	_mvpp2_prs_hw_write
	jmp	LBB0_7
LBB0_6:
	movl	%ebx, %r15d
LBB0_7:
	movl	%r15d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ## @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ## @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_PPPOE,4,2         ## @MVPP2_PRS_LU_PPPOE
	.comm	_PPP_IP,4,2                     ## @PPP_IP
	.comm	_MVPP2_PRS_LU_IP4,4,2           ## @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PRS_RI_L3_IP4_OPT,4,2    ## @MVPP2_PRS_RI_L3_IP4_OPT
	.comm	_MVPP2_PRS_RI_L3_PROTO_MASK,4,2 ## @MVPP2_PRS_RI_L3_PROTO_MASK
	.comm	_MVPP2_ETH_TYPE_LEN,8,3         ## @MVPP2_ETH_TYPE_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L3,4,2 ## @MVPP2_PRS_SRAM_UDF_TYPE_L3
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_PRS_IPV4_HEAD,4,2        ## @MVPP2_PRS_IPV4_HEAD
	.comm	_MVPP2_PRS_IPV4_IHL,4,2         ## @MVPP2_PRS_IPV4_IHL
	.comm	_MVPP2_PRS_IPV4_HEAD_MASK,4,2   ## @MVPP2_PRS_IPV4_HEAD_MASK
	.comm	_MVPP2_PRS_IPV4_IHL_MASK,4,2    ## @MVPP2_PRS_IPV4_IHL_MASK
	.comm	_MVPP2_PRS_SRAM_RI_WORD,8,3     ## @MVPP2_PRS_SRAM_RI_WORD
	.comm	_MVPP2_PRS_SRAM_RI_CTRL_WORD,8,3 ## @MVPP2_PRS_SRAM_RI_CTRL_WORD
	.comm	_MVPP2_PRS_RI_L3_IP4,4,2        ## @MVPP2_PRS_RI_L3_IP4
	.comm	_PPP_IPV6,4,2                   ## @PPP_IPV6
	.comm	_MVPP2_PRS_LU_IP6,4,2           ## @MVPP2_PRS_LU_IP6
	.comm	_MVPP2_PRS_RI_L3_IP6,4,2        ## @MVPP2_PRS_RI_L3_IP6
	.comm	_MVPP2_PRS_RI_L3_UN,4,2         ## @MVPP2_PRS_RI_L3_UN
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ## @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ## @MVPP2_PRS_SRAM_LU_GEN_BIT
	.no_dead_strip	_mvpp2_prs_pppoe_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_pppoe_init
_mvpp2_prs_pppoe_init:                  ; @mvpp2_prs_pppoe_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x22, _MVPP2_PE_FIRST_FREE_TID@GOTPAGE
Lloh1:
	ldr	x22, [x22, _MVPP2_PE_FIRST_FREE_TID@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh2:
	adrp	x23, _MVPP2_PE_LAST_FREE_TID@GOTPAGE
Lloh3:
	ldr	x23, [x23, _MVPP2_PE_LAST_FREE_TID@GOTPAGEOFF]
	ldr	w2, [x23]
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_5
; %bb.1:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
Lloh4:
	adrp	x21, _MVPP2_PRS_LU_PPPOE@GOTPAGE
Lloh5:
	ldr	x21, [x21, _MVPP2_PRS_LU_PPPOE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh6:
	adrp	x8, _PPP_IP@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PPP_IP@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
Lloh9:
	adrp	x8, _MVPP2_PRS_LU_IP4@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MVPP2_PRS_LU_IP4@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh12:
	adrp	x8, _MVPP2_PRS_RI_L3_IP4_OPT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_IP4_OPT@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x27, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGE
Lloh16:
	ldr	x27, [x27, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGEOFF]
	ldr	w2, [x27]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
Lloh17:
	adrp	x24, _MVPP2_ETH_TYPE_LEN@GOTPAGE
Lloh18:
	ldr	x24, [x24, _MVPP2_ETH_TYPE_LEN@GOTPAGEOFF]
	ldr	x8, [x24]
	add	x1, x8, #4
Lloh19:
	adrp	x28, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh20:
	ldr	x28, [x28, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
	ldr	w2, [x28]
	mov	x0, sp
	bl	_mvpp2_prs_sram_shift_set
Lloh21:
	adrp	x25, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGE
Lloh22:
	ldr	x25, [x25, _MVPP2_PRS_SRAM_UDF_TYPE_L3@GOTPAGEOFF]
	ldr	w1, [x25]
	ldr	x2, [x24]
Lloh23:
	adrp	x26, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGE
Lloh24:
	ldr	x26, [x26, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGEOFF]
	ldr	w3, [x26]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x22]
	ldr	w2, [x23]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_5
; %bb.2:
	str	w20, [sp]
	ldr	x1, [x24]
Lloh25:
	adrp	x8, _MVPP2_PRS_IPV4_HEAD@GOTPAGE
Lloh26:
	ldr	x8, [x8, _MVPP2_PRS_IPV4_HEAD@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
Lloh28:
	adrp	x9, _MVPP2_PRS_IPV4_IHL@GOTPAGE
Lloh29:
	ldr	x9, [x9, _MVPP2_PRS_IPV4_IHL@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	adrp	x10, _MVPP2_PRS_IPV4_HEAD_MASK@GOTPAGE
Lloh32:
	ldr	x10, [x10, _MVPP2_PRS_IPV4_HEAD_MASK@GOTPAGEOFF]
	orr	w2, w9, w8
Lloh33:
	ldr	w8, [x10]
Lloh34:
	adrp	x9, _MVPP2_PRS_IPV4_IHL_MASK@GOTPAGE
Lloh35:
	ldr	x9, [x9, _MVPP2_PRS_IPV4_IHL_MASK@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	orr	w3, w9, w8
	mov	x0, sp
	bl	_mvpp2_prs_tcam_data_byte_set
	ldr	x8, [sp, #8]
Lloh37:
	adrp	x9, _MVPP2_PRS_SRAM_RI_WORD@GOTPAGE
Lloh38:
	ldr	x9, [x9, _MVPP2_PRS_SRAM_RI_WORD@GOTPAGEOFF]
Lloh39:
	ldr	x9, [x9]
	str	wzr, [x8, x9, lsl #2]
Lloh40:
	adrp	x9, _MVPP2_PRS_SRAM_RI_CTRL_WORD@GOTPAGE
Lloh41:
	ldr	x9, [x9, _MVPP2_PRS_SRAM_RI_CTRL_WORD@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	str	wzr, [x8, x9, lsl #2]
Lloh43:
	adrp	x8, _MVPP2_PRS_RI_L3_IP4@GOTPAGE
Lloh44:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_IP4@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	ldr	w2, [x27]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x22]
	ldr	w2, [x23]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_5
; %bb.3:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh46:
	adrp	x8, _PPP_IPV6@GOTPAGE
Lloh47:
	ldr	x8, [x8, _PPP_IPV6@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	x0, sp
	mov	w1, #0
	bl	_mvpp2_prs_match_etype
Lloh49:
	adrp	x8, _MVPP2_PRS_LU_IP6@GOTPAGE
Lloh50:
	ldr	x8, [x8, _MVPP2_PRS_LU_IP6@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh52:
	adrp	x8, _MVPP2_PRS_RI_L3_IP6@GOTPAGE
Lloh53:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_IP6@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	ldr	w2, [x27]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
	ldr	x8, [x24]
	add	x1, x8, #4
	ldr	w2, [x28]
	mov	x0, sp
	bl	_mvpp2_prs_sram_shift_set
	ldr	w1, [x25]
	ldr	x2, [x24]
	ldr	w3, [x26]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	ldr	w1, [x22]
	ldr	w2, [x23]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_5
; %bb.4:
	mov	x0, sp
	mov	w1, #0
	mov	w2, #16
	bl	_memset
	ldr	w1, [x21]
	mov	x0, sp
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp]
Lloh55:
	adrp	x8, _MVPP2_PRS_RI_L3_UN@GOTPAGE
Lloh56:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_UN@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
	ldr	w2, [x27]
	mov	x0, sp
	bl	_mvpp2_prs_sram_ri_update
Lloh58:
	adrp	x8, _MVPP2_PRS_LU_FLOWS@GOTPAGE
Lloh59:
	ldr	x8, [x8, _MVPP2_PRS_LU_FLOWS@GOTPAGEOFF]
Lloh60:
	ldr	w1, [x8]
	mov	x0, sp
	bl	_mvpp2_prs_sram_next_lu_set
Lloh61:
	adrp	x8, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGE
Lloh62:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGEOFF]
Lloh63:
	ldr	w1, [x8]
	mov	x0, sp
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
	ldr	w1, [x25]
	ldr	x2, [x24]
	ldr	w3, [x26]
	mov	x0, sp
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [sp]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	mov	x1, sp
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	mov	w20, #0
LBB0_5:
	mov	x0, x20
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ; @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ; @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_PPPOE,4,2         ; @MVPP2_PRS_LU_PPPOE
	.comm	_PPP_IP,4,2                     ; @PPP_IP
	.comm	_MVPP2_PRS_LU_IP4,4,2           ; @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PRS_RI_L3_IP4_OPT,4,2    ; @MVPP2_PRS_RI_L3_IP4_OPT
	.comm	_MVPP2_PRS_RI_L3_PROTO_MASK,4,2 ; @MVPP2_PRS_RI_L3_PROTO_MASK
	.comm	_MVPP2_ETH_TYPE_LEN,8,3         ; @MVPP2_ETH_TYPE_LEN
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L3,4,2 ; @MVPP2_PRS_SRAM_UDF_TYPE_L3
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_PRS_IPV4_HEAD,4,2        ; @MVPP2_PRS_IPV4_HEAD
	.comm	_MVPP2_PRS_IPV4_IHL,4,2         ; @MVPP2_PRS_IPV4_IHL
	.comm	_MVPP2_PRS_IPV4_HEAD_MASK,4,2   ; @MVPP2_PRS_IPV4_HEAD_MASK
	.comm	_MVPP2_PRS_IPV4_IHL_MASK,4,2    ; @MVPP2_PRS_IPV4_IHL_MASK
	.comm	_MVPP2_PRS_SRAM_RI_WORD,8,3     ; @MVPP2_PRS_SRAM_RI_WORD
	.comm	_MVPP2_PRS_SRAM_RI_CTRL_WORD,8,3 ; @MVPP2_PRS_SRAM_RI_CTRL_WORD
	.comm	_MVPP2_PRS_RI_L3_IP4,4,2        ; @MVPP2_PRS_RI_L3_IP4
	.comm	_PPP_IPV6,4,2                   ; @PPP_IPV6
	.comm	_MVPP2_PRS_LU_IP6,4,2           ; @MVPP2_PRS_LU_IP6
	.comm	_MVPP2_PRS_RI_L3_IP6,4,2        ; @MVPP2_PRS_RI_L3_IP6
	.comm	_MVPP2_PRS_RI_L3_UN,4,2         ; @MVPP2_PRS_RI_L3_UN
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ; @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ; @MVPP2_PRS_SRAM_LU_GEN_BIT
	.no_dead_strip	_mvpp2_prs_pppoe_init
.subsections_via_symbols
