	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ks_pcie_setup_rc_app_regs
_ks_pcie_setup_rc_app_regs:             ## @ks_pcie_setup_rc_app_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %r12d
	movq	16(%rdi), %r15
	movq	(%r15), %rax
	movq	(%rax), %rbx
	movq	8(%rax), %r13
	callq	_ks_pcie_set_dbi_mode
	movq	_PCI_BASE_ADDRESS_0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCI_BASE_ADDRESS_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
	movq	%r14, %rdi
	callq	_ks_pcie_clear_dbi_mode
	cmpq	$0, 8(%r14)
	je	LBB0_1
## %bb.7:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movq	_OB_WIN_SIZE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	callq	_ilog2
	movq	_OB_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r14, -64(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_ks_pcie_app_writel
	testl	%r12d, %r12d
	jle	LBB0_6
## %bb.2:
	cmpq	-56(%rbp), %rbx                 ## 8-byte Folded Reload
	jge	LBB0_6
## %bb.3:
	movl	$1, %r13d
	movl	%r12d, -44(%rbp)                ## 4-byte Spill
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	leal	-1(%r13), %r15d
	movl	%r15d, %edi
	callq	_OB_OFFSET_INDEX
	movl	%eax, %r12d
	movq	%rbx, %rdi
	callq	_lower_32_bits
	movq	_OB_ENABLEN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	-44(%rbp), %r12d                ## 4-byte Reload
	movl	%eax, %edx
	callq	_ks_pcie_app_writel
	movl	%r15d, %edi
	callq	_OB_OFFSET_HI
	movl	%eax, %r15d
	movq	%rbx, %rdi
	callq	_upper_32_bits
	movq	%r14, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_ks_pcie_app_writel
	cmpl	%r12d, %r13d
	jge	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	movq	_OB_WIN_SIZE@GOTPCREL(%rip), %rax
	addq	(%rax), %rbx
	incl	%r13d
	cmpq	-56(%rbp), %rbx                 ## 8-byte Folded Reload
	jl	LBB0_4
LBB0_6:
	movq	_CMD_STATUS@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	-64(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_ks_pcie_app_readl
	movq	_OB_XLAT_EN_VAL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ks_pcie_app_writel             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_BASE_ADDRESS_0,4,2         ## @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_1,4,2         ## @PCI_BASE_ADDRESS_1
	.comm	_OB_WIN_SIZE,8,3                ## @OB_WIN_SIZE
	.comm	_OB_SIZE,4,2                    ## @OB_SIZE
	.comm	_OB_ENABLEN,4,2                 ## @OB_ENABLEN
	.comm	_CMD_STATUS,4,2                 ## @CMD_STATUS
	.comm	_OB_XLAT_EN_VAL,4,2             ## @OB_XLAT_EN_VAL
	.no_dead_strip	_ks_pcie_setup_rc_app_regs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ks_pcie_setup_rc_app_regs
_ks_pcie_setup_rc_app_regs:             ; @ks_pcie_setup_rc_app_regs
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w23, [x0]
	ldr	x21, [x0, #16]
	ldr	x8, [x21]
	ldp	x20, x24, [x8]
	bl	_ks_pcie_set_dbi_mode
Lloh0:
	adrp	x8, _PCI_BASE_ADDRESS_0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_0@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x21
	mov	w2, #0
	bl	_dw_pcie_writel_dbi
Lloh3:
	adrp	x8, _PCI_BASE_ADDRESS_1@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_1@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x21
	mov	w2, #0
	bl	_dw_pcie_writel_dbi
	mov	x0, x19
	bl	_ks_pcie_clear_dbi_mode
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
LBB0_2:
Lloh6:
	adrp	x25, _OB_WIN_SIZE@GOTPAGE
Lloh7:
	ldr	x25, [x25, _OB_WIN_SIZE@GOTPAGEOFF]
	ldr	x0, [x25]
	bl	_ilog2
	mov	x2, x0
Lloh8:
	adrp	x8, _OB_SIZE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _OB_SIZE@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_ks_pcie_app_writel
	cmp	w23, #1
	b.lt	LBB0_7
; %bb.3:
	cmp	x20, x24
	b.ge	LBB0_7
; %bb.4:
	mov	w26, #1
Lloh11:
	adrp	x27, _OB_ENABLEN@GOTPAGE
Lloh12:
	ldr	x27, [x27, _OB_ENABLEN@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	sub	w21, w26, #1
	mov	x0, x21
	bl	_OB_OFFSET_INDEX
	mov	x22, x0
	mov	x0, x20
	bl	_lower_32_bits
	ldr	w8, [x27]
	orr	w2, w8, w0
	mov	x0, x19
	mov	x1, x22
	bl	_ks_pcie_app_writel
	mov	x0, x21
	bl	_OB_OFFSET_HI
	mov	x21, x0
	mov	x0, x20
	bl	_upper_32_bits
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_ks_pcie_app_writel
	cmp	w26, w23
	b.ge	LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	ldr	x8, [x25]
	add	w26, w26, #1
	add	x20, x8, x20
	cmp	x20, x24
	b.lt	LBB0_5
LBB0_7:
Lloh13:
	adrp	x20, _CMD_STATUS@GOTPAGE
Lloh14:
	ldr	x20, [x20, _CMD_STATUS@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_ks_pcie_app_readl
Lloh15:
	adrp	x8, _OB_XLAT_EN_VAL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _OB_XLAT_EN_VAL@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_ks_pcie_app_writel
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_BASE_ADDRESS_0,4,2         ; @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_1,4,2         ; @PCI_BASE_ADDRESS_1
	.comm	_OB_WIN_SIZE,8,3                ; @OB_WIN_SIZE
	.comm	_OB_SIZE,4,2                    ; @OB_SIZE
	.comm	_OB_ENABLEN,4,2                 ; @OB_ENABLEN
	.comm	_CMD_STATUS,4,2                 ; @CMD_STATUS
	.comm	_OB_XLAT_EN_VAL,4,2             ; @OB_XLAT_EN_VAL
	.no_dead_strip	_ks_pcie_setup_rc_app_regs
.subsections_via_symbols
