	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath5k_hw_tweak_initval_settings
_ath5k_hw_tweak_initval_settings:       ## @ath5k_hw_tweak_initval_settings
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	(%rdi), %rax
	movq	_AR5K_AR5212@GOTPCREL(%rip), %r12
	cmpq	(%r12), %rax
	jne	LBB0_3
## %bb.1:
	movq	8(%r15), %rax
	movq	_AR5K_SREV_PHY_5212A@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_3
## %bb.2:
	movq	_AR5K_PHY_ADC_CTL_INBUFGAIN_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2, %edi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movq	_AR5K_PHY_ADC_CTL_INBUFGAIN_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2, %edi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movq	_AR5K_PHY_ADC_CTL_PWD_DAC_OFF@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_AR5K_PHY_ADC_CTL_PWD_ADC_OFF@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_AR5K_PHY_ADC_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ath5k_hw_reg_write
	movq	_AR5K_PHY_DAG_CCK_CTL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_AR5K_REG_DISABLE_BITS
	movl	(%rbx), %esi
	movq	_AR5K_PHY_DAG_CCK_CTL_RSSI_THR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_SEQ_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$15, %esi
	callq	_ath5k_hw_reg_write
LBB0_3:
	movq	8(%r15), %rax
	movq	_AR5K_SREV_PHY_5212B@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rcx
	cmpq	%rcx, %rax
	jl	LBB0_5
## %bb.4:
	movq	_AR5K_PHY_BLUETOOTH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_ath5k_hw_reg_write
	movq	8(%r15), %rax
	movq	(%rbx), %rcx
LBB0_5:
	cmpq	%rcx, %rax
	jle	LBB0_7
## %bb.6:
	movq	_AR5K_TXCFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_TXCFG_DCU_DBL_BUF_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_AR5K_REG_DISABLE_BITS
LBB0_7:
	movq	16(%r15), %rax
	movq	_AR5K_RF5413@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_10
## %bb.8:
	movq	_AR5K_RF2317@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_10
## %bb.9:
	movq	_AR5K_SREV_AR2417@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	sarl	$4, %eax
	cmpl	%eax, 24(%r15)
	jne	LBB0_12
LBB0_10:
	movl	(%r14), %eax
	cmpl	$2462, %eax                     ## imm = 0x99E
	setne	%cl
	cmpl	$2467, %eax                     ## imm = 0x9A3
	setne	%al
	andb	%cl, %al
	movzbl	%al, %ebx
	movq	_AR5K_PHY_FAST_ADC@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_ath5k_hw_reg_read
	cmpl	%ebx, %eax
	je	LBB0_12
## %bb.11:
	movl	(%r13), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ath5k_hw_reg_write
LBB0_12:
	movq	16(%r15), %rax
	movq	_AR5K_RF5112@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_15
## %bb.13:
	movq	32(%r15), %rax
	movq	_AR5K_SREV_RAD_5112A@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_15
## %bb.14:
	movq	_AR5K_PHY_CCKTXCTL_WORLD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_CCKTXCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_ath5k_hw_reg_write
	movq	8(%r14), %rax
	movq	_NL80211_BAND_5GHZ@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movl	$-4714464, %eax                 ## imm = 0xFFB81020
	movl	$-4715232, %esi                 ## imm = 0xFFB80D20
	cmovel	%eax, %esi
	movq	_AR5K_PHY_FRAME_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_ath5k_hw_reg_write
LBB0_15:
	movq	40(%r15), %rax
	movq	_AR5K_SREV_AR5211@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_17
## %bb.16:
	movq	_AR5K_QCUDCU_CLKGT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_ath5k_hw_reg_write
	movq	_AR5K_PHY_SCAL_32MHZ_5311@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_SCAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_ath5k_hw_reg_write
	movq	_AR5K_DIAG_SW_5211@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_DIAG_SW_ECO_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_AR5K_REG_ENABLE_BITS
LBB0_17:
	movq	48(%r15), %rax
	testq	%rax, %rax
	je	LBB0_26
## %bb.18:
	movq	_AR5K_BWMODE_40MHZ@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_23
## %bb.19:
	movq	_AR5K_PHY_SETTLING@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR5K_PHY_SETTLING_AGC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AR5K_AGC_SETTLING_TURBO@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	(%r15), %rax
	cmpq	(%r12), %rax
	jne	LBB0_21
## %bb.20:
	movl	(%rbx), %esi
	movq	_AR5K_PHY_SETTLING_SWITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_AR5K_SWITCH_SETTLING_TURBO@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	(%r15), %rax
LBB0_21:
	movq	_AR5K_AR5210@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_29
## %bb.22:
	movq	_AR5K_PHY_FRAME_CTL_INI@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_TURBO_MODE@GOTPCREL(%rip), %rax
	movq	_AR5K_PHY_TURBO_SHORT@GOTPCREL(%rip), %rcx
	orl	(%rax), %esi
	orl	(%rcx), %esi
	orl	$8224, %esi                     ## imm = 0x2020
	jmp	LBB0_28
LBB0_26:
	movq	(%r15), %rax
	movq	_AR5K_AR5210@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_29
## %bb.27:
	movq	_AR5K_PHY_FRAME_CTL_INI@GOTPCREL(%rip), %rax
	movl	$4128, %esi                     ## imm = 0x1020
	orl	(%rax), %esi
LBB0_28:
	movq	_AR5K_PHY_FRAME_CTL_5210@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath5k_hw_reg_write             ## TAILCALL
LBB0_23:
	movq	40(%r15), %rax
	movq	_AR5K_SREV_AR5424@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_29
## %bb.24:
	movq	_AR5K_SREV_AR5414@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jg	LBB0_29
## %bb.25:
	movq	_AR5K_PHY_FRAME_CTL_5211@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_FRAME_CTL_WIN_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$3, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_AR5K_REG_WRITE_BITS            ## TAILCALL
LBB0_29:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR5K_AR5212,8,3                ## @AR5K_AR5212
	.comm	_AR5K_SREV_PHY_5212A,8,3        ## @AR5K_SREV_PHY_5212A
	.comm	_AR5K_PHY_ADC_CTL_INBUFGAIN_OFF,4,2 ## @AR5K_PHY_ADC_CTL_INBUFGAIN_OFF
	.comm	_AR5K_PHY_ADC_CTL_INBUFGAIN_ON,4,2 ## @AR5K_PHY_ADC_CTL_INBUFGAIN_ON
	.comm	_AR5K_PHY_ADC_CTL_PWD_DAC_OFF,4,2 ## @AR5K_PHY_ADC_CTL_PWD_DAC_OFF
	.comm	_AR5K_PHY_ADC_CTL_PWD_ADC_OFF,4,2 ## @AR5K_PHY_ADC_CTL_PWD_ADC_OFF
	.comm	_AR5K_PHY_ADC_CTL,4,2           ## @AR5K_PHY_ADC_CTL
	.comm	_AR5K_PHY_DAG_CCK_CTL,4,2       ## @AR5K_PHY_DAG_CCK_CTL
	.comm	_AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR,4,2 ## @AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR
	.comm	_AR5K_PHY_DAG_CCK_CTL_RSSI_THR,4,2 ## @AR5K_PHY_DAG_CCK_CTL_RSSI_THR
	.comm	_AR5K_SEQ_MASK,4,2              ## @AR5K_SEQ_MASK
	.comm	_AR5K_SREV_PHY_5212B,8,3        ## @AR5K_SREV_PHY_5212B
	.comm	_AR5K_PHY_BLUETOOTH,4,2         ## @AR5K_PHY_BLUETOOTH
	.comm	_AR5K_TXCFG,4,2                 ## @AR5K_TXCFG
	.comm	_AR5K_TXCFG_DCU_DBL_BUF_DIS,4,2 ## @AR5K_TXCFG_DCU_DBL_BUF_DIS
	.comm	_AR5K_RF5413,8,3                ## @AR5K_RF5413
	.comm	_AR5K_RF2317,8,3                ## @AR5K_RF2317
	.comm	_AR5K_SREV_AR2417,4,2           ## @AR5K_SREV_AR2417
	.comm	_AR5K_PHY_FAST_ADC,4,2          ## @AR5K_PHY_FAST_ADC
	.comm	_AR5K_RF5112,8,3                ## @AR5K_RF5112
	.comm	_AR5K_SREV_RAD_5112A,8,3        ## @AR5K_SREV_RAD_5112A
	.comm	_AR5K_PHY_CCKTXCTL_WORLD,4,2    ## @AR5K_PHY_CCKTXCTL_WORLD
	.comm	_AR5K_PHY_CCKTXCTL,4,2          ## @AR5K_PHY_CCKTXCTL
	.comm	_NL80211_BAND_5GHZ,8,3          ## @NL80211_BAND_5GHZ
	.comm	_AR5K_PHY_FRAME_CTL,4,2         ## @AR5K_PHY_FRAME_CTL
	.comm	_AR5K_SREV_AR5211,8,3           ## @AR5K_SREV_AR5211
	.comm	_AR5K_QCUDCU_CLKGT,4,2          ## @AR5K_QCUDCU_CLKGT
	.comm	_AR5K_PHY_SCAL_32MHZ_5311,4,2   ## @AR5K_PHY_SCAL_32MHZ_5311
	.comm	_AR5K_PHY_SCAL,4,2              ## @AR5K_PHY_SCAL
	.comm	_AR5K_DIAG_SW_5211,4,2          ## @AR5K_DIAG_SW_5211
	.comm	_AR5K_DIAG_SW_ECO_ENABLE,4,2    ## @AR5K_DIAG_SW_ECO_ENABLE
	.comm	_AR5K_BWMODE_40MHZ,8,3          ## @AR5K_BWMODE_40MHZ
	.comm	_AR5K_PHY_SETTLING,4,2          ## @AR5K_PHY_SETTLING
	.comm	_AR5K_PHY_SETTLING_AGC,4,2      ## @AR5K_PHY_SETTLING_AGC
	.comm	_AR5K_AGC_SETTLING_TURBO,4,2    ## @AR5K_AGC_SETTLING_TURBO
	.comm	_AR5K_PHY_SETTLING_SWITCH,4,2   ## @AR5K_PHY_SETTLING_SWITCH
	.comm	_AR5K_SWITCH_SETTLING_TURBO,4,2 ## @AR5K_SWITCH_SETTLING_TURBO
	.comm	_AR5K_AR5210,8,3                ## @AR5K_AR5210
	.comm	_AR5K_PHY_FRAME_CTL_INI,4,2     ## @AR5K_PHY_FRAME_CTL_INI
	.comm	_AR5K_PHY_TURBO_MODE,4,2        ## @AR5K_PHY_TURBO_MODE
	.comm	_AR5K_PHY_TURBO_SHORT,4,2       ## @AR5K_PHY_TURBO_SHORT
	.comm	_AR5K_PHY_FRAME_CTL_5210,4,2    ## @AR5K_PHY_FRAME_CTL_5210
	.comm	_AR5K_SREV_AR5424,8,3           ## @AR5K_SREV_AR5424
	.comm	_AR5K_SREV_AR5414,8,3           ## @AR5K_SREV_AR5414
	.comm	_AR5K_PHY_FRAME_CTL_5211,4,2    ## @AR5K_PHY_FRAME_CTL_5211
	.comm	_AR5K_PHY_FRAME_CTL_WIN_LEN,4,2 ## @AR5K_PHY_FRAME_CTL_WIN_LEN
	.no_dead_strip	_ath5k_hw_tweak_initval_settings
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath5k_hw_tweak_initval_settings
_ath5k_hw_tweak_initval_settings:       ; @ath5k_hw_tweak_initval_settings
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x22, _AR5K_AR5212@GOTPAGE
Lloh1:
	ldr	x22, [x22, _AR5K_AR5212@GOTPAGEOFF]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_3
; %bb.1:
	ldr	x8, [x19, #8]
Lloh2:
	adrp	x9, _AR5K_SREV_PHY_5212A@GOTPAGE
Lloh3:
	ldr	x9, [x9, _AR5K_SREV_PHY_5212A@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_3
; %bb.2:
Lloh5:
	adrp	x8, _AR5K_PHY_ADC_CTL_INBUFGAIN_OFF@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AR5K_PHY_ADC_CTL_INBUFGAIN_OFF@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	w0, #2
	bl	_AR5K_REG_SM
	mov	x21, x0
Lloh8:
	adrp	x8, _AR5K_PHY_ADC_CTL_INBUFGAIN_ON@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AR5K_PHY_ADC_CTL_INBUFGAIN_ON@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	mov	w0, #2
	bl	_AR5K_REG_SM
	orr	w8, w0, w21
Lloh11:
	adrp	x9, _AR5K_PHY_ADC_CTL_PWD_DAC_OFF@GOTPAGE
Lloh12:
	ldr	x9, [x9, _AR5K_PHY_ADC_CTL_PWD_DAC_OFF@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
Lloh14:
	adrp	x10, _AR5K_PHY_ADC_CTL_PWD_ADC_OFF@GOTPAGE
Lloh15:
	ldr	x10, [x10, _AR5K_PHY_ADC_CTL_PWD_ADC_OFF@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh16:
	ldr	w9, [x10]
	orr	w1, w8, w9
Lloh17:
	adrp	x8, _AR5K_PHY_ADC_CTL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _AR5K_PHY_ADC_CTL@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ath5k_hw_reg_write
Lloh20:
	adrp	x21, _AR5K_PHY_DAG_CCK_CTL@GOTPAGE
Lloh21:
	ldr	x21, [x21, _AR5K_PHY_DAG_CCK_CTL@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh22:
	adrp	x8, _AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR@GOTPAGE
Lloh23:
	ldr	x8, [x8, _AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_AR5K_REG_DISABLE_BITS
	ldr	w1, [x21]
Lloh25:
	adrp	x8, _AR5K_PHY_DAG_CCK_CTL_RSSI_THR@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AR5K_PHY_DAG_CCK_CTL_RSSI_THR@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #2
	bl	_AR5K_REG_WRITE_BITS
Lloh28:
	adrp	x8, _AR5K_SEQ_MASK@GOTPAGE
Lloh29:
	ldr	x8, [x8, _AR5K_SEQ_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #15
	bl	_ath5k_hw_reg_write
LBB0_3:
	ldr	x8, [x19, #8]
Lloh31:
	adrp	x21, _AR5K_SREV_PHY_5212B@GOTPAGE
Lloh32:
	ldr	x21, [x21, _AR5K_SREV_PHY_5212B@GOTPAGEOFF]
	ldr	x9, [x21]
	cmp	x8, x9
	b.lt	LBB0_5
; %bb.4:
Lloh33:
	adrp	x8, _AR5K_PHY_BLUETOOTH@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AR5K_PHY_BLUETOOTH@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_ath5k_hw_reg_write
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
LBB0_5:
	cmp	x8, x9
	b.le	LBB0_7
; %bb.6:
Lloh36:
	adrp	x8, _AR5K_TXCFG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AR5K_TXCFG@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x8, _AR5K_TXCFG_DCU_DBL_BUF_DIS@GOTPAGE
Lloh40:
	ldr	x8, [x8, _AR5K_TXCFG_DCU_DBL_BUF_DIS@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_AR5K_REG_DISABLE_BITS
LBB0_7:
	ldr	x8, [x19, #16]
Lloh42:
	adrp	x9, _AR5K_RF5413@GOTPAGE
Lloh43:
	ldr	x9, [x9, _AR5K_RF5413@GOTPAGEOFF]
Lloh44:
	ldr	x9, [x9]
Lloh45:
	adrp	x10, _AR5K_RF2317@GOTPAGE
Lloh46:
	ldr	x10, [x10, _AR5K_RF2317@GOTPAGEOFF]
Lloh47:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.eq	LBB0_9
; %bb.8:
	ldr	w8, [x19, #24]
Lloh48:
	adrp	x9, _AR5K_SREV_AR2417@GOTPAGE
Lloh49:
	ldr	x9, [x9, _AR5K_SREV_AR2417@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	cmp	w8, w9, asr #4
	b.ne	LBB0_11
LBB0_9:
	ldr	w8, [x20]
	cmp	w8, #2462
	mov	w9, #2467
	ccmp	w8, w9, #4, ne
	cset	w21, ne
Lloh51:
	adrp	x23, _AR5K_PHY_FAST_ADC@GOTPAGE
Lloh52:
	ldr	x23, [x23, _AR5K_PHY_FAST_ADC@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_ath5k_hw_reg_read
	cmp	w0, w21
	b.eq	LBB0_11
; %bb.10:
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x21
	bl	_ath5k_hw_reg_write
LBB0_11:
	ldr	x8, [x19, #16]
Lloh53:
	adrp	x9, _AR5K_RF5112@GOTPAGE
Lloh54:
	ldr	x9, [x9, _AR5K_RF5112@GOTPAGEOFF]
Lloh55:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_14
; %bb.12:
	ldr	x8, [x19, #32]
Lloh56:
	adrp	x9, _AR5K_SREV_RAD_5112A@GOTPAGE
Lloh57:
	ldr	x9, [x9, _AR5K_SREV_RAD_5112A@GOTPAGEOFF]
Lloh58:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_14
; %bb.13:
Lloh59:
	adrp	x8, _AR5K_PHY_CCKTXCTL_WORLD@GOTPAGE
Lloh60:
	ldr	x8, [x8, _AR5K_PHY_CCKTXCTL_WORLD@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
Lloh62:
	adrp	x8, _AR5K_PHY_CCKTXCTL@GOTPAGE
Lloh63:
	ldr	x8, [x8, _AR5K_PHY_CCKTXCTL@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ath5k_hw_reg_write
	ldr	x8, [x20, #8]
Lloh65:
	adrp	x9, _NL80211_BAND_5GHZ@GOTPAGE
Lloh66:
	ldr	x9, [x9, _NL80211_BAND_5GHZ@GOTPAGEOFF]
Lloh67:
	ldr	x9, [x9]
	mov	w10, #3360
	movk	w10, #65464, lsl #16
	add	w11, w10, #768
	cmp	x8, x9
	csel	w1, w11, w10, eq
Lloh68:
	adrp	x8, _AR5K_PHY_FRAME_CTL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _AR5K_PHY_FRAME_CTL@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ath5k_hw_reg_write
LBB0_14:
	ldr	x8, [x19, #40]
Lloh71:
	adrp	x9, _AR5K_SREV_AR5211@GOTPAGE
Lloh72:
	ldr	x9, [x9, _AR5K_SREV_AR5211@GOTPAGEOFF]
Lloh73:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_16
; %bb.15:
Lloh74:
	adrp	x8, _AR5K_QCUDCU_CLKGT@GOTPAGE
Lloh75:
	ldr	x8, [x8, _AR5K_QCUDCU_CLKGT@GOTPAGEOFF]
Lloh76:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_ath5k_hw_reg_write
Lloh77:
	adrp	x8, _AR5K_PHY_SCAL_32MHZ_5311@GOTPAGE
Lloh78:
	ldr	x8, [x8, _AR5K_PHY_SCAL_32MHZ_5311@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
Lloh80:
	adrp	x8, _AR5K_PHY_SCAL@GOTPAGE
Lloh81:
	ldr	x8, [x8, _AR5K_PHY_SCAL@GOTPAGEOFF]
Lloh82:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ath5k_hw_reg_write
Lloh83:
	adrp	x8, _AR5K_DIAG_SW_5211@GOTPAGE
Lloh84:
	ldr	x8, [x8, _AR5K_DIAG_SW_5211@GOTPAGEOFF]
Lloh85:
	ldr	w1, [x8]
Lloh86:
	adrp	x8, _AR5K_DIAG_SW_ECO_ENABLE@GOTPAGE
Lloh87:
	ldr	x8, [x8, _AR5K_DIAG_SW_ECO_ENABLE@GOTPAGEOFF]
Lloh88:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_AR5K_REG_ENABLE_BITS
LBB0_16:
	ldr	x8, [x19, #48]
	cbz	x8, LBB0_22
; %bb.17:
Lloh89:
	adrp	x9, _AR5K_BWMODE_40MHZ@GOTPAGE
Lloh90:
	ldr	x9, [x9, _AR5K_BWMODE_40MHZ@GOTPAGEOFF]
Lloh91:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_25
; %bb.18:
Lloh92:
	adrp	x20, _AR5K_PHY_SETTLING@GOTPAGE
Lloh93:
	ldr	x20, [x20, _AR5K_PHY_SETTLING@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh94:
	adrp	x8, _AR5K_PHY_SETTLING_AGC@GOTPAGE
Lloh95:
	ldr	x8, [x8, _AR5K_PHY_SETTLING_AGC@GOTPAGEOFF]
Lloh96:
	ldr	w2, [x8]
Lloh97:
	adrp	x8, _AR5K_AGC_SETTLING_TURBO@GOTPAGE
Lloh98:
	ldr	x8, [x8, _AR5K_AGC_SETTLING_TURBO@GOTPAGEOFF]
Lloh99:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	x8, [x19]
	ldr	x9, [x22]
	cmp	x8, x9
	b.ne	LBB0_20
; %bb.19:
	ldr	w1, [x20]
Lloh100:
	adrp	x8, _AR5K_PHY_SETTLING_SWITCH@GOTPAGE
Lloh101:
	ldr	x8, [x8, _AR5K_PHY_SETTLING_SWITCH@GOTPAGEOFF]
Lloh102:
	ldr	w2, [x8]
Lloh103:
	adrp	x8, _AR5K_SWITCH_SETTLING_TURBO@GOTPAGE
Lloh104:
	ldr	x8, [x8, _AR5K_SWITCH_SETTLING_TURBO@GOTPAGEOFF]
Lloh105:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	x8, [x19]
LBB0_20:
Lloh106:
	adrp	x9, _AR5K_AR5210@GOTPAGE
Lloh107:
	ldr	x9, [x9, _AR5K_AR5210@GOTPAGEOFF]
Lloh108:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_28
; %bb.21:
Lloh109:
	adrp	x8, _AR5K_PHY_FRAME_CTL_INI@GOTPAGE
Lloh110:
	ldr	x8, [x8, _AR5K_PHY_FRAME_CTL_INI@GOTPAGEOFF]
Lloh111:
	ldr	w8, [x8]
Lloh112:
	adrp	x9, _AR5K_PHY_TURBO_MODE@GOTPAGE
Lloh113:
	ldr	x9, [x9, _AR5K_PHY_TURBO_MODE@GOTPAGEOFF]
Lloh114:
	adrp	x10, _AR5K_PHY_TURBO_SHORT@GOTPAGE
Lloh115:
	ldr	x10, [x10, _AR5K_PHY_TURBO_SHORT@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
Lloh117:
	ldr	w10, [x10]
	orr	w8, w8, w9
	orr	w8, w8, w10
	mov	w9, #8224
	b	LBB0_24
LBB0_22:
	ldr	x8, [x19]
Lloh118:
	adrp	x9, _AR5K_AR5210@GOTPAGE
Lloh119:
	ldr	x9, [x9, _AR5K_AR5210@GOTPAGEOFF]
Lloh120:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_28
; %bb.23:
Lloh121:
	adrp	x8, _AR5K_PHY_FRAME_CTL_INI@GOTPAGE
Lloh122:
	ldr	x8, [x8, _AR5K_PHY_FRAME_CTL_INI@GOTPAGEOFF]
Lloh123:
	ldr	w8, [x8]
	mov	w9, #4128
LBB0_24:
	orr	w1, w8, w9
Lloh124:
	adrp	x8, _AR5K_PHY_FRAME_CTL_5210@GOTPAGE
Lloh125:
	ldr	x8, [x8, _AR5K_PHY_FRAME_CTL_5210@GOTPAGEOFF]
Lloh126:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_ath5k_hw_reg_write
LBB0_25:
	ldr	x8, [x19, #40]
Lloh127:
	adrp	x9, _AR5K_SREV_AR5424@GOTPAGE
Lloh128:
	ldr	x9, [x9, _AR5K_SREV_AR5424@GOTPAGEOFF]
Lloh129:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_28
; %bb.26:
Lloh130:
	adrp	x9, _AR5K_SREV_AR5414@GOTPAGE
Lloh131:
	ldr	x9, [x9, _AR5K_SREV_AR5414@GOTPAGEOFF]
Lloh132:
	ldr	x9, [x9]
	cmp	x8, x9
	b.gt	LBB0_28
; %bb.27:
Lloh133:
	adrp	x8, _AR5K_PHY_FRAME_CTL_5211@GOTPAGE
Lloh134:
	ldr	x8, [x8, _AR5K_PHY_FRAME_CTL_5211@GOTPAGEOFF]
Lloh135:
	adrp	x9, _AR5K_PHY_FRAME_CTL_WIN_LEN@GOTPAGE
Lloh136:
	ldr	x9, [x9, _AR5K_PHY_FRAME_CTL_WIN_LEN@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
Lloh138:
	ldr	w2, [x9]
	mov	x0, x19
	mov	w3, #3
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_AR5K_REG_WRITE_BITS
LBB0_28:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh116
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh137
	.cfi_endproc
                                        ; -- End function
	.comm	_AR5K_AR5212,8,3                ; @AR5K_AR5212
	.comm	_AR5K_SREV_PHY_5212A,8,3        ; @AR5K_SREV_PHY_5212A
	.comm	_AR5K_PHY_ADC_CTL_INBUFGAIN_OFF,4,2 ; @AR5K_PHY_ADC_CTL_INBUFGAIN_OFF
	.comm	_AR5K_PHY_ADC_CTL_INBUFGAIN_ON,4,2 ; @AR5K_PHY_ADC_CTL_INBUFGAIN_ON
	.comm	_AR5K_PHY_ADC_CTL_PWD_DAC_OFF,4,2 ; @AR5K_PHY_ADC_CTL_PWD_DAC_OFF
	.comm	_AR5K_PHY_ADC_CTL_PWD_ADC_OFF,4,2 ; @AR5K_PHY_ADC_CTL_PWD_ADC_OFF
	.comm	_AR5K_PHY_ADC_CTL,4,2           ; @AR5K_PHY_ADC_CTL
	.comm	_AR5K_PHY_DAG_CCK_CTL,4,2       ; @AR5K_PHY_DAG_CCK_CTL
	.comm	_AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR,4,2 ; @AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR
	.comm	_AR5K_PHY_DAG_CCK_CTL_RSSI_THR,4,2 ; @AR5K_PHY_DAG_CCK_CTL_RSSI_THR
	.comm	_AR5K_SEQ_MASK,4,2              ; @AR5K_SEQ_MASK
	.comm	_AR5K_SREV_PHY_5212B,8,3        ; @AR5K_SREV_PHY_5212B
	.comm	_AR5K_PHY_BLUETOOTH,4,2         ; @AR5K_PHY_BLUETOOTH
	.comm	_AR5K_TXCFG,4,2                 ; @AR5K_TXCFG
	.comm	_AR5K_TXCFG_DCU_DBL_BUF_DIS,4,2 ; @AR5K_TXCFG_DCU_DBL_BUF_DIS
	.comm	_AR5K_RF5413,8,3                ; @AR5K_RF5413
	.comm	_AR5K_RF2317,8,3                ; @AR5K_RF2317
	.comm	_AR5K_SREV_AR2417,4,2           ; @AR5K_SREV_AR2417
	.comm	_AR5K_PHY_FAST_ADC,4,2          ; @AR5K_PHY_FAST_ADC
	.comm	_AR5K_RF5112,8,3                ; @AR5K_RF5112
	.comm	_AR5K_SREV_RAD_5112A,8,3        ; @AR5K_SREV_RAD_5112A
	.comm	_AR5K_PHY_CCKTXCTL_WORLD,4,2    ; @AR5K_PHY_CCKTXCTL_WORLD
	.comm	_AR5K_PHY_CCKTXCTL,4,2          ; @AR5K_PHY_CCKTXCTL
	.comm	_NL80211_BAND_5GHZ,8,3          ; @NL80211_BAND_5GHZ
	.comm	_AR5K_PHY_FRAME_CTL,4,2         ; @AR5K_PHY_FRAME_CTL
	.comm	_AR5K_SREV_AR5211,8,3           ; @AR5K_SREV_AR5211
	.comm	_AR5K_QCUDCU_CLKGT,4,2          ; @AR5K_QCUDCU_CLKGT
	.comm	_AR5K_PHY_SCAL_32MHZ_5311,4,2   ; @AR5K_PHY_SCAL_32MHZ_5311
	.comm	_AR5K_PHY_SCAL,4,2              ; @AR5K_PHY_SCAL
	.comm	_AR5K_DIAG_SW_5211,4,2          ; @AR5K_DIAG_SW_5211
	.comm	_AR5K_DIAG_SW_ECO_ENABLE,4,2    ; @AR5K_DIAG_SW_ECO_ENABLE
	.comm	_AR5K_BWMODE_40MHZ,8,3          ; @AR5K_BWMODE_40MHZ
	.comm	_AR5K_PHY_SETTLING,4,2          ; @AR5K_PHY_SETTLING
	.comm	_AR5K_PHY_SETTLING_AGC,4,2      ; @AR5K_PHY_SETTLING_AGC
	.comm	_AR5K_AGC_SETTLING_TURBO,4,2    ; @AR5K_AGC_SETTLING_TURBO
	.comm	_AR5K_PHY_SETTLING_SWITCH,4,2   ; @AR5K_PHY_SETTLING_SWITCH
	.comm	_AR5K_SWITCH_SETTLING_TURBO,4,2 ; @AR5K_SWITCH_SETTLING_TURBO
	.comm	_AR5K_AR5210,8,3                ; @AR5K_AR5210
	.comm	_AR5K_PHY_FRAME_CTL_INI,4,2     ; @AR5K_PHY_FRAME_CTL_INI
	.comm	_AR5K_PHY_TURBO_MODE,4,2        ; @AR5K_PHY_TURBO_MODE
	.comm	_AR5K_PHY_TURBO_SHORT,4,2       ; @AR5K_PHY_TURBO_SHORT
	.comm	_AR5K_PHY_FRAME_CTL_5210,4,2    ; @AR5K_PHY_FRAME_CTL_5210
	.comm	_AR5K_SREV_AR5424,8,3           ; @AR5K_SREV_AR5424
	.comm	_AR5K_SREV_AR5414,8,3           ; @AR5K_SREV_AR5414
	.comm	_AR5K_PHY_FRAME_CTL_5211,4,2    ; @AR5K_PHY_FRAME_CTL_5211
	.comm	_AR5K_PHY_FRAME_CTL_WIN_LEN,4,2 ; @AR5K_PHY_FRAME_CTL_WIN_LEN
	.no_dead_strip	_ath5k_hw_tweak_initval_settings
.subsections_via_symbols
