	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_tx_start              ## -- Begin function iwl_pcie_tx_start
	.p2align	4, 0x90
_iwl_pcie_tx_start:                     ## @iwl_pcie_tx_start
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rdi, %r13
	callq	_IWL_TRANS_GET_PCIE_TRANS
	movq	%rax, %r14
	movq	(%r13), %rax
	movq	8(%rax), %rax
	movl	(%rax), %edi
	callq	_SCD_TRANS_TBL_OFFSET_QUEUE
	movl	%eax, %r15d
	movq	_SCD_CONTEXT_MEM_LOWER_BOUND@GOTPCREL(%rip), %rbx
	subl	(%rbx), %r15d
	sarl	$3, %r15d
	movl	28(%r14), %edi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movl	24(%r14), %edi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_SCD_SRAM_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_iwl_read_prph
	movq	%rax, (%r14)
	testq	%r12, %r12
	setne	%cl
	cmpq	%r12, %rax
	setne	%al
	andb	%cl, %al
	movzbl	%al, %edi
	callq	_WARN_ON
	movl	(%rbx), %esi
	addl	(%r14), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	movl	%r15d, %ecx
	callq	_iwl_trans_write_mem
	movq	_SCD_DRAM_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	20(%r14), %edx
	sarl	$10, %edx
	movq	%r13, %rdi
	callq	_iwl_write_prph
	movq	(%r13), %rax
	movq	8(%rax), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_2
## %bb.1:
	movq	_SCD_CHAINEXT_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	xorl	%edx, %edx
	callq	_iwl_write_prph
LBB0_2:
	movl	16(%r14), %esi
	movl	8(%r14), %ecx
	movl	12(%r14), %edx
	movq	%r13, %rdi
	callq	_iwl_trans_ac_txq_enable
	movq	%r13, %rdi
	callq	_iwl_scd_activate_fifos
	movq	_FH_TCSR_CHNL_NUM@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_5
## %bb.3:
	xorl	%ebx, %ebx
	movq	_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPCREL(%rip), %r15
	movq	_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	_FH_TCSR_CHNL_TX_CONFIG_REG
	movq	(%r12), %rdx
	orq	(%r15), %rdx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_iwl_write_direct32
	incl	%ebx
	cmpl	(%r14), %ebx
	jl	LBB0_4
LBB0_5:
	movq	_FH_TX_CHICKEN_BITS_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_iwl_read_direct32
	movl	(%rbx), %esi
	movq	_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN@GOTPCREL(%rip), %rcx
	orq	(%rcx), %rax
	movq	%r13, %rdi
	movq	%rax, %rdx
	callq	_iwl_write_direct32
	movq	(%r13), %rax
	movq	(%rax), %rax
	movq	_IWL_DEVICE_FAMILY_8000@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_6
## %bb.7:
	movq	_APMG_PCIDEV_STT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_iwl_clear_bits_prph            ## TAILCALL
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SCD_CONTEXT_MEM_LOWER_BOUND,4,2 ## @SCD_CONTEXT_MEM_LOWER_BOUND
	.comm	_SCD_SRAM_BASE_ADDR,4,2         ## @SCD_SRAM_BASE_ADDR
	.comm	_SCD_DRAM_BASE_ADDR,4,2         ## @SCD_DRAM_BASE_ADDR
	.comm	_SCD_CHAINEXT_EN,4,2            ## @SCD_CHAINEXT_EN
	.comm	_FH_TCSR_CHNL_NUM,4,2           ## @FH_TCSR_CHNL_NUM
	.comm	_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE,8,3 ## @FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
	.comm	_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE,8,3 ## @FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
	.comm	_FH_TX_CHICKEN_BITS_REG,4,2     ## @FH_TX_CHICKEN_BITS_REG
	.comm	_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN,8,3 ## @FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
	.comm	_IWL_DEVICE_FAMILY_8000,8,3     ## @IWL_DEVICE_FAMILY_8000
	.comm	_APMG_PCIDEV_STT_REG,4,2        ## @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS,4,2 ## @APMG_PCIDEV_STT_VAL_L1_ACT_DIS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_tx_start              ; -- Begin function iwl_pcie_tx_start
	.p2align	2
_iwl_pcie_tx_start:                     ; @iwl_pcie_tx_start
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x1
	mov	x19, x0
	bl	_IWL_TRANS_GET_PCIE_TRANS
	mov	x20, x0
	ldr	x8, [x19]
	ldr	x8, [x8, #8]
	ldr	w0, [x8]
	bl	_SCD_TRANS_TBL_OFFSET_QUEUE
Lloh0:
	adrp	x23, _SCD_CONTEXT_MEM_LOWER_BOUND@GOTPAGE
Lloh1:
	ldr	x23, [x23, _SCD_CONTEXT_MEM_LOWER_BOUND@GOTPAGEOFF]
	ldr	w8, [x23]
	sub	w8, w0, w8
	asr	w22, w8, #3
	ldr	w0, [x20, #28]
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	w0, [x20, #24]
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh2:
	adrp	x8, _SCD_SRAM_BASE_ADDR@GOTPAGE
Lloh3:
	ldr	x8, [x8, _SCD_SRAM_BASE_ADDR@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_iwl_read_prph
	str	x0, [x20]
	cmp	x21, #0
	ccmp	x0, x21, #4, ne
	cset	w0, ne
	bl	_WARN_ON
	ldr	w8, [x20]
	ldr	w9, [x23]
	add	w1, w9, w8
	mov	x0, x19
	mov	x2, #0
	mov	x3, x22
	bl	_iwl_trans_write_mem
Lloh5:
	adrp	x8, _SCD_DRAM_BASE_ADDR@GOTPAGE
Lloh6:
	ldr	x8, [x8, _SCD_DRAM_BASE_ADDR@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	ldr	w8, [x20, #20]
	asr	w2, w8, #10
	mov	x0, x19
	bl	_iwl_write_prph
	ldr	x8, [x19]
	ldr	x8, [x8, #8]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_2
; %bb.1:
Lloh8:
	adrp	x8, _SCD_CHAINEXT_EN@GOTPAGE
Lloh9:
	ldr	x8, [x8, _SCD_CHAINEXT_EN@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_iwl_write_prph
LBB0_2:
	ldp	w2, w1, [x20, #12]
	ldr	w3, [x20, #8]
	mov	x0, x19
	bl	_iwl_trans_ac_txq_enable
	mov	x0, x19
	bl	_iwl_scd_activate_fifos
Lloh11:
	adrp	x21, _FH_TCSR_CHNL_NUM@GOTPAGE
Lloh12:
	ldr	x21, [x21, _FH_TCSR_CHNL_NUM@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.3:
	mov	w20, #0
Lloh13:
	adrp	x22, _FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPAGE
Lloh14:
	ldr	x22, [x22, _FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPAGEOFF]
Lloh15:
	adrp	x23, _FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE@GOTPAGE
Lloh16:
	ldr	x23, [x23, _FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	bl	_FH_TCSR_CHNL_TX_CONFIG_REG
	mov	x1, x0
	ldr	x8, [x22]
	ldr	x9, [x23]
	orr	x2, x9, x8
	mov	x0, x19
	bl	_iwl_write_direct32
	add	w20, w20, #1
	ldr	w8, [x21]
	cmp	w20, w8
	b.lt	LBB0_4
LBB0_5:
Lloh17:
	adrp	x20, _FH_TX_CHICKEN_BITS_REG@GOTPAGE
Lloh18:
	ldr	x20, [x20, _FH_TX_CHICKEN_BITS_REG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_iwl_read_direct32
	ldr	w1, [x20]
Lloh19:
	adrp	x8, _FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN@GOTPAGE
Lloh20:
	ldr	x8, [x8, _FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN@GOTPAGEOFF]
Lloh21:
	ldr	x8, [x8]
	orr	x2, x8, x0
	mov	x0, x19
	bl	_iwl_write_direct32
	ldr	x8, [x19]
	ldr	x8, [x8]
Lloh22:
	adrp	x9, _IWL_DEVICE_FAMILY_8000@GOTPAGE
Lloh23:
	ldr	x9, [x9, _IWL_DEVICE_FAMILY_8000@GOTPAGEOFF]
Lloh24:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_7
; %bb.6:
Lloh25:
	adrp	x8, _APMG_PCIDEV_STT_REG@GOTPAGE
Lloh26:
	ldr	x8, [x8, _APMG_PCIDEV_STT_REG@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
Lloh28:
	adrp	x8, _APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPAGE
Lloh29:
	ldr	x8, [x8, _APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_iwl_clear_bits_prph
LBB0_7:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.cfi_endproc
                                        ; -- End function
	.comm	_SCD_CONTEXT_MEM_LOWER_BOUND,4,2 ; @SCD_CONTEXT_MEM_LOWER_BOUND
	.comm	_SCD_SRAM_BASE_ADDR,4,2         ; @SCD_SRAM_BASE_ADDR
	.comm	_SCD_DRAM_BASE_ADDR,4,2         ; @SCD_DRAM_BASE_ADDR
	.comm	_SCD_CHAINEXT_EN,4,2            ; @SCD_CHAINEXT_EN
	.comm	_FH_TCSR_CHNL_NUM,4,2           ; @FH_TCSR_CHNL_NUM
	.comm	_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE,8,3 ; @FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
	.comm	_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE,8,3 ; @FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
	.comm	_FH_TX_CHICKEN_BITS_REG,4,2     ; @FH_TX_CHICKEN_BITS_REG
	.comm	_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN,8,3 ; @FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
	.comm	_IWL_DEVICE_FAMILY_8000,8,3     ; @IWL_DEVICE_FAMILY_8000
	.comm	_APMG_PCIDEV_STT_REG,4,2        ; @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS,4,2 ; @APMG_PCIDEV_STT_VAL_L1_ACT_DIS
.subsections_via_symbols
