	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rockchip_pcie_prog_ob_atu
_rockchip_pcie_prog_ob_atu:             ## @rockchip_pcie_prog_ob_atu
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %eax
	movq	_MAX_AXI_WRAPPER_REGION_NUM@GOTPCREL(%rip), %rcx
	cmpl	%esi, (%rcx)
	jle	LBB0_1
## %bb.2:
	cmpl	$6, %eax
	jle	LBB0_1
## %bb.3:
	cmpl	$64, %eax
	jae	LBB0_1
## %bb.4:
	movl	%r9d, %r15d
	movl	%edx, %ebx
	movq	%rdi, %r14
	movl	$2, %edx
	movl	%eax, %ecx
	shlq	%cl, %rdx
	testl	%esi, %esi
	je	LBB0_5
## %bb.9:
	movq	_AXI_REGION_SIZE@GOTPCREL(%rip), %rcx
	cmpq	%rdx, (%rcx)
	jae	LBB0_7
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_8:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_5:
	movq	_AXI_REGION_0_SIZE@GOTPCREL(%rip), %rcx
	cmpq	%rdx, (%rcx)
	jb	LBB0_1
LBB0_7:
	movq	_OB_REG_SIZE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r8d
	orl	%eax, %r8d
	orl	$8388608, %ebx                  ## imm = 0x800000
	movq	_PCIE_CORE_OB_REGION_ADDR0@GOTPCREL(%rip), %rax
	movslq	%esi, %r12
	movq	(%rax), %rdx
	addq	%r12, %rdx
	movq	%r14, %rdi
	movl	%r8d, %esi
	callq	_rockchip_pcie_write
	movq	_PCIE_CORE_OB_REGION_ADDR1@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	%r12, %rdx
	movq	%r14, %rdi
	movl	%r15d, %esi
	callq	_rockchip_pcie_write
	movq	_PCIE_CORE_OB_REGION_DESC0@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	%r12, %rdx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_rockchip_pcie_write
	movq	_PCIE_CORE_OB_REGION_DESC1@GOTPCREL(%rip), %rax
	addq	(%rax), %r12
	xorl	%ebx, %ebx
	movq	%r14, %rdi
	xorl	%esi, %esi
	movq	%r12, %rdx
	callq	_rockchip_pcie_write
	jmp	LBB0_8
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX_AXI_WRAPPER_REGION_NUM,4,2 ## @MAX_AXI_WRAPPER_REGION_NUM
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_AXI_REGION_0_SIZE,8,3          ## @AXI_REGION_0_SIZE
	.comm	_AXI_REGION_SIZE,8,3            ## @AXI_REGION_SIZE
	.comm	_OB_REG_SIZE_SHIFT,4,2          ## @OB_REG_SIZE_SHIFT
	.comm	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS,4,2 ## @PCIE_CORE_OB_REGION_ADDR0_NUM_BITS
	.comm	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR,4,2 ## @PCIE_CORE_OB_REGION_ADDR0_LO_ADDR
	.comm	_PCIE_CORE_OB_REGION_ADDR0,8,3  ## @PCIE_CORE_OB_REGION_ADDR0
	.comm	_PCIE_CORE_OB_REGION_ADDR1,8,3  ## @PCIE_CORE_OB_REGION_ADDR1
	.comm	_PCIE_CORE_OB_REGION_DESC0,8,3  ## @PCIE_CORE_OB_REGION_DESC0
	.comm	_PCIE_CORE_OB_REGION_DESC1,8,3  ## @PCIE_CORE_OB_REGION_DESC1
	.no_dead_strip	_rockchip_pcie_prog_ob_atu
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rockchip_pcie_prog_ob_atu
_rockchip_pcie_prog_ob_atu:             ; @rockchip_pcie_prog_ob_atu
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
                                        ; kill: def $w3 killed $w3 def $x3
Lloh0:
	adrp	x8, _MAX_AXI_WRAPPER_REGION_NUM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MAX_AXI_WRAPPER_REGION_NUM@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, w1
	b.le	LBB0_7
; %bb.1:
	cmp	w3, #6
	b.le	LBB0_7
; %bb.2:
	cmp	w3, #64
	b.hs	LBB0_7
; %bb.3:
	mov	x20, x5
	mov	x19, x0
	cbz	w1, LBB0_5
; %bb.4:
Lloh3:
	adrp	x8, _AXI_REGION_SIZE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AXI_REGION_SIZE@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh5:
	adrp	x8, _AXI_REGION_0_SIZE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AXI_REGION_0_SIZE@GOTPAGEOFF]
LBB0_6:
	ldr	x8, [x8]
	mov	w9, #2
	lsl	x9, x9, x3
	cmp	x8, x9
	b.hs	LBB0_9
LBB0_7:
Lloh7:
	adrp	x8, _EINVAL@GOTPAGE
Lloh8:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_8:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_9:
Lloh10:
	adrp	x8, _OB_REG_SIZE_SHIFT@GOTPAGE
Lloh11:
	ldr	x8, [x8, _OB_REG_SIZE_SHIFT@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	lsl	w8, w1, w8
Lloh13:
	adrp	x9, _PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPAGE
Lloh14:
	ldr	x9, [x9, _PCIE_CORE_OB_REGION_ADDR0_NUM_BITS@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	and	w9, w9, w3
Lloh16:
	adrp	x10, _PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPAGE
Lloh17:
	ldr	x10, [x10, _PCIE_CORE_OB_REGION_ADDR0_LO_ADDR@GOTPAGEOFF]
Lloh18:
	ldr	w10, [x10]
	and	w10, w10, w4
	orr	w1, w10, w9
	orr	w21, w2, #0x800000
Lloh19:
	adrp	x9, _PCIE_CORE_OB_REGION_ADDR0@GOTPAGE
Lloh20:
	ldr	x9, [x9, _PCIE_CORE_OB_REGION_ADDR0@GOTPAGEOFF]
Lloh21:
	ldr	x9, [x9]
	sxtw	x22, w8
	add	x2, x9, x22
	mov	x0, x19
	bl	_rockchip_pcie_write
Lloh22:
	adrp	x8, _PCIE_CORE_OB_REGION_ADDR1@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_ADDR1@GOTPAGEOFF]
Lloh24:
	ldr	x8, [x8]
	add	x2, x8, x22
	mov	x0, x19
	mov	x1, x20
	bl	_rockchip_pcie_write
Lloh25:
	adrp	x8, _PCIE_CORE_OB_REGION_DESC0@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_DESC0@GOTPAGEOFF]
Lloh27:
	ldr	x8, [x8]
	add	x2, x8, x22
	mov	x0, x19
	mov	x1, x21
	bl	_rockchip_pcie_write
Lloh28:
	adrp	x8, _PCIE_CORE_OB_REGION_DESC1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PCIE_CORE_OB_REGION_DESC1@GOTPAGEOFF]
Lloh30:
	ldr	x8, [x8]
	add	x2, x8, x22
	mov	x0, x19
	mov	w1, #0
	bl	_rockchip_pcie_write
	mov	w0, #0
	b	LBB0_8
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX_AXI_WRAPPER_REGION_NUM,4,2 ; @MAX_AXI_WRAPPER_REGION_NUM
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_AXI_REGION_0_SIZE,8,3          ; @AXI_REGION_0_SIZE
	.comm	_AXI_REGION_SIZE,8,3            ; @AXI_REGION_SIZE
	.comm	_OB_REG_SIZE_SHIFT,4,2          ; @OB_REG_SIZE_SHIFT
	.comm	_PCIE_CORE_OB_REGION_ADDR0_NUM_BITS,4,2 ; @PCIE_CORE_OB_REGION_ADDR0_NUM_BITS
	.comm	_PCIE_CORE_OB_REGION_ADDR0_LO_ADDR,4,2 ; @PCIE_CORE_OB_REGION_ADDR0_LO_ADDR
	.comm	_PCIE_CORE_OB_REGION_ADDR0,8,3  ; @PCIE_CORE_OB_REGION_ADDR0
	.comm	_PCIE_CORE_OB_REGION_ADDR1,8,3  ; @PCIE_CORE_OB_REGION_ADDR1
	.comm	_PCIE_CORE_OB_REGION_DESC0,8,3  ; @PCIE_CORE_OB_REGION_DESC0
	.comm	_PCIE_CORE_OB_REGION_DESC1,8,3  ; @PCIE_CORE_OB_REGION_DESC1
	.no_dead_strip	_rockchip_pcie_prog_ob_atu
.subsections_via_symbols
