	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_il3945_hw_tx_queue_init        ## -- Begin function il3945_hw_tx_queue_init
	.p2align	4, 0x90
_il3945_hw_tx_queue_init:               ## @il3945_hw_tx_queue_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movslq	(%rsi), %rbx
	movq	(%rdi), %r15
	movl	8(%rsi), %edi
	callq	_cpu_to_le32
	movq	(%r15), %rcx
	movl	%eax, (%rcx,%rbx,4)
	movl	%ebx, %edi
	callq	_FH39_CBCC_CTRL
	movq	%r14, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_il_wr
	movl	%ebx, %edi
	callq	_FH39_CBCC_BASE
	movq	%r14, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_il_wr
	movl	%ebx, %edi
	callq	_FH39_TCSR_CONFIG
	movq	_FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT@GOTPCREL(%rip), %rcx
	movq	_FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_il_wr
	movq	_FH39_TSSR_CBB_BASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	__il_rd
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT,4,2 ## @FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF,4,2 ## @FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD,4,2 ## @FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL,4,2 ## @FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE,4,2 ## @FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
	.comm	_FH39_TSSR_CBB_BASE,4,2         ## @FH39_TSSR_CBB_BASE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_il3945_hw_tx_queue_init        ; -- Begin function il3945_hw_tx_queue_init
	.p2align	2
_il3945_hw_tx_queue_init:               ; @il3945_hw_tx_queue_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldrsw	x20, [x1]
	ldr	x21, [x0]
	ldr	w0, [x1, #8]
	bl	_cpu_to_le32
	ldr	x8, [x21]
	str	w0, [x8, x20, lsl #2]
	mov	x0, x20
	bl	_FH39_CBCC_CTRL
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_il_wr
	mov	x0, x20
	bl	_FH39_CBCC_BASE
	mov	x1, x0
	mov	x0, x19
	mov	w2, #0
	bl	_il_wr
	mov	x0, x20
	bl	_FH39_TCSR_CONFIG
	mov	x1, x0
Lloh0:
	adrp	x8, _FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF@GOTPAGE
Lloh4:
	ldr	x9, [x9, _FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD@GOTPAGE
Lloh7:
	ldr	x9, [x9, _FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL@GOTPAGE
Lloh10:
	ldr	x9, [x9, _FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPAGE
Lloh13:
	ldr	x9, [x9, _FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_il_wr
Lloh15:
	adrp	x8, _FH39_TSSR_CBB_BASE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _FH39_TSSR_CBB_BASE@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	__il_rd
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT,4,2 ; @FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF,4,2 ; @FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD,4,2 ; @FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL,4,2 ; @FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
	.comm	_FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE,4,2 ; @FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
	.comm	_FH39_TSSR_CBB_BASE,4,2         ; @FH39_TSSR_CBB_BASE
.subsections_via_symbols
