	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_qed_mcp_trans_speed_mask       ## -- Begin function qed_mcp_trans_speed_mask
	.p2align	4, 0x90
_qed_mcp_trans_speed_mask:              ## @qed_mcp_trans_speed_mask
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdx, %r14
	movq	%rdi, %rbx
	leaq	-24(%rbp), %rdx
	leaq	-20(%rbp), %rcx
	callq	_qed_mcp_get_transceiver_data
	testl	%eax, %eax
	jne	LBB0_23
## %bb.1:
	movl	-24(%rbp), %edi
	movl	-20(%rbp), %esi
	callq	_qed_is_transceiver_ready
	testl	%eax, %eax
	je	LBB0_2
## %bb.3:
	movl	-20(%rbp), %edx
	leal	-128(%rdx), %eax
	cmpl	$39, %eax
	ja	LBB0_21
## %bb.4:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_7:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_2:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_23
LBB0_12:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_5:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rax
LBB0_6:
	movl	(%rax), %eax
	movl	%eax, (%r14)
	jmp	LBB0_22
LBB0_11:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPCREL(%rip), %rax
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rcx
	jmp	LBB0_9
LBB0_8:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rax
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rcx
	jmp	LBB0_9
LBB0_13:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_18:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPCREL(%rip), %rax
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_17:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPCREL(%rip), %rax
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rax
	jmp	LBB0_15
LBB0_16:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rax
LBB0_14:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_15:
	orl	(%rax), %ecx
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_21:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_DP_INFO
	movl	$255, (%r14)
	jmp	LBB0_22
LBB0_19:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_20:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rax
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rcx
LBB0_9:
	movl	(%rcx), %ecx
LBB0_10:
	orl	(%rax), %ecx
	movl	%ecx, (%r14)
LBB0_22:
	xorl	%eax, %eax
LBB0_23:
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_18, LBB0_18-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_16, LBB0_16-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
LJTI0_0:
	.long	L0_0_set_19
	.long	L0_0_set_18
	.long	L0_0_set_18
	.long	L0_0_set_17
	.long	L0_0_set_18
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_16
	.long	L0_0_set_13
	.long	L0_0_set_7
	.long	L0_0_set_8
	.long	L0_0_set_8
	.long	L0_0_set_16
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_13
	.long	L0_0_set_13
	.long	L0_0_set_13
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_12
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_5
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_7
	.long	L0_0_set_20
	.long	L0_0_set_7
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_17
	.long	L0_0_set_11
	.long	L0_0_set_11
	.long	L0_0_set_5
	.end_data_region
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unknown transceiver type 0x%x\n"

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_qed_mcp_trans_speed_mask       ; -- Begin function qed_mcp_trans_speed_mask
	.p2align	2
_qed_mcp_trans_speed_mask:              ; @qed_mcp_trans_speed_mask
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x2
	mov	x20, x0
	add	x2, sp, #8
	add	x3, sp, #12
	bl	_qed_mcp_get_transceiver_data
	cbnz	w0, LBB0_22
; %bb.1:
	ldp	w0, w1, [sp, #8]
	bl	_qed_is_transceiver_ready
	cbz	w0, LBB0_5
; %bb.2:
	ldr	w2, [sp, #12]
	sub	w8, w2, #128
	cmp	w8, #39
	b.hi	LBB0_17
; %bb.3:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_4
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_4:
	mov	w0, #0
Lloh2:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh3:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	b	LBB0_21
LBB0_5:
Lloh5:
	adrp	x8, _EINVAL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_22
LBB0_6:
	mov	w0, #0
Lloh8:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh9:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	b	LBB0_21
LBB0_7:
	mov	w0, #0
Lloh11:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh12:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	b	LBB0_21
LBB0_8:
	mov	w0, #0
Lloh14:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGE
Lloh15:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh18:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
	b	LBB0_20
LBB0_9:
	mov	w0, #0
Lloh19:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh20:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh23:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
	b	LBB0_20
LBB0_10:
	mov	w0, #0
Lloh24:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh25:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
	b	LBB0_14
LBB0_11:
	mov	w0, #0
Lloh26:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGE
Lloh27:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGEOFF]
Lloh28:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh29:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh32:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh33:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh36:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
	b	LBB0_16
LBB0_12:
	mov	w0, #0
Lloh37:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGE
Lloh38:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGEOFF]
Lloh39:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGE
Lloh40:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh43:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh44:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh46:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh47:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
Lloh49:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGE
Lloh50:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh51:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh52:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh53:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	orr	w8, w8, w9
	b	LBB0_15
LBB0_13:
	mov	w0, #0
Lloh55:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh56:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
LBB0_14:
	ldr	w8, [x8]
Lloh57:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh58:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w8, w9, w8
LBB0_15:
Lloh60:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh61:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
LBB0_16:
	ldr	w9, [x9]
	orr	w8, w8, w9
	b	LBB0_21
LBB0_17:
Lloh62:
	adrp	x1, l_.str@PAGE
Lloh63:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x20
	bl	_DP_INFO
	mov	w0, #0
	mov	w8, #255
	b	LBB0_21
LBB0_18:
	mov	w0, #0
Lloh64:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh65:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	b	LBB0_21
LBB0_19:
	mov	w0, #0
Lloh67:
	adrp	x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh68:
	ldr	x8, [x8, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
Lloh70:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh71:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
LBB0_20:
	ldr	w9, [x9]
	orr	w8, w9, w8
LBB0_21:
	str	w8, [x19]
LBB0_22:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh30
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh41
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpAdd	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_18-LBB0_4)>>2
	.byte	(LBB0_11-LBB0_4)>>2
	.byte	(LBB0_11-LBB0_4)>>2
	.byte	(LBB0_12-LBB0_4)>>2
	.byte	(LBB0_11-LBB0_4)>>2
	.byte	(LBB0_9-LBB0_4)>>2
	.byte	(LBB0_9-LBB0_4)>>2
	.byte	(LBB0_13-LBB0_4)>>2
	.byte	(LBB0_10-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_9-LBB0_4)>>2
	.byte	(LBB0_9-LBB0_4)>>2
	.byte	(LBB0_13-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_10-LBB0_4)>>2
	.byte	(LBB0_10-LBB0_4)>>2
	.byte	(LBB0_10-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_6-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_19-LBB0_4)>>2
	.byte	(LBB0_4-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_12-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_8-LBB0_4)>>2
	.byte	(LBB0_7-LBB0_4)>>2
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unknown transceiver type 0x%x\n"

.subsections_via_symbols
