	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function b43_nphy_superswitch_init
_b43_nphy_superswitch_init:             ## @b43_nphy_superswitch_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	cmpl	$2, 8(%rdi)
	jg	LBB0_2
## %bb.1:
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_B43_NPHY_GPIO_LOOEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_b43_phy_write
	movq	_B43_NPHY_GPIO_HIOEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_b43_phy_write
	movq	_B43_MMIO_MACCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_B43_MACCTL_GPOUTSMSK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	movq	%rbx, %rdi
	xorl	%ecx, %ecx
	callq	_b43_maskset32
	movq	_B43_MMIO_GPIO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$-1, %edx
	movl	$64512, %ecx                    ## imm = 0xFC00
	callq	_b43_maskset16
	movq	_B43_MMIO_GPIO_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1023, %edx                     ## imm = 0x3FF
	xorl	%ecx, %ecx
	callq	_b43_maskset16
	testl	%r14d, %r14d
	je	LBB0_2
## %bb.3:
	movq	_B43_NPHY_RFCTL_LUT_TRSW_LO1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$728, %edx                      ## imm = 0x2D8
	callq	_b43_phy_write
	movq	_B43_NPHY_RFCTL_LUT_TRSW_UP1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$769, %edx                      ## imm = 0x301
	callq	_b43_phy_write
	movq	_B43_NPHY_RFCTL_LUT_TRSW_LO2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$728, %edx                      ## imm = 0x2D8
	callq	_b43_phy_write
	movq	_B43_NPHY_RFCTL_LUT_TRSW_UP2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$769, %edx                      ## imm = 0x301
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_b43_phy_write                  ## TAILCALL
LBB0_2:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_B43_NPHY_GPIO_LOOEN,4,2        ## @B43_NPHY_GPIO_LOOEN
	.comm	_B43_NPHY_GPIO_HIOEN,4,2        ## @B43_NPHY_GPIO_HIOEN
	.comm	_B43_MMIO_MACCTL,4,2            ## @B43_MMIO_MACCTL
	.comm	_B43_MACCTL_GPOUTSMSK,4,2       ## @B43_MACCTL_GPOUTSMSK
	.comm	_B43_MMIO_GPIO_MASK,4,2         ## @B43_MMIO_GPIO_MASK
	.comm	_B43_MMIO_GPIO_CONTROL,4,2      ## @B43_MMIO_GPIO_CONTROL
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_LO1,4,2 ## @B43_NPHY_RFCTL_LUT_TRSW_LO1
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_UP1,4,2 ## @B43_NPHY_RFCTL_LUT_TRSW_UP1
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_LO2,4,2 ## @B43_NPHY_RFCTL_LUT_TRSW_LO2
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_UP2,4,2 ## @B43_NPHY_RFCTL_LUT_TRSW_UP2
	.no_dead_strip	_b43_nphy_superswitch_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function b43_nphy_superswitch_init
_b43_nphy_superswitch_init:             ; @b43_nphy_superswitch_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0, #8]
	cmp	w8, #2
	b.gt	LBB0_3
; %bb.1:
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _B43_NPHY_GPIO_LOOEN@GOTPAGE
Lloh1:
	ldr	x8, [x8, _B43_NPHY_GPIO_LOOEN@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_b43_phy_write
Lloh3:
	adrp	x8, _B43_NPHY_GPIO_HIOEN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _B43_NPHY_GPIO_HIOEN@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_b43_phy_write
Lloh6:
	adrp	x8, _B43_MMIO_MACCTL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _B43_MMIO_MACCTL@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _B43_MACCTL_GPOUTSMSK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _B43_MACCTL_GPOUTSMSK@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	mvn	w2, w8
	mov	x0, x19
	mov	w3, #0
	bl	_b43_maskset32
Lloh12:
	adrp	x8, _B43_MMIO_GPIO_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _B43_MMIO_GPIO_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1
	mov	w3, #64512
	bl	_b43_maskset16
Lloh15:
	adrp	x8, _B43_MMIO_GPIO_CONTROL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _B43_MMIO_GPIO_CONTROL@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1023
	mov	w3, #0
	bl	_b43_maskset16
	cbz	w20, LBB0_3
; %bb.2:
Lloh18:
	adrp	x8, _B43_NPHY_RFCTL_LUT_TRSW_LO1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _B43_NPHY_RFCTL_LUT_TRSW_LO1@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #728
	bl	_b43_phy_write
Lloh21:
	adrp	x8, _B43_NPHY_RFCTL_LUT_TRSW_UP1@GOTPAGE
Lloh22:
	ldr	x8, [x8, _B43_NPHY_RFCTL_LUT_TRSW_UP1@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #769
	bl	_b43_phy_write
Lloh24:
	adrp	x8, _B43_NPHY_RFCTL_LUT_TRSW_LO2@GOTPAGE
Lloh25:
	ldr	x8, [x8, _B43_NPHY_RFCTL_LUT_TRSW_LO2@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #728
	bl	_b43_phy_write
Lloh27:
	adrp	x8, _B43_NPHY_RFCTL_LUT_TRSW_UP2@GOTPAGE
Lloh28:
	ldr	x8, [x8, _B43_NPHY_RFCTL_LUT_TRSW_UP2@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #769
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_b43_phy_write
LBB0_3:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_B43_NPHY_GPIO_LOOEN,4,2        ; @B43_NPHY_GPIO_LOOEN
	.comm	_B43_NPHY_GPIO_HIOEN,4,2        ; @B43_NPHY_GPIO_HIOEN
	.comm	_B43_MMIO_MACCTL,4,2            ; @B43_MMIO_MACCTL
	.comm	_B43_MACCTL_GPOUTSMSK,4,2       ; @B43_MACCTL_GPOUTSMSK
	.comm	_B43_MMIO_GPIO_MASK,4,2         ; @B43_MMIO_GPIO_MASK
	.comm	_B43_MMIO_GPIO_CONTROL,4,2      ; @B43_MMIO_GPIO_CONTROL
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_LO1,4,2 ; @B43_NPHY_RFCTL_LUT_TRSW_LO1
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_UP1,4,2 ; @B43_NPHY_RFCTL_LUT_TRSW_UP1
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_LO2,4,2 ; @B43_NPHY_RFCTL_LUT_TRSW_LO2
	.comm	_B43_NPHY_RFCTL_LUT_TRSW_UP2,4,2 ; @B43_NPHY_RFCTL_LUT_TRSW_UP2
	.no_dead_strip	_b43_nphy_superswitch_init
.subsections_via_symbols
