	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rt2500pci_init_registers
_rt2500pci_init_registers:              ## @rt2500pci_init_registers
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_PSCSR0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$131074, %edx                   ## imm = 0x20002
	callq	_rt2x00mmio_register_write
	movq	_PSCSR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$2, %edx
	callq	_rt2x00mmio_register_write
	movq	_PSCSR2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$131074, %edx                   ## imm = 0x20002
	callq	_rt2x00mmio_register_write
	movq	_PSCSR3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$2, %edx
	callq	_rt2x00mmio_register_write
	movq	_TIMECSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_TIMECSR_US_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$33, %edx
	callq	_rt2x00_set_field32
	movq	_TIMECSR_US_64_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$63, %edx
	callq	_rt2x00_set_field32
	movq	_TIMECSR_BEACON_EXPECT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r13d, %r13d
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_CSR9@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_CSR9_MAX_FRAME_UNIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%r15), %rax
	movl	(%rax), %eax
	leal	127(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$7, %edx
	movq	%rbx, %rdi
	callq	_rt2x00_set_field32
	movl	(%r14), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_CSR11@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_CSR11_CW_SELECT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movl	(%r14), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_CSR14@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_CSR14_TSF_COUNT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_TSF_SYNC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_TBCN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_TCFP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_TATIMW@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_BEACON_GEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_CFP_COUNT_PRELOAD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR14_TBCM_PRELOAD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_CNT3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_rt2x00mmio_register_write
	movq	_TXCSR8@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_TXCSR8_BBP_ID0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$10, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID0_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$11, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID1_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$13, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID2_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$12, %edx
	callq	_rt2x00_set_field32
	movq	_TXCSR8_BBP_ID3_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_ARTCSR0@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_ARTCSR0_ACK_CTS_1MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$112, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR0_ACK_CTS_2MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$56, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR0_ACK_CTS_5_5MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$20, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR0_ACK_CTS_11MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$10, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_ARTCSR1@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_ARTCSR1_ACK_CTS_6MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$45, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR1_ACK_CTS_9MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$37, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR1_ACK_CTS_12MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$33, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR1_ACK_CTS_18MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$29, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_ARTCSR2@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_ARTCSR2_ACK_CTS_24MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$29, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR2_ACK_CTS_36MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$25, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR2_ACK_CTS_48MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$25, %edx
	callq	_rt2x00_set_field32
	movq	_ARTCSR2_ACK_CTS_54MBS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$25, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_RXCSR3@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_RXCSR3_BBP_ID0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$47, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID0_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$51, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID1_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$42, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID2_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$51, %edx
	callq	_rt2x00_set_field32
	movq	_RXCSR3_BBP_ID3_VALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_PCICSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_PCICSR_BIG_ENDIAN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_PCICSR_RX_TRESHOLD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_PCICSR_TX_TRESHOLD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$3, %edx
	callq	_rt2x00_set_field32
	movq	_PCICSR_BURST_LENTH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_PCICSR_ENABLE_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_PCICSR_READ_MULTIPLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_PCICSR_WRITE_INVALID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_PWRCSR0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1060843776, %edx               ## imm = 0x3F3B3100
	callq	_rt2x00mmio_register_write
	movq	_GPIOCSR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$65280, %edx                    ## imm = 0xFF00
	callq	_rt2x00mmio_register_write
	movq	_TESTCSR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$240, %edx
	callq	_rt2x00mmio_register_write
	movq	(%r15), %rax
	movq	(%rax), %rax
	movq	_STATE_AWAKE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	%r15, %rdi
	callq	*(%rax)
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_EBUSY@GOTPCREL(%rip), %rax
	subl	(%rax), %r13d
	jmp	LBB0_3
LBB0_2:
	movq	_MACCSR0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$2175523, %edx                  ## imm = 0x213223
	callq	_rt2x00mmio_register_write
	movq	_MACCSR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$2315544, %edx                  ## imm = 0x235518
	callq	_rt2x00mmio_register_write
	movq	_MACCSR2@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_MACCSR2_DELAY@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rbx
	movq	%rbx, %rdi
	movl	$64, %edx
	callq	_rt2x00_set_field32
	movl	(%r14), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_RALINKCSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_RALINKCSR_AR_BBP_DATA0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$17, %edx
	callq	_rt2x00_set_field32
	movq	_RALINKCSR_AR_BBP_ID0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$26, %edx
	callq	_rt2x00_set_field32
	movq	_RALINKCSR_AR_BBP_VALID0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_RALINKCSR_AR_BBP_DATA1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_RALINKCSR_AR_BBP_ID1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$26, %edx
	callq	_rt2x00_set_field32
	movq	_RALINKCSR_AR_BBP_VALID1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_BBPCSR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-2112323072, %edx              ## imm = 0x82188200
	callq	_rt2x00mmio_register_write
	movq	_TXACKCSR0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$32, %edx
	callq	_rt2x00mmio_register_write
	movq	_CSR1@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_CSR1_SOFT_RESET@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_CSR1_BBP_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movq	_CSR1_HOST_READY@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movl	(%r13), %esi
	xorl	%r13d, %r13d
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_rt2x00_set_field32
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-44(%rbp), %edx
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_write
	movq	_CNT0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_CNT4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_rt2x00mmio_register_read
LBB0_3:
	movl	%r13d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PSCSR0,4,2                     ## @PSCSR0
	.comm	_PSCSR1,4,2                     ## @PSCSR1
	.comm	_PSCSR2,4,2                     ## @PSCSR2
	.comm	_PSCSR3,4,2                     ## @PSCSR3
	.comm	_TIMECSR,4,2                    ## @TIMECSR
	.comm	_TIMECSR_US_COUNT,4,2           ## @TIMECSR_US_COUNT
	.comm	_TIMECSR_US_64_COUNT,4,2        ## @TIMECSR_US_64_COUNT
	.comm	_TIMECSR_BEACON_EXPECT,4,2      ## @TIMECSR_BEACON_EXPECT
	.comm	_CSR9,4,2                       ## @CSR9
	.comm	_CSR9_MAX_FRAME_UNIT,4,2        ## @CSR9_MAX_FRAME_UNIT
	.comm	_CSR11,4,2                      ## @CSR11
	.comm	_CSR11_CW_SELECT,4,2            ## @CSR11_CW_SELECT
	.comm	_CSR14,4,2                      ## @CSR14
	.comm	_CSR14_TSF_COUNT,4,2            ## @CSR14_TSF_COUNT
	.comm	_CSR14_TSF_SYNC,4,2             ## @CSR14_TSF_SYNC
	.comm	_CSR14_TBCN,4,2                 ## @CSR14_TBCN
	.comm	_CSR14_TCFP,4,2                 ## @CSR14_TCFP
	.comm	_CSR14_TATIMW,4,2               ## @CSR14_TATIMW
	.comm	_CSR14_BEACON_GEN,4,2           ## @CSR14_BEACON_GEN
	.comm	_CSR14_CFP_COUNT_PRELOAD,4,2    ## @CSR14_CFP_COUNT_PRELOAD
	.comm	_CSR14_TBCM_PRELOAD,4,2         ## @CSR14_TBCM_PRELOAD
	.comm	_CNT3,4,2                       ## @CNT3
	.comm	_TXCSR8,4,2                     ## @TXCSR8
	.comm	_TXCSR8_BBP_ID0,4,2             ## @TXCSR8_BBP_ID0
	.comm	_TXCSR8_BBP_ID0_VALID,4,2       ## @TXCSR8_BBP_ID0_VALID
	.comm	_TXCSR8_BBP_ID1,4,2             ## @TXCSR8_BBP_ID1
	.comm	_TXCSR8_BBP_ID1_VALID,4,2       ## @TXCSR8_BBP_ID1_VALID
	.comm	_TXCSR8_BBP_ID2,4,2             ## @TXCSR8_BBP_ID2
	.comm	_TXCSR8_BBP_ID2_VALID,4,2       ## @TXCSR8_BBP_ID2_VALID
	.comm	_TXCSR8_BBP_ID3,4,2             ## @TXCSR8_BBP_ID3
	.comm	_TXCSR8_BBP_ID3_VALID,4,2       ## @TXCSR8_BBP_ID3_VALID
	.comm	_ARTCSR0,4,2                    ## @ARTCSR0
	.comm	_ARTCSR0_ACK_CTS_1MBS,4,2       ## @ARTCSR0_ACK_CTS_1MBS
	.comm	_ARTCSR0_ACK_CTS_2MBS,4,2       ## @ARTCSR0_ACK_CTS_2MBS
	.comm	_ARTCSR0_ACK_CTS_5_5MBS,4,2     ## @ARTCSR0_ACK_CTS_5_5MBS
	.comm	_ARTCSR0_ACK_CTS_11MBS,4,2      ## @ARTCSR0_ACK_CTS_11MBS
	.comm	_ARTCSR1,4,2                    ## @ARTCSR1
	.comm	_ARTCSR1_ACK_CTS_6MBS,4,2       ## @ARTCSR1_ACK_CTS_6MBS
	.comm	_ARTCSR1_ACK_CTS_9MBS,4,2       ## @ARTCSR1_ACK_CTS_9MBS
	.comm	_ARTCSR1_ACK_CTS_12MBS,4,2      ## @ARTCSR1_ACK_CTS_12MBS
	.comm	_ARTCSR1_ACK_CTS_18MBS,4,2      ## @ARTCSR1_ACK_CTS_18MBS
	.comm	_ARTCSR2,4,2                    ## @ARTCSR2
	.comm	_ARTCSR2_ACK_CTS_24MBS,4,2      ## @ARTCSR2_ACK_CTS_24MBS
	.comm	_ARTCSR2_ACK_CTS_36MBS,4,2      ## @ARTCSR2_ACK_CTS_36MBS
	.comm	_ARTCSR2_ACK_CTS_48MBS,4,2      ## @ARTCSR2_ACK_CTS_48MBS
	.comm	_ARTCSR2_ACK_CTS_54MBS,4,2      ## @ARTCSR2_ACK_CTS_54MBS
	.comm	_RXCSR3,4,2                     ## @RXCSR3
	.comm	_RXCSR3_BBP_ID0,4,2             ## @RXCSR3_BBP_ID0
	.comm	_RXCSR3_BBP_ID0_VALID,4,2       ## @RXCSR3_BBP_ID0_VALID
	.comm	_RXCSR3_BBP_ID1,4,2             ## @RXCSR3_BBP_ID1
	.comm	_RXCSR3_BBP_ID1_VALID,4,2       ## @RXCSR3_BBP_ID1_VALID
	.comm	_RXCSR3_BBP_ID2,4,2             ## @RXCSR3_BBP_ID2
	.comm	_RXCSR3_BBP_ID2_VALID,4,2       ## @RXCSR3_BBP_ID2_VALID
	.comm	_RXCSR3_BBP_ID3,4,2             ## @RXCSR3_BBP_ID3
	.comm	_RXCSR3_BBP_ID3_VALID,4,2       ## @RXCSR3_BBP_ID3_VALID
	.comm	_PCICSR,4,2                     ## @PCICSR
	.comm	_PCICSR_BIG_ENDIAN,4,2          ## @PCICSR_BIG_ENDIAN
	.comm	_PCICSR_RX_TRESHOLD,4,2         ## @PCICSR_RX_TRESHOLD
	.comm	_PCICSR_TX_TRESHOLD,4,2         ## @PCICSR_TX_TRESHOLD
	.comm	_PCICSR_BURST_LENTH,4,2         ## @PCICSR_BURST_LENTH
	.comm	_PCICSR_ENABLE_CLK,4,2          ## @PCICSR_ENABLE_CLK
	.comm	_PCICSR_READ_MULTIPLE,4,2       ## @PCICSR_READ_MULTIPLE
	.comm	_PCICSR_WRITE_INVALID,4,2       ## @PCICSR_WRITE_INVALID
	.comm	_PWRCSR0,4,2                    ## @PWRCSR0
	.comm	_GPIOCSR,4,2                    ## @GPIOCSR
	.comm	_TESTCSR,4,2                    ## @TESTCSR
	.comm	_STATE_AWAKE,4,2                ## @STATE_AWAKE
	.comm	_EBUSY,4,2                      ## @EBUSY
	.comm	_MACCSR0,4,2                    ## @MACCSR0
	.comm	_MACCSR1,4,2                    ## @MACCSR1
	.comm	_MACCSR2,4,2                    ## @MACCSR2
	.comm	_MACCSR2_DELAY,4,2              ## @MACCSR2_DELAY
	.comm	_RALINKCSR,4,2                  ## @RALINKCSR
	.comm	_RALINKCSR_AR_BBP_DATA0,4,2     ## @RALINKCSR_AR_BBP_DATA0
	.comm	_RALINKCSR_AR_BBP_ID0,4,2       ## @RALINKCSR_AR_BBP_ID0
	.comm	_RALINKCSR_AR_BBP_VALID0,4,2    ## @RALINKCSR_AR_BBP_VALID0
	.comm	_RALINKCSR_AR_BBP_DATA1,4,2     ## @RALINKCSR_AR_BBP_DATA1
	.comm	_RALINKCSR_AR_BBP_ID1,4,2       ## @RALINKCSR_AR_BBP_ID1
	.comm	_RALINKCSR_AR_BBP_VALID1,4,2    ## @RALINKCSR_AR_BBP_VALID1
	.comm	_BBPCSR1,4,2                    ## @BBPCSR1
	.comm	_TXACKCSR0,4,2                  ## @TXACKCSR0
	.comm	_CSR1,4,2                       ## @CSR1
	.comm	_CSR1_SOFT_RESET,4,2            ## @CSR1_SOFT_RESET
	.comm	_CSR1_BBP_RESET,4,2             ## @CSR1_BBP_RESET
	.comm	_CSR1_HOST_READY,4,2            ## @CSR1_HOST_READY
	.comm	_CNT0,4,2                       ## @CNT0
	.comm	_CNT4,4,2                       ## @CNT4
	.no_dead_strip	_rt2500pci_init_registers
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rt2500pci_init_registers
_rt2500pci_init_registers:              ; @rt2500pci_init_registers
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _PSCSR0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PSCSR0@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #131074
	bl	_rt2x00mmio_register_write
Lloh3:
	adrp	x8, _PSCSR1@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PSCSR1@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2
	bl	_rt2x00mmio_register_write
Lloh6:
	adrp	x8, _PSCSR2@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PSCSR2@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #131074
	bl	_rt2x00mmio_register_write
Lloh9:
	adrp	x8, _PSCSR3@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PSCSR3@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #2
	bl	_rt2x00mmio_register_write
Lloh12:
	adrp	x20, _TIMECSR@GOTPAGE
Lloh13:
	ldr	x20, [x20, _TIMECSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh14:
	adrp	x8, _TIMECSR_US_COUNT@GOTPAGE
Lloh15:
	ldr	x8, [x8, _TIMECSR_US_COUNT@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #33
	bl	_rt2x00_set_field32
Lloh17:
	adrp	x8, _TIMECSR_US_64_COUNT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _TIMECSR_US_64_COUNT@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #63
	bl	_rt2x00_set_field32
Lloh20:
	adrp	x8, _TIMECSR_BEACON_EXPECT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _TIMECSR_BEACON_EXPECT@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh23:
	adrp	x20, _CSR9@GOTPAGE
Lloh24:
	ldr	x20, [x20, _CSR9@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh25:
	adrp	x8, _CSR9_MAX_FRAME_UNIT@GOTPAGE
Lloh26:
	ldr	x8, [x8, _CSR9_MAX_FRAME_UNIT@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
	add	w9, w8, #127
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w2, w8, #7
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh28:
	adrp	x20, _CSR11@GOTPAGE
Lloh29:
	ldr	x20, [x20, _CSR11@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh30:
	adrp	x8, _CSR11_CW_SELECT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CSR11_CW_SELECT@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh33:
	adrp	x20, _CSR14@GOTPAGE
Lloh34:
	ldr	x20, [x20, _CSR14@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh35:
	adrp	x8, _CSR14_TSF_COUNT@GOTPAGE
Lloh36:
	ldr	x8, [x8, _CSR14_TSF_COUNT@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh38:
	adrp	x8, _CSR14_TSF_SYNC@GOTPAGE
Lloh39:
	ldr	x8, [x8, _CSR14_TSF_SYNC@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh41:
	adrp	x8, _CSR14_TBCN@GOTPAGE
Lloh42:
	ldr	x8, [x8, _CSR14_TBCN@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh44:
	adrp	x8, _CSR14_TCFP@GOTPAGE
Lloh45:
	ldr	x8, [x8, _CSR14_TCFP@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh47:
	adrp	x8, _CSR14_TATIMW@GOTPAGE
Lloh48:
	ldr	x8, [x8, _CSR14_TATIMW@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh50:
	adrp	x8, _CSR14_BEACON_GEN@GOTPAGE
Lloh51:
	ldr	x8, [x8, _CSR14_BEACON_GEN@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh53:
	adrp	x8, _CSR14_CFP_COUNT_PRELOAD@GOTPAGE
Lloh54:
	ldr	x8, [x8, _CSR14_CFP_COUNT_PRELOAD@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh56:
	adrp	x8, _CSR14_TBCM_PRELOAD@GOTPAGE
Lloh57:
	ldr	x8, [x8, _CSR14_TBCM_PRELOAD@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh59:
	adrp	x8, _CNT3@GOTPAGE
Lloh60:
	ldr	x8, [x8, _CNT3@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_rt2x00mmio_register_write
Lloh62:
	adrp	x20, _TXCSR8@GOTPAGE
Lloh63:
	ldr	x20, [x20, _TXCSR8@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh64:
	adrp	x8, _TXCSR8_BBP_ID0@GOTPAGE
Lloh65:
	ldr	x8, [x8, _TXCSR8_BBP_ID0@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #10
	bl	_rt2x00_set_field32
Lloh67:
	adrp	x8, _TXCSR8_BBP_ID0_VALID@GOTPAGE
Lloh68:
	ldr	x8, [x8, _TXCSR8_BBP_ID0_VALID@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh70:
	adrp	x8, _TXCSR8_BBP_ID1@GOTPAGE
Lloh71:
	ldr	x8, [x8, _TXCSR8_BBP_ID1@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #11
	bl	_rt2x00_set_field32
Lloh73:
	adrp	x8, _TXCSR8_BBP_ID1_VALID@GOTPAGE
Lloh74:
	ldr	x8, [x8, _TXCSR8_BBP_ID1_VALID@GOTPAGEOFF]
Lloh75:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh76:
	adrp	x8, _TXCSR8_BBP_ID2@GOTPAGE
Lloh77:
	ldr	x8, [x8, _TXCSR8_BBP_ID2@GOTPAGEOFF]
Lloh78:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #13
	bl	_rt2x00_set_field32
Lloh79:
	adrp	x8, _TXCSR8_BBP_ID2_VALID@GOTPAGE
Lloh80:
	ldr	x8, [x8, _TXCSR8_BBP_ID2_VALID@GOTPAGEOFF]
Lloh81:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh82:
	adrp	x8, _TXCSR8_BBP_ID3@GOTPAGE
Lloh83:
	ldr	x8, [x8, _TXCSR8_BBP_ID3@GOTPAGEOFF]
Lloh84:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #12
	bl	_rt2x00_set_field32
Lloh85:
	adrp	x8, _TXCSR8_BBP_ID3_VALID@GOTPAGE
Lloh86:
	ldr	x8, [x8, _TXCSR8_BBP_ID3_VALID@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh88:
	adrp	x20, _ARTCSR0@GOTPAGE
Lloh89:
	ldr	x20, [x20, _ARTCSR0@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh90:
	adrp	x8, _ARTCSR0_ACK_CTS_1MBS@GOTPAGE
Lloh91:
	ldr	x8, [x8, _ARTCSR0_ACK_CTS_1MBS@GOTPAGEOFF]
Lloh92:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #112
	bl	_rt2x00_set_field32
Lloh93:
	adrp	x8, _ARTCSR0_ACK_CTS_2MBS@GOTPAGE
Lloh94:
	ldr	x8, [x8, _ARTCSR0_ACK_CTS_2MBS@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #56
	bl	_rt2x00_set_field32
Lloh96:
	adrp	x8, _ARTCSR0_ACK_CTS_5_5MBS@GOTPAGE
Lloh97:
	ldr	x8, [x8, _ARTCSR0_ACK_CTS_5_5MBS@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #20
	bl	_rt2x00_set_field32
Lloh99:
	adrp	x8, _ARTCSR0_ACK_CTS_11MBS@GOTPAGE
Lloh100:
	ldr	x8, [x8, _ARTCSR0_ACK_CTS_11MBS@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #10
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh102:
	adrp	x20, _ARTCSR1@GOTPAGE
Lloh103:
	ldr	x20, [x20, _ARTCSR1@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh104:
	adrp	x8, _ARTCSR1_ACK_CTS_6MBS@GOTPAGE
Lloh105:
	ldr	x8, [x8, _ARTCSR1_ACK_CTS_6MBS@GOTPAGEOFF]
Lloh106:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #45
	bl	_rt2x00_set_field32
Lloh107:
	adrp	x8, _ARTCSR1_ACK_CTS_9MBS@GOTPAGE
Lloh108:
	ldr	x8, [x8, _ARTCSR1_ACK_CTS_9MBS@GOTPAGEOFF]
Lloh109:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #37
	bl	_rt2x00_set_field32
Lloh110:
	adrp	x8, _ARTCSR1_ACK_CTS_12MBS@GOTPAGE
Lloh111:
	ldr	x8, [x8, _ARTCSR1_ACK_CTS_12MBS@GOTPAGEOFF]
Lloh112:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #33
	bl	_rt2x00_set_field32
Lloh113:
	adrp	x8, _ARTCSR1_ACK_CTS_18MBS@GOTPAGE
Lloh114:
	ldr	x8, [x8, _ARTCSR1_ACK_CTS_18MBS@GOTPAGEOFF]
Lloh115:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #29
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh116:
	adrp	x20, _ARTCSR2@GOTPAGE
Lloh117:
	ldr	x20, [x20, _ARTCSR2@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh118:
	adrp	x8, _ARTCSR2_ACK_CTS_24MBS@GOTPAGE
Lloh119:
	ldr	x8, [x8, _ARTCSR2_ACK_CTS_24MBS@GOTPAGEOFF]
Lloh120:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #29
	bl	_rt2x00_set_field32
Lloh121:
	adrp	x8, _ARTCSR2_ACK_CTS_36MBS@GOTPAGE
Lloh122:
	ldr	x8, [x8, _ARTCSR2_ACK_CTS_36MBS@GOTPAGEOFF]
Lloh123:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #25
	bl	_rt2x00_set_field32
Lloh124:
	adrp	x8, _ARTCSR2_ACK_CTS_48MBS@GOTPAGE
Lloh125:
	ldr	x8, [x8, _ARTCSR2_ACK_CTS_48MBS@GOTPAGEOFF]
Lloh126:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #25
	bl	_rt2x00_set_field32
Lloh127:
	adrp	x8, _ARTCSR2_ACK_CTS_54MBS@GOTPAGE
Lloh128:
	ldr	x8, [x8, _ARTCSR2_ACK_CTS_54MBS@GOTPAGEOFF]
Lloh129:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #25
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh130:
	adrp	x20, _RXCSR3@GOTPAGE
Lloh131:
	ldr	x20, [x20, _RXCSR3@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh132:
	adrp	x8, _RXCSR3_BBP_ID0@GOTPAGE
Lloh133:
	ldr	x8, [x8, _RXCSR3_BBP_ID0@GOTPAGEOFF]
Lloh134:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #47
	bl	_rt2x00_set_field32
Lloh135:
	adrp	x8, _RXCSR3_BBP_ID0_VALID@GOTPAGE
Lloh136:
	ldr	x8, [x8, _RXCSR3_BBP_ID0_VALID@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh138:
	adrp	x8, _RXCSR3_BBP_ID1@GOTPAGE
Lloh139:
	ldr	x8, [x8, _RXCSR3_BBP_ID1@GOTPAGEOFF]
Lloh140:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #51
	bl	_rt2x00_set_field32
Lloh141:
	adrp	x8, _RXCSR3_BBP_ID1_VALID@GOTPAGE
Lloh142:
	ldr	x8, [x8, _RXCSR3_BBP_ID1_VALID@GOTPAGEOFF]
Lloh143:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh144:
	adrp	x8, _RXCSR3_BBP_ID2@GOTPAGE
Lloh145:
	ldr	x8, [x8, _RXCSR3_BBP_ID2@GOTPAGEOFF]
Lloh146:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #42
	bl	_rt2x00_set_field32
Lloh147:
	adrp	x8, _RXCSR3_BBP_ID2_VALID@GOTPAGE
Lloh148:
	ldr	x8, [x8, _RXCSR3_BBP_ID2_VALID@GOTPAGEOFF]
Lloh149:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh150:
	adrp	x8, _RXCSR3_BBP_ID3@GOTPAGE
Lloh151:
	ldr	x8, [x8, _RXCSR3_BBP_ID3@GOTPAGEOFF]
Lloh152:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #51
	bl	_rt2x00_set_field32
Lloh153:
	adrp	x8, _RXCSR3_BBP_ID3_VALID@GOTPAGE
Lloh154:
	ldr	x8, [x8, _RXCSR3_BBP_ID3_VALID@GOTPAGEOFF]
Lloh155:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh156:
	adrp	x20, _PCICSR@GOTPAGE
Lloh157:
	ldr	x20, [x20, _PCICSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh158:
	adrp	x8, _PCICSR_BIG_ENDIAN@GOTPAGE
Lloh159:
	ldr	x8, [x8, _PCICSR_BIG_ENDIAN@GOTPAGEOFF]
Lloh160:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh161:
	adrp	x8, _PCICSR_RX_TRESHOLD@GOTPAGE
Lloh162:
	ldr	x8, [x8, _PCICSR_RX_TRESHOLD@GOTPAGEOFF]
Lloh163:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh164:
	adrp	x8, _PCICSR_TX_TRESHOLD@GOTPAGE
Lloh165:
	ldr	x8, [x8, _PCICSR_TX_TRESHOLD@GOTPAGEOFF]
Lloh166:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #3
	bl	_rt2x00_set_field32
Lloh167:
	adrp	x8, _PCICSR_BURST_LENTH@GOTPAGE
Lloh168:
	ldr	x8, [x8, _PCICSR_BURST_LENTH@GOTPAGEOFF]
Lloh169:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh170:
	adrp	x8, _PCICSR_ENABLE_CLK@GOTPAGE
Lloh171:
	ldr	x8, [x8, _PCICSR_ENABLE_CLK@GOTPAGEOFF]
Lloh172:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh173:
	adrp	x8, _PCICSR_READ_MULTIPLE@GOTPAGE
Lloh174:
	ldr	x8, [x8, _PCICSR_READ_MULTIPLE@GOTPAGEOFF]
Lloh175:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh176:
	adrp	x8, _PCICSR_WRITE_INVALID@GOTPAGE
Lloh177:
	ldr	x8, [x8, _PCICSR_WRITE_INVALID@GOTPAGEOFF]
Lloh178:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh179:
	adrp	x8, _PWRCSR0@GOTPAGE
Lloh180:
	ldr	x8, [x8, _PWRCSR0@GOTPAGEOFF]
Lloh181:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #12544
	movk	w2, #16187, lsl #16
	bl	_rt2x00mmio_register_write
Lloh182:
	adrp	x8, _GPIOCSR@GOTPAGE
Lloh183:
	ldr	x8, [x8, _GPIOCSR@GOTPAGEOFF]
Lloh184:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #65280
	bl	_rt2x00mmio_register_write
Lloh185:
	adrp	x8, _TESTCSR@GOTPAGE
Lloh186:
	ldr	x8, [x8, _TESTCSR@GOTPAGEOFF]
Lloh187:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #240
	bl	_rt2x00mmio_register_write
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8]
Lloh188:
	adrp	x9, _STATE_AWAKE@GOTPAGE
Lloh189:
	ldr	x9, [x9, _STATE_AWAKE@GOTPAGEOFF]
Lloh190:
	ldr	w1, [x9]
	mov	x0, x19
	blr	x8
	cbz	x0, LBB0_2
; %bb.1:
Lloh191:
	adrp	x8, _EBUSY@GOTPAGE
Lloh192:
	ldr	x8, [x8, _EBUSY@GOTPAGEOFF]
Lloh193:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_3
LBB0_2:
Lloh194:
	adrp	x8, _MACCSR0@GOTPAGE
Lloh195:
	ldr	x8, [x8, _MACCSR0@GOTPAGEOFF]
Lloh196:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #12835
	movk	w2, #33, lsl #16
	bl	_rt2x00mmio_register_write
Lloh197:
	adrp	x8, _MACCSR1@GOTPAGE
Lloh198:
	ldr	x8, [x8, _MACCSR1@GOTPAGEOFF]
Lloh199:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #21784
	movk	w2, #35, lsl #16
	bl	_rt2x00mmio_register_write
Lloh200:
	adrp	x20, _MACCSR2@GOTPAGE
Lloh201:
	ldr	x20, [x20, _MACCSR2@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh202:
	adrp	x8, _MACCSR2_DELAY@GOTPAGE
Lloh203:
	ldr	x8, [x8, _MACCSR2_DELAY@GOTPAGEOFF]
Lloh204:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #64
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh205:
	adrp	x20, _RALINKCSR@GOTPAGE
Lloh206:
	ldr	x20, [x20, _RALINKCSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh207:
	adrp	x8, _RALINKCSR_AR_BBP_DATA0@GOTPAGE
Lloh208:
	ldr	x8, [x8, _RALINKCSR_AR_BBP_DATA0@GOTPAGEOFF]
Lloh209:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #17
	bl	_rt2x00_set_field32
Lloh210:
	adrp	x8, _RALINKCSR_AR_BBP_ID0@GOTPAGE
Lloh211:
	ldr	x8, [x8, _RALINKCSR_AR_BBP_ID0@GOTPAGEOFF]
Lloh212:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #26
	bl	_rt2x00_set_field32
Lloh213:
	adrp	x8, _RALINKCSR_AR_BBP_VALID0@GOTPAGE
Lloh214:
	ldr	x8, [x8, _RALINKCSR_AR_BBP_VALID0@GOTPAGEOFF]
Lloh215:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh216:
	adrp	x8, _RALINKCSR_AR_BBP_DATA1@GOTPAGE
Lloh217:
	ldr	x8, [x8, _RALINKCSR_AR_BBP_DATA1@GOTPAGEOFF]
Lloh218:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh219:
	adrp	x8, _RALINKCSR_AR_BBP_ID1@GOTPAGE
Lloh220:
	ldr	x8, [x8, _RALINKCSR_AR_BBP_ID1@GOTPAGEOFF]
Lloh221:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #26
	bl	_rt2x00_set_field32
Lloh222:
	adrp	x8, _RALINKCSR_AR_BBP_VALID1@GOTPAGE
Lloh223:
	ldr	x8, [x8, _RALINKCSR_AR_BBP_VALID1@GOTPAGEOFF]
Lloh224:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh225:
	adrp	x8, _BBPCSR1@GOTPAGE
Lloh226:
	ldr	x8, [x8, _BBPCSR1@GOTPAGEOFF]
Lloh227:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #33280
	movk	w2, #33304, lsl #16
	bl	_rt2x00mmio_register_write
Lloh228:
	adrp	x8, _TXACKCSR0@GOTPAGE
Lloh229:
	ldr	x8, [x8, _TXACKCSR0@GOTPAGEOFF]
Lloh230:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #32
	bl	_rt2x00mmio_register_write
Lloh231:
	adrp	x20, _CSR1@GOTPAGE
Lloh232:
	ldr	x20, [x20, _CSR1@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh233:
	adrp	x21, _CSR1_SOFT_RESET@GOTPAGE
Lloh234:
	ldr	x21, [x21, _CSR1_SOFT_RESET@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh235:
	adrp	x8, _CSR1_BBP_RESET@GOTPAGE
Lloh236:
	ldr	x8, [x8, _CSR1_BBP_RESET@GOTPAGEOFF]
Lloh237:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
Lloh238:
	adrp	x22, _CSR1_HOST_READY@GOTPAGE
Lloh239:
	ldr	x22, [x22, _CSR1_HOST_READY@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
	ldr	w1, [x21]
	add	x0, sp, #12
	mov	w2, #0
	bl	_rt2x00_set_field32
	ldr	w1, [x22]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh240:
	adrp	x8, _CNT0@GOTPAGE
Lloh241:
	ldr	x8, [x8, _CNT0@GOTPAGEOFF]
Lloh242:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh243:
	adrp	x8, _CNT4@GOTPAGE
Lloh244:
	ldr	x8, [x8, _CNT4@GOTPAGEOFF]
Lloh245:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	mov	w0, #0
LBB0_3:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh188, Lloh189, Lloh190
	.loh AdrpLdrGotLdr	Lloh185, Lloh186, Lloh187
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGotLdr	Lloh179, Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGotLdr	Lloh173, Lloh174, Lloh175
	.loh AdrpLdrGotLdr	Lloh170, Lloh171, Lloh172
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGot	Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGot	Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGot	Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGot	Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh191, Lloh192, Lloh193
	.loh AdrpLdrGotLdr	Lloh243, Lloh244, Lloh245
	.loh AdrpLdrGotLdr	Lloh240, Lloh241, Lloh242
	.loh AdrpLdrGot	Lloh238, Lloh239
	.loh AdrpLdrGotLdr	Lloh235, Lloh236, Lloh237
	.loh AdrpLdrGot	Lloh233, Lloh234
	.loh AdrpLdrGot	Lloh231, Lloh232
	.loh AdrpLdrGotLdr	Lloh228, Lloh229, Lloh230
	.loh AdrpLdrGotLdr	Lloh225, Lloh226, Lloh227
	.loh AdrpLdrGotLdr	Lloh222, Lloh223, Lloh224
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGot	Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh202, Lloh203, Lloh204
	.loh AdrpLdrGot	Lloh200, Lloh201
	.loh AdrpLdrGotLdr	Lloh197, Lloh198, Lloh199
	.loh AdrpLdrGotLdr	Lloh194, Lloh195, Lloh196
	.cfi_endproc
                                        ; -- End function
	.comm	_PSCSR0,4,2                     ; @PSCSR0
	.comm	_PSCSR1,4,2                     ; @PSCSR1
	.comm	_PSCSR2,4,2                     ; @PSCSR2
	.comm	_PSCSR3,4,2                     ; @PSCSR3
	.comm	_TIMECSR,4,2                    ; @TIMECSR
	.comm	_TIMECSR_US_COUNT,4,2           ; @TIMECSR_US_COUNT
	.comm	_TIMECSR_US_64_COUNT,4,2        ; @TIMECSR_US_64_COUNT
	.comm	_TIMECSR_BEACON_EXPECT,4,2      ; @TIMECSR_BEACON_EXPECT
	.comm	_CSR9,4,2                       ; @CSR9
	.comm	_CSR9_MAX_FRAME_UNIT,4,2        ; @CSR9_MAX_FRAME_UNIT
	.comm	_CSR11,4,2                      ; @CSR11
	.comm	_CSR11_CW_SELECT,4,2            ; @CSR11_CW_SELECT
	.comm	_CSR14,4,2                      ; @CSR14
	.comm	_CSR14_TSF_COUNT,4,2            ; @CSR14_TSF_COUNT
	.comm	_CSR14_TSF_SYNC,4,2             ; @CSR14_TSF_SYNC
	.comm	_CSR14_TBCN,4,2                 ; @CSR14_TBCN
	.comm	_CSR14_TCFP,4,2                 ; @CSR14_TCFP
	.comm	_CSR14_TATIMW,4,2               ; @CSR14_TATIMW
	.comm	_CSR14_BEACON_GEN,4,2           ; @CSR14_BEACON_GEN
	.comm	_CSR14_CFP_COUNT_PRELOAD,4,2    ; @CSR14_CFP_COUNT_PRELOAD
	.comm	_CSR14_TBCM_PRELOAD,4,2         ; @CSR14_TBCM_PRELOAD
	.comm	_CNT3,4,2                       ; @CNT3
	.comm	_TXCSR8,4,2                     ; @TXCSR8
	.comm	_TXCSR8_BBP_ID0,4,2             ; @TXCSR8_BBP_ID0
	.comm	_TXCSR8_BBP_ID0_VALID,4,2       ; @TXCSR8_BBP_ID0_VALID
	.comm	_TXCSR8_BBP_ID1,4,2             ; @TXCSR8_BBP_ID1
	.comm	_TXCSR8_BBP_ID1_VALID,4,2       ; @TXCSR8_BBP_ID1_VALID
	.comm	_TXCSR8_BBP_ID2,4,2             ; @TXCSR8_BBP_ID2
	.comm	_TXCSR8_BBP_ID2_VALID,4,2       ; @TXCSR8_BBP_ID2_VALID
	.comm	_TXCSR8_BBP_ID3,4,2             ; @TXCSR8_BBP_ID3
	.comm	_TXCSR8_BBP_ID3_VALID,4,2       ; @TXCSR8_BBP_ID3_VALID
	.comm	_ARTCSR0,4,2                    ; @ARTCSR0
	.comm	_ARTCSR0_ACK_CTS_1MBS,4,2       ; @ARTCSR0_ACK_CTS_1MBS
	.comm	_ARTCSR0_ACK_CTS_2MBS,4,2       ; @ARTCSR0_ACK_CTS_2MBS
	.comm	_ARTCSR0_ACK_CTS_5_5MBS,4,2     ; @ARTCSR0_ACK_CTS_5_5MBS
	.comm	_ARTCSR0_ACK_CTS_11MBS,4,2      ; @ARTCSR0_ACK_CTS_11MBS
	.comm	_ARTCSR1,4,2                    ; @ARTCSR1
	.comm	_ARTCSR1_ACK_CTS_6MBS,4,2       ; @ARTCSR1_ACK_CTS_6MBS
	.comm	_ARTCSR1_ACK_CTS_9MBS,4,2       ; @ARTCSR1_ACK_CTS_9MBS
	.comm	_ARTCSR1_ACK_CTS_12MBS,4,2      ; @ARTCSR1_ACK_CTS_12MBS
	.comm	_ARTCSR1_ACK_CTS_18MBS,4,2      ; @ARTCSR1_ACK_CTS_18MBS
	.comm	_ARTCSR2,4,2                    ; @ARTCSR2
	.comm	_ARTCSR2_ACK_CTS_24MBS,4,2      ; @ARTCSR2_ACK_CTS_24MBS
	.comm	_ARTCSR2_ACK_CTS_36MBS,4,2      ; @ARTCSR2_ACK_CTS_36MBS
	.comm	_ARTCSR2_ACK_CTS_48MBS,4,2      ; @ARTCSR2_ACK_CTS_48MBS
	.comm	_ARTCSR2_ACK_CTS_54MBS,4,2      ; @ARTCSR2_ACK_CTS_54MBS
	.comm	_RXCSR3,4,2                     ; @RXCSR3
	.comm	_RXCSR3_BBP_ID0,4,2             ; @RXCSR3_BBP_ID0
	.comm	_RXCSR3_BBP_ID0_VALID,4,2       ; @RXCSR3_BBP_ID0_VALID
	.comm	_RXCSR3_BBP_ID1,4,2             ; @RXCSR3_BBP_ID1
	.comm	_RXCSR3_BBP_ID1_VALID,4,2       ; @RXCSR3_BBP_ID1_VALID
	.comm	_RXCSR3_BBP_ID2,4,2             ; @RXCSR3_BBP_ID2
	.comm	_RXCSR3_BBP_ID2_VALID,4,2       ; @RXCSR3_BBP_ID2_VALID
	.comm	_RXCSR3_BBP_ID3,4,2             ; @RXCSR3_BBP_ID3
	.comm	_RXCSR3_BBP_ID3_VALID,4,2       ; @RXCSR3_BBP_ID3_VALID
	.comm	_PCICSR,4,2                     ; @PCICSR
	.comm	_PCICSR_BIG_ENDIAN,4,2          ; @PCICSR_BIG_ENDIAN
	.comm	_PCICSR_RX_TRESHOLD,4,2         ; @PCICSR_RX_TRESHOLD
	.comm	_PCICSR_TX_TRESHOLD,4,2         ; @PCICSR_TX_TRESHOLD
	.comm	_PCICSR_BURST_LENTH,4,2         ; @PCICSR_BURST_LENTH
	.comm	_PCICSR_ENABLE_CLK,4,2          ; @PCICSR_ENABLE_CLK
	.comm	_PCICSR_READ_MULTIPLE,4,2       ; @PCICSR_READ_MULTIPLE
	.comm	_PCICSR_WRITE_INVALID,4,2       ; @PCICSR_WRITE_INVALID
	.comm	_PWRCSR0,4,2                    ; @PWRCSR0
	.comm	_GPIOCSR,4,2                    ; @GPIOCSR
	.comm	_TESTCSR,4,2                    ; @TESTCSR
	.comm	_STATE_AWAKE,4,2                ; @STATE_AWAKE
	.comm	_EBUSY,4,2                      ; @EBUSY
	.comm	_MACCSR0,4,2                    ; @MACCSR0
	.comm	_MACCSR1,4,2                    ; @MACCSR1
	.comm	_MACCSR2,4,2                    ; @MACCSR2
	.comm	_MACCSR2_DELAY,4,2              ; @MACCSR2_DELAY
	.comm	_RALINKCSR,4,2                  ; @RALINKCSR
	.comm	_RALINKCSR_AR_BBP_DATA0,4,2     ; @RALINKCSR_AR_BBP_DATA0
	.comm	_RALINKCSR_AR_BBP_ID0,4,2       ; @RALINKCSR_AR_BBP_ID0
	.comm	_RALINKCSR_AR_BBP_VALID0,4,2    ; @RALINKCSR_AR_BBP_VALID0
	.comm	_RALINKCSR_AR_BBP_DATA1,4,2     ; @RALINKCSR_AR_BBP_DATA1
	.comm	_RALINKCSR_AR_BBP_ID1,4,2       ; @RALINKCSR_AR_BBP_ID1
	.comm	_RALINKCSR_AR_BBP_VALID1,4,2    ; @RALINKCSR_AR_BBP_VALID1
	.comm	_BBPCSR1,4,2                    ; @BBPCSR1
	.comm	_TXACKCSR0,4,2                  ; @TXACKCSR0
	.comm	_CSR1,4,2                       ; @CSR1
	.comm	_CSR1_SOFT_RESET,4,2            ; @CSR1_SOFT_RESET
	.comm	_CSR1_BBP_RESET,4,2             ; @CSR1_BBP_RESET
	.comm	_CSR1_HOST_READY,4,2            ; @CSR1_HOST_READY
	.comm	_CNT0,4,2                       ; @CNT0
	.comm	_CNT4,4,2                       ; @CNT4
	.no_dead_strip	_rt2500pci_init_registers
.subsections_via_symbols
