	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlxsw_sp1_from_ptys_supported_port
_mlxsw_sp1_from_ptys_supported_port:    ## @mlxsw_sp1_from_ptys_supported_port
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPCREL(%rip), %rax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	%rdx, %r14
	movl	%esi, %ebx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%esi, %ecx
	je	LBB0_2
## %bb.1:
	movq	_supported@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FIBRE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ethtool_link_ksettings_add_link_mode
LBB0_2:
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPCREL(%rip), %rax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%ebx, %ecx
	je	LBB0_3
## %bb.4:
	movq	_supported@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_Backplane@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_ethtool_link_ksettings_add_link_mode ## TAILCALL
LBB0_3:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_SGMII,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_SGMII
	.comm	_supported,4,2                  ## @supported
	.comm	_FIBRE,4,2                      ## @FIBRE
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX
	.comm	_Backplane,4,2                  ## @Backplane
	.no_dead_strip	_mlxsw_sp1_from_ptys_supported_port
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlxsw_sp1_from_ptys_supported_port
_mlxsw_sp1_from_ptys_supported_port:    ; @mlxsw_sp1_from_ptys_supported_port
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x20, x1
Lloh0:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPAGE
Lloh4:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
Lloh6:
	adrp	x10, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPAGE
Lloh7:
	ldr	x10, [x10, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh8:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPAGE
Lloh16:
	ldr	x10, [x10, _MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh17:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh18:
	adrp	x21, _supported@GOTPAGE
Lloh19:
	ldr	x21, [x21, _supported@GOTPAGEOFF]
	tst	w8, w1
	b.eq	LBB0_2
; %bb.1:
	ldr	w1, [x21]
Lloh20:
	adrp	x8, _FIBRE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _FIBRE@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ethtool_link_ksettings_add_link_mode
LBB0_2:
Lloh23:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
Lloh26:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPAGE
Lloh27:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
Lloh29:
	adrp	x10, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPAGE
Lloh30:
	ldr	x10, [x10, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPAGEOFF]
	orr	w8, w9, w8
Lloh31:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh32:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPAGE
Lloh33:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh35:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX@GOTPAGE
Lloh36:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w20
	b.eq	LBB0_4
; %bb.3:
	ldr	w1, [x21]
Lloh38:
	adrp	x8, _Backplane@GOTPAGE
Lloh39:
	ldr	x8, [x8, _Backplane@GOTPAGEOFF]
Lloh40:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_ethtool_link_ksettings_add_link_mode
LBB0_4:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_SGMII,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_SGMII
	.comm	_supported,4,2                  ; @supported
	.comm	_FIBRE,4,2                      ; @FIBRE
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX
	.comm	_Backplane,4,2                  ; @Backplane
	.no_dead_strip	_mlxsw_sp1_from_ptys_supported_port
.subsections_via_symbols
