	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rvu_enable_afvf_intr
_rvu_enable_afvf_intr:                  ## @rvu_enable_afvf_intr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %r15d
	xorl	%edi, %edi
	callq	_RVU_PF_VFPF_MBOX_INTX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	xorl	%edi, %edi
	callq	_RVU_PF_VFPF_MBOX_INT_ENA_W1SX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	xorl	%edi, %edi
	callq	_RVU_PF_VFFLR_INTX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	xorl	%edi, %edi
	callq	_RVU_PF_VFFLR_INT_ENA_W1SX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	xorl	%edi, %edi
	callq	_RVU_PF_VFME_INT_ENA_W1SX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	cmpl	$65, %r15d
	jge	LBB0_2
## %bb.1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movl	$1, %edi
	callq	_RVU_PF_VFPF_MBOX_INTX
	movl	%eax, %ebx
	addl	$-64, %r15d
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	movl	$1, %edi
	callq	_RVU_PF_VFPF_MBOX_INT_ENA_W1SX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	movl	$1, %edi
	callq	_RVU_PF_VFFLR_INTX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	movl	$1, %edi
	callq	_RVU_PF_VFFLR_INT_ENA_W1SX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_rvupf_write64
	movl	$1, %edi
	callq	_RVU_PF_VFME_INT_ENA_W1SX
	movl	%eax, %ebx
	movl	%r15d, %edi
	callq	_INTR_MASK
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rvupf_write64                  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_rvu_enable_afvf_intr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rvu_enable_afvf_intr
_rvu_enable_afvf_intr:                  ; @rvu_enable_afvf_intr
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w20, [x0]
	mov	w0, #0
	bl	_RVU_PF_VFPF_MBOX_INTX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #0
	bl	_RVU_PF_VFPF_MBOX_INT_ENA_W1SX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #0
	bl	_RVU_PF_VFFLR_INTX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #0
	bl	_RVU_PF_VFFLR_INT_ENA_W1SX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #0
	bl	_RVU_PF_VFME_INT_ENA_W1SX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	cmp	w20, #65
	b.ge	LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	w0, #1
	bl	_RVU_PF_VFPF_MBOX_INTX
	mov	x21, x0
	sub	w20, w20, #64
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #1
	bl	_RVU_PF_VFPF_MBOX_INT_ENA_W1SX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #1
	bl	_RVU_PF_VFFLR_INTX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #1
	bl	_RVU_PF_VFFLR_INT_ENA_W1SX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rvupf_write64
	mov	w0, #1
	bl	_RVU_PF_VFME_INT_ENA_W1SX
	mov	x21, x0
	mov	x0, x20
	bl	_INTR_MASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_rvupf_write64
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_rvu_enable_afvf_intr
.subsections_via_symbols
