	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function miphy28lp_init_pcie
_miphy28lp_init_pcie:                   ## @miphy28lp_init_pcie
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	8(%rdi), %rax
	movq	_SYSCFG_SATA@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rcx
	cmpl	$0, (%rax,%rcx,4)
	je	LBB0_4
## %bb.1:
	movq	_SYSCFG_PCI@GOTPCREL(%rip), %r12
	movq	(%r12), %rcx
	cmpl	$0, (%rax,%rcx,4)
	je	LBB0_4
## %bb.2:
	movq	%rdi, %r14
	movl	16(%rdi), %edx
	testl	%edx, %edx
	je	LBB0_4
## %bb.3:
	cmpq	$0, (%r14)
	je	LBB0_4
## %bb.5:
	movq	24(%r14), %r15
	movl	(%r15), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_info
	movl	4(%r15), %edi
	movq	8(%r14), %rax
	movq	(%rbx), %rcx
	movl	(%rax,%rcx,4), %esi
	movq	_SATA_CTRL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SATA_CTRL_SELECT_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	callq	_regmap_update_bits
	movl	4(%r15), %edi
	movq	8(%r14), %rax
	movq	(%r12), %rcx
	movl	(%rax,%rcx,4), %esi
	movq	_PCIE_CTRL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_SYSCFG_PCIE_PCIE_VAL@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	callq	_regmap_update_bits
	movq	_MIPHY_CTRL_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_miphy28lp_setup
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %ebx
	movl	(%r15), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_8
LBB0_4:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_8:
	movl	%ebx, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movq	%r14, %rdi
	callq	_miphy28lp_configure_pcie
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_8
## %bb.9:
	movl	$260, %esi                      ## imm = 0x104
	addq	(%r14), %rsi
	movl	$104, %edi
	callq	_writeb_relaxed
	movl	$261, %esi                      ## imm = 0x105
	addq	(%r14), %rsi
	movl	$97, %edi
	callq	_writeb_relaxed
	movl	$264, %esi                      ## imm = 0x108
	addq	(%r14), %rsi
	movl	$104, %edi
	callq	_writeb_relaxed
	movl	$265, %esi                      ## imm = 0x109
	addq	(%r14), %rsi
	movl	$97, %edi
	callq	_writeb_relaxed
	movl	$268, %esi                      ## imm = 0x10C
	addq	(%r14), %rsi
	movl	$104, %edi
	callq	_writeb_relaxed
	movl	$269, %esi                      ## imm = 0x10D
	addq	(%r14), %rsi
	movl	$96, %edi
	callq	_writeb_relaxed
	movq	%r14, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_miphy_is_ready                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_SYSCFG_SATA,8,3                ## @SYSCFG_SATA
	.comm	_SYSCFG_PCI,8,3                 ## @SYSCFG_PCI
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"pcie-up mode, addr 0x%p\n"

	.comm	_SATA_CTRL_MASK,4,2             ## @SATA_CTRL_MASK
	.comm	_SATA_CTRL_SELECT_PCIE,4,2      ## @SATA_CTRL_SELECT_PCIE
	.comm	_PCIE_CTRL_MASK,4,2             ## @PCIE_CTRL_MASK
	.comm	_SYSCFG_PCIE_PCIE_VAL,4,2       ## @SYSCFG_PCIE_PCIE_VAL
	.comm	_MIPHY_CTRL_DEFAULT,4,2         ## @MIPHY_CTRL_DEFAULT
L_.str.1:                               ## @.str.1
	.asciz	"PCIe phy setup failed\n"

	.no_dead_strip	_miphy28lp_init_pcie
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function miphy28lp_init_pcie
_miphy28lp_init_pcie:                   ; @miphy28lp_init_pcie
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	ldr	x8, [x0, #8]
Lloh0:
	adrp	x22, _SYSCFG_SATA@GOTPAGE
Lloh1:
	ldr	x22, [x22, _SYSCFG_SATA@GOTPAGEOFF]
	ldr	x9, [x22]
	ldr	w9, [x8, x9, lsl #2]
	cbz	w9, LBB0_6
; %bb.1:
Lloh2:
	adrp	x20, _SYSCFG_PCI@GOTPAGE
Lloh3:
	ldr	x20, [x20, _SYSCFG_PCI@GOTPAGEOFF]
	ldr	x9, [x20]
	ldr	w8, [x8, x9, lsl #2]
	cbz	w8, LBB0_6
; %bb.2:
	mov	x19, x0
	ldr	w2, [x0, #16]
	cbz	w2, LBB0_6
; %bb.3:
	ldr	x8, [x19]
	cbz	x8, LBB0_6
; %bb.4:
	ldr	x21, [x19, #24]
	ldr	w0, [x21]
Lloh4:
	adrp	x1, l_.str@PAGE
Lloh5:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_info
	ldr	w0, [x21, #4]
	ldr	x8, [x19, #8]
	ldr	x9, [x22]
	ldr	w1, [x8, x9, lsl #2]
Lloh6:
	adrp	x8, _SATA_CTRL_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SATA_CTRL_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
Lloh9:
	adrp	x8, _SATA_CTRL_SELECT_PCIE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SATA_CTRL_SELECT_PCIE@GOTPAGEOFF]
Lloh11:
	ldr	w3, [x8]
	bl	_regmap_update_bits
	ldr	w0, [x21, #4]
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	ldr	w1, [x8, x9, lsl #2]
Lloh12:
	adrp	x8, _PCIE_CTRL_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PCIE_CTRL_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w2, [x8]
Lloh15:
	adrp	x8, _SYSCFG_PCIE_PCIE_VAL@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SYSCFG_PCIE_PCIE_VAL@GOTPAGEOFF]
Lloh17:
	ldr	w3, [x8]
	bl	_regmap_update_bits
Lloh18:
	adrp	x8, _MIPHY_CTRL_DEFAULT@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MIPHY_CTRL_DEFAULT@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_miphy28lp_setup
	cbz	w0, LBB0_8
; %bb.5:
	mov	x20, x0
	ldr	w0, [x21]
Lloh21:
	adrp	x1, l_.str.1@PAGE
Lloh22:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	b	LBB0_7
LBB0_6:
Lloh23:
	adrp	x8, _EINVAL@GOTPAGE
Lloh24:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	neg	w20, w8
LBB0_7:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_8:
	mov	x0, x19
	bl	_miphy28lp_configure_pcie
	mov	x20, x0
	cbnz	w0, LBB0_7
; %bb.9:
	ldr	x8, [x19]
	add	x1, x8, #260
	mov	w0, #104
	bl	_writeb_relaxed
	ldr	x8, [x19]
	add	x1, x8, #261
	mov	w0, #97
	bl	_writeb_relaxed
	ldr	x8, [x19]
	add	x1, x8, #264
	mov	w0, #104
	bl	_writeb_relaxed
	ldr	x8, [x19]
	add	x1, x8, #265
	mov	w0, #97
	bl	_writeb_relaxed
	ldr	x8, [x19]
	add	x1, x8, #268
	mov	w0, #104
	bl	_writeb_relaxed
	ldr	x8, [x19]
	add	x1, x8, #269
	mov	w0, #96
	bl	_writeb_relaxed
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_miphy_is_ready
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.cfi_endproc
                                        ; -- End function
	.comm	_SYSCFG_SATA,8,3                ; @SYSCFG_SATA
	.comm	_SYSCFG_PCI,8,3                 ; @SYSCFG_PCI
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"pcie-up mode, addr 0x%p\n"

	.comm	_SATA_CTRL_MASK,4,2             ; @SATA_CTRL_MASK
	.comm	_SATA_CTRL_SELECT_PCIE,4,2      ; @SATA_CTRL_SELECT_PCIE
	.comm	_PCIE_CTRL_MASK,4,2             ; @PCIE_CTRL_MASK
	.comm	_SYSCFG_PCIE_PCIE_VAL,4,2       ; @SYSCFG_PCIE_PCIE_VAL
	.comm	_MIPHY_CTRL_DEFAULT,4,2         ; @MIPHY_CTRL_DEFAULT
l_.str.1:                               ; @.str.1
	.asciz	"PCIe phy setup failed\n"

	.no_dead_strip	_miphy28lp_init_pcie
.subsections_via_symbols
