	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vxge_config_vpaths
_vxge_config_vpaths:                    ## @vxge_config_vpaths
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r15
	movl	%esi, %r13d
	movq	%rdi, -56(%rbp)                 ## 8-byte Spill
	movq	_driver_config@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rcx
	movl	(%rcx), %ebx
	movq	_VXGE_USE_DEFAULT@GOTPCREL(%rip), %rdx
	movl	%ebx, %eax
	cmpl	(%rdx), %ebx
	movl	%ebx, -60(%rbp)                 ## 4-byte Spill
	jne	LBB0_13
## %bb.1:
	movq	_max_config_dev@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	_VXGE_MAX_CONFIG_DEV@GOTPCREL(%rip), %rsi
	movl	%ebx, %eax
	cmpq	(%rsi), %rdx
	jne	LBB0_13
## %bb.2:
	movl	4(%rcx), %eax
	cmpl	$-1, %eax
	je	LBB0_8
## %bb.3:
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	testl	%eax, %eax
	jne	LBB0_5
## %bb.4:
	xorl	%eax, %eax
	callq	_netif_get_num_default_rss_queues
	movq	_driver_config@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, 4(%rcx)
LBB0_5:
	movl	%eax, %edx
	sarl	%edx
	cmpl	$2, %eax
	movl	$1, %eax
	cmovael	%edx, %eax
	movl	%eax, (%rcx)
	movq	_VXGE_HW_MAX_VIRTUAL_PATHS@GOTPCREL(%rip), %r12
	cmpl	$0, (%r12)
	jle	LBB0_9
## %bb.6:
	xorl	%ebx, %ebx
	xorl	%r14d, %r14d
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	%r13d, %edi
	movl	%ebx, %esi
	movl	$1, %edx
	callq	_vxge_bVALn
	cmpl	$1, %eax
	sbbl	$-1, %r14d
	incl	%ebx
	cmpl	(%r12), %ebx
	jl	LBB0_7
	jmp	LBB0_10
LBB0_8:
	xorl	%r12d, %r12d
	jmp	LBB0_29
LBB0_9:
	xorl	%r14d, %r14d
LBB0_10:
	movq	_driver_config@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rax
	movl	(%rax), %ecx
	cmpl	%ecx, %r14d
	jge	LBB0_12
## %bb.11:
	movl	%r14d, (%rax)
	movl	%r14d, %ecx
LBB0_12:
	movl	4(%rax), %edx
	addl	%ecx, %ecx
	subl	%ecx, %edx
	testl	%edx, %edx
	movl	$-1, %ecx
	cmovgl	%edx, %ecx
	movl	%ecx, 4(%rax)
	movq	(%rdi), %rax
	movl	(%rax), %eax
	movl	-44(%rbp), %r13d                ## 4-byte Reload
LBB0_13:
	cmpl	$1, %eax
	jne	LBB0_15
## %bb.14:
	movq	_VXGE_TRACE@GOTPCREL(%rip), %rax
	movq	%rdi, %r14
	movl	(%rax), %edi
	movq	_VXGE_DRIVER_NAME@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	L_.str(%rip), %rsi
	xorl	%eax, %eax
	callq	_vxge_debug_ll_config
	movq	%r14, %rdi
	movq	_NO_STEERING@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r15)
	movq	%rax, (%r15)
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	$0, 8(%rax)
LBB0_15:
	movq	_VXGE_HW_MAX_VIRTUAL_PATHS@GOTPCREL(%rip), %rbx
	cmpl	$0, (%rbx)
	jle	LBB0_26
## %bb.16:
	movq	_bw_percentage@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	$216, %ecx
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	addq	(%rdx), %rcx
	xorl	%edx, %edx
	.p2align	4, 0x90
LBB0_17:                                ## =>This Inner Loop Header: Depth=1
	movl	(%rax,%rdx,4), %esi
	movl	%esi, (%rcx)
	incq	%rdx
	movslq	(%rbx), %rsi
	addq	$224, %rcx
	cmpq	%rsi, %rdx
	jl	LBB0_17
## %bb.18:
	testl	%esi, %esi
	jle	LBB0_26
## %bb.19:
	movl	%r13d, -44(%rbp)                ## 4-byte Spill
	xorl	%r14d, %r14d
	xorl	%r15d, %r15d
	xorl	%r12d, %r12d
	jmp	LBB0_22
	.p2align	4, 0x90
LBB0_20:                                ##   in Loop: Header=BB0_22 Depth=1
	leaq	L_.str.2(%rip), %rsi
	movl	%r15d, %ecx
	xorl	%eax, %eax
	callq	_vxge_debug_ll_config
	movq	_VXGE_HW_FIFO_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-56(%rbp), %rcx                 ## 8-byte Reload
	movq	(%rcx), %rsi
	movl	%eax, 208(%rsi,%r14)
	movq	_MAX_SKB_FRAGS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leal	1(%rax), %ecx
	movl	%ecx, 192(%rsi,%r14)
	movq	_VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %ecx
	movl	%ecx, 196(%rsi,%r14)
	leal	4(,%rax,4), %ecx
	movl	(%rdx), %eax
	cltd
	idivl	%ecx
	movl	%eax, %ecx
	movq	_VXGE_DEF_FIFO_LENGTH@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	decl	%eax
	cltd
	idivl	%ecx
	incl	%eax
	movl	%eax, 200(%rsi,%r14)
	movq	_VXGE_HW_FIFO_QUEUE_INTR_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 204(%rsi,%r14)
	movq	_VXGE_HW_TIM_INTR_ENABLE@GOTPCREL(%rip), %r8
	movq	(%r8), %rax
	movq	%rax, 184(%rsi,%r14)
	movq	_VXGE_TTI_BTIMER_VAL@GOTPCREL(%rip), %rax
	imull	$1000, (%rax), %eax             ## imm = 0x3E8
	cltq
	imulq	$2021161081, %rax, %rax         ## imm = 0x78787879
	movq	%rax, %rcx
	shrq	$63, %rcx
	shrq	$32, %rax
	sarl	$7, %eax
	addl	%ecx, %eax
	movl	%eax, 112(%rsi,%r14)
	movq	_VXGE_HW_TIM_TIMER_AC_ENABLE@GOTPCREL(%rip), %r9
	movq	(%r9), %rax
	movq	%rax, 176(%rsi,%r14)
	movq	%rbx, %rdx
	movq	_VXGE_HW_TIM_TIMER_CI_DISABLE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rax
	movq	%rax, 168(%rsi,%r14)
	movq	_VXGE_HW_TIM_TIMER_RI_DISABLE@GOTPCREL(%rip), %rdi
	movq	(%rdi), %rax
	movq	%rax, 160(%rsi,%r14)
	movq	_VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 152(%rsi,%r14)
	movq	_VXGE_TTI_LTIMER_VAL@GOTPCREL(%rip), %rax
	imull	$1000, (%rax), %eax             ## imm = 0x3E8
	cltq
	imulq	$2021161081, %rax, %rax         ## imm = 0x78787879
	movq	%rax, %rcx
	shrq	$63, %rcx
	shrq	$32, %rax
	sarl	$7, %eax
	addl	%ecx, %eax
	movl	%eax, 116(%rsi,%r14)
	movq	_VXGE_TTI_RTIMER_VAL@GOTPCREL(%rip), %rax
	imull	$1000, (%rax), %eax             ## imm = 0x3E8
	cltq
	imulq	$2021161081, %rax, %rax         ## imm = 0x78787879
	movq	%rax, %rcx
	shrq	$63, %rcx
	shrq	$32, %rax
	sarl	$7, %eax
	addl	%ecx, %eax
	movl	%eax, 120(%rsi,%r14)
	movq	_TTI_TX_URANGE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 148(%rsi,%r14)
	movq	_TTI_TX_URANGE_B@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 144(%rsi,%r14)
	movq	_TTI_TX_URANGE_C@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 140(%rsi,%r14)
	movq	_TTI_TX_UFC_A@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 136(%rsi,%r14)
	movq	_TTI_TX_UFC_B@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 132(%rsi,%r14)
	movq	_TTI_TX_UFC_C@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 128(%rsi,%r14)
	movq	_TTI_TX_UFC_D@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 124(%rsi,%r14)
	movq	_VXGE_HW_RING_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 104(%rsi,%r14)
	movq	_VXGE_HW_DEF_RING_BLOCKS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 100(%rsi,%r14)
	movq	_VXGE_HW_RING_RXD_BUFFER_MODE_1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 96(%rsi,%r14)
	movq	_VXGE_HW_DEF_RING_RXDS_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 92(%rsi,%r14)
	movq	_VXGE_HW_RING_SCATTER_MODE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 88(%rsi,%r14)
	movq	(%r8), %rax
	movq	%rax, 80(%rsi,%r14)
	movq	_VXGE_RTI_BTIMER_VAL@GOTPCREL(%rip), %rax
	imull	$1000, (%rax), %eax             ## imm = 0x3E8
	cltq
	imulq	$2021161081, %rax, %rax         ## imm = 0x78787879
	movq	%rax, %rcx
	shrq	$63, %rcx
	shrq	$32, %rax
	sarl	$7, %eax
	addl	%ecx, %eax
	movl	%eax, 8(%rsi,%r14)
	movq	(%r9), %rax
	movq	%rax, 72(%rsi,%r14)
	movq	(%rbx), %rax
	movq	%rdx, %rbx
	movq	%rax, 64(%rsi,%r14)
	movq	(%rdi), %rax
	movq	%rax, 56(%rsi,%r14)
	movq	_VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 48(%rsi,%r14)
	movq	_RTI_RX_URANGE_A@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 44(%rsi,%r14)
	movq	_RTI_RX_URANGE_B@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 40(%rsi,%r14)
	movq	_RTI_RX_URANGE_C@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rsi,%r14)
	movq	_RTI_RX_UFC_A@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 32(%rsi,%r14)
	movq	_RTI_RX_UFC_B@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 28(%rsi,%r14)
	movq	_RTI_RX_UFC_C@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 24(%rsi,%r14)
	movq	_RTI_RX_UFC_D@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 20(%rsi,%r14)
	movq	_VXGE_RTI_RTIMER_VAL@GOTPCREL(%rip), %rax
	imull	$1000, (%rax), %eax             ## imm = 0x3E8
	cltq
	imulq	$2021161081, %rax, %rax         ## imm = 0x78787879
	movq	%rax, %rcx
	shrq	$63, %rcx
	shrq	$32, %rax
	sarl	$7, %eax
	addl	%ecx, %eax
	movl	%eax, 12(%rsi,%r14)
	movq	_VXGE_RTI_LTIMER_VAL@GOTPCREL(%rip), %rax
	imull	$1000, (%rax), %eax             ## imm = 0x3E8
	cltq
	imulq	$2021161081, %rax, %rax         ## imm = 0x78787879
	movq	%rax, %rcx
	shrq	$63, %rcx
	shrq	$32, %rax
	sarl	$7, %eax
	addl	%ecx, %eax
	movl	%eax, 16(%rsi,%r14)
	movq	_vlan_tag_strip@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%rsi,%r14)
	incl	%r12d
LBB0_21:                                ##   in Loop: Header=BB0_22 Depth=1
	incq	%r15
	movslq	(%rbx), %rax
	addq	$224, %r14
	cmpq	%rax, %r15
	movq	%r13, %rdi
	jge	LBB0_28
LBB0_22:                                ## =>This Inner Loop Header: Depth=1
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movl	%r15d, (%rax,%r14)
	movq	_VXGE_HW_DEFAULT_MTU@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, 212(%rax,%r14)
	movq	%rdi, %r13
	movq	(%rdi), %rax
	cmpl	(%rax), %r12d
	jge	LBB0_27
## %bb.23:                              ##   in Loop: Header=BB0_22 Depth=1
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	movl	%r15d, %esi
	movl	$1, %edx
	callq	_vxge_bVALn
	movq	_VXGE_TRACE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	movq	_VXGE_DRIVER_NAME@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	testl	%eax, %eax
	jne	LBB0_20
## %bb.24:                              ##   in Loop: Header=BB0_22 Depth=1
	leaq	L_.str.1(%rip), %rsi
	movl	%r15d, %ecx
	xorl	%eax, %eax
	callq	_vxge_debug_ll_config
	jmp	LBB0_21
LBB0_26:
	xorl	%r12d, %r12d
	jmp	LBB0_28
LBB0_27:
	movq	_VXGE_TRACE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_VXGE_DRIVER_NAME@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	leaq	L_.str.3(%rip), %rsi
	movl	%r15d, %ecx
	xorl	%eax, %eax
	callq	_vxge_debug_ll_config
	movq	%r13, %rdi
LBB0_28:
	movq	(%rdi), %rax
	movl	-60(%rbp), %ecx                 ## 4-byte Reload
	movl	%ecx, (%rax)
LBB0_29:
	movl	%r12d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_driver_config,8,3              ## @driver_config
	.comm	_VXGE_USE_DEFAULT,4,2           ## @VXGE_USE_DEFAULT
	.comm	_max_config_dev,8,3             ## @max_config_dev
	.comm	_VXGE_MAX_CONFIG_DEV,8,3        ## @VXGE_MAX_CONFIG_DEV
	.comm	_VXGE_HW_MAX_VIRTUAL_PATHS,4,2  ## @VXGE_HW_MAX_VIRTUAL_PATHS
	.comm	_VXGE_TRACE,4,2                 ## @VXGE_TRACE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s: Disable tx and rx steering, as single vpath is configured"

	.comm	_VXGE_DRIVER_NAME,4,2           ## @VXGE_DRIVER_NAME
	.comm	_NO_STEERING,8,3                ## @NO_STEERING
	.comm	_bw_percentage,8,3              ## @bw_percentage
	.comm	_VXGE_HW_DEFAULT_MTU,4,2        ## @VXGE_HW_DEFAULT_MTU
L_.str.1:                               ## @.str.1
	.asciz	"%s: vpath: %d is not available"

L_.str.2:                               ## @.str.2
	.asciz	"%s: vpath: %d available"

L_.str.3:                               ## @.str.3
	.asciz	"%s: vpath: %d is not configured, max_config_vpath exceeded"

	.comm	_VXGE_HW_FIFO_ENABLE,4,2        ## @VXGE_HW_FIFO_ENABLE
	.comm	_MAX_SKB_FRAGS,4,2              ## @MAX_SKB_FRAGS
	.comm	_VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE,4,2 ## @VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE
	.comm	_VXGE_DEF_FIFO_LENGTH,4,2       ## @VXGE_DEF_FIFO_LENGTH
	.comm	_VXGE_HW_FIFO_QUEUE_INTR_DISABLE,4,2 ## @VXGE_HW_FIFO_QUEUE_INTR_DISABLE
	.comm	_VXGE_HW_TIM_INTR_ENABLE,8,3    ## @VXGE_HW_TIM_INTR_ENABLE
	.comm	_VXGE_TTI_BTIMER_VAL,4,2        ## @VXGE_TTI_BTIMER_VAL
	.comm	_VXGE_HW_TIM_TIMER_AC_ENABLE,8,3 ## @VXGE_HW_TIM_TIMER_AC_ENABLE
	.comm	_VXGE_HW_TIM_TIMER_CI_DISABLE,8,3 ## @VXGE_HW_TIM_TIMER_CI_DISABLE
	.comm	_VXGE_HW_TIM_TIMER_RI_DISABLE,8,3 ## @VXGE_HW_TIM_TIMER_RI_DISABLE
	.comm	_VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL,4,2 ## @VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL
	.comm	_VXGE_TTI_LTIMER_VAL,4,2        ## @VXGE_TTI_LTIMER_VAL
	.comm	_VXGE_TTI_RTIMER_VAL,4,2        ## @VXGE_TTI_RTIMER_VAL
	.comm	_TTI_TX_URANGE_A,4,2            ## @TTI_TX_URANGE_A
	.comm	_TTI_TX_URANGE_B,4,2            ## @TTI_TX_URANGE_B
	.comm	_TTI_TX_URANGE_C,4,2            ## @TTI_TX_URANGE_C
	.comm	_TTI_TX_UFC_A,4,2               ## @TTI_TX_UFC_A
	.comm	_TTI_TX_UFC_B,4,2               ## @TTI_TX_UFC_B
	.comm	_TTI_TX_UFC_C,4,2               ## @TTI_TX_UFC_C
	.comm	_TTI_TX_UFC_D,4,2               ## @TTI_TX_UFC_D
	.comm	_VXGE_HW_RING_ENABLE,4,2        ## @VXGE_HW_RING_ENABLE
	.comm	_VXGE_HW_DEF_RING_BLOCKS,4,2    ## @VXGE_HW_DEF_RING_BLOCKS
	.comm	_VXGE_HW_RING_RXD_BUFFER_MODE_1,4,2 ## @VXGE_HW_RING_RXD_BUFFER_MODE_1
	.comm	_VXGE_HW_DEF_RING_RXDS_LIMIT,4,2 ## @VXGE_HW_DEF_RING_RXDS_LIMIT
	.comm	_VXGE_HW_RING_SCATTER_MODE_A,4,2 ## @VXGE_HW_RING_SCATTER_MODE_A
	.comm	_VXGE_RTI_BTIMER_VAL,4,2        ## @VXGE_RTI_BTIMER_VAL
	.comm	_VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL,4,2 ## @VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL
	.comm	_RTI_RX_URANGE_A,4,2            ## @RTI_RX_URANGE_A
	.comm	_RTI_RX_URANGE_B,4,2            ## @RTI_RX_URANGE_B
	.comm	_RTI_RX_URANGE_C,4,2            ## @RTI_RX_URANGE_C
	.comm	_RTI_RX_UFC_A,4,2               ## @RTI_RX_UFC_A
	.comm	_RTI_RX_UFC_B,4,2               ## @RTI_RX_UFC_B
	.comm	_RTI_RX_UFC_C,4,2               ## @RTI_RX_UFC_C
	.comm	_RTI_RX_UFC_D,4,2               ## @RTI_RX_UFC_D
	.comm	_VXGE_RTI_RTIMER_VAL,4,2        ## @VXGE_RTI_RTIMER_VAL
	.comm	_VXGE_RTI_LTIMER_VAL,4,2        ## @VXGE_RTI_LTIMER_VAL
	.comm	_vlan_tag_strip,4,2             ## @vlan_tag_strip
	.no_dead_strip	_vxge_config_vpaths
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vxge_config_vpaths
_vxge_config_vpaths:                    ; @vxge_config_vpaths
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x2
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x12, _driver_config@GOTPAGE
Lloh1:
	ldr	x12, [x12, _driver_config@GOTPAGEOFF]
	ldr	x8, [x12]
Lloh2:
	adrp	x9, _VXGE_USE_DEFAULT@GOTPAGE
Lloh3:
	ldr	x9, [x9, _VXGE_USE_DEFAULT@GOTPAGEOFF]
	ldr	w25, [x8]
Lloh4:
	ldr	w10, [x9]
Lloh5:
	adrp	x27, _VXGE_HW_MAX_VIRTUAL_PATHS@GOTPAGE
Lloh6:
	ldr	x27, [x27, _VXGE_HW_MAX_VIRTUAL_PATHS@GOTPAGEOFF]
	mov	x9, x25
	cmp	w25, w10
	b.ne	LBB0_13
; %bb.1:
Lloh7:
	adrp	x9, _max_config_dev@GOTPAGE
Lloh8:
	ldr	x9, [x9, _max_config_dev@GOTPAGEOFF]
Lloh9:
	ldr	x10, [x9]
Lloh10:
	adrp	x9, _VXGE_MAX_CONFIG_DEV@GOTPAGE
Lloh11:
	ldr	x9, [x9, _VXGE_MAX_CONFIG_DEV@GOTPAGEOFF]
Lloh12:
	ldr	x11, [x9]
	mov	x9, x25
	cmp	x10, x11
	b.ne	LBB0_13
; %bb.2:
	ldr	w0, [x8, #4]
	cmn	w0, #1
	b.eq	LBB0_8
; %bb.3:
	mov	x24, x12
	cbnz	w0, LBB0_5
; %bb.4:
	bl	_netif_get_num_default_rss_queues
	ldr	x8, [x24]
	str	w0, [x8, #4]
LBB0_5:
	asr	w9, w0, #1
	cmp	w0, #1
	csinc	w9, w9, wzr, hi
	str	w9, [x8]
	ldr	w8, [x27]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.6:
	mov	w22, #0
	mov	w23, #0
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x22
	mov	w2, #1
	bl	_vxge_bVALn
	cmp	w0, #0
	cinc	w23, w23, ne
	add	w22, w22, #1
	ldr	w8, [x27]
	cmp	w22, w8
	b.lt	LBB0_7
	b	LBB0_10
LBB0_8:
	mov	w21, #0
	b	LBB0_28
LBB0_9:
	mov	w23, #0
LBB0_10:
	mov	x12, x24
	ldr	x8, [x24]
	ldr	w9, [x8]
	cmp	w23, w9
	b.ge	LBB0_12
; %bb.11:
	str	w23, [x8]
	mov	x9, x23
LBB0_12:
	ldr	w10, [x8, #4]
	sub	w9, w10, w9, lsl #1
	cmp	w9, #1
	csinv	w9, w9, wzr, ge
	str	w9, [x8, #4]
	ldr	x8, [x12]
	ldr	w9, [x8]
LBB0_13:
	cmp	w9, #1
	b.ne	LBB0_15
; %bb.14:
Lloh13:
	adrp	x8, _VXGE_TRACE@GOTPAGE
Lloh14:
	ldr	x8, [x8, _VXGE_TRACE@GOTPAGEOFF]
Lloh15:
	ldr	w0, [x8]
Lloh16:
	adrp	x8, _VXGE_DRIVER_NAME@GOTPAGE
Lloh17:
	ldr	x8, [x8, _VXGE_DRIVER_NAME@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
Lloh19:
	adrp	x1, l_.str@PAGE
Lloh20:
	add	x1, x1, l_.str@PAGEOFF
	mov	x22, x12
	bl	_vxge_debug_ll_config
	mov	x12, x22
Lloh21:
	adrp	x8, _NO_STEERING@GOTPAGE
Lloh22:
	ldr	x8, [x8, _NO_STEERING@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
	stp	x8, x8, [x21]
	str	xzr, [x20, #8]
LBB0_15:
	str	w25, [sp, #12]                  ; 4-byte Folded Spill
	ldr	w8, [x27]
	cmp	w8, #1
	b.lt	LBB0_25
; %bb.16:
	mov	x8, #0
Lloh24:
	adrp	x9, _bw_percentage@GOTPAGE
Lloh25:
	ldr	x9, [x9, _bw_percentage@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	ldr	x10, [x20]
	add	x10, x10, #216
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	ldr	w11, [x9, x8, lsl #2]
	str	w11, [x10], #224
	add	x8, x8, #1
	ldrsw	x11, [x27]
	cmp	x8, x11
	b.lt	LBB0_17
; %bb.18:
	cmp	w11, #1
	b.lt	LBB0_25
; %bb.19:
	mov	x28, #0
	mov	x22, #0
	mov	w21, #0
	mov	w24, #1000
	mov	w26, #30841
	movk	w26, #30840, lsl #16
Lloh27:
	adrp	x25, _VXGE_HW_TIM_TIMER_RI_DISABLE@GOTPAGE
Lloh28:
	ldr	x25, [x25, _VXGE_HW_TIM_TIMER_RI_DISABLE@GOTPAGEOFF]
	b	LBB0_22
LBB0_20:                                ;   in Loop: Header=BB0_22 Depth=1
	str	x22, [sp]
Lloh29:
	adrp	x1, l_.str.2@PAGE
Lloh30:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_vxge_debug_ll_config
Lloh31:
	adrp	x8, _VXGE_HW_FIFO_ENABLE@GOTPAGE
Lloh32:
	ldr	x8, [x8, _VXGE_HW_FIFO_ENABLE@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x8]
	ldr	x8, [x20]
	add	x8, x8, x28
	str	w9, [x8, #208]
Lloh34:
	adrp	x9, _MAX_SKB_FRAGS@GOTPAGE
Lloh35:
	ldr	x9, [x9, _MAX_SKB_FRAGS@GOTPAGEOFF]
Lloh36:
	ldr	w9, [x9]
	add	w9, w9, #1
	str	w9, [x8, #192]
Lloh37:
	adrp	x11, _VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE@GOTPAGE
Lloh38:
	ldr	x11, [x11, _VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE@GOTPAGEOFF]
	ldr	w10, [x11]
	str	w10, [x8, #196]
	lsl	w9, w9, #2
	ldr	w10, [x11]
	sdiv	w9, w10, w9
Lloh39:
	adrp	x10, _VXGE_DEF_FIFO_LENGTH@GOTPAGE
Lloh40:
	ldr	x10, [x10, _VXGE_DEF_FIFO_LENGTH@GOTPAGEOFF]
Lloh41:
	ldr	w10, [x10]
	sub	w10, w10, #1
	sdiv	w9, w10, w9
	add	w9, w9, #1
	str	w9, [x8, #200]
Lloh42:
	adrp	x9, _VXGE_HW_FIFO_QUEUE_INTR_DISABLE@GOTPAGE
Lloh43:
	ldr	x9, [x9, _VXGE_HW_FIFO_QUEUE_INTR_DISABLE@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	str	w9, [x8, #204]
Lloh45:
	adrp	x11, _VXGE_HW_TIM_INTR_ENABLE@GOTPAGE
Lloh46:
	ldr	x11, [x11, _VXGE_HW_TIM_INTR_ENABLE@GOTPAGEOFF]
	ldr	x9, [x11]
	str	x9, [x8, #184]
Lloh47:
	adrp	x9, _VXGE_TTI_BTIMER_VAL@GOTPAGE
Lloh48:
	ldr	x9, [x9, _VXGE_TTI_BTIMER_VAL@GOTPAGEOFF]
Lloh49:
	ldr	w9, [x9]
	mul	w9, w9, w24
	smull	x9, w9, w26
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #7
	str	w9, [x8, #112]
Lloh50:
	adrp	x12, _VXGE_HW_TIM_TIMER_AC_ENABLE@GOTPAGE
Lloh51:
	ldr	x12, [x12, _VXGE_HW_TIM_TIMER_AC_ENABLE@GOTPAGEOFF]
	ldr	x9, [x12]
	str	x9, [x8, #176]
Lloh52:
	adrp	x13, _VXGE_HW_TIM_TIMER_CI_DISABLE@GOTPAGE
Lloh53:
	ldr	x13, [x13, _VXGE_HW_TIM_TIMER_CI_DISABLE@GOTPAGEOFF]
	ldr	x9, [x13]
	str	x9, [x8, #168]
	ldr	x9, [x25]
	str	x9, [x8, #160]
Lloh54:
	adrp	x9, _VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL@GOTPAGE
Lloh55:
	ldr	x9, [x9, _VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	str	w9, [x8, #152]
Lloh57:
	adrp	x9, _VXGE_TTI_LTIMER_VAL@GOTPAGE
Lloh58:
	ldr	x9, [x9, _VXGE_TTI_LTIMER_VAL@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	mul	w9, w9, w24
	smull	x9, w9, w26
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #7
	str	w9, [x8, #116]
Lloh60:
	adrp	x9, _VXGE_TTI_RTIMER_VAL@GOTPAGE
Lloh61:
	ldr	x9, [x9, _VXGE_TTI_RTIMER_VAL@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	mul	w9, w9, w24
	smull	x9, w9, w26
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #7
	str	w9, [x8, #120]
Lloh63:
	adrp	x9, _TTI_TX_URANGE_A@GOTPAGE
Lloh64:
	ldr	x9, [x9, _TTI_TX_URANGE_A@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	str	w9, [x8, #148]
Lloh66:
	adrp	x9, _TTI_TX_URANGE_B@GOTPAGE
Lloh67:
	ldr	x9, [x9, _TTI_TX_URANGE_B@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	str	w9, [x8, #144]
Lloh69:
	adrp	x9, _TTI_TX_URANGE_C@GOTPAGE
Lloh70:
	ldr	x9, [x9, _TTI_TX_URANGE_C@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	str	w9, [x8, #140]
Lloh72:
	adrp	x9, _TTI_TX_UFC_A@GOTPAGE
Lloh73:
	ldr	x9, [x9, _TTI_TX_UFC_A@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	str	w9, [x8, #136]
Lloh75:
	adrp	x9, _TTI_TX_UFC_B@GOTPAGE
Lloh76:
	ldr	x9, [x9, _TTI_TX_UFC_B@GOTPAGEOFF]
Lloh77:
	ldr	w9, [x9]
	str	w9, [x8, #132]
Lloh78:
	adrp	x9, _TTI_TX_UFC_C@GOTPAGE
Lloh79:
	ldr	x9, [x9, _TTI_TX_UFC_C@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	str	w9, [x8, #128]
Lloh81:
	adrp	x9, _TTI_TX_UFC_D@GOTPAGE
Lloh82:
	ldr	x9, [x9, _TTI_TX_UFC_D@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	str	w9, [x8, #124]
Lloh84:
	adrp	x9, _VXGE_HW_RING_ENABLE@GOTPAGE
Lloh85:
	ldr	x9, [x9, _VXGE_HW_RING_ENABLE@GOTPAGEOFF]
Lloh86:
	ldr	w9, [x9]
	str	w9, [x8, #104]
Lloh87:
	adrp	x9, _VXGE_HW_DEF_RING_BLOCKS@GOTPAGE
Lloh88:
	ldr	x9, [x9, _VXGE_HW_DEF_RING_BLOCKS@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	str	w9, [x8, #100]
Lloh90:
	adrp	x9, _VXGE_HW_RING_RXD_BUFFER_MODE_1@GOTPAGE
Lloh91:
	ldr	x9, [x9, _VXGE_HW_RING_RXD_BUFFER_MODE_1@GOTPAGEOFF]
Lloh92:
	ldr	w9, [x9]
	str	w9, [x8, #96]
Lloh93:
	adrp	x9, _VXGE_HW_DEF_RING_RXDS_LIMIT@GOTPAGE
Lloh94:
	ldr	x9, [x9, _VXGE_HW_DEF_RING_RXDS_LIMIT@GOTPAGEOFF]
Lloh95:
	ldr	w9, [x9]
	str	w9, [x8, #92]
Lloh96:
	adrp	x9, _VXGE_HW_RING_SCATTER_MODE_A@GOTPAGE
Lloh97:
	ldr	x9, [x9, _VXGE_HW_RING_SCATTER_MODE_A@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	str	w9, [x8, #88]
	ldr	x9, [x11]
	str	x9, [x8, #80]
Lloh99:
	adrp	x9, _VXGE_RTI_BTIMER_VAL@GOTPAGE
Lloh100:
	ldr	x9, [x9, _VXGE_RTI_BTIMER_VAL@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
	mul	w9, w9, w24
	smull	x9, w9, w26
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #7
	str	w9, [x8, #8]
	ldr	x9, [x12]
	str	x9, [x8, #72]
	ldr	x9, [x13]
	str	x9, [x8, #64]
	ldr	x9, [x25]
	str	x9, [x8, #56]
Lloh102:
	adrp	x9, _VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL@GOTPAGE
Lloh103:
	ldr	x9, [x9, _VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL@GOTPAGEOFF]
Lloh104:
	ldr	w9, [x9]
	str	w9, [x8, #48]
Lloh105:
	adrp	x9, _RTI_RX_URANGE_A@GOTPAGE
Lloh106:
	ldr	x9, [x9, _RTI_RX_URANGE_A@GOTPAGEOFF]
Lloh107:
	ldr	w9, [x9]
	str	w9, [x8, #44]
Lloh108:
	adrp	x9, _RTI_RX_URANGE_B@GOTPAGE
Lloh109:
	ldr	x9, [x9, _RTI_RX_URANGE_B@GOTPAGEOFF]
Lloh110:
	ldr	w9, [x9]
	str	w9, [x8, #40]
Lloh111:
	adrp	x9, _RTI_RX_URANGE_C@GOTPAGE
Lloh112:
	ldr	x9, [x9, _RTI_RX_URANGE_C@GOTPAGEOFF]
Lloh113:
	ldr	w9, [x9]
	str	w9, [x8, #36]
Lloh114:
	adrp	x9, _RTI_RX_UFC_A@GOTPAGE
Lloh115:
	ldr	x9, [x9, _RTI_RX_UFC_A@GOTPAGEOFF]
Lloh116:
	ldr	w9, [x9]
	str	w9, [x8, #32]
Lloh117:
	adrp	x9, _RTI_RX_UFC_B@GOTPAGE
Lloh118:
	ldr	x9, [x9, _RTI_RX_UFC_B@GOTPAGEOFF]
Lloh119:
	ldr	w9, [x9]
	str	w9, [x8, #28]
Lloh120:
	adrp	x9, _RTI_RX_UFC_C@GOTPAGE
Lloh121:
	ldr	x9, [x9, _RTI_RX_UFC_C@GOTPAGEOFF]
Lloh122:
	ldr	w9, [x9]
	str	w9, [x8, #24]
Lloh123:
	adrp	x9, _RTI_RX_UFC_D@GOTPAGE
Lloh124:
	ldr	x9, [x9, _RTI_RX_UFC_D@GOTPAGEOFF]
Lloh125:
	ldr	w9, [x9]
	str	w9, [x8, #20]
Lloh126:
	adrp	x9, _VXGE_RTI_RTIMER_VAL@GOTPAGE
Lloh127:
	ldr	x9, [x9, _VXGE_RTI_RTIMER_VAL@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
	mul	w9, w9, w24
	smull	x9, w9, w26
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #7
	str	w9, [x8, #12]
Lloh129:
	adrp	x9, _VXGE_RTI_LTIMER_VAL@GOTPAGE
Lloh130:
	ldr	x9, [x9, _VXGE_RTI_LTIMER_VAL@GOTPAGEOFF]
Lloh131:
	ldr	w9, [x9]
	mul	w9, w9, w24
	smull	x9, w9, w26
	lsr	x10, x9, #32
	lsr	x9, x9, #63
	add	w9, w9, w10, asr #7
	str	w9, [x8, #16]
Lloh132:
	adrp	x9, _vlan_tag_strip@GOTPAGE
Lloh133:
	ldr	x9, [x9, _vlan_tag_strip@GOTPAGEOFF]
Lloh134:
	ldr	w9, [x9]
	str	w9, [x8, #4]
	add	w21, w21, #1
LBB0_21:                                ;   in Loop: Header=BB0_22 Depth=1
	add	x22, x22, #1
	ldrsw	x8, [x27]
	add	x28, x28, #224
	cmp	x22, x8
	mov	x12, x23
	b.ge	LBB0_27
LBB0_22:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20]
	add	x8, x8, x28
	str	w22, [x8]
Lloh135:
	adrp	x9, _VXGE_HW_DEFAULT_MTU@GOTPAGE
Lloh136:
	ldr	x9, [x9, _VXGE_HW_DEFAULT_MTU@GOTPAGEOFF]
Lloh137:
	ldr	w9, [x9]
	str	w9, [x8, #212]
	mov	x23, x12
	ldr	x8, [x12]
	ldr	w8, [x8]
	cmp	w21, w8
	b.ge	LBB0_26
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=1
	mov	x0, x19
	mov	x1, x22
	mov	w2, #1
	bl	_vxge_bVALn
	mov	x8, x0
Lloh138:
	adrp	x9, _VXGE_TRACE@GOTPAGE
Lloh139:
	ldr	x9, [x9, _VXGE_TRACE@GOTPAGEOFF]
Lloh140:
	ldr	w0, [x9]
Lloh141:
	adrp	x9, _VXGE_DRIVER_NAME@GOTPAGE
Lloh142:
	ldr	x9, [x9, _VXGE_DRIVER_NAME@GOTPAGEOFF]
Lloh143:
	ldr	w2, [x9]
	cbnz	w8, LBB0_20
; %bb.24:                               ;   in Loop: Header=BB0_22 Depth=1
	str	x22, [sp]
Lloh144:
	adrp	x1, l_.str.1@PAGE
Lloh145:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_vxge_debug_ll_config
	b	LBB0_21
LBB0_25:
	mov	w21, #0
	b	LBB0_27
LBB0_26:
Lloh146:
	adrp	x8, _VXGE_TRACE@GOTPAGE
Lloh147:
	ldr	x8, [x8, _VXGE_TRACE@GOTPAGEOFF]
Lloh148:
	ldr	w0, [x8]
Lloh149:
	adrp	x8, _VXGE_DRIVER_NAME@GOTPAGE
Lloh150:
	ldr	x8, [x8, _VXGE_DRIVER_NAME@GOTPAGEOFF]
Lloh151:
	ldr	w2, [x8]
	str	x22, [sp]
Lloh152:
	adrp	x1, l_.str.3@PAGE
Lloh153:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_vxge_debug_ll_config
	mov	x12, x23
LBB0_27:
	ldr	x8, [x12]
	ldr	w9, [sp, #12]                   ; 4-byte Folded Reload
	str	w9, [x8]
LBB0_28:
	mov	x0, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpAdd	Lloh144, Lloh145
	.loh AdrpAdd	Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.cfi_endproc
                                        ; -- End function
	.comm	_driver_config,8,3              ; @driver_config
	.comm	_VXGE_USE_DEFAULT,4,2           ; @VXGE_USE_DEFAULT
	.comm	_max_config_dev,8,3             ; @max_config_dev
	.comm	_VXGE_MAX_CONFIG_DEV,8,3        ; @VXGE_MAX_CONFIG_DEV
	.comm	_VXGE_HW_MAX_VIRTUAL_PATHS,4,2  ; @VXGE_HW_MAX_VIRTUAL_PATHS
	.comm	_VXGE_TRACE,4,2                 ; @VXGE_TRACE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s: Disable tx and rx steering, as single vpath is configured"

	.comm	_VXGE_DRIVER_NAME,4,2           ; @VXGE_DRIVER_NAME
	.comm	_NO_STEERING,8,3                ; @NO_STEERING
	.comm	_bw_percentage,8,3              ; @bw_percentage
	.comm	_VXGE_HW_DEFAULT_MTU,4,2        ; @VXGE_HW_DEFAULT_MTU
l_.str.1:                               ; @.str.1
	.asciz	"%s: vpath: %d is not available"

l_.str.2:                               ; @.str.2
	.asciz	"%s: vpath: %d available"

l_.str.3:                               ; @.str.3
	.asciz	"%s: vpath: %d is not configured, max_config_vpath exceeded"

	.comm	_VXGE_HW_FIFO_ENABLE,4,2        ; @VXGE_HW_FIFO_ENABLE
	.comm	_MAX_SKB_FRAGS,4,2              ; @MAX_SKB_FRAGS
	.comm	_VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE,4,2 ; @VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE
	.comm	_VXGE_DEF_FIFO_LENGTH,4,2       ; @VXGE_DEF_FIFO_LENGTH
	.comm	_VXGE_HW_FIFO_QUEUE_INTR_DISABLE,4,2 ; @VXGE_HW_FIFO_QUEUE_INTR_DISABLE
	.comm	_VXGE_HW_TIM_INTR_ENABLE,8,3    ; @VXGE_HW_TIM_INTR_ENABLE
	.comm	_VXGE_TTI_BTIMER_VAL,4,2        ; @VXGE_TTI_BTIMER_VAL
	.comm	_VXGE_HW_TIM_TIMER_AC_ENABLE,8,3 ; @VXGE_HW_TIM_TIMER_AC_ENABLE
	.comm	_VXGE_HW_TIM_TIMER_CI_DISABLE,8,3 ; @VXGE_HW_TIM_TIMER_CI_DISABLE
	.comm	_VXGE_HW_TIM_TIMER_RI_DISABLE,8,3 ; @VXGE_HW_TIM_TIMER_RI_DISABLE
	.comm	_VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL,4,2 ; @VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL
	.comm	_VXGE_TTI_LTIMER_VAL,4,2        ; @VXGE_TTI_LTIMER_VAL
	.comm	_VXGE_TTI_RTIMER_VAL,4,2        ; @VXGE_TTI_RTIMER_VAL
	.comm	_TTI_TX_URANGE_A,4,2            ; @TTI_TX_URANGE_A
	.comm	_TTI_TX_URANGE_B,4,2            ; @TTI_TX_URANGE_B
	.comm	_TTI_TX_URANGE_C,4,2            ; @TTI_TX_URANGE_C
	.comm	_TTI_TX_UFC_A,4,2               ; @TTI_TX_UFC_A
	.comm	_TTI_TX_UFC_B,4,2               ; @TTI_TX_UFC_B
	.comm	_TTI_TX_UFC_C,4,2               ; @TTI_TX_UFC_C
	.comm	_TTI_TX_UFC_D,4,2               ; @TTI_TX_UFC_D
	.comm	_VXGE_HW_RING_ENABLE,4,2        ; @VXGE_HW_RING_ENABLE
	.comm	_VXGE_HW_DEF_RING_BLOCKS,4,2    ; @VXGE_HW_DEF_RING_BLOCKS
	.comm	_VXGE_HW_RING_RXD_BUFFER_MODE_1,4,2 ; @VXGE_HW_RING_RXD_BUFFER_MODE_1
	.comm	_VXGE_HW_DEF_RING_RXDS_LIMIT,4,2 ; @VXGE_HW_DEF_RING_RXDS_LIMIT
	.comm	_VXGE_HW_RING_SCATTER_MODE_A,4,2 ; @VXGE_HW_RING_SCATTER_MODE_A
	.comm	_VXGE_RTI_BTIMER_VAL,4,2        ; @VXGE_RTI_BTIMER_VAL
	.comm	_VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL,4,2 ; @VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL
	.comm	_RTI_RX_URANGE_A,4,2            ; @RTI_RX_URANGE_A
	.comm	_RTI_RX_URANGE_B,4,2            ; @RTI_RX_URANGE_B
	.comm	_RTI_RX_URANGE_C,4,2            ; @RTI_RX_URANGE_C
	.comm	_RTI_RX_UFC_A,4,2               ; @RTI_RX_UFC_A
	.comm	_RTI_RX_UFC_B,4,2               ; @RTI_RX_UFC_B
	.comm	_RTI_RX_UFC_C,4,2               ; @RTI_RX_UFC_C
	.comm	_RTI_RX_UFC_D,4,2               ; @RTI_RX_UFC_D
	.comm	_VXGE_RTI_RTIMER_VAL,4,2        ; @VXGE_RTI_RTIMER_VAL
	.comm	_VXGE_RTI_LTIMER_VAL,4,2        ; @VXGE_RTI_LTIMER_VAL
	.comm	_vlan_tag_strip,4,2             ; @vlan_tag_strip
	.no_dead_strip	_vxge_config_vpaths
.subsections_via_symbols
