	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pcie_config_aspm_l1ss
_pcie_config_aspm_l1ss:                 ## @pcie_config_aspm_l1ss
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	32(%rdi), %r12
	movq	24(%rdi), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movl	(%rdi), %ebx
	movl	4(%rdi), %r15d
	movl	8(%rdi), %eax
	notl	%ebx
	movl	%esi, -52(%rbp)                 ## 4-byte Spill
	andl	%esi, %ebx
	movq	_PCI_L1SS_CTL1@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	addl	%eax, %esi
	movq	_PCI_L1SS_CTL1_L1SS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%ecx, %ecx
	callq	_pci_clear_and_set_dword
	movl	(%r13), %esi
	movl	%r15d, -48(%rbp)                ## 4-byte Spill
	addl	%r15d, %esi
	movq	_PCI_L1SS_CTL1_L1SS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	xorl	%ecx, %ecx
	callq	_pci_clear_and_set_dword
	movq	_ASPM_STATE_L1_1@GOTPCREL(%rip), %rcx
	movq	_ASPM_STATE_L1_2@GOTPCREL(%rip), %r15
	movl	(%r15), %eax
	orl	(%rcx), %eax
	testl	%ebx, %eax
	je	LBB0_2
## %bb.1:
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCI_EXP_LNKCTL_ASPM_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%ecx, %ecx
	callq	_pcie_capability_clear_and_set_word
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCI_EXP_LNKCTL_ASPM_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%ecx, %ecx
	callq	_pcie_capability_clear_and_set_word
LBB0_2:
	movq	_ASPM_STATE_L1_2_MASK@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_4
## %bb.3:
	movq	_PCI_L1SS_CTL2@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movl	-48(%rbp), %ebx                 ## 4-byte Reload
	addl	%ebx, %esi
	movl	16(%r14), %edx
	movq	%r13, %rdi
	callq	_pci_write_config_dword
	movl	(%r15), %esi
	movq	_ASPM_STATE_L1_2@GOTPCREL(%rip), %r15
	addl	-44(%rbp), %esi                 ## 4-byte Folded Reload
	movl	16(%r14), %edx
	movq	%r12, %rdi
	callq	_pci_write_config_dword
	movq	_PCI_L1SS_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%ebx, %esi
	movq	_PCI_L1SS_CTL1_CM_RESTORE_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	12(%r14), %ecx
	movq	%r13, %rdi
	callq	_pci_clear_and_set_dword
	movq	_PCI_L1SS_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%ebx, %esi
	movq	_PCI_L1SS_CTL1_LTR_L12_TH_VALUE@GOTPCREL(%rip), %rbx
	movq	_PCI_L1SS_CTL1_LTR_L12_TH_SCALE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	(%rbx), %edx
	movl	12(%r14), %ecx
	movq	%r13, %rdi
	callq	_pci_clear_and_set_dword
	movq	_PCI_L1SS_CTL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	-44(%rbp), %esi                 ## 4-byte Folded Reload
	movq	_PCI_L1SS_CTL1_LTR_L12_TH_SCALE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	(%rbx), %edx
	movl	12(%r14), %ecx
	movq	%r12, %rdi
	callq	_pci_clear_and_set_dword
LBB0_4:
	movq	_ASPM_STATE_L1_1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	-52(%rbp), %edx                 ## 4-byte Reload
	andl	%edx, %eax
	je	LBB0_6
## %bb.5:
	movq	_PCI_L1SS_CTL1_ASPM_L1_1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
LBB0_6:
	movl	(%r15), %ebx
	andl	%edx, %ebx
	je	LBB0_8
## %bb.7:
	movq	_PCI_L1SS_CTL1_ASPM_L1_2@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
LBB0_8:
	movq	_ASPM_STATE_L1_1_PCIPM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edx, %ecx
	je	LBB0_10
## %bb.9:
	movq	_PCI_L1SS_CTL1_PCIPM_L1_1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
LBB0_10:
	orl	%eax, %ebx
	movq	_ASPM_STATE_L1_2_PCIPM@GOTPCREL(%rip), %rax
	andl	(%rax), %edx
	je	LBB0_12
## %bb.11:
	movq	_PCI_L1SS_CTL1_PCIPM_L1_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_12:
	orl	%edx, %ecx
	orl	%ecx, %ebx
	movq	_PCI_L1SS_CTL1@GOTPCREL(%rip), %r15
	movl	-48(%rbp), %esi                 ## 4-byte Reload
	addl	(%r15), %esi
	movq	_PCI_L1SS_CAP_L1_PM_SS@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	movq	%r13, %rdi
	movl	%ebx, %ecx
	callq	_pci_clear_and_set_dword
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	addl	(%r15), %esi
	movl	(%r14), %edx
	movq	%r12, %rdi
	movl	%ebx, %ecx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_pci_clear_and_set_dword        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_L1SS_CTL1,4,2              ## @PCI_L1SS_CTL1
	.comm	_PCI_L1SS_CTL1_L1SS_MASK,4,2    ## @PCI_L1SS_CTL1_L1SS_MASK
	.comm	_ASPM_STATE_L1_1,4,2            ## @ASPM_STATE_L1_1
	.comm	_ASPM_STATE_L1_2,4,2            ## @ASPM_STATE_L1_2
	.comm	_PCI_EXP_LNKCTL,4,2             ## @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_ASPM_L1,4,2     ## @PCI_EXP_LNKCTL_ASPM_L1
	.comm	_ASPM_STATE_L1_2_MASK,4,2       ## @ASPM_STATE_L1_2_MASK
	.comm	_PCI_L1SS_CTL2,4,2              ## @PCI_L1SS_CTL2
	.comm	_PCI_L1SS_CTL1_CM_RESTORE_TIME,4,2 ## @PCI_L1SS_CTL1_CM_RESTORE_TIME
	.comm	_PCI_L1SS_CTL1_LTR_L12_TH_VALUE,4,2 ## @PCI_L1SS_CTL1_LTR_L12_TH_VALUE
	.comm	_PCI_L1SS_CTL1_LTR_L12_TH_SCALE,4,2 ## @PCI_L1SS_CTL1_LTR_L12_TH_SCALE
	.comm	_PCI_L1SS_CTL1_ASPM_L1_1,4,2    ## @PCI_L1SS_CTL1_ASPM_L1_1
	.comm	_PCI_L1SS_CTL1_ASPM_L1_2,4,2    ## @PCI_L1SS_CTL1_ASPM_L1_2
	.comm	_ASPM_STATE_L1_1_PCIPM,4,2      ## @ASPM_STATE_L1_1_PCIPM
	.comm	_PCI_L1SS_CTL1_PCIPM_L1_1,4,2   ## @PCI_L1SS_CTL1_PCIPM_L1_1
	.comm	_ASPM_STATE_L1_2_PCIPM,4,2      ## @ASPM_STATE_L1_2_PCIPM
	.comm	_PCI_L1SS_CTL1_PCIPM_L1_2,4,2   ## @PCI_L1SS_CTL1_PCIPM_L1_2
	.comm	_PCI_L1SS_CAP_L1_PM_SS,4,2      ## @PCI_L1SS_CAP_L1_PM_SS
	.no_dead_strip	_pcie_config_aspm_l1ss
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pcie_config_aspm_l1ss
_pcie_config_aspm_l1ss:                 ; @pcie_config_aspm_l1ss
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x21, x1
	mov	x22, x0
	ldp	x20, x19, [x0, #24]
	ldp	w25, w23, [x0, #4]
	ldr	w8, [x0]
Lloh0:
	adrp	x24, _PCI_L1SS_CTL1@GOTPAGE
Lloh1:
	ldr	x24, [x24, _PCI_L1SS_CTL1@GOTPAGEOFF]
	bic	w28, w1, w8
	ldr	w8, [x24]
	add	w1, w8, w23
Lloh2:
	adrp	x26, _PCI_L1SS_CTL1_L1SS_MASK@GOTPAGE
Lloh3:
	ldr	x26, [x26, _PCI_L1SS_CTL1_L1SS_MASK@GOTPAGEOFF]
	ldr	w2, [x26]
	mov	x0, x19
	mov	w3, #0
	bl	_pci_clear_and_set_dword
	ldr	w8, [x24]
	add	w1, w8, w25
	ldr	w2, [x26]
	mov	x0, x20
	mov	w3, #0
	bl	_pci_clear_and_set_dword
Lloh4:
	adrp	x8, _ASPM_STATE_L1_1@GOTPAGE
Lloh5:
	ldr	x8, [x8, _ASPM_STATE_L1_1@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
Lloh7:
	adrp	x9, _ASPM_STATE_L1_2@GOTPAGE
Lloh8:
	ldr	x9, [x9, _ASPM_STATE_L1_2@GOTPAGEOFF]
Lloh9:
	ldr	w9, [x9]
	orr	w8, w9, w8
	tst	w8, w28
	b.eq	LBB0_2
; %bb.1:
Lloh10:
	adrp	x26, _PCI_EXP_LNKCTL@GOTPAGE
Lloh11:
	ldr	x26, [x26, _PCI_EXP_LNKCTL@GOTPAGEOFF]
	ldr	w1, [x26]
Lloh12:
	adrp	x27, _PCI_EXP_LNKCTL_ASPM_L1@GOTPAGE
Lloh13:
	ldr	x27, [x27, _PCI_EXP_LNKCTL_ASPM_L1@GOTPAGEOFF]
	ldr	w2, [x27]
	mov	x0, x19
	mov	w3, #0
	bl	_pcie_capability_clear_and_set_word
	ldr	w1, [x26]
	ldr	w2, [x27]
	mov	x0, x20
	mov	w3, #0
	bl	_pcie_capability_clear_and_set_word
LBB0_2:
Lloh14:
	adrp	x8, _ASPM_STATE_L1_2_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _ASPM_STATE_L1_2_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
	tst	w8, w28
	b.eq	LBB0_4
; %bb.3:
Lloh17:
	adrp	x26, _PCI_L1SS_CTL2@GOTPAGE
Lloh18:
	ldr	x26, [x26, _PCI_L1SS_CTL2@GOTPAGEOFF]
	ldr	w8, [x26]
	add	w1, w8, w25
	ldr	w2, [x22, #16]
	mov	x0, x20
	bl	_pci_write_config_dword
	ldr	w8, [x26]
	add	w1, w8, w23
	ldr	w2, [x22, #16]
	mov	x0, x19
	bl	_pci_write_config_dword
	ldr	w8, [x24]
	add	w1, w8, w25
Lloh19:
	adrp	x8, _PCI_L1SS_CTL1_CM_RESTORE_TIME@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PCI_L1SS_CTL1_CM_RESTORE_TIME@GOTPAGEOFF]
Lloh21:
	ldr	w2, [x8]
	ldr	w3, [x22, #12]
	mov	x0, x20
	bl	_pci_clear_and_set_dword
	ldr	w8, [x24]
	add	w1, w8, w25
Lloh22:
	adrp	x26, _PCI_L1SS_CTL1_LTR_L12_TH_VALUE@GOTPAGE
Lloh23:
	ldr	x26, [x26, _PCI_L1SS_CTL1_LTR_L12_TH_VALUE@GOTPAGEOFF]
	ldr	w8, [x26]
Lloh24:
	adrp	x27, _PCI_L1SS_CTL1_LTR_L12_TH_SCALE@GOTPAGE
Lloh25:
	ldr	x27, [x27, _PCI_L1SS_CTL1_LTR_L12_TH_SCALE@GOTPAGEOFF]
	ldr	w9, [x27]
	orr	w2, w9, w8
	ldr	w3, [x22, #12]
	mov	x0, x20
	bl	_pci_clear_and_set_dword
	ldr	w8, [x24]
	add	w1, w8, w23
	ldr	w8, [x26]
	ldr	w9, [x27]
	orr	w2, w9, w8
	ldr	w3, [x22, #12]
	mov	x0, x19
	bl	_pci_clear_and_set_dword
LBB0_4:
Lloh26:
	adrp	x8, _ASPM_STATE_L1_1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _ASPM_STATE_L1_1@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
Lloh29:
	adrp	x9, _PCI_L1SS_CTL1_ASPM_L1_1@GOTPAGE
Lloh30:
	ldr	x9, [x9, _PCI_L1SS_CTL1_ASPM_L1_1@GOTPAGEOFF]
Lloh31:
	ldr	w9, [x9]
	tst	w8, w21
	csel	w8, wzr, w9, eq
Lloh32:
	adrp	x9, _ASPM_STATE_L1_2@GOTPAGE
Lloh33:
	ldr	x9, [x9, _ASPM_STATE_L1_2@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
Lloh35:
	adrp	x10, _PCI_L1SS_CTL1_ASPM_L1_2@GOTPAGE
Lloh36:
	ldr	x10, [x10, _PCI_L1SS_CTL1_ASPM_L1_2@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	tst	w9, w21
	csel	w9, wzr, w10, eq
	orr	w8, w9, w8
Lloh38:
	adrp	x9, _ASPM_STATE_L1_1_PCIPM@GOTPAGE
Lloh39:
	ldr	x9, [x9, _ASPM_STATE_L1_1_PCIPM@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
Lloh41:
	adrp	x10, _PCI_L1SS_CTL1_PCIPM_L1_1@GOTPAGE
Lloh42:
	ldr	x10, [x10, _PCI_L1SS_CTL1_PCIPM_L1_1@GOTPAGEOFF]
Lloh43:
	ldr	w10, [x10]
	tst	w9, w21
	csel	w9, wzr, w10, eq
	orr	w8, w8, w9
Lloh44:
	adrp	x9, _ASPM_STATE_L1_2_PCIPM@GOTPAGE
Lloh45:
	ldr	x9, [x9, _ASPM_STATE_L1_2_PCIPM@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
Lloh47:
	adrp	x10, _PCI_L1SS_CTL1_PCIPM_L1_2@GOTPAGE
Lloh48:
	ldr	x10, [x10, _PCI_L1SS_CTL1_PCIPM_L1_2@GOTPAGEOFF]
Lloh49:
	ldr	w10, [x10]
	tst	w9, w21
	csel	w9, wzr, w10, eq
	orr	w21, w8, w9
	ldr	w8, [x24]
	add	w1, w8, w25
Lloh50:
	adrp	x22, _PCI_L1SS_CAP_L1_PM_SS@GOTPAGE
Lloh51:
	ldr	x22, [x22, _PCI_L1SS_CAP_L1_PM_SS@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x20
	mov	x3, x21
	bl	_pci_clear_and_set_dword
	ldr	w8, [x24]
	add	w1, w8, w23
	ldr	w2, [x22]
	mov	x0, x19
	mov	x3, x21
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_pci_clear_and_set_dword
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_L1SS_CTL1,4,2              ; @PCI_L1SS_CTL1
	.comm	_PCI_L1SS_CTL1_L1SS_MASK,4,2    ; @PCI_L1SS_CTL1_L1SS_MASK
	.comm	_ASPM_STATE_L1_1,4,2            ; @ASPM_STATE_L1_1
	.comm	_ASPM_STATE_L1_2,4,2            ; @ASPM_STATE_L1_2
	.comm	_PCI_EXP_LNKCTL,4,2             ; @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_ASPM_L1,4,2     ; @PCI_EXP_LNKCTL_ASPM_L1
	.comm	_ASPM_STATE_L1_2_MASK,4,2       ; @ASPM_STATE_L1_2_MASK
	.comm	_PCI_L1SS_CTL2,4,2              ; @PCI_L1SS_CTL2
	.comm	_PCI_L1SS_CTL1_CM_RESTORE_TIME,4,2 ; @PCI_L1SS_CTL1_CM_RESTORE_TIME
	.comm	_PCI_L1SS_CTL1_LTR_L12_TH_VALUE,4,2 ; @PCI_L1SS_CTL1_LTR_L12_TH_VALUE
	.comm	_PCI_L1SS_CTL1_LTR_L12_TH_SCALE,4,2 ; @PCI_L1SS_CTL1_LTR_L12_TH_SCALE
	.comm	_PCI_L1SS_CTL1_ASPM_L1_1,4,2    ; @PCI_L1SS_CTL1_ASPM_L1_1
	.comm	_PCI_L1SS_CTL1_ASPM_L1_2,4,2    ; @PCI_L1SS_CTL1_ASPM_L1_2
	.comm	_ASPM_STATE_L1_1_PCIPM,4,2      ; @ASPM_STATE_L1_1_PCIPM
	.comm	_PCI_L1SS_CTL1_PCIPM_L1_1,4,2   ; @PCI_L1SS_CTL1_PCIPM_L1_1
	.comm	_ASPM_STATE_L1_2_PCIPM,4,2      ; @ASPM_STATE_L1_2_PCIPM
	.comm	_PCI_L1SS_CTL1_PCIPM_L1_2,4,2   ; @PCI_L1SS_CTL1_PCIPM_L1_2
	.comm	_PCI_L1SS_CAP_L1_PM_SS,4,2      ; @PCI_L1SS_CAP_L1_PM_SS
	.no_dead_strip	_pcie_config_aspm_l1ss
.subsections_via_symbols
