	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rt2800_vco_calibration         ## -- Begin function rt2800_vco_calibration
	.p2align	4, 0x90
_rt2800_vco_calibration:                ## @rt2800_vco_calibration
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_TX_PIN_CFG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_rt2800_register_read
	movq	_TX_PIN_CFG_PA_PE_DISABLE@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movl	(%r15), %esi
	movq	%r14, %rdi
	movl	%eax, %edx
	callq	_rt2800_register_write
	movl	12(%r14), %edx
	leal	-128(%rdx), %eax
	cmpl	$18, %eax
	ja	LBB0_4
## %bb.1:
	movl	$15358, %ecx                    ## imm = 0x3BFE
	btl	%eax, %ecx
	jae	LBB0_2
## %bb.6:
	movq	%r14, %rdi
	movl	$3, %esi
	callq	_rt2800_rfcsr_read
	movl	%eax, -44(%rbp)
	movq	_RFCSR3_VCOCAL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field8
	movl	-44(%rbp), %edx
	movq	%r14, %rdi
	movl	$3, %esi
	callq	_rt2800_rfcsr_write
	movl	$1000, %edi                     ## imm = 0x3E8
LBB0_7:
	leal	(%rdi,%rdi), %esi
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_usleep_range
	jmp	LBB0_8
LBB0_2:
	movl	$508928, %ecx                   ## imm = 0x7C400
	movq	%r14, %rdi
	btl	%eax, %ecx
	jae	LBB0_3
## %bb.5:
	movl	$7, %esi
	callq	_rt2800_rfcsr_read
	movl	%eax, -44(%rbp)
	movq	_RFCSR7_RF_TUNING@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field8
	movl	-44(%rbp), %edx
	movq	%r14, %rdi
	movl	$7, %esi
	callq	_rt2800_rfcsr_write
LBB0_8:
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_rt2800_register_read
	movl	%eax, -48(%rbp)
	movl	(%r14), %ebx
	movl	4(%r14), %eax
	cmpl	$2, %eax
	je	LBB0_14
## %bb.9:
	cmpl	$3, %eax
	jne	LBB0_18
## %bb.10:
	cmpl	$15, %ebx
	jge	LBB0_11
## %bb.12:
	movq	_TX_PIN_CFG_PA_PE_G2_EN@GOTPCREL(%rip), %rax
	jmp	LBB0_13
LBB0_11:
	movq	_TX_PIN_CFG_PA_PE_A2_EN@GOTPCREL(%rip), %rax
LBB0_13:
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
LBB0_14:
	cmpl	$15, %ebx
	jge	LBB0_15
## %bb.16:
	movq	_TX_PIN_CFG_PA_PE_G1_EN@GOTPCREL(%rip), %rax
	jmp	LBB0_17
LBB0_15:
	movq	_TX_PIN_CFG_PA_PE_A1_EN@GOTPCREL(%rip), %rax
LBB0_17:
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
LBB0_18:
	cmpl	$15, %ebx
	jge	LBB0_19
## %bb.20:
	movq	_TX_PIN_CFG_PA_PE_G0_EN@GOTPCREL(%rip), %rax
	jmp	LBB0_21
LBB0_19:
	movq	_TX_PIN_CFG_PA_PE_A0_EN@GOTPCREL(%rip), %rax
LBB0_21:
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-48(%rbp), %edx
	movq	%r14, %rdi
	callq	_rt2800_register_write
	movq	_RT6352@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_rt2x00_rt
	testq	%rax, %rax
	je	LBB0_25
## %bb.22:
	xorl	%r12d, %r12d
	xorl	%edx, %edx
	cmpl	$1, 8(%r14)
	setne	%r12b
	movl	$18, %eax
	movl	$48, %r15d
	cmovel	%eax, %r15d
	sete	%dl
	orl	$6, %edx
	movl	%r12d, %ebx
	shll	$7, %ebx
	orl	$26, %ebx
	movl	%r12d, %r13d
	shll	$6, %r13d
	orl	$160, %r13d
	shll	$5, %r12d
	orl	$16, %r12d
	movq	%r14, %rdi
	movl	$91, %esi
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$95, %esi
	movl	%ebx, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$195, %esi
	movl	$128, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$196, %esi
	movl	%r13d, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$195, %esi
	movl	$170, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$196, %esi
	movl	%r15d, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$195, %esi
	movl	$171, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$196, %esi
	movl	%r12d, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	callq	_rt2x00_has_cap_external_lna_bg
	testq	%rax, %rax
	je	LBB0_24
## %bb.23:
	movq	%r14, %rdi
	movl	$75, %esi
	movl	$104, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$76, %esi
	movl	$76, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$79, %esi
	movl	$28, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$80, %esi
	movl	$12, %edx
	callq	_rt2800_bbp_write
	movq	%r14, %rdi
	movl	$82, %esi
	movl	$182, %edx
	callq	_rt2800_bbp_write
LBB0_24:
	movl	$1000, %edi                     ## imm = 0x3E8
	movl	$1500, %esi                     ## imm = 0x5DC
	callq	_usleep_range
LBB0_25:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	leaq	L_.str(%rip), %rsi
	movl	$1, %edi
                                        ## kill: def $edx killed $edx killed $rdx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_WARN_ONCE                      ## TAILCALL
LBB0_3:
	movl	$5, %esi
	movl	$64, %edx
	callq	_rt2800_rfcsr_write
	movq	%r14, %rdi
	movl	$4, %esi
	movl	$12, %edx
	callq	_rt2800_rfcsr_write
	movq	%r14, %rdi
	movl	$4, %esi
	callq	_rt2800_rfcsr_read
	movl	%eax, -44(%rbp)
	movq	_RFCSR4_VCOCAL_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field8
	movl	-44(%rbp), %edx
	movq	%r14, %rdi
	movl	$4, %esi
	callq	_rt2800_rfcsr_write
	movl	$2000, %edi                     ## imm = 0x7D0
	jmp	LBB0_7
	.cfi_endproc
                                        ## -- End function
	.comm	_TX_PIN_CFG,4,2                 ## @TX_PIN_CFG
	.comm	_TX_PIN_CFG_PA_PE_DISABLE,4,2   ## @TX_PIN_CFG_PA_PE_DISABLE
	.comm	_RFCSR7_RF_TUNING,4,2           ## @RFCSR7_RF_TUNING
	.comm	_RFCSR3_VCOCAL_EN,4,2           ## @RFCSR3_VCOCAL_EN
	.comm	_RFCSR4_VCOCAL_EN,4,2           ## @RFCSR4_VCOCAL_EN
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Not supported RF chipset %x for VCO recalibration"

	.comm	_TX_PIN_CFG_PA_PE_G2_EN,4,2     ## @TX_PIN_CFG_PA_PE_G2_EN
	.comm	_TX_PIN_CFG_PA_PE_G1_EN,4,2     ## @TX_PIN_CFG_PA_PE_G1_EN
	.comm	_TX_PIN_CFG_PA_PE_G0_EN,4,2     ## @TX_PIN_CFG_PA_PE_G0_EN
	.comm	_TX_PIN_CFG_PA_PE_A2_EN,4,2     ## @TX_PIN_CFG_PA_PE_A2_EN
	.comm	_TX_PIN_CFG_PA_PE_A1_EN,4,2     ## @TX_PIN_CFG_PA_PE_A1_EN
	.comm	_TX_PIN_CFG_PA_PE_A0_EN,4,2     ## @TX_PIN_CFG_PA_PE_A0_EN
	.comm	_RT6352,4,2                     ## @RT6352
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rt2800_vco_calibration         ; -- Begin function rt2800_vco_calibration
	.p2align	2
_rt2800_vco_calibration:                ; @rt2800_vco_calibration
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _TX_PIN_CFG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _TX_PIN_CFG@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_rt2800_register_read
Lloh2:
	adrp	x8, _TX_PIN_CFG_PA_PE_DISABLE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _TX_PIN_CFG_PA_PE_DISABLE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	and	w2, w8, w0
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2800_register_write
	ldr	w2, [x19, #12]
	sub	w8, w2, #128
	cmp	w8, #18
	b.hi	LBB0_15
; %bb.1:
	mov	w9, #1
	lsl	w8, w9, w8
	mov	w9, #15358
	tst	w8, w9
	b.eq	LBB0_4
; %bb.2:
	mov	x0, x19
	mov	w1, #3
	bl	_rt2800_rfcsr_read
	str	w0, [sp, #8]
Lloh5:
	adrp	x8, _RFCSR3_VCOCAL_EN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _RFCSR3_VCOCAL_EN@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	add	x0, sp, #8
	mov	w2, #1
	bl	_rt2x00_set_field8
	ldr	w2, [sp, #8]
	mov	x0, x19
	mov	w1, #3
	bl	_rt2800_rfcsr_write
	mov	w0, #1000
LBB0_3:
	lsl	w1, w0, #1
	bl	_usleep_range
	b	LBB0_6
LBB0_4:
	mov	w9, #50176
	movk	w9, #7, lsl #16
	mov	x0, x19
	tst	w8, w9
	b.eq	LBB0_16
; %bb.5:
	mov	w1, #7
	bl	_rt2800_rfcsr_read
	str	w0, [sp, #8]
Lloh8:
	adrp	x8, _RFCSR7_RF_TUNING@GOTPAGE
Lloh9:
	ldr	x8, [x8, _RFCSR7_RF_TUNING@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	add	x0, sp, #8
	mov	w2, #1
	bl	_rt2x00_set_field8
	ldr	w2, [sp, #8]
	mov	x0, x19
	mov	w1, #7
	bl	_rt2800_rfcsr_write
LBB0_6:
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2800_register_read
	str	w0, [sp, #12]
	ldp	w21, w8, [x19]
	cmp	w8, #2
	b.eq	LBB0_9
; %bb.7:
	cmp	w8, #3
	b.ne	LBB0_10
; %bb.8:
Lloh11:
	adrp	x8, _TX_PIN_CFG_PA_PE_G2_EN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _TX_PIN_CFG_PA_PE_G2_EN@GOTPAGEOFF]
Lloh13:
	adrp	x9, _TX_PIN_CFG_PA_PE_A2_EN@GOTPAGE
Lloh14:
	ldr	x9, [x9, _TX_PIN_CFG_PA_PE_A2_EN@GOTPAGEOFF]
	cmp	w21, #15
	csel	x8, x8, x9, lt
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
LBB0_9:
Lloh15:
	adrp	x8, _TX_PIN_CFG_PA_PE_G1_EN@GOTPAGE
Lloh16:
	ldr	x8, [x8, _TX_PIN_CFG_PA_PE_G1_EN@GOTPAGEOFF]
Lloh17:
	adrp	x9, _TX_PIN_CFG_PA_PE_A1_EN@GOTPAGE
Lloh18:
	ldr	x9, [x9, _TX_PIN_CFG_PA_PE_A1_EN@GOTPAGEOFF]
	cmp	w21, #15
	csel	x8, x8, x9, lt
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
LBB0_10:
Lloh19:
	adrp	x8, _TX_PIN_CFG_PA_PE_G0_EN@GOTPAGE
Lloh20:
	ldr	x8, [x8, _TX_PIN_CFG_PA_PE_G0_EN@GOTPAGEOFF]
Lloh21:
	adrp	x9, _TX_PIN_CFG_PA_PE_A0_EN@GOTPAGE
Lloh22:
	ldr	x9, [x9, _TX_PIN_CFG_PA_PE_A0_EN@GOTPAGEOFF]
	cmp	w21, #15
	csel	x8, x8, x9, lt
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2800_register_write
Lloh23:
	adrp	x8, _RT6352@GOTPAGE
Lloh24:
	ldr	x8, [x8, _RT6352@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_rt2x00_rt
	cbz	x0, LBB0_14
; %bb.11:
	mov	w8, #6
	mov	w9, #154
	ldr	w10, [x19, #8]
	mov	w11, #26
	cmp	w10, #1
	csel	w20, w11, w9, eq
	cinc	w2, w8, eq
	mov	w8, #224
	mov	w9, #160
	csel	w21, w9, w8, eq
	mov	w8, #48
	mov	w9, #18
	csel	w22, w9, w8, eq
	mov	w9, #16
	csel	w23, w9, w8, eq
	mov	x0, x19
	mov	w1, #91
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #95
	mov	x2, x20
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #195
	mov	w2, #128
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #196
	mov	x2, x21
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #195
	mov	w2, #170
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #196
	mov	x2, x22
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #195
	mov	w2, #171
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #196
	mov	x2, x23
	bl	_rt2800_bbp_write
	mov	x0, x19
	bl	_rt2x00_has_cap_external_lna_bg
	cbz	x0, LBB0_13
; %bb.12:
	mov	x0, x19
	mov	w1, #75
	mov	w2, #104
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #76
	mov	w2, #76
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #79
	mov	w2, #28
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #80
	mov	w2, #12
	bl	_rt2800_bbp_write
	mov	x0, x19
	mov	w1, #82
	mov	w2, #182
	bl	_rt2800_bbp_write
LBB0_13:
	mov	w0, #1000
	mov	w1, #1500
	bl	_usleep_range
LBB0_14:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_15:
Lloh26:
	adrp	x1, l_.str@PAGE
Lloh27:
	add	x1, x1, l_.str@PAGEOFF
	mov	w0, #1
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_WARN_ONCE
LBB0_16:
	mov	w1, #5
	mov	w2, #64
	bl	_rt2800_rfcsr_write
	mov	x0, x19
	mov	w1, #4
	mov	w2, #12
	bl	_rt2800_rfcsr_write
	mov	x0, x19
	mov	w1, #4
	bl	_rt2800_rfcsr_read
	str	w0, [sp, #8]
Lloh28:
	adrp	x8, _RFCSR4_VCOCAL_EN@GOTPAGE
Lloh29:
	ldr	x8, [x8, _RFCSR4_VCOCAL_EN@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	add	x0, sp, #8
	mov	w2, #1
	bl	_rt2x00_set_field8
	ldr	w2, [sp, #8]
	mov	x0, x19
	mov	w1, #4
	bl	_rt2800_rfcsr_write
	mov	w0, #2000
	b	LBB0_3
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_TX_PIN_CFG,4,2                 ; @TX_PIN_CFG
	.comm	_TX_PIN_CFG_PA_PE_DISABLE,4,2   ; @TX_PIN_CFG_PA_PE_DISABLE
	.comm	_RFCSR7_RF_TUNING,4,2           ; @RFCSR7_RF_TUNING
	.comm	_RFCSR3_VCOCAL_EN,4,2           ; @RFCSR3_VCOCAL_EN
	.comm	_RFCSR4_VCOCAL_EN,4,2           ; @RFCSR4_VCOCAL_EN
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Not supported RF chipset %x for VCO recalibration"

	.comm	_TX_PIN_CFG_PA_PE_G2_EN,4,2     ; @TX_PIN_CFG_PA_PE_G2_EN
	.comm	_TX_PIN_CFG_PA_PE_G1_EN,4,2     ; @TX_PIN_CFG_PA_PE_G1_EN
	.comm	_TX_PIN_CFG_PA_PE_G0_EN,4,2     ; @TX_PIN_CFG_PA_PE_G0_EN
	.comm	_TX_PIN_CFG_PA_PE_A2_EN,4,2     ; @TX_PIN_CFG_PA_PE_A2_EN
	.comm	_TX_PIN_CFG_PA_PE_A1_EN,4,2     ; @TX_PIN_CFG_PA_PE_A1_EN
	.comm	_TX_PIN_CFG_PA_PE_A0_EN,4,2     ; @TX_PIN_CFG_PA_PE_A0_EN
	.comm	_RT6352,4,2                     ; @RT6352
.subsections_via_symbols
