	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ocelot_pll5_init
_ocelot_pll5_init:                      ## @ocelot_pll5_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	(%rdi), %rax
	movq	_HSIO@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rcx
	movq	%rdx, %r13
	movl	(%rax,%rcx,4), %r14d
	movq	_HSIO_PLL5G_CFG4@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$30208, %edi                    ## imm = 0x7600
	callq	_HSIO_PLL5G_CFG4_IB_CTRL
	movl	%eax, %ebx
	movl	$8, %edi
	callq	_HSIO_PLL5G_CFG4_IB_BIAS_CTRL
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movq	(%r12), %rax
	movq	(%r13), %rcx
	movl	(%rax,%rcx,4), %r14d
	movq	_HSIO_PLL5G_CFG0@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$17, %edi
	callq	_HSIO_PLL5G_CFG0_CORE_CLK_DIV
	movl	%eax, %r13d
	movl	$2, %edi
	callq	_HSIO_PLL5G_CFG0_CPU_CLK_DIV
	orl	%eax, %r13d
	movq	_HSIO_PLL5G_CFG0_ENA_BIAS@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_HSIO_PLL5G_CFG0_ENA_VCO_BUF@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movq	_HSIO_PLL5G_CFG0_ENA_CP1@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	movl	$2, %edi
	callq	_HSIO_PLL5G_CFG0_SELCPI
	movl	%eax, %ebx
	movl	$14, %edi
	callq	_HSIO_PLL5G_CFG0_LOOP_BW_RES
	orl	%eax, %ebx
	movl	$4, %edi
	callq	_HSIO_PLL5G_CFG0_SELBGV820
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movq	_HSIO_PLL5G_CFG0_DIV4@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_HSIO_PLL5G_CFG0_ENA_CLKTREE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_HSIO_PLL5G_CFG0_ENA_LANE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movq	(%r12), %rax
	movq	_HSIO@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	(%rax,%rcx,4), %r14d
	movq	_HSIO_PLL5G_CFG2@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET@GOTPCREL(%rip), %rax
	movq	_HSIO_PLL5G_CFG2_EN_RESET_OVERRUN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movl	$8, %edi
	callq	_HSIO_PLL5G_CFG2_GAIN_TEST
	orl	%eax, %ebx
	movq	_HSIO_PLL5G_CFG2_ENA_AMPCTRL@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_HSIO_PLL5G_CFG2_PWD_AMPCTRL_N@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$16, %edi
	callq	_HSIO_PLL5G_CFG2_AMPC_SEL
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_write                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_HSIO,8,3                       ## @HSIO
	.comm	_HSIO_PLL5G_CFG4,4,2            ## @HSIO_PLL5G_CFG4
	.comm	_HSIO_PLL5G_CFG0,4,2            ## @HSIO_PLL5G_CFG0
	.comm	_HSIO_PLL5G_CFG0_ENA_BIAS,4,2   ## @HSIO_PLL5G_CFG0_ENA_BIAS
	.comm	_HSIO_PLL5G_CFG0_ENA_VCO_BUF,4,2 ## @HSIO_PLL5G_CFG0_ENA_VCO_BUF
	.comm	_HSIO_PLL5G_CFG0_ENA_CP1,4,2    ## @HSIO_PLL5G_CFG0_ENA_CP1
	.comm	_HSIO_PLL5G_CFG0_DIV4,4,2       ## @HSIO_PLL5G_CFG0_DIV4
	.comm	_HSIO_PLL5G_CFG0_ENA_CLKTREE,4,2 ## @HSIO_PLL5G_CFG0_ENA_CLKTREE
	.comm	_HSIO_PLL5G_CFG0_ENA_LANE,4,2   ## @HSIO_PLL5G_CFG0_ENA_LANE
	.comm	_HSIO_PLL5G_CFG2,4,2            ## @HSIO_PLL5G_CFG2
	.comm	_HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET,4,2 ## @HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET
	.comm	_HSIO_PLL5G_CFG2_EN_RESET_OVERRUN,4,2 ## @HSIO_PLL5G_CFG2_EN_RESET_OVERRUN
	.comm	_HSIO_PLL5G_CFG2_ENA_AMPCTRL,4,2 ## @HSIO_PLL5G_CFG2_ENA_AMPCTRL
	.comm	_HSIO_PLL5G_CFG2_PWD_AMPCTRL_N,4,2 ## @HSIO_PLL5G_CFG2_PWD_AMPCTRL_N
	.no_dead_strip	_ocelot_pll5_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ocelot_pll5_init
_ocelot_pll5_init:                      ; @ocelot_pll5_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x23, _HSIO@GOTPAGE
Lloh1:
	ldr	x23, [x23, _HSIO@GOTPAGEOFF]
	ldr	x9, [x23]
	ldr	w20, [x8, x9, lsl #2]
Lloh2:
	adrp	x8, _HSIO_PLL5G_CFG4@GOTPAGE
Lloh3:
	ldr	x8, [x8, _HSIO_PLL5G_CFG4@GOTPAGEOFF]
Lloh4:
	ldr	w21, [x8]
	mov	w0, #30208
	bl	_HSIO_PLL5G_CFG4_IB_CTRL
	mov	x22, x0
	mov	w0, #8
	bl	_HSIO_PLL5G_CFG4_IB_BIAS_CTRL
	orr	w2, w0, w22
	mov	x0, x20
	mov	x1, x21
	bl	_regmap_write
	ldr	x8, [x19]
	ldr	x9, [x23]
	ldr	w20, [x8, x9, lsl #2]
Lloh5:
	adrp	x8, _HSIO_PLL5G_CFG0@GOTPAGE
Lloh6:
	ldr	x8, [x8, _HSIO_PLL5G_CFG0@GOTPAGEOFF]
Lloh7:
	ldr	w21, [x8]
	mov	w0, #17
	bl	_HSIO_PLL5G_CFG0_CORE_CLK_DIV
	mov	x22, x0
	mov	w0, #2
	bl	_HSIO_PLL5G_CFG0_CPU_CLK_DIV
	orr	w8, w0, w22
Lloh8:
	adrp	x9, _HSIO_PLL5G_CFG0_ENA_BIAS@GOTPAGE
Lloh9:
	ldr	x9, [x9, _HSIO_PLL5G_CFG0_ENA_BIAS@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh11:
	adrp	x9, _HSIO_PLL5G_CFG0_ENA_VCO_BUF@GOTPAGE
Lloh12:
	ldr	x9, [x9, _HSIO_PLL5G_CFG0_ENA_VCO_BUF@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh14:
	adrp	x9, _HSIO_PLL5G_CFG0_ENA_CP1@GOTPAGE
Lloh15:
	ldr	x9, [x9, _HSIO_PLL5G_CFG0_ENA_CP1@GOTPAGEOFF]
Lloh16:
	ldr	w9, [x9]
	orr	w22, w8, w9
	mov	w0, #2
	bl	_HSIO_PLL5G_CFG0_SELCPI
	orr	w22, w22, w0
	mov	w0, #14
	bl	_HSIO_PLL5G_CFG0_LOOP_BW_RES
	orr	w22, w22, w0
	mov	w0, #4
	bl	_HSIO_PLL5G_CFG0_SELBGV820
	orr	w8, w22, w0
Lloh17:
	adrp	x9, _HSIO_PLL5G_CFG0_DIV4@GOTPAGE
Lloh18:
	ldr	x9, [x9, _HSIO_PLL5G_CFG0_DIV4@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh20:
	adrp	x9, _HSIO_PLL5G_CFG0_ENA_CLKTREE@GOTPAGE
Lloh21:
	ldr	x9, [x9, _HSIO_PLL5G_CFG0_ENA_CLKTREE@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh23:
	adrp	x9, _HSIO_PLL5G_CFG0_ENA_LANE@GOTPAGE
Lloh24:
	ldr	x9, [x9, _HSIO_PLL5G_CFG0_ENA_LANE@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x20
	mov	x1, x21
	bl	_regmap_write
	ldr	x8, [x19]
	ldr	x9, [x23]
	ldr	w19, [x8, x9, lsl #2]
Lloh26:
	adrp	x8, _HSIO_PLL5G_CFG2@GOTPAGE
Lloh27:
	ldr	x8, [x8, _HSIO_PLL5G_CFG2@GOTPAGEOFF]
Lloh28:
	adrp	x9, _HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET@GOTPAGE
Lloh29:
	ldr	x9, [x9, _HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET@GOTPAGEOFF]
Lloh30:
	ldr	w20, [x8]
Lloh31:
	ldr	w8, [x9]
Lloh32:
	adrp	x9, _HSIO_PLL5G_CFG2_EN_RESET_OVERRUN@GOTPAGE
Lloh33:
	ldr	x9, [x9, _HSIO_PLL5G_CFG2_EN_RESET_OVERRUN@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w21, w9, w8
	mov	w0, #8
	bl	_HSIO_PLL5G_CFG2_GAIN_TEST
	orr	w8, w21, w0
Lloh35:
	adrp	x9, _HSIO_PLL5G_CFG2_ENA_AMPCTRL@GOTPAGE
Lloh36:
	ldr	x9, [x9, _HSIO_PLL5G_CFG2_ENA_AMPCTRL@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh38:
	adrp	x9, _HSIO_PLL5G_CFG2_PWD_AMPCTRL_N@GOTPAGE
Lloh39:
	ldr	x9, [x9, _HSIO_PLL5G_CFG2_PWD_AMPCTRL_N@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w21, w8, w9
	mov	w0, #16
	bl	_HSIO_PLL5G_CFG2_AMPC_SEL
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_regmap_write
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh30
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_HSIO,8,3                       ; @HSIO
	.comm	_HSIO_PLL5G_CFG4,4,2            ; @HSIO_PLL5G_CFG4
	.comm	_HSIO_PLL5G_CFG0,4,2            ; @HSIO_PLL5G_CFG0
	.comm	_HSIO_PLL5G_CFG0_ENA_BIAS,4,2   ; @HSIO_PLL5G_CFG0_ENA_BIAS
	.comm	_HSIO_PLL5G_CFG0_ENA_VCO_BUF,4,2 ; @HSIO_PLL5G_CFG0_ENA_VCO_BUF
	.comm	_HSIO_PLL5G_CFG0_ENA_CP1,4,2    ; @HSIO_PLL5G_CFG0_ENA_CP1
	.comm	_HSIO_PLL5G_CFG0_DIV4,4,2       ; @HSIO_PLL5G_CFG0_DIV4
	.comm	_HSIO_PLL5G_CFG0_ENA_CLKTREE,4,2 ; @HSIO_PLL5G_CFG0_ENA_CLKTREE
	.comm	_HSIO_PLL5G_CFG0_ENA_LANE,4,2   ; @HSIO_PLL5G_CFG0_ENA_LANE
	.comm	_HSIO_PLL5G_CFG2,4,2            ; @HSIO_PLL5G_CFG2
	.comm	_HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET,4,2 ; @HSIO_PLL5G_CFG2_EN_RESET_FRQ_DET
	.comm	_HSIO_PLL5G_CFG2_EN_RESET_OVERRUN,4,2 ; @HSIO_PLL5G_CFG2_EN_RESET_OVERRUN
	.comm	_HSIO_PLL5G_CFG2_ENA_AMPCTRL,4,2 ; @HSIO_PLL5G_CFG2_ENA_AMPCTRL
	.comm	_HSIO_PLL5G_CFG2_PWD_AMPCTRL_N,4,2 ; @HSIO_PLL5G_CFG2_PWD_AMPCTRL_N
	.no_dead_strip	_ocelot_pll5_init
.subsections_via_symbols
