	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xlgmac_config_mtl_mode
_xlgmac_config_mtl_mode:                ## @xlgmac_config_mtl_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_MTL_OMR@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r14), %rdi
	callq	_readl
	movq	_MTL_OMR_ETSALG_POS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MTL_OMR_ETSALG_LEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MTL_ETSALG_WRR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_XLGMAC_SET_REG_BITS
	movq	(%rbx), %rsi
	addq	(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	cmpl	$0, 8(%r14)
	je	LBB0_3
## %bb.1:
	xorl	%ebx, %ebx
	movq	_MTL_TC_ETSCR@GOTPCREL(%rip), %r13
	movq	_MTL_TC_QWR@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r13), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_XLGMAC_MTL_REG
	movq	%rax, %rdi
	callq	_readl
	movq	_MTL_TC_ETSCR_TSA_POS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MTL_TC_ETSCR_TSA_LEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MTL_TSA_ETS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_XLGMAC_SET_REG_BITS
	movl	%eax, %r15d
	movl	(%r13), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_XLGMAC_MTL_REG
	movl	%r15d, %edi
	movq	%rax, %rsi
	callq	_writel
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_XLGMAC_MTL_REG
	movq	%rax, %rdi
	callq	_readl
	movq	_MTL_TC_QWR_QW_POS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MTL_TC_QWR_QW_LEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%eax, %edi
	movl	$1, %ecx
	callq	_XLGMAC_SET_REG_BITS
	movl	%eax, %r15d
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_XLGMAC_MTL_REG
	movl	%r15d, %edi
	movq	%rax, %rsi
	callq	_writel
	incl	%ebx
	cmpl	8(%r14), %ebx
	jb	LBB0_2
LBB0_3:
	movq	_MTL_OMR@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	(%r14), %rdi
	callq	_readl
	movq	_MTL_OMR_RAA_POS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_MTL_OMR_RAA_LEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_MTL_RAA_SP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%eax, %edi
	callq	_XLGMAC_SET_REG_BITS
	movq	(%rbx), %rsi
	addq	(%r14), %rsi
	movl	%eax, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MTL_OMR,8,3                    ## @MTL_OMR
	.comm	_MTL_OMR_ETSALG_POS,4,2         ## @MTL_OMR_ETSALG_POS
	.comm	_MTL_OMR_ETSALG_LEN,4,2         ## @MTL_OMR_ETSALG_LEN
	.comm	_MTL_ETSALG_WRR,4,2             ## @MTL_ETSALG_WRR
	.comm	_MTL_TC_ETSCR,4,2               ## @MTL_TC_ETSCR
	.comm	_MTL_TC_ETSCR_TSA_POS,4,2       ## @MTL_TC_ETSCR_TSA_POS
	.comm	_MTL_TC_ETSCR_TSA_LEN,4,2       ## @MTL_TC_ETSCR_TSA_LEN
	.comm	_MTL_TSA_ETS,4,2                ## @MTL_TSA_ETS
	.comm	_MTL_TC_QWR,4,2                 ## @MTL_TC_QWR
	.comm	_MTL_TC_QWR_QW_POS,4,2          ## @MTL_TC_QWR_QW_POS
	.comm	_MTL_TC_QWR_QW_LEN,4,2          ## @MTL_TC_QWR_QW_LEN
	.comm	_MTL_OMR_RAA_POS,4,2            ## @MTL_OMR_RAA_POS
	.comm	_MTL_OMR_RAA_LEN,4,2            ## @MTL_OMR_RAA_LEN
	.comm	_MTL_RAA_SP,4,2                 ## @MTL_RAA_SP
	.no_dead_strip	_xlgmac_config_mtl_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xlgmac_config_mtl_mode
_xlgmac_config_mtl_mode:                ; @xlgmac_config_mtl_mode
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x20, _MTL_OMR@GOTPAGE
Lloh1:
	ldr	x20, [x20, _MTL_OMR@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh2:
	adrp	x8, _MTL_OMR_ETSALG_POS@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MTL_OMR_ETSALG_POS@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
Lloh5:
	adrp	x8, _MTL_OMR_ETSALG_LEN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MTL_OMR_ETSALG_LEN@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
Lloh8:
	adrp	x8, _MTL_ETSALG_WRR@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MTL_ETSALG_WRR@GOTPAGEOFF]
Lloh10:
	ldr	w3, [x8]
	bl	_XLGMAC_SET_REG_BITS
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writel
	ldr	w8, [x19, #8]
	cbz	w8, LBB0_3
; %bb.1:
	mov	w20, #0
Lloh11:
	adrp	x23, _MTL_TC_ETSCR@GOTPAGE
Lloh12:
	ldr	x23, [x23, _MTL_TC_ETSCR@GOTPAGEOFF]
Lloh13:
	adrp	x24, _MTL_TC_ETSCR_TSA_POS@GOTPAGE
Lloh14:
	ldr	x24, [x24, _MTL_TC_ETSCR_TSA_POS@GOTPAGEOFF]
Lloh15:
	adrp	x25, _MTL_TC_ETSCR_TSA_LEN@GOTPAGE
Lloh16:
	ldr	x25, [x25, _MTL_TC_ETSCR_TSA_LEN@GOTPAGEOFF]
Lloh17:
	adrp	x26, _MTL_TSA_ETS@GOTPAGE
Lloh18:
	ldr	x26, [x26, _MTL_TSA_ETS@GOTPAGEOFF]
Lloh19:
	adrp	x27, _MTL_TC_QWR@GOTPAGE
Lloh20:
	ldr	x27, [x27, _MTL_TC_QWR@GOTPAGEOFF]
Lloh21:
	adrp	x28, _MTL_TC_QWR_QW_POS@GOTPAGE
Lloh22:
	ldr	x28, [x28, _MTL_TC_QWR_QW_POS@GOTPAGEOFF]
Lloh23:
	adrp	x22, _MTL_TC_QWR_QW_LEN@GOTPAGE
Lloh24:
	ldr	x22, [x22, _MTL_TC_QWR_QW_LEN@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x20
	bl	_XLGMAC_MTL_REG
	bl	_readl
	ldr	w1, [x24]
	ldr	w2, [x25]
	ldr	w3, [x26]
	bl	_XLGMAC_SET_REG_BITS
	mov	x21, x0
	ldr	w2, [x23]
	mov	x0, x19
	mov	x1, x20
	bl	_XLGMAC_MTL_REG
	mov	x1, x0
	mov	x0, x21
	bl	_writel
	ldr	w2, [x27]
	mov	x0, x19
	mov	x1, x20
	bl	_XLGMAC_MTL_REG
	bl	_readl
	ldr	w1, [x28]
	ldr	w2, [x22]
	mov	w3, #1
	bl	_XLGMAC_SET_REG_BITS
	mov	x21, x0
	ldr	w2, [x27]
	mov	x0, x19
	mov	x1, x20
	bl	_XLGMAC_MTL_REG
	mov	x1, x0
	mov	x0, x21
	bl	_writel
	add	w20, w20, #1
	ldr	w8, [x19, #8]
	cmp	w20, w8
	b.lo	LBB0_2
LBB0_3:
	ldr	x8, [x19]
Lloh25:
	adrp	x20, _MTL_OMR@GOTPAGE
Lloh26:
	ldr	x20, [x20, _MTL_OMR@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh27:
	adrp	x8, _MTL_OMR_RAA_POS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MTL_OMR_RAA_POS@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
Lloh30:
	adrp	x8, _MTL_OMR_RAA_LEN@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MTL_OMR_RAA_LEN@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
Lloh33:
	adrp	x8, _MTL_RAA_SP@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MTL_RAA_SP@GOTPAGEOFF]
Lloh35:
	ldr	w3, [x8]
	bl	_XLGMAC_SET_REG_BITS
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_MTL_OMR,8,3                    ; @MTL_OMR
	.comm	_MTL_OMR_ETSALG_POS,4,2         ; @MTL_OMR_ETSALG_POS
	.comm	_MTL_OMR_ETSALG_LEN,4,2         ; @MTL_OMR_ETSALG_LEN
	.comm	_MTL_ETSALG_WRR,4,2             ; @MTL_ETSALG_WRR
	.comm	_MTL_TC_ETSCR,4,2               ; @MTL_TC_ETSCR
	.comm	_MTL_TC_ETSCR_TSA_POS,4,2       ; @MTL_TC_ETSCR_TSA_POS
	.comm	_MTL_TC_ETSCR_TSA_LEN,4,2       ; @MTL_TC_ETSCR_TSA_LEN
	.comm	_MTL_TSA_ETS,4,2                ; @MTL_TSA_ETS
	.comm	_MTL_TC_QWR,4,2                 ; @MTL_TC_QWR
	.comm	_MTL_TC_QWR_QW_POS,4,2          ; @MTL_TC_QWR_QW_POS
	.comm	_MTL_TC_QWR_QW_LEN,4,2          ; @MTL_TC_QWR_QW_LEN
	.comm	_MTL_OMR_RAA_POS,4,2            ; @MTL_OMR_RAA_POS
	.comm	_MTL_OMR_RAA_LEN,4,2            ; @MTL_OMR_RAA_LEN
	.comm	_MTL_RAA_SP,4,2                 ; @MTL_RAA_SP
	.no_dead_strip	_xlgmac_config_mtl_mode
.subsections_via_symbols
