	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvebu_pci_bridge_emul_base_conf_write
_mvebu_pci_bridge_emul_base_conf_write: ## @mvebu_pci_bridge_emul_base_conf_write
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
                                        ## kill: def $esi killed $esi def $rsi
	addl	$-128, %esi
	cmpl	$4, %esi
	ja	LBB0_11
## %bb.1:
	movl	%ecx, %r14d
	movq	%rdi, %rbx
	movq	16(%rdi), %r15
	leaq	LJTI0_0(%rip), %rax
	movslq	(%rax,%rsi,4), %rcx
	addq	%rax, %rcx
	jmpq	*%rcx
LBB0_10:
	movl	4(%rbx), %esi
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvebu_pcie_set_local_bus_nr    ## TAILCALL
LBB0_8:
	movq	_PCI_IO_RANGE_TYPE_32@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	%eax, 12(%rbx)
	orl	%eax, 8(%rbx)
LBB0_9:
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvebu_pcie_handle_iobase_change ## TAILCALL
LBB0_2:
	movl	%edx, %r12d
	movq	%r15, %rdi
	callq	_mvebu_has_ioport
	testl	%eax, %eax
	jne	LBB0_4
## %bb.3:
	movq	_PCI_COMMAND_IO@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, (%rbx)
LBB0_4:
	xorl	%r12d, %r14d
	movq	_PCI_COMMAND_IO@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_6
## %bb.5:
	movq	%r15, %rdi
	callq	_mvebu_pcie_handle_iobase_change
LBB0_6:
	movq	_PCI_COMMAND_MEMORY@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_11
LBB0_7:
	movq	%r15, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvebu_pcie_handle_membase_change ## TAILCALL
LBB0_11:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
LJTI0_0:
	.long	L0_0_set_10
	.long	L0_0_set_7
	.long	L0_0_set_9
	.long	L0_0_set_8
	.long	L0_0_set_2
	.end_data_region
                                        ## -- End function
	.comm	_PCI_COMMAND_IO,4,2             ## @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,4,2         ## @PCI_COMMAND_MEMORY
	.comm	_PCI_IO_RANGE_TYPE_32,4,2       ## @PCI_IO_RANGE_TYPE_32
	.no_dead_strip	_mvebu_pci_bridge_emul_base_conf_write
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvebu_pci_bridge_emul_base_conf_write
_mvebu_pci_bridge_emul_base_conf_write: ; @mvebu_pci_bridge_emul_base_conf_write
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	sub	w8, w1, #128
	cmp	w8, #4
	b.hi	LBB0_11
; %bb.1:
	mov	x20, x0
	ldr	x19, [x0, #16]
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	ldr	w1, [x20, #4]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mvebu_pcie_set_local_bus_nr
LBB0_3:
Lloh2:
	adrp	x8, _PCI_IO_RANGE_TYPE_32@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCI_IO_RANGE_TYPE_32@GOTPAGEOFF]
	ldr	d0, [x20, #8]
	ld1r.2s	{ v1 }, [x8]
	orr.8b	v0, v0, v1
	str	d0, [x20, #8]
LBB0_4:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mvebu_pcie_handle_iobase_change
LBB0_5:
	mov	x21, x3
	mov	x22, x2
	mov	x0, x19
	bl	_mvebu_has_ioport
Lloh4:
	adrp	x8, _PCI_COMMAND_IO@GOTPAGE
Lloh5:
	ldr	x8, [x8, _PCI_COMMAND_IO@GOTPAGEOFF]
	cbnz	w0, LBB0_7
; %bb.6:
	ldr	w9, [x8]
	ldr	w10, [x20]
	bic	w9, w10, w9
	str	w9, [x20]
LBB0_7:
	eor	w20, w21, w22
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_9
; %bb.8:
	mov	x0, x19
	bl	_mvebu_pcie_handle_iobase_change
LBB0_9:
Lloh6:
	adrp	x8, _PCI_COMMAND_MEMORY@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCI_COMMAND_MEMORY@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w20
	b.eq	LBB0_11
LBB0_10:
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_mvebu_pcie_handle_membase_change
LBB0_11:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_10-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
                                        ; -- End function
	.comm	_PCI_COMMAND_IO,4,2             ; @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,4,2         ; @PCI_COMMAND_MEMORY
	.comm	_PCI_IO_RANGE_TYPE_32,4,2       ; @PCI_IO_RANGE_TYPE_32
	.no_dead_strip	_mvebu_pci_bridge_emul_base_conf_write
.subsections_via_symbols
