	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function brcmf_pcie_reset_device
_brcmf_pcie_reset_device:               ## @brcmf_pcie_reset_device
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$120, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movq	_BRCMF_PCIE_CFGREG_STATUS_CMD@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -144(%rbp)
	movq	_BRCMF_PCIE_CFGREG_PM_CSR@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -136(%rbp)
	movq	_BRCMF_PCIE_CFGREG_MSI_CAP@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -128(%rbp)
	movq	_BRCMF_PCIE_CFGREG_MSI_ADDR_L@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -120(%rbp)
	movq	_BRCMF_PCIE_CFGREG_MSI_ADDR_H@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -112(%rbp)
	movq	_BRCMF_PCIE_CFGREG_MSI_DATA@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -104(%rbp)
	movq	_BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -96(%rbp)
	movq	_BRCMF_PCIE_CFGREG_RBAR_CTRL@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -88(%rbp)
	movq	_BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -80(%rbp)
	movq	_BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -72(%rbp)
	movq	_BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -64(%rbp)
	cmpl	$0, (%rdi)
	je	LBB0_5
## %bb.1:
	movq	%rdi, %r12
	movq	_BCMA_CORE_PCIE2@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_brcmf_pcie_select_core
	movl	4(%r12), %edi
	movq	_BRCMF_PCIE_REG_LINK_STATUS_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-152(%rbp), %rdx
	callq	_pci_read_config_dword
	movq	_BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	notq	%rdx
	andq	-152(%rbp), %rdx
	movl	4(%r12), %edi
	movl	(%rbx), %esi
	callq	_pci_write_config_dword
	movq	_BCMA_CORE_CHIPCOMMON@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_brcmf_pcie_select_core
	movq	_watchdog@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$4, %edx
	callq	_WRITECC32
	movl	$100, %edi
	callq	_msleep
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_brcmf_pcie_select_core
	movl	4(%r12), %edi
	movl	(%rbx), %esi
	movq	-152(%rbp), %rdx
	callq	_pci_write_config_dword
	movl	(%r12), %edi
	movl	(%r14), %esi
	callq	_brcmf_chip_get_core
	cmpl	$13, (%rax)
	jg	LBB0_5
## %bb.2:
	leaq	-144(%rbp), %rdi
	callq	_ARRAY_SIZE
	testq	%rax, %rax
	je	LBB0_5
## %bb.3:
	xorl	%ebx, %ebx
	movq	_BRCMF_PCIE_PCIE2REG_CONFIGDATA@GOTPCREL(%rip), %r14
	leaq	-144(%rbp), %r15
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	_BRCMF_PCIE_PCIE2REG_CONFIGADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	-144(%rbp,%rbx,8), %rdx
	movq	%r12, %rdi
	callq	_brcmf_pcie_write_reg32
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_brcmf_pcie_read_reg32
	movq	%rax, %r13
	movq	_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	-144(%rbp,%rbx,8), %rdx
	leaq	L_.str(%rip), %rsi
	movq	%r13, %rcx
	callq	_brcmf_dbg
	movl	(%r14), %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	callq	_brcmf_pcie_write_reg32
	incq	%rbx
	movq	%r15, %rdi
	callq	_ARRAY_SIZE
	cmpq	%rax, %rbx
	jb	LBB0_4
LBB0_5:
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_7
## %bb.6:
	addq	$120, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_BRCMF_PCIE_CFGREG_STATUS_CMD,8,3 ## @BRCMF_PCIE_CFGREG_STATUS_CMD
	.comm	_BRCMF_PCIE_CFGREG_PM_CSR,8,3   ## @BRCMF_PCIE_CFGREG_PM_CSR
	.comm	_BRCMF_PCIE_CFGREG_MSI_CAP,8,3  ## @BRCMF_PCIE_CFGREG_MSI_CAP
	.comm	_BRCMF_PCIE_CFGREG_MSI_ADDR_L,8,3 ## @BRCMF_PCIE_CFGREG_MSI_ADDR_L
	.comm	_BRCMF_PCIE_CFGREG_MSI_ADDR_H,8,3 ## @BRCMF_PCIE_CFGREG_MSI_ADDR_H
	.comm	_BRCMF_PCIE_CFGREG_MSI_DATA,8,3 ## @BRCMF_PCIE_CFGREG_MSI_DATA
	.comm	_BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,8,3 ## @BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2
	.comm	_BRCMF_PCIE_CFGREG_RBAR_CTRL,8,3 ## @BRCMF_PCIE_CFGREG_RBAR_CTRL
	.comm	_BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,8,3 ## @BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1
	.comm	_BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,8,3 ## @BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG
	.comm	_BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG,8,3 ## @BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG
	.comm	_BCMA_CORE_PCIE2,4,2            ## @BCMA_CORE_PCIE2
	.comm	_BRCMF_PCIE_REG_LINK_STATUS_CTRL,4,2 ## @BRCMF_PCIE_REG_LINK_STATUS_CTRL
	.comm	_BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB,8,3 ## @BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB
	.comm	_BCMA_CORE_CHIPCOMMON,4,2       ## @BCMA_CORE_CHIPCOMMON
	.comm	_watchdog,4,2                   ## @watchdog
	.comm	_BRCMF_PCIE_PCIE2REG_CONFIGADDR,4,2 ## @BRCMF_PCIE_PCIE2REG_CONFIGADDR
	.comm	_BRCMF_PCIE_PCIE2REG_CONFIGDATA,4,2 ## @BRCMF_PCIE_PCIE2REG_CONFIGDATA
	.comm	_PCIE,4,2                       ## @PCIE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"config offset 0x%04x, value 0x%04x\n"

	.no_dead_strip	_brcmf_pcie_reset_device
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function brcmf_pcie_reset_device
_brcmf_pcie_reset_device:               ; @brcmf_pcie_reset_device
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #208
	.cfi_def_cfa_offset 208
	stp	x28, x27, [sp, #112]            ; 16-byte Folded Spill
	stp	x26, x25, [sp, #128]            ; 16-byte Folded Spill
	stp	x24, x23, [sp, #144]            ; 16-byte Folded Spill
	stp	x22, x21, [sp, #160]            ; 16-byte Folded Spill
	stp	x20, x19, [sp, #176]            ; 16-byte Folded Spill
	stp	x29, x30, [sp, #192]            ; 16-byte Folded Spill
	add	x29, sp, #192
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-88]
Lloh3:
	adrp	x8, _BRCMF_PCIE_CFGREG_STATUS_CMD@GOTPAGE
Lloh4:
	ldr	x8, [x8, _BRCMF_PCIE_CFGREG_STATUS_CMD@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
Lloh6:
	adrp	x9, _BRCMF_PCIE_CFGREG_PM_CSR@GOTPAGE
Lloh7:
	ldr	x9, [x9, _BRCMF_PCIE_CFGREG_PM_CSR@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
Lloh9:
	adrp	x10, _BRCMF_PCIE_CFGREG_MSI_CAP@GOTPAGE
Lloh10:
	ldr	x10, [x10, _BRCMF_PCIE_CFGREG_MSI_CAP@GOTPAGEOFF]
	stp	x8, x9, [sp, #16]
Lloh11:
	ldr	x8, [x10]
Lloh12:
	adrp	x9, _BRCMF_PCIE_CFGREG_MSI_ADDR_L@GOTPAGE
Lloh13:
	ldr	x9, [x9, _BRCMF_PCIE_CFGREG_MSI_ADDR_L@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	stp	x8, x9, [sp, #32]
Lloh15:
	adrp	x8, _BRCMF_PCIE_CFGREG_MSI_ADDR_H@GOTPAGE
Lloh16:
	ldr	x8, [x8, _BRCMF_PCIE_CFGREG_MSI_ADDR_H@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
Lloh18:
	adrp	x9, _BRCMF_PCIE_CFGREG_MSI_DATA@GOTPAGE
Lloh19:
	ldr	x9, [x9, _BRCMF_PCIE_CFGREG_MSI_DATA@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	stp	x8, x9, [sp, #48]
Lloh21:
	adrp	x8, _BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2@GOTPAGE
Lloh22:
	ldr	x8, [x8, _BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2@GOTPAGEOFF]
Lloh23:
	ldr	x8, [x8]
Lloh24:
	adrp	x9, _BRCMF_PCIE_CFGREG_RBAR_CTRL@GOTPAGE
Lloh25:
	ldr	x9, [x9, _BRCMF_PCIE_CFGREG_RBAR_CTRL@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
Lloh27:
	adrp	x10, _BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1@GOTPAGE
Lloh28:
	ldr	x10, [x10, _BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1@GOTPAGEOFF]
	stp	x8, x9, [sp, #64]
Lloh29:
	ldr	x8, [x10]
Lloh30:
	adrp	x9, _BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG@GOTPAGE
Lloh31:
	ldr	x9, [x9, _BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	stp	x8, x9, [sp, #80]
Lloh33:
	adrp	x8, _BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG@GOTPAGEOFF]
Lloh35:
	ldr	x8, [x8]
	str	x8, [sp, #96]
	ldr	w8, [x0]
	cbz	w8, LBB0_5
; %bb.1:
	mov	x19, x0
Lloh36:
	adrp	x20, _BCMA_CORE_PCIE2@GOTPAGE
Lloh37:
	ldr	x20, [x20, _BCMA_CORE_PCIE2@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_brcmf_pcie_select_core
	ldr	w0, [x19, #4]
Lloh38:
	adrp	x21, _BRCMF_PCIE_REG_LINK_STATUS_CTRL@GOTPAGE
Lloh39:
	ldr	x21, [x21, _BRCMF_PCIE_REG_LINK_STATUS_CTRL@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #8
	bl	_pci_read_config_dword
	ldr	x8, [sp, #8]
Lloh40:
	adrp	x9, _BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB@GOTPAGE
Lloh41:
	ldr	x9, [x9, _BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	bic	x2, x8, x9
	ldr	w0, [x19, #4]
	ldr	w1, [x21]
	bl	_pci_write_config_dword
Lloh43:
	adrp	x8, _BCMA_CORE_CHIPCOMMON@GOTPAGE
Lloh44:
	ldr	x8, [x8, _BCMA_CORE_CHIPCOMMON@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_brcmf_pcie_select_core
Lloh46:
	adrp	x8, _watchdog@GOTPAGE
Lloh47:
	ldr	x8, [x8, _watchdog@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #4
	bl	_WRITECC32
	mov	w0, #100
	bl	_msleep
	ldr	w1, [x20]
	mov	x0, x19
	bl	_brcmf_pcie_select_core
	ldr	w0, [x19, #4]
	ldr	w1, [x21]
	ldr	x2, [sp, #8]
	bl	_pci_write_config_dword
	ldr	w0, [x19]
	ldr	w1, [x20]
	bl	_brcmf_chip_get_core
	ldr	w8, [x0]
	cmp	w8, #13
	b.gt	LBB0_5
; %bb.2:
	add	x22, sp, #16
	add	x0, sp, #16
	bl	_ARRAY_SIZE
	cbz	x0, LBB0_5
; %bb.3:
	mov	x23, #0
Lloh49:
	adrp	x24, _BRCMF_PCIE_PCIE2REG_CONFIGADDR@GOTPAGE
Lloh50:
	ldr	x24, [x24, _BRCMF_PCIE_PCIE2REG_CONFIGADDR@GOTPAGEOFF]
Lloh51:
	adrp	x25, _BRCMF_PCIE_PCIE2REG_CONFIGDATA@GOTPAGE
Lloh52:
	ldr	x25, [x25, _BRCMF_PCIE_PCIE2REG_CONFIGDATA@GOTPAGEOFF]
Lloh53:
	adrp	x26, _PCIE@GOTPAGE
Lloh54:
	ldr	x26, [x26, _PCIE@GOTPAGEOFF]
Lloh55:
	adrp	x20, l_.str@PAGE
Lloh56:
	add	x20, x20, l_.str@PAGEOFF
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w1, [x24]
	lsl	x27, x23, #3
	ldr	x2, [x22, x27]
	mov	x0, x19
	bl	_brcmf_pcie_write_reg32
	ldr	w1, [x25]
	mov	x0, x19
	bl	_brcmf_pcie_read_reg32
	mov	x21, x0
	ldr	w0, [x26]
	ldr	x2, [x22, x27]
	mov	x1, x20
	mov	x3, x21
	bl	_brcmf_dbg
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x21
	bl	_brcmf_pcie_write_reg32
	add	x23, x23, #1
	add	x0, sp, #16
	bl	_ARRAY_SIZE
	cmp	x23, x0
	b.lo	LBB0_4
LBB0_5:
	ldur	x8, [x29, #-88]
Lloh57:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh58:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh59:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_7
; %bb.6:
	ldp	x29, x30, [sp, #192]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #176]            ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #160]            ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #144]            ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #128]            ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #112]            ; 16-byte Folded Reload
	add	sp, sp, #208
	ret
LBB0_7:
	bl	___stack_chk_fail
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.cfi_endproc
                                        ; -- End function
	.comm	_BRCMF_PCIE_CFGREG_STATUS_CMD,8,3 ; @BRCMF_PCIE_CFGREG_STATUS_CMD
	.comm	_BRCMF_PCIE_CFGREG_PM_CSR,8,3   ; @BRCMF_PCIE_CFGREG_PM_CSR
	.comm	_BRCMF_PCIE_CFGREG_MSI_CAP,8,3  ; @BRCMF_PCIE_CFGREG_MSI_CAP
	.comm	_BRCMF_PCIE_CFGREG_MSI_ADDR_L,8,3 ; @BRCMF_PCIE_CFGREG_MSI_ADDR_L
	.comm	_BRCMF_PCIE_CFGREG_MSI_ADDR_H,8,3 ; @BRCMF_PCIE_CFGREG_MSI_ADDR_H
	.comm	_BRCMF_PCIE_CFGREG_MSI_DATA,8,3 ; @BRCMF_PCIE_CFGREG_MSI_DATA
	.comm	_BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,8,3 ; @BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2
	.comm	_BRCMF_PCIE_CFGREG_RBAR_CTRL,8,3 ; @BRCMF_PCIE_CFGREG_RBAR_CTRL
	.comm	_BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,8,3 ; @BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1
	.comm	_BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,8,3 ; @BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG
	.comm	_BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG,8,3 ; @BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG
	.comm	_BCMA_CORE_PCIE2,4,2            ; @BCMA_CORE_PCIE2
	.comm	_BRCMF_PCIE_REG_LINK_STATUS_CTRL,4,2 ; @BRCMF_PCIE_REG_LINK_STATUS_CTRL
	.comm	_BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB,8,3 ; @BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB
	.comm	_BCMA_CORE_CHIPCOMMON,4,2       ; @BCMA_CORE_CHIPCOMMON
	.comm	_watchdog,4,2                   ; @watchdog
	.comm	_BRCMF_PCIE_PCIE2REG_CONFIGADDR,4,2 ; @BRCMF_PCIE_PCIE2REG_CONFIGADDR
	.comm	_BRCMF_PCIE_PCIE2REG_CONFIGDATA,4,2 ; @BRCMF_PCIE_PCIE2REG_CONFIGDATA
	.comm	_PCIE,4,2                       ; @PCIE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"config offset 0x%04x, value 0x%04x\n"

	.no_dead_strip	_brcmf_pcie_reset_device
.subsections_via_symbols
