	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function hclge_parse_cfg
_hclge_parse_cfg:                       ## @hclge_parse_cfg
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	(%rsi), %r12
	movq	(%r12), %rax
	movl	(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_VMDQ_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_VMDQ_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 88(%r15)
	movq	(%r12), %rax
	movl	(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_TC_NUM_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_TC_NUM_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 80(%r15)
	movq	(%r12), %rax
	movl	(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_TQP_DESC_N_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_TQP_DESC_N_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 72(%r15)
	movq	(%r12), %rax
	movl	4(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_PHY_ADDR_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_PHY_ADDR_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 64(%r15)
	movq	(%r12), %rax
	movl	4(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_MEDIA_TP_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_MEDIA_TP_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 56(%r15)
	movq	(%r12), %rax
	movl	4(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_RX_BUF_LEN_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_RX_BUF_LEN_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 48(%r15)
	movq	(%r12), %rax
	movl	8(%rax), %edi
	callq	___le32_to_cpu
	movq	%rax, %rbx
	movq	(%r12), %rax
	movl	12(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_MAC_ADDR_H_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_MAC_ADDR_H_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	(%r12), %rax
	movl	12(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_DEFAULT_SPEED_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_DEFAULT_SPEED_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 40(%r15)
	movq	(%r12), %rax
	movl	12(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_RSS_SIZE_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_RSS_SIZE_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 32(%r15)
	movq	_ETH_ALEN@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	je	LBB0_3
## %bb.1:
	movq	(%r15), %rdx
	xorl	%ecx, %ecx
	xorl	%esi, %esi
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	sarl	%cl, %edi
	movzbl	%dil, %edi
	movl	%edi, (%rdx,%rsi,4)
	incq	%rsi
	movl	(%rax), %edi
	addl	$8, %ecx
	cmpq	%rdi, %rsi
	jb	LBB0_2
LBB0_3:
	movq	8(%r14), %rbx
	movq	(%rbx), %rax
	movl	(%rax), %edi
	callq	___le32_to_cpu
	movq	%rax, 24(%r15)
	movq	(%rbx), %rax
	movl	4(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_SPEED_ABILITY_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_SPEED_ABILITY_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 16(%r15)
	movq	(%rbx), %rax
	movl	4(%rax), %edi
	callq	___le32_to_cpu
	movq	_HCLGE_CFG_UMV_TBL_SPACE_M@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_HCLGE_CFG_UMV_TBL_SPACE_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rax, %rdi
	callq	_hnae3_get_field
	movq	%rax, 8(%r15)
	testq	%rax, %rax
	jne	LBB0_5
## %bb.4:
	movq	_HCLGE_DEFAULT_UMV_SPACE_PER_PF@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 8(%r15)
LBB0_5:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HCLGE_CFG_VMDQ_M,4,2           ## @HCLGE_CFG_VMDQ_M
	.comm	_HCLGE_CFG_VMDQ_S,4,2           ## @HCLGE_CFG_VMDQ_S
	.comm	_HCLGE_CFG_TC_NUM_M,4,2         ## @HCLGE_CFG_TC_NUM_M
	.comm	_HCLGE_CFG_TC_NUM_S,4,2         ## @HCLGE_CFG_TC_NUM_S
	.comm	_HCLGE_CFG_TQP_DESC_N_M,4,2     ## @HCLGE_CFG_TQP_DESC_N_M
	.comm	_HCLGE_CFG_TQP_DESC_N_S,4,2     ## @HCLGE_CFG_TQP_DESC_N_S
	.comm	_HCLGE_CFG_PHY_ADDR_M,4,2       ## @HCLGE_CFG_PHY_ADDR_M
	.comm	_HCLGE_CFG_PHY_ADDR_S,4,2       ## @HCLGE_CFG_PHY_ADDR_S
	.comm	_HCLGE_CFG_MEDIA_TP_M,4,2       ## @HCLGE_CFG_MEDIA_TP_M
	.comm	_HCLGE_CFG_MEDIA_TP_S,4,2       ## @HCLGE_CFG_MEDIA_TP_S
	.comm	_HCLGE_CFG_RX_BUF_LEN_M,4,2     ## @HCLGE_CFG_RX_BUF_LEN_M
	.comm	_HCLGE_CFG_RX_BUF_LEN_S,4,2     ## @HCLGE_CFG_RX_BUF_LEN_S
	.comm	_HCLGE_CFG_MAC_ADDR_H_M,4,2     ## @HCLGE_CFG_MAC_ADDR_H_M
	.comm	_HCLGE_CFG_MAC_ADDR_H_S,4,2     ## @HCLGE_CFG_MAC_ADDR_H_S
	.comm	_HCLGE_CFG_DEFAULT_SPEED_M,4,2  ## @HCLGE_CFG_DEFAULT_SPEED_M
	.comm	_HCLGE_CFG_DEFAULT_SPEED_S,4,2  ## @HCLGE_CFG_DEFAULT_SPEED_S
	.comm	_HCLGE_CFG_RSS_SIZE_M,4,2       ## @HCLGE_CFG_RSS_SIZE_M
	.comm	_HCLGE_CFG_RSS_SIZE_S,4,2       ## @HCLGE_CFG_RSS_SIZE_S
	.comm	_ETH_ALEN,4,2                   ## @ETH_ALEN
	.comm	_HCLGE_CFG_SPEED_ABILITY_M,4,2  ## @HCLGE_CFG_SPEED_ABILITY_M
	.comm	_HCLGE_CFG_SPEED_ABILITY_S,4,2  ## @HCLGE_CFG_SPEED_ABILITY_S
	.comm	_HCLGE_CFG_UMV_TBL_SPACE_M,4,2  ## @HCLGE_CFG_UMV_TBL_SPACE_M
	.comm	_HCLGE_CFG_UMV_TBL_SPACE_S,4,2  ## @HCLGE_CFG_UMV_TBL_SPACE_S
	.comm	_HCLGE_DEFAULT_UMV_SPACE_PER_PF,8,3 ## @HCLGE_DEFAULT_UMV_SPACE_PER_PF
	.no_dead_strip	_hclge_parse_cfg
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function hclge_parse_cfg
_hclge_parse_cfg:                       ; @hclge_parse_cfg
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x1
	mov	x19, x0
	ldr	x22, [x1]
	ldr	x8, [x22]
	ldr	w0, [x8]
	bl	___le32_to_cpu
Lloh0:
	adrp	x8, _HCLGE_CFG_VMDQ_M@GOTPAGE
Lloh1:
	ldr	x8, [x8, _HCLGE_CFG_VMDQ_M@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _HCLGE_CFG_VMDQ_S@GOTPAGE
Lloh4:
	ldr	x8, [x8, _HCLGE_CFG_VMDQ_S@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #88]
	ldr	x8, [x22]
	ldr	w0, [x8]
	bl	___le32_to_cpu
Lloh6:
	adrp	x8, _HCLGE_CFG_TC_NUM_M@GOTPAGE
Lloh7:
	ldr	x8, [x8, _HCLGE_CFG_TC_NUM_M@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
Lloh9:
	adrp	x8, _HCLGE_CFG_TC_NUM_S@GOTPAGE
Lloh10:
	ldr	x8, [x8, _HCLGE_CFG_TC_NUM_S@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #80]
	ldr	x8, [x22]
	ldr	w0, [x8]
	bl	___le32_to_cpu
Lloh12:
	adrp	x8, _HCLGE_CFG_TQP_DESC_N_M@GOTPAGE
Lloh13:
	ldr	x8, [x8, _HCLGE_CFG_TQP_DESC_N_M@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
Lloh15:
	adrp	x8, _HCLGE_CFG_TQP_DESC_N_S@GOTPAGE
Lloh16:
	ldr	x8, [x8, _HCLGE_CFG_TQP_DESC_N_S@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #72]
	ldr	x8, [x22]
	ldr	w0, [x8, #4]
	bl	___le32_to_cpu
Lloh18:
	adrp	x8, _HCLGE_CFG_PHY_ADDR_M@GOTPAGE
Lloh19:
	ldr	x8, [x8, _HCLGE_CFG_PHY_ADDR_M@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _HCLGE_CFG_PHY_ADDR_S@GOTPAGE
Lloh22:
	ldr	x8, [x8, _HCLGE_CFG_PHY_ADDR_S@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #64]
	ldr	x8, [x22]
	ldr	w0, [x8, #4]
	bl	___le32_to_cpu
Lloh24:
	adrp	x8, _HCLGE_CFG_MEDIA_TP_M@GOTPAGE
Lloh25:
	ldr	x8, [x8, _HCLGE_CFG_MEDIA_TP_M@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
Lloh27:
	adrp	x8, _HCLGE_CFG_MEDIA_TP_S@GOTPAGE
Lloh28:
	ldr	x8, [x8, _HCLGE_CFG_MEDIA_TP_S@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #56]
	ldr	x8, [x22]
	ldr	w0, [x8, #4]
	bl	___le32_to_cpu
Lloh30:
	adrp	x8, _HCLGE_CFG_RX_BUF_LEN_M@GOTPAGE
Lloh31:
	ldr	x8, [x8, _HCLGE_CFG_RX_BUF_LEN_M@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _HCLGE_CFG_RX_BUF_LEN_S@GOTPAGE
Lloh34:
	ldr	x8, [x8, _HCLGE_CFG_RX_BUF_LEN_S@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #48]
	ldr	x8, [x22]
	ldr	w0, [x8, #8]
	bl	___le32_to_cpu
	mov	x21, x0
	ldr	x8, [x22]
	ldr	w0, [x8, #12]
	bl	___le32_to_cpu
Lloh36:
	adrp	x8, _HCLGE_CFG_MAC_ADDR_H_M@GOTPAGE
Lloh37:
	ldr	x8, [x8, _HCLGE_CFG_MAC_ADDR_H_M@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x8, _HCLGE_CFG_MAC_ADDR_H_S@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HCLGE_CFG_MAC_ADDR_H_S@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	ldr	x8, [x22]
	ldr	w0, [x8, #12]
	bl	___le32_to_cpu
Lloh42:
	adrp	x8, _HCLGE_CFG_DEFAULT_SPEED_M@GOTPAGE
Lloh43:
	ldr	x8, [x8, _HCLGE_CFG_DEFAULT_SPEED_M@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
Lloh45:
	adrp	x8, _HCLGE_CFG_DEFAULT_SPEED_S@GOTPAGE
Lloh46:
	ldr	x8, [x8, _HCLGE_CFG_DEFAULT_SPEED_S@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #40]
	ldr	x8, [x22]
	ldr	w0, [x8, #12]
	bl	___le32_to_cpu
Lloh48:
	adrp	x8, _HCLGE_CFG_RSS_SIZE_M@GOTPAGE
Lloh49:
	ldr	x8, [x8, _HCLGE_CFG_RSS_SIZE_M@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
Lloh51:
	adrp	x8, _HCLGE_CFG_RSS_SIZE_S@GOTPAGE
Lloh52:
	ldr	x8, [x8, _HCLGE_CFG_RSS_SIZE_S@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #32]
Lloh54:
	adrp	x8, _ETH_ALEN@GOTPAGE
Lloh55:
	ldr	x8, [x8, _ETH_ALEN@GOTPAGEOFF]
	ldr	w9, [x8]
	cbz	w9, LBB0_3
; %bb.1:
	mov	w9, #0
	mov	x10, #0
	ldr	x11, [x19]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	asr	w12, w21, w9
	and	w12, w12, #0xff
	str	w12, [x11, x10, lsl #2]
	add	x10, x10, #1
	ldr	w12, [x8]
	add	w9, w9, #8
	cmp	x10, x12
	b.lo	LBB0_2
LBB0_3:
	ldr	x20, [x20, #8]
	ldr	x8, [x20]
	ldr	w0, [x8]
	bl	___le32_to_cpu
	str	x0, [x19, #24]
	ldr	x8, [x20]
	ldr	w0, [x8, #4]
	bl	___le32_to_cpu
Lloh56:
	adrp	x8, _HCLGE_CFG_SPEED_ABILITY_M@GOTPAGE
Lloh57:
	ldr	x8, [x8, _HCLGE_CFG_SPEED_ABILITY_M@GOTPAGEOFF]
Lloh58:
	ldr	w1, [x8]
Lloh59:
	adrp	x8, _HCLGE_CFG_SPEED_ABILITY_S@GOTPAGE
Lloh60:
	ldr	x8, [x8, _HCLGE_CFG_SPEED_ABILITY_S@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #16]
	ldr	x8, [x20]
	ldr	w0, [x8, #4]
	bl	___le32_to_cpu
Lloh62:
	adrp	x8, _HCLGE_CFG_UMV_TBL_SPACE_M@GOTPAGE
Lloh63:
	ldr	x8, [x8, _HCLGE_CFG_UMV_TBL_SPACE_M@GOTPAGEOFF]
Lloh64:
	ldr	w1, [x8]
Lloh65:
	adrp	x8, _HCLGE_CFG_UMV_TBL_SPACE_S@GOTPAGE
Lloh66:
	ldr	x8, [x8, _HCLGE_CFG_UMV_TBL_SPACE_S@GOTPAGEOFF]
Lloh67:
	ldr	w2, [x8]
	bl	_hnae3_get_field
	str	x0, [x19, #8]
	cbnz	x0, LBB0_5
; %bb.4:
Lloh68:
	adrp	x8, _HCLGE_DEFAULT_UMV_SPACE_PER_PF@GOTPAGE
Lloh69:
	ldr	x8, [x8, _HCLGE_DEFAULT_UMV_SPACE_PER_PF@GOTPAGEOFF]
Lloh70:
	ldr	x8, [x8]
	str	x8, [x19, #8]
LBB0_5:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.cfi_endproc
                                        ; -- End function
	.comm	_HCLGE_CFG_VMDQ_M,4,2           ; @HCLGE_CFG_VMDQ_M
	.comm	_HCLGE_CFG_VMDQ_S,4,2           ; @HCLGE_CFG_VMDQ_S
	.comm	_HCLGE_CFG_TC_NUM_M,4,2         ; @HCLGE_CFG_TC_NUM_M
	.comm	_HCLGE_CFG_TC_NUM_S,4,2         ; @HCLGE_CFG_TC_NUM_S
	.comm	_HCLGE_CFG_TQP_DESC_N_M,4,2     ; @HCLGE_CFG_TQP_DESC_N_M
	.comm	_HCLGE_CFG_TQP_DESC_N_S,4,2     ; @HCLGE_CFG_TQP_DESC_N_S
	.comm	_HCLGE_CFG_PHY_ADDR_M,4,2       ; @HCLGE_CFG_PHY_ADDR_M
	.comm	_HCLGE_CFG_PHY_ADDR_S,4,2       ; @HCLGE_CFG_PHY_ADDR_S
	.comm	_HCLGE_CFG_MEDIA_TP_M,4,2       ; @HCLGE_CFG_MEDIA_TP_M
	.comm	_HCLGE_CFG_MEDIA_TP_S,4,2       ; @HCLGE_CFG_MEDIA_TP_S
	.comm	_HCLGE_CFG_RX_BUF_LEN_M,4,2     ; @HCLGE_CFG_RX_BUF_LEN_M
	.comm	_HCLGE_CFG_RX_BUF_LEN_S,4,2     ; @HCLGE_CFG_RX_BUF_LEN_S
	.comm	_HCLGE_CFG_MAC_ADDR_H_M,4,2     ; @HCLGE_CFG_MAC_ADDR_H_M
	.comm	_HCLGE_CFG_MAC_ADDR_H_S,4,2     ; @HCLGE_CFG_MAC_ADDR_H_S
	.comm	_HCLGE_CFG_DEFAULT_SPEED_M,4,2  ; @HCLGE_CFG_DEFAULT_SPEED_M
	.comm	_HCLGE_CFG_DEFAULT_SPEED_S,4,2  ; @HCLGE_CFG_DEFAULT_SPEED_S
	.comm	_HCLGE_CFG_RSS_SIZE_M,4,2       ; @HCLGE_CFG_RSS_SIZE_M
	.comm	_HCLGE_CFG_RSS_SIZE_S,4,2       ; @HCLGE_CFG_RSS_SIZE_S
	.comm	_ETH_ALEN,4,2                   ; @ETH_ALEN
	.comm	_HCLGE_CFG_SPEED_ABILITY_M,4,2  ; @HCLGE_CFG_SPEED_ABILITY_M
	.comm	_HCLGE_CFG_SPEED_ABILITY_S,4,2  ; @HCLGE_CFG_SPEED_ABILITY_S
	.comm	_HCLGE_CFG_UMV_TBL_SPACE_M,4,2  ; @HCLGE_CFG_UMV_TBL_SPACE_M
	.comm	_HCLGE_CFG_UMV_TBL_SPACE_S,4,2  ; @HCLGE_CFG_UMV_TBL_SPACE_S
	.comm	_HCLGE_DEFAULT_UMV_SPACE_PER_PF,8,3 ; @HCLGE_DEFAULT_UMV_SPACE_PER_PF
	.no_dead_strip	_hclge_parse_cfg
.subsections_via_symbols
