	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ar9160_hw_compute_pll_control
_ar9160_hw_compute_pll_control:         ## @ar9160_hw_compute_pll_control
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rsi, %rbx
	movq	_AR_RTC_9160_PLL_REFDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$5, %edi
	callq	_SM
	movl	%eax, %r14d
	testq	%rbx, %rbx
	je	LBB0_5
## %bb.1:
	movq	%rbx, %rdi
	callq	_IS_CHAN_HALF_RATE
	movl	$1, %edi
	testq	%rax, %rax
	jne	LBB0_3
## %bb.2:
	movq	%rbx, %rdi
	callq	_IS_CHAN_QUARTER_RATE
	movl	$2, %edi
	testq	%rax, %rax
	je	LBB0_4
LBB0_3:
	movq	_AR_RTC_9160_PLL_CLKSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	%eax, %r14d
LBB0_4:
	movq	%rbx, %rdi
	callq	_IS_CHAN_5GHZ
	movl	$80, %edi
	testq	%rax, %rax
	jne	LBB0_6
LBB0_5:
	movl	$88, %edi
LBB0_6:
	movq	_AR_RTC_9160_PLL_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	%r14d, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_RTC_9160_PLL_REFDIV,4,2     ## @AR_RTC_9160_PLL_REFDIV
	.comm	_AR_RTC_9160_PLL_CLKSEL,4,2     ## @AR_RTC_9160_PLL_CLKSEL
	.comm	_AR_RTC_9160_PLL_DIV,4,2        ## @AR_RTC_9160_PLL_DIV
	.no_dead_strip	_ar9160_hw_compute_pll_control
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ar9160_hw_compute_pll_control
_ar9160_hw_compute_pll_control:         ; @ar9160_hw_compute_pll_control
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x20, x1
Lloh0:
	adrp	x8, _AR_RTC_9160_PLL_REFDIV@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AR_RTC_9160_PLL_REFDIV@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w0, #5
	bl	_SM
	mov	x19, x0
	cbz	x20, LBB0_8
; %bb.1:
	mov	x0, x20
	bl	_IS_CHAN_HALF_RATE
	cbz	x0, LBB0_3
; %bb.2:
	mov	w0, #1
	b	LBB0_5
LBB0_3:
	mov	x0, x20
	bl	_IS_CHAN_QUARTER_RATE
	cbz	x0, LBB0_6
; %bb.4:
	mov	w0, #2
LBB0_5:
Lloh3:
	adrp	x8, _AR_RTC_9160_PLL_CLKSEL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AR_RTC_9160_PLL_CLKSEL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_SM
	orr	w19, w0, w19
LBB0_6:
	mov	x0, x20
	bl	_IS_CHAN_5GHZ
	cbz	x0, LBB0_8
; %bb.7:
	mov	w0, #80
	b	LBB0_9
LBB0_8:
	mov	w0, #88
LBB0_9:
Lloh6:
	adrp	x8, _AR_RTC_9160_PLL_DIV@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AR_RTC_9160_PLL_DIV@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	bl	_SM
	orr	w0, w0, w19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_RTC_9160_PLL_REFDIV,4,2     ; @AR_RTC_9160_PLL_REFDIV
	.comm	_AR_RTC_9160_PLL_CLKSEL,4,2     ; @AR_RTC_9160_PLL_CLKSEL
	.comm	_AR_RTC_9160_PLL_DIV,4,2        ; @AR_RTC_9160_PLL_DIV
	.no_dead_strip	_ar9160_hw_compute_pll_control
.subsections_via_symbols
