	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp22_rx_fifo_init
_mvpp22_rx_fifo_init:                   ## @mvpp22_rx_fifo_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	xorl	%edi, %edi
	callq	_MVPP2_RX_DATA_FIFO_SIZE_REG
	movq	_MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mvpp2_write
	xorl	%edi, %edi
	callq	_MVPP2_RX_ATTR_FIFO_SIZE_REG
	movq	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mvpp2_write
	movl	$1, %edi
	callq	_MVPP2_RX_DATA_FIFO_SIZE_REG
	movq	_MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mvpp2_write
	movl	$1, %edi
	callq	_MVPP2_RX_ATTR_FIFO_SIZE_REG
	movq	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mvpp2_write
	movq	_MVPP2_MAX_PORTS@GOTPCREL(%rip), %r15
	cmpl	$3, (%r15)
	jl	LBB0_3
## %bb.1:
	movl	$2, %ebx
	movq	_MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB@GOTPCREL(%rip), %r12
	movq	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	_MVPP2_RX_DATA_FIFO_SIZE_REG
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mvpp2_write
	movl	%ebx, %edi
	callq	_MVPP2_RX_ATTR_FIFO_SIZE_REG
	movl	(%r13), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mvpp2_write
	incl	%ebx
	cmpl	(%r15), %ebx
	jl	LBB0_2
LBB0_3:
	movq	_MVPP2_RX_MIN_PKT_SIZE_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_RX_FIFO_PORT_MIN_PKT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_write
	movq	_MVPP2_RX_FIFO_INIT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvpp2_write                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB,4,2 ## @MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB
	.comm	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB,4,2 ## @MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB
	.comm	_MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB,4,2 ## @MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB
	.comm	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB,4,2 ## @MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB
	.comm	_MVPP2_MAX_PORTS,4,2            ## @MVPP2_MAX_PORTS
	.comm	_MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB,4,2 ## @MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB
	.comm	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB,4,2 ## @MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB
	.comm	_MVPP2_RX_MIN_PKT_SIZE_REG,4,2  ## @MVPP2_RX_MIN_PKT_SIZE_REG
	.comm	_MVPP2_RX_FIFO_PORT_MIN_PKT,4,2 ## @MVPP2_RX_FIFO_PORT_MIN_PKT
	.comm	_MVPP2_RX_FIFO_INIT_REG,4,2     ## @MVPP2_RX_FIFO_INIT_REG
	.no_dead_strip	_mvpp22_rx_fifo_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp22_rx_fifo_init
_mvpp22_rx_fifo_init:                   ; @mvpp22_rx_fifo_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	mov	w0, #0
	bl	_MVPP2_RX_DATA_FIFO_SIZE_REG
	mov	x1, x0
Lloh0:
	adrp	x8, _MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_write
	mov	w0, #0
	bl	_MVPP2_RX_ATTR_FIFO_SIZE_REG
	mov	x1, x0
Lloh3:
	adrp	x8, _MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_write
	mov	w0, #1
	bl	_MVPP2_RX_DATA_FIFO_SIZE_REG
	mov	x1, x0
Lloh6:
	adrp	x8, _MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_write
	mov	w0, #1
	bl	_MVPP2_RX_ATTR_FIFO_SIZE_REG
	mov	x1, x0
Lloh9:
	adrp	x8, _MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_write
Lloh12:
	adrp	x21, _MVPP2_MAX_PORTS@GOTPAGE
Lloh13:
	ldr	x21, [x21, _MVPP2_MAX_PORTS@GOTPAGEOFF]
	ldr	w8, [x21]
	cmp	w8, #3
	b.lt	LBB0_3
; %bb.1:
	mov	w20, #2
Lloh14:
	adrp	x22, _MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB@GOTPAGE
Lloh15:
	ldr	x22, [x22, _MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB@GOTPAGEOFF]
Lloh16:
	adrp	x23, _MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB@GOTPAGE
Lloh17:
	ldr	x23, [x23, _MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	bl	_MVPP2_RX_DATA_FIFO_SIZE_REG
	mov	x1, x0
	ldr	w2, [x22]
	mov	x0, x19
	bl	_mvpp2_write
	mov	x0, x20
	bl	_MVPP2_RX_ATTR_FIFO_SIZE_REG
	mov	x1, x0
	ldr	w2, [x23]
	mov	x0, x19
	bl	_mvpp2_write
	add	w20, w20, #1
	ldr	w8, [x21]
	cmp	w20, w8
	b.lt	LBB0_2
LBB0_3:
Lloh18:
	adrp	x8, _MVPP2_RX_MIN_PKT_SIZE_REG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MVPP2_RX_MIN_PKT_SIZE_REG@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
Lloh21:
	adrp	x8, _MVPP2_RX_FIFO_PORT_MIN_PKT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MVPP2_RX_FIFO_PORT_MIN_PKT@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_write
Lloh24:
	adrp	x8, _MVPP2_RX_FIFO_INIT_REG@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MVPP2_RX_FIFO_INIT_REG@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_mvpp2_write
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB,4,2 ; @MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB
	.comm	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB,4,2 ; @MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB
	.comm	_MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB,4,2 ; @MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB
	.comm	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB,4,2 ; @MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB
	.comm	_MVPP2_MAX_PORTS,4,2            ; @MVPP2_MAX_PORTS
	.comm	_MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB,4,2 ; @MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB
	.comm	_MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB,4,2 ; @MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB
	.comm	_MVPP2_RX_MIN_PKT_SIZE_REG,4,2  ; @MVPP2_RX_MIN_PKT_SIZE_REG
	.comm	_MVPP2_RX_FIFO_PORT_MIN_PKT,4,2 ; @MVPP2_RX_FIFO_PORT_MIN_PKT
	.comm	_MVPP2_RX_FIFO_INIT_REG,4,2     ; @MVPP2_RX_FIFO_INIT_REG
	.no_dead_strip	_mvpp22_rx_fifo_init
.subsections_via_symbols
