	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function advk_sw_pci_bridge_init
_advk_sw_pci_bridge_init:               ## @advk_sw_pci_bridge_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	_PCIE_CORE_DEV_ID_REG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_advk_readl
	movzwl	%ax, %eax
	movl	%eax, 24(%rbx)
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_advk_readl
	sarl	$16, %eax
	movl	%eax, 28(%rbx)
	movq	_PCIE_CORE_DEV_REV_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_advk_readl
	movzbl	%al, %eax
	movl	%eax, 32(%rbx)
	movq	_PCI_IO_RANGE_TYPE_32@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 64(%rbx)
	movq	%rax, 56(%rbx)
	movq	_PCI_PREF_RANGE_TYPE_64@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 48(%rbx)
	movq	%rax, 40(%rbx)
	movq	_PCIE_CORE_INT_A_ASSERT_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 36(%rbx)
	movl	$1, (%rbx)
	movq	%rbx, 16(%rbx)
	movq	_advk_pci_bridge_emul_ops@GOTPCREL(%rip), %rax
	movq	%rax, 8(%rbx)
	movq	%rbx, %rdi
	xorl	%esi, %esi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_pci_bridge_emul_init           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_CORE_DEV_ID_REG,4,2       ## @PCIE_CORE_DEV_ID_REG
	.comm	_PCIE_CORE_DEV_REV_REG,4,2      ## @PCIE_CORE_DEV_REV_REG
	.comm	_PCI_IO_RANGE_TYPE_32,8,3       ## @PCI_IO_RANGE_TYPE_32
	.comm	_PCI_PREF_RANGE_TYPE_64,8,3     ## @PCI_PREF_RANGE_TYPE_64
	.comm	_PCIE_CORE_INT_A_ASSERT_ENABLE,4,2 ## @PCIE_CORE_INT_A_ASSERT_ENABLE
	.comm	_advk_pci_bridge_emul_ops,4,2   ## @advk_pci_bridge_emul_ops
	.no_dead_strip	_advk_sw_pci_bridge_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function advk_sw_pci_bridge_init
_advk_sw_pci_bridge_init:               ; @advk_sw_pci_bridge_init
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x20, _PCIE_CORE_DEV_ID_REG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCIE_CORE_DEV_ID_REG@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_advk_readl
	and	w8, w0, #0xffff
	str	w8, [x19, #24]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_advk_readl
	asr	w8, w0, #16
	str	w8, [x19, #28]
Lloh2:
	adrp	x8, _PCIE_CORE_DEV_REV_REG@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_CORE_DEV_REV_REG@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_advk_readl
Lloh5:
	adrp	x8, _PCI_IO_RANGE_TYPE_32@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCI_IO_RANGE_TYPE_32@GOTPAGEOFF]
Lloh7:
	ldr	x8, [x8]
Lloh8:
	adrp	x9, _PCI_PREF_RANGE_TYPE_64@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PCI_PREF_RANGE_TYPE_64@GOTPAGEOFF]
	stp	x8, x8, [x19, #56]
Lloh10:
	ldr	x8, [x9]
	stp	x8, x8, [x19, #40]
Lloh11:
	adrp	x8, _PCIE_CORE_INT_A_ASSERT_ENABLE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PCIE_CORE_INT_A_ASSERT_ENABLE@GOTPAGEOFF]
	and	w9, w0, #0xff
Lloh13:
	ldr	w8, [x8]
	stp	w9, w8, [x19, #32]
	mov	w8, #1
	str	w8, [x19]
Lloh14:
	adrp	x8, _advk_pci_bridge_emul_ops@GOTPAGE
Lloh15:
	ldr	x8, [x8, _advk_pci_bridge_emul_ops@GOTPAGEOFF]
	stp	x8, x19, [x19, #8]
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_pci_bridge_emul_init
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_CORE_DEV_ID_REG,4,2       ; @PCIE_CORE_DEV_ID_REG
	.comm	_PCIE_CORE_DEV_REV_REG,4,2      ; @PCIE_CORE_DEV_REV_REG
	.comm	_PCI_IO_RANGE_TYPE_32,8,3       ; @PCI_IO_RANGE_TYPE_32
	.comm	_PCI_PREF_RANGE_TYPE_64,8,3     ; @PCI_PREF_RANGE_TYPE_64
	.comm	_PCIE_CORE_INT_A_ASSERT_ENABLE,4,2 ; @PCIE_CORE_INT_A_ASSERT_ENABLE
	.comm	_advk_pci_bridge_emul_ops,4,2   ; @advk_pci_bridge_emul_ops
	.no_dead_strip	_advk_sw_pci_bridge_init
.subsections_via_symbols
