	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dra7xx_pcie_enable_phy
_dra7xx_pcie_enable_phy:                ## @dra7xx_pcie_enable_phy
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	(%rdi), %r13d
	xorl	%r12d, %r12d
	testl	%r13d, %r13d
	jle	LBB0_11
## %bb.1:
	movq	%rdi, %r15
	negq	%r13
	movl	$1, %ebx
	movq	_PHY_MODE_PCIE@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movl	-4(%rax,%rbx,4), %edi
	movl	(%r14), %esi
	callq	_phy_set_mode
	testl	%eax, %eax
	js	LBB0_8
## %bb.3:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	8(%r15), %rax
	movl	-4(%rax,%rbx,4), %edi
	callq	_phy_init
	testl	%eax, %eax
	js	LBB0_8
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	8(%r15), %rax
	movl	-4(%rax,%rbx,4), %edi
	callq	_phy_power_on
	testl	%eax, %eax
	js	LBB0_9
## %bb.5:                               ##   in Loop: Header=BB0_2 Depth=1
	leaq	(%rbx,%r13), %rax
	incq	%rax
	incq	%rbx
	cmpq	$1, %rax
	jne	LBB0_2
## %bb.6:
	xorl	%r12d, %r12d
	jmp	LBB0_11
LBB0_8:
	movl	%eax, %r12d
	cmpl	$1, %ebx
	je	LBB0_11
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movq	8(%r15), %rax
	movl	-8(%rax,%rbx,4), %edi
	callq	_phy_power_off
	movq	8(%r15), %rax
	movl	-8(%rax,%rbx,4), %edi
	callq	_phy_exit
	decq	%rbx
	cmpq	$1, %rbx
	ja	LBB0_10
LBB0_11:
	movl	%r12d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_9:
	movl	%eax, %r12d
	movq	8(%r15), %rax
	movl	-4(%rax,%rbx,4), %edi
	callq	_phy_exit
	cmpl	$1, %ebx
	je	LBB0_11
	jmp	LBB0_10
	.cfi_endproc
                                        ## -- End function
	.comm	_PHY_MODE_PCIE,4,2              ## @PHY_MODE_PCIE
	.no_dead_strip	_dra7xx_pcie_enable_phy
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dra7xx_pcie_enable_phy
_dra7xx_pcie_enable_phy:                ; @dra7xx_pcie_enable_phy
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	w22, [x0]
	cmp	w22, #1
	b.lt	LBB0_6
; %bb.1:
	mov	x19, x0
	mov	x21, #0
Lloh0:
	adrp	x23, _PHY_MODE_PCIE@GOTPAGE
Lloh1:
	ldr	x23, [x23, _PHY_MODE_PCIE@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x21, lsl #2]
	ldr	w1, [x23]
	bl	_phy_set_mode
	tbnz	w0, #31, LBB0_7
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x21, lsl #2]
	bl	_phy_init
	tbnz	w0, #31, LBB0_7
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x21, lsl #2]
	bl	_phy_power_on
	tbnz	w0, #31, LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	add	x21, x21, #1
	cmp	x22, x21
	b.ne	LBB0_2
LBB0_6:
	mov	w20, #0
	b	LBB0_11
LBB0_7:
	mov	x20, x0
	cbnz	w21, LBB0_9
	b	LBB0_11
LBB0_8:
	mov	x20, x0
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x21, lsl #2]
	bl	_phy_exit
	cbz	w21, LBB0_11
LBB0_9:
	sub	x21, x21, #1
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19, #8]
	lsl	x22, x21, #2
	ldr	w0, [x8, x22]
	bl	_phy_power_off
	ldr	x8, [x19, #8]
	ldr	w0, [x8, x22]
	bl	_phy_exit
	add	x8, x21, #1
	sub	x21, x21, #1
	cmp	x8, #1
	b.hi	LBB0_10
LBB0_11:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_PHY_MODE_PCIE,4,2              ; @PHY_MODE_PCIE
	.no_dead_strip	_dra7xx_pcie_enable_phy
.subsections_via_symbols
