	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function imx6_pcie_init_phy
_imx6_pcie_init_phy:                    ## @imx6_pcie_init_phy
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	24(%rdi), %rax
	movl	(%rax), %eax
	cmpl	$130, %eax
	je	LBB0_5
## %bb.1:
	cmpl	$129, %eax
	je	LBB0_4
## %bb.2:
	cmpl	$128, %eax
	jne	LBB0_6
## %bb.3:
	movl	20(%rbx), %r14d
	movq	%rbx, %rdi
	callq	_imx6_pcie_grp_offset
	movq	_IMX8MQ_GPR_PCIE_REF_USE_PAD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%r14d, %edi
	movl	%eax, %esi
	movl	%ecx, %edx
	jmp	LBB0_7
LBB0_5:
	movl	20(%rbx), %edi
	movq	_IOMUXC_GPR12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX6SX_GPR12_PCIE_RX_EQ_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_IMX6SX_GPR12_PCIE_RX_EQ_2@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	callq	_regmap_update_bits
LBB0_6:
	movl	20(%rbx), %edi
	movq	_IOMUXC_GPR12@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_IMX6Q_GPR12_PCIE_CTL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	20(%rbx), %edi
	movl	(%r14), %esi
	movq	_IMX6Q_GPR12_LOS_LEVEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$144, %ecx
	callq	_regmap_update_bits
	movl	(%rbx), %ecx
	movl	20(%rbx), %edi
	movq	_IOMUXC_GPR8@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_IMX6Q_GPR8_TX_DEEMPH_GEN1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_update_bits
	movl	4(%rbx), %ecx
	movl	20(%rbx), %edi
	movl	(%r14), %esi
	movq	_IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	shll	$6, %ecx
	callq	_regmap_update_bits
	movl	8(%rbx), %ecx
	movl	20(%rbx), %edi
	movl	(%r14), %esi
	movq	_IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	shll	$12, %ecx
	callq	_regmap_update_bits
	movl	12(%rbx), %ecx
	movl	20(%rbx), %edi
	movl	(%r14), %esi
	movq	_IMX6Q_GPR8_TX_SWING_FULL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	shll	$18, %ecx
	callq	_regmap_update_bits
	movl	16(%rbx), %ecx
	movl	20(%rbx), %edi
	movl	(%r14), %esi
	movq	_IMX6Q_GPR8_TX_SWING_LOW@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	shll	$25, %ecx
	jmp	LBB0_7
LBB0_4:
	movl	20(%rbx), %edi
	movq	_IOMUXC_GPR12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX7D_GPR12_PCIE_PHY_REFCLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
LBB0_7:
	callq	_regmap_update_bits
	movq	%rbx, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_imx6_pcie_configure_type       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_IMX8MQ_GPR_PCIE_REF_USE_PAD,4,2 ## @IMX8MQ_GPR_PCIE_REF_USE_PAD
	.comm	_IOMUXC_GPR12,4,2               ## @IOMUXC_GPR12
	.comm	_IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,4,2 ## @IMX7D_GPR12_PCIE_PHY_REFCLK_SEL
	.comm	_IMX6SX_GPR12_PCIE_RX_EQ_MASK,4,2 ## @IMX6SX_GPR12_PCIE_RX_EQ_MASK
	.comm	_IMX6SX_GPR12_PCIE_RX_EQ_2,4,2  ## @IMX6SX_GPR12_PCIE_RX_EQ_2
	.comm	_IMX6Q_GPR12_PCIE_CTL_2,4,2     ## @IMX6Q_GPR12_PCIE_CTL_2
	.comm	_IMX6Q_GPR12_LOS_LEVEL,4,2      ## @IMX6Q_GPR12_LOS_LEVEL
	.comm	_IOMUXC_GPR8,4,2                ## @IOMUXC_GPR8
	.comm	_IMX6Q_GPR8_TX_DEEMPH_GEN1,4,2  ## @IMX6Q_GPR8_TX_DEEMPH_GEN1
	.comm	_IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,4,2 ## @IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB
	.comm	_IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,4,2 ## @IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB
	.comm	_IMX6Q_GPR8_TX_SWING_FULL,4,2   ## @IMX6Q_GPR8_TX_SWING_FULL
	.comm	_IMX6Q_GPR8_TX_SWING_LOW,4,2    ## @IMX6Q_GPR8_TX_SWING_LOW
	.no_dead_strip	_imx6_pcie_init_phy
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function imx6_pcie_init_phy
_imx6_pcie_init_phy:                    ; @imx6_pcie_init_phy
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x8, [x0, #24]
	ldr	w8, [x8]
	cmp	w8, #130
	b.eq	LBB0_4
; %bb.1:
	cmp	w8, #129
	b.eq	LBB0_6
; %bb.2:
	cmp	w8, #128
	b.ne	LBB0_5
; %bb.3:
	ldr	w20, [x19, #20]
	mov	x0, x19
	bl	_imx6_pcie_grp_offset
	mov	x1, x0
Lloh0:
	adrp	x8, _IMX8MQ_GPR_PCIE_REF_USE_PAD@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IMX8MQ_GPR_PCIE_REF_USE_PAD@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x20
	mov	x3, x2
	b	LBB0_7
LBB0_4:
	ldr	w0, [x19, #20]
Lloh3:
	adrp	x8, _IOMUXC_GPR12@GOTPAGE
Lloh4:
	ldr	x8, [x8, _IOMUXC_GPR12@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
Lloh6:
	adrp	x8, _IMX6SX_GPR12_PCIE_RX_EQ_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _IMX6SX_GPR12_PCIE_RX_EQ_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
Lloh9:
	adrp	x8, _IMX6SX_GPR12_PCIE_RX_EQ_2@GOTPAGE
Lloh10:
	ldr	x8, [x8, _IMX6SX_GPR12_PCIE_RX_EQ_2@GOTPAGEOFF]
Lloh11:
	ldr	w3, [x8]
	bl	_regmap_update_bits
LBB0_5:
	ldr	w0, [x19, #20]
Lloh12:
	adrp	x20, _IOMUXC_GPR12@GOTPAGE
Lloh13:
	ldr	x20, [x20, _IOMUXC_GPR12@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh14:
	adrp	x8, _IMX6Q_GPR12_PCIE_CTL_2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _IMX6Q_GPR12_PCIE_CTL_2@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19, #20]
	ldr	w1, [x20]
Lloh17:
	adrp	x8, _IMX6Q_GPR12_LOS_LEVEL@GOTPAGE
Lloh18:
	ldr	x8, [x8, _IMX6Q_GPR12_LOS_LEVEL@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	w3, #144
	bl	_regmap_update_bits
Lloh20:
	adrp	x20, _IOMUXC_GPR8@GOTPAGE
Lloh21:
	ldr	x20, [x20, _IOMUXC_GPR8@GOTPAGEOFF]
	ldr	w0, [x19, #20]
	ldr	w1, [x20]
Lloh22:
	adrp	x8, _IMX6Q_GPR8_TX_DEEMPH_GEN1@GOTPAGE
Lloh23:
	ldr	x8, [x8, _IMX6Q_GPR8_TX_DEEMPH_GEN1@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	ldr	w3, [x19]
	bl	_regmap_update_bits
	ldr	w0, [x19, #20]
	ldr	w1, [x20]
Lloh25:
	adrp	x8, _IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB@GOTPAGE
Lloh26:
	ldr	x8, [x8, _IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	ldr	w8, [x19, #4]
	lsl	w3, w8, #6
	bl	_regmap_update_bits
	ldr	w0, [x19, #20]
	ldr	w1, [x20]
Lloh28:
	adrp	x8, _IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB@GOTPAGE
Lloh29:
	ldr	x8, [x8, _IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	ldr	w8, [x19, #8]
	lsl	w3, w8, #12
	bl	_regmap_update_bits
	ldr	w0, [x19, #20]
	ldr	w1, [x20]
Lloh31:
	adrp	x8, _IMX6Q_GPR8_TX_SWING_FULL@GOTPAGE
Lloh32:
	ldr	x8, [x8, _IMX6Q_GPR8_TX_SWING_FULL@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	ldr	w8, [x19, #12]
	lsl	w3, w8, #18
	bl	_regmap_update_bits
	ldr	w1, [x20]
Lloh34:
	adrp	x8, _IMX6Q_GPR8_TX_SWING_LOW@GOTPAGE
Lloh35:
	ldr	x8, [x8, _IMX6Q_GPR8_TX_SWING_LOW@GOTPAGEOFF]
Lloh36:
	ldr	w2, [x8]
	ldp	w8, w0, [x19, #16]
	lsl	w3, w8, #25
	b	LBB0_7
LBB0_6:
	ldr	w0, [x19, #20]
Lloh37:
	adrp	x8, _IOMUXC_GPR12@GOTPAGE
Lloh38:
	ldr	x8, [x8, _IOMUXC_GPR12@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
Lloh40:
	adrp	x8, _IMX7D_GPR12_PCIE_PHY_REFCLK_SEL@GOTPAGE
Lloh41:
	ldr	x8, [x8, _IMX7D_GPR12_PCIE_PHY_REFCLK_SEL@GOTPAGEOFF]
Lloh42:
	ldr	w2, [x8]
	mov	w3, #0
LBB0_7:
	bl	_regmap_update_bits
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_imx6_pcie_configure_type
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.cfi_endproc
                                        ; -- End function
	.comm	_IMX8MQ_GPR_PCIE_REF_USE_PAD,4,2 ; @IMX8MQ_GPR_PCIE_REF_USE_PAD
	.comm	_IOMUXC_GPR12,4,2               ; @IOMUXC_GPR12
	.comm	_IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,4,2 ; @IMX7D_GPR12_PCIE_PHY_REFCLK_SEL
	.comm	_IMX6SX_GPR12_PCIE_RX_EQ_MASK,4,2 ; @IMX6SX_GPR12_PCIE_RX_EQ_MASK
	.comm	_IMX6SX_GPR12_PCIE_RX_EQ_2,4,2  ; @IMX6SX_GPR12_PCIE_RX_EQ_2
	.comm	_IMX6Q_GPR12_PCIE_CTL_2,4,2     ; @IMX6Q_GPR12_PCIE_CTL_2
	.comm	_IMX6Q_GPR12_LOS_LEVEL,4,2      ; @IMX6Q_GPR12_LOS_LEVEL
	.comm	_IOMUXC_GPR8,4,2                ; @IOMUXC_GPR8
	.comm	_IMX6Q_GPR8_TX_DEEMPH_GEN1,4,2  ; @IMX6Q_GPR8_TX_DEEMPH_GEN1
	.comm	_IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,4,2 ; @IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB
	.comm	_IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,4,2 ; @IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB
	.comm	_IMX6Q_GPR8_TX_SWING_FULL,4,2   ; @IMX6Q_GPR8_TX_SWING_FULL
	.comm	_IMX6Q_GPR8_TX_SWING_LOW,4,2    ; @IMX6Q_GPR8_TX_SWING_LOW
	.no_dead_strip	_imx6_pcie_init_phy
.subsections_via_symbols
