	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function socfpga_gen10_set_phy_mode
_socfpga_gen10_set_phy_mode:            ## @socfpga_gen10_set_phy_mode
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	movq	40(%rdi), %r15
	callq	_socfpga_get_plat_phymode
	movl	%eax, %r14d
	movl	(%r13), %r12d
	movl	4(%r13), %ebx
	leaq	-52(%rbp), %rsi
	movl	%eax, %edi
	callq	_socfpga_set_phy_mode_common
	testq	%rax, %rax
	je	LBB0_1
LBB0_12:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
LBB0_13:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_1:
	cmpq	$0, 32(%r13)
	je	LBB0_3
## %bb.2:
	movq	_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -52(%rbp)
LBB0_3:
	movl	20(%r13), %edi
	callq	_reset_control_assert
	movl	16(%r13), %edi
	callq	_reset_control_assert
	leaq	-44(%rbp), %rdx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_regmap_read
	movq	_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	orl	-52(%rbp), %edx
	cmpq	$0, 24(%r13)
	movq	_PHY_INTERFACE_MODE_SGMII@GOTPCREL(%rip), %rsi
	movq	_SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jne	LBB0_7
## %bb.4:
	movq	_PHY_INTERFACE_MODE_MII@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %r14d
	je	LBB0_7
## %bb.5:
	movq	_PHY_INTERFACE_MODE_GMII@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %r14d
	je	LBB0_7
## %bb.6:
	cmpl	(%rsi), %r14d
	je	LBB0_7
## %bb.8:
	notl	%eax
	andl	%eax, %edx
	movl	%edx, -44(%rbp)
	jmp	LBB0_9
LBB0_7:
	orl	%edx, %eax
	movl	%eax, -44(%rbp)
	movq	_SYSMGR_FPGAINTF_EMAC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%r15, %rdi
	callq	_regmap_read
	movq	_SYSMGR_FPGAINTF_EMAC_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %ecx
	shll	%cl, %edx
	orl	-48(%rbp), %edx
	movl	%edx, -48(%rbp)
	movq	_SYSMGR_FPGAINTF_EMAC_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_regmap_write
	movl	-44(%rbp), %edx
LBB0_9:
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_regmap_write
	movl	20(%r13), %edi
	callq	_reset_control_deassert
	movl	16(%r13), %edi
	callq	_reset_control_deassert
	xorl	%ebx, %ebx
	movq	_PHY_INTERFACE_MODE_SGMII@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r14d
	jne	LBB0_13
## %bb.10:
	leaq	12(%r13), %rsi
	movl	12(%r13), %edi
	callq	_tse_pcs_init
	testq	%rax, %rax
	je	LBB0_13
## %bb.11:
	movl	8(%r13), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII,4,2 ## @SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII
	.comm	_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,4,2 ## @SYSMGR_EMACGRP_CTRL_PHYSEL_MASK
	.comm	_PHY_INTERFACE_MODE_MII,4,2     ## @PHY_INTERFACE_MODE_MII
	.comm	_PHY_INTERFACE_MODE_GMII,4,2    ## @PHY_INTERFACE_MODE_GMII
	.comm	_PHY_INTERFACE_MODE_SGMII,4,2   ## @PHY_INTERFACE_MODE_SGMII
	.comm	_SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK,4,2 ## @SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK
	.comm	_SYSMGR_FPGAINTF_EMAC_REG,4,2   ## @SYSMGR_FPGAINTF_EMAC_REG
	.comm	_SYSMGR_FPGAINTF_EMAC_BIT,4,2   ## @SYSMGR_FPGAINTF_EMAC_BIT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unable to initialize TSE PCS"

	.no_dead_strip	_socfpga_gen10_set_phy_mode
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function socfpga_gen10_set_phy_mode
_socfpga_gen10_set_phy_mode:            ; @socfpga_gen10_set_phy_mode
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x21, [x0, #40]
	bl	_socfpga_get_plat_phymode
	mov	x20, x0
	ldp	w22, w23, [x19]
	add	x1, sp, #8
	bl	_socfpga_set_phy_mode_common
	cbz	x0, LBB0_3
LBB0_1:
Lloh0:
	adrp	x8, _EINVAL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_2:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_3:
	ldr	x8, [x19, #32]
	cbz	x8, LBB0_5
; %bb.4:
Lloh3:
	adrp	x8, _SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [sp, #8]
LBB0_5:
	ldr	w0, [x19, #20]
	bl	_reset_control_assert
	ldr	w0, [x19, #16]
	bl	_reset_control_assert
	add	x2, sp, #12
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_read
Lloh6:
	adrp	x8, _SYSMGR_EMACGRP_CTRL_PHYSEL_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SYSMGR_EMACGRP_CTRL_PHYSEL_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	ldr	w9, [sp, #8]
	orr	w8, w9, w8
	ldr	x10, [x19, #24]
Lloh9:
	adrp	x24, _PHY_INTERFACE_MODE_SGMII@GOTPAGE
Lloh10:
	ldr	x24, [x24, _PHY_INTERFACE_MODE_SGMII@GOTPAGEOFF]
Lloh11:
	adrp	x9, _SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK@GOTPAGE
Lloh12:
	ldr	x9, [x9, _SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	cbnz	x10, LBB0_8
; %bb.6:
Lloh14:
	adrp	x10, _PHY_INTERFACE_MODE_MII@GOTPAGE
Lloh15:
	ldr	x10, [x10, _PHY_INTERFACE_MODE_MII@GOTPAGEOFF]
Lloh16:
	adrp	x11, _PHY_INTERFACE_MODE_GMII@GOTPAGE
Lloh17:
	ldr	x11, [x11, _PHY_INTERFACE_MODE_GMII@GOTPAGEOFF]
Lloh18:
	ldr	w10, [x10]
Lloh19:
	ldr	w11, [x11]
	ldr	w12, [x24]
	cmp	w20, w10
	ccmp	w20, w11, #4, ne
	ccmp	w20, w12, #4, ne
	b.eq	LBB0_8
; %bb.7:
	bic	w2, w8, w9
	str	w2, [sp, #12]
	b	LBB0_9
LBB0_8:
	orr	w8, w9, w8
	str	w8, [sp, #12]
Lloh20:
	adrp	x25, _SYSMGR_FPGAINTF_EMAC_REG@GOTPAGE
Lloh21:
	ldr	x25, [x25, _SYSMGR_FPGAINTF_EMAC_REG@GOTPAGEOFF]
	ldr	w1, [x25]
	add	x2, sp, #4
	mov	x0, x21
	bl	_regmap_read
Lloh22:
	adrp	x8, _SYSMGR_FPGAINTF_EMAC_BIT@GOTPAGE
Lloh23:
	ldr	x8, [x8, _SYSMGR_FPGAINTF_EMAC_BIT@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	lsl	w8, w8, w23
	ldr	w9, [sp, #4]
	orr	w2, w9, w8
	str	w2, [sp, #4]
	ldr	w1, [x25]
	mov	x0, x21
	bl	_regmap_write
	ldr	w2, [sp, #12]
LBB0_9:
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w0, [x19, #20]
	bl	_reset_control_deassert
	ldr	w0, [x19, #16]
	bl	_reset_control_deassert
	ldr	w8, [x24]
	cmp	w20, w8
	b.ne	LBB0_12
; %bb.10:
	mov	x1, x19
	ldr	w0, [x1, #12]!
	bl	_tse_pcs_init
	cbz	x0, LBB0_2
; %bb.11:
	ldr	w0, [x19, #8]
Lloh25:
	adrp	x1, l_.str@PAGE
Lloh26:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_1
LBB0_12:
	mov	w0, #0
	b	LBB0_2
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh18
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpAdd	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII,4,2 ; @SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII
	.comm	_SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,4,2 ; @SYSMGR_EMACGRP_CTRL_PHYSEL_MASK
	.comm	_PHY_INTERFACE_MODE_MII,4,2     ; @PHY_INTERFACE_MODE_MII
	.comm	_PHY_INTERFACE_MODE_GMII,4,2    ; @PHY_INTERFACE_MODE_GMII
	.comm	_PHY_INTERFACE_MODE_SGMII,4,2   ; @PHY_INTERFACE_MODE_SGMII
	.comm	_SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK,4,2 ; @SYSMGR_GEN10_EMACGRP_CTRL_PTP_REF_CLK_MASK
	.comm	_SYSMGR_FPGAINTF_EMAC_REG,4,2   ; @SYSMGR_FPGAINTF_EMAC_REG
	.comm	_SYSMGR_FPGAINTF_EMAC_BIT,4,2   ; @SYSMGR_FPGAINTF_EMAC_BIT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unable to initialize TSE PCS"

	.no_dead_strip	_socfpga_gen10_set_phy_mode
.subsections_via_symbols
