	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iwl_pcie_nic_init
_iwl_pcie_nic_init:                     ## @iwl_pcie_nic_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_IWL_TRANS_GET_PCIE_TRANS
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_spin_lock
	movq	%r15, %rdi
	callq	_iwl_pcie_apm_init
	movl	%eax, %r14d
	movq	%rbx, %rdi
	callq	_spin_unlock
	testl	%r14d, %r14d
	jne	LBB0_5
## %bb.1:
	xorl	%r14d, %r14d
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_iwl_pcie_set_pwr
	movl	8(%r15), %edi
	callq	_iwl_op_mode_nic_config
	movq	%r15, %rdi
	callq	_iwl_pcie_rx_init
	movq	%r15, %rdi
	callq	_iwl_pcie_tx_init
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_ENOMEM@GOTPCREL(%rip), %rax
	subl	(%rax), %r14d
	jmp	LBB0_5
LBB0_3:
	movq	(%r15), %rax
	movq	(%rax), %rax
	cmpq	$0, (%rax)
	je	LBB0_5
## %bb.4:
	movq	_CSR_MAC_SHADOW_REG_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-2146435073, %edx              ## imm = 0x800FFFFF
	callq	_iwl_set_bit
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	callq	_IWL_DEBUG_INFO
LBB0_5:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ENOMEM,4,2                     ## @ENOMEM
	.comm	_CSR_MAC_SHADOW_REG_CTRL,4,2    ## @CSR_MAC_SHADOW_REG_CTRL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Enabling shadow registers in device\n"

	.no_dead_strip	_iwl_pcie_nic_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iwl_pcie_nic_init
_iwl_pcie_nic_init:                     ; @iwl_pcie_nic_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_IWL_TRANS_GET_PCIE_TRANS
	mov	x21, x0
	bl	_spin_lock
	mov	x0, x19
	bl	_iwl_pcie_apm_init
	mov	x20, x0
	mov	x0, x21
	bl	_spin_unlock
	cbnz	w20, LBB0_6
; %bb.1:
	mov	x0, x19
	mov	w1, #0
	bl	_iwl_pcie_set_pwr
	ldr	w0, [x19, #8]
	bl	_iwl_op_mode_nic_config
	mov	x0, x19
	bl	_iwl_pcie_rx_init
	mov	x0, x19
	bl	_iwl_pcie_tx_init
	cbz	x0, LBB0_3
; %bb.2:
Lloh0:
	adrp	x8, _ENOMEM@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ENOMEM@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_6
LBB0_3:
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	x8, [x8]
	cbz	x8, LBB0_5
; %bb.4:
Lloh3:
	adrp	x8, _CSR_MAC_SHADOW_REG_CTRL@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CSR_MAC_SHADOW_REG_CTRL@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-2146435073
	bl	_iwl_set_bit
Lloh6:
	adrp	x1, l_.str@PAGE
Lloh7:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_INFO
LBB0_5:
	mov	w20, #0
LBB0_6:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_ENOMEM,4,2                     ; @ENOMEM
	.comm	_CSR_MAC_SHADOW_REG_CTRL,4,2    ; @CSR_MAC_SHADOW_REG_CTRL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Enabling shadow registers in device\n"

	.no_dead_strip	_iwl_pcie_nic_init
.subsections_via_symbols
