	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rtl8xxxu_gen2_config_channel   ## -- Begin function rtl8xxxu_gen2_config_channel
	.p2align	4, 0x90
_rtl8xxxu_gen2_config_channel:          ## @rtl8xxxu_gen2_config_channel
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	24(%rdi), %r12
	movq	_REG_WMAC_TRXPTCL_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read16
	movq	_WMAC_TRXPTCL_CTL_BW_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movq	_REG_RESPONSE_RATE_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movq	8(%r14), %rax
	movl	(%rax), %r13d
	movq	%r14, -72(%rbp)                 ## 8-byte Spill
	movl	(%r14), %ecx
	movl	$1, %esi
	addl	$-128, %ecx
	cmpl	$3, %ecx
	ja	LBB0_3
## %bb.1:
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_2:
	movl	$1, %eax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movq	_WMAC_TRXPTCL_CTL_BW_80@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	jmp	LBB0_4
LBB0_3:
	movl	$1, %eax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
LBB0_4:
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	jmp	LBB0_9
LBB0_5:
	movl	$1, %ecx
	movq	%rcx, -56(%rbp)                 ## 8-byte Spill
	movq	_WMAC_TRXPTCL_CTL_BW_40@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	movl	16(%rcx), %r14d
	movl	%r14d, -60(%rbp)                ## 4-byte Spill
	movl	4(%rax), %eax
	movl	%eax, -64(%rbp)                 ## 4-byte Spill
	movq	_REG_FPGA0_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movq	_FPGA_RF_MODE@GOTPCREL(%rip), %r15
	orl	(%r15), %eax
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA1_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	orl	(%r15), %eax
	movl	(%rbx), %esi
	movq	%r12, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_CCK0_SYSTEM@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movq	_CCK0_SIDEBAND@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%eax, %edx
	movl	(%rbx), %esi
	movl	-64(%rbp), %r15d                ## 4-byte Reload
	cmpl	%r15d, %r14d
	cmovgl	%ecx, %edx
	movq	_OFDM_LSTF_PRIME_CH_HIGH@GOTPCREL(%rip), %rbx
	cmovgq	_OFDM_LSTF_PRIME_CH_LOW@GOTPCREL(%rip), %rbx
	movq	%r12, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_OFDM1_LSTF@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movq	_OFDM_LSTF_PRIME_CH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	orl	(%rbx), %edx
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_POWER_SAVE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	xorl	%ecx, %ecx
	cmpl	%r15d, -60(%rbp)                ## 4-byte Folded Reload
	setg	%cl
	leal	-2(%r13,%rcx,4), %r13d
	movq	_FPGA0_PS_LOWER_CHANNEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_FPGA0_PS_UPPER_CHANNEL@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%ecx, %esi
	cmovgl	%edx, %esi
	orl	%ecx, %edx
	notl	%edx
	andl	%eax, %edx
	orl	%esi, %edx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	jmp	LBB0_8
LBB0_6:
	xorl	%esi, %esi
LBB0_7:
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	_WMAC_TRXPTCL_CTL_BW_20@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%ebx, -44(%rbp)                 ## 4-byte Spill
	movq	_REG_FPGA0_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movq	_FPGA_RF_MODE@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA1_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movl	(%r14), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_OFDM0_TX_PSDO_NOISE_WEIGHT@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r12, %rdi
	callq	_rtl8xxxu_read32
	movl	%eax, %r15d
	movl	$30, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$31, %edi
	callq	_BIT
	orl	%eax, %ebx
	notl	%ebx
	andl	%r15d, %ebx
	movl	(%r14), %esi
	movq	%r12, %rdi
	movl	%ebx, %edx
LBB0_8:
	callq	_rtl8xxxu_write32
LBB0_9:
	movq	_RF_A@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	cmpl	(%r12), %ebx
	jge	LBB0_12
## %bb.10:
	movq	_RF6052_REG_MODE_AG@GOTPCREL(%rip), %r14
	movq	_MODE_AG_CHANNEL_MASK@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_read_rfreg
	movl	(%r15), %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%r13d, %ecx
	movl	(%r14), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_write_rfreg
	incl	%ebx
	cmpl	(%r12), %ebx
	jl	LBB0_11
LBB0_12:
	movq	_REG_WMAC_TRXPTCL_CTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	callq	_rtl8xxxu_write16
	movq	_REG_DATA_SUBCHANNEL@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r12, %rdi
	xorl	%edx, %edx
	callq	_rtl8xxxu_write8
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	leal	10(,%rax,4), %ebx
	movq	_REG_SIFS_CCK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	incq	%rsi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write8
	movq	_REG_SIFS_OFDM@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	incq	%rsi
	movq	%r12, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write8
	movq	_REG_R2T_SIFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$2056, %edx                     ## imm = 0x808
	callq	_rtl8xxxu_write16
	movq	_REG_T2T_SIFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	movl	$2570, %edx                     ## imm = 0xA0A
	callq	_rtl8xxxu_write16
	movq	_RF_A@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	cmpl	(%r12), %ebx
	jge	LBB0_19
## %bb.13:
	movq	_RF6052_REG_MODE_AG@GOTPCREL(%rip), %r15
	movq	_MODE_AG_BW_MASK@GOTPCREL(%rip), %r13
	movq	_MODE_AG_BW_20MHZ_8723B@GOTPCREL(%rip), %r14
	jmp	LBB0_15
	.p2align	4, 0x90
LBB0_14:                                ##   in Loop: Header=BB0_15 Depth=1
	orl	(%rcx), %eax
	movl	(%r15), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %ecx
	callq	_rtl8xxxu_write_rfreg
	incl	%ebx
	cmpl	(%r12), %ebx
	jge	LBB0_19
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_read_rfreg
	movq	-72(%rbp), %rcx                 ## 8-byte Reload
	movl	(%rcx), %edx
	movq	%r14, %rcx
	cmpl	$129, %edx
	jne	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=1
	movq	_MODE_AG_BW_40MHZ_8723B@GOTPCREL(%rip), %rcx
LBB0_17:                                ##   in Loop: Header=BB0_15 Depth=1
	movl	(%r13), %esi
	notl	%esi
	andl	%esi, %eax
	cmpl	$128, %edx
	jne	LBB0_14
## %bb.18:                              ##   in Loop: Header=BB0_15 Depth=1
	movq	_MODE_AG_BW_80MHZ_8723B@GOTPCREL(%rip), %rcx
	jmp	LBB0_14
LBB0_19:
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_5
	.long	L0_0_set_6
	.long	L0_0_set_7
	.end_data_region
                                        ## -- End function
	.comm	_REG_WMAC_TRXPTCL_CTL,4,2       ## @REG_WMAC_TRXPTCL_CTL
	.comm	_WMAC_TRXPTCL_CTL_BW_MASK,4,2   ## @WMAC_TRXPTCL_CTL_BW_MASK
	.comm	_REG_RESPONSE_RATE_SET,4,2      ## @REG_RESPONSE_RATE_SET
	.comm	_WMAC_TRXPTCL_CTL_BW_20,4,2     ## @WMAC_TRXPTCL_CTL_BW_20
	.comm	_REG_FPGA0_RF_MODE,4,2          ## @REG_FPGA0_RF_MODE
	.comm	_FPGA_RF_MODE,4,2               ## @FPGA_RF_MODE
	.comm	_REG_FPGA1_RF_MODE,4,2          ## @REG_FPGA1_RF_MODE
	.comm	_REG_OFDM0_TX_PSDO_NOISE_WEIGHT,4,2 ## @REG_OFDM0_TX_PSDO_NOISE_WEIGHT
	.comm	_WMAC_TRXPTCL_CTL_BW_40,4,2     ## @WMAC_TRXPTCL_CTL_BW_40
	.comm	_REG_CCK0_SYSTEM,4,2            ## @REG_CCK0_SYSTEM
	.comm	_CCK0_SIDEBAND,4,2              ## @CCK0_SIDEBAND
	.comm	_REG_OFDM1_LSTF,4,2             ## @REG_OFDM1_LSTF
	.comm	_OFDM_LSTF_PRIME_CH_MASK,4,2    ## @OFDM_LSTF_PRIME_CH_MASK
	.comm	_OFDM_LSTF_PRIME_CH_LOW,4,2     ## @OFDM_LSTF_PRIME_CH_LOW
	.comm	_OFDM_LSTF_PRIME_CH_HIGH,4,2    ## @OFDM_LSTF_PRIME_CH_HIGH
	.comm	_REG_FPGA0_POWER_SAVE,4,2       ## @REG_FPGA0_POWER_SAVE
	.comm	_FPGA0_PS_LOWER_CHANNEL,4,2     ## @FPGA0_PS_LOWER_CHANNEL
	.comm	_FPGA0_PS_UPPER_CHANNEL,4,2     ## @FPGA0_PS_UPPER_CHANNEL
	.comm	_WMAC_TRXPTCL_CTL_BW_80,4,2     ## @WMAC_TRXPTCL_CTL_BW_80
	.comm	_RF_A,4,2                       ## @RF_A
	.comm	_RF6052_REG_MODE_AG,4,2         ## @RF6052_REG_MODE_AG
	.comm	_MODE_AG_CHANNEL_MASK,4,2       ## @MODE_AG_CHANNEL_MASK
	.comm	_REG_DATA_SUBCHANNEL,8,3        ## @REG_DATA_SUBCHANNEL
	.comm	_REG_SIFS_CCK,8,3               ## @REG_SIFS_CCK
	.comm	_REG_SIFS_OFDM,8,3              ## @REG_SIFS_OFDM
	.comm	_REG_R2T_SIFS,4,2               ## @REG_R2T_SIFS
	.comm	_REG_T2T_SIFS,4,2               ## @REG_T2T_SIFS
	.comm	_MODE_AG_BW_MASK,4,2            ## @MODE_AG_BW_MASK
	.comm	_MODE_AG_BW_80MHZ_8723B,4,2     ## @MODE_AG_BW_80MHZ_8723B
	.comm	_MODE_AG_BW_40MHZ_8723B,4,2     ## @MODE_AG_BW_40MHZ_8723B
	.comm	_MODE_AG_BW_20MHZ_8723B,4,2     ## @MODE_AG_BW_20MHZ_8723B
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rtl8xxxu_gen2_config_channel   ; -- Begin function rtl8xxxu_gen2_config_channel
	.p2align	2
_rtl8xxxu_gen2_config_channel:          ; @rtl8xxxu_gen2_config_channel
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x20, [x0, #24]
Lloh0:
	adrp	x24, _REG_WMAC_TRXPTCL_CTL@GOTPAGE
Lloh1:
	ldr	x24, [x24, _REG_WMAC_TRXPTCL_CTL@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_rtl8xxxu_read16
Lloh2:
	adrp	x8, _WMAC_TRXPTCL_CTL_BW_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _WMAC_TRXPTCL_CTL_BW_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w21, w0, w8
Lloh5:
	adrp	x8, _REG_RESPONSE_RATE_SET@GOTPAGE
Lloh6:
	ldr	x8, [x8, _REG_RESPONSE_RATE_SET@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	ldr	x8, [x19, #8]
	ldr	w25, [x8]
	ldr	w9, [x19]
	mov	w26, #1
	sub	w9, w9, #128
	cmp	w9, #3
	b.hi	LBB0_7
; %bb.1:
Lloh8:
	adrp	x10, lJTI0_0@PAGE
Lloh9:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_2
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_2:
Lloh10:
	adrp	x8, _WMAC_TRXPTCL_CTL_BW_80@GOTPAGE
Lloh11:
	ldr	x8, [x8, _WMAC_TRXPTCL_CTL_BW_80@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w21, w8, w21
	b	LBB0_4
LBB0_3:
Lloh13:
	adrp	x9, _WMAC_TRXPTCL_CTL_BW_40@GOTPAGE
Lloh14:
	ldr	x9, [x9, _WMAC_TRXPTCL_CTL_BW_40@GOTPAGEOFF]
Lloh15:
	ldr	w26, [x9]
	ldr	w22, [x19, #16]
	ldr	w23, [x8, #4]
Lloh16:
	adrp	x27, _REG_FPGA0_RF_MODE@GOTPAGE
Lloh17:
	ldr	x27, [x27, _REG_FPGA0_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh18:
	adrp	x28, _FPGA_RF_MODE@GOTPAGE
Lloh19:
	ldr	x28, [x28, _FPGA_RF_MODE@GOTPAGEOFF]
	ldr	w8, [x28]
	orr	w2, w8, w0
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh20:
	adrp	x27, _REG_FPGA1_RF_MODE@GOTPAGE
Lloh21:
	ldr	x27, [x27, _REG_FPGA1_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	ldr	w8, [x28]
	orr	w2, w8, w0
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh22:
	adrp	x27, _REG_CCK0_SYSTEM@GOTPAGE
Lloh23:
	ldr	x27, [x27, _REG_CCK0_SYSTEM@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh24:
	adrp	x8, _CCK0_SIDEBAND@GOTPAGE
Lloh25:
	ldr	x8, [x8, _CCK0_SIDEBAND@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	bic	w9, w0, w8
	orr	w8, w8, w0
	cmp	w22, w23
	csel	w2, w9, w8, gt
	ldr	w1, [x27]
Lloh27:
	adrp	x8, _OFDM_LSTF_PRIME_CH_LOW@GOTPAGE
Lloh28:
	ldr	x8, [x8, _OFDM_LSTF_PRIME_CH_LOW@GOTPAGEOFF]
Lloh29:
	adrp	x9, _OFDM_LSTF_PRIME_CH_HIGH@GOTPAGE
Lloh30:
	ldr	x9, [x9, _OFDM_LSTF_PRIME_CH_HIGH@GOTPAGEOFF]
	csel	x27, x8, x9, gt
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh31:
	adrp	x28, _REG_OFDM1_LSTF@GOTPAGE
Lloh32:
	ldr	x28, [x28, _REG_OFDM1_LSTF@GOTPAGEOFF]
	ldr	w1, [x28]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh33:
	adrp	x8, _OFDM_LSTF_PRIME_CH_MASK@GOTPAGE
Lloh34:
	ldr	x8, [x8, _OFDM_LSTF_PRIME_CH_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x27]
	orr	w2, w9, w8
	ldr	w1, [x28]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh36:
	adrp	x27, _REG_FPGA0_POWER_SAVE@GOTPAGE
Lloh37:
	ldr	x27, [x27, _REG_FPGA0_POWER_SAVE@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	orr	w21, w26, w21
	mov	w8, #2
Lloh38:
	adrp	x9, _FPGA0_PS_LOWER_CHANNEL@GOTPAGE
Lloh39:
	ldr	x9, [x9, _FPGA0_PS_LOWER_CHANNEL@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
Lloh41:
	adrp	x10, _FPGA0_PS_UPPER_CHANNEL@GOTPAGE
Lloh42:
	ldr	x10, [x10, _FPGA0_PS_UPPER_CHANNEL@GOTPAGEOFF]
Lloh43:
	ldr	w10, [x10]
	cmp	w22, w23
	csel	w11, w10, w9, gt
	cneg	w8, w8, le
	add	w25, w8, w25
	orr	w8, w10, w9
	bic	w8, w0, w8
	orr	w2, w8, w11
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_write32
LBB0_4:
	mov	w26, #1
	b	LBB0_7
LBB0_5:
	mov	w26, #0
LBB0_6:
Lloh44:
	adrp	x8, _WMAC_TRXPTCL_CTL_BW_20@GOTPAGE
Lloh45:
	ldr	x8, [x8, _WMAC_TRXPTCL_CTL_BW_20@GOTPAGEOFF]
Lloh46:
	ldr	w8, [x8]
	orr	w21, w8, w21
Lloh47:
	adrp	x22, _REG_FPGA0_RF_MODE@GOTPAGE
Lloh48:
	ldr	x22, [x22, _REG_FPGA0_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh49:
	adrp	x23, _FPGA_RF_MODE@GOTPAGE
Lloh50:
	ldr	x23, [x23, _FPGA_RF_MODE@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w2, w0, w8
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh51:
	adrp	x22, _REG_FPGA1_RF_MODE@GOTPAGE
Lloh52:
	ldr	x22, [x22, _REG_FPGA1_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	ldr	w8, [x23]
	bic	w2, w0, w8
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh53:
	adrp	x27, _REG_OFDM0_TX_PSDO_NOISE_WEIGHT@GOTPAGE
Lloh54:
	ldr	x27, [x27, _REG_OFDM0_TX_PSDO_NOISE_WEIGHT@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	mov	x22, x0
	mov	w0, #30
	bl	_BIT
	mov	x23, x0
	mov	w0, #31
	bl	_BIT
	orr	w8, w0, w23
	bic	w2, w22, w8
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_write32
LBB0_7:
Lloh55:
	adrp	x23, _RF_A@GOTPAGE
Lloh56:
	ldr	x23, [x23, _RF_A@GOTPAGEOFF]
	ldr	w22, [x23]
	ldr	w8, [x20]
	cmp	w22, w8
	b.ge	LBB0_10
; %bb.8:
Lloh57:
	adrp	x27, _RF6052_REG_MODE_AG@GOTPAGE
Lloh58:
	ldr	x27, [x27, _RF6052_REG_MODE_AG@GOTPAGEOFF]
Lloh59:
	adrp	x28, _MODE_AG_CHANNEL_MASK@GOTPAGE
Lloh60:
	ldr	x28, [x28, _MODE_AG_CHANNEL_MASK@GOTPAGEOFF]
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x27]
	mov	x0, x20
	mov	x1, x22
	bl	_rtl8xxxu_read_rfreg
	ldr	w8, [x28]
	bic	w8, w0, w8
	orr	w3, w8, w25
	ldr	w2, [x27]
	mov	x0, x20
	mov	x1, x22
	bl	_rtl8xxxu_write_rfreg
	add	w22, w22, #1
	ldr	w8, [x20]
	cmp	w22, w8
	b.lt	LBB0_9
LBB0_10:
	ldr	w1, [x24]
	mov	x0, x20
	mov	x2, x21
	bl	_rtl8xxxu_write16
Lloh61:
	adrp	x8, _REG_DATA_SUBCHANNEL@GOTPAGE
Lloh62:
	ldr	x8, [x8, _REG_DATA_SUBCHANNEL@GOTPAGEOFF]
Lloh63:
	ldr	x1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_rtl8xxxu_write8
	mov	w8, #14
	mov	w9, #10
	cmp	w26, #0
	csel	w21, w9, w8, eq
Lloh64:
	adrp	x8, _REG_SIFS_CCK@GOTPAGE
Lloh65:
	ldr	x8, [x8, _REG_SIFS_CCK@GOTPAGEOFF]
Lloh66:
	ldr	x8, [x8]
	add	x1, x8, #1
	mov	x0, x20
	mov	x2, x21
	bl	_rtl8xxxu_write8
Lloh67:
	adrp	x8, _REG_SIFS_OFDM@GOTPAGE
Lloh68:
	ldr	x8, [x8, _REG_SIFS_OFDM@GOTPAGEOFF]
Lloh69:
	ldr	x8, [x8]
	add	x1, x8, #1
	mov	x0, x20
	mov	x2, x21
	bl	_rtl8xxxu_write8
Lloh70:
	adrp	x8, _REG_R2T_SIFS@GOTPAGE
Lloh71:
	ldr	x8, [x8, _REG_R2T_SIFS@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2056
	bl	_rtl8xxxu_write16
Lloh73:
	adrp	x8, _REG_T2T_SIFS@GOTPAGE
Lloh74:
	ldr	x8, [x8, _REG_T2T_SIFS@GOTPAGEOFF]
Lloh75:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2570
	bl	_rtl8xxxu_write16
	ldr	w21, [x23]
	ldr	w8, [x20]
	cmp	w21, w8
	b.ge	LBB0_13
; %bb.11:
Lloh76:
	adrp	x22, _RF6052_REG_MODE_AG@GOTPAGE
Lloh77:
	ldr	x22, [x22, _RF6052_REG_MODE_AG@GOTPAGEOFF]
Lloh78:
	adrp	x23, _MODE_AG_BW_MASK@GOTPAGE
Lloh79:
	ldr	x23, [x23, _MODE_AG_BW_MASK@GOTPAGEOFF]
Lloh80:
	adrp	x24, _MODE_AG_BW_80MHZ_8723B@GOTPAGE
Lloh81:
	ldr	x24, [x24, _MODE_AG_BW_80MHZ_8723B@GOTPAGEOFF]
Lloh82:
	adrp	x25, _MODE_AG_BW_40MHZ_8723B@GOTPAGE
Lloh83:
	ldr	x25, [x25, _MODE_AG_BW_40MHZ_8723B@GOTPAGEOFF]
Lloh84:
	adrp	x26, _MODE_AG_BW_20MHZ_8723B@GOTPAGE
Lloh85:
	ldr	x26, [x26, _MODE_AG_BW_20MHZ_8723B@GOTPAGEOFF]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x21
	bl	_rtl8xxxu_read_rfreg
	ldr	w8, [x23]
	bic	w8, w0, w8
	ldr	w9, [x19]
	cmp	w9, #129
	csel	x10, x25, x26, eq
	cmp	w9, #128
	csel	x9, x24, x10, eq
	ldr	w9, [x9]
	orr	w3, w9, w8
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x21
	bl	_rtl8xxxu_write_rfreg
	add	w21, w21, #1
	ldr	w8, [x20]
	cmp	w21, w8
	b.lt	LBB0_12
LBB0_13:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh84, Lloh85
	.loh AdrpLdrGot	Lloh82, Lloh83
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh76, Lloh77
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
                                        ; -- End function
	.comm	_REG_WMAC_TRXPTCL_CTL,4,2       ; @REG_WMAC_TRXPTCL_CTL
	.comm	_WMAC_TRXPTCL_CTL_BW_MASK,4,2   ; @WMAC_TRXPTCL_CTL_BW_MASK
	.comm	_REG_RESPONSE_RATE_SET,4,2      ; @REG_RESPONSE_RATE_SET
	.comm	_WMAC_TRXPTCL_CTL_BW_20,4,2     ; @WMAC_TRXPTCL_CTL_BW_20
	.comm	_REG_FPGA0_RF_MODE,4,2          ; @REG_FPGA0_RF_MODE
	.comm	_FPGA_RF_MODE,4,2               ; @FPGA_RF_MODE
	.comm	_REG_FPGA1_RF_MODE,4,2          ; @REG_FPGA1_RF_MODE
	.comm	_REG_OFDM0_TX_PSDO_NOISE_WEIGHT,4,2 ; @REG_OFDM0_TX_PSDO_NOISE_WEIGHT
	.comm	_WMAC_TRXPTCL_CTL_BW_40,4,2     ; @WMAC_TRXPTCL_CTL_BW_40
	.comm	_REG_CCK0_SYSTEM,4,2            ; @REG_CCK0_SYSTEM
	.comm	_CCK0_SIDEBAND,4,2              ; @CCK0_SIDEBAND
	.comm	_REG_OFDM1_LSTF,4,2             ; @REG_OFDM1_LSTF
	.comm	_OFDM_LSTF_PRIME_CH_MASK,4,2    ; @OFDM_LSTF_PRIME_CH_MASK
	.comm	_OFDM_LSTF_PRIME_CH_LOW,4,2     ; @OFDM_LSTF_PRIME_CH_LOW
	.comm	_OFDM_LSTF_PRIME_CH_HIGH,4,2    ; @OFDM_LSTF_PRIME_CH_HIGH
	.comm	_REG_FPGA0_POWER_SAVE,4,2       ; @REG_FPGA0_POWER_SAVE
	.comm	_FPGA0_PS_LOWER_CHANNEL,4,2     ; @FPGA0_PS_LOWER_CHANNEL
	.comm	_FPGA0_PS_UPPER_CHANNEL,4,2     ; @FPGA0_PS_UPPER_CHANNEL
	.comm	_WMAC_TRXPTCL_CTL_BW_80,4,2     ; @WMAC_TRXPTCL_CTL_BW_80
	.comm	_RF_A,4,2                       ; @RF_A
	.comm	_RF6052_REG_MODE_AG,4,2         ; @RF6052_REG_MODE_AG
	.comm	_MODE_AG_CHANNEL_MASK,4,2       ; @MODE_AG_CHANNEL_MASK
	.comm	_REG_DATA_SUBCHANNEL,8,3        ; @REG_DATA_SUBCHANNEL
	.comm	_REG_SIFS_CCK,8,3               ; @REG_SIFS_CCK
	.comm	_REG_SIFS_OFDM,8,3              ; @REG_SIFS_OFDM
	.comm	_REG_R2T_SIFS,4,2               ; @REG_R2T_SIFS
	.comm	_REG_T2T_SIFS,4,2               ; @REG_T2T_SIFS
	.comm	_MODE_AG_BW_MASK,4,2            ; @MODE_AG_BW_MASK
	.comm	_MODE_AG_BW_80MHZ_8723B,4,2     ; @MODE_AG_BW_80MHZ_8723B
	.comm	_MODE_AG_BW_40MHZ_8723B,4,2     ; @MODE_AG_BW_40MHZ_8723B
	.comm	_MODE_AG_BW_20MHZ_8723B,4,2     ; @MODE_AG_BW_20MHZ_8723B
.subsections_via_symbols
