	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function config_gen3_gen4_eq_presets
_config_gen3_gen4_eq_presets:           ## @config_gen3_gen4_eq_presets
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	leaq	4(%rdi), %r14
	cmpl	$0, (%rdi)
	jle	LBB0_3
## %bb.1:
	movq	%rdi, %r12
	xorl	%r13d, %r13d
	xorl	%r15d, %r15d
	movq	%r14, -56(%rbp)                 ## 8-byte Spill
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	4(%r12), %edi
	movq	_CAP_SPCIE_CAP_OFF@GOTPCREL(%rip), %rbx
	addl	(%rbx), %edi
	addl	%r13d, %edi
	movl	$2, %esi
	leaq	-44(%rbp), %rdx
	callq	_dw_pcie_read
	movq	_CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	-44(%rbp), %eax
	movq	_GEN3_GEN4_EQ_PRESET_INIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	%edx, %eax
	movq	_CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	shll	%cl, %edx
	notl	%esi
	andl	%eax, %esi
	orl	%esi, %edx
	movl	%edx, -44(%rbp)
	movl	4(%r12), %edi
	addl	(%rbx), %edi
	addl	%r13d, %edi
	movl	$2, %esi
	callq	_dw_pcie_write
	movq	_PCI_EXT_CAP_ID_PL_16GT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_find_ext_capability
	movl	%eax, %ebx
	movq	_PCI_PL_16GT_LE_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	4(%r12), %edi
	addl	%ebx, %edi
	addl	%r14d, %edi
	addl	%r15d, %edi
	movl	$1, %esi
	leaq	-44(%rbp), %rdx
	callq	_dw_pcie_read
	movq	_PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	-44(%rbp), %eax
	movq	_GEN3_GEN4_EQ_PRESET_INIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	%edx, %eax
	movq	_PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	shll	%cl, %edx
	notl	%esi
	andl	%eax, %esi
	orl	%esi, %edx
	movl	%edx, -44(%rbp)
	addl	4(%r12), %ebx
	addl	%r14d, %ebx
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	addl	%r15d, %ebx
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_dw_pcie_write
	incl	%r15d
	addl	$2, %r13d
	cmpl	(%r12), %r15d
	jl	LBB0_2
LBB0_3:
	movq	_GEN3_RELATED_OFF@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	movl	%edx, -44(%rbp)
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_GEN3_EQ_CONTROL_OFF@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	movq	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$1023, %esi                     ## imm = 0x3FF
	shll	%cl, %esi
	andl	%eax, %edx
	orl	%edx, %esi
	movq	_GEN3_EQ_CONTROL_OFF_FB_MODE_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	notl	%edx
	andl	%esi, %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_writel_dbi
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %edx
	movl	%edx, -44(%rbp)
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_writel_dbi
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$864, %esi                      ## imm = 0x360
	shll	%cl, %esi
	notl	%edx
	andl	%eax, %edx
	orl	%edx, %esi
	movl	(%r12), %edx
	notl	%edx
	andl	%esi, %edx
	movl	%edx, -44(%rbp)
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_writel_dbi
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	movl	%edx, -44(%rbp)
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_writel_dbi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CAP_SPCIE_CAP_OFF,4,2          ## @CAP_SPCIE_CAP_OFF
	.comm	_CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK,4,2 ## @CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK
	.comm	_GEN3_GEN4_EQ_PRESET_INIT,4,2   ## @GEN3_GEN4_EQ_PRESET_INIT
	.comm	_CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK,4,2 ## @CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK
	.comm	_CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT,4,2 ## @CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT
	.comm	_PCI_EXT_CAP_ID_PL_16GT,4,2     ## @PCI_EXT_CAP_ID_PL_16GT
	.comm	_PCI_PL_16GT_LE_CTRL,4,2        ## @PCI_PL_16GT_LE_CTRL
	.comm	_PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK,4,2 ## @PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK
	.comm	_PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK,4,2 ## @PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK
	.comm	_PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT,4,2 ## @PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT
	.comm	_GEN3_RELATED_OFF,4,2           ## @GEN3_RELATED_OFF
	.comm	_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,4,2 ## @GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK
	.comm	_GEN3_EQ_CONTROL_OFF,4,2        ## @GEN3_EQ_CONTROL_OFF
	.comm	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK,4,2 ## @GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK
	.comm	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT,4,2 ## @GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT
	.comm	_GEN3_EQ_CONTROL_OFF_FB_MODE_MASK,4,2 ## @GEN3_EQ_CONTROL_OFF_FB_MODE_MASK
	.comm	_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT,4,2 ## @GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT
	.no_dead_strip	_config_gen3_gen4_eq_presets
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function config_gen3_gen4_eq_presets
_config_gen3_gen4_eq_presets:           ; @config_gen3_gen4_eq_presets
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	w8, [x19], #4
	cmp	w8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	x20, x0
	mov	w22, #0
	mov	w23, #0
Lloh0:
	adrp	x24, _CAP_SPCIE_CAP_OFF@GOTPAGE
Lloh1:
	ldr	x24, [x24, _CAP_SPCIE_CAP_OFF@GOTPAGEOFF]
Lloh2:
	adrp	x26, _GEN3_GEN4_EQ_PRESET_INIT@GOTPAGE
Lloh3:
	ldr	x26, [x26, _GEN3_GEN4_EQ_PRESET_INIT@GOTPAGEOFF]
Lloh4:
	adrp	x25, _PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK@GOTPAGE
Lloh5:
	ldr	x25, [x25, _PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK@GOTPAGEOFF]
Lloh6:
	adrp	x27, _PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT@GOTPAGE
Lloh7:
	ldr	x27, [x27, _PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x20, #4]
	ldr	w9, [x24]
	add	w8, w8, w9
	add	w0, w22, w8
	add	x2, sp, #12
	mov	w1, #2
	bl	_dw_pcie_read
Lloh8:
	adrp	x8, _CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	ldr	w9, [x26]
	orr	w8, w9, w8
Lloh11:
	adrp	x10, _CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK@GOTPAGE
Lloh12:
	ldr	x10, [x10, _CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
	bic	w8, w8, w10
Lloh14:
	adrp	x10, _CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT@GOTPAGE
Lloh15:
	ldr	x10, [x10, _CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT@GOTPAGEOFF]
Lloh16:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w8, [x20, #4]
	ldr	w9, [x24]
	add	w8, w8, w9
	add	w0, w22, w8
	mov	w1, #2
	bl	_dw_pcie_write
Lloh17:
	adrp	x8, _PCI_EXT_CAP_ID_PL_16GT@GOTPAGE
Lloh18:
	ldr	x8, [x8, _PCI_EXT_CAP_ID_PL_16GT@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_dw_pcie_find_ext_capability
	mov	x21, x0
Lloh20:
	adrp	x8, _PCI_PL_16GT_LE_CTRL@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PCI_PL_16GT_LE_CTRL@GOTPAGEOFF]
Lloh22:
	ldr	w28, [x8]
	ldr	w8, [x20, #4]
	add	w8, w0, w8
	add	w8, w8, w28
	add	w0, w23, w8
	add	x2, sp, #12
	mov	w1, #1
	bl	_dw_pcie_read
Lloh23:
	adrp	x8, _PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	ldr	w9, [x26]
	orr	w8, w9, w8
	ldr	w10, [x25]
	bic	w8, w8, w10
	ldr	w10, [x27]
	lsl	w9, w9, w10
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w8, [x20, #4]
	add	w8, w21, w8
	add	w8, w8, w28
	add	w0, w23, w8
	mov	w1, #1
	bl	_dw_pcie_write
	add	w23, w23, #1
	ldr	w8, [x20]
	add	w22, w22, #2
	cmp	w23, w8
	b.lt	LBB0_2
LBB0_3:
Lloh26:
	adrp	x20, _GEN3_RELATED_OFF@GOTPAGE
Lloh27:
	ldr	x20, [x20, _GEN3_RELATED_OFF@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh28:
	adrp	x21, _GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK@GOTPAGE
Lloh29:
	ldr	x21, [x21, _GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK@GOTPAGEOFF]
	ldr	w8, [x21]
	bic	w2, w0, w8
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
Lloh30:
	adrp	x22, _GEN3_EQ_CONTROL_OFF@GOTPAGE
Lloh31:
	ldr	x22, [x22, _GEN3_EQ_CONTROL_OFF@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh32:
	adrp	x23, _GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK@GOTPAGE
Lloh33:
	ldr	x23, [x23, _GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK@GOTPAGEOFF]
	ldr	w8, [x23]
	bic	w8, w0, w8
Lloh34:
	adrp	x24, _GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT@GOTPAGE
Lloh35:
	ldr	x24, [x24, _GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT@GOTPAGEOFF]
	ldr	w9, [x24]
	mov	w10, #1023
	lsl	w9, w10, w9
	orr	w8, w9, w8
Lloh36:
	adrp	x25, _GEN3_EQ_CONTROL_OFF_FB_MODE_MASK@GOTPAGE
Lloh37:
	ldr	x25, [x25, _GEN3_EQ_CONTROL_OFF_FB_MODE_MASK@GOTPAGEOFF]
	ldr	w9, [x25]
	bic	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	ldr	w8, [x21]
	bic	w8, w0, w8
Lloh38:
	adrp	x9, _GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT@GOTPAGE
Lloh39:
	ldr	x9, [x9, _GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	mov	w10, #1
	lsl	w9, w10, w9
	orr	w2, w9, w8
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
	ldr	w1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	ldr	w8, [x23]
	bic	w8, w0, w8
	ldr	w9, [x24]
	mov	w10, #864
	lsl	w9, w10, w9
	orr	w8, w9, w8
	ldr	w9, [x25]
	bic	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	ldr	w8, [x21]
	bic	w2, w0, w8
	str	w2, [sp, #12]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.cfi_endproc
                                        ; -- End function
	.comm	_CAP_SPCIE_CAP_OFF,4,2          ; @CAP_SPCIE_CAP_OFF
	.comm	_CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK,4,2 ; @CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK
	.comm	_GEN3_GEN4_EQ_PRESET_INIT,4,2   ; @GEN3_GEN4_EQ_PRESET_INIT
	.comm	_CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK,4,2 ; @CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK
	.comm	_CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT,4,2 ; @CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT
	.comm	_PCI_EXT_CAP_ID_PL_16GT,4,2     ; @PCI_EXT_CAP_ID_PL_16GT
	.comm	_PCI_PL_16GT_LE_CTRL,4,2        ; @PCI_PL_16GT_LE_CTRL
	.comm	_PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK,4,2 ; @PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK
	.comm	_PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK,4,2 ; @PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK
	.comm	_PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT,4,2 ; @PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT
	.comm	_GEN3_RELATED_OFF,4,2           ; @GEN3_RELATED_OFF
	.comm	_GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,4,2 ; @GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK
	.comm	_GEN3_EQ_CONTROL_OFF,4,2        ; @GEN3_EQ_CONTROL_OFF
	.comm	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK,4,2 ; @GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK
	.comm	_GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT,4,2 ; @GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT
	.comm	_GEN3_EQ_CONTROL_OFF_FB_MODE_MASK,4,2 ; @GEN3_EQ_CONTROL_OFF_FB_MODE_MASK
	.comm	_GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT,4,2 ; @GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT
	.no_dead_strip	_config_gen3_gen4_eq_presets
.subsections_via_symbols
