	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_hns_ppe_set_indir_table        ## -- Begin function hns_ppe_set_indir_table
	.p2align	4, 0x90
_hns_ppe_set_indir_table:               ## @hns_ppe_set_indir_table
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	_HNS_PPEV2_RSS_IND_TBL_SIZE@GOTPCREL(%rip), %r14
	cmpl	$4, (%r14)
	jl	LBB0_3
## %bb.1:
	xorl	%ebx, %ebx
	xorl	%r12d, %r12d
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	_PPEV2_INDRECTION_TBL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_dsaf_read_dev
	movl	%eax, %r13d
	movq	_PPEV2_CFG_RSS_TBL_4N0_M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PPEV2_CFG_RSS_TBL_4N0_S@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r15,%rbx,4), %ecx
	andl	$31, %ecx
	movl	%r13d, %edi
	callq	_dsaf_set_field
	movq	_PPEV2_CFG_RSS_TBL_4N1_M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PPEV2_CFG_RSS_TBL_4N1_S@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	4(%r15,%rbx,4), %ecx
	andl	$31, %ecx
	movl	%r13d, %edi
	callq	_dsaf_set_field
	movq	_PPEV2_CFG_RSS_TBL_4N2_M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PPEV2_CFG_RSS_TBL_4N2_S@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	8(%r15,%rbx,4), %ecx
	andl	$31, %ecx
	movl	%r13d, %edi
	callq	_dsaf_set_field
	movq	_PPEV2_CFG_RSS_TBL_4N3_M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PPEV2_CFG_RSS_TBL_4N3_S@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	12(%r15,%rbx,4), %ecx
	andl	$31, %ecx
	movl	%r13d, %edi
	callq	_dsaf_set_field
	movq	_PPEV2_INDRECTION_TBL_REG@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%rbx, %rsi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movl	%r13d, %edx
	callq	_dsaf_write_dev
	incq	%r12
	movl	(%r14), %eax
	leal	3(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$2, %ecx
	movslq	%ecx, %rax
	addq	$4, %rbx
	cmpq	%rax, %r12
	jl	LBB0_2
LBB0_3:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_HNS_PPEV2_RSS_IND_TBL_SIZE,4,2 ## @HNS_PPEV2_RSS_IND_TBL_SIZE
	.comm	_PPEV2_INDRECTION_TBL_REG,8,3   ## @PPEV2_INDRECTION_TBL_REG
	.comm	_PPEV2_CFG_RSS_TBL_4N0_M,4,2    ## @PPEV2_CFG_RSS_TBL_4N0_M
	.comm	_PPEV2_CFG_RSS_TBL_4N0_S,4,2    ## @PPEV2_CFG_RSS_TBL_4N0_S
	.comm	_PPEV2_CFG_RSS_TBL_4N1_M,4,2    ## @PPEV2_CFG_RSS_TBL_4N1_M
	.comm	_PPEV2_CFG_RSS_TBL_4N1_S,4,2    ## @PPEV2_CFG_RSS_TBL_4N1_S
	.comm	_PPEV2_CFG_RSS_TBL_4N2_M,4,2    ## @PPEV2_CFG_RSS_TBL_4N2_M
	.comm	_PPEV2_CFG_RSS_TBL_4N2_S,4,2    ## @PPEV2_CFG_RSS_TBL_4N2_S
	.comm	_PPEV2_CFG_RSS_TBL_4N3_M,4,2    ## @PPEV2_CFG_RSS_TBL_4N3_M
	.comm	_PPEV2_CFG_RSS_TBL_4N3_S,4,2    ## @PPEV2_CFG_RSS_TBL_4N3_S
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_hns_ppe_set_indir_table        ; -- Begin function hns_ppe_set_indir_table
	.p2align	2
_hns_ppe_set_indir_table:               ; @hns_ppe_set_indir_table
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
Lloh0:
	adrp	x22, _HNS_PPEV2_RSS_IND_TBL_SIZE@GOTPAGE
Lloh1:
	ldr	x22, [x22, _HNS_PPEV2_RSS_IND_TBL_SIZE@GOTPAGEOFF]
	ldr	w8, [x22]
	cmp	w8, #4
	b.lt	LBB0_3
; %bb.1:
	mov	x19, x1
	mov	x20, x0
	mov	x23, #0
	mov	x24, #0
Lloh2:
	adrp	x25, _PPEV2_INDRECTION_TBL_REG@GOTPAGE
Lloh3:
	ldr	x25, [x25, _PPEV2_INDRECTION_TBL_REG@GOTPAGEOFF]
Lloh4:
	adrp	x28, _PPEV2_CFG_RSS_TBL_4N3_M@GOTPAGE
Lloh5:
	ldr	x28, [x28, _PPEV2_CFG_RSS_TBL_4N3_M@GOTPAGEOFF]
Lloh6:
	adrp	x26, _PPEV2_CFG_RSS_TBL_4N3_S@GOTPAGE
Lloh7:
	ldr	x26, [x26, _PPEV2_CFG_RSS_TBL_4N3_S@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x25]
	add	x1, x23, x8
	mov	x0, x20
	bl	_dsaf_read_dev
	mov	x21, x0
Lloh8:
	adrp	x8, _PPEV2_CFG_RSS_TBL_4N0_M@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PPEV2_CFG_RSS_TBL_4N0_M@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
Lloh11:
	adrp	x8, _PPEV2_CFG_RSS_TBL_4N0_S@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PPEV2_CFG_RSS_TBL_4N0_S@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	add	x27, x19, x23, lsl #2
	ldr	w8, [x27]
	and	w3, w8, #0x1f
	bl	_dsaf_set_field
Lloh14:
	adrp	x8, _PPEV2_CFG_RSS_TBL_4N1_M@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PPEV2_CFG_RSS_TBL_4N1_M@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
Lloh17:
	adrp	x8, _PPEV2_CFG_RSS_TBL_4N1_S@GOTPAGE
Lloh18:
	ldr	x8, [x8, _PPEV2_CFG_RSS_TBL_4N1_S@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	ldr	w8, [x27, #4]
	and	w3, w8, #0x1f
	mov	x0, x21
	bl	_dsaf_set_field
Lloh20:
	adrp	x8, _PPEV2_CFG_RSS_TBL_4N2_M@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PPEV2_CFG_RSS_TBL_4N2_M@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
Lloh23:
	adrp	x8, _PPEV2_CFG_RSS_TBL_4N2_S@GOTPAGE
Lloh24:
	ldr	x8, [x8, _PPEV2_CFG_RSS_TBL_4N2_S@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	ldr	w8, [x27, #8]
	and	w3, w8, #0x1f
	mov	x0, x21
	bl	_dsaf_set_field
	ldr	w1, [x28]
	ldr	w2, [x26]
	ldr	w8, [x27, #12]
	and	w3, w8, #0x1f
	mov	x0, x21
	bl	_dsaf_set_field
	ldr	x8, [x25]
	add	x1, x23, x8
	mov	x0, x20
	mov	x2, x21
	bl	_dsaf_write_dev
	add	x24, x24, #1
	ldr	w8, [x22]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w8, w8, #2
	add	x23, x23, #4
	cmp	x24, w8, sxtw
	b.lt	LBB0_2
LBB0_3:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.cfi_endproc
                                        ; -- End function
	.comm	_HNS_PPEV2_RSS_IND_TBL_SIZE,4,2 ; @HNS_PPEV2_RSS_IND_TBL_SIZE
	.comm	_PPEV2_INDRECTION_TBL_REG,8,3   ; @PPEV2_INDRECTION_TBL_REG
	.comm	_PPEV2_CFG_RSS_TBL_4N0_M,4,2    ; @PPEV2_CFG_RSS_TBL_4N0_M
	.comm	_PPEV2_CFG_RSS_TBL_4N0_S,4,2    ; @PPEV2_CFG_RSS_TBL_4N0_S
	.comm	_PPEV2_CFG_RSS_TBL_4N1_M,4,2    ; @PPEV2_CFG_RSS_TBL_4N1_M
	.comm	_PPEV2_CFG_RSS_TBL_4N1_S,4,2    ; @PPEV2_CFG_RSS_TBL_4N1_S
	.comm	_PPEV2_CFG_RSS_TBL_4N2_M,4,2    ; @PPEV2_CFG_RSS_TBL_4N2_M
	.comm	_PPEV2_CFG_RSS_TBL_4N2_S,4,2    ; @PPEV2_CFG_RSS_TBL_4N2_S
	.comm	_PPEV2_CFG_RSS_TBL_4N3_M,4,2    ; @PPEV2_CFG_RSS_TBL_4N3_M
	.comm	_PPEV2_CFG_RSS_TBL_4N3_S,4,2    ; @PPEV2_CFG_RSS_TBL_4N3_S
.subsections_via_symbols
