	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_ip6_init
_mvpp2_prs_ip6_init:                    ## @mvpp2_prs_ip6_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_IPPROTO_TCP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L4_TCP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MVPP2_PRS_RI_L4_PROTO_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	callq	_mvpp2_prs_ip6_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_7
## %bb.1:
	movq	_IPPROTO_UDP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L4_UDP@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r12), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_ip6_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_7
## %bb.2:
	movq	_IPPROTO_ICMPV6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	_MVPP2_PRS_RI_CPU_CODE_MASK@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_UDF3_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_ip6_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_7
## %bb.3:
	movq	_IPPROTO_IPIP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_UDF7_IP6_LITE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MVPP2_PRS_RI_UDF7_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r15, %rdi
	callq	_mvpp2_prs_ip6_proto
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_7
## %bb.4:
	movq	_MVPP2_PRS_L3_MULTI_CAST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_mvpp2_prs_ip6_cast
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_7
## %bb.5:
	movq	_MVPP2_PE_FIRST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PE_LAST_FREE_TID@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_tcam_first_free
	movl	%eax, %ebx
	testl	%eax, %eax
	js	LBB0_7
## %bb.6:
	leaq	-48(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_MVPP2_PRS_LU_IP6@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movl	%ebx, -48(%rbp)
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_RI_L3_UN@GOTPCREL(%rip), %rax
	movq	_MVPP2_PRS_RI_DROP_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	(%rax), %esi
	orl	%edx, %esi
	movq	_MVPP2_PRS_RI_L3_PROTO_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_IPV6_HOP_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	movl	$1, %esi
	xorl	%edx, %edx
	callq	_mvpp2_prs_tcam_data_byte_set
	movq	_MVPP2_PRS_IPV6_NO_EXT_AI_BIT@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movl	-48(%rbp), %esi
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PE_IP6_PROTO_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_RI_L4_OTHER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_L4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_mvpp2_prs_sram_offset_set
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movq	_MVPP2_PRS_PORT_MASK@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PE_IP6_EXT_PROTO_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movq	_MVPP2_PRS_LU_FLOWS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_RI_L4_OTHER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r12), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_IPV6_EXT_AI_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movq	_MVPP2_PRS_LU_IP4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_lu_set
	movq	_MVPP2_PE_IP6_ADDR_UN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -48(%rbp)
	movl	(%r13), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_next_lu_set
	movq	_MVPP2_PRS_RI_L3_UCAST@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MVPP2_PRS_RI_L3_ADDR_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mvpp2_prs_sram_ri_update
	movq	_MVPP2_PRS_IPV6_NO_EXT_AI_BIT@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r14, %rdi
	movl	%edx, %esi
	callq	_mvpp2_prs_sram_ai_update
	movq	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	movl	$-18, %esi
	callq	_mvpp2_prs_sram_shift_set
	movl	(%r12), %edx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_mvpp2_prs_tcam_ai_update
	movq	_MVPP2_PRS_PORT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_mvpp2_prs_tcam_port_map_set
	movl	-48(%rbp), %esi
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_mvpp2_prs_shadow_set
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	_mvpp2_prs_hw_write
	xorl	%ebx, %ebx
LBB0_7:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IPPROTO_TCP,4,2                ## @IPPROTO_TCP
	.comm	_MVPP2_PRS_RI_L4_TCP,4,2        ## @MVPP2_PRS_RI_L4_TCP
	.comm	_MVPP2_PRS_RI_L4_PROTO_MASK,4,2 ## @MVPP2_PRS_RI_L4_PROTO_MASK
	.comm	_IPPROTO_UDP,4,2                ## @IPPROTO_UDP
	.comm	_MVPP2_PRS_RI_L4_UDP,4,2        ## @MVPP2_PRS_RI_L4_UDP
	.comm	_IPPROTO_ICMPV6,4,2             ## @IPPROTO_ICMPV6
	.comm	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC,4,2 ## @MVPP2_PRS_RI_CPU_CODE_RX_SPEC
	.comm	_MVPP2_PRS_RI_UDF3_RX_SPECIAL,4,2 ## @MVPP2_PRS_RI_UDF3_RX_SPECIAL
	.comm	_MVPP2_PRS_RI_CPU_CODE_MASK,4,2 ## @MVPP2_PRS_RI_CPU_CODE_MASK
	.comm	_MVPP2_PRS_RI_UDF3_MASK,4,2     ## @MVPP2_PRS_RI_UDF3_MASK
	.comm	_IPPROTO_IPIP,4,2               ## @IPPROTO_IPIP
	.comm	_MVPP2_PRS_RI_UDF7_IP6_LITE,4,2 ## @MVPP2_PRS_RI_UDF7_IP6_LITE
	.comm	_MVPP2_PRS_RI_UDF7_MASK,4,2     ## @MVPP2_PRS_RI_UDF7_MASK
	.comm	_MVPP2_PRS_L3_MULTI_CAST,4,2    ## @MVPP2_PRS_L3_MULTI_CAST
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ## @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ## @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_IP6,4,2           ## @MVPP2_PRS_LU_IP6
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ## @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ## @MVPP2_PRS_SRAM_LU_GEN_BIT
	.comm	_MVPP2_PRS_RI_L3_UN,4,2         ## @MVPP2_PRS_RI_L3_UN
	.comm	_MVPP2_PRS_RI_DROP_MASK,4,2     ## @MVPP2_PRS_RI_DROP_MASK
	.comm	_MVPP2_PRS_RI_L3_PROTO_MASK,4,2 ## @MVPP2_PRS_RI_L3_PROTO_MASK
	.comm	_MVPP2_PRS_IPV6_HOP_MASK,4,2    ## @MVPP2_PRS_IPV6_HOP_MASK
	.comm	_MVPP2_PRS_IPV6_NO_EXT_AI_BIT,4,2 ## @MVPP2_PRS_IPV6_NO_EXT_AI_BIT
	.comm	_MVPP2_PRS_LU_IP4,4,2           ## @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PE_IP6_PROTO_UN,4,2      ## @MVPP2_PE_IP6_PROTO_UN
	.comm	_MVPP2_PRS_RI_L4_OTHER,4,2      ## @MVPP2_PRS_RI_L4_OTHER
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L4,4,2 ## @MVPP2_PRS_SRAM_UDF_TYPE_L4
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ## @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PE_IP6_EXT_PROTO_UN,4,2  ## @MVPP2_PE_IP6_EXT_PROTO_UN
	.comm	_MVPP2_PRS_IPV6_EXT_AI_BIT,4,2  ## @MVPP2_PRS_IPV6_EXT_AI_BIT
	.comm	_MVPP2_PE_IP6_ADDR_UN,4,2       ## @MVPP2_PE_IP6_ADDR_UN
	.comm	_MVPP2_PRS_RI_L3_UCAST,4,2      ## @MVPP2_PRS_RI_L3_UCAST
	.comm	_MVPP2_PRS_RI_L3_ADDR_MASK,4,2  ## @MVPP2_PRS_RI_L3_ADDR_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.no_dead_strip	_mvpp2_prs_ip6_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_ip6_init
_mvpp2_prs_ip6_init:                    ; @mvpp2_prs_ip6_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
Lloh0:
	adrp	x8, _IPPROTO_TCP@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IPPROTO_TCP@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _MVPP2_PRS_RI_L4_TCP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MVPP2_PRS_RI_L4_TCP@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
Lloh6:
	adrp	x21, _MVPP2_PRS_RI_L4_PROTO_MASK@GOTPAGE
Lloh7:
	ldr	x21, [x21, _MVPP2_PRS_RI_L4_PROTO_MASK@GOTPAGEOFF]
	ldr	w3, [x21]
	bl	_mvpp2_prs_ip6_proto
	mov	x20, x0
	cbnz	w0, LBB0_7
; %bb.1:
Lloh8:
	adrp	x8, _IPPROTO_UDP@GOTPAGE
Lloh9:
	ldr	x8, [x8, _IPPROTO_UDP@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
Lloh11:
	adrp	x8, _MVPP2_PRS_RI_L4_UDP@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MVPP2_PRS_RI_L4_UDP@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	ldr	w3, [x21]
	mov	x0, x19
	bl	_mvpp2_prs_ip6_proto
	mov	x20, x0
	cbnz	w0, LBB0_7
; %bb.2:
Lloh14:
	adrp	x8, _IPPROTO_ICMPV6@GOTPAGE
Lloh15:
	ldr	x8, [x8, _IPPROTO_ICMPV6@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
Lloh17:
	adrp	x8, _MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MVPP2_PRS_RI_CPU_CODE_RX_SPEC@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
Lloh20:
	adrp	x9, _MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPAGE
Lloh21:
	ldr	x9, [x9, _MVPP2_PRS_RI_UDF3_RX_SPECIAL@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
Lloh23:
	adrp	x10, _MVPP2_PRS_RI_CPU_CODE_MASK@GOTPAGE
Lloh24:
	ldr	x10, [x10, _MVPP2_PRS_RI_CPU_CODE_MASK@GOTPAGEOFF]
	orr	w2, w9, w8
Lloh25:
	ldr	w8, [x10]
Lloh26:
	adrp	x9, _MVPP2_PRS_RI_UDF3_MASK@GOTPAGE
Lloh27:
	ldr	x9, [x9, _MVPP2_PRS_RI_UDF3_MASK@GOTPAGEOFF]
Lloh28:
	ldr	w9, [x9]
	orr	w3, w9, w8
	mov	x0, x19
	bl	_mvpp2_prs_ip6_proto
	mov	x20, x0
	cbnz	w0, LBB0_7
; %bb.3:
Lloh29:
	adrp	x8, _IPPROTO_IPIP@GOTPAGE
Lloh30:
	ldr	x8, [x8, _IPPROTO_IPIP@GOTPAGEOFF]
Lloh31:
	ldr	w1, [x8]
Lloh32:
	adrp	x8, _MVPP2_PRS_RI_UDF7_IP6_LITE@GOTPAGE
Lloh33:
	ldr	x8, [x8, _MVPP2_PRS_RI_UDF7_IP6_LITE@GOTPAGEOFF]
Lloh34:
	ldr	w2, [x8]
Lloh35:
	adrp	x8, _MVPP2_PRS_RI_UDF7_MASK@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MVPP2_PRS_RI_UDF7_MASK@GOTPAGEOFF]
Lloh37:
	ldr	w3, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_ip6_proto
	mov	x20, x0
	cbnz	w0, LBB0_7
; %bb.4:
Lloh38:
	adrp	x8, _MVPP2_PRS_L3_MULTI_CAST@GOTPAGE
Lloh39:
	ldr	x8, [x8, _MVPP2_PRS_L3_MULTI_CAST@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_ip6_cast
	mov	x20, x0
	cbnz	w0, LBB0_7
; %bb.5:
Lloh41:
	adrp	x8, _MVPP2_PE_FIRST_FREE_TID@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MVPP2_PE_FIRST_FREE_TID@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
Lloh44:
	adrp	x8, _MVPP2_PE_LAST_FREE_TID@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MVPP2_PE_LAST_FREE_TID@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_tcam_first_free
	mov	x20, x0
	tbnz	w0, #31, LBB0_7
; %bb.6:
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh47:
	adrp	x22, _MVPP2_PRS_LU_IP6@GOTPAGE
Lloh48:
	ldr	x22, [x22, _MVPP2_PRS_LU_IP6@GOTPAGEOFF]
	ldr	w1, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
	str	w20, [sp, #8]
Lloh49:
	adrp	x23, _MVPP2_PRS_LU_FLOWS@GOTPAGE
Lloh50:
	ldr	x23, [x23, _MVPP2_PRS_LU_FLOWS@GOTPAGEOFF]
	ldr	w1, [x23]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh51:
	adrp	x24, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGE
Lloh52:
	ldr	x24, [x24, _MVPP2_PRS_SRAM_LU_GEN_BIT@GOTPAGEOFF]
	ldr	w1, [x24]
	add	x0, sp, #8
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
Lloh53:
	adrp	x8, _MVPP2_PRS_RI_L3_UN@GOTPAGE
Lloh54:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_UN@GOTPAGEOFF]
Lloh55:
	ldr	w8, [x8]
Lloh56:
	adrp	x9, _MVPP2_PRS_RI_DROP_MASK@GOTPAGE
Lloh57:
	ldr	x9, [x9, _MVPP2_PRS_RI_DROP_MASK@GOTPAGEOFF]
Lloh58:
	ldr	w9, [x9]
	orr	w1, w9, w8
Lloh59:
	adrp	x8, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGE
Lloh60:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_PROTO_MASK@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	orr	w2, w8, w9
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
Lloh62:
	adrp	x8, _MVPP2_PRS_IPV6_HOP_MASK@GOTPAGE
Lloh63:
	ldr	x8, [x8, _MVPP2_PRS_IPV6_HOP_MASK@GOTPAGEOFF]
Lloh64:
	ldr	w3, [x8]
	add	x0, sp, #8
	mov	w1, #1
	mov	w2, #0
	bl	_mvpp2_prs_tcam_data_byte_set
Lloh65:
	adrp	x20, _MVPP2_PRS_IPV6_NO_EXT_AI_BIT@GOTPAGE
Lloh66:
	ldr	x20, [x20, _MVPP2_PRS_IPV6_NO_EXT_AI_BIT@GOTPAGEOFF]
	ldr	w1, [x20]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_tcam_ai_update
	ldr	w1, [sp, #8]
Lloh67:
	adrp	x25, _MVPP2_PRS_LU_IP4@GOTPAGE
Lloh68:
	ldr	x25, [x25, _MVPP2_PRS_LU_IP4@GOTPAGEOFF]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	w1, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
Lloh69:
	adrp	x8, _MVPP2_PE_IP6_PROTO_UN@GOTPAGE
Lloh70:
	ldr	x8, [x8, _MVPP2_PE_IP6_PROTO_UN@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	ldr	w1, [x23]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
	ldr	w1, [x24]
	add	x0, sp, #8
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
Lloh72:
	adrp	x27, _MVPP2_PRS_RI_L4_OTHER@GOTPAGE
Lloh73:
	ldr	x27, [x27, _MVPP2_PRS_RI_L4_OTHER@GOTPAGEOFF]
	ldr	w1, [x27]
	ldr	w2, [x21]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
Lloh74:
	adrp	x8, _MVPP2_PRS_SRAM_UDF_TYPE_L4@GOTPAGE
Lloh75:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_UDF_TYPE_L4@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
Lloh77:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGE
Lloh78:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_UDF_ADD@GOTPAGEOFF]
Lloh79:
	ldr	w3, [x8]
	add	x0, sp, #8
	mov	w2, #0
	bl	_mvpp2_prs_sram_offset_set
	ldr	w1, [x20]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_tcam_ai_update
Lloh80:
	adrp	x26, _MVPP2_PRS_PORT_MASK@GOTPAGE
Lloh81:
	ldr	x26, [x26, _MVPP2_PRS_PORT_MASK@GOTPAGEOFF]
	ldr	w1, [x26]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	w1, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
Lloh82:
	adrp	x8, _MVPP2_PE_IP6_EXT_PROTO_UN@GOTPAGE
Lloh83:
	ldr	x8, [x8, _MVPP2_PE_IP6_EXT_PROTO_UN@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	ldr	w1, [x23]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
	ldr	w1, [x24]
	add	x0, sp, #8
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
	ldr	w1, [x27]
	ldr	w2, [x21]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
Lloh85:
	adrp	x8, _MVPP2_PRS_IPV6_EXT_AI_BIT@GOTPAGE
Lloh86:
	ldr	x8, [x8, _MVPP2_PRS_IPV6_EXT_AI_BIT@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_tcam_ai_update
	ldr	w1, [x26]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x25]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
	ldr	w1, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_lu_set
Lloh88:
	adrp	x8, _MVPP2_PE_IP6_ADDR_UN@GOTPAGE
Lloh89:
	ldr	x8, [x8, _MVPP2_PE_IP6_ADDR_UN@GOTPAGEOFF]
Lloh90:
	ldr	w8, [x8]
	str	w8, [sp, #8]
	ldr	w1, [x22]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_next_lu_set
Lloh91:
	adrp	x8, _MVPP2_PRS_RI_L3_UCAST@GOTPAGE
Lloh92:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_UCAST@GOTPAGEOFF]
Lloh93:
	ldr	w1, [x8]
Lloh94:
	adrp	x8, _MVPP2_PRS_RI_L3_ADDR_MASK@GOTPAGE
Lloh95:
	ldr	x8, [x8, _MVPP2_PRS_RI_L3_ADDR_MASK@GOTPAGEOFF]
Lloh96:
	ldr	w2, [x8]
	add	x0, sp, #8
	bl	_mvpp2_prs_sram_ri_update
	ldr	w1, [x20]
	add	x0, sp, #8
	mov	x2, x1
	bl	_mvpp2_prs_sram_ai_update
Lloh97:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGE
Lloh98:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD@GOTPAGEOFF]
Lloh99:
	ldr	w2, [x8]
	add	x0, sp, #8
	mov	w1, #-18
	bl	_mvpp2_prs_sram_shift_set
	ldr	w2, [x20]
	add	x0, sp, #8
	mov	w1, #0
	bl	_mvpp2_prs_tcam_ai_update
	ldr	w1, [x26]
	add	x0, sp, #8
	bl	_mvpp2_prs_tcam_port_map_set
	ldr	w1, [sp, #8]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_mvpp2_prs_shadow_set
	add	x1, sp, #8
	mov	x0, x19
	bl	_mvpp2_prs_hw_write
	mov	w20, #0
LBB0_7:
	mov	x0, x20
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGot	Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGot	Lloh67, Lloh68
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.cfi_endproc
                                        ; -- End function
	.comm	_IPPROTO_TCP,4,2                ; @IPPROTO_TCP
	.comm	_MVPP2_PRS_RI_L4_TCP,4,2        ; @MVPP2_PRS_RI_L4_TCP
	.comm	_MVPP2_PRS_RI_L4_PROTO_MASK,4,2 ; @MVPP2_PRS_RI_L4_PROTO_MASK
	.comm	_IPPROTO_UDP,4,2                ; @IPPROTO_UDP
	.comm	_MVPP2_PRS_RI_L4_UDP,4,2        ; @MVPP2_PRS_RI_L4_UDP
	.comm	_IPPROTO_ICMPV6,4,2             ; @IPPROTO_ICMPV6
	.comm	_MVPP2_PRS_RI_CPU_CODE_RX_SPEC,4,2 ; @MVPP2_PRS_RI_CPU_CODE_RX_SPEC
	.comm	_MVPP2_PRS_RI_UDF3_RX_SPECIAL,4,2 ; @MVPP2_PRS_RI_UDF3_RX_SPECIAL
	.comm	_MVPP2_PRS_RI_CPU_CODE_MASK,4,2 ; @MVPP2_PRS_RI_CPU_CODE_MASK
	.comm	_MVPP2_PRS_RI_UDF3_MASK,4,2     ; @MVPP2_PRS_RI_UDF3_MASK
	.comm	_IPPROTO_IPIP,4,2               ; @IPPROTO_IPIP
	.comm	_MVPP2_PRS_RI_UDF7_IP6_LITE,4,2 ; @MVPP2_PRS_RI_UDF7_IP6_LITE
	.comm	_MVPP2_PRS_RI_UDF7_MASK,4,2     ; @MVPP2_PRS_RI_UDF7_MASK
	.comm	_MVPP2_PRS_L3_MULTI_CAST,4,2    ; @MVPP2_PRS_L3_MULTI_CAST
	.comm	_MVPP2_PE_FIRST_FREE_TID,4,2    ; @MVPP2_PE_FIRST_FREE_TID
	.comm	_MVPP2_PE_LAST_FREE_TID,4,2     ; @MVPP2_PE_LAST_FREE_TID
	.comm	_MVPP2_PRS_LU_IP6,4,2           ; @MVPP2_PRS_LU_IP6
	.comm	_MVPP2_PRS_LU_FLOWS,4,2         ; @MVPP2_PRS_LU_FLOWS
	.comm	_MVPP2_PRS_SRAM_LU_GEN_BIT,4,2  ; @MVPP2_PRS_SRAM_LU_GEN_BIT
	.comm	_MVPP2_PRS_RI_L3_UN,4,2         ; @MVPP2_PRS_RI_L3_UN
	.comm	_MVPP2_PRS_RI_DROP_MASK,4,2     ; @MVPP2_PRS_RI_DROP_MASK
	.comm	_MVPP2_PRS_RI_L3_PROTO_MASK,4,2 ; @MVPP2_PRS_RI_L3_PROTO_MASK
	.comm	_MVPP2_PRS_IPV6_HOP_MASK,4,2    ; @MVPP2_PRS_IPV6_HOP_MASK
	.comm	_MVPP2_PRS_IPV6_NO_EXT_AI_BIT,4,2 ; @MVPP2_PRS_IPV6_NO_EXT_AI_BIT
	.comm	_MVPP2_PRS_LU_IP4,4,2           ; @MVPP2_PRS_LU_IP4
	.comm	_MVPP2_PE_IP6_PROTO_UN,4,2      ; @MVPP2_PE_IP6_PROTO_UN
	.comm	_MVPP2_PRS_RI_L4_OTHER,4,2      ; @MVPP2_PRS_RI_L4_OTHER
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_L4,4,2 ; @MVPP2_PRS_SRAM_UDF_TYPE_L4
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_UDF_ADD
	.comm	_MVPP2_PRS_PORT_MASK,4,2        ; @MVPP2_PRS_PORT_MASK
	.comm	_MVPP2_PE_IP6_EXT_PROTO_UN,4,2  ; @MVPP2_PE_IP6_EXT_PROTO_UN
	.comm	_MVPP2_PRS_IPV6_EXT_AI_BIT,4,2  ; @MVPP2_PRS_IPV6_EXT_AI_BIT
	.comm	_MVPP2_PE_IP6_ADDR_UN,4,2       ; @MVPP2_PE_IP6_ADDR_UN
	.comm	_MVPP2_PRS_RI_L3_UCAST,4,2      ; @MVPP2_PRS_RI_L3_UCAST
	.comm	_MVPP2_PRS_RI_L3_ADDR_MASK,4,2  ; @MVPP2_PRS_RI_L3_ADDR_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD
	.no_dead_strip	_mvpp2_prs_ip6_init
.subsections_via_symbols
