	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function bcm7xxx_28nm_ephy_eee_enable
_bcm7xxx_28nm_ephy_eee_enable:          ## @bcm7xxx_28nm_ephy_eee_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_MII_BCM7XXX_TEST@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MII_BCM7XXX_SHD_MODE_2@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	xorl	%ecx, %ecx
	callq	_phy_set_clr_bits
	testl	%eax, %eax
	js	LBB0_12
## %bb.1:
	movq	_MII_BCM7XXX_SHD_2_ADDR_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MII_BCM7XXX_SHD_3_AN_EEE_ADV@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.2:
	movq	_MII_BCM7XXX_SHD_2_CTRL_STAT@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_MDIO_EEE_100TX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.3:
	movl	(%rbx), %esi
	movq	_MII_BCM7XXX_SHD_3_PCS_CTRL_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.4:
	movl	(%r13), %esi
	movq	_MII_BCM7XXX_PCS_CTRL_2_DEF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.5:
	movl	(%rbx), %esi
	movq	_MII_BCM7XXX_SHD_3_EEE_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.6:
	movl	(%r13), %esi
	movq	_MII_BCM7XXX_EEE_THRESH_DEF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.7:
	movl	(%rbx), %esi
	movq	_MII_BCM7XXX_SHD_3_AN_STAT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	testl	%eax, %eax
	js	LBB0_9
## %bb.8:
	movl	(%r13), %esi
	movq	_MII_BCM7XXX_AN_NULL_MSG_EN@GOTPCREL(%rip), %rax
	movq	_MII_BCM7XXX_AN_EEE_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
LBB0_9:
	movl	(%r15), %esi
	movl	(%r12), %ecx
	xorl	%ebx, %ebx
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_phy_set_clr_bits
	testl	%eax, %eax
	js	LBB0_12
## %bb.10:
	movq	_MII_BMCR@GOTPCREL(%rip), %rax
	movq	_BMCR_SPEED100@GOTPCREL(%rip), %rcx
	movq	_BMCR_ANENABLE@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_BMCR_ANRESTART@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_phy_write
	jmp	LBB0_13
LBB0_12:
	movl	%eax, %ebx
LBB0_13:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MII_BCM7XXX_TEST,4,2           ## @MII_BCM7XXX_TEST
	.comm	_MII_BCM7XXX_SHD_MODE_2,4,2     ## @MII_BCM7XXX_SHD_MODE_2
	.comm	_MII_BCM7XXX_SHD_2_ADDR_CTRL,4,2 ## @MII_BCM7XXX_SHD_2_ADDR_CTRL
	.comm	_MII_BCM7XXX_SHD_3_AN_EEE_ADV,4,2 ## @MII_BCM7XXX_SHD_3_AN_EEE_ADV
	.comm	_MII_BCM7XXX_SHD_2_CTRL_STAT,4,2 ## @MII_BCM7XXX_SHD_2_CTRL_STAT
	.comm	_MDIO_EEE_100TX,4,2             ## @MDIO_EEE_100TX
	.comm	_MII_BCM7XXX_SHD_3_PCS_CTRL_2,4,2 ## @MII_BCM7XXX_SHD_3_PCS_CTRL_2
	.comm	_MII_BCM7XXX_PCS_CTRL_2_DEF,4,2 ## @MII_BCM7XXX_PCS_CTRL_2_DEF
	.comm	_MII_BCM7XXX_SHD_3_EEE_THRESH,4,2 ## @MII_BCM7XXX_SHD_3_EEE_THRESH
	.comm	_MII_BCM7XXX_EEE_THRESH_DEF,4,2 ## @MII_BCM7XXX_EEE_THRESH_DEF
	.comm	_MII_BCM7XXX_SHD_3_AN_STAT,4,2  ## @MII_BCM7XXX_SHD_3_AN_STAT
	.comm	_MII_BCM7XXX_AN_NULL_MSG_EN,4,2 ## @MII_BCM7XXX_AN_NULL_MSG_EN
	.comm	_MII_BCM7XXX_AN_EEE_EN,4,2      ## @MII_BCM7XXX_AN_EEE_EN
	.comm	_MII_BMCR,4,2                   ## @MII_BMCR
	.comm	_BMCR_SPEED100,4,2              ## @BMCR_SPEED100
	.comm	_BMCR_ANENABLE,4,2              ## @BMCR_ANENABLE
	.comm	_BMCR_ANRESTART,4,2             ## @BMCR_ANRESTART
	.no_dead_strip	_bcm7xxx_28nm_ephy_eee_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function bcm7xxx_28nm_ephy_eee_enable
_bcm7xxx_28nm_ephy_eee_enable:          ; @bcm7xxx_28nm_ephy_eee_enable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x20, _MII_BCM7XXX_TEST@GOTPAGE
Lloh1:
	ldr	x20, [x20, _MII_BCM7XXX_TEST@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x21, _MII_BCM7XXX_SHD_MODE_2@GOTPAGE
Lloh3:
	ldr	x21, [x21, _MII_BCM7XXX_SHD_MODE_2@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	w3, #0
	bl	_phy_set_clr_bits
	tbnz	w0, #31, LBB0_11
; %bb.1:
Lloh4:
	adrp	x23, _MII_BCM7XXX_SHD_2_ADDR_CTRL@GOTPAGE
Lloh5:
	ldr	x23, [x23, _MII_BCM7XXX_SHD_2_ADDR_CTRL@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh6:
	adrp	x8, _MII_BCM7XXX_SHD_3_AN_EEE_ADV@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MII_BCM7XXX_SHD_3_AN_EEE_ADV@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.2:
Lloh9:
	adrp	x22, _MII_BCM7XXX_SHD_2_CTRL_STAT@GOTPAGE
Lloh10:
	ldr	x22, [x22, _MII_BCM7XXX_SHD_2_CTRL_STAT@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh11:
	adrp	x8, _MDIO_EEE_100TX@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MDIO_EEE_100TX@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.3:
	ldr	w1, [x23]
Lloh14:
	adrp	x8, _MII_BCM7XXX_SHD_3_PCS_CTRL_2@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MII_BCM7XXX_SHD_3_PCS_CTRL_2@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.4:
	ldr	w1, [x22]
Lloh17:
	adrp	x8, _MII_BCM7XXX_PCS_CTRL_2_DEF@GOTPAGE
Lloh18:
	ldr	x8, [x8, _MII_BCM7XXX_PCS_CTRL_2_DEF@GOTPAGEOFF]
Lloh19:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.5:
	ldr	w1, [x23]
Lloh20:
	adrp	x8, _MII_BCM7XXX_SHD_3_EEE_THRESH@GOTPAGE
Lloh21:
	ldr	x8, [x8, _MII_BCM7XXX_SHD_3_EEE_THRESH@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.6:
	ldr	w1, [x22]
Lloh23:
	adrp	x8, _MII_BCM7XXX_EEE_THRESH_DEF@GOTPAGE
Lloh24:
	ldr	x8, [x8, _MII_BCM7XXX_EEE_THRESH_DEF@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.7:
	ldr	w1, [x23]
Lloh26:
	adrp	x8, _MII_BCM7XXX_SHD_3_AN_STAT@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MII_BCM7XXX_SHD_3_AN_STAT@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_phy_write
	tbnz	w0, #31, LBB0_9
; %bb.8:
Lloh29:
	adrp	x8, _MII_BCM7XXX_AN_NULL_MSG_EN@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MII_BCM7XXX_AN_NULL_MSG_EN@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh31:
	ldr	w8, [x8]
Lloh32:
	adrp	x9, _MII_BCM7XXX_AN_EEE_EN@GOTPAGE
Lloh33:
	ldr	x9, [x9, _MII_BCM7XXX_AN_EEE_EN@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_phy_write
LBB0_9:
	ldr	w1, [x20]
	ldr	w3, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_phy_set_clr_bits
	tbnz	w0, #31, LBB0_11
; %bb.10:
Lloh35:
	adrp	x8, _MII_BMCR@GOTPAGE
Lloh36:
	ldr	x8, [x8, _MII_BMCR@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
Lloh38:
	adrp	x8, _BMCR_SPEED100@GOTPAGE
Lloh39:
	ldr	x8, [x8, _BMCR_SPEED100@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
Lloh41:
	adrp	x9, _BMCR_ANENABLE@GOTPAGE
Lloh42:
	ldr	x9, [x9, _BMCR_ANENABLE@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh44:
	adrp	x9, _BMCR_ANRESTART@GOTPAGE
Lloh45:
	ldr	x9, [x9, _BMCR_ANRESTART@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_phy_write
	mov	w0, #0
LBB0_11:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_MII_BCM7XXX_TEST,4,2           ; @MII_BCM7XXX_TEST
	.comm	_MII_BCM7XXX_SHD_MODE_2,4,2     ; @MII_BCM7XXX_SHD_MODE_2
	.comm	_MII_BCM7XXX_SHD_2_ADDR_CTRL,4,2 ; @MII_BCM7XXX_SHD_2_ADDR_CTRL
	.comm	_MII_BCM7XXX_SHD_3_AN_EEE_ADV,4,2 ; @MII_BCM7XXX_SHD_3_AN_EEE_ADV
	.comm	_MII_BCM7XXX_SHD_2_CTRL_STAT,4,2 ; @MII_BCM7XXX_SHD_2_CTRL_STAT
	.comm	_MDIO_EEE_100TX,4,2             ; @MDIO_EEE_100TX
	.comm	_MII_BCM7XXX_SHD_3_PCS_CTRL_2,4,2 ; @MII_BCM7XXX_SHD_3_PCS_CTRL_2
	.comm	_MII_BCM7XXX_PCS_CTRL_2_DEF,4,2 ; @MII_BCM7XXX_PCS_CTRL_2_DEF
	.comm	_MII_BCM7XXX_SHD_3_EEE_THRESH,4,2 ; @MII_BCM7XXX_SHD_3_EEE_THRESH
	.comm	_MII_BCM7XXX_EEE_THRESH_DEF,4,2 ; @MII_BCM7XXX_EEE_THRESH_DEF
	.comm	_MII_BCM7XXX_SHD_3_AN_STAT,4,2  ; @MII_BCM7XXX_SHD_3_AN_STAT
	.comm	_MII_BCM7XXX_AN_NULL_MSG_EN,4,2 ; @MII_BCM7XXX_AN_NULL_MSG_EN
	.comm	_MII_BCM7XXX_AN_EEE_EN,4,2      ; @MII_BCM7XXX_AN_EEE_EN
	.comm	_MII_BMCR,4,2                   ; @MII_BMCR
	.comm	_BMCR_SPEED100,4,2              ; @BMCR_SPEED100
	.comm	_BMCR_ANENABLE,4,2              ; @BMCR_ANENABLE
	.comm	_BMCR_ANRESTART,4,2             ; @BMCR_ANRESTART
	.no_dead_strip	_bcm7xxx_28nm_ephy_eee_enable
.subsections_via_symbols
