	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_apply_sw_fixup
_tegra_pcie_apply_sw_fixup:             ## @tegra_pcie_apply_sw_fixup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	cmpq	$0, 24(%r14)
	je	LBB0_2
## %bb.1:
	movq	_RP_VEND_CTL0@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	movq	_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	callq	_writel
LBB0_2:
	cmpq	$0, 16(%r14)
	je	LBB0_4
## %bb.3:
	movq	_RP_RX_HDR_LIMIT@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_RX_HDR_LIMIT_PW_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	movq	_RP_RX_HDR_LIMIT_PW@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	callq	_writel
	movq	_RP_PRIV_XP_DL@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_RP_VEND_XP@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	orl	(%r14), %edi
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	callq	_writel
LBB0_4:
	cmpq	$0, 8(%r14)
	je	LBB0_6
## %bb.5:
	movq	_RP_VEND_XP@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	orl	(%r14), %edi
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	callq	_writel
LBB0_6:
	movq	_RP_LINK_CONTROL_STATUS_2@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_PCI_EXP_LNKSTA_CLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	movq	_PCI_EXP_LNKSTA_CLS_2_5GB@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	(%r14), %rsi
	addq	(%rbx), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RP_VEND_CTL0,8,3               ## @RP_VEND_CTL0
	.comm	_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK,4,2 ## @RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK
	.comm	_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH,4,2 ## @RP_VEND_CTL0_DSK_RST_PULSE_WIDTH
	.comm	_RP_RX_HDR_LIMIT,8,3            ## @RP_RX_HDR_LIMIT
	.comm	_RP_RX_HDR_LIMIT_PW_MASK,4,2    ## @RP_RX_HDR_LIMIT_PW_MASK
	.comm	_RP_RX_HDR_LIMIT_PW,4,2         ## @RP_RX_HDR_LIMIT_PW
	.comm	_RP_PRIV_XP_DL,8,3              ## @RP_PRIV_XP_DL
	.comm	_RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD,4,2 ## @RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD
	.comm	_RP_VEND_XP,8,3                 ## @RP_VEND_XP
	.comm	_RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK,4,2 ## @RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK
	.comm	_RP_LINK_CONTROL_STATUS_2,8,3   ## @RP_LINK_CONTROL_STATUS_2
	.comm	_PCI_EXP_LNKSTA_CLS,4,2         ## @PCI_EXP_LNKSTA_CLS
	.comm	_PCI_EXP_LNKSTA_CLS_2_5GB,4,2   ## @PCI_EXP_LNKSTA_CLS_2_5GB
	.no_dead_strip	_tegra_pcie_apply_sw_fixup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_apply_sw_fixup
_tegra_pcie_apply_sw_fixup:             ; @tegra_pcie_apply_sw_fixup
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x20, [x8]
	ldr	x8, [x20, #24]
	cbz	x8, LBB0_2
; %bb.1:
	ldr	x8, [x19]
Lloh0:
	adrp	x21, _RP_VEND_CTL0@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RP_VEND_CTL0@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh2:
	adrp	x8, _RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _RP_VEND_CTL0_DSK_RST_PULSE_WIDTH@GOTPAGE
Lloh6:
	ldr	x9, [x9, _RP_VEND_CTL0_DSK_RST_PULSE_WIDTH@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh7:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
LBB0_2:
	ldr	x8, [x20, #16]
Lloh8:
	adrp	x21, _RP_VEND_XP@GOTPAGE
Lloh9:
	ldr	x21, [x21, _RP_VEND_XP@GOTPAGEOFF]
Lloh10:
	adrp	x22, _RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK@GOTPAGE
Lloh11:
	ldr	x22, [x22, _RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK@GOTPAGEOFF]
	cbz	x8, LBB0_4
; %bb.3:
	ldr	x8, [x19]
Lloh12:
	adrp	x23, _RP_RX_HDR_LIMIT@GOTPAGE
Lloh13:
	ldr	x23, [x23, _RP_RX_HDR_LIMIT@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_readl
Lloh14:
	adrp	x8, _RP_RX_HDR_LIMIT_PW_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _RP_RX_HDR_LIMIT_PW_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _RP_RX_HDR_LIMIT_PW@GOTPAGE
Lloh18:
	ldr	x9, [x9, _RP_RX_HDR_LIMIT_PW@GOTPAGEOFF]
	bic	w8, w0, w8
Lloh19:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19]
	ldr	x9, [x23]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
Lloh20:
	adrp	x23, _RP_PRIV_XP_DL@GOTPAGE
Lloh21:
	ldr	x23, [x23, _RP_PRIV_XP_DL@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x0, x9, x8
	bl	_readl
Lloh22:
	adrp	x8, _RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x19]
	ldr	x9, [x23]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x22]
	bic	w8, w0, w8
	ldr	w9, [x20]
	orr	w0, w8, w9
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
LBB0_4:
	ldr	x8, [x20, #8]
	cbz	x8, LBB0_6
; %bb.5:
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x22]
	bic	w8, w0, w8
	ldr	w9, [x20]
	orr	w0, w8, w9
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
LBB0_6:
	ldr	x8, [x19]
Lloh25:
	adrp	x20, _RP_LINK_CONTROL_STATUS_2@GOTPAGE
Lloh26:
	ldr	x20, [x20, _RP_LINK_CONTROL_STATUS_2@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh27:
	adrp	x8, _PCI_EXP_LNKSTA_CLS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PCI_EXP_LNKSTA_CLS@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh30:
	adrp	x9, _PCI_EXP_LNKSTA_CLS_2_5GB@GOTPAGE
Lloh31:
	ldr	x9, [x9, _PCI_EXP_LNKSTA_CLS_2_5GB@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_RP_VEND_CTL0,8,3               ; @RP_VEND_CTL0
	.comm	_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK,4,2 ; @RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK
	.comm	_RP_VEND_CTL0_DSK_RST_PULSE_WIDTH,4,2 ; @RP_VEND_CTL0_DSK_RST_PULSE_WIDTH
	.comm	_RP_RX_HDR_LIMIT,8,3            ; @RP_RX_HDR_LIMIT
	.comm	_RP_RX_HDR_LIMIT_PW_MASK,4,2    ; @RP_RX_HDR_LIMIT_PW_MASK
	.comm	_RP_RX_HDR_LIMIT_PW,4,2         ; @RP_RX_HDR_LIMIT_PW
	.comm	_RP_PRIV_XP_DL,8,3              ; @RP_PRIV_XP_DL
	.comm	_RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD,4,2 ; @RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD
	.comm	_RP_VEND_XP,8,3                 ; @RP_VEND_XP
	.comm	_RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK,4,2 ; @RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK
	.comm	_RP_LINK_CONTROL_STATUS_2,8,3   ; @RP_LINK_CONTROL_STATUS_2
	.comm	_PCI_EXP_LNKSTA_CLS,4,2         ; @PCI_EXP_LNKSTA_CLS
	.comm	_PCI_EXP_LNKSTA_CLS_2_5GB,4,2   ; @PCI_EXP_LNKSTA_CLS_2_5GB
	.no_dead_strip	_tegra_pcie_apply_sw_fixup
.subsections_via_symbols
