	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_prs_sram_offset_set
_mvpp2_prs_sram_offset_set:             ## @mvpp2_prs_sram_offset_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, %r12d
	movl	%esi, -44(%rbp)                 ## 4-byte Spill
	movq	%rdi, %rbx
	movq	_MVPP2_PRS_SRAM_UDF_SIGN_BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	testl	%edx, %edx
	js	LBB0_1
## %bb.2:
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_clear
	jmp	LBB0_3
LBB0_1:
	movl	$1, %edx
	callq	_mvpp2_prs_sram_bits_set
	negl	%r12d
LBB0_3:
	movq	_MVPP2_PRS_SRAM_UDF_OFFS@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_MVPP2_PRS_SRAM_UDF_MASK@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_bits_clear
	movl	(%r13), %esi
	andl	(%r15), %r12d
	movq	%rbx, %rdi
	movl	%r12d, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_OFFS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MVPP2_PRS_SRAM_UDF_TYPE_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_bits_clear
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MVPP2_PRS_SRAM_OP_SEL_UDF_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%rbx, %rdi
	callq	_mvpp2_prs_sram_bits_clear
	movl	(%r15), %esi
	andl	(%r12), %r14d
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_mvpp2_prs_sram_bits_set
	movq	_MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	movl	$1, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvpp2_prs_sram_bits_clear      ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_PRS_SRAM_UDF_SIGN_BIT,4,2 ## @MVPP2_PRS_SRAM_UDF_SIGN_BIT
	.comm	_MVPP2_PRS_SRAM_UDF_OFFS,4,2    ## @MVPP2_PRS_SRAM_UDF_OFFS
	.comm	_MVPP2_PRS_SRAM_UDF_MASK,4,2    ## @MVPP2_PRS_SRAM_UDF_MASK
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_OFFS,4,2 ## @MVPP2_PRS_SRAM_UDF_TYPE_OFFS
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_MASK,4,2 ## @MVPP2_PRS_SRAM_UDF_TYPE_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_MASK,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS,4,2 ## @MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
	.no_dead_strip	_mvpp2_prs_sram_offset_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_prs_sram_offset_set
_mvpp2_prs_sram_offset_set:             ; @mvpp2_prs_sram_offset_set
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x3
	mov	x22, x2
	mov	x21, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _MVPP2_PRS_SRAM_UDF_SIGN_BIT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_UDF_SIGN_BIT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	tbnz	w2, #31, LBB0_2
; %bb.1:
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_clear
	b	LBB0_3
LBB0_2:
	mov	w2, #1
	bl	_mvpp2_prs_sram_bits_set
	neg	w22, w22
LBB0_3:
Lloh3:
	adrp	x23, _MVPP2_PRS_SRAM_UDF_OFFS@GOTPAGE
Lloh4:
	ldr	x23, [x23, _MVPP2_PRS_SRAM_UDF_OFFS@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh5:
	adrp	x24, _MVPP2_PRS_SRAM_UDF_MASK@GOTPAGE
Lloh6:
	ldr	x24, [x24, _MVPP2_PRS_SRAM_UDF_MASK@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_mvpp2_prs_sram_bits_clear
	ldr	w1, [x23]
	ldr	w8, [x24]
	and	w2, w8, w22
	mov	x0, x19
	bl	_mvpp2_prs_sram_bits_set
Lloh7:
	adrp	x22, _MVPP2_PRS_SRAM_UDF_TYPE_OFFS@GOTPAGE
Lloh8:
	ldr	x22, [x22, _MVPP2_PRS_SRAM_UDF_TYPE_OFFS@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh9:
	adrp	x8, _MVPP2_PRS_SRAM_UDF_TYPE_MASK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_UDF_TYPE_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mvpp2_prs_sram_bits_clear
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x21
	bl	_mvpp2_prs_sram_bits_set
Lloh12:
	adrp	x21, _MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS@GOTPAGE
Lloh13:
	ldr	x21, [x21, _MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh14:
	adrp	x22, _MVPP2_PRS_SRAM_OP_SEL_UDF_MASK@GOTPAGE
Lloh15:
	ldr	x22, [x22, _MVPP2_PRS_SRAM_OP_SEL_UDF_MASK@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x19
	bl	_mvpp2_prs_sram_bits_clear
	ldr	w1, [x21]
	ldr	w8, [x22]
	and	w2, w8, w20
	mov	x0, x19
	bl	_mvpp2_prs_sram_bits_set
Lloh16:
	adrp	x8, _MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS@GOTPAGE
Lloh17:
	ldr	x8, [x8, _MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_mvpp2_prs_sram_bits_clear
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_PRS_SRAM_UDF_SIGN_BIT,4,2 ; @MVPP2_PRS_SRAM_UDF_SIGN_BIT
	.comm	_MVPP2_PRS_SRAM_UDF_OFFS,4,2    ; @MVPP2_PRS_SRAM_UDF_OFFS
	.comm	_MVPP2_PRS_SRAM_UDF_MASK,4,2    ; @MVPP2_PRS_SRAM_UDF_MASK
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_OFFS,4,2 ; @MVPP2_PRS_SRAM_UDF_TYPE_OFFS
	.comm	_MVPP2_PRS_SRAM_UDF_TYPE_MASK,4,2 ; @MVPP2_PRS_SRAM_UDF_TYPE_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS
	.comm	_MVPP2_PRS_SRAM_OP_SEL_UDF_MASK,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_UDF_MASK
	.comm	_MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS,4,2 ; @MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS
	.no_dead_strip	_mvpp2_prs_sram_offset_set
.subsections_via_symbols
