	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function stih4xx_fix_retime_src
_stih4xx_fix_retime_src:                ## @stih4xx_fix_retime_src
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %r14
	movq	16(%rdi), %rdi
	movq	_PHY_INTERFACE_MODE_MII@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdi
	jne	LBB0_2
## %bb.1:
	movq	_TX_RETIME_SRC_TXCLK@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	jmp	LBB0_19
LBB0_2:
	movq	_PHY_INTERFACE_MODE_RMII@GOTPCREL(%rip), %rax
	cmpq	(%rax), %rdi
	jne	LBB0_6
## %bb.3:
	cmpq	$0, 32(%rbx)
	je	LBB0_5
## %bb.4:
	movq	_TX_RETIME_SRC_PHYCLK@GOTPCREL(%rip), %rax
	movq	(%rax), %r12
	jmp	LBB0_19
LBB0_6:
	movq	%rsi, %r15
	movq	(%rbx), %r12
	callq	_IS_PHY_IF_MODE_RGMII
	testq	%rax, %rax
	je	LBB0_19
## %bb.7:
	movq	_SPEED_1000@GOTPCREL(%rip), %rax
	cmpq	%r15, (%rax)
	jne	LBB0_9
## %bb.8:
	movq	_DWMAC_125MHZ@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_TX_RETIME_SRC_CLKGEN@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	jmp	LBB0_16
LBB0_5:
	movq	_TX_RETIME_SRC_CLKGEN@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	movq	_DWMAC_50MHZ@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_9:
	movq	_TX_RETIME_SRC_CLKGEN@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	movq	_SPEED_100@GOTPCREL(%rip), %rax
	cmpq	%r15, (%rax)
	jne	LBB0_11
## %bb.10:
	movq	_DWMAC_25MHZ@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_11:
	movq	_SPEED_10@GOTPCREL(%rip), %rax
	cmpq	%r15, (%rax)
	jne	LBB0_12
## %bb.13:
	movq	_DWMAC_2_5MHZ@GOTPCREL(%rip), %rax
LBB0_14:
	movq	(%rax), %rsi
LBB0_15:
	movq	%r13, %r12
LBB0_16:
	cmpq	%r13, %r12
	jne	LBB0_19
## %bb.17:
	testq	%rsi, %rsi
	je	LBB0_19
## %bb.18:
	movl	28(%rbx), %edi
	callq	_clk_set_rate
	movq	%r13, %r12
LBB0_19:
	movl	24(%rbx), %edi
	movq	_STIH4XX_RETIME_SRC_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_stih4xx_tx_retime_val@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movl	(%rax,%r12,4), %ecx
	movq	%r14, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_update_bits             ## TAILCALL
LBB0_12:
	xorl	%esi, %esi
	jmp	LBB0_15
	.cfi_endproc
                                        ## -- End function
	.comm	_PHY_INTERFACE_MODE_MII,8,3     ## @PHY_INTERFACE_MODE_MII
	.comm	_TX_RETIME_SRC_TXCLK,8,3        ## @TX_RETIME_SRC_TXCLK
	.comm	_PHY_INTERFACE_MODE_RMII,8,3    ## @PHY_INTERFACE_MODE_RMII
	.comm	_TX_RETIME_SRC_PHYCLK,8,3       ## @TX_RETIME_SRC_PHYCLK
	.comm	_TX_RETIME_SRC_CLKGEN,8,3       ## @TX_RETIME_SRC_CLKGEN
	.comm	_DWMAC_50MHZ,8,3                ## @DWMAC_50MHZ
	.comm	_SPEED_1000,8,3                 ## @SPEED_1000
	.comm	_DWMAC_125MHZ,8,3               ## @DWMAC_125MHZ
	.comm	_SPEED_100,8,3                  ## @SPEED_100
	.comm	_DWMAC_25MHZ,8,3                ## @DWMAC_25MHZ
	.comm	_SPEED_10,8,3                   ## @SPEED_10
	.comm	_DWMAC_2_5MHZ,8,3               ## @DWMAC_2_5MHZ
	.comm	_STIH4XX_RETIME_SRC_MASK,4,2    ## @STIH4XX_RETIME_SRC_MASK
	.comm	_stih4xx_tx_retime_val,8,3      ## @stih4xx_tx_retime_val
	.no_dead_strip	_stih4xx_fix_retime_src
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function stih4xx_fix_retime_src
_stih4xx_fix_retime_src:                ; @stih4xx_fix_retime_src
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	ldp	x19, x0, [x0, #8]
Lloh0:
	adrp	x8, _PHY_INTERFACE_MODE_MII@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PHY_INTERFACE_MODE_MII@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _TX_RETIME_SRC_TXCLK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _TX_RETIME_SRC_TXCLK@GOTPAGEOFF]
Lloh5:
	ldr	x22, [x8]
	b	LBB0_15
LBB0_2:
Lloh6:
	adrp	x8, _PHY_INTERFACE_MODE_RMII@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PHY_INTERFACE_MODE_RMII@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	cmp	x0, x8
	b.ne	LBB0_5
; %bb.3:
	ldr	x8, [x20, #32]
	cbz	x8, LBB0_8
; %bb.4:
Lloh9:
	adrp	x8, _TX_RETIME_SRC_PHYCLK@GOTPAGE
Lloh10:
	ldr	x8, [x8, _TX_RETIME_SRC_PHYCLK@GOTPAGEOFF]
Lloh11:
	ldr	x22, [x8]
	b	LBB0_15
LBB0_5:
	mov	x21, x1
	ldr	x22, [x20]
	bl	_IS_PHY_IF_MODE_RGMII
	cbz	x0, LBB0_15
; %bb.6:
Lloh12:
	adrp	x8, _SPEED_1000@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SPEED_1000@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
	cmp	x8, x21
	b.ne	LBB0_9
; %bb.7:
Lloh15:
	adrp	x8, _DWMAC_125MHZ@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DWMAC_125MHZ@GOTPAGEOFF]
Lloh17:
	ldr	x1, [x8]
Lloh18:
	adrp	x8, _TX_RETIME_SRC_CLKGEN@GOTPAGE
Lloh19:
	ldr	x8, [x8, _TX_RETIME_SRC_CLKGEN@GOTPAGEOFF]
Lloh20:
	ldr	x23, [x8]
	b	LBB0_13
LBB0_8:
Lloh21:
	adrp	x8, _TX_RETIME_SRC_CLKGEN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _TX_RETIME_SRC_CLKGEN@GOTPAGEOFF]
Lloh23:
	ldr	x23, [x8]
Lloh24:
	adrp	x8, _DWMAC_50MHZ@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DWMAC_50MHZ@GOTPAGEOFF]
Lloh26:
	ldr	x1, [x8]
	b	LBB0_12
LBB0_9:
Lloh27:
	adrp	x8, _TX_RETIME_SRC_CLKGEN@GOTPAGE
Lloh28:
	ldr	x8, [x8, _TX_RETIME_SRC_CLKGEN@GOTPAGEOFF]
Lloh29:
	ldr	x23, [x8]
Lloh30:
	adrp	x8, _SPEED_100@GOTPAGE
Lloh31:
	ldr	x8, [x8, _SPEED_100@GOTPAGEOFF]
Lloh32:
	ldr	x8, [x8]
	cmp	x8, x21
	b.ne	LBB0_11
; %bb.10:
Lloh33:
	adrp	x8, _DWMAC_25MHZ@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DWMAC_25MHZ@GOTPAGEOFF]
Lloh35:
	ldr	x1, [x8]
	b	LBB0_12
LBB0_11:
Lloh36:
	adrp	x8, _SPEED_10@GOTPAGE
Lloh37:
	ldr	x8, [x8, _SPEED_10@GOTPAGEOFF]
Lloh38:
	ldr	x8, [x8]
Lloh39:
	adrp	x9, _DWMAC_2_5MHZ@GOTPAGE
Lloh40:
	ldr	x9, [x9, _DWMAC_2_5MHZ@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	cmp	x8, x21
	csel	x1, x9, xzr, eq
LBB0_12:
	mov	x22, x23
LBB0_13:
	cmp	x22, x23
	ccmp	x1, #0, #4, eq
	b.eq	LBB0_15
; %bb.14:
	ldr	w0, [x20, #28]
	bl	_clk_set_rate
	mov	x22, x23
LBB0_15:
	ldr	w0, [x20, #24]
Lloh42:
	adrp	x8, _STIH4XX_RETIME_SRC_MASK@GOTPAGE
Lloh43:
	ldr	x8, [x8, _STIH4XX_RETIME_SRC_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w2, [x8]
Lloh45:
	adrp	x8, _stih4xx_tx_retime_val@GOTPAGE
Lloh46:
	ldr	x8, [x8, _stih4xx_tx_retime_val@GOTPAGEOFF]
Lloh47:
	ldr	x8, [x8]
	ldr	w3, [x8, x22, lsl #2]
	mov	x1, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_regmap_update_bits
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.cfi_endproc
                                        ; -- End function
	.comm	_PHY_INTERFACE_MODE_MII,8,3     ; @PHY_INTERFACE_MODE_MII
	.comm	_TX_RETIME_SRC_TXCLK,8,3        ; @TX_RETIME_SRC_TXCLK
	.comm	_PHY_INTERFACE_MODE_RMII,8,3    ; @PHY_INTERFACE_MODE_RMII
	.comm	_TX_RETIME_SRC_PHYCLK,8,3       ; @TX_RETIME_SRC_PHYCLK
	.comm	_TX_RETIME_SRC_CLKGEN,8,3       ; @TX_RETIME_SRC_CLKGEN
	.comm	_DWMAC_50MHZ,8,3                ; @DWMAC_50MHZ
	.comm	_SPEED_1000,8,3                 ; @SPEED_1000
	.comm	_DWMAC_125MHZ,8,3               ; @DWMAC_125MHZ
	.comm	_SPEED_100,8,3                  ; @SPEED_100
	.comm	_DWMAC_25MHZ,8,3                ; @DWMAC_25MHZ
	.comm	_SPEED_10,8,3                   ; @SPEED_10
	.comm	_DWMAC_2_5MHZ,8,3               ; @DWMAC_2_5MHZ
	.comm	_STIH4XX_RETIME_SRC_MASK,4,2    ; @STIH4XX_RETIME_SRC_MASK
	.comm	_stih4xx_tx_retime_val,8,3      ; @stih4xx_tx_retime_val
	.no_dead_strip	_stih4xx_fix_retime_src
.subsections_via_symbols
