	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pci_enable_atomic_ops_to_root  ## -- Begin function pci_enable_atomic_ops_to_root
	.p2align	4, 0x90
_pci_enable_atomic_ops_to_root:         ## @pci_enable_atomic_ops_to_root
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, -48(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r13
	movq	(%rdi), %r12
	callq	_pci_is_pcie
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	movq	%r13, %rdi
	callq	_pci_pcie_type
	addl	$-130, %eax
	cmpl	$2, %eax
	ja	LBB0_1
## %bb.3:
	cmpq	$0, (%r12)
	je	LBB0_13
## %bb.4:
	movq	_PCI_EXP_DEVCAP2@GOTPCREL(%rip), %r14
	leaq	-44(%rbp), %r15
	jmp	LBB0_5
	.p2align	4, 0x90
LBB0_12:                                ##   in Loop: Header=BB0_5 Depth=1
	movq	(%r12), %r12
	cmpq	$0, (%r12)
	je	LBB0_13
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r12), %rbx
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movq	%r15, %rdx
	callq	_pcie_capability_read_dword
	movq	%rbx, %rdi
	callq	_pci_pcie_type
	cmpl	$133, %eax
	je	LBB0_8
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	cmpl	$129, %eax
	je	LBB0_9
## %bb.7:                               ##   in Loop: Header=BB0_5 Depth=1
	cmpl	$128, %eax
	jne	LBB0_10
LBB0_8:                                 ##   in Loop: Header=BB0_5 Depth=1
	movq	_PCI_EXP_DEVCAP2_ATOMIC_ROUTE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_10
	jmp	LBB0_1
	.p2align	4, 0x90
LBB0_9:                                 ##   in Loop: Header=BB0_5 Depth=1
	movl	-44(%rbp), %eax
	notl	%eax
	testl	%eax, -48(%rbp)                 ## 4-byte Folded Reload
	jne	LBB0_1
LBB0_10:                                ##   in Loop: Header=BB0_5 Depth=1
	movq	%rbx, %rdi
	callq	_pci_pcie_type
	cmpl	$128, %eax
	jne	LBB0_12
## %bb.11:                              ##   in Loop: Header=BB0_5 Depth=1
	movq	_PCI_EXP_DEVCTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	leaq	-52(%rbp), %rdx
	callq	_pcie_capability_read_dword
	movq	_PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -52(%rbp)
	je	LBB0_12
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_14
LBB0_13:
	movq	_PCI_EXP_DEVCTL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCI_EXP_DEVCTL2_ATOMIC_REQ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_pcie_capability_set_word
	xorl	%eax, %eax
LBB0_14:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PCI_EXP_DEVCAP2,4,2            ## @PCI_EXP_DEVCAP2
	.comm	_PCI_EXP_DEVCAP2_ATOMIC_ROUTE,4,2 ## @PCI_EXP_DEVCAP2_ATOMIC_ROUTE
	.comm	_PCI_EXP_DEVCTL2,4,2            ## @PCI_EXP_DEVCTL2
	.comm	_PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK,4,2 ## @PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
	.comm	_PCI_EXP_DEVCTL2_ATOMIC_REQ,4,2 ## @PCI_EXP_DEVCTL2_ATOMIC_REQ
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pci_enable_atomic_ops_to_root  ; -- Begin function pci_enable_atomic_ops_to_root
	.p2align	2
_pci_enable_atomic_ops_to_root:         ; @pci_enable_atomic_ops_to_root
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x19, x0
	ldr	x22, [x0]
	bl	_pci_is_pcie
	cbz	w0, LBB0_12
; %bb.1:
	mov	x0, x19
	bl	_pci_pcie_type
	sub	w8, w0, #130
	cmp	w8, #2
	b.hi	LBB0_12
; %bb.2:
	ldr	x8, [x22]
Lloh0:
	adrp	x23, _PCI_EXP_DEVCTL2@GOTPAGE
Lloh1:
	ldr	x23, [x23, _PCI_EXP_DEVCTL2@GOTPAGEOFF]
	cbz	x8, LBB0_13
; %bb.3:
Lloh2:
	adrp	x24, _PCI_EXP_DEVCAP2@GOTPAGE
Lloh3:
	ldr	x24, [x24, _PCI_EXP_DEVCAP2@GOTPAGEOFF]
Lloh4:
	adrp	x25, _PCI_EXP_DEVCAP2_ATOMIC_ROUTE@GOTPAGE
Lloh5:
	ldr	x25, [x25, _PCI_EXP_DEVCAP2_ATOMIC_ROUTE@GOTPAGEOFF]
Lloh6:
	adrp	x26, _PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK@GOTPAGE
Lloh7:
	ldr	x26, [x26, _PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK@GOTPAGEOFF]
	b	LBB0_5
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	x22, [x22]
	ldr	x8, [x22]
	cbz	x8, LBB0_13
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x21, [x22, #8]
	ldr	w1, [x24]
	add	x2, sp, #12
	mov	x0, x21
	bl	_pcie_capability_read_dword
	mov	x0, x21
	bl	_pci_pcie_type
	cmp	w0, #133
	b.eq	LBB0_8
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	cmp	w0, #129
	b.eq	LBB0_9
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=1
	cmp	w0, #128
	b.ne	LBB0_10
LBB0_8:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [sp, #12]
	ldr	w9, [x25]
	tst	w9, w8
	b.ne	LBB0_10
	b	LBB0_12
LBB0_9:                                 ;   in Loop: Header=BB0_5 Depth=1
	ldr	w8, [sp, #12]
	bics	wzr, w20, w8
	b.ne	LBB0_12
LBB0_10:                                ;   in Loop: Header=BB0_5 Depth=1
	mov	x0, x21
	bl	_pci_pcie_type
	cmp	w0, #128
	b.ne	LBB0_4
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=1
	ldr	w1, [x23]
	add	x2, sp, #8
	mov	x0, x21
	bl	_pcie_capability_read_dword
	ldr	w8, [sp, #8]
	ldr	w9, [x26]
	tst	w9, w8
	b.eq	LBB0_4
LBB0_12:
Lloh8:
	adrp	x8, _EINVAL@GOTPAGE
Lloh9:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_14
LBB0_13:
	ldr	w1, [x23]
Lloh11:
	adrp	x8, _PCI_EXP_DEVCTL2_ATOMIC_REQ@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PCI_EXP_DEVCTL2_ATOMIC_REQ@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_pcie_capability_set_word
	mov	w0, #0
LBB0_14:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PCI_EXP_DEVCAP2,4,2            ; @PCI_EXP_DEVCAP2
	.comm	_PCI_EXP_DEVCAP2_ATOMIC_ROUTE,4,2 ; @PCI_EXP_DEVCAP2_ATOMIC_ROUTE
	.comm	_PCI_EXP_DEVCTL2,4,2            ; @PCI_EXP_DEVCTL2
	.comm	_PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK,4,2 ; @PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
	.comm	_PCI_EXP_DEVCTL2_ATOMIC_REQ,4,2 ; @PCI_EXP_DEVCTL2_ATOMIC_REQ
.subsections_via_symbols
