	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function v3_get_dma_range_config
_v3_get_dma_range_config:               ## @v3_get_dma_range_config
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rdi
	movl	8(%rsi), %r12d
	movq	_V3_PCI_BASE_M_ADR_BASE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %eax
	movl	%eax, %ebx
	notl	%ebx
	testl	%ebx, %r12d
	je	LBB0_3
## %bb.1:
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_2
LBB0_3:
	movl	4(%rsi), %r8d
	leal	-1(%r8), %r9d
	addl	(%rsi), %r9d
	andl	%r12d, %eax
	movl	%eax, (%rdx)
	movl	(%rsi), %r14d
	movq	_V3_PCI_MAP_M_MAP_ADR@GOTPCREL(%rip), %rax
	movl	(%rax), %r11d
	movl	%r11d, %eax
	notl	%eax
	testl	%eax, %r14d
	je	LBB0_5
## %bb.4:
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_2
LBB0_5:
	movl	4(%rsi), %r15d
	addl	$-128, %r15d
	cmpl	$12, %r15d
	jae	LBB0_6
## %bb.7:
	movslq	%r9d, %r10
	leal	(%r8,%r12), %eax
	decl	%eax
	movslq	%eax, %r9
	andl	%r14d, %r11d
	movslq	%r15d, %rax
	leaq	l_switch.table.v3_get_dma_range_config(%rip), %rbx
	movq	(%rbx,%rax,8), %rax
	movq	_V3_PCI_MAP_M_REG_EN@GOTPCREL(%rip), %rbx
	movq	_V3_PCI_MAP_M_ENABLE@GOTPCREL(%rip), %r8
	orl	(%rax), %r11d
	orl	(%rbx), %r11d
	orl	(%r8), %r11d
	movl	%r11d, (%rcx)
	movl	(%rsi), %ecx
	movl	8(%rsi), %r8d
	movl	(%rdx), %eax
	leaq	L_.str.3(%rip), %rsi
	movl	%ecx, %edx
	movq	%r10, %rcx
	pushq	%r11
	pushq	%rax
	callq	_dev_dbg
	addq	$16, %rsp
	xorl	%eax, %eax
	jmp	LBB0_8
LBB0_6:
	leaq	L_.str.2(%rip), %rsi
LBB0_2:
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_8:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_V3_PCI_BASE_M_ADR_BASE,4,2     ## @V3_PCI_BASE_M_ADR_BASE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"illegal range, only PCI bits 31..20 allowed\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_V3_PCI_MAP_M_MAP_ADR,4,2       ## @V3_PCI_MAP_M_MAP_ADR
L_.str.1:                               ## @.str.1
	.asciz	"illegal range, only CPU bits 31..20 allowed\n"

	.comm	_V3_LB_BASE_ADR_SIZE_1MB,4,2    ## @V3_LB_BASE_ADR_SIZE_1MB
	.comm	_V3_LB_BASE_ADR_SIZE_2MB,4,2    ## @V3_LB_BASE_ADR_SIZE_2MB
	.comm	_V3_LB_BASE_ADR_SIZE_4MB,4,2    ## @V3_LB_BASE_ADR_SIZE_4MB
	.comm	_V3_LB_BASE_ADR_SIZE_8MB,4,2    ## @V3_LB_BASE_ADR_SIZE_8MB
	.comm	_V3_LB_BASE_ADR_SIZE_16MB,4,2   ## @V3_LB_BASE_ADR_SIZE_16MB
	.comm	_V3_LB_BASE_ADR_SIZE_32MB,4,2   ## @V3_LB_BASE_ADR_SIZE_32MB
	.comm	_V3_LB_BASE_ADR_SIZE_64MB,4,2   ## @V3_LB_BASE_ADR_SIZE_64MB
	.comm	_V3_LB_BASE_ADR_SIZE_128MB,4,2  ## @V3_LB_BASE_ADR_SIZE_128MB
	.comm	_V3_LB_BASE_ADR_SIZE_256MB,4,2  ## @V3_LB_BASE_ADR_SIZE_256MB
	.comm	_V3_LB_BASE_ADR_SIZE_512MB,4,2  ## @V3_LB_BASE_ADR_SIZE_512MB
	.comm	_V3_LB_BASE_ADR_SIZE_1GB,4,2    ## @V3_LB_BASE_ADR_SIZE_1GB
	.comm	_V3_LB_BASE_ADR_SIZE_2GB,4,2    ## @V3_LB_BASE_ADR_SIZE_2GB
L_.str.2:                               ## @.str.2
	.asciz	"illegal dma memory chunk size\n"

	.comm	_V3_PCI_MAP_M_REG_EN,4,2        ## @V3_PCI_MAP_M_REG_EN
	.comm	_V3_PCI_MAP_M_ENABLE,4,2        ## @V3_PCI_MAP_M_ENABLE
L_.str.3:                               ## @.str.3
	.asciz	"DMA MEM CPU: 0x%016llx -> 0x%016llx => PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n"

	.no_dead_strip	_v3_get_dma_range_config
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.v3_get_dma_range_config
l_switch.table.v3_get_dma_range_config:
	.quad	_V3_LB_BASE_ADR_SIZE_8MB
	.quad	_V3_LB_BASE_ADR_SIZE_64MB
	.quad	_V3_LB_BASE_ADR_SIZE_512MB
	.quad	_V3_LB_BASE_ADR_SIZE_4MB
	.quad	_V3_LB_BASE_ADR_SIZE_32MB
	.quad	_V3_LB_BASE_ADR_SIZE_2MB
	.quad	_V3_LB_BASE_ADR_SIZE_2GB
	.quad	_V3_LB_BASE_ADR_SIZE_256MB
	.quad	_V3_LB_BASE_ADR_SIZE_1MB
	.quad	_V3_LB_BASE_ADR_SIZE_1GB
	.quad	_V3_LB_BASE_ADR_SIZE_16MB
	.quad	_V3_LB_BASE_ADR_SIZE_128MB

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function v3_get_dma_range_config
_v3_get_dma_range_config:               ; @v3_get_dma_range_config
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	ldr	x0, [x0]
	ldr	w9, [x1, #8]
Lloh0:
	adrp	x8, _V3_PCI_BASE_M_ADR_BASE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _V3_PCI_BASE_M_ADR_BASE@GOTPAGEOFF]
Lloh2:
	ldr	w10, [x8]
	bics	wzr, w9, w10
	b.eq	LBB0_2
; %bb.1:
Lloh3:
	adrp	x1, l_.str@PAGE
Lloh4:
	add	x1, x1, l_.str@PAGEOFF
	b	LBB0_7
LBB0_2:
	ldp	w8, w12, [x1]
	and	w10, w10, w9
	str	w10, [x2]
	ldr	w10, [x1]
Lloh5:
	adrp	x11, _V3_PCI_MAP_M_MAP_ADR@GOTPAGE
Lloh6:
	ldr	x11, [x11, _V3_PCI_MAP_M_MAP_ADR@GOTPAGEOFF]
Lloh7:
	ldr	w11, [x11]
	bics	wzr, w10, w11
	b.eq	LBB0_4
; %bb.3:
Lloh8:
	adrp	x1, l_.str.1@PAGE
Lloh9:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_7
LBB0_4:
	ldr	w13, [x1, #4]
	sub	w13, w13, #128
	cmp	w13, #12
	b.hs	LBB0_6
; %bb.5:
	sub	w12, w12, #1
	add	w8, w12, w8
	sxtw	x8, w8
	add	w9, w12, w9
	sxtw	x5, w9
	and	w9, w11, w10
Lloh10:
	adrp	x10, l_switch.table.v3_get_dma_range_config@PAGE
Lloh11:
	add	x10, x10, l_switch.table.v3_get_dma_range_config@PAGEOFF
	ldr	x10, [x10, w13, sxtw #3]
Lloh12:
	adrp	x11, _V3_PCI_MAP_M_REG_EN@GOTPAGE
Lloh13:
	ldr	x11, [x11, _V3_PCI_MAP_M_REG_EN@GOTPAGEOFF]
	ldr	w10, [x10]
Lloh14:
	ldr	w11, [x11]
Lloh15:
	adrp	x12, _V3_PCI_MAP_M_ENABLE@GOTPAGE
Lloh16:
	ldr	x12, [x12, _V3_PCI_MAP_M_ENABLE@GOTPAGEOFF]
Lloh17:
	ldr	w12, [x12]
	orr	w9, w10, w9
	orr	w9, w9, w11
	orr	w7, w9, w12
	str	w7, [x3]
	ldr	w9, [x1]
	ldr	w4, [x1, #8]
	ldr	w6, [x2]
Lloh18:
	adrp	x1, l_.str.3@PAGE
Lloh19:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x2, x9
	mov	x3, x8
	bl	_dev_dbg
	mov	w0, #0
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
LBB0_6:
Lloh20:
	adrp	x1, l_.str.2@PAGE
Lloh21:
	add	x1, x1, l_.str.2@PAGEOFF
LBB0_7:
	bl	_dev_err
Lloh22:
	adrp	x8, _EINVAL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	neg	w0, w8
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_V3_PCI_BASE_M_ADR_BASE,4,2     ; @V3_PCI_BASE_M_ADR_BASE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"illegal range, only PCI bits 31..20 allowed\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_V3_PCI_MAP_M_MAP_ADR,4,2       ; @V3_PCI_MAP_M_MAP_ADR
l_.str.1:                               ; @.str.1
	.asciz	"illegal range, only CPU bits 31..20 allowed\n"

	.comm	_V3_LB_BASE_ADR_SIZE_1MB,4,2    ; @V3_LB_BASE_ADR_SIZE_1MB
	.comm	_V3_LB_BASE_ADR_SIZE_2MB,4,2    ; @V3_LB_BASE_ADR_SIZE_2MB
	.comm	_V3_LB_BASE_ADR_SIZE_4MB,4,2    ; @V3_LB_BASE_ADR_SIZE_4MB
	.comm	_V3_LB_BASE_ADR_SIZE_8MB,4,2    ; @V3_LB_BASE_ADR_SIZE_8MB
	.comm	_V3_LB_BASE_ADR_SIZE_16MB,4,2   ; @V3_LB_BASE_ADR_SIZE_16MB
	.comm	_V3_LB_BASE_ADR_SIZE_32MB,4,2   ; @V3_LB_BASE_ADR_SIZE_32MB
	.comm	_V3_LB_BASE_ADR_SIZE_64MB,4,2   ; @V3_LB_BASE_ADR_SIZE_64MB
	.comm	_V3_LB_BASE_ADR_SIZE_128MB,4,2  ; @V3_LB_BASE_ADR_SIZE_128MB
	.comm	_V3_LB_BASE_ADR_SIZE_256MB,4,2  ; @V3_LB_BASE_ADR_SIZE_256MB
	.comm	_V3_LB_BASE_ADR_SIZE_512MB,4,2  ; @V3_LB_BASE_ADR_SIZE_512MB
	.comm	_V3_LB_BASE_ADR_SIZE_1GB,4,2    ; @V3_LB_BASE_ADR_SIZE_1GB
	.comm	_V3_LB_BASE_ADR_SIZE_2GB,4,2    ; @V3_LB_BASE_ADR_SIZE_2GB
l_.str.2:                               ; @.str.2
	.asciz	"illegal dma memory chunk size\n"

	.comm	_V3_PCI_MAP_M_REG_EN,4,2        ; @V3_PCI_MAP_M_REG_EN
	.comm	_V3_PCI_MAP_M_ENABLE,4,2        ; @V3_PCI_MAP_M_ENABLE
l_.str.3:                               ; @.str.3
	.asciz	"DMA MEM CPU: 0x%016llx -> 0x%016llx => PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n"

	.no_dead_strip	_v3_get_dma_range_config
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.v3_get_dma_range_config
l_switch.table.v3_get_dma_range_config:
	.quad	_V3_LB_BASE_ADR_SIZE_8MB
	.quad	_V3_LB_BASE_ADR_SIZE_64MB
	.quad	_V3_LB_BASE_ADR_SIZE_512MB
	.quad	_V3_LB_BASE_ADR_SIZE_4MB
	.quad	_V3_LB_BASE_ADR_SIZE_32MB
	.quad	_V3_LB_BASE_ADR_SIZE_2MB
	.quad	_V3_LB_BASE_ADR_SIZE_2GB
	.quad	_V3_LB_BASE_ADR_SIZE_256MB
	.quad	_V3_LB_BASE_ADR_SIZE_1MB
	.quad	_V3_LB_BASE_ADR_SIZE_1GB
	.quad	_V3_LB_BASE_ADR_SIZE_16MB
	.quad	_V3_LB_BASE_ADR_SIZE_128MB

.subsections_via_symbols
