	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_dw_host_init
_tegra_pcie_dw_host_init:               ## @tegra_pcie_dw_host_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_to_dw_pcie_from_pp
	movq	%rax, %r12
	movq	%rax, %rdi
	callq	_to_tegra_pcie
	movq	%rax, %r15
	movq	%r14, %rdi
	callq	_tegra_pcie_prepare_host
	movq	%r12, %rdi
	callq	_dw_pcie_wait_for_link
	testq	%rax, %rax
	je	LBB0_4
## %bb.1:
	movq	_APPL_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movl	%eax, %ebx
	movq	_APPL_DEBUG_LTSSM_STATE_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	movq	_APPL_DEBUG_LTSSM_STATE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	sarl	%cl, %ebx
	movq	_APPL_LINK_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	cmpl	$17, %ebx
	jne	LBB0_5
## %bb.2:
	movq	_APPL_LINK_STATUS_RDLH_LINK_UP@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	jne	LBB0_5
## %bb.3:
	movl	(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_info
	movl	(%r12), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_info
	movq	_APPL_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movq	_APPL_CTRL_LTSSM_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_appl_writel
	movl	16(%r15), %edi
	callq	_reset_control_assert
	movl	16(%r15), %edi
	callq	_reset_control_deassert
	movq	_PCI_EXT_CAP_ID_DLF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_dw_pcie_find_ext_capability
	movl	%eax, %ebx
	movq	_PCI_DLF_CAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	addl	%ebx, %esi
	movq	%r12, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PCI_DLF_EXCHANGE_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_dw_pcie_writel_dbi
	movq	%r14, %rdi
	callq	_tegra_pcie_prepare_host
	movq	%r12, %rdi
	callq	_dw_pcie_wait_for_link
	testq	%rax, %rax
	jne	LBB0_5
LBB0_4:
	movq	_PCI_EXP_LNKSTA@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r15), %rsi
	movq	%r12, %rdi
	callq	_dw_pcie_readw_dbi
	movq	_PCI_EXP_LNKSTA_CLS@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	cltq
	movl	(%r15), %edi
	movq	_pcie_gen_freq@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	-4(%rcx,%rax,4), %esi
	callq	_clk_set_rate
	movq	%r14, %rdi
	callq	_tegra_pcie_enable_interrupts
LBB0_5:
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_APPL_DEBUG,4,2                 ## @APPL_DEBUG
	.comm	_APPL_DEBUG_LTSSM_STATE_MASK,4,2 ## @APPL_DEBUG_LTSSM_STATE_MASK
	.comm	_APPL_DEBUG_LTSSM_STATE_SHIFT,4,2 ## @APPL_DEBUG_LTSSM_STATE_SHIFT
	.comm	_APPL_LINK_STATUS,4,2           ## @APPL_LINK_STATUS
	.comm	_APPL_LINK_STATUS_RDLH_LINK_UP,4,2 ## @APPL_LINK_STATUS_RDLH_LINK_UP
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Link is down in DLL"

L_.str.1:                               ## @.str.1
	.asciz	"Trying again with DLFE disabled\n"

	.comm	_APPL_CTRL,4,2                  ## @APPL_CTRL
	.comm	_APPL_CTRL_LTSSM_EN,4,2         ## @APPL_CTRL_LTSSM_EN
	.comm	_PCI_EXT_CAP_ID_DLF,4,2         ## @PCI_EXT_CAP_ID_DLF
	.comm	_PCI_DLF_CAP,4,2                ## @PCI_DLF_CAP
	.comm	_PCI_DLF_EXCHANGE_ENABLE,4,2    ## @PCI_DLF_EXCHANGE_ENABLE
	.comm	_PCI_EXP_LNKSTA,8,3             ## @PCI_EXP_LNKSTA
	.comm	_PCI_EXP_LNKSTA_CLS,4,2         ## @PCI_EXP_LNKSTA_CLS
	.comm	_pcie_gen_freq,8,3              ## @pcie_gen_freq
	.no_dead_strip	_tegra_pcie_dw_host_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_dw_host_init
_tegra_pcie_dw_host_init:               ; @tegra_pcie_dw_host_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_to_dw_pcie_from_pp
	mov	x21, x0
	bl	_to_tegra_pcie
	mov	x20, x0
	mov	x0, x19
	bl	_tegra_pcie_prepare_host
	mov	x0, x21
	bl	_dw_pcie_wait_for_link
	cbz	x0, LBB0_3
; %bb.1:
Lloh0:
	adrp	x8, _APPL_DEBUG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _APPL_DEBUG@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_appl_readl
Lloh3:
	adrp	x8, _APPL_DEBUG_LTSSM_STATE_MASK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _APPL_DEBUG_LTSSM_STATE_MASK@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
Lloh6:
	adrp	x9, _APPL_DEBUG_LTSSM_STATE_SHIFT@GOTPAGE
Lloh7:
	ldr	x9, [x9, _APPL_DEBUG_LTSSM_STATE_SHIFT@GOTPAGEOFF]
	and	w8, w8, w0
Lloh8:
	ldr	w9, [x9]
	asr	w22, w8, w9
Lloh9:
	adrp	x8, _APPL_LINK_STATUS@GOTPAGE
Lloh10:
	ldr	x8, [x8, _APPL_LINK_STATUS@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_appl_readl
Lloh12:
	adrp	x8, _APPL_LINK_STATUS_RDLH_LINK_UP@GOTPAGE
Lloh13:
	ldr	x8, [x8, _APPL_LINK_STATUS_RDLH_LINK_UP@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	and	w8, w8, w0
	cmp	w22, #17
	ccmp	w8, #0, #0, eq
	b.ne	LBB0_4
; %bb.2:
	ldr	w0, [x21]
Lloh15:
	adrp	x1, l_.str@PAGE
Lloh16:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_info
	ldr	w0, [x21]
Lloh17:
	adrp	x1, l_.str.1@PAGE
Lloh18:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_info
Lloh19:
	adrp	x22, _APPL_CTRL@GOTPAGE
Lloh20:
	ldr	x22, [x22, _APPL_CTRL@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_appl_readl
Lloh21:
	adrp	x8, _APPL_CTRL_LTSSM_EN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _APPL_CTRL_LTSSM_EN@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	bic	w1, w0, w8
	ldr	w2, [x22]
	mov	x0, x20
	bl	_appl_writel
	ldr	w0, [x20, #16]
	bl	_reset_control_assert
	ldr	w0, [x20, #16]
	bl	_reset_control_deassert
Lloh24:
	adrp	x8, _PCI_EXT_CAP_ID_DLF@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PCI_EXT_CAP_ID_DLF@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_dw_pcie_find_ext_capability
	mov	x22, x0
Lloh27:
	adrp	x8, _PCI_DLF_CAP@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PCI_DLF_CAP@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	add	w1, w8, w0
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh30:
	adrp	x8, _PCI_DLF_EXCHANGE_ENABLE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PCI_DLF_EXCHANGE_ENABLE@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x21
	mov	x1, x22
	bl	_dw_pcie_writel_dbi
	mov	x0, x19
	bl	_tegra_pcie_prepare_host
	mov	x0, x21
	bl	_dw_pcie_wait_for_link
	cbnz	x0, LBB0_4
LBB0_3:
	ldr	x8, [x20, #8]
Lloh33:
	adrp	x9, _PCI_EXP_LNKSTA@GOTPAGE
Lloh34:
	ldr	x9, [x9, _PCI_EXP_LNKSTA@GOTPAGEOFF]
Lloh35:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x21
	bl	_dw_pcie_readw_dbi
Lloh36:
	adrp	x8, _PCI_EXP_LNKSTA_CLS@GOTPAGE
Lloh37:
	ldr	x8, [x8, _PCI_EXP_LNKSTA_CLS@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	and	w8, w8, w0
	ldr	w0, [x20]
Lloh39:
	adrp	x9, _pcie_gen_freq@GOTPAGE
Lloh40:
	ldr	x9, [x9, _pcie_gen_freq@GOTPAGEOFF]
Lloh41:
	ldr	x9, [x9]
	sub	w8, w8, #1
	ldr	w1, [x9, w8, sxtw #2]
	bl	_clk_set_rate
	mov	x0, x19
	bl	_tegra_pcie_enable_interrupts
LBB0_4:
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.cfi_endproc
                                        ; -- End function
	.comm	_APPL_DEBUG,4,2                 ; @APPL_DEBUG
	.comm	_APPL_DEBUG_LTSSM_STATE_MASK,4,2 ; @APPL_DEBUG_LTSSM_STATE_MASK
	.comm	_APPL_DEBUG_LTSSM_STATE_SHIFT,4,2 ; @APPL_DEBUG_LTSSM_STATE_SHIFT
	.comm	_APPL_LINK_STATUS,4,2           ; @APPL_LINK_STATUS
	.comm	_APPL_LINK_STATUS_RDLH_LINK_UP,4,2 ; @APPL_LINK_STATUS_RDLH_LINK_UP
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Link is down in DLL"

l_.str.1:                               ; @.str.1
	.asciz	"Trying again with DLFE disabled\n"

	.comm	_APPL_CTRL,4,2                  ; @APPL_CTRL
	.comm	_APPL_CTRL_LTSSM_EN,4,2         ; @APPL_CTRL_LTSSM_EN
	.comm	_PCI_EXT_CAP_ID_DLF,4,2         ; @PCI_EXT_CAP_ID_DLF
	.comm	_PCI_DLF_CAP,4,2                ; @PCI_DLF_CAP
	.comm	_PCI_DLF_EXCHANGE_ENABLE,4,2    ; @PCI_DLF_EXCHANGE_ENABLE
	.comm	_PCI_EXP_LNKSTA,8,3             ; @PCI_EXP_LNKSTA
	.comm	_PCI_EXP_LNKSTA_CLS,4,2         ; @PCI_EXP_LNKSTA_CLS
	.comm	_pcie_gen_freq,8,3              ; @pcie_gen_freq
	.no_dead_strip	_tegra_pcie_dw_host_init
.subsections_via_symbols
