	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function imx6_pcie_establish_link
_imx6_pcie_establish_link:              ## @imx6_pcie_establish_link
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	movq	16(%rdi), %rbx
	movq	(%rbx), %r15
	movq	_PCIE_RC_LCR@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	%r15, %rdi
	callq	_imx6_pcie_ltssm_enable
	movq	%rbx, %rdi
	callq	_dw_pcie_wait_for_link
	movl	%eax, %r12d
	testl	%eax, %eax
	je	LBB0_1
LBB0_6:
	movq	_PCIE_PORT_DEBUG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movl	%eax, %r13d
	movq	_PCIE_PORT_DEBUG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	leaq	L_.str.3(%rip), %rsi
	movq	%r15, %rdi
	movl	%r13d, %edx
	movl	%eax, %ecx
	callq	_dev_dbg
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_imx6_pcie_reset_phy
	jmp	LBB0_9
LBB0_1:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	cmpl	$2, (%rax)
	jne	LBB0_7
## %bb.2:
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movl	(%r13), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PORT_LOGIC_SPEED_CHANGE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r12), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	movq	8(%rdi), %rax
	movq	_IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	testl	%ecx, (%rax)
	je	LBB0_4
## %bb.3:
	callq	_imx6_pcie_wait_for_speed_change
	movl	%eax, %r12d
	testl	%eax, %eax
	jne	LBB0_5
LBB0_4:
	movq	%rbx, %rdi
	callq	_dw_pcie_wait_for_link
	movl	%eax, %r12d
	testl	%eax, %eax
	je	LBB0_8
LBB0_5:
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	callq	_dev_err
	jmp	LBB0_6
LBB0_7:
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_dev_info
LBB0_8:
	movq	_PCIE_RC_LCSR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	shrl	$16, %eax
	andl	$15, %eax
	leaq	L_.str.2(%rip), %rsi
	xorl	%r12d, %r12d
	movq	%r15, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_info
LBB0_9:
	movl	%r12d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_RC_LCR,4,2                ## @PCIE_RC_LCR
	.comm	_PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK,4,2 ## @PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
	.comm	_PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1,4,2 ## @PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1
	.comm	_PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2,4,2 ## @PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2
	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,4,2 ## @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_PORT_LOGIC_SPEED_CHANGE,4,2    ## @PORT_LOGIC_SPEED_CHANGE
	.comm	_IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,4,2 ## @IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to bring link up!\n"

L_.str.1:                               ## @.str.1
	.asciz	"Link: Gen2 disabled\n"

	.comm	_PCIE_RC_LCSR,4,2               ## @PCIE_RC_LCSR
L_.str.2:                               ## @.str.2
	.asciz	"Link up, Gen%i\n"

L_.str.3:                               ## @.str.3
	.asciz	"PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n"

	.comm	_PCIE_PORT_DEBUG0,4,2           ## @PCIE_PORT_DEBUG0
	.comm	_PCIE_PORT_DEBUG1,4,2           ## @PCIE_PORT_DEBUG1
	.no_dead_strip	_imx6_pcie_establish_link
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function imx6_pcie_establish_link
_imx6_pcie_establish_link:              ; @imx6_pcie_establish_link
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	ldr	x21, [x0, #16]
	ldr	x19, [x21]
Lloh0:
	adrp	x23, _PCIE_RC_LCR@GOTPAGE
Lloh1:
	ldr	x23, [x23, _PCIE_RC_LCR@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh2:
	adrp	x24, _PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK@GOTPAGE
Lloh3:
	ldr	x24, [x24, _PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK@GOTPAGEOFF]
	ldr	w8, [x24]
	bic	w8, w0, w8
Lloh4:
	adrp	x9, _PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1@GOTPAGE
Lloh5:
	ldr	x9, [x9, _PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1@GOTPAGEOFF]
Lloh6:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	w1, [x23]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
	mov	x0, x19
	bl	_imx6_pcie_ltssm_enable
	mov	x0, x21
	bl	_dw_pcie_wait_for_link
	mov	x22, x0
	cbz	w0, LBB0_2
LBB0_1:
Lloh7:
	adrp	x8, _PCIE_PORT_DEBUG0@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PCIE_PORT_DEBUG0@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
	mov	x23, x0
Lloh10:
	adrp	x8, _PCIE_PORT_DEBUG1@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PCIE_PORT_DEBUG1@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
	mov	x3, x0
Lloh13:
	adrp	x1, l_.str.3@PAGE
Lloh14:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	mov	x2, x23
	bl	_dev_dbg
	mov	x0, x20
	bl	_imx6_pcie_reset_phy
	b	LBB0_9
LBB0_2:
	ldr	w8, [x20]
	cmp	w8, #2
	b.ne	LBB0_7
; %bb.3:
	ldr	w1, [x23]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
	ldr	w8, [x24]
	bic	w8, w0, w8
Lloh15:
	adrp	x9, _PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2@GOTPAGE
Lloh16:
	ldr	x9, [x9, _PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	w1, [x23]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
Lloh18:
	adrp	x22, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGE
Lloh19:
	ldr	x22, [x22, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh20:
	adrp	x8, _PORT_LOGIC_SPEED_CHANGE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _PORT_LOGIC_SPEED_CHANGE@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
	ldr	x8, [x20, #8]
	ldr	w8, [x8]
Lloh23:
	adrp	x9, _IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE@GOTPAGE
Lloh24:
	ldr	x9, [x9, _IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_5
; %bb.4:
	mov	x0, x20
	bl	_imx6_pcie_wait_for_speed_change
	mov	x22, x0
	cbnz	w0, LBB0_6
LBB0_5:
	mov	x0, x21
	bl	_dw_pcie_wait_for_link
	mov	x22, x0
	cbz	w0, LBB0_8
LBB0_6:
Lloh26:
	adrp	x1, l_.str@PAGE
Lloh27:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dev_err
	b	LBB0_1
LBB0_7:
Lloh28:
	adrp	x1, l_.str.1@PAGE
Lloh29:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_dev_info
LBB0_8:
Lloh30:
	adrp	x8, _PCIE_RC_LCSR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PCIE_RC_LCSR@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
	ubfx	w8, w0, #16, #4
	str	x8, [sp]
Lloh33:
	adrp	x1, l_.str.2@PAGE
Lloh34:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_dev_info
	mov	w22, #0
LBB0_9:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_RC_LCR,4,2                ; @PCIE_RC_LCR
	.comm	_PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK,4,2 ; @PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
	.comm	_PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1,4,2 ; @PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1
	.comm	_PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2,4,2 ; @PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2
	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,4,2 ; @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_PORT_LOGIC_SPEED_CHANGE,4,2    ; @PORT_LOGIC_SPEED_CHANGE
	.comm	_IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,4,2 ; @IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to bring link up!\n"

l_.str.1:                               ; @.str.1
	.asciz	"Link: Gen2 disabled\n"

	.comm	_PCIE_RC_LCSR,4,2               ; @PCIE_RC_LCSR
l_.str.2:                               ; @.str.2
	.asciz	"Link up, Gen%i\n"

l_.str.3:                               ; @.str.3
	.asciz	"PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n"

	.comm	_PCIE_PORT_DEBUG0,4,2           ; @PCIE_PORT_DEBUG0
	.comm	_PCIE_PORT_DEBUG1,4,2           ; @PCIE_PORT_DEBUG1
	.no_dead_strip	_imx6_pcie_establish_link
.subsections_via_symbols
