	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function print_hw_id
_print_hw_id:                           ## @print_hw_id
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_pci_get_drvdata
	movq	%rax, %r15
	movl	$0, -48(%rbp)
	movl	$0, -44(%rbp)
	movq	_PCI_LINK_STATUS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-48(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_pci_read_config_word
	movq	_PCI_DEV_CTRL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-44(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_pci_read_config_word
	movq	_BDX_NIC_NAME@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	cmpl	$1, (%r15)
	leaq	L_.str.1(%rip), %rax
	leaq	L_.str.2(%rip), %rdx
	cmoveq	%rax, %rdx
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_info
	movq	_SROM_VER@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	8(%r15), %rdi
	callq	_readl
	movl	%eax, %r14d
	movq	_FPGA_VER@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	8(%r15), %rdi
	callq	_readl
	movl	%eax, %ebx
	andl	$4095, %ebx                     ## imm = 0xFFF
	movq	_FPGA_SEED@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	addq	8(%r15), %rdi
	callq	_readl
	movl	%eax, %r15d
	movl	-48(%rbp), %edi
	callq	_GET_LINK_STATUS_LANES
	movl	%eax, %r12d
	movl	-44(%rbp), %edi
	callq	_GET_DEV_CTRL_MAXPL
	movl	%eax, %r13d
	movl	-44(%rbp), %edi
	callq	_GET_DEV_CTRL_MRRS
	movl	%eax, (%rsp)
	leaq	L_.str.3(%rip), %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movl	%r15d, %ecx
	movl	%r12d, %r8d
	movl	%r13d, %r9d
	xorl	%eax, %eax
	callq	_pr_info
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_LINK_STATUS_REG,4,2        ## @PCI_LINK_STATUS_REG
	.comm	_PCI_DEV_CTRL_REG,4,2           ## @PCI_DEV_CTRL_REG
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s%s\n"

	.comm	_BDX_NIC_NAME,4,2               ## @BDX_NIC_NAME
L_.str.1:                               ## @.str.1
	.space	1

L_.str.2:                               ## @.str.2
	.asciz	", 2-Port"

L_.str.3:                               ## @.str.3
	.asciz	"srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n"

	.comm	_SROM_VER,8,3                   ## @SROM_VER
	.comm	_FPGA_VER,8,3                   ## @FPGA_VER
	.comm	_FPGA_SEED,8,3                  ## @FPGA_SEED
	.no_dead_strip	_print_hw_id
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function print_hw_id
_print_hw_id:                           ; @print_hw_id
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_pci_get_drvdata
	mov	x20, x0
	str	xzr, [sp, #40]
Lloh0:
	adrp	x8, _PCI_LINK_STATUS_REG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_LINK_STATUS_REG@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x2, sp, #44
	mov	x0, x19
	bl	_pci_read_config_word
Lloh3:
	adrp	x8, _PCI_DEV_CTRL_REG@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_DEV_CTRL_REG@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x2, sp, #40
	mov	x0, x19
	bl	_pci_read_config_word
Lloh6:
	adrp	x8, _BDX_NIC_NAME@GOTPAGE
Lloh7:
	ldr	x8, [x8, _BDX_NIC_NAME@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	ldr	w8, [x20]
Lloh9:
	adrp	x9, l_.str.2@PAGE
Lloh10:
	add	x9, x9, l_.str.2@PAGEOFF
Lloh11:
	adrp	x10, l_.str.1@PAGE
Lloh12:
	add	x10, x10, l_.str.1@PAGEOFF
	cmp	w8, #1
	csel	x8, x10, x9, eq
	str	x8, [sp]
Lloh13:
	adrp	x0, l_.str@PAGE
Lloh14:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_info
	ldr	x8, [x20, #8]
Lloh15:
	adrp	x9, _SROM_VER@GOTPAGE
Lloh16:
	ldr	x9, [x9, _SROM_VER@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_readl
	mov	x19, x0
	ldr	x8, [x20, #8]
Lloh18:
	adrp	x9, _FPGA_VER@GOTPAGE
Lloh19:
	ldr	x9, [x9, _FPGA_VER@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_readl
	and	w23, w0, #0xfff
	ldr	x8, [x20, #8]
Lloh21:
	adrp	x9, _FPGA_SEED@GOTPAGE
Lloh22:
	ldr	x9, [x9, _FPGA_SEED@GOTPAGEOFF]
Lloh23:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_readl
	mov	x20, x0
	ldr	w0, [sp, #44]
	bl	_GET_LINK_STATUS_LANES
	mov	x21, x0
	ldr	w0, [sp, #40]
	bl	_GET_DEV_CTRL_MAXPL
	mov	x22, x0
	ldr	w0, [sp, #40]
	bl	_GET_DEV_CTRL_MRRS
                                        ; kill: def $w0 killed $w0 def $x0
	stp	x22, x0, [sp, #24]
	stp	x20, x21, [sp, #8]
	str	x23, [sp]
Lloh24:
	adrp	x0, l_.str.3@PAGE
Lloh25:
	add	x0, x0, l_.str.3@PAGEOFF
	mov	x1, x19
	bl	_pr_info
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_LINK_STATUS_REG,4,2        ; @PCI_LINK_STATUS_REG
	.comm	_PCI_DEV_CTRL_REG,4,2           ; @PCI_DEV_CTRL_REG
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s%s\n"

	.comm	_BDX_NIC_NAME,4,2               ; @BDX_NIC_NAME
l_.str.1:                               ; @.str.1
	.space	1

l_.str.2:                               ; @.str.2
	.asciz	", 2-Port"

l_.str.3:                               ; @.str.3
	.asciz	"srom 0x%x fpga %d build %u lane# %d max_pl 0x%x mrrs 0x%x\n"

	.comm	_SROM_VER,8,3                   ; @SROM_VER
	.comm	_FPGA_VER,8,3                   ; @FPGA_VER
	.comm	_FPGA_SEED,8,3                  ; @FPGA_SEED
	.no_dead_strip	_print_hw_id
.subsections_via_symbols
