	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iproc_pcie_check_link
_iproc_pcie_check_link:                 ## @iproc_pcie_check_link
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	xorl	%r15d, %r15d
	cmpq	$0, (%rdi)
	jne	LBB0_12
## %bb.1:
	movq	%rdi, %rbx
	movq	8(%rdi), %r14
	movq	_IPROC_PCIE_LINK_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_iproc_pcie_read_reg
	movq	_PCIE_PHYLINKUP@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
## %bb.2:
	movq	_PCIE_DL_ACTIVE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_3
## %bb.4:
	movq	_PCI_HEADER_TYPE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	xorl	%r15d, %r15d
	leaq	-56(%rbp), %r8
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$1, %ecx
	callq	_iproc_pci_raw_config_read32
	movl	-56(%rbp), %edx
	movl	%edx, %eax
	andl	$127, %eax
	movq	_PCI_HEADER_TYPE_BRIDGE@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_5
## %bb.6:
	xorl	%r15d, %r15d
	leaq	-48(%rbp), %r8
	movl	$1084, %edx                     ## imm = 0x43C
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$4, %ecx
	callq	_iproc_pci_raw_config_read32
	movl	$-16776961, %eax                ## imm = 0xFF0000FF
	andl	-48(%rbp), %eax
	movq	_PCI_CLASS_BRIDGE_PCI@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r8d
	shll	$8, %r8d
	orl	%eax, %r8d
	movl	%r8d, -48(%rbp)
	movl	$1084, %edx                     ## imm = 0x43C
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$4, %ecx
	callq	_iproc_pci_raw_config_write32
	movq	_IPROC_PCI_EXP_CAP@GOTPCREL(%rip), %r13
	movq	_PCI_EXP_LNKSTA@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	(%r13), %rdx
	leaq	-44(%rbp), %r8
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$2, %ecx
	callq	_iproc_pci_raw_config_read32
	movq	_PCI_EXP_LNKSTA_NLW@GOTPCREL(%rip), %r12
	movl	(%r12), %eax
	testl	%eax, -44(%rbp)
	je	LBB0_7
LBB0_9:
	leaq	L_.str.2(%rip), %rsi
	leaq	L_.str.3(%rip), %rdx
	movq	%r14, %rdi
	callq	_dev_info
	jmp	LBB0_12
LBB0_3:
	leaq	L_.str(%rip), %rsi
	xorl	%r15d, %r15d
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movq	_ENODEV@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_5:
	leaq	L_.str.1(%rip), %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	callq	_dev_err
	movq	_EFAULT@GOTPCREL(%rip), %rax
LBB0_11:
	subl	(%rax), %r15d
LBB0_12:
	movl	%r15d, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_7:
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	(%r13), %rdx
	leaq	-52(%rbp), %r8
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$4, %ecx
	callq	_iproc_pci_raw_config_read32
	movl	-52(%rbp), %r8d
	movl	%r8d, %eax
	andl	$15, %eax
	cmpl	$2, %eax
	jne	LBB0_10
## %bb.8:
	andl	$-16, %r8d
	orl	$1, %r8d
	movl	%r8d, -52(%rbp)
	movq	_PCI_EXP_LNKCTL2@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	(%r13), %rdx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$4, %ecx
	callq	_iproc_pci_raw_config_write32
	movl	$100, %edi
	callq	_msleep
	movq	_PCI_EXP_LNKSTA@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	addq	(%r13), %rdx
	leaq	-44(%rbp), %r8
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	$2, %ecx
	callq	_iproc_pci_raw_config_read32
	movl	(%r12), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_9
LBB0_10:
	leaq	L_.str.2(%rip), %rsi
	leaq	L_.str.4(%rip), %rdx
	movq	%r14, %rdi
	callq	_dev_info
	movq	_ENODEV@GOTPCREL(%rip), %rax
	xorl	%r15d, %r15d
	jmp	LBB0_11
	.cfi_endproc
                                        ## -- End function
	.comm	_IPROC_PCIE_LINK_STATUS,4,2     ## @IPROC_PCIE_LINK_STATUS
	.comm	_PCIE_PHYLINKUP,4,2             ## @PCIE_PHYLINKUP
	.comm	_PCIE_DL_ACTIVE,4,2             ## @PCIE_DL_ACTIVE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"PHY or data link is INACTIVE!\n"

	.comm	_ENODEV,4,2                     ## @ENODEV
	.comm	_PCI_HEADER_TYPE,8,3            ## @PCI_HEADER_TYPE
	.comm	_PCI_HEADER_TYPE_BRIDGE,4,2     ## @PCI_HEADER_TYPE_BRIDGE
L_.str.1:                               ## @.str.1
	.asciz	"in EP mode, hdr=%#02x\n"

	.comm	_EFAULT,4,2                     ## @EFAULT
	.comm	_PCI_CLASS_BRIDGE_PCI,4,2       ## @PCI_CLASS_BRIDGE_PCI
	.comm	_IPROC_PCI_EXP_CAP,8,3          ## @IPROC_PCI_EXP_CAP
	.comm	_PCI_EXP_LNKSTA,8,3             ## @PCI_EXP_LNKSTA
	.comm	_PCI_EXP_LNKSTA_NLW,4,2         ## @PCI_EXP_LNKSTA_NLW
	.comm	_PCI_EXP_LNKCTL2,8,3            ## @PCI_EXP_LNKCTL2
L_.str.2:                               ## @.str.2
	.asciz	"link: %s\n"

L_.str.3:                               ## @.str.3
	.asciz	"UP"

L_.str.4:                               ## @.str.4
	.asciz	"DOWN"

	.comm	_PCI_BRIDGE_CTRL_REG_OFFSET,8,3 ## @PCI_BRIDGE_CTRL_REG_OFFSET
	.comm	_PCI_CLASS_BRIDGE_MASK,4,2      ## @PCI_CLASS_BRIDGE_MASK
	.comm	_PCI_CLASS_BRIDGE_SHIFT,4,2     ## @PCI_CLASS_BRIDGE_SHIFT
	.comm	_PCI_TARGET_LINK_SPEED_GEN1,4,2 ## @PCI_TARGET_LINK_SPEED_GEN1
	.comm	_PCI_TARGET_LINK_SPEED_GEN2,4,2 ## @PCI_TARGET_LINK_SPEED_GEN2
	.comm	_PCI_TARGET_LINK_SPEED_MASK,4,2 ## @PCI_TARGET_LINK_SPEED_MASK
	.no_dead_strip	_iproc_pcie_check_link
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iproc_pcie_check_link
_iproc_pcie_check_link:                 ; @iproc_pcie_check_link
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	x8, [x0]
	cbz	x8, LBB0_2
; %bb.1:
	mov	w0, #0
	b	LBB0_11
LBB0_2:
	mov	x20, x0
	ldr	x19, [x0, #8]
Lloh0:
	adrp	x8, _IPROC_PCIE_LINK_STATUS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IPROC_PCIE_LINK_STATUS@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_iproc_pcie_read_reg
Lloh3:
	adrp	x8, _PCIE_PHYLINKUP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_PHYLINKUP@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_7
; %bb.3:
Lloh6:
	adrp	x8, _PCIE_DL_ACTIVE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCIE_DL_ACTIVE@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_7
; %bb.4:
Lloh9:
	adrp	x8, _PCI_HEADER_TYPE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCI_HEADER_TYPE@GOTPAGEOFF]
Lloh11:
	ldr	x2, [x8]
	add	x4, sp, #28
	mov	x0, x20
	mov	w1, #0
	mov	w3, #1
	bl	_iproc_pci_raw_config_read32
	ldr	w8, [sp, #28]
	and	w9, w8, #0x7f
Lloh12:
	adrp	x10, _PCI_HEADER_TYPE_BRIDGE@GOTPAGE
Lloh13:
	ldr	x10, [x10, _PCI_HEADER_TYPE_BRIDGE@GOTPAGEOFF]
Lloh14:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_9
; %bb.5:
	add	x4, sp, #16
	mov	x0, x20
	mov	w1, #0
	mov	w2, #1084
	mov	w3, #4
	bl	_iproc_pci_raw_config_read32
	ldr	w8, [sp, #16]
	and	w8, w8, #0xff0000ff
Lloh15:
	adrp	x9, _PCI_CLASS_BRIDGE_PCI@GOTPAGE
Lloh16:
	ldr	x9, [x9, _PCI_CLASS_BRIDGE_PCI@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w4, w8, w9, lsl #8
	str	w4, [sp, #16]
	mov	x0, x20
	mov	w1, #0
	mov	w2, #1084
	mov	w3, #4
	bl	_iproc_pci_raw_config_write32
Lloh18:
	adrp	x21, _IPROC_PCI_EXP_CAP@GOTPAGE
Lloh19:
	ldr	x21, [x21, _IPROC_PCI_EXP_CAP@GOTPAGEOFF]
	ldr	x8, [x21]
Lloh20:
	adrp	x22, _PCI_EXP_LNKSTA@GOTPAGE
Lloh21:
	ldr	x22, [x22, _PCI_EXP_LNKSTA@GOTPAGEOFF]
	ldr	x9, [x22]
	add	x2, x9, x8
	add	x4, sp, #20
	mov	x0, x20
	mov	w1, #0
	mov	w3, #2
	bl	_iproc_pci_raw_config_read32
	ldr	w8, [sp, #20]
Lloh22:
	adrp	x23, _PCI_EXP_LNKSTA_NLW@GOTPAGE
Lloh23:
	ldr	x23, [x23, _PCI_EXP_LNKSTA_NLW@GOTPAGEOFF]
	ldr	w9, [x23]
	tst	w9, w8
	b.eq	LBB0_12
LBB0_6:
Lloh24:
	adrp	x1, l_.str.2@PAGE
Lloh25:
	add	x1, x1, l_.str.2@PAGEOFF
Lloh26:
	adrp	x2, l_.str.3@PAGE
Lloh27:
	add	x2, x2, l_.str.3@PAGEOFF
	mov	x0, x19
	bl	_dev_info
	mov	w0, #0
	b	LBB0_11
LBB0_7:
Lloh28:
	adrp	x1, l_.str@PAGE
Lloh29:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_dev_err
LBB0_8:
Lloh30:
	adrp	x8, _ENODEV@GOTPAGE
Lloh31:
	ldr	x8, [x8, _ENODEV@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
	str	x8, [sp]
Lloh32:
	adrp	x1, l_.str.1@PAGE
Lloh33:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_dev_err
Lloh34:
	adrp	x8, _EFAULT@GOTPAGE
Lloh35:
	ldr	x8, [x8, _EFAULT@GOTPAGEOFF]
LBB0_10:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_11:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
LBB0_12:
	ldr	x8, [x21]
Lloh36:
	adrp	x24, _PCI_EXP_LNKCTL2@GOTPAGE
Lloh37:
	ldr	x24, [x24, _PCI_EXP_LNKCTL2@GOTPAGEOFF]
	ldr	x9, [x24]
	add	x2, x9, x8
	add	x4, sp, #24
	mov	x0, x20
	mov	w1, #0
	mov	w3, #4
	bl	_iproc_pci_raw_config_read32
	ldr	w8, [sp, #24]
	and	w9, w8, #0xf
	cmp	w9, #2
	b.ne	LBB0_14
; %bb.13:
	and	w8, w8, #0xfffffff0
	orr	w4, w8, #0x1
	str	w4, [sp, #24]
	ldr	x8, [x21]
	ldr	x9, [x24]
	add	x2, x9, x8
	mov	x0, x20
	mov	w1, #0
	mov	w3, #4
	bl	_iproc_pci_raw_config_write32
	mov	w0, #100
	bl	_msleep
	ldr	x8, [x21]
	ldr	x9, [x22]
	add	x2, x9, x8
	add	x4, sp, #20
	mov	x0, x20
	mov	w1, #0
	mov	w3, #2
	bl	_iproc_pci_raw_config_read32
	ldr	w8, [sp, #20]
	ldr	w9, [x23]
	tst	w9, w8
	b.ne	LBB0_6
LBB0_14:
Lloh38:
	adrp	x1, l_.str.2@PAGE
Lloh39:
	add	x1, x1, l_.str.2@PAGEOFF
Lloh40:
	adrp	x2, l_.str.4@PAGE
Lloh41:
	add	x2, x2, l_.str.4@PAGEOFF
	mov	x0, x19
	bl	_dev_info
	b	LBB0_8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpAdd	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpAdd	Lloh40, Lloh41
	.loh AdrpAdd	Lloh38, Lloh39
	.cfi_endproc
                                        ; -- End function
	.comm	_IPROC_PCIE_LINK_STATUS,4,2     ; @IPROC_PCIE_LINK_STATUS
	.comm	_PCIE_PHYLINKUP,4,2             ; @PCIE_PHYLINKUP
	.comm	_PCIE_DL_ACTIVE,4,2             ; @PCIE_DL_ACTIVE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"PHY or data link is INACTIVE!\n"

	.comm	_ENODEV,4,2                     ; @ENODEV
	.comm	_PCI_HEADER_TYPE,8,3            ; @PCI_HEADER_TYPE
	.comm	_PCI_HEADER_TYPE_BRIDGE,4,2     ; @PCI_HEADER_TYPE_BRIDGE
l_.str.1:                               ; @.str.1
	.asciz	"in EP mode, hdr=%#02x\n"

	.comm	_EFAULT,4,2                     ; @EFAULT
	.comm	_PCI_CLASS_BRIDGE_PCI,4,2       ; @PCI_CLASS_BRIDGE_PCI
	.comm	_IPROC_PCI_EXP_CAP,8,3          ; @IPROC_PCI_EXP_CAP
	.comm	_PCI_EXP_LNKSTA,8,3             ; @PCI_EXP_LNKSTA
	.comm	_PCI_EXP_LNKSTA_NLW,4,2         ; @PCI_EXP_LNKSTA_NLW
	.comm	_PCI_EXP_LNKCTL2,8,3            ; @PCI_EXP_LNKCTL2
l_.str.2:                               ; @.str.2
	.asciz	"link: %s\n"

l_.str.3:                               ; @.str.3
	.asciz	"UP"

l_.str.4:                               ; @.str.4
	.asciz	"DOWN"

	.comm	_PCI_BRIDGE_CTRL_REG_OFFSET,8,3 ; @PCI_BRIDGE_CTRL_REG_OFFSET
	.comm	_PCI_CLASS_BRIDGE_MASK,4,2      ; @PCI_CLASS_BRIDGE_MASK
	.comm	_PCI_CLASS_BRIDGE_SHIFT,4,2     ; @PCI_CLASS_BRIDGE_SHIFT
	.comm	_PCI_TARGET_LINK_SPEED_GEN1,4,2 ; @PCI_TARGET_LINK_SPEED_GEN1
	.comm	_PCI_TARGET_LINK_SPEED_GEN2,4,2 ; @PCI_TARGET_LINK_SPEED_GEN2
	.comm	_PCI_TARGET_LINK_SPEED_MASK,4,2 ; @PCI_TARGET_LINK_SPEED_MASK
	.no_dead_strip	_iproc_pcie_check_link
.subsections_via_symbols
