	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function imx6_pcie_assert_core_reset
_imx6_pcie_assert_core_reset:           ## @imx6_pcie_assert_core_reset
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	24(%rdi), %rax
	movq	32(%rdi), %rcx
	movq	(%rcx), %r14
	movl	(%rax), %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	ja	LBB0_8
## %bb.1:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movl	16(%rbx), %edi
	callq	_reset_control_assert
	movl	12(%rbx), %edi
	callq	_reset_control_assert
	jmp	LBB0_8
LBB0_3:
	movl	8(%rbx), %edi
	movq	_IOMUXC_GPR12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX6SX_GPR12_PCIE_TEST_POWERDOWN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	8(%rbx), %edi
	movq	_IOMUXC_GPR5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX6SX_GPR5_PCIE_BTNRST_RESET@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_4:
	movl	8(%rbx), %edi
	movq	_IOMUXC_GPR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IMX6Q_GPR1_PCIE_SW_RST@GOTPCREL(%rip), %rax
LBB0_5:
	movl	(%rax), %ecx
	movl	%ecx, %edx
	jmp	LBB0_7
LBB0_6:
	movl	8(%rbx), %edi
	movq	_IOMUXC_GPR1@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_IMX6Q_GPR1_PCIE_TEST_PD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$262144, %ecx                   ## imm = 0x40000
	callq	_regmap_update_bits
	movl	8(%rbx), %edi
	movl	(%r15), %esi
	movq	_IMX6Q_GPR1_PCIE_REF_CLK_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
LBB0_7:
	callq	_regmap_update_bits
LBB0_8:
	movq	(%rbx), %rdi
	testq	%rdi, %rdi
	je	LBB0_11
## %bb.9:
	callq	_regulator_is_enabled
	testq	%rax, %rax
	jle	LBB0_11
## %bb.10:
	movq	(%rbx), %rdi
	callq	_regulator_disable
	testl	%eax, %eax
	je	LBB0_11
## %bb.12:
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	movl	%eax, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dev_err                        ## TAILCALL
LBB0_11:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
LJTI0_0:
	.long	L0_0_set_2
	.long	L0_0_set_2
	.long	L0_0_set_3
	.long	L0_0_set_4
	.long	L0_0_set_6
	.end_data_region
                                        ## -- End function
	.comm	_IOMUXC_GPR12,4,2               ## @IOMUXC_GPR12
	.comm	_IMX6SX_GPR12_PCIE_TEST_POWERDOWN,4,2 ## @IMX6SX_GPR12_PCIE_TEST_POWERDOWN
	.comm	_IOMUXC_GPR5,4,2                ## @IOMUXC_GPR5
	.comm	_IMX6SX_GPR5_PCIE_BTNRST_RESET,4,2 ## @IMX6SX_GPR5_PCIE_BTNRST_RESET
	.comm	_IOMUXC_GPR1,4,2                ## @IOMUXC_GPR1
	.comm	_IMX6Q_GPR1_PCIE_SW_RST,4,2     ## @IMX6Q_GPR1_PCIE_SW_RST
	.comm	_IMX6Q_GPR1_PCIE_TEST_PD,4,2    ## @IMX6Q_GPR1_PCIE_TEST_PD
	.comm	_IMX6Q_GPR1_PCIE_REF_CLK_EN,4,2 ## @IMX6Q_GPR1_PCIE_REF_CLK_EN
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to disable vpcie regulator: %d\n"

	.no_dead_strip	_imx6_pcie_assert_core_reset
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function imx6_pcie_assert_core_reset
_imx6_pcie_assert_core_reset:           ; @imx6_pcie_assert_core_reset
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	ldp	x9, x8, [x0, #24]
	ldr	x19, [x8]
	ldr	w8, [x9]
	sub	w8, w8, #128
	cmp	w8, #4
	b.hi	LBB0_3
; %bb.1:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
	ldr	w0, [x20, #16]
	bl	_reset_control_assert
	ldr	w0, [x20, #12]
	bl	_reset_control_assert
LBB0_3:
	ldr	x0, [x20]
	cbnz	x0, LBB0_9
	b	LBB0_12
LBB0_4:
	ldr	w0, [x20, #8]
Lloh2:
	adrp	x8, _IOMUXC_GPR12@GOTPAGE
Lloh3:
	ldr	x8, [x8, _IOMUXC_GPR12@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
Lloh5:
	adrp	x8, _IMX6SX_GPR12_PCIE_TEST_POWERDOWN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _IMX6SX_GPR12_PCIE_TEST_POWERDOWN@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x20, #8]
Lloh8:
	adrp	x8, _IOMUXC_GPR5@GOTPAGE
Lloh9:
	ldr	x8, [x8, _IOMUXC_GPR5@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
Lloh11:
	adrp	x8, _IMX6SX_GPR5_PCIE_BTNRST_RESET@GOTPAGE
Lloh12:
	ldr	x8, [x8, _IMX6SX_GPR5_PCIE_BTNRST_RESET@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
	ldr	w0, [x20, #8]
Lloh13:
	adrp	x8, _IOMUXC_GPR1@GOTPAGE
Lloh14:
	ldr	x8, [x8, _IOMUXC_GPR1@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
Lloh16:
	adrp	x8, _IMX6Q_GPR1_PCIE_SW_RST@GOTPAGE
Lloh17:
	ldr	x8, [x8, _IMX6Q_GPR1_PCIE_SW_RST@GOTPAGEOFF]
LBB0_6:
	ldr	w2, [x8]
	mov	x3, x2
	b	LBB0_8
LBB0_7:
	ldr	w0, [x20, #8]
Lloh18:
	adrp	x21, _IOMUXC_GPR1@GOTPAGE
Lloh19:
	ldr	x21, [x21, _IOMUXC_GPR1@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh20:
	adrp	x8, _IMX6Q_GPR1_PCIE_TEST_PD@GOTPAGE
Lloh21:
	ldr	x8, [x8, _IMX6Q_GPR1_PCIE_TEST_PD@GOTPAGEOFF]
Lloh22:
	ldr	w2, [x8]
	mov	w3, #262144
	bl	_regmap_update_bits
	ldr	w0, [x20, #8]
	ldr	w1, [x21]
Lloh23:
	adrp	x8, _IMX6Q_GPR1_PCIE_REF_CLK_EN@GOTPAGE
Lloh24:
	ldr	x8, [x8, _IMX6Q_GPR1_PCIE_REF_CLK_EN@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	w3, #0
LBB0_8:
	bl	_regmap_update_bits
	ldr	x0, [x20]
	cbz	x0, LBB0_12
LBB0_9:
	bl	_regulator_is_enabled
	cmp	x0, #1
	b.lt	LBB0_12
; %bb.10:
	ldr	x0, [x20]
	bl	_regulator_disable
	cbz	w0, LBB0_12
; %bb.11:
	mov	x2, x0
Lloh26:
	adrp	x1, l_.str@PAGE
Lloh27:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_dev_err
LBB0_12:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpAdd	Lloh26, Lloh27
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_7-LBB0_2)>>2
                                        ; -- End function
	.comm	_IOMUXC_GPR12,4,2               ; @IOMUXC_GPR12
	.comm	_IMX6SX_GPR12_PCIE_TEST_POWERDOWN,4,2 ; @IMX6SX_GPR12_PCIE_TEST_POWERDOWN
	.comm	_IOMUXC_GPR5,4,2                ; @IOMUXC_GPR5
	.comm	_IMX6SX_GPR5_PCIE_BTNRST_RESET,4,2 ; @IMX6SX_GPR5_PCIE_BTNRST_RESET
	.comm	_IOMUXC_GPR1,4,2                ; @IOMUXC_GPR1
	.comm	_IMX6Q_GPR1_PCIE_SW_RST,4,2     ; @IMX6Q_GPR1_PCIE_SW_RST
	.comm	_IMX6Q_GPR1_PCIE_TEST_PD,4,2    ; @IMX6Q_GPR1_PCIE_TEST_PD
	.comm	_IMX6Q_GPR1_PCIE_REF_CLK_EN,4,2 ; @IMX6Q_GPR1_PCIE_REF_CLK_EN
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to disable vpcie regulator: %d\n"

	.no_dead_strip	_imx6_pcie_assert_core_reset
.subsections_via_symbols
