	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ar9002_hw_configpcipowersave
_ar9002_hw_configpcipowersave:          ## @ar9002_hw_configpcipowersave
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	testl	%esi, %esi
	je	LBB0_1
## %bb.5:
	movq	_AR_PCIE_PM_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_PCIE_PM_CTRL_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_REG_CLR_BIT
	movq	_AR_WA@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_REG_READ
	movl	%eax, %r14d
	movl	(%r15), %ebx
	testl	%ebx, %ebx
	je	LBB0_7
## %bb.6:
	movq	_AR_WA_D3_L1_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%eax, %ebx
	cmovnel	%eax, %ebx
	jmp	LBB0_15
LBB0_1:
	movq	%r15, %rdi
	callq	_AR_SREV_9280_20_OR_LATER
	testq	%rax, %rax
	je	LBB0_25
## %bb.2:
	cmpq	$0, 8(%r15)
	jle	LBB0_26
## %bb.3:
	leaq	8(%r15), %r14
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_INI_RA
	movl	%eax, %r12d
	movq	%r14, %rdi
	movq	%rbx, %rsi
	movl	$1, %edx
	callq	_INI_RA
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_REG_WRITE
	incq	%rbx
	cmpq	8(%r15), %rbx
	jl	LBB0_4
	jmp	LBB0_26
LBB0_7:
	movq	%r15, %rdi
	callq	_AR_SREV_9285
	testq	%rax, %rax
	jne	LBB0_10
## %bb.8:
	movq	%r15, %rdi
	callq	_AR_SREV_9271
	testq	%rax, %rax
	jne	LBB0_10
## %bb.9:
	movq	%r15, %rdi
	callq	_AR_SREV_9287
	testq	%rax, %rax
	je	LBB0_11
LBB0_10:
	movq	_AR9285_WA_DEFAULT@GOTPCREL(%rip), %rax
LBB0_14:
	movq	_AR_WA_D3_L1_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	(%rax), %ebx
	andl	%ecx, %ebx
	cmovnel	%ecx, %ebx
LBB0_15:
	orl	%r14d, %ebx
LBB0_16:
	movq	%r15, %rdi
	callq	_AR_SREV_9280
	testq	%rax, %rax
	jne	LBB0_19
## %bb.17:
	movq	%r15, %rdi
	callq	_AR_SREV_9285
	testq	%rax, %rax
	jne	LBB0_19
## %bb.18:
	movq	%r15, %rdi
	callq	_AR_SREV_9287
	testq	%rax, %rax
	je	LBB0_20
LBB0_19:
	movq	_AR_WA_BIT6@GOTPCREL(%rip), %rax
	movq	_AR_WA_BIT7@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	notl	%ecx
	andl	%ecx, %ebx
LBB0_20:
	movq	%r15, %rdi
	callq	_AR_SREV_9280
	xorl	%r13d, %r13d
	movl	$0, %r14d
	testq	%rax, %rax
	je	LBB0_22
## %bb.21:
	movq	_AR_WA_BIT22@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
LBB0_22:
	movq	%r15, %rdi
	callq	_AR_SREV_9285E_20
	testq	%rax, %rax
	je	LBB0_24
## %bb.23:
	movq	_AR_WA_BIT23@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
LBB0_24:
	orl	%r13d, %ebx
	orl	%ebx, %r14d
	movl	(%r12), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_WRITE                      ## TAILCALL
LBB0_25:
	movq	%r15, %rdi
	callq	_ENABLE_REGWRITE_BUFFER
	movq	_AR_PCIE_SERDES@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$-1840710656, %edx              ## imm = 0x9248FC00
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$613566756, %edx                ## imm = 0x24924924
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$671088697, %edx                ## imm = 0x28000039
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$1393952804, %edx               ## imm = 0x53160824
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$-443021959, %edx               ## imm = 0xE5980579
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$1961983, %edx                  ## imm = 0x1DEFFF
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$447397440, %edx                ## imm = 0x1AAABE40
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$-1106225836, %edx              ## imm = 0xBE105554
	callq	_REG_WRITE
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	$929799, %edx                   ## imm = 0xE3007
	callq	_REG_WRITE
	movq	_AR_PCIE_SERDES2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_REG_WRITE
	movq	%r15, %rdi
	callq	_REGWRITE_BUFFER_FLUSH
LBB0_26:
	movl	$1000, %edi                     ## imm = 0x3E8
	callq	_udelay
	movl	(%r15), %ebx
	testl	%ebx, %ebx
	je	LBB0_28
## %bb.27:
	movq	_AR_WA_D3_L1_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %ebx
	jmp	LBB0_36
LBB0_28:
	movq	%r15, %rdi
	callq	_AR_SREV_9285
	testq	%rax, %rax
	jne	LBB0_31
## %bb.29:
	movq	%r15, %rdi
	callq	_AR_SREV_9271
	testq	%rax, %rax
	jne	LBB0_31
## %bb.30:
	movq	%r15, %rdi
	callq	_AR_SREV_9287
	testq	%rax, %rax
	je	LBB0_33
LBB0_31:
	movq	_AR9285_WA_DEFAULT@GOTPCREL(%rip), %rax
LBB0_32:
	movq	_AR_WA_D3_L1_DISABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	(%rax), %ebx
LBB0_36:
	movq	%r15, %rdi
	callq	_AR_SREV_9285
	testq	%rax, %rax
	jne	LBB0_38
## %bb.37:
	movq	%r15, %rdi
	callq	_AR_SREV_9287
	testq	%rax, %rax
	je	LBB0_39
LBB0_38:
	movq	_AR_WA_BIT6@GOTPCREL(%rip), %rax
	movq	_AR_WA_BIT7@GOTPCREL(%rip), %rcx
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
LBB0_39:
	movq	%r15, %rdi
	callq	_AR_SREV_9285E_20
	xorl	%edx, %edx
	testq	%rax, %rax
	je	LBB0_41
## %bb.40:
	movq	_AR_WA_BIT23@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
LBB0_41:
	orl	%ebx, %edx
	movq	_AR_WA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_REG_WRITE
	movq	_AR_PCIE_PM_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_PCIE_PM_CTRL_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_SET_BIT                    ## TAILCALL
LBB0_11:
	movq	%r15, %rdi
	callq	_AR_SREV_9280
	testq	%rax, %rax
	je	LBB0_12
## %bb.13:
	movq	_AR9280_WA_DEFAULT@GOTPCREL(%rip), %rax
	jmp	LBB0_14
LBB0_33:
	movq	%r15, %rdi
	callq	_AR_SREV_9280
	testq	%rax, %rax
	je	LBB0_35
## %bb.34:
	movq	_AR9280_WA_DEFAULT@GOTPCREL(%rip), %rax
	jmp	LBB0_32
LBB0_12:
	movl	%r14d, %ebx
	jmp	LBB0_16
LBB0_35:
	movq	_AR_WA_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	jmp	LBB0_36
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_PCIE_SERDES,4,2             ## @AR_PCIE_SERDES
	.comm	_AR_PCIE_SERDES2,4,2            ## @AR_PCIE_SERDES2
	.comm	_AR_PCIE_PM_CTRL,4,2            ## @AR_PCIE_PM_CTRL
	.comm	_AR_PCIE_PM_CTRL_ENA,4,2        ## @AR_PCIE_PM_CTRL_ENA
	.comm	_AR_WA,4,2                      ## @AR_WA
	.comm	_AR_WA_D3_L1_DISABLE,4,2        ## @AR_WA_D3_L1_DISABLE
	.comm	_AR9285_WA_DEFAULT,4,2          ## @AR9285_WA_DEFAULT
	.comm	_AR9280_WA_DEFAULT,4,2          ## @AR9280_WA_DEFAULT
	.comm	_AR_WA_BIT6,4,2                 ## @AR_WA_BIT6
	.comm	_AR_WA_BIT7,4,2                 ## @AR_WA_BIT7
	.comm	_AR_WA_BIT22,4,2                ## @AR_WA_BIT22
	.comm	_AR_WA_BIT23,4,2                ## @AR_WA_BIT23
	.comm	_AR_WA_DEFAULT,4,2              ## @AR_WA_DEFAULT
	.no_dead_strip	_ar9002_hw_configpcipowersave
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ar9002_hw_configpcipowersave
_ar9002_hw_configpcipowersave:          ; @ar9002_hw_configpcipowersave
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	cbz	w1, LBB0_13
; %bb.1:
Lloh0:
	adrp	x8, _AR_PCIE_PM_CTRL@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AR_PCIE_PM_CTRL@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _AR_PCIE_PM_CTRL_ENA@GOTPAGE
Lloh4:
	ldr	x8, [x8, _AR_PCIE_PM_CTRL_ENA@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_REG_CLR_BIT
Lloh6:
	adrp	x21, _AR_WA@GOTPAGE
Lloh7:
	ldr	x21, [x21, _AR_WA@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_REG_READ
	mov	x20, x0
	ldr	w8, [x19]
	cbnz	w8, LBB0_7
; %bb.2:
	mov	x0, x19
	bl	_AR_SREV_9285
	cbnz	x0, LBB0_5
; %bb.3:
	mov	x0, x19
	bl	_AR_SREV_9271
	cbnz	x0, LBB0_5
; %bb.4:
	mov	x0, x19
	bl	_AR_SREV_9287
	cbz	x0, LBB0_29
LBB0_5:
Lloh8:
	adrp	x8, _AR9285_WA_DEFAULT@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AR9285_WA_DEFAULT@GOTPAGEOFF]
LBB0_6:
	ldr	w8, [x8]
LBB0_7:
Lloh10:
	adrp	x9, _AR_WA_D3_L1_DISABLE@GOTPAGE
Lloh11:
	ldr	x9, [x9, _AR_WA_D3_L1_DISABLE@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	tst	w9, w8
	csel	w8, wzr, w9, eq
	orr	w20, w8, w20
LBB0_8:
	mov	x0, x19
	bl	_AR_SREV_9280
	cbnz	x0, LBB0_11
; %bb.9:
	mov	x0, x19
	bl	_AR_SREV_9285
	cbnz	x0, LBB0_11
; %bb.10:
	mov	x0, x19
	bl	_AR_SREV_9287
	cbz	x0, LBB0_12
LBB0_11:
Lloh13:
	adrp	x8, _AR_WA_BIT6@GOTPAGE
Lloh14:
	ldr	x8, [x8, _AR_WA_BIT6@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
Lloh16:
	adrp	x9, _AR_WA_BIT7@GOTPAGE
Lloh17:
	ldr	x9, [x9, _AR_WA_BIT7@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w20, w20, w8
LBB0_12:
	mov	x0, x19
	bl	_AR_SREV_9280
Lloh19:
	adrp	x8, _AR_WA_BIT22@GOTPAGE
Lloh20:
	ldr	x8, [x8, _AR_WA_BIT22@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w20, w8, w20
	mov	x0, x19
	bl	_AR_SREV_9285E_20
Lloh22:
	adrp	x8, _AR_WA_BIT23@GOTPAGE
Lloh23:
	ldr	x8, [x8, _AR_WA_BIT23@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w2, w20, w8
	ldr	w1, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_REG_WRITE
LBB0_13:
	mov	x0, x19
	bl	_AR_SREV_9280_20_OR_LATER
	cbz	x0, LBB0_17
; %bb.14:
	mov	x20, x19
	ldr	x8, [x20, #8]!
	cmp	x8, #1
	b.lt	LBB0_18
; %bb.15:
	mov	x21, #0
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	mov	x1, x21
	mov	w2, #0
	bl	_INI_RA
	mov	x22, x0
	mov	x0, x20
	mov	x1, x21
	mov	w2, #1
	bl	_INI_RA
	mov	x2, x0
	mov	x0, x19
	mov	x1, x22
	bl	_REG_WRITE
	add	x21, x21, #1
	ldr	x8, [x19, #8]
	cmp	x21, x8
	b.lt	LBB0_16
	b	LBB0_18
LBB0_17:
	mov	x0, x19
	bl	_ENABLE_REGWRITE_BUFFER
Lloh25:
	adrp	x20, _AR_PCIE_SERDES@GOTPAGE
Lloh26:
	ldr	x20, [x20, _AR_PCIE_SERDES@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #64512
	movk	w2, #37448, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #18724
	movk	w2, #9362, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #57
	movk	w2, #10240, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #2084
	movk	w2, #21270, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #1401
	movk	w2, #58776, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #61439
	movk	w2, #29, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #48704
	movk	w2, #6826, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #21844
	movk	w2, #48656, lsl #16
	bl	_REG_WRITE
	ldr	w1, [x20]
	mov	x0, x19
	mov	w2, #12295
	movk	w2, #14, lsl #16
	bl	_REG_WRITE
Lloh27:
	adrp	x8, _AR_PCIE_SERDES2@GOTPAGE
Lloh28:
	ldr	x8, [x8, _AR_PCIE_SERDES2@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_REG_WRITE
	mov	x0, x19
	bl	_REGWRITE_BUFFER_FLUSH
LBB0_18:
	mov	w0, #1000
	bl	_udelay
	ldr	w8, [x19]
	cbnz	w8, LBB0_24
; %bb.19:
	mov	x0, x19
	bl	_AR_SREV_9285
	cbnz	x0, LBB0_22
; %bb.20:
	mov	x0, x19
	bl	_AR_SREV_9271
	cbnz	x0, LBB0_22
; %bb.21:
	mov	x0, x19
	bl	_AR_SREV_9287
	cbz	x0, LBB0_31
LBB0_22:
Lloh30:
	adrp	x8, _AR9285_WA_DEFAULT@GOTPAGE
Lloh31:
	ldr	x8, [x8, _AR9285_WA_DEFAULT@GOTPAGEOFF]
LBB0_23:
	ldr	w8, [x8]
LBB0_24:
Lloh32:
	adrp	x9, _AR_WA_D3_L1_DISABLE@GOTPAGE
Lloh33:
	ldr	x9, [x9, _AR_WA_D3_L1_DISABLE@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
	bic	w20, w8, w9
LBB0_25:
	mov	x0, x19
	bl	_AR_SREV_9285
	cbnz	x0, LBB0_27
; %bb.26:
	mov	x0, x19
	bl	_AR_SREV_9287
	cbz	x0, LBB0_28
LBB0_27:
Lloh35:
	adrp	x8, _AR_WA_BIT6@GOTPAGE
Lloh36:
	ldr	x8, [x8, _AR_WA_BIT6@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
Lloh38:
	adrp	x9, _AR_WA_BIT7@GOTPAGE
Lloh39:
	ldr	x9, [x9, _AR_WA_BIT7@GOTPAGEOFF]
Lloh40:
	ldr	w9, [x9]
	orr	w8, w8, w20
	orr	w20, w8, w9
LBB0_28:
	mov	x0, x19
	bl	_AR_SREV_9285E_20
Lloh41:
	adrp	x8, _AR_WA_BIT23@GOTPAGE
Lloh42:
	ldr	x8, [x8, _AR_WA_BIT23@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	cmp	x0, #0
	csel	w8, wzr, w8, eq
	orr	w2, w8, w20
Lloh44:
	adrp	x8, _AR_WA@GOTPAGE
Lloh45:
	ldr	x8, [x8, _AR_WA@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_WRITE
Lloh47:
	adrp	x8, _AR_PCIE_PM_CTRL@GOTPAGE
Lloh48:
	ldr	x8, [x8, _AR_PCIE_PM_CTRL@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
Lloh50:
	adrp	x8, _AR_PCIE_PM_CTRL_ENA@GOTPAGE
Lloh51:
	ldr	x8, [x8, _AR_PCIE_PM_CTRL_ENA@GOTPAGEOFF]
Lloh52:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_REG_SET_BIT
LBB0_29:
	mov	x0, x19
	bl	_AR_SREV_9280
	cbz	x0, LBB0_8
; %bb.30:
Lloh53:
	adrp	x8, _AR9280_WA_DEFAULT@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AR9280_WA_DEFAULT@GOTPAGEOFF]
	b	LBB0_6
LBB0_31:
	mov	x0, x19
	bl	_AR_SREV_9280
	cbz	x0, LBB0_33
; %bb.32:
Lloh55:
	adrp	x8, _AR9280_WA_DEFAULT@GOTPAGE
Lloh56:
	ldr	x8, [x8, _AR9280_WA_DEFAULT@GOTPAGEOFF]
	b	LBB0_23
LBB0_33:
Lloh57:
	adrp	x8, _AR_WA_DEFAULT@GOTPAGE
Lloh58:
	ldr	x8, [x8, _AR_WA_DEFAULT@GOTPAGEOFF]
Lloh59:
	ldr	w20, [x8]
	b	LBB0_25
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_PCIE_SERDES,4,2             ; @AR_PCIE_SERDES
	.comm	_AR_PCIE_SERDES2,4,2            ; @AR_PCIE_SERDES2
	.comm	_AR_PCIE_PM_CTRL,4,2            ; @AR_PCIE_PM_CTRL
	.comm	_AR_PCIE_PM_CTRL_ENA,4,2        ; @AR_PCIE_PM_CTRL_ENA
	.comm	_AR_WA,4,2                      ; @AR_WA
	.comm	_AR_WA_D3_L1_DISABLE,4,2        ; @AR_WA_D3_L1_DISABLE
	.comm	_AR9285_WA_DEFAULT,4,2          ; @AR9285_WA_DEFAULT
	.comm	_AR9280_WA_DEFAULT,4,2          ; @AR9280_WA_DEFAULT
	.comm	_AR_WA_BIT6,4,2                 ; @AR_WA_BIT6
	.comm	_AR_WA_BIT7,4,2                 ; @AR_WA_BIT7
	.comm	_AR_WA_BIT22,4,2                ; @AR_WA_BIT22
	.comm	_AR_WA_BIT23,4,2                ; @AR_WA_BIT23
	.comm	_AR_WA_DEFAULT,4,2              ; @AR_WA_DEFAULT
	.no_dead_strip	_ar9002_hw_configpcipowersave
.subsections_via_symbols
