	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlx5e_build_tir_ctx_lro
_mlx5e_build_tir_ctx_lro:               ## @mlx5e_build_tir_ctx_lro
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	cmpl	$0, 4(%rdi)
	je	LBB0_1
## %bb.2:
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movq	_lro_enable_mask@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO@GOTPCREL(%rip), %rax
	movq	_MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	%rsi, %rdi
	callq	_MLX5_SET
	movq	_lro_max_ip_payload_size@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ@GOTPCREL(%rip), %rax
	movl	$-256, %ecx
	addl	(%rax), %ecx
	sarl	$8, %ecx
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	callq	_MLX5_SET
	movq	_lro_timeout_period_usecs@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	(%r14), %ecx
	movq	%rbx, %rdi
	movq	%rbx, %rsi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_MLX5_SET                       ## TAILCALL
LBB0_1:
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_lro_enable_mask,4,2            ## @lro_enable_mask
	.comm	_MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO,4,2 ## @MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
	.comm	_MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO,4,2 ## @MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
	.comm	_lro_max_ip_payload_size,4,2    ## @lro_max_ip_payload_size
	.comm	_MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ,4,2 ## @MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
	.comm	_lro_timeout_period_usecs,4,2   ## @lro_timeout_period_usecs
	.comm	_ROUGH_MAX_L2_L3_HDR_SZ,4,2     ## @ROUGH_MAX_L2_L3_HDR_SZ
	.no_dead_strip	_mlx5e_build_tir_ctx_lro
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlx5e_build_tir_ctx_lro
_mlx5e_build_tir_ctx_lro:               ; @mlx5e_build_tir_ctx_lro
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	w8, [x0, #4]
	cbz	w8, LBB0_2
; %bb.1:
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x8, _lro_enable_mask@GOTPAGE
Lloh1:
	ldr	x8, [x8, _lro_enable_mask@GOTPAGEOFF]
Lloh2:
	adrp	x9, _MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO@GOTPAGE
Lloh3:
	ldr	x9, [x9, _MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
Lloh5:
	ldr	w8, [x9]
Lloh6:
	adrp	x9, _MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w3, w9, w8
	mov	x0, x1
	bl	_MLX5_SET
Lloh9:
	adrp	x8, _lro_max_ip_payload_size@GOTPAGE
Lloh10:
	ldr	x8, [x8, _lro_max_ip_payload_size@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
Lloh12:
	adrp	x8, _MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ@GOTPAGE
Lloh13:
	ldr	x8, [x8, _MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	sub	w8, w8, #256
	asr	w3, w8, #8
	mov	x0, x19
	mov	x1, x19
	bl	_MLX5_SET
Lloh15:
	adrp	x8, _lro_timeout_period_usecs@GOTPAGE
Lloh16:
	ldr	x8, [x8, _lro_timeout_period_usecs@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	ldr	w3, [x20]
	mov	x0, x19
	mov	x1, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_MLX5_SET
LBB0_2:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_lro_enable_mask,4,2            ; @lro_enable_mask
	.comm	_MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO,4,2 ; @MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
	.comm	_MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO,4,2 ; @MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
	.comm	_lro_max_ip_payload_size,4,2    ; @lro_max_ip_payload_size
	.comm	_MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ,4,2 ; @MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
	.comm	_lro_timeout_period_usecs,4,2   ; @lro_timeout_period_usecs
	.comm	_ROUGH_MAX_L2_L3_HDR_SZ,4,2     ; @ROUGH_MAX_L2_L3_HDR_SZ
	.no_dead_strip	_mlx5e_build_tir_ctx_lro
.subsections_via_symbols
