	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath_pci_read_cachesize
_ath_pci_read_cachesize:                ## @ath_pci_read_cachesize
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	%rsi, %rbx
	movq	(%rdi), %rax
	movl	(%rax), %edi
	callq	_to_pci_dev
	movq	_PCI_CACHE_LINE_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	leaq	-16(%rbp), %rdx
	movl	%eax, %edi
	callq	_pci_read_config_byte
	movl	-16(%rbp), %eax
	movl	%eax, (%rbx)
	testl	%eax, %eax
	jne	LBB0_2
## %bb.1:
	movq	_DEFAULT_CACHELINE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	sarl	$2, %eax
	movl	%eax, (%rbx)
LBB0_2:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_CACHE_LINE_SIZE,4,2        ## @PCI_CACHE_LINE_SIZE
	.comm	_DEFAULT_CACHELINE,4,2          ## @DEFAULT_CACHELINE
	.no_dead_strip	_ath_pci_read_cachesize
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath_pci_read_cachesize
_ath_pci_read_cachesize:                ; @ath_pci_read_cachesize
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x1
	ldr	x8, [x0]
	ldr	w0, [x8]
	bl	_to_pci_dev
Lloh0:
	adrp	x8, _PCI_CACHE_LINE_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_CACHE_LINE_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x2, sp, #8
	bl	_pci_read_config_byte
	ldr	w8, [sp, #8]
	str	w8, [x19]
	cbnz	w8, LBB0_2
; %bb.1:
Lloh3:
	adrp	x8, _DEFAULT_CACHELINE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DEFAULT_CACHELINE@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	asr	w8, w8, #2
	str	w8, [x19]
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_CACHE_LINE_SIZE,4,2        ; @PCI_CACHE_LINE_SIZE
	.comm	_DEFAULT_CACHELINE,4,2          ; @DEFAULT_CACHELINE
	.no_dead_strip	_ath_pci_read_cachesize
.subsections_via_symbols
