	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_il_apm_init                    ## -- Begin function il_apm_init
	.p2align	4, 0x90
_il_apm_init:                           ## @il_apm_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	leaq	L_.str(%rip), %rdi
	callq	_D_INFO
	movq	_CSR_GIO_CHICKEN_BITS@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%rbx, %rdi
	callq	_il_set_bit
	movl	(%r14), %esi
	movq	_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%rbx, %rdi
	callq	_il_set_bit
	movq	_CSR_DBG_HPET_MEM_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_DBG_HPET_MEM_REG_VAL@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%rbx, %rdi
	callq	_il_set_bit
	movq	_CSR_HW_IF_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%rbx, %rdi
	callq	_il_set_bit
	movq	(%rbx), %rax
	cmpq	$0, 16(%rax)
	je	LBB0_5
## %bb.1:
	movl	8(%rbx), %edi
	movq	_PCI_EXP_LNKCTL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-20(%rbp), %rdx
	callq	_pcie_capability_read_word
	movq	_PCI_EXP_LNKCTL_ASPM_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CSR_GIO_REG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_CSR_GIO_REG_VAL_L0S_ENABLED@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdx
	testl	%eax, -20(%rbp)
	je	LBB0_3
## %bb.2:
	movq	%rbx, %rdi
	callq	_il_set_bit
	leaq	L_.str.1(%rip), %rdi
	jmp	LBB0_4
LBB0_3:
	movq	%rbx, %rdi
	callq	_il_clear_bit
	leaq	L_.str.2(%rip), %rdi
LBB0_4:
	callq	_D_POWER
LBB0_5:
	movq	(%rbx), %rax
	movq	8(%rax), %rdx
	testq	%rdx, %rdx
	je	LBB0_7
## %bb.6:
	movq	_CSR_ANA_PLL_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_il_set_bit
LBB0_7:
	movq	_CSR_GP_CNTRL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_CSR_GP_CNTRL_REG_FLAG_INIT_DONE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%rbx, %rdi
	callq	_il_set_bit
	movl	(%r14), %esi
	movq	_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%ecx, %edx
	movl	$25000, %r8d                    ## imm = 0x61A8
	callq	__il_poll_bit
	movl	%eax, %r14d
	testl	%eax, %eax
	js	LBB0_8
## %bb.9:
	movq	(%rbx), %rax
	xorl	%edx, %edx
	cmpq	$0, (%rax)
	movq	_APMG_CLK_EN_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_CLK_VAL_DMA_CLK_RQT@GOTPCREL(%rip), %rax
	je	LBB0_11
## %bb.10:
	movq	_APMG_CLK_VAL_BSM_CLK_RQT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
LBB0_11:
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_il_wr_prph
	movl	$20, %edi
	callq	_udelay
	movq	_APMG_PCIDEV_STT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_il_set_bits_prph
	jmp	LBB0_12
LBB0_8:
	leaq	L_.str.3(%rip), %rdi
	callq	_D_INFO
LBB0_12:
	movl	%r14d, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Init card's basic functions\n"

	.comm	_CSR_GIO_CHICKEN_BITS,4,2       ## @CSR_GIO_CHICKEN_BITS
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER,8,3 ## @CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX,8,3 ## @CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
	.comm	_CSR_DBG_HPET_MEM_REG,4,2       ## @CSR_DBG_HPET_MEM_REG
	.comm	_CSR_DBG_HPET_MEM_REG_VAL,8,3   ## @CSR_DBG_HPET_MEM_REG_VAL
	.comm	_CSR_HW_IF_CONFIG_REG,4,2       ## @CSR_HW_IF_CONFIG_REG
	.comm	_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A,8,3 ## @CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
	.comm	_PCI_EXP_LNKCTL,4,2             ## @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_ASPM_L1,4,2     ## @PCI_EXP_LNKCTL_ASPM_L1
	.comm	_CSR_GIO_REG,4,2                ## @CSR_GIO_REG
	.comm	_CSR_GIO_REG_VAL_L0S_ENABLED,8,3 ## @CSR_GIO_REG_VAL_L0S_ENABLED
L_.str.1:                               ## @.str.1
	.asciz	"L1 Enabled; Disabling L0S\n"

L_.str.2:                               ## @.str.2
	.asciz	"L1 Disabled; Enabling L0S\n"

	.comm	_CSR_ANA_PLL_CFG,4,2            ## @CSR_ANA_PLL_CFG
	.comm	_CSR_GP_CNTRL,4,2               ## @CSR_GP_CNTRL
	.comm	_CSR_GP_CNTRL_REG_FLAG_INIT_DONE,8,3 ## @CSR_GP_CNTRL_REG_FLAG_INIT_DONE
	.comm	_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,4,2 ## @CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
L_.str.3:                               ## @.str.3
	.asciz	"Failed to init the card\n"

	.comm	_APMG_CLK_EN_REG,4,2            ## @APMG_CLK_EN_REG
	.comm	_APMG_CLK_VAL_DMA_CLK_RQT,4,2   ## @APMG_CLK_VAL_DMA_CLK_RQT
	.comm	_APMG_CLK_VAL_BSM_CLK_RQT,4,2   ## @APMG_CLK_VAL_BSM_CLK_RQT
	.comm	_APMG_PCIDEV_STT_REG,4,2        ## @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS,4,2 ## @APMG_PCIDEV_STT_VAL_L1_ACT_DIS
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_il_apm_init                    ; -- Begin function il_apm_init
	.p2align	2
_il_apm_init:                           ; @il_apm_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_D_INFO
Lloh2:
	adrp	x20, _CSR_GIO_CHICKEN_BITS@GOTPAGE
Lloh3:
	ldr	x20, [x20, _CSR_GIO_CHICKEN_BITS@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh4:
	adrp	x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER@GOTPAGE
Lloh5:
	ldr	x8, [x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER@GOTPAGEOFF]
Lloh6:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_il_set_bit
	ldr	w1, [x20]
Lloh7:
	adrp	x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX@GOTPAGE
Lloh8:
	ldr	x8, [x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX@GOTPAGEOFF]
Lloh9:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_il_set_bit
Lloh10:
	adrp	x8, _CSR_DBG_HPET_MEM_REG@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CSR_DBG_HPET_MEM_REG@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
Lloh13:
	adrp	x8, _CSR_DBG_HPET_MEM_REG_VAL@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CSR_DBG_HPET_MEM_REG_VAL@GOTPAGEOFF]
Lloh15:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_il_set_bit
Lloh16:
	adrp	x8, _CSR_HW_IF_CONFIG_REG@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CSR_HW_IF_CONFIG_REG@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
Lloh19:
	adrp	x8, _CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A@GOTPAGE
Lloh20:
	ldr	x8, [x8, _CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A@GOTPAGEOFF]
Lloh21:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_il_set_bit
	ldr	x8, [x19]
	ldr	x8, [x8, #16]
	cbz	x8, LBB0_5
; %bb.1:
	ldr	w0, [x19, #8]
Lloh22:
	adrp	x8, _PCI_EXP_LNKCTL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PCI_EXP_LNKCTL@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	add	x2, sp, #12
	bl	_pcie_capability_read_word
	ldr	w8, [sp, #12]
Lloh25:
	adrp	x9, _PCI_EXP_LNKCTL_ASPM_L1@GOTPAGE
Lloh26:
	ldr	x9, [x9, _PCI_EXP_LNKCTL_ASPM_L1@GOTPAGEOFF]
Lloh27:
	adrp	x10, _CSR_GIO_REG@GOTPAGE
Lloh28:
	ldr	x10, [x10, _CSR_GIO_REG@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	ldr	w1, [x10]
Lloh31:
	adrp	x10, _CSR_GIO_REG_VAL_L0S_ENABLED@GOTPAGE
Lloh32:
	ldr	x10, [x10, _CSR_GIO_REG_VAL_L0S_ENABLED@GOTPAGEOFF]
Lloh33:
	ldr	x2, [x10]
	mov	x0, x19
	tst	w9, w8
	b.eq	LBB0_3
; %bb.2:
	bl	_il_set_bit
Lloh34:
	adrp	x0, l_.str.1@PAGE
Lloh35:
	add	x0, x0, l_.str.1@PAGEOFF
	b	LBB0_4
LBB0_3:
	bl	_il_clear_bit
Lloh36:
	adrp	x0, l_.str.2@PAGE
Lloh37:
	add	x0, x0, l_.str.2@PAGEOFF
LBB0_4:
	bl	_D_POWER
LBB0_5:
	ldr	x8, [x19]
	ldr	x2, [x8, #8]
	cbz	x2, LBB0_7
; %bb.6:
Lloh38:
	adrp	x8, _CSR_ANA_PLL_CFG@GOTPAGE
Lloh39:
	ldr	x8, [x8, _CSR_ANA_PLL_CFG@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_il_set_bit
LBB0_7:
Lloh41:
	adrp	x20, _CSR_GP_CNTRL@GOTPAGE
Lloh42:
	ldr	x20, [x20, _CSR_GP_CNTRL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh43:
	adrp	x8, _CSR_GP_CNTRL_REG_FLAG_INIT_DONE@GOTPAGE
Lloh44:
	ldr	x8, [x8, _CSR_GP_CNTRL_REG_FLAG_INIT_DONE@GOTPAGEOFF]
Lloh45:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_il_set_bit
	ldr	w1, [x20]
Lloh46:
	adrp	x8, _CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	mov	w4, #25000
	bl	__il_poll_bit
	mov	x20, x0
	tbnz	w0, #31, LBB0_9
; %bb.8:
	ldr	x8, [x19]
	ldr	x8, [x8]
Lloh49:
	adrp	x9, _APMG_CLK_EN_REG@GOTPAGE
Lloh50:
	ldr	x9, [x9, _APMG_CLK_EN_REG@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x9]
Lloh52:
	adrp	x9, _APMG_CLK_VAL_DMA_CLK_RQT@GOTPAGE
Lloh53:
	ldr	x9, [x9, _APMG_CLK_VAL_DMA_CLK_RQT@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
Lloh55:
	adrp	x10, _APMG_CLK_VAL_BSM_CLK_RQT@GOTPAGE
Lloh56:
	ldr	x10, [x10, _APMG_CLK_VAL_BSM_CLK_RQT@GOTPAGEOFF]
Lloh57:
	ldr	w10, [x10]
	cmp	x8, #0
	csel	w8, wzr, w10, eq
	orr	w2, w9, w8
	mov	x0, x19
	bl	_il_wr_prph
	mov	w0, #20
	bl	_udelay
Lloh58:
	adrp	x8, _APMG_PCIDEV_STT_REG@GOTPAGE
Lloh59:
	ldr	x8, [x8, _APMG_PCIDEV_STT_REG@GOTPAGEOFF]
Lloh60:
	ldr	w1, [x8]
Lloh61:
	adrp	x8, _APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPAGE
Lloh62:
	ldr	x8, [x8, _APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_il_set_bits_prph
	b	LBB0_10
LBB0_9:
Lloh64:
	adrp	x0, l_.str.3@PAGE
Lloh65:
	add	x0, x0, l_.str.3@PAGEOFF
	bl	_D_INFO
LBB0_10:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpAdd	Lloh34, Lloh35
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpAdd	Lloh64, Lloh65
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Init card's basic functions\n"

	.comm	_CSR_GIO_CHICKEN_BITS,4,2       ; @CSR_GIO_CHICKEN_BITS
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER,8,3 ; @CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX,8,3 ; @CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
	.comm	_CSR_DBG_HPET_MEM_REG,4,2       ; @CSR_DBG_HPET_MEM_REG
	.comm	_CSR_DBG_HPET_MEM_REG_VAL,8,3   ; @CSR_DBG_HPET_MEM_REG_VAL
	.comm	_CSR_HW_IF_CONFIG_REG,4,2       ; @CSR_HW_IF_CONFIG_REG
	.comm	_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A,8,3 ; @CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
	.comm	_PCI_EXP_LNKCTL,4,2             ; @PCI_EXP_LNKCTL
	.comm	_PCI_EXP_LNKCTL_ASPM_L1,4,2     ; @PCI_EXP_LNKCTL_ASPM_L1
	.comm	_CSR_GIO_REG,4,2                ; @CSR_GIO_REG
	.comm	_CSR_GIO_REG_VAL_L0S_ENABLED,8,3 ; @CSR_GIO_REG_VAL_L0S_ENABLED
l_.str.1:                               ; @.str.1
	.asciz	"L1 Enabled; Disabling L0S\n"

l_.str.2:                               ; @.str.2
	.asciz	"L1 Disabled; Enabling L0S\n"

	.comm	_CSR_ANA_PLL_CFG,4,2            ; @CSR_ANA_PLL_CFG
	.comm	_CSR_GP_CNTRL,4,2               ; @CSR_GP_CNTRL
	.comm	_CSR_GP_CNTRL_REG_FLAG_INIT_DONE,8,3 ; @CSR_GP_CNTRL_REG_FLAG_INIT_DONE
	.comm	_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,4,2 ; @CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
l_.str.3:                               ; @.str.3
	.asciz	"Failed to init the card\n"

	.comm	_APMG_CLK_EN_REG,4,2            ; @APMG_CLK_EN_REG
	.comm	_APMG_CLK_VAL_DMA_CLK_RQT,4,2   ; @APMG_CLK_VAL_DMA_CLK_RQT
	.comm	_APMG_CLK_VAL_BSM_CLK_RQT,4,2   ; @APMG_CLK_VAL_BSM_CLK_RQT
	.comm	_APMG_PCIDEV_STT_REG,4,2        ; @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS,4,2 ; @APMG_PCIDEV_STT_VAL_L1_ACT_DIS
.subsections_via_symbols
