	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ath5k_hw_reset_tx_queue        ## -- Begin function ath5k_hw_reset_tx_queue
	.p2align	4, 0x90
_ath5k_hw_reset_tx_queue:               ## @ath5k_hw_reset_tx_queue
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	movq	64(%rdi), %r13
	movl	56(%rdi), %esi
	movl	%r14d, %edi
	callq	_AR5K_ASSERT_ENTRY
	movq	(%r15), %rax
	movq	_AR5K_AR5210@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_45
## %bb.1:
	movl	%r14d, %eax
	leaq	(%rax,%rax,8), %r12
	movl	(%r13,%r12,4), %eax
	movq	_AR5K_TX_QUEUE_INACTIVE@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_45
## %bb.2:
	movl	4(%r13,%r12,4), %edi
	movq	_AR5K_DCU_LCL_IFS_CW_MIN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movl	8(%r13,%r12,4), %edi
	movq	_AR5K_DCU_LCL_IFS_CW_MAX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movl	12(%r13,%r12,4), %edi
	movq	_AR5K_DCU_LCL_IFS_AIFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_LOCAL_IFS
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_ath5k_hw_set_tx_retry_limits
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_MISC
	movq	_AR5K_DCU_MISC_FRAG_WAIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
	movq	8(%r15), %rax
	movq	_AR5K_SREV_AR5211@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_4
## %bb.3:
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_MISC
	movq	_AR5K_DCU_MISC_SEQNUM_CTL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
LBB0_4:
	movl	16(%r13,%r12,4), %edi
	testl	%edi, %edi
	je	LBB0_7
## %bb.5:
	movq	_AR5K_QCU_CBRCFG_INTVAL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movl	20(%r13,%r12,4), %edi
	movq	_AR5K_QCU_CBRCFG_ORN_THRES@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_CBRCFG
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_MISC
	movq	_AR5K_QCU_MISC_FRSHED_CBR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
	cmpl	$0, 20(%r13,%r12,4)
	je	LBB0_7
## %bb.6:
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_MISC
	movq	_AR5K_QCU_MISC_CBR_THRES_ENABLE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
LBB0_7:
	leaq	(,%r12,4), %rax
	addq	%r13, %rax
	movq	%rax, -56(%rbp)                 ## 8-byte Spill
	movl	24(%r13,%r12,4), %edi
	testl	%edi, %edi
	je	LBB0_10
## %bb.8:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	cmpl	$130, (%rax)
	je	LBB0_10
## %bb.9:
	movq	_AR5K_QCU_RDYTIMECFG_INTVAL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movq	_AR5K_QCU_RDYTIMECFG_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_RDYTIMECFG
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
LBB0_10:
	movl	28(%r13,%r12,4), %edi
	testl	%edi, %edi
	je	LBB0_13
## %bb.11:
	movq	_AR5K_DCU_CHAN_TIME_DUR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movq	_AR5K_DCU_CHAN_TIME_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_CHANNEL_TIME
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
	movq	_AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, 32(%r13,%r12,4)
	je	LBB0_13
## %bb.12:
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_MISC
	movq	_AR5K_QCU_MISC_RDY_VEOL_POLICY@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
LBB0_13:
	leaq	32(,%r12,4), %rbx
	addq	%r13, %rbx
	movl	32(%r13,%r12,4), %eax
	movq	_AR5K_TXQ_FLAG_BACKOFF_DISABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	je	LBB0_15
## %bb.14:
	movq	_AR5K_DCU_MISC_POST_FR_BKOFF_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_MISC
	movq	%r15, %rdi
	movl	%ebx, %esi
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
	movl	(%rbx), %eax
LBB0_15:
	movq	_AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_17
## %bb.16:
	movq	_AR5K_DCU_MISC_BACKOFF_FRAG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_MISC
	movq	%r15, %rdi
	movl	%ebx, %esi
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
LBB0_17:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %eax
	cmpl	$128, %eax
	je	LBB0_22
## %bb.18:
	cmpl	$130, %eax
	je	LBB0_21
## %bb.19:
	cmpl	$131, %eax
	jne	LBB0_24
## %bb.20:
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_MISC
	movq	_AR5K_QCU_MISC_FRSHED_DBA_GT@GOTPCREL(%rip), %rcx
	movq	_AR5K_QCU_MISC_CBREXP_BCN_DIS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_AR5K_QCU_MISC_BCN_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_MISC
	movq	_AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_AR5K_DCU_MISC_ARBLOCK_CTL_S@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
	movq	_AR5K_DCU_MISC_ARBLOCK_IGNORE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_AR5K_DCU_MISC_POST_FR_BKOFF_DIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	_AR5K_DCU_MISC_BCN_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	jmp	LBB0_23
LBB0_22:
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_MISC
	movq	_AR5K_QCU_MISC_CBREXP_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	jmp	LBB0_23
LBB0_21:
	leaq	24(,%r12,4), %rbx
	addq	%r13, %rbx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_MISC
	movq	_AR5K_QCU_MISC_FRSHED_DBA_GT@GOTPCREL(%rip), %rcx
	movq	_AR5K_QCU_MISC_CBREXP_DIS@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_AR5K_QCU_MISC_CBREXP_BCN_DIS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
	movl	(%rbx), %ebx
	movq	_AR5K_TUNE_SW_BEACON_RESP@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_AR5K_TUNE_DMA_BEACON_RESP@GOTPCREL(%rip), %rcx
	addl	(%rcx), %ebx
	movq	_AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF@GOTPCREL(%rip), %rcx
	addl	(%rcx), %eax
	subl	%eax, %ebx
	shll	$10, %ebx
	movq	_AR5K_QCU_RDYTIMECFG_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_RDYTIMECFG
	movq	%r15, %rdi
	movl	%ebx, %esi
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	%eax, %edx
	callq	_ath5k_hw_reg_write
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_DFS_MISC
	movq	_AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_AR5K_DCU_MISC_ARBLOCK_CTL_S@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edx
LBB0_23:
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_AR5K_REG_ENABLE_BITS
LBB0_24:
	movl	(%rbx), %eax
	movq	_AR5K_TXQ_FLAG_TXOKINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_26
## %bb.25:
	movl	16(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_26:
	movq	_AR5K_TXQ_FLAG_TXERRINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_28
## %bb.27:
	movl	20(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_28:
	movq	_AR5K_TXQ_FLAG_TXURNINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_30
## %bb.29:
	movl	24(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_30:
	movq	_AR5K_TXQ_FLAG_TXDESCINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_32
## %bb.31:
	movl	28(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_32:
	movq	_AR5K_TXQ_FLAG_TXEOLINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_34
## %bb.33:
	movl	32(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_34:
	movq	_AR5K_TXQ_FLAG_CBRORNINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_36
## %bb.35:
	movl	36(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_36:
	movq	_AR5K_TXQ_FLAG_CBRURNINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_38
## %bb.37:
	movl	40(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_38:
	movq	_AR5K_TXQ_FLAG_QTRIGINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_40
## %bb.39:
	movl	44(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
	movl	(%rbx), %eax
LBB0_40:
	movq	_AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_42
## %bb.41:
	movl	48(%r15), %edi
	movl	%r14d, %esi
	callq	_AR5K_Q_ENABLE_BITS
LBB0_42:
	movl	52(%r15), %eax
	movd	%eax, %xmm0
	pshufd	$0, %xmm0, %xmm0                ## xmm0 = xmm0[0,0,0,0]
	movdqu	16(%r15), %xmm1
	movdqu	32(%r15), %xmm2
	pand	%xmm0, %xmm1
	movdqu	%xmm1, 16(%r15)
	pand	%xmm0, %xmm2
	movdqu	%xmm2, 32(%r15)
	andl	%eax, 48(%r15)
	movq	_AR5K_SIMR0_QCU_TXOK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movd	%xmm1, %edi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movl	28(%r15), %edi
	movq	_AR5K_SIMR0_QCU_TXDESC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movq	_AR5K_SIMR0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ath5k_hw_reg_write
	movl	20(%r15), %edi
	movq	_AR5K_SIMR1_QCU_TXERR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movl	32(%r15), %edi
	movq	_AR5K_SIMR1_QCU_TXEOL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movq	_AR5K_SIMR1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ath5k_hw_reg_write
	movq	_AR5K_SIMR2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR5K_SIMR2_QCU_TXURN@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_AR5K_REG_DISABLE_BITS
	movl	(%rbx), %ebx
	movl	24(%r15), %edi
	movl	(%r12), %esi
	callq	_AR5K_REG_SM
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_AR5K_REG_ENABLE_BITS
	movl	36(%r15), %edi
	movq	_AR5K_SIMR3_QCBRORN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %ebx
	movl	40(%r15), %edi
	movq	_AR5K_SIMR3_QCBRURN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	orl	%eax, %ebx
	movq	_AR5K_SIMR3@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_ath5k_hw_reg_write
	movl	44(%r15), %edi
	movq	_AR5K_SIMR4_QTRIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movq	_AR5K_SIMR4@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_ath5k_hw_reg_write
	movl	48(%r15), %edi
	movq	_AR5K_TXNOFRM_QCU@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movq	_AR5K_TXNOFRM@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_ath5k_hw_reg_write
	cmpl	$0, 48(%r15)
	jne	LBB0_44
## %bb.43:
	movl	(%rbx), %edx
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_ath5k_hw_reg_write
LBB0_44:
	movl	%r14d, %edi
	callq	_AR5K_QUEUE_QCUMASK
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%r14d, %edx
	callq	_AR5K_REG_WRITE_Q
LBB0_45:
	xorl	%eax, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR5K_AR5210,8,3                ## @AR5K_AR5210
	.comm	_AR5K_TX_QUEUE_INACTIVE,4,2     ## @AR5K_TX_QUEUE_INACTIVE
	.comm	_AR5K_DCU_LCL_IFS_CW_MIN,4,2    ## @AR5K_DCU_LCL_IFS_CW_MIN
	.comm	_AR5K_DCU_LCL_IFS_CW_MAX,4,2    ## @AR5K_DCU_LCL_IFS_CW_MAX
	.comm	_AR5K_DCU_LCL_IFS_AIFS,4,2      ## @AR5K_DCU_LCL_IFS_AIFS
	.comm	_AR5K_DCU_MISC_FRAG_WAIT,4,2    ## @AR5K_DCU_MISC_FRAG_WAIT
	.comm	_AR5K_SREV_AR5211,8,3           ## @AR5K_SREV_AR5211
	.comm	_AR5K_DCU_MISC_SEQNUM_CTL,4,2   ## @AR5K_DCU_MISC_SEQNUM_CTL
	.comm	_AR5K_QCU_CBRCFG_INTVAL,4,2     ## @AR5K_QCU_CBRCFG_INTVAL
	.comm	_AR5K_QCU_CBRCFG_ORN_THRES,4,2  ## @AR5K_QCU_CBRCFG_ORN_THRES
	.comm	_AR5K_QCU_MISC_FRSHED_CBR,4,2   ## @AR5K_QCU_MISC_FRSHED_CBR
	.comm	_AR5K_QCU_MISC_CBR_THRES_ENABLE,4,2 ## @AR5K_QCU_MISC_CBR_THRES_ENABLE
	.comm	_AR5K_QCU_RDYTIMECFG_INTVAL,4,2 ## @AR5K_QCU_RDYTIMECFG_INTVAL
	.comm	_AR5K_QCU_RDYTIMECFG_ENABLE,4,2 ## @AR5K_QCU_RDYTIMECFG_ENABLE
	.comm	_AR5K_DCU_CHAN_TIME_DUR,4,2     ## @AR5K_DCU_CHAN_TIME_DUR
	.comm	_AR5K_DCU_CHAN_TIME_ENABLE,4,2  ## @AR5K_DCU_CHAN_TIME_ENABLE
	.comm	_AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE,4,2 ## @AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
	.comm	_AR5K_QCU_MISC_RDY_VEOL_POLICY,4,2 ## @AR5K_QCU_MISC_RDY_VEOL_POLICY
	.comm	_AR5K_TXQ_FLAG_BACKOFF_DISABLE,4,2 ## @AR5K_TXQ_FLAG_BACKOFF_DISABLE
	.comm	_AR5K_DCU_MISC_POST_FR_BKOFF_DIS,4,2 ## @AR5K_DCU_MISC_POST_FR_BKOFF_DIS
	.comm	_AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE,4,2 ## @AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
	.comm	_AR5K_DCU_MISC_BACKOFF_FRAG,4,2 ## @AR5K_DCU_MISC_BACKOFF_FRAG
	.comm	_AR5K_QCU_MISC_FRSHED_DBA_GT,4,2 ## @AR5K_QCU_MISC_FRSHED_DBA_GT
	.comm	_AR5K_QCU_MISC_CBREXP_BCN_DIS,4,2 ## @AR5K_QCU_MISC_CBREXP_BCN_DIS
	.comm	_AR5K_QCU_MISC_BCN_ENABLE,4,2   ## @AR5K_QCU_MISC_BCN_ENABLE
	.comm	_AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL,4,2 ## @AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL
	.comm	_AR5K_DCU_MISC_ARBLOCK_CTL_S,4,2 ## @AR5K_DCU_MISC_ARBLOCK_CTL_S
	.comm	_AR5K_DCU_MISC_ARBLOCK_IGNORE,4,2 ## @AR5K_DCU_MISC_ARBLOCK_IGNORE
	.comm	_AR5K_DCU_MISC_BCN_ENABLE,4,2   ## @AR5K_DCU_MISC_BCN_ENABLE
	.comm	_AR5K_QCU_MISC_CBREXP_DIS,4,2   ## @AR5K_QCU_MISC_CBREXP_DIS
	.comm	_AR5K_TUNE_SW_BEACON_RESP,4,2   ## @AR5K_TUNE_SW_BEACON_RESP
	.comm	_AR5K_TUNE_DMA_BEACON_RESP,4,2  ## @AR5K_TUNE_DMA_BEACON_RESP
	.comm	_AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF,4,2 ## @AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF
	.comm	_AR5K_TXQ_FLAG_TXOKINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_TXOKINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXERRINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_TXERRINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXURNINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_TXURNINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXDESCINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_TXDESCINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXEOLINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_TXEOLINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_CBRORNINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_CBRORNINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_CBRURNINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_CBRURNINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_QTRIGINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_QTRIGINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE,4,2 ## @AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE
	.comm	_AR5K_SIMR0_QCU_TXOK,4,2        ## @AR5K_SIMR0_QCU_TXOK
	.comm	_AR5K_SIMR0_QCU_TXDESC,4,2      ## @AR5K_SIMR0_QCU_TXDESC
	.comm	_AR5K_SIMR0,4,2                 ## @AR5K_SIMR0
	.comm	_AR5K_SIMR1_QCU_TXERR,4,2       ## @AR5K_SIMR1_QCU_TXERR
	.comm	_AR5K_SIMR1_QCU_TXEOL,4,2       ## @AR5K_SIMR1_QCU_TXEOL
	.comm	_AR5K_SIMR1,4,2                 ## @AR5K_SIMR1
	.comm	_AR5K_SIMR2,4,2                 ## @AR5K_SIMR2
	.comm	_AR5K_SIMR2_QCU_TXURN,4,2       ## @AR5K_SIMR2_QCU_TXURN
	.comm	_AR5K_SIMR3_QCBRORN,4,2         ## @AR5K_SIMR3_QCBRORN
	.comm	_AR5K_SIMR3_QCBRURN,4,2         ## @AR5K_SIMR3_QCBRURN
	.comm	_AR5K_SIMR3,4,2                 ## @AR5K_SIMR3
	.comm	_AR5K_SIMR4_QTRIG,4,2           ## @AR5K_SIMR4_QTRIG
	.comm	_AR5K_SIMR4,4,2                 ## @AR5K_SIMR4
	.comm	_AR5K_TXNOFRM_QCU,4,2           ## @AR5K_TXNOFRM_QCU
	.comm	_AR5K_TXNOFRM,4,2               ## @AR5K_TXNOFRM
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ath5k_hw_reset_tx_queue        ; -- Begin function ath5k_hw_reset_tx_queue
	.p2align	2
_ath5k_hw_reset_tx_queue:               ; @ath5k_hw_reset_tx_queue
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x1
	mov	x20, x0
	ldr	x22, [x0, #64]
	ldr	w1, [x0, #56]
	mov	x0, x19
	bl	_AR5K_ASSERT_ENTRY
	ldr	x8, [x20]
Lloh0:
	adrp	x9, _AR5K_AR5210@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AR5K_AR5210@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_45
; %bb.1:
	mov	w24, w19
	mov	w8, #36
	madd	x23, x24, x8, x22
	ldr	w8, [x23]
Lloh3:
	adrp	x9, _AR5K_TX_QUEUE_INACTIVE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AR5K_TX_QUEUE_INACTIVE@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	cmp	w8, w9
	b.eq	LBB0_45
; %bb.2:
	mov	w8, #36
	madd	x25, x24, x8, x22
	ldr	w0, [x25, #4]
Lloh6:
	adrp	x8, _AR5K_DCU_LCL_IFS_CW_MIN@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AR5K_DCU_LCL_IFS_CW_MIN@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x21, x0
	ldr	w0, [x25, #8]
Lloh9:
	adrp	x8, _AR5K_DCU_LCL_IFS_CW_MAX@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AR5K_DCU_LCL_IFS_CW_MAX@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w21, w0, w21
	ldr	w0, [x25, #12]
Lloh12:
	adrp	x8, _AR5K_DCU_LCL_IFS_AIFS@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AR5K_DCU_LCL_IFS_AIFS@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w21, w21, w0
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_LOCAL_IFS
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
	mov	x0, x20
	mov	x1, x19
	bl	_ath5k_hw_set_tx_retry_limits
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_MISC
	mov	x1, x0
Lloh15:
	adrp	x8, _AR5K_DCU_MISC_FRAG_WAIT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AR5K_DCU_MISC_FRAG_WAIT@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
	ldr	x8, [x20, #8]
Lloh18:
	adrp	x9, _AR5K_SREV_AR5211@GOTPAGE
Lloh19:
	ldr	x9, [x9, _AR5K_SREV_AR5211@GOTPAGEOFF]
Lloh20:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_4
; %bb.3:
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_MISC
	mov	x1, x0
Lloh21:
	adrp	x8, _AR5K_DCU_MISC_SEQNUM_CTL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AR5K_DCU_MISC_SEQNUM_CTL@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
LBB0_4:
	mov	w8, #36
	madd	x8, x24, x8, x22
	ldr	w0, [x8, #16]
	cbz	w0, LBB0_7
; %bb.5:
Lloh24:
	adrp	x8, _AR5K_QCU_CBRCFG_INTVAL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _AR5K_QCU_CBRCFG_INTVAL@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x21, x0
	mov	w8, #36
	madd	x25, x24, x8, x22
	ldr	w0, [x25, #20]
Lloh27:
	adrp	x8, _AR5K_QCU_CBRCFG_ORN_THRES@GOTPAGE
Lloh28:
	ldr	x8, [x8, _AR5K_QCU_CBRCFG_ORN_THRES@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w21, w0, w21
	mov	x0, x19
	bl	_AR5K_QUEUE_CBRCFG
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
	mov	x0, x19
	bl	_AR5K_QUEUE_MISC
	mov	x1, x0
Lloh30:
	adrp	x8, _AR5K_QCU_MISC_FRSHED_CBR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _AR5K_QCU_MISC_FRSHED_CBR@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
	ldr	w8, [x25, #20]
	cbz	w8, LBB0_7
; %bb.6:
	mov	x0, x19
	bl	_AR5K_QUEUE_MISC
	mov	x1, x0
Lloh33:
	adrp	x8, _AR5K_QCU_MISC_CBR_THRES_ENABLE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AR5K_QCU_MISC_CBR_THRES_ENABLE@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
LBB0_7:
	mov	w8, #36
	madd	x25, x24, x8, x22
	ldr	w0, [x25, #24]!
	cbz	w0, LBB0_10
; %bb.8:
	ldr	w8, [x23]
	cmp	w8, #130
	b.eq	LBB0_10
; %bb.9:
Lloh36:
	adrp	x8, _AR5K_QCU_RDYTIMECFG_INTVAL@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AR5K_QCU_RDYTIMECFG_INTVAL@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
Lloh39:
	adrp	x8, _AR5K_QCU_RDYTIMECFG_ENABLE@GOTPAGE
Lloh40:
	ldr	x8, [x8, _AR5K_QCU_RDYTIMECFG_ENABLE@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	orr	w21, w8, w0
	mov	x0, x19
	bl	_AR5K_QUEUE_RDYTIMECFG
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
LBB0_10:
	mov	w8, #36
	madd	x8, x24, x8, x22
	ldr	w0, [x8, #28]
	cbz	w0, LBB0_13
; %bb.11:
Lloh42:
	adrp	x8, _AR5K_DCU_CHAN_TIME_DUR@GOTPAGE
Lloh43:
	ldr	x8, [x8, _AR5K_DCU_CHAN_TIME_DUR@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
Lloh45:
	adrp	x8, _AR5K_DCU_CHAN_TIME_ENABLE@GOTPAGE
Lloh46:
	ldr	x8, [x8, _AR5K_DCU_CHAN_TIME_ENABLE@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	orr	w21, w8, w0
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_CHANNEL_TIME
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
	mov	w8, #36
	madd	x8, x24, x8, x22
	ldr	w8, [x8, #32]
Lloh48:
	adrp	x9, _AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE@GOTPAGE
Lloh49:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE@GOTPAGEOFF]
Lloh50:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_13
; %bb.12:
	mov	x0, x19
	bl	_AR5K_QUEUE_MISC
	mov	x1, x0
Lloh51:
	adrp	x8, _AR5K_QCU_MISC_RDY_VEOL_POLICY@GOTPAGE
Lloh52:
	ldr	x8, [x8, _AR5K_QCU_MISC_RDY_VEOL_POLICY@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
LBB0_13:
	mov	w8, #36
	madd	x22, x24, x8, x22
	ldr	w8, [x22, #32]!
Lloh54:
	adrp	x9, _AR5K_TXQ_FLAG_BACKOFF_DISABLE@GOTPAGE
Lloh55:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_BACKOFF_DISABLE@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_15
; %bb.14:
Lloh57:
	adrp	x8, _AR5K_DCU_MISC_POST_FR_BKOFF_DIS@GOTPAGE
Lloh58:
	ldr	x8, [x8, _AR5K_DCU_MISC_POST_FR_BKOFF_DIS@GOTPAGEOFF]
Lloh59:
	ldr	w21, [x8]
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_MISC
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
	ldr	w8, [x22]
LBB0_15:
Lloh60:
	adrp	x9, _AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE@GOTPAGE
Lloh61:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE@GOTPAGEOFF]
Lloh62:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_17
; %bb.16:
Lloh63:
	adrp	x8, _AR5K_DCU_MISC_BACKOFF_FRAG@GOTPAGE
Lloh64:
	ldr	x8, [x8, _AR5K_DCU_MISC_BACKOFF_FRAG@GOTPAGEOFF]
Lloh65:
	ldr	w21, [x8]
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_MISC
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
LBB0_17:
	ldr	w8, [x23]
	cmp	w8, #128
	b.eq	LBB0_21
; %bb.18:
	cmp	w8, #130
	b.eq	LBB0_22
; %bb.19:
	cmp	w8, #131
	b.ne	LBB0_24
; %bb.20:
	mov	x0, x19
	bl	_AR5K_QUEUE_MISC
	mov	x1, x0
Lloh66:
	adrp	x8, _AR5K_QCU_MISC_FRSHED_DBA_GT@GOTPAGE
Lloh67:
	ldr	x8, [x8, _AR5K_QCU_MISC_FRSHED_DBA_GT@GOTPAGEOFF]
Lloh68:
	ldr	w8, [x8]
Lloh69:
	adrp	x9, _AR5K_QCU_MISC_CBREXP_BCN_DIS@GOTPAGE
Lloh70:
	ldr	x9, [x9, _AR5K_QCU_MISC_CBREXP_BCN_DIS@GOTPAGEOFF]
Lloh71:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh72:
	adrp	x9, _AR5K_QCU_MISC_BCN_ENABLE@GOTPAGE
Lloh73:
	ldr	x9, [x9, _AR5K_QCU_MISC_BCN_ENABLE@GOTPAGEOFF]
Lloh74:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_MISC
	mov	x1, x0
Lloh75:
	adrp	x8, _AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL@GOTPAGE
Lloh76:
	ldr	x8, [x8, _AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL@GOTPAGEOFF]
Lloh77:
	ldr	w8, [x8]
Lloh78:
	adrp	x9, _AR5K_DCU_MISC_ARBLOCK_CTL_S@GOTPAGE
Lloh79:
	ldr	x9, [x9, _AR5K_DCU_MISC_ARBLOCK_CTL_S@GOTPAGEOFF]
Lloh80:
	ldr	w9, [x9]
	lsl	w8, w8, w9
Lloh81:
	adrp	x9, _AR5K_DCU_MISC_ARBLOCK_IGNORE@GOTPAGE
Lloh82:
	ldr	x9, [x9, _AR5K_DCU_MISC_ARBLOCK_IGNORE@GOTPAGEOFF]
Lloh83:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh84:
	adrp	x9, _AR5K_DCU_MISC_POST_FR_BKOFF_DIS@GOTPAGE
Lloh85:
	ldr	x9, [x9, _AR5K_DCU_MISC_POST_FR_BKOFF_DIS@GOTPAGEOFF]
Lloh86:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh87:
	adrp	x9, _AR5K_DCU_MISC_BCN_ENABLE@GOTPAGE
Lloh88:
	ldr	x9, [x9, _AR5K_DCU_MISC_BCN_ENABLE@GOTPAGEOFF]
Lloh89:
	ldr	w9, [x9]
	orr	w2, w8, w9
	b	LBB0_23
LBB0_21:
	mov	x0, x19
	bl	_AR5K_QUEUE_MISC
	mov	x1, x0
Lloh90:
	adrp	x8, _AR5K_QCU_MISC_CBREXP_DIS@GOTPAGE
Lloh91:
	ldr	x8, [x8, _AR5K_QCU_MISC_CBREXP_DIS@GOTPAGEOFF]
Lloh92:
	ldr	w2, [x8]
	b	LBB0_23
LBB0_22:
	mov	x0, x19
	bl	_AR5K_QUEUE_MISC
	mov	x1, x0
Lloh93:
	adrp	x8, _AR5K_QCU_MISC_FRSHED_DBA_GT@GOTPAGE
Lloh94:
	ldr	x8, [x8, _AR5K_QCU_MISC_FRSHED_DBA_GT@GOTPAGEOFF]
Lloh95:
	ldr	w8, [x8]
Lloh96:
	adrp	x9, _AR5K_QCU_MISC_CBREXP_DIS@GOTPAGE
Lloh97:
	ldr	x9, [x9, _AR5K_QCU_MISC_CBREXP_DIS@GOTPAGEOFF]
Lloh98:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh99:
	adrp	x9, _AR5K_QCU_MISC_CBREXP_BCN_DIS@GOTPAGE
Lloh100:
	ldr	x9, [x9, _AR5K_QCU_MISC_CBREXP_BCN_DIS@GOTPAGEOFF]
Lloh101:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
	ldr	w8, [x25]
Lloh102:
	adrp	x9, _AR5K_TUNE_SW_BEACON_RESP@GOTPAGE
Lloh103:
	ldr	x9, [x9, _AR5K_TUNE_SW_BEACON_RESP@GOTPAGEOFF]
Lloh104:
	adrp	x10, _AR5K_TUNE_DMA_BEACON_RESP@GOTPAGE
Lloh105:
	ldr	x10, [x10, _AR5K_TUNE_DMA_BEACON_RESP@GOTPAGEOFF]
Lloh106:
	ldr	w9, [x9]
Lloh107:
	ldr	w10, [x10]
Lloh108:
	adrp	x11, _AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF@GOTPAGE
Lloh109:
	ldr	x11, [x11, _AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF@GOTPAGEOFF]
Lloh110:
	ldr	w11, [x11]
	add	w8, w8, w10
	add	w9, w9, w11
	sub	w8, w8, w9
Lloh111:
	adrp	x9, _AR5K_QCU_RDYTIMECFG_ENABLE@GOTPAGE
Lloh112:
	ldr	x9, [x9, _AR5K_QCU_RDYTIMECFG_ENABLE@GOTPAGEOFF]
Lloh113:
	ldr	w9, [x9]
	orr	w21, w9, w8, lsl #10
	mov	x0, x19
	bl	_AR5K_QUEUE_RDYTIMECFG
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_ath5k_hw_reg_write
	mov	x0, x19
	bl	_AR5K_QUEUE_DFS_MISC
	mov	x1, x0
Lloh114:
	adrp	x8, _AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL@GOTPAGE
Lloh115:
	ldr	x8, [x8, _AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL@GOTPAGEOFF]
Lloh116:
	ldr	w8, [x8]
Lloh117:
	adrp	x9, _AR5K_DCU_MISC_ARBLOCK_CTL_S@GOTPAGE
Lloh118:
	ldr	x9, [x9, _AR5K_DCU_MISC_ARBLOCK_CTL_S@GOTPAGEOFF]
Lloh119:
	ldr	w9, [x9]
	lsl	w2, w8, w9
LBB0_23:
	mov	x0, x20
	bl	_AR5K_REG_ENABLE_BITS
LBB0_24:
	ldr	w8, [x22]
Lloh120:
	adrp	x9, _AR5K_TXQ_FLAG_TXOKINT_ENABLE@GOTPAGE
Lloh121:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_TXOKINT_ENABLE@GOTPAGEOFF]
Lloh122:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_26
; %bb.25:
	ldr	w0, [x20, #16]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_26:
Lloh123:
	adrp	x9, _AR5K_TXQ_FLAG_TXERRINT_ENABLE@GOTPAGE
Lloh124:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_TXERRINT_ENABLE@GOTPAGEOFF]
Lloh125:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_28
; %bb.27:
	ldr	w0, [x20, #20]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_28:
Lloh126:
	adrp	x9, _AR5K_TXQ_FLAG_TXURNINT_ENABLE@GOTPAGE
Lloh127:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_TXURNINT_ENABLE@GOTPAGEOFF]
Lloh128:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_30
; %bb.29:
	ldr	w0, [x20, #24]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_30:
Lloh129:
	adrp	x9, _AR5K_TXQ_FLAG_TXDESCINT_ENABLE@GOTPAGE
Lloh130:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_TXDESCINT_ENABLE@GOTPAGEOFF]
Lloh131:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_32
; %bb.31:
	ldr	w0, [x20, #28]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_32:
Lloh132:
	adrp	x9, _AR5K_TXQ_FLAG_TXEOLINT_ENABLE@GOTPAGE
Lloh133:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_TXEOLINT_ENABLE@GOTPAGEOFF]
Lloh134:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_34
; %bb.33:
	ldr	w0, [x20, #32]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_34:
Lloh135:
	adrp	x9, _AR5K_TXQ_FLAG_CBRORNINT_ENABLE@GOTPAGE
Lloh136:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_CBRORNINT_ENABLE@GOTPAGEOFF]
Lloh137:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_36
; %bb.35:
	ldr	w0, [x20, #36]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_36:
Lloh138:
	adrp	x9, _AR5K_TXQ_FLAG_CBRURNINT_ENABLE@GOTPAGE
Lloh139:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_CBRURNINT_ENABLE@GOTPAGEOFF]
Lloh140:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_38
; %bb.37:
	ldr	w0, [x20, #40]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_38:
Lloh141:
	adrp	x9, _AR5K_TXQ_FLAG_QTRIGINT_ENABLE@GOTPAGE
Lloh142:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_QTRIGINT_ENABLE@GOTPAGEOFF]
Lloh143:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_40
; %bb.39:
	ldr	w0, [x20, #44]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
	ldr	w8, [x22]
LBB0_40:
Lloh144:
	adrp	x9, _AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE@GOTPAGE
Lloh145:
	ldr	x9, [x9, _AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE@GOTPAGEOFF]
Lloh146:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_42
; %bb.41:
	ldr	w0, [x20, #48]
	mov	x1, x19
	bl	_AR5K_Q_ENABLE_BITS
LBB0_42:
	ldp	w9, w8, [x20, #48]
	dup.4s	v0, w8
	ldp	q1, q2, [x20, #16]
	and.16b	v1, v1, v0
	and.16b	v0, v2, v0
	stp	q1, q0, [x20, #16]
	and	w8, w9, w8
	str	w8, [x20, #48]
Lloh147:
	adrp	x8, _AR5K_SIMR0_QCU_TXOK@GOTPAGE
Lloh148:
	ldr	x8, [x8, _AR5K_SIMR0_QCU_TXOK@GOTPAGEOFF]
Lloh149:
	ldr	w1, [x8]
	fmov	w0, s1
	bl	_AR5K_REG_SM
	mov	x21, x0
	ldr	w0, [x20, #28]
Lloh150:
	adrp	x8, _AR5K_SIMR0_QCU_TXDESC@GOTPAGE
Lloh151:
	ldr	x8, [x8, _AR5K_SIMR0_QCU_TXDESC@GOTPAGEOFF]
Lloh152:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w1, w0, w21
Lloh153:
	adrp	x8, _AR5K_SIMR0@GOTPAGE
Lloh154:
	ldr	x8, [x8, _AR5K_SIMR0@GOTPAGEOFF]
Lloh155:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_ath5k_hw_reg_write
	ldr	w0, [x20, #20]
Lloh156:
	adrp	x8, _AR5K_SIMR1_QCU_TXERR@GOTPAGE
Lloh157:
	ldr	x8, [x8, _AR5K_SIMR1_QCU_TXERR@GOTPAGEOFF]
Lloh158:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x21, x0
	ldr	w0, [x20, #32]
Lloh159:
	adrp	x8, _AR5K_SIMR1_QCU_TXEOL@GOTPAGE
Lloh160:
	ldr	x8, [x8, _AR5K_SIMR1_QCU_TXEOL@GOTPAGEOFF]
Lloh161:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w1, w0, w21
Lloh162:
	adrp	x8, _AR5K_SIMR1@GOTPAGE
Lloh163:
	ldr	x8, [x8, _AR5K_SIMR1@GOTPAGEOFF]
Lloh164:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_ath5k_hw_reg_write
Lloh165:
	adrp	x21, _AR5K_SIMR2@GOTPAGE
Lloh166:
	ldr	x21, [x21, _AR5K_SIMR2@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh167:
	adrp	x22, _AR5K_SIMR2_QCU_TXURN@GOTPAGE
Lloh168:
	ldr	x22, [x22, _AR5K_SIMR2_QCU_TXURN@GOTPAGEOFF]
	ldr	w2, [x22]
	mov	x0, x20
	bl	_AR5K_REG_DISABLE_BITS
	ldr	w21, [x21]
	ldr	w0, [x20, #24]
	ldr	w1, [x22]
	bl	_AR5K_REG_SM
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_AR5K_REG_ENABLE_BITS
	ldr	w0, [x20, #36]
Lloh169:
	adrp	x8, _AR5K_SIMR3_QCBRORN@GOTPAGE
Lloh170:
	ldr	x8, [x8, _AR5K_SIMR3_QCBRORN@GOTPAGEOFF]
Lloh171:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x21, x0
	ldr	w0, [x20, #40]
Lloh172:
	adrp	x8, _AR5K_SIMR3_QCBRURN@GOTPAGE
Lloh173:
	ldr	x8, [x8, _AR5K_SIMR3_QCBRURN@GOTPAGEOFF]
Lloh174:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w1, w0, w21
Lloh175:
	adrp	x8, _AR5K_SIMR3@GOTPAGE
Lloh176:
	ldr	x8, [x8, _AR5K_SIMR3@GOTPAGEOFF]
Lloh177:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_ath5k_hw_reg_write
	ldr	w0, [x20, #44]
Lloh178:
	adrp	x8, _AR5K_SIMR4_QTRIG@GOTPAGE
Lloh179:
	ldr	x8, [x8, _AR5K_SIMR4_QTRIG@GOTPAGEOFF]
Lloh180:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x1, x0
Lloh181:
	adrp	x8, _AR5K_SIMR4@GOTPAGE
Lloh182:
	ldr	x8, [x8, _AR5K_SIMR4@GOTPAGEOFF]
Lloh183:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_ath5k_hw_reg_write
	ldr	w0, [x20, #48]
Lloh184:
	adrp	x8, _AR5K_TXNOFRM_QCU@GOTPAGE
Lloh185:
	ldr	x8, [x8, _AR5K_TXNOFRM_QCU@GOTPAGEOFF]
Lloh186:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x1, x0
Lloh187:
	adrp	x21, _AR5K_TXNOFRM@GOTPAGE
Lloh188:
	ldr	x21, [x21, _AR5K_TXNOFRM@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x20
	bl	_ath5k_hw_reg_write
	ldr	w8, [x20, #48]
	cbnz	w8, LBB0_44
; %bb.43:
	ldr	w2, [x21]
	mov	x0, x20
	mov	w1, #0
	bl	_ath5k_hw_reg_write
LBB0_44:
	mov	x0, x19
	bl	_AR5K_QUEUE_QCUMASK
	mov	x1, x0
	mov	x0, x20
	mov	x2, x19
	bl	_AR5K_REG_WRITE_Q
LBB0_45:
	mov	w0, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh106
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.loh AdrpLdrGotLdr	Lloh129, Lloh130, Lloh131
	.loh AdrpLdrGotLdr	Lloh132, Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGotLdr	Lloh138, Lloh139, Lloh140
	.loh AdrpLdrGotLdr	Lloh141, Lloh142, Lloh143
	.loh AdrpLdrGotLdr	Lloh144, Lloh145, Lloh146
	.loh AdrpLdrGot	Lloh187, Lloh188
	.loh AdrpLdrGotLdr	Lloh184, Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh181, Lloh182, Lloh183
	.loh AdrpLdrGotLdr	Lloh178, Lloh179, Lloh180
	.loh AdrpLdrGotLdr	Lloh175, Lloh176, Lloh177
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh174
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGot	Lloh167, Lloh168
	.loh AdrpLdrGot	Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh162, Lloh163, Lloh164
	.loh AdrpLdrGotLdr	Lloh159, Lloh160, Lloh161
	.loh AdrpLdrGotLdr	Lloh156, Lloh157, Lloh158
	.loh AdrpLdrGotLdr	Lloh153, Lloh154, Lloh155
	.loh AdrpLdrGotLdr	Lloh150, Lloh151, Lloh152
	.loh AdrpLdrGotLdr	Lloh147, Lloh148, Lloh149
	.cfi_endproc
                                        ; -- End function
	.comm	_AR5K_AR5210,8,3                ; @AR5K_AR5210
	.comm	_AR5K_TX_QUEUE_INACTIVE,4,2     ; @AR5K_TX_QUEUE_INACTIVE
	.comm	_AR5K_DCU_LCL_IFS_CW_MIN,4,2    ; @AR5K_DCU_LCL_IFS_CW_MIN
	.comm	_AR5K_DCU_LCL_IFS_CW_MAX,4,2    ; @AR5K_DCU_LCL_IFS_CW_MAX
	.comm	_AR5K_DCU_LCL_IFS_AIFS,4,2      ; @AR5K_DCU_LCL_IFS_AIFS
	.comm	_AR5K_DCU_MISC_FRAG_WAIT,4,2    ; @AR5K_DCU_MISC_FRAG_WAIT
	.comm	_AR5K_SREV_AR5211,8,3           ; @AR5K_SREV_AR5211
	.comm	_AR5K_DCU_MISC_SEQNUM_CTL,4,2   ; @AR5K_DCU_MISC_SEQNUM_CTL
	.comm	_AR5K_QCU_CBRCFG_INTVAL,4,2     ; @AR5K_QCU_CBRCFG_INTVAL
	.comm	_AR5K_QCU_CBRCFG_ORN_THRES,4,2  ; @AR5K_QCU_CBRCFG_ORN_THRES
	.comm	_AR5K_QCU_MISC_FRSHED_CBR,4,2   ; @AR5K_QCU_MISC_FRSHED_CBR
	.comm	_AR5K_QCU_MISC_CBR_THRES_ENABLE,4,2 ; @AR5K_QCU_MISC_CBR_THRES_ENABLE
	.comm	_AR5K_QCU_RDYTIMECFG_INTVAL,4,2 ; @AR5K_QCU_RDYTIMECFG_INTVAL
	.comm	_AR5K_QCU_RDYTIMECFG_ENABLE,4,2 ; @AR5K_QCU_RDYTIMECFG_ENABLE
	.comm	_AR5K_DCU_CHAN_TIME_DUR,4,2     ; @AR5K_DCU_CHAN_TIME_DUR
	.comm	_AR5K_DCU_CHAN_TIME_ENABLE,4,2  ; @AR5K_DCU_CHAN_TIME_ENABLE
	.comm	_AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE,4,2 ; @AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
	.comm	_AR5K_QCU_MISC_RDY_VEOL_POLICY,4,2 ; @AR5K_QCU_MISC_RDY_VEOL_POLICY
	.comm	_AR5K_TXQ_FLAG_BACKOFF_DISABLE,4,2 ; @AR5K_TXQ_FLAG_BACKOFF_DISABLE
	.comm	_AR5K_DCU_MISC_POST_FR_BKOFF_DIS,4,2 ; @AR5K_DCU_MISC_POST_FR_BKOFF_DIS
	.comm	_AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE,4,2 ; @AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
	.comm	_AR5K_DCU_MISC_BACKOFF_FRAG,4,2 ; @AR5K_DCU_MISC_BACKOFF_FRAG
	.comm	_AR5K_QCU_MISC_FRSHED_DBA_GT,4,2 ; @AR5K_QCU_MISC_FRSHED_DBA_GT
	.comm	_AR5K_QCU_MISC_CBREXP_BCN_DIS,4,2 ; @AR5K_QCU_MISC_CBREXP_BCN_DIS
	.comm	_AR5K_QCU_MISC_BCN_ENABLE,4,2   ; @AR5K_QCU_MISC_BCN_ENABLE
	.comm	_AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL,4,2 ; @AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL
	.comm	_AR5K_DCU_MISC_ARBLOCK_CTL_S,4,2 ; @AR5K_DCU_MISC_ARBLOCK_CTL_S
	.comm	_AR5K_DCU_MISC_ARBLOCK_IGNORE,4,2 ; @AR5K_DCU_MISC_ARBLOCK_IGNORE
	.comm	_AR5K_DCU_MISC_BCN_ENABLE,4,2   ; @AR5K_DCU_MISC_BCN_ENABLE
	.comm	_AR5K_QCU_MISC_CBREXP_DIS,4,2   ; @AR5K_QCU_MISC_CBREXP_DIS
	.comm	_AR5K_TUNE_SW_BEACON_RESP,4,2   ; @AR5K_TUNE_SW_BEACON_RESP
	.comm	_AR5K_TUNE_DMA_BEACON_RESP,4,2  ; @AR5K_TUNE_DMA_BEACON_RESP
	.comm	_AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF,4,2 ; @AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF
	.comm	_AR5K_TXQ_FLAG_TXOKINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_TXOKINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXERRINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_TXERRINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXURNINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_TXURNINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXDESCINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_TXDESCINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXEOLINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_TXEOLINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_CBRORNINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_CBRORNINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_CBRURNINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_CBRURNINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_QTRIGINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_QTRIGINT_ENABLE
	.comm	_AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE,4,2 ; @AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE
	.comm	_AR5K_SIMR0_QCU_TXOK,4,2        ; @AR5K_SIMR0_QCU_TXOK
	.comm	_AR5K_SIMR0_QCU_TXDESC,4,2      ; @AR5K_SIMR0_QCU_TXDESC
	.comm	_AR5K_SIMR0,4,2                 ; @AR5K_SIMR0
	.comm	_AR5K_SIMR1_QCU_TXERR,4,2       ; @AR5K_SIMR1_QCU_TXERR
	.comm	_AR5K_SIMR1_QCU_TXEOL,4,2       ; @AR5K_SIMR1_QCU_TXEOL
	.comm	_AR5K_SIMR1,4,2                 ; @AR5K_SIMR1
	.comm	_AR5K_SIMR2,4,2                 ; @AR5K_SIMR2
	.comm	_AR5K_SIMR2_QCU_TXURN,4,2       ; @AR5K_SIMR2_QCU_TXURN
	.comm	_AR5K_SIMR3_QCBRORN,4,2         ; @AR5K_SIMR3_QCBRORN
	.comm	_AR5K_SIMR3_QCBRURN,4,2         ; @AR5K_SIMR3_QCBRURN
	.comm	_AR5K_SIMR3,4,2                 ; @AR5K_SIMR3
	.comm	_AR5K_SIMR4_QTRIG,4,2           ; @AR5K_SIMR4_QTRIG
	.comm	_AR5K_SIMR4,4,2                 ; @AR5K_SIMR4
	.comm	_AR5K_TXNOFRM_QCU,4,2           ; @AR5K_TXNOFRM_QCU
	.comm	_AR5K_TXNOFRM,4,2               ; @AR5K_TXNOFRM
.subsections_via_symbols
