	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos_sata_phy_init
_exynos_sata_phy_init:                  ## @exynos_sata_phy_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movabsq	$47244640314, %rax              ## imm = 0xB0000003A
	movq	%rax, -40(%rbp)
	callq	_phy_get_drvdata
	movq	%rax, %r14
	movl	20(%rax), %edi
	movq	_SATAPHY_CONTROL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_EXYNOS5_SATAPHY_PMU_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$1, %ecx
	callq	_regmap_update_bits
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movq	(%r14), %rdi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
LBB0_2:
	movq	_EXYNOS5_SATA_RESET@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	addq	8(%r14), %rsi
	xorl	%edi, %edi
	callq	_writel
	movq	(%r15), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_RESET_GLOBAL_RST_N@GOTPCREL(%rip), %rcx
	movq	_RESET_CMN_RST_N@GOTPCREL(%rip), %r12
	movq	_RESET_CMN_BLOCK_RST_N@GOTPCREL(%rip), %rdx
	movq	_RESET_CMN_I2C_RST_N@GOTPCREL(%rip), %rsi
	movq	_RESET_TX_RX_PIPE_RST_N@GOTPCREL(%rip), %rdi
	movq	_RESET_TX_RX_BLOCK_RST_N@GOTPCREL(%rip), %rbx
	movq	_RESET_TX_RX_I2C_RST_N@GOTPCREL(%rip), %r8
	orl	(%rcx), %eax
	orl	(%r12), %eax
	orl	(%rdx), %eax
	orl	(%rsi), %eax
	orl	(%rdi), %eax
	orl	(%rbx), %eax
	orl	(%r8), %eax
	movq	(%r15), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	(%r15), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_LINK_RESET@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r15), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	(%r15), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	orl	(%r12), %eax
	movq	(%r15), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_EXYNOS5_SATA_PHSATA_CTRLM@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_PHCTRLM_REF_RATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
	movq	(%rbx), %rsi
	addq	8(%r14), %rsi
	callq	_writel
	movq	(%rbx), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_PHCTRLM_HIGH_SPEED@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_EXYNOS5_SATA_CTRL0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_CTRL0_P0_PHY_CALIBRATED_SEL@GOTPCREL(%rip), %rcx
	movq	_CTRL0_P0_PHY_CALIBRATED@GOTPCREL(%rip), %rdx
	orl	(%rcx), %eax
	orl	(%rdx), %eax
	movq	(%rbx), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_EXYNOS5_SATA_MODE0@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movq	_SATA_SPD_GEN3@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%rbx), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movl	16(%r14), %edi
	leaq	-40(%rbp), %rsi
	movl	$8, %edx
	callq	_i2c_master_send
	testl	%eax, %eax
	js	LBB0_3
## %bb.4:
	movq	(%r15), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	movl	(%r12), %edi
	notl	%edi
	andl	%eax, %edi
	movq	(%r15), %rsi
	addq	8(%r14), %rsi
	callq	_writel
	movq	(%r15), %rdi
	addq	8(%r14), %rdi
	callq	_readl
	orl	(%r12), %eax
	movq	(%r15), %rsi
	addq	8(%r14), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	8(%r14), %rdi
	movq	_EXYNOS5_SATA_PHSATA_STATM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PHSTATM_PLL_LOCKED@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	$1, %ecx
	callq	_wait_for_reg_status
	movl	%eax, %ebx
	testl	%eax, %eax
	jns	LBB0_6
## %bb.5:
	movq	(%r14), %rdi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_6
LBB0_3:
	movl	%eax, %ebx
LBB0_6:
	movl	%ebx, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SATAPHY_CONTROL_OFFSET,4,2     ## @SATAPHY_CONTROL_OFFSET
	.comm	_EXYNOS5_SATAPHY_PMU_ENABLE,4,2 ## @EXYNOS5_SATAPHY_PMU_ENABLE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"phy init failed\n"

	.comm	_EXYNOS5_SATA_RESET,8,3         ## @EXYNOS5_SATA_RESET
	.comm	_RESET_GLOBAL_RST_N,4,2         ## @RESET_GLOBAL_RST_N
	.comm	_RESET_CMN_RST_N,4,2            ## @RESET_CMN_RST_N
	.comm	_RESET_CMN_BLOCK_RST_N,4,2      ## @RESET_CMN_BLOCK_RST_N
	.comm	_RESET_CMN_I2C_RST_N,4,2        ## @RESET_CMN_I2C_RST_N
	.comm	_RESET_TX_RX_PIPE_RST_N,4,2     ## @RESET_TX_RX_PIPE_RST_N
	.comm	_RESET_TX_RX_BLOCK_RST_N,4,2    ## @RESET_TX_RX_BLOCK_RST_N
	.comm	_RESET_TX_RX_I2C_RST_N,4,2      ## @RESET_TX_RX_I2C_RST_N
	.comm	_LINK_RESET,4,2                 ## @LINK_RESET
	.comm	_EXYNOS5_SATA_PHSATA_CTRLM,8,3  ## @EXYNOS5_SATA_PHSATA_CTRLM
	.comm	_PHCTRLM_REF_RATE,4,2           ## @PHCTRLM_REF_RATE
	.comm	_PHCTRLM_HIGH_SPEED,4,2         ## @PHCTRLM_HIGH_SPEED
	.comm	_EXYNOS5_SATA_CTRL0,8,3         ## @EXYNOS5_SATA_CTRL0
	.comm	_CTRL0_P0_PHY_CALIBRATED_SEL,4,2 ## @CTRL0_P0_PHY_CALIBRATED_SEL
	.comm	_CTRL0_P0_PHY_CALIBRATED,4,2    ## @CTRL0_P0_PHY_CALIBRATED
	.comm	_EXYNOS5_SATA_MODE0,8,3         ## @EXYNOS5_SATA_MODE0
	.comm	_SATA_SPD_GEN3,4,2              ## @SATA_SPD_GEN3
	.comm	_EXYNOS5_SATA_PHSATA_STATM,4,2  ## @EXYNOS5_SATA_PHSATA_STATM
	.comm	_PHSTATM_PLL_LOCKED,4,2         ## @PHSTATM_PLL_LOCKED
L_.str.1:                               ## @.str.1
	.asciz	"PHY PLL locking failed\n"

	.no_dead_strip	_exynos_sata_phy_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos_sata_phy_init
_exynos_sata_phy_init:                  ; @exynos_sata_phy_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x8, #58
	movk	x8, #11, lsl #32
	str	x8, [sp, #8]
	bl	_phy_get_drvdata
	mov	x19, x0
	ldr	w0, [x0, #20]
Lloh0:
	adrp	x8, _SATAPHY_CONTROL_OFFSET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SATAPHY_CONTROL_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _EXYNOS5_SATAPHY_PMU_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _EXYNOS5_SATAPHY_PMU_ENABLE@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_regmap_update_bits
	cbz	w0, LBB0_2
; %bb.1:
	ldr	x0, [x19]
Lloh6:
	adrp	x1, l_.str@PAGE
Lloh7:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
LBB0_2:
	ldr	x8, [x19, #8]
Lloh8:
	adrp	x21, _EXYNOS5_SATA_RESET@GOTPAGE
Lloh9:
	ldr	x21, [x21, _EXYNOS5_SATA_RESET@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x1, x9, x8
	mov	w0, #0
	bl	_writel
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh10:
	adrp	x8, _RESET_GLOBAL_RST_N@GOTPAGE
Lloh11:
	ldr	x8, [x8, _RESET_GLOBAL_RST_N@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
Lloh13:
	adrp	x22, _RESET_CMN_RST_N@GOTPAGE
Lloh14:
	ldr	x22, [x22, _RESET_CMN_RST_N@GOTPAGEOFF]
Lloh15:
	adrp	x9, _RESET_CMN_BLOCK_RST_N@GOTPAGE
Lloh16:
	ldr	x9, [x9, _RESET_CMN_BLOCK_RST_N@GOTPAGEOFF]
	ldr	w10, [x22]
Lloh17:
	ldr	w9, [x9]
Lloh18:
	adrp	x11, _RESET_CMN_I2C_RST_N@GOTPAGE
Lloh19:
	ldr	x11, [x11, _RESET_CMN_I2C_RST_N@GOTPAGEOFF]
Lloh20:
	adrp	x12, _RESET_TX_RX_PIPE_RST_N@GOTPAGE
Lloh21:
	ldr	x12, [x12, _RESET_TX_RX_PIPE_RST_N@GOTPAGEOFF]
Lloh22:
	ldr	w11, [x11]
Lloh23:
	ldr	w12, [x12]
Lloh24:
	adrp	x13, _RESET_TX_RX_BLOCK_RST_N@GOTPAGE
Lloh25:
	ldr	x13, [x13, _RESET_TX_RX_BLOCK_RST_N@GOTPAGEOFF]
Lloh26:
	adrp	x14, _RESET_TX_RX_I2C_RST_N@GOTPAGE
Lloh27:
	ldr	x14, [x14, _RESET_TX_RX_I2C_RST_N@GOTPAGEOFF]
Lloh28:
	ldr	w13, [x13]
Lloh29:
	ldr	w14, [x14]
	orr	w8, w8, w0
	orr	w8, w8, w10
	orr	w8, w8, w9
	orr	w8, w8, w11
	orr	w8, w8, w12
	orr	w8, w8, w13
	orr	w0, w8, w14
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh30:
	adrp	x8, _LINK_RESET@GOTPAGE
Lloh31:
	ldr	x8, [x8, _LINK_RESET@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x22]
	orr	w0, w8, w0
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
Lloh33:
	adrp	x20, _EXYNOS5_SATA_PHSATA_CTRLM@GOTPAGE
Lloh34:
	ldr	x20, [x20, _EXYNOS5_SATA_PHSATA_CTRLM@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh35:
	adrp	x8, _PHCTRLM_REF_RATE@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PHCTRLM_REF_RATE@GOTPAGEOFF]
Lloh37:
	ldr	w8, [x8]
	bic	w0, w0, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh38:
	adrp	x8, _PHCTRLM_HIGH_SPEED@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PHCTRLM_HIGH_SPEED@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
Lloh41:
	adrp	x20, _EXYNOS5_SATA_CTRL0@GOTPAGE
Lloh42:
	ldr	x20, [x20, _EXYNOS5_SATA_CTRL0@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh43:
	adrp	x8, _CTRL0_P0_PHY_CALIBRATED_SEL@GOTPAGE
Lloh44:
	ldr	x8, [x8, _CTRL0_P0_PHY_CALIBRATED_SEL@GOTPAGEOFF]
Lloh45:
	ldr	w8, [x8]
Lloh46:
	adrp	x9, _CTRL0_P0_PHY_CALIBRATED@GOTPAGE
Lloh47:
	ldr	x9, [x9, _CTRL0_P0_PHY_CALIBRATED@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w0, w8, w9
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
Lloh49:
	adrp	x20, _EXYNOS5_SATA_MODE0@GOTPAGE
Lloh50:
	ldr	x20, [x20, _EXYNOS5_SATA_MODE0@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh51:
	adrp	x8, _SATA_SPD_GEN3@GOTPAGE
Lloh52:
	ldr	x8, [x8, _SATA_SPD_GEN3@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x19, #8]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writel
	ldr	w0, [x19, #16]
	add	x1, sp, #8
	mov	w2, #8
	bl	_i2c_master_send
	tbnz	w0, #31, LBB0_5
; %bb.3:
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x22]
	bic	w0, w0, w8
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	ldr	w8, [x22]
	orr	w0, w8, w0
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x0, [x19, #8]
Lloh54:
	adrp	x8, _EXYNOS5_SATA_PHSATA_STATM@GOTPAGE
Lloh55:
	ldr	x8, [x8, _EXYNOS5_SATA_PHSATA_STATM@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
Lloh57:
	adrp	x8, _PHSTATM_PLL_LOCKED@GOTPAGE
Lloh58:
	ldr	x8, [x8, _PHSTATM_PLL_LOCKED@GOTPAGEOFF]
Lloh59:
	ldr	w2, [x8]
	mov	w3, #1
	bl	_wait_for_reg_status
	mov	x20, x0
	tbz	w0, #31, LBB0_6
; %bb.4:
	ldr	x0, [x19]
Lloh60:
	adrp	x1, l_.str.1@PAGE
Lloh61:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	b	LBB0_6
LBB0_5:
	mov	x20, x0
LBB0_6:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh28
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh22
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpAdd	Lloh60, Lloh61
	.cfi_endproc
                                        ; -- End function
	.comm	_SATAPHY_CONTROL_OFFSET,4,2     ; @SATAPHY_CONTROL_OFFSET
	.comm	_EXYNOS5_SATAPHY_PMU_ENABLE,4,2 ; @EXYNOS5_SATAPHY_PMU_ENABLE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"phy init failed\n"

	.comm	_EXYNOS5_SATA_RESET,8,3         ; @EXYNOS5_SATA_RESET
	.comm	_RESET_GLOBAL_RST_N,4,2         ; @RESET_GLOBAL_RST_N
	.comm	_RESET_CMN_RST_N,4,2            ; @RESET_CMN_RST_N
	.comm	_RESET_CMN_BLOCK_RST_N,4,2      ; @RESET_CMN_BLOCK_RST_N
	.comm	_RESET_CMN_I2C_RST_N,4,2        ; @RESET_CMN_I2C_RST_N
	.comm	_RESET_TX_RX_PIPE_RST_N,4,2     ; @RESET_TX_RX_PIPE_RST_N
	.comm	_RESET_TX_RX_BLOCK_RST_N,4,2    ; @RESET_TX_RX_BLOCK_RST_N
	.comm	_RESET_TX_RX_I2C_RST_N,4,2      ; @RESET_TX_RX_I2C_RST_N
	.comm	_LINK_RESET,4,2                 ; @LINK_RESET
	.comm	_EXYNOS5_SATA_PHSATA_CTRLM,8,3  ; @EXYNOS5_SATA_PHSATA_CTRLM
	.comm	_PHCTRLM_REF_RATE,4,2           ; @PHCTRLM_REF_RATE
	.comm	_PHCTRLM_HIGH_SPEED,4,2         ; @PHCTRLM_HIGH_SPEED
	.comm	_EXYNOS5_SATA_CTRL0,8,3         ; @EXYNOS5_SATA_CTRL0
	.comm	_CTRL0_P0_PHY_CALIBRATED_SEL,4,2 ; @CTRL0_P0_PHY_CALIBRATED_SEL
	.comm	_CTRL0_P0_PHY_CALIBRATED,4,2    ; @CTRL0_P0_PHY_CALIBRATED
	.comm	_EXYNOS5_SATA_MODE0,8,3         ; @EXYNOS5_SATA_MODE0
	.comm	_SATA_SPD_GEN3,4,2              ; @SATA_SPD_GEN3
	.comm	_EXYNOS5_SATA_PHSATA_STATM,4,2  ; @EXYNOS5_SATA_PHSATA_STATM
	.comm	_PHSTATM_PLL_LOCKED,4,2         ; @PHSTATM_PLL_LOCKED
l_.str.1:                               ; @.str.1
	.asciz	"PHY PLL locking failed\n"

	.no_dead_strip	_exynos_sata_phy_init
.subsections_via_symbols
