	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_bm_pool_put
_mvpp2_bm_pool_put:                     ## @mvpp2_bm_pool_put
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%ecx, %r14d
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movl	%esi, %r13d
	movq	%rdi, %r12
	movq	8(%rdi), %rbx
	xorl	%eax, %eax
	callq	_get_cpu
	movq	%rbx, %rdi
	movl	%eax, %esi
	callq	_mvpp2_cpu_to_thread
	movl	%eax, %ebx
	movq	8(%r12), %rsi
	addq	$8, %rsi
	movl	%eax, %edi
	callq	_test_bit
	movl	%ebx, %r15d
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	leaq	(,%r15,4), %rdi
	addq	(%r12), %rdi
	xorl	%esi, %esi
	callq	_spin_lock_irqsave
LBB0_2:
	movq	8(%r12), %rdi
	movq	(%rdi), %rax
	movq	_MVPP22@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_4
## %bb.3:
	movq	_MVPP22_BM_ADDR_HIGH_RLS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	xorl	%ecx, %ecx
	callq	_mvpp2_thread_write_relaxed
	movq	8(%r12), %rdi
LBB0_4:
	movq	_MVPP2_BM_VIRT_RLS_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%ebx, %esi
	movl	%r14d, %ecx
	callq	_mvpp2_thread_write_relaxed
	movq	8(%r12), %r14
	movl	%r13d, %edi
	callq	_MVPP2_BM_PHY_RLS_REG
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	callq	_mvpp2_thread_write_relaxed
	movq	8(%r12), %rsi
	addq	$8, %rsi
	movl	%ebx, %edi
	callq	_test_bit
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	shlq	$2, %r15
	addq	(%r12), %r15
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_spin_unlock_irqrestore
LBB0_6:
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_put_cpu                        ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP22,8,3                     ## @MVPP22
	.comm	_MVPP22_BM_ADDR_HIGH_RLS_REG,4,2 ## @MVPP22_BM_ADDR_HIGH_RLS_REG
	.comm	_MVPP2_BM_VIRT_RLS_REG,4,2      ## @MVPP2_BM_VIRT_RLS_REG
	.comm	_MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK,4,2 ## @MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK
	.comm	_MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK,4,2 ## @MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK
	.comm	_MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT,4,2 ## @MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT
	.no_dead_strip	_mvpp2_bm_pool_put
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_bm_pool_put
_mvpp2_bm_pool_put:                     ; @mvpp2_bm_pool_put
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x23, x3
	mov	x21, x2
	mov	x22, x1
	mov	x19, x0
	ldr	x20, [x0, #8]
	bl	_get_cpu
	mov	x1, x0
	mov	x0, x20
	bl	_mvpp2_cpu_to_thread
	mov	x20, x0
	ldr	x8, [x19, #8]
	add	x1, x8, #8
	bl	_test_bit
	cbz	x0, LBB0_2
; %bb.1:
	ldr	x8, [x19]
	add	x0, x8, w20, uxtw #2
	mov	x1, #0
	bl	_spin_lock_irqsave
LBB0_2:
	ldr	x0, [x19, #8]
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _MVPP22@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MVPP22@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_4
; %bb.3:
Lloh3:
	adrp	x8, _MVPP22_BM_ADDR_HIGH_RLS_REG@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MVPP22_BM_ADDR_HIGH_RLS_REG@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x1, x20
	mov	w3, #0
	bl	_mvpp2_thread_write_relaxed
	ldr	x0, [x19, #8]
LBB0_4:
Lloh6:
	adrp	x8, _MVPP2_BM_VIRT_RLS_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _MVPP2_BM_VIRT_RLS_REG@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x1, x20
	mov	x3, x23
	bl	_mvpp2_thread_write_relaxed
	ldr	x23, [x19, #8]
	mov	x0, x22
	bl	_MVPP2_BM_PHY_RLS_REG
	mov	x2, x0
	mov	x0, x23
	mov	x1, x20
	mov	x3, x21
	bl	_mvpp2_thread_write_relaxed
	ldr	x8, [x19, #8]
	add	x1, x8, #8
	mov	x0, x20
	bl	_test_bit
	cbz	x0, LBB0_6
; %bb.5:
	ldr	x8, [x19]
	add	x0, x8, w20, uxtw #2
	mov	x1, #0
	bl	_spin_unlock_irqrestore
LBB0_6:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_put_cpu
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP22,8,3                     ; @MVPP22
	.comm	_MVPP22_BM_ADDR_HIGH_RLS_REG,4,2 ; @MVPP22_BM_ADDR_HIGH_RLS_REG
	.comm	_MVPP2_BM_VIRT_RLS_REG,4,2      ; @MVPP2_BM_VIRT_RLS_REG
	.comm	_MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK,4,2 ; @MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK
	.comm	_MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK,4,2 ; @MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK
	.comm	_MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT,4,2 ; @MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT
	.no_dead_strip	_mvpp2_bm_pool_put
.subsections_via_symbols
