	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_enable_rp_features
_tegra_pcie_enable_rp_features:         ## @tegra_pcie_enable_rp_features
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	movq	_RP_VEND_CTL1@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_VEND_CTL1_ERPT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_RP_VEND_XP@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_VEND_XP_OPPORTUNISTIC_ACK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_RP_VEND_XP_BIST@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel
	movq	_RP_PRIV_MISC@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	(%rbx), %rdi
	callq	_readl
	movq	_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	cmpq	$0, (%r14)
	je	LBB0_2
## %bb.1:
	movq	_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK@GOTPCREL(%rip), %rcx
	movq	_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, %eax
	movq	_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD@GOTPCREL(%rip), %rcx
	movq	_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	orl	%edx, %eax
LBB0_2:
	movq	(%r15), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_RP_VEND_CTL1,8,3               ## @RP_VEND_CTL1
	.comm	_RP_VEND_CTL1_ERPT,4,2          ## @RP_VEND_CTL1_ERPT
	.comm	_RP_VEND_XP,8,3                 ## @RP_VEND_XP
	.comm	_RP_VEND_XP_OPPORTUNISTIC_ACK,4,2 ## @RP_VEND_XP_OPPORTUNISTIC_ACK
	.comm	_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC,4,2 ## @RP_VEND_XP_OPPORTUNISTIC_UPDATEFC
	.comm	_RP_VEND_XP_BIST,8,3            ## @RP_VEND_XP_BIST
	.comm	_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE,4,2 ## @RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE
	.comm	_RP_PRIV_MISC,8,3               ## @RP_PRIV_MISC
	.comm	_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE,4,2 ## @RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE
	.comm	_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE,4,2 ## @RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE
	.comm	_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK,4,2 ## @RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK
	.comm	_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK,4,2 ## @RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK
	.comm	_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD,4,2 ## @RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD
	.comm	_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD,4,2 ## @RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD
	.no_dead_strip	_tegra_pcie_enable_rp_features
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_enable_rp_features
_tegra_pcie_enable_rp_features:         ; @tegra_pcie_enable_rp_features
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldp	x9, x8, [x0]
	ldr	x20, [x8]
Lloh0:
	adrp	x21, _RP_VEND_CTL1@GOTPAGE
Lloh1:
	ldr	x21, [x21, _RP_VEND_CTL1@GOTPAGEOFF]
	ldr	x8, [x21]
	add	x0, x8, x9
	bl	_readl
Lloh2:
	adrp	x8, _RP_VEND_CTL1_ERPT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _RP_VEND_CTL1_ERPT@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
Lloh5:
	adrp	x21, _RP_VEND_XP@GOTPAGE
Lloh6:
	ldr	x21, [x21, _RP_VEND_XP@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh7:
	adrp	x8, _RP_VEND_XP_OPPORTUNISTIC_ACK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _RP_VEND_XP_OPPORTUNISTIC_ACK@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
Lloh10:
	adrp	x9, _RP_VEND_XP_OPPORTUNISTIC_UPDATEFC@GOTPAGE
Lloh11:
	ldr	x9, [x9, _RP_VEND_XP_OPPORTUNISTIC_UPDATEFC@GOTPAGEOFF]
	orr	w8, w8, w0
Lloh12:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
Lloh13:
	adrp	x21, _RP_VEND_XP_BIST@GOTPAGE
Lloh14:
	ldr	x21, [x21, _RP_VEND_XP_BIST@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh15:
	adrp	x8, _RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	orr	w0, w8, w0
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x19]
Lloh18:
	adrp	x21, _RP_PRIV_MISC@GOTPAGE
Lloh19:
	ldr	x21, [x21, _RP_PRIV_MISC@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
Lloh20:
	adrp	x8, _RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE@GOTPAGE
Lloh21:
	ldr	x8, [x8, _RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh23:
	adrp	x9, _RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE@GOTPAGE
Lloh24:
	ldr	x9, [x9, _RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x20]
	cbz	x8, LBB0_2
; %bb.1:
Lloh26:
	adrp	x8, _RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK@GOTPAGE
Lloh27:
	ldr	x8, [x8, _RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK@GOTPAGEOFF]
Lloh28:
	adrp	x9, _RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK@GOTPAGE
Lloh29:
	ldr	x9, [x9, _RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
Lloh31:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w8, w0, w8
Lloh32:
	adrp	x9, _RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD@GOTPAGE
Lloh33:
	ldr	x9, [x9, _RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD@GOTPAGEOFF]
Lloh34:
	ldr	w9, [x9]
Lloh35:
	adrp	x10, _RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD@GOTPAGE
Lloh36:
	ldr	x10, [x10, _RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD@GOTPAGEOFF]
Lloh37:
	ldr	w10, [x10]
	orr	w9, w10, w9
	orr	w0, w9, w8
LBB0_2:
	ldr	x8, [x19]
	ldr	x9, [x21]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_RP_VEND_CTL1,8,3               ; @RP_VEND_CTL1
	.comm	_RP_VEND_CTL1_ERPT,4,2          ; @RP_VEND_CTL1_ERPT
	.comm	_RP_VEND_XP,8,3                 ; @RP_VEND_XP
	.comm	_RP_VEND_XP_OPPORTUNISTIC_ACK,4,2 ; @RP_VEND_XP_OPPORTUNISTIC_ACK
	.comm	_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC,4,2 ; @RP_VEND_XP_OPPORTUNISTIC_UPDATEFC
	.comm	_RP_VEND_XP_BIST,8,3            ; @RP_VEND_XP_BIST
	.comm	_RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE,4,2 ; @RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE
	.comm	_RP_PRIV_MISC,8,3               ; @RP_PRIV_MISC
	.comm	_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE,4,2 ; @RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE
	.comm	_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE,4,2 ; @RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE
	.comm	_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK,4,2 ; @RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK
	.comm	_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK,4,2 ; @RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK
	.comm	_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD,4,2 ; @RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD
	.comm	_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD,4,2 ; @RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD
	.no_dead_strip	_tegra_pcie_enable_rp_features
.subsections_via_symbols
