	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos4x12_setup_clk
_exynos4x12_setup_clk:                  ## @exynos4x12_setup_clk
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	(%rdi), %rbx
	movq	_EXYNOS_4x12_UPHYCLK@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	8(%rbx), %rdi
	callq	_readl
	movq	16(%rbx), %rcx
	cmpq	$0, (%rcx)
	je	LBB0_1
## %bb.2:
	movq	_EXYNOS_3250_UPHYCLK_REFCLKSEL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	jmp	LBB0_3
LBB0_1:
	movq	_EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	notl	%ecx
	andl	%ecx, %eax
LBB0_3:
	movl	(%rbx), %edi
	movq	_EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %edi
	orl	%eax, %edi
	movq	_EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	(%r14), %rsi
	addq	8(%rbx), %rsi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_EXYNOS_4x12_UPHYCLK,8,3        ## @EXYNOS_4x12_UPHYCLK
	.comm	_EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK,4,2 ## @EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK
	.comm	_EXYNOS_3250_UPHYCLK_REFCLKSEL,4,2 ## @EXYNOS_3250_UPHYCLK_REFCLKSEL
	.comm	_EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET,4,2 ## @EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET
	.comm	_EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON,4,2 ## @EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON
	.no_dead_strip	_exynos4x12_setup_clk
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos4x12_setup_clk
_exynos4x12_setup_clk:                  ; @exynos4x12_setup_clk
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x19, [x0]
	ldr	x8, [x19, #8]
Lloh0:
	adrp	x20, _EXYNOS_4x12_UPHYCLK@GOTPAGE
Lloh1:
	ldr	x20, [x20, _EXYNOS_4x12_UPHYCLK@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh2:
	adrp	x8, _EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldp	x10, x9, [x19, #8]
	ldr	x9, [x9]
	cmp	x9, #0
Lloh5:
	adrp	x9, _EXYNOS_3250_UPHYCLK_REFCLKSEL@GOTPAGE
Lloh6:
	ldr	x9, [x9, _EXYNOS_3250_UPHYCLK_REFCLKSEL@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	csel	w8, w8, w9, eq
Lloh8:
	adrp	x9, _EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET@GOTPAGE
Lloh9:
	ldr	x9, [x9, _EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET@GOTPAGEOFF]
	ldr	w11, [x19]
Lloh10:
	ldr	w9, [x9]
	lsl	w9, w11, w9
	orr	w8, w9, w8
Lloh11:
	adrp	x9, _EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON@GOTPAGE
Lloh12:
	ldr	x9, [x9, _EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w0, w8, w9
	ldr	x8, [x20]
	add	x1, x8, x10
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_EXYNOS_4x12_UPHYCLK,8,3        ; @EXYNOS_4x12_UPHYCLK
	.comm	_EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK,4,2 ; @EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK
	.comm	_EXYNOS_3250_UPHYCLK_REFCLKSEL,4,2 ; @EXYNOS_3250_UPHYCLK_REFCLKSEL
	.comm	_EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET,4,2 ; @EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET
	.comm	_EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON,4,2 ; @EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON
	.no_dead_strip	_exynos4x12_setup_clk
.subsections_via_symbols
