	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sw_reset_and_clock
_sw_reset_and_clock:                    ## @sw_reset_and_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movl	(%rdi), %edi
	movq	_IPW_REG_RESET_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IPW_AUX_HOST_RESET_REG_SW_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_write_register
	movl	$1000, %ebx                     ## imm = 0x3E8
	movq	_IPW_WAIT_RESET_ARC_COMPLETE_DELAY@GOTPCREL(%rip), %r13
	leaq	-44(%rbp), %r14
	movq	_IPW_AUX_HOST_RESET_REG_PRINCETON_RESET@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r13), %edi
	callq	_udelay
	movl	(%r12), %edi
	movq	_IPW_REG_RESET_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdx
	callq	_read_register
	movl	(%r15), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_4
## %bb.2:                               ##   in Loop: Header=BB0_1 Depth=1
	decl	%ebx
	jne	LBB0_1
	jmp	LBB0_3
LBB0_4:
	movl	(%r12), %edi
	movq	_IPW_REG_GP_CNTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_write_register
	movl	$10000, %ebx                    ## imm = 0x2710
	movq	_IPW_WAIT_CLOCK_STABILIZATION_DELAY@GOTPCREL(%rip), %r13
	leaq	-44(%rbp), %r14
	movq	_IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r13), %edi
	shll	$2, %edi
	callq	_udelay
	movl	(%r12), %edi
	movq	_IPW_REG_GP_CNTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdx
	callq	_read_register
	movl	(%r15), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_7
## %bb.6:                               ##   in Loop: Header=BB0_5 Depth=1
	decl	%ebx
	jne	LBB0_5
LBB0_3:
	movq	_EIO@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_8
LBB0_7:
	movl	(%r12), %edi
	movq	_IPW_REG_GP_CNTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	leaq	-44(%rbp), %rdx
	callq	_read_register
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movq	_IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	-44(%rbp), %edx
	callq	_write_register
	xorl	%eax, %eax
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IPW_REG_RESET_REG,4,2          ## @IPW_REG_RESET_REG
	.comm	_IPW_AUX_HOST_RESET_REG_SW_RESET,4,2 ## @IPW_AUX_HOST_RESET_REG_SW_RESET
	.comm	_IPW_WAIT_RESET_ARC_COMPLETE_DELAY,4,2 ## @IPW_WAIT_RESET_ARC_COMPLETE_DELAY
	.comm	_IPW_AUX_HOST_RESET_REG_PRINCETON_RESET,4,2 ## @IPW_AUX_HOST_RESET_REG_PRINCETON_RESET
	.comm	_EIO,4,2                        ## @EIO
	.comm	_IPW_REG_GP_CNTRL,4,2           ## @IPW_REG_GP_CNTRL
	.comm	_IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE,4,2 ## @IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE
	.comm	_IPW_WAIT_CLOCK_STABILIZATION_DELAY,4,2 ## @IPW_WAIT_CLOCK_STABILIZATION_DELAY
	.comm	_IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY,4,2 ## @IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY
	.comm	_IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY,4,2 ## @IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY
	.no_dead_strip	_sw_reset_and_clock
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sw_reset_and_clock
_sw_reset_and_clock:                    ; @sw_reset_and_clock
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x20, _IPW_REG_RESET_REG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _IPW_REG_RESET_REG@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _IPW_AUX_HOST_RESET_REG_SW_RESET@GOTPAGE
Lloh3:
	ldr	x8, [x8, _IPW_AUX_HOST_RESET_REG_SW_RESET@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	bl	_write_register
	mov	w21, #1000
Lloh5:
	adrp	x22, _IPW_WAIT_RESET_ARC_COMPLETE_DELAY@GOTPAGE
Lloh6:
	ldr	x22, [x22, _IPW_WAIT_RESET_ARC_COMPLETE_DELAY@GOTPAGEOFF]
Lloh7:
	adrp	x23, _IPW_AUX_HOST_RESET_REG_PRINCETON_RESET@GOTPAGE
Lloh8:
	ldr	x23, [x23, _IPW_AUX_HOST_RESET_REG_PRINCETON_RESET@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x22]
	bl	_udelay
	ldr	w0, [x19]
	ldr	w1, [x20]
	add	x2, sp, #12
	bl	_read_register
	ldr	w8, [sp, #12]
	ldr	w9, [x23]
	tst	w9, w8
	b.ne	LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	subs	w21, w21, #1
	b.ne	LBB0_1
	b	LBB0_6
LBB0_3:
	ldr	w0, [x19]
Lloh9:
	adrp	x20, _IPW_REG_GP_CNTRL@GOTPAGE
Lloh10:
	ldr	x20, [x20, _IPW_REG_GP_CNTRL@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh11:
	adrp	x8, _IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	bl	_write_register
	mov	w21, #10000
Lloh14:
	adrp	x22, _IPW_WAIT_CLOCK_STABILIZATION_DELAY@GOTPAGE
Lloh15:
	ldr	x22, [x22, _IPW_WAIT_CLOCK_STABILIZATION_DELAY@GOTPAGEOFF]
Lloh16:
	adrp	x23, _IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY@GOTPAGE
Lloh17:
	ldr	x23, [x23, _IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x22]
	lsl	w0, w8, #2
	bl	_udelay
	ldr	w0, [x19]
	ldr	w1, [x20]
	add	x2, sp, #12
	bl	_read_register
	ldr	w8, [sp, #12]
	ldr	w9, [x23]
	tst	w9, w8
	b.ne	LBB0_7
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	subs	w21, w21, #1
	b.ne	LBB0_4
LBB0_6:
Lloh18:
	adrp	x8, _EIO@GOTPAGE
Lloh19:
	ldr	x8, [x8, _EIO@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_8
LBB0_7:
	ldr	w0, [x19]
	ldr	w1, [x20]
	add	x2, sp, #12
	bl	_read_register
	ldr	w0, [x19]
	ldr	w1, [x20]
	ldr	w8, [sp, #12]
Lloh21:
	adrp	x9, _IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY@GOTPAGE
Lloh22:
	ldr	x9, [x9, _IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	orr	w2, w9, w8
	bl	_write_register
	mov	w0, #0
LBB0_8:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_IPW_REG_RESET_REG,4,2          ; @IPW_REG_RESET_REG
	.comm	_IPW_AUX_HOST_RESET_REG_SW_RESET,4,2 ; @IPW_AUX_HOST_RESET_REG_SW_RESET
	.comm	_IPW_WAIT_RESET_ARC_COMPLETE_DELAY,4,2 ; @IPW_WAIT_RESET_ARC_COMPLETE_DELAY
	.comm	_IPW_AUX_HOST_RESET_REG_PRINCETON_RESET,4,2 ; @IPW_AUX_HOST_RESET_REG_PRINCETON_RESET
	.comm	_EIO,4,2                        ; @EIO
	.comm	_IPW_REG_GP_CNTRL,4,2           ; @IPW_REG_GP_CNTRL
	.comm	_IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE,4,2 ; @IPW_AUX_HOST_GP_CNTRL_BIT_INIT_DONE
	.comm	_IPW_WAIT_CLOCK_STABILIZATION_DELAY,4,2 ; @IPW_WAIT_CLOCK_STABILIZATION_DELAY
	.comm	_IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY,4,2 ; @IPW_AUX_HOST_GP_CNTRL_BIT_CLOCK_READY
	.comm	_IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY,4,2 ; @IPW_AUX_HOST_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY
	.no_dead_strip	_sw_reset_and_clock
.subsections_via_symbols
