	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function artpec6_pcie_init_phy_a7
_artpec6_pcie_init_phy_a7:              ## @artpec6_pcie_init_phy_a7
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	(%rdi), %r15
	movq	_PCIESTAT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_artpec6_pcie_readl
	movl	%eax, %r14d
	movq	_PCIESTAT_EXTREFCLK@GOTPCREL(%rip), %rax
	andl	(%rax), %r14d
	movl	(%r15), %edi
	leaq	L_.str.2(%rip), %rax
	leaq	L_.str.1(%rip), %rdx
	cmoveq	%rax, %rdx
	leaq	L_.str(%rip), %rsi
	callq	_dev_dbg
	movq	_PCIECFG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_artpec6_pcie_readl
	movq	_PCIECFG_RISRCREN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_PCIECFG_PCLK_ENABLE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_PCIECFG_REFCLKSEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, %ecx
	orl	%eax, %ecx
	notl	%edx
	andl	%eax, %edx
	testl	%r14d, %r14d
	cmovnel	%ecx, %edx
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_artpec6_pcie_writel
	movl	$10, %edi
	movl	$20, %esi
	callq	_usleep_range
	movq	_NOCCFG@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_artpec6_pcie_readl
	movq	_NOCCFG_ENABLE_CLK_PCIE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_artpec6_pcie_writel
	movl	$20, %edi
	movl	$30, %esi
	callq	_usleep_range
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_artpec6_pcie_readl
	movq	_NOCCFG_POWER_PCIE_IDLEREQ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%r14), %esi
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_artpec6_pcie_writel            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIESTAT,4,2                   ## @PCIESTAT
	.comm	_PCIESTAT_EXTREFCLK,4,2         ## @PCIESTAT_EXTREFCLK
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Using reference clock: %s\n"

L_.str.1:                               ## @.str.1
	.asciz	"external"

L_.str.2:                               ## @.str.2
	.asciz	"internal"

	.comm	_PCIECFG,4,2                    ## @PCIECFG
	.comm	_PCIECFG_RISRCREN,4,2           ## @PCIECFG_RISRCREN
	.comm	_PCIECFG_PCLK_ENABLE,4,2        ## @PCIECFG_PCLK_ENABLE
	.comm	_PCIECFG_REFCLKSEL,4,2          ## @PCIECFG_REFCLKSEL
	.comm	_NOCCFG,4,2                     ## @NOCCFG
	.comm	_NOCCFG_ENABLE_CLK_PCIE,4,2     ## @NOCCFG_ENABLE_CLK_PCIE
	.comm	_NOCCFG_POWER_PCIE_IDLEREQ,4,2  ## @NOCCFG_POWER_PCIE_IDLEREQ
	.no_dead_strip	_artpec6_pcie_init_phy_a7
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function artpec6_pcie_init_phy_a7
_artpec6_pcie_init_phy_a7:              ; @artpec6_pcie_init_phy_a7
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x21, [x0]
Lloh0:
	adrp	x8, _PCIESTAT@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIESTAT@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_artpec6_pcie_readl
	mov	x20, x0
Lloh3:
	adrp	x8, _PCIESTAT_EXTREFCLK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIESTAT_EXTREFCLK@GOTPAGEOFF]
Lloh5:
	ldr	w22, [x8]
	ldr	w0, [x21]
Lloh6:
	adrp	x8, l_.str.1@PAGE
Lloh7:
	add	x8, x8, l_.str.1@PAGEOFF
Lloh8:
	adrp	x9, l_.str.2@PAGE
Lloh9:
	add	x9, x9, l_.str.2@PAGEOFF
	tst	w22, w20
	csel	x2, x9, x8, eq
Lloh10:
	adrp	x1, l_.str@PAGE
Lloh11:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
Lloh12:
	adrp	x21, _PCIECFG@GOTPAGE
Lloh13:
	ldr	x21, [x21, _PCIECFG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_artpec6_pcie_readl
	tst	w22, w20
Lloh14:
	adrp	x8, _PCIECFG_RISRCREN@GOTPAGE
Lloh15:
	ldr	x8, [x8, _PCIECFG_RISRCREN@GOTPAGEOFF]
Lloh16:
	ldr	w8, [x8]
Lloh17:
	adrp	x9, _PCIECFG_PCLK_ENABLE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PCIECFG_PCLK_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w0
Lloh20:
	adrp	x10, _PCIECFG_REFCLKSEL@GOTPAGE
Lloh21:
	ldr	x10, [x10, _PCIECFG_REFCLKSEL@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh22:
	ldr	w9, [x10]
	orr	w10, w9, w8
	bic	w8, w8, w9
	csel	w2, w8, w10, eq
	ldr	w1, [x21]
	mov	x0, x19
	bl	_artpec6_pcie_writel
	mov	w0, #10
	mov	w1, #20
	bl	_usleep_range
Lloh23:
	adrp	x20, _NOCCFG@GOTPAGE
Lloh24:
	ldr	x20, [x20, _NOCCFG@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_artpec6_pcie_readl
Lloh25:
	adrp	x8, _NOCCFG_ENABLE_CLK_PCIE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _NOCCFG_ENABLE_CLK_PCIE@GOTPAGEOFF]
Lloh27:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x20]
	mov	x0, x19
	bl	_artpec6_pcie_writel
	mov	w0, #20
	mov	w1, #30
	bl	_usleep_range
	ldr	w1, [x20]
	mov	x0, x19
	bl	_artpec6_pcie_readl
Lloh28:
	adrp	x8, _NOCCFG_POWER_PCIE_IDLEREQ@GOTPAGE
Lloh29:
	ldr	x8, [x8, _NOCCFG_POWER_PCIE_IDLEREQ@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_artpec6_pcie_writel
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIESTAT,4,2                   ; @PCIESTAT
	.comm	_PCIESTAT_EXTREFCLK,4,2         ; @PCIESTAT_EXTREFCLK
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Using reference clock: %s\n"

l_.str.1:                               ; @.str.1
	.asciz	"external"

l_.str.2:                               ; @.str.2
	.asciz	"internal"

	.comm	_PCIECFG,4,2                    ; @PCIECFG
	.comm	_PCIECFG_RISRCREN,4,2           ; @PCIECFG_RISRCREN
	.comm	_PCIECFG_PCLK_ENABLE,4,2        ; @PCIECFG_PCLK_ENABLE
	.comm	_PCIECFG_REFCLKSEL,4,2          ; @PCIECFG_REFCLKSEL
	.comm	_NOCCFG,4,2                     ; @NOCCFG
	.comm	_NOCCFG_ENABLE_CLK_PCIE,4,2     ; @NOCCFG_ENABLE_CLK_PCIE
	.comm	_NOCCFG_POWER_PCIE_IDLEREQ,4,2  ; @NOCCFG_POWER_PCIE_IDLEREQ
	.no_dead_strip	_artpec6_pcie_init_phy_a7
.subsections_via_symbols
