	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rtl8xxxu_gen1_config_channel   ## -- Begin function rtl8xxxu_gen1_config_channel
	.p2align	4, 0x90
_rtl8xxxu_gen1_config_channel:          ## @rtl8xxxu_gen1_config_channel
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	24(%rdi), %r13
	movq	_REG_BW_OPMODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read8
	movl	%eax, %r15d
	movq	_REG_RESPONSE_RATE_SET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movl	%eax, %r14d
	movq	8(%rbx), %rcx
	movl	(%rcx), %r12d
	movl	(%rbx), %eax
	cmpl	$128, %eax
	movq	%rbx, -64(%rbp)                 ## 8-byte Spill
	je	LBB0_7
## %bb.1:
	cmpl	$130, %eax
	je	LBB0_2
## %bb.3:
	cmpl	$129, %eax
	jne	LBB0_4
## %bb.5:
	xorl	%eax, %eax
	jmp	LBB0_6
LBB0_7:
	movl	16(%rbx), %ebx
	movl	%ebx, -48(%rbp)                 ## 4-byte Spill
	movl	4(%rcx), %eax
	movl	%eax, -52(%rbp)                 ## 4-byte Spill
	movq	_BW_OPMODE_20MHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r15d
	movq	_REG_BW_OPMODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r13, %rdi
	movl	%r15d, %edx
	callq	_rtl8xxxu_write8
	movq	_RSR_RSC_BANDWIDTH_40M@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, %r14d
	cmpl	-52(%rbp), %ebx                 ## 4-byte Folded Reload
	movq	_RSR_RSC_LOWER_SUB_CHANNEL@GOTPCREL(%rip), %rax
	cmovgq	_RSR_RSC_UPPER_SUB_CHANNEL@GOTPCREL(%rip), %rax
	movq	_OFDM_LSTF_PRIME_CH_HIGH@GOTPCREL(%rip), %r15
	cmovgq	_OFDM_LSTF_PRIME_CH_LOW@GOTPCREL(%rip), %r15
	movq	_REG_RESPONSE_RATE_SET@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %r14d
	movq	%r13, %rdi
	movl	%r14d, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movq	_FPGA_RF_MODE@GOTPCREL(%rip), %r14
	movl	(%rbx), %esi
	orl	(%r14), %eax
	movq	%r13, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA1_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movl	(%rbx), %esi
	orl	(%r14), %eax
	movq	%r13, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_CCK0_SYSTEM@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movq	_CCK0_SIDEBAND@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%eax, %edx
	movl	-52(%rbp), %r14d                ## 4-byte Reload
	cmpl	%r14d, -48(%rbp)                ## 4-byte Folded Reload
	cmovgl	%ecx, %edx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_OFDM1_LSTF@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movq	_OFDM_LSTF_PRIME_CH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	orl	(%r15), %edx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_ANALOG2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movq	_FPGA0_ANALOG2_20MHZ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_POWER_SAVE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	xorl	%ecx, %ecx
	cmpl	%r14d, -48(%rbp)                ## 4-byte Folded Reload
	setg	%cl
	leal	-2(%r12,%rcx,4), %r12d
	movq	_FPGA0_PS_LOWER_CHANNEL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	_FPGA0_PS_UPPER_CHANNEL@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movl	%ecx, %esi
	cmovgl	%edx, %esi
	orl	%ecx, %edx
	notl	%edx
	andl	%eax, %edx
	orl	%esi, %edx
	movl	$1, %eax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	jmp	LBB0_8
LBB0_2:
	movl	$1, %eax
LBB0_6:
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_BW_OPMODE_20MHZ@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_REG_BW_OPMODE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r13, %rdi
	movl	%r15d, %edx
	callq	_rtl8xxxu_write8
	movq	_REG_FPGA0_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movq	_FPGA_RF_MODE@GOTPCREL(%rip), %r14
	movl	(%r14), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA1_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movl	(%r14), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_ANALOG2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_read32
	movl	%eax, %edx
	movq	_FPGA0_ANALOG2_20MHZ@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
LBB0_8:
	movl	(%rbx), %esi
	movq	%r13, %rdi
	callq	_rtl8xxxu_write32
	jmp	LBB0_9
LBB0_4:
	movl	$1, %eax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
LBB0_9:
	movq	_RF_A@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	cmpl	(%r13), %ebx
	jge	LBB0_12
## %bb.10:
	movq	_RF6052_REG_MODE_AG@GOTPCREL(%rip), %r15
	movq	_MODE_AG_CHANNEL_MASK@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_read_rfreg
	movl	(%r14), %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%r12d, %ecx
	movl	(%r15), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_write_rfreg
	incl	%ebx
	cmpl	(%r13), %ebx
	jl	LBB0_11
LBB0_12:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	leal	10(,%rax,4), %ebx
	movq	_REG_SIFS_CCK@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	incq	%rsi
	movq	%r13, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write8
	movq	_REG_SIFS_OFDM@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	incq	%rsi
	movq	%r13, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write8
	movq	_REG_R2T_SIFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2056, %edx                     ## imm = 0x808
	callq	_rtl8xxxu_write16
	movq	_REG_T2T_SIFS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	$2570, %edx                     ## imm = 0xA0A
	callq	_rtl8xxxu_write16
	movq	_RF_A@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	cmpl	(%r13), %ebx
	movq	-64(%rbp), %r14                 ## 8-byte Reload
	jge	LBB0_15
## %bb.13:
	movq	_RF6052_REG_MODE_AG@GOTPCREL(%rip), %r15
	movq	_MODE_AG_CHANNEL_20MHZ@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r15), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_read_rfreg
	movl	(%r12), %ecx
	movl	%ecx, %edx
	notl	%edx
	andl	%eax, %edx
	orl	%eax, %ecx
	cmpl	$128, (%r14)
	cmovel	%edx, %ecx
	movl	(%r15), %edx
	movq	%r13, %rdi
	movl	%ebx, %esi
	callq	_rtl8xxxu_write_rfreg
	incl	%ebx
	cmpl	(%r13), %ebx
	jl	LBB0_14
LBB0_15:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_BW_OPMODE,8,3              ## @REG_BW_OPMODE
	.comm	_REG_RESPONSE_RATE_SET,4,2      ## @REG_RESPONSE_RATE_SET
	.comm	_BW_OPMODE_20MHZ,4,2            ## @BW_OPMODE_20MHZ
	.comm	_REG_FPGA0_RF_MODE,4,2          ## @REG_FPGA0_RF_MODE
	.comm	_FPGA_RF_MODE,4,2               ## @FPGA_RF_MODE
	.comm	_REG_FPGA1_RF_MODE,4,2          ## @REG_FPGA1_RF_MODE
	.comm	_REG_FPGA0_ANALOG2,4,2          ## @REG_FPGA0_ANALOG2
	.comm	_FPGA0_ANALOG2_20MHZ,4,2        ## @FPGA0_ANALOG2_20MHZ
	.comm	_RSR_RSC_BANDWIDTH_40M,4,2      ## @RSR_RSC_BANDWIDTH_40M
	.comm	_RSR_RSC_UPPER_SUB_CHANNEL,4,2  ## @RSR_RSC_UPPER_SUB_CHANNEL
	.comm	_RSR_RSC_LOWER_SUB_CHANNEL,4,2  ## @RSR_RSC_LOWER_SUB_CHANNEL
	.comm	_REG_CCK0_SYSTEM,4,2            ## @REG_CCK0_SYSTEM
	.comm	_CCK0_SIDEBAND,4,2              ## @CCK0_SIDEBAND
	.comm	_REG_OFDM1_LSTF,4,2             ## @REG_OFDM1_LSTF
	.comm	_OFDM_LSTF_PRIME_CH_MASK,4,2    ## @OFDM_LSTF_PRIME_CH_MASK
	.comm	_OFDM_LSTF_PRIME_CH_LOW,4,2     ## @OFDM_LSTF_PRIME_CH_LOW
	.comm	_OFDM_LSTF_PRIME_CH_HIGH,4,2    ## @OFDM_LSTF_PRIME_CH_HIGH
	.comm	_REG_FPGA0_POWER_SAVE,4,2       ## @REG_FPGA0_POWER_SAVE
	.comm	_FPGA0_PS_LOWER_CHANNEL,4,2     ## @FPGA0_PS_LOWER_CHANNEL
	.comm	_FPGA0_PS_UPPER_CHANNEL,4,2     ## @FPGA0_PS_UPPER_CHANNEL
	.comm	_RF_A,4,2                       ## @RF_A
	.comm	_RF6052_REG_MODE_AG,4,2         ## @RF6052_REG_MODE_AG
	.comm	_MODE_AG_CHANNEL_MASK,4,2       ## @MODE_AG_CHANNEL_MASK
	.comm	_REG_SIFS_CCK,8,3               ## @REG_SIFS_CCK
	.comm	_REG_SIFS_OFDM,8,3              ## @REG_SIFS_OFDM
	.comm	_REG_R2T_SIFS,4,2               ## @REG_R2T_SIFS
	.comm	_REG_T2T_SIFS,4,2               ## @REG_T2T_SIFS
	.comm	_MODE_AG_CHANNEL_20MHZ,4,2      ## @MODE_AG_CHANNEL_20MHZ
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rtl8xxxu_gen1_config_channel   ; -- Begin function rtl8xxxu_gen1_config_channel
	.p2align	2
_rtl8xxxu_gen1_config_channel:          ; @rtl8xxxu_gen1_config_channel
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x0
	ldr	x20, [x0, #24]
Lloh0:
	adrp	x26, _REG_BW_OPMODE@GOTPAGE
Lloh1:
	ldr	x26, [x26, _REG_BW_OPMODE@GOTPAGEOFF]
	ldr	x1, [x26]
	mov	x0, x20
	bl	_rtl8xxxu_read8
	mov	x21, x0
Lloh2:
	adrp	x27, _REG_RESPONSE_RATE_SET@GOTPAGE
Lloh3:
	ldr	x27, [x27, _REG_RESPONSE_RATE_SET@GOTPAGEOFF]
	ldr	w1, [x27]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	ldr	x9, [x19, #8]
	ldr	w23, [x9]
	ldr	w8, [x19]
	cmp	w8, #128
	b.eq	LBB0_5
; %bb.1:
	mov	w22, #1
	cmp	w8, #130
	b.eq	LBB0_4
; %bb.2:
	cmp	w8, #129
	b.ne	LBB0_7
; %bb.3:
	mov	w22, #0
LBB0_4:
Lloh4:
	adrp	x8, _BW_OPMODE_20MHZ@GOTPAGE
Lloh5:
	ldr	x8, [x8, _BW_OPMODE_20MHZ@GOTPAGEOFF]
Lloh6:
	ldr	w8, [x8]
	orr	w2, w8, w21
	ldr	x1, [x26]
	mov	x0, x20
	bl	_rtl8xxxu_write8
Lloh7:
	adrp	x21, _REG_FPGA0_RF_MODE@GOTPAGE
Lloh8:
	ldr	x21, [x21, _REG_FPGA0_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh9:
	adrp	x24, _FPGA_RF_MODE@GOTPAGE
Lloh10:
	ldr	x24, [x24, _FPGA_RF_MODE@GOTPAGEOFF]
	ldr	w8, [x24]
	bic	w2, w0, w8
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh11:
	adrp	x21, _REG_FPGA1_RF_MODE@GOTPAGE
Lloh12:
	ldr	x21, [x21, _REG_FPGA1_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	ldr	w8, [x24]
	bic	w2, w0, w8
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh13:
	adrp	x21, _REG_FPGA0_ANALOG2@GOTPAGE
Lloh14:
	ldr	x21, [x21, _REG_FPGA0_ANALOG2@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh15:
	adrp	x8, _FPGA0_ANALOG2_20MHZ@GOTPAGE
Lloh16:
	ldr	x8, [x8, _FPGA0_ANALOG2_20MHZ@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	orr	w2, w8, w0
	b	LBB0_6
LBB0_5:
	mov	x22, x0
	ldr	w24, [x19, #16]
	ldr	w25, [x9, #4]
Lloh18:
	adrp	x8, _BW_OPMODE_20MHZ@GOTPAGE
Lloh19:
	ldr	x8, [x8, _BW_OPMODE_20MHZ@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	bic	w2, w21, w8
	ldr	x1, [x26]
	mov	x0, x20
	bl	_rtl8xxxu_write8
Lloh21:
	adrp	x8, _RSR_RSC_BANDWIDTH_40M@GOTPAGE
Lloh22:
	ldr	x8, [x8, _RSR_RSC_BANDWIDTH_40M@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _RSR_RSC_UPPER_SUB_CHANNEL@GOTPAGE
Lloh25:
	ldr	x9, [x9, _RSR_RSC_UPPER_SUB_CHANNEL@GOTPAGEOFF]
Lloh26:
	adrp	x10, _RSR_RSC_LOWER_SUB_CHANNEL@GOTPAGE
Lloh27:
	ldr	x10, [x10, _RSR_RSC_LOWER_SUB_CHANNEL@GOTPAGEOFF]
	bic	w8, w22, w8
	cmp	w24, w25
	csel	x9, x9, x10, gt
	ldr	w9, [x9]
	orr	w2, w9, w8
	ldr	w1, [x27]
Lloh28:
	adrp	x8, _OFDM_LSTF_PRIME_CH_LOW@GOTPAGE
Lloh29:
	ldr	x8, [x8, _OFDM_LSTF_PRIME_CH_LOW@GOTPAGEOFF]
Lloh30:
	adrp	x9, _OFDM_LSTF_PRIME_CH_HIGH@GOTPAGE
Lloh31:
	ldr	x9, [x9, _OFDM_LSTF_PRIME_CH_HIGH@GOTPAGEOFF]
	csel	x21, x8, x9, gt
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh32:
	adrp	x22, _REG_FPGA0_RF_MODE@GOTPAGE
Lloh33:
	ldr	x22, [x22, _REG_FPGA0_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh34:
	adrp	x26, _FPGA_RF_MODE@GOTPAGE
Lloh35:
	ldr	x26, [x26, _FPGA_RF_MODE@GOTPAGEOFF]
	ldr	w8, [x26]
	orr	w2, w8, w0
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh36:
	adrp	x22, _REG_FPGA1_RF_MODE@GOTPAGE
Lloh37:
	ldr	x22, [x22, _REG_FPGA1_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	ldr	w8, [x26]
	orr	w2, w8, w0
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh38:
	adrp	x22, _REG_CCK0_SYSTEM@GOTPAGE
Lloh39:
	ldr	x22, [x22, _REG_CCK0_SYSTEM@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh40:
	adrp	x8, _CCK0_SIDEBAND@GOTPAGE
Lloh41:
	ldr	x8, [x8, _CCK0_SIDEBAND@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	bic	w9, w0, w8
	orr	w8, w8, w0
	cmp	w24, w25
	csel	w2, w9, w8, gt
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh43:
	adrp	x22, _REG_OFDM1_LSTF@GOTPAGE
Lloh44:
	ldr	x22, [x22, _REG_OFDM1_LSTF@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh45:
	adrp	x8, _OFDM_LSTF_PRIME_CH_MASK@GOTPAGE
Lloh46:
	ldr	x8, [x8, _OFDM_LSTF_PRIME_CH_MASK@GOTPAGEOFF]
Lloh47:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x21]
	orr	w2, w9, w8
	ldr	w1, [x22]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh48:
	adrp	x21, _REG_FPGA0_ANALOG2@GOTPAGE
Lloh49:
	ldr	x21, [x21, _REG_FPGA0_ANALOG2@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_read32
Lloh50:
	adrp	x8, _FPGA0_ANALOG2_20MHZ@GOTPAGE
Lloh51:
	ldr	x8, [x8, _FPGA0_ANALOG2_20MHZ@GOTPAGEOFF]
Lloh52:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_write32
Lloh53:
	adrp	x21, _REG_FPGA0_POWER_SAVE@GOTPAGE
Lloh54:
	ldr	x21, [x21, _REG_FPGA0_POWER_SAVE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_read32
	mov	w8, #2
Lloh55:
	adrp	x9, _FPGA0_PS_LOWER_CHANNEL@GOTPAGE
Lloh56:
	ldr	x9, [x9, _FPGA0_PS_LOWER_CHANNEL@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
Lloh58:
	adrp	x10, _FPGA0_PS_UPPER_CHANNEL@GOTPAGE
Lloh59:
	ldr	x10, [x10, _FPGA0_PS_UPPER_CHANNEL@GOTPAGEOFF]
Lloh60:
	ldr	w10, [x10]
	cmp	w24, w25
	csel	w11, w10, w9, gt
	cneg	w8, w8, le
	add	w23, w8, w23
	orr	w8, w10, w9
	bic	w8, w0, w8
	orr	w2, w8, w11
	mov	w22, #1
LBB0_6:
	ldr	w1, [x21]
	mov	x0, x20
	bl	_rtl8xxxu_write32
LBB0_7:
Lloh61:
	adrp	x25, _RF_A@GOTPAGE
Lloh62:
	ldr	x25, [x25, _RF_A@GOTPAGEOFF]
	ldr	w21, [x25]
	ldr	w8, [x20]
Lloh63:
	adrp	x24, _RF6052_REG_MODE_AG@GOTPAGE
Lloh64:
	ldr	x24, [x24, _RF6052_REG_MODE_AG@GOTPAGEOFF]
	cmp	w21, w8
	b.ge	LBB0_10
; %bb.8:
Lloh65:
	adrp	x26, _MODE_AG_CHANNEL_MASK@GOTPAGE
Lloh66:
	ldr	x26, [x26, _MODE_AG_CHANNEL_MASK@GOTPAGEOFF]
LBB0_9:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x24]
	mov	x0, x20
	mov	x1, x21
	bl	_rtl8xxxu_read_rfreg
	ldr	w8, [x26]
	bic	w8, w0, w8
	orr	w3, w8, w23
	ldr	w2, [x24]
	mov	x0, x20
	mov	x1, x21
	bl	_rtl8xxxu_write_rfreg
	add	w21, w21, #1
	ldr	w8, [x20]
	cmp	w21, w8
	b.lt	LBB0_9
LBB0_10:
	mov	w8, #14
	mov	w9, #10
	cmp	w22, #0
	csel	w21, w9, w8, eq
Lloh67:
	adrp	x8, _REG_SIFS_CCK@GOTPAGE
Lloh68:
	ldr	x8, [x8, _REG_SIFS_CCK@GOTPAGEOFF]
Lloh69:
	ldr	x8, [x8]
	add	x1, x8, #1
	mov	x0, x20
	mov	x2, x21
	bl	_rtl8xxxu_write8
Lloh70:
	adrp	x8, _REG_SIFS_OFDM@GOTPAGE
Lloh71:
	ldr	x8, [x8, _REG_SIFS_OFDM@GOTPAGEOFF]
Lloh72:
	ldr	x8, [x8]
	add	x1, x8, #1
	mov	x0, x20
	mov	x2, x21
	bl	_rtl8xxxu_write8
Lloh73:
	adrp	x8, _REG_R2T_SIFS@GOTPAGE
Lloh74:
	ldr	x8, [x8, _REG_R2T_SIFS@GOTPAGEOFF]
Lloh75:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2056
	bl	_rtl8xxxu_write16
Lloh76:
	adrp	x8, _REG_T2T_SIFS@GOTPAGE
Lloh77:
	ldr	x8, [x8, _REG_T2T_SIFS@GOTPAGEOFF]
Lloh78:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #2570
	bl	_rtl8xxxu_write16
	ldr	w21, [x25]
	ldr	w8, [x20]
	cmp	w21, w8
	b.ge	LBB0_13
; %bb.11:
Lloh79:
	adrp	x22, _MODE_AG_CHANNEL_20MHZ@GOTPAGE
Lloh80:
	ldr	x22, [x22, _MODE_AG_CHANNEL_20MHZ@GOTPAGEOFF]
LBB0_12:                                ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x24]
	mov	x0, x20
	mov	x1, x21
	bl	_rtl8xxxu_read_rfreg
	ldr	w8, [x19]
	ldr	w9, [x22]
	bic	w10, w0, w9
	orr	w9, w9, w0
	cmp	w8, #128
	csel	w3, w10, w9, eq
	ldr	w2, [x24]
	mov	x0, x20
	mov	x1, x21
	bl	_rtl8xxxu_write_rfreg
	add	w21, w21, #1
	ldr	w8, [x20]
	cmp	w21, w8
	b.lt	LBB0_12
LBB0_13:
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGot	Lloh79, Lloh80
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_BW_OPMODE,8,3              ; @REG_BW_OPMODE
	.comm	_REG_RESPONSE_RATE_SET,4,2      ; @REG_RESPONSE_RATE_SET
	.comm	_BW_OPMODE_20MHZ,4,2            ; @BW_OPMODE_20MHZ
	.comm	_REG_FPGA0_RF_MODE,4,2          ; @REG_FPGA0_RF_MODE
	.comm	_FPGA_RF_MODE,4,2               ; @FPGA_RF_MODE
	.comm	_REG_FPGA1_RF_MODE,4,2          ; @REG_FPGA1_RF_MODE
	.comm	_REG_FPGA0_ANALOG2,4,2          ; @REG_FPGA0_ANALOG2
	.comm	_FPGA0_ANALOG2_20MHZ,4,2        ; @FPGA0_ANALOG2_20MHZ
	.comm	_RSR_RSC_BANDWIDTH_40M,4,2      ; @RSR_RSC_BANDWIDTH_40M
	.comm	_RSR_RSC_UPPER_SUB_CHANNEL,4,2  ; @RSR_RSC_UPPER_SUB_CHANNEL
	.comm	_RSR_RSC_LOWER_SUB_CHANNEL,4,2  ; @RSR_RSC_LOWER_SUB_CHANNEL
	.comm	_REG_CCK0_SYSTEM,4,2            ; @REG_CCK0_SYSTEM
	.comm	_CCK0_SIDEBAND,4,2              ; @CCK0_SIDEBAND
	.comm	_REG_OFDM1_LSTF,4,2             ; @REG_OFDM1_LSTF
	.comm	_OFDM_LSTF_PRIME_CH_MASK,4,2    ; @OFDM_LSTF_PRIME_CH_MASK
	.comm	_OFDM_LSTF_PRIME_CH_LOW,4,2     ; @OFDM_LSTF_PRIME_CH_LOW
	.comm	_OFDM_LSTF_PRIME_CH_HIGH,4,2    ; @OFDM_LSTF_PRIME_CH_HIGH
	.comm	_REG_FPGA0_POWER_SAVE,4,2       ; @REG_FPGA0_POWER_SAVE
	.comm	_FPGA0_PS_LOWER_CHANNEL,4,2     ; @FPGA0_PS_LOWER_CHANNEL
	.comm	_FPGA0_PS_UPPER_CHANNEL,4,2     ; @FPGA0_PS_UPPER_CHANNEL
	.comm	_RF_A,4,2                       ; @RF_A
	.comm	_RF6052_REG_MODE_AG,4,2         ; @RF6052_REG_MODE_AG
	.comm	_MODE_AG_CHANNEL_MASK,4,2       ; @MODE_AG_CHANNEL_MASK
	.comm	_REG_SIFS_CCK,8,3               ; @REG_SIFS_CCK
	.comm	_REG_SIFS_OFDM,8,3              ; @REG_SIFS_OFDM
	.comm	_REG_R2T_SIFS,4,2               ; @REG_R2T_SIFS
	.comm	_REG_T2T_SIFS,4,2               ; @REG_T2T_SIFS
	.comm	_MODE_AG_CHANNEL_20MHZ,4,2      ; @MODE_AG_CHANNEL_20MHZ
.subsections_via_symbols
