	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_phy_cfg_cmu_clk_type
_xgene_phy_cfg_cmu_clk_type:            ## @xgene_phy_cfg_cmu_clk_type
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r15d
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_CMU_REG12@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-36(%rbp), %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG12_STATE_DELAY9_SET
	movl	%eax, -36(%rbp)
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG13@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$546, %ecx                      ## imm = 0x222
	callq	_cmu_wr
	movq	_CMU_REG14@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	$8741, %ecx                     ## imm = 0x2225
	callq	_cmu_wr
	movq	_CLK_EXT_DIFF@GOTPCREL(%rip), %rax
	cmpl	%r15d, (%rax)
	jne	LBB0_2
## %bb.1:
	movq	_CMU_REG0@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-36(%rbp), %r15
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	xorl	%esi, %esi
	callq	_CMU_REG0_PLL_REF_SEL_SET
	movl	%eax, -36(%rbp)
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	xorl	%esi, %esi
	callq	_CMU_REG1_REFCLK_CMOS_SEL_SET
	movl	%eax, -36(%rbp)
	leaq	L_.str(%rip), %r15
	jmp	LBB0_6
LBB0_2:
	movq	_CLK_INT_DIFF@GOTPCREL(%rip), %rax
	cmpl	%r15d, (%rax)
	jne	LBB0_4
## %bb.3:
	movq	_CMU_REG0@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-36(%rbp), %r15
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG0_PLL_REF_SEL_SET
	movl	%eax, -36(%rbp)
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG1_REFCLK_CMOS_SEL_SET
	movl	%eax, -36(%rbp)
	leaq	L_.str.1(%rip), %r15
	jmp	LBB0_6
LBB0_4:
	movq	_CLK_INT_SING@GOTPCREL(%rip), %rax
	cmpl	%r15d, (%rax)
	jne	LBB0_7
## %bb.5:
	movq	_CMU_REG1@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-36(%rbp), %r15
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	movl	$1, %esi
	callq	_CMU_REG1_REFCLK_CMOS_SEL_SET
	movl	%eax, -36(%rbp)
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	xorl	%esi, %esi
	callq	_CMU_REG1_REFCLK_CMOS_SEL_SET
	movl	%eax, -36(%rbp)
	leaq	L_.str.2(%rip), %r15
LBB0_6:
	movq	_CMU_REG1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movl	(%rbx), %edi
	movq	%r15, %rsi
	callq	_dev_dbg
LBB0_7:
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CMU_REG12,4,2                  ## @CMU_REG12
	.comm	_CMU_REG13,4,2                  ## @CMU_REG13
	.comm	_CMU_REG14,4,2                  ## @CMU_REG14
	.comm	_CLK_EXT_DIFF,4,2               ## @CLK_EXT_DIFF
	.comm	_CMU_REG0,4,2                   ## @CMU_REG0
	.comm	_CMU_REG1,4,2                   ## @CMU_REG1
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Set external reference clock\n"

	.comm	_CLK_INT_DIFF,4,2               ## @CLK_INT_DIFF
L_.str.1:                               ## @.str.1
	.asciz	"Set internal reference clock\n"

	.comm	_CLK_INT_SING,4,2               ## @CLK_INT_SING
L_.str.2:                               ## @.str.2
	.asciz	"Set internal single ended reference clock\n"

	.no_dead_strip	_xgene_phy_cfg_cmu_clk_type
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_phy_cfg_cmu_clk_type
_xgene_phy_cfg_cmu_clk_type:            ; @xgene_phy_cfg_cmu_clk_type
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x22, _CMU_REG12@GOTPAGE
Lloh1:
	ldr	x22, [x22, _CMU_REG12@GOTPAGEOFF]
	ldr	w2, [x22]
	add	x3, sp, #12
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG12_STATE_DELAY9_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x22]
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_wr
Lloh2:
	adrp	x8, _CMU_REG13@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CMU_REG13@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #546
	bl	_cmu_wr
Lloh5:
	adrp	x8, _CMU_REG14@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CMU_REG14@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	mov	w3, #8741
	bl	_cmu_wr
Lloh8:
	adrp	x8, _CLK_EXT_DIFF@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CLK_EXT_DIFF@GOTPAGEOFF]
Lloh10:
	ldr	w8, [x8]
Lloh11:
	adrp	x22, _CMU_REG1@GOTPAGE
Lloh12:
	ldr	x22, [x22, _CMU_REG1@GOTPAGEOFF]
	cmp	w8, w21
	b.ne	LBB0_2
; %bb.1:
Lloh13:
	adrp	x21, _CMU_REG0@GOTPAGE
Lloh14:
	ldr	x21, [x21, _CMU_REG0@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_CMU_REG0_PLL_REF_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_wr
	ldr	w2, [x22]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_CMU_REG1_REFCLK_CMOS_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
Lloh15:
	adrp	x21, l_.str@PAGE
Lloh16:
	add	x21, x21, l_.str@PAGEOFF
	b	LBB0_6
LBB0_2:
Lloh17:
	adrp	x8, _CLK_INT_DIFF@GOTPAGE
Lloh18:
	ldr	x8, [x8, _CLK_INT_DIFF@GOTPAGEOFF]
Lloh19:
	ldr	w8, [x8]
	cmp	w8, w21
	b.ne	LBB0_4
; %bb.3:
Lloh20:
	adrp	x21, _CMU_REG0@GOTPAGE
Lloh21:
	ldr	x21, [x21, _CMU_REG0@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG0_PLL_REF_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_wr
	ldr	w2, [x22]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG1_REFCLK_CMOS_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
Lloh22:
	adrp	x21, l_.str.1@PAGE
Lloh23:
	add	x21, x21, l_.str.1@PAGEOFF
	b	LBB0_6
LBB0_4:
Lloh24:
	adrp	x8, _CLK_INT_SING@GOTPAGE
Lloh25:
	ldr	x8, [x8, _CLK_INT_SING@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	cmp	w8, w21
	b.ne	LBB0_7
; %bb.5:
	ldr	w2, [x22]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG1_REFCLK_CMOS_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x22]
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_wr
	ldr	w2, [x22]
	add	x3, sp, #12
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #0
	bl	_CMU_REG1_REFCLK_CMOS_SEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
Lloh27:
	adrp	x21, l_.str.2@PAGE
Lloh28:
	add	x21, x21, l_.str.2@PAGEOFF
LBB0_6:
	ldr	w2, [x22]
	mov	x0, x19
	mov	x1, x20
	bl	_cmu_wr
	ldr	w0, [x19]
	mov	x1, x21
	bl	_dev_dbg
LBB0_7:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.cfi_endproc
                                        ; -- End function
	.comm	_CMU_REG12,4,2                  ; @CMU_REG12
	.comm	_CMU_REG13,4,2                  ; @CMU_REG13
	.comm	_CMU_REG14,4,2                  ; @CMU_REG14
	.comm	_CLK_EXT_DIFF,4,2               ; @CLK_EXT_DIFF
	.comm	_CMU_REG0,4,2                   ; @CMU_REG0
	.comm	_CMU_REG1,4,2                   ; @CMU_REG1
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Set external reference clock\n"

	.comm	_CLK_INT_DIFF,4,2               ; @CLK_INT_DIFF
l_.str.1:                               ; @.str.1
	.asciz	"Set internal reference clock\n"

	.comm	_CLK_INT_SING,4,2               ; @CLK_INT_SING
l_.str.2:                               ; @.str.2
	.asciz	"Set internal single ended reference clock\n"

	.no_dead_strip	_xgene_phy_cfg_cmu_clk_type
.subsections_via_symbols
