	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dw_pcie_setup_rc               ## -- Begin function dw_pcie_setup_rc
	.p2align	4, 0x90
_dw_pcie_setup_rc:                      ## @dw_pcie_setup_rc
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_to_dw_pcie_from_pp
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_dw_pcie_dbi_ro_wr_en
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	callq	_dw_pcie_setup
	movq	40(%r12), %rax
	cmpl	$0, 4(%rax)
	jne	LBB0_7
## %bb.1:
	movq	(%r12), %rax
	movq	_MAX_MSI_IRQS_PER_CTRL@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	cmpq	%rax, %rcx
	ja	LBB0_7
## %bb.2:
	movq	%rax, %rdx
	orq	%rcx, %rdx
	shrq	$32, %rdx
	je	LBB0_3
## %bb.4:
	xorl	%edx, %edx
	divq	%rcx
	jmp	LBB0_5
LBB0_3:
                                        ## kill: def $eax killed $eax killed $rax
	xorl	%edx, %edx
	divl	%ecx
                                        ## kill: def $eax killed $eax def $rax
LBB0_5:
	cmpq	$2, %rax
	movl	$1, %r15d
	cmovaeq	%rax, %r15
	xorl	%ebx, %ebx
	movq	_MSI_REG_CTRL_BLOCK_SIZE@GOTPCREL(%rip), %r14
	movq	_PCIE_MSI_INTR0_ENABLE@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r12), %rax
	movq	$-1, (%rax,%rbx,8)
	movq	(%r14), %rsi
	imulq	%rbx, %rsi
	movq	_PCIE_MSI_INTR0_MASK@GOTPCREL(%rip), %rax
	addq	(%rax), %rsi
	movq	%r12, %rdi
	movl	$4, %edx
	movq	$-1, %rcx
	callq	_dw_pcie_wr_own_conf
	movq	(%r14), %rsi
	imulq	%rbx, %rsi
	addq	(%r13), %rsi
	movq	%r12, %rdi
	movl	$4, %edx
	movq	$-1, %rcx
	callq	_dw_pcie_wr_own_conf
	incq	%rbx
	cmpq	%r15, %rbx
	jne	LBB0_6
LBB0_7:
	movq	_PCI_BASE_ADDRESS_0@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	movl	$4, %edx
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PCI_BASE_ADDRESS_1@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCI_INTERRUPT_LINE@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	andl	$-65281, %eax                   ## imm = 0xFFFF00FF
	leaq	256(%rax), %rdx
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PCI_PRIMARY_BUS@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	andl	$-16777216, %eax                ## imm = 0xFF000000
	leaq	16711936(%rax), %rdx
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PCI_COMMAND@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	andl	$-65536, %eax                   ## imm = 0xFFFF0000
	movq	_PCI_COMMAND_IO@GOTPCREL(%rip), %rcx
	movq	_PCI_COMMAND_MEMORY@GOTPCREL(%rip), %rdx
	movq	_PCI_COMMAND_MASTER@GOTPCREL(%rip), %rsi
	movq	_PCI_COMMAND_SERR@GOTPCREL(%rip), %rdi
	orq	(%rcx), %rax
	orq	(%rdx), %rax
	orq	(%rsi), %rax
	orq	(%rdi), %rax
	movq	%rax, -48(%rbp)
	movq	(%r14), %rsi
	movq	%rbx, %rdi
	movq	%rax, %rdx
	callq	_dw_pcie_writel_dbi
	movq	40(%r12), %rax
	cmpl	$0, (%rax)
	jne	LBB0_10
## %bb.8:
	movq	_PCIE_ATU_REGION_INDEX0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_ATU_TYPE_MEM@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	36(%r12), %ecx
	movl	28(%r12), %r9d
	movl	32(%r12), %r8d
	movq	%rbx, %rdi
	callq	_dw_pcie_prog_outbound_atu
	cmpl	$3, (%rbx)
	jl	LBB0_10
## %bb.9:
	movq	_PCIE_ATU_REGION_INDEX2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_ATU_TYPE_IO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	24(%r12), %ecx
	movl	16(%r12), %r9d
	movl	20(%r12), %r8d
	movq	%rbx, %rdi
	callq	_dw_pcie_prog_outbound_atu
LBB0_10:
	movq	(%r15), %rsi
	movq	%r12, %rdi
	movl	$4, %edx
	xorl	%ecx, %ecx
	callq	_dw_pcie_wr_own_conf
	movq	_PCI_CLASS_DEVICE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_PCI_CLASS_BRIDGE_PCI@GOTPCREL(%rip), %rax
	movq	(%rax), %rcx
	movq	%r12, %rdi
	movl	$2, %edx
	callq	_dw_pcie_wr_own_conf
	movq	_PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	leaq	-48(%rbp), %rcx
	movq	%r12, %rdi
	movl	$4, %edx
	callq	_dw_pcie_rd_own_conf
	movq	_PORT_LOGIC_SPEED_CHANGE@GOTPCREL(%rip), %rax
	movq	-48(%rbp), %rcx
	orq	(%rax), %rcx
	movq	%rcx, -48(%rbp)
	movq	(%r14), %rsi
	movq	%r12, %rdi
	movl	$4, %edx
	callq	_dw_pcie_wr_own_conf
	movq	%rbx, %rdi
	callq	_dw_pcie_dbi_ro_wr_dis
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MAX_MSI_IRQS_PER_CTRL,8,3      ## @MAX_MSI_IRQS_PER_CTRL
	.comm	_PCIE_MSI_INTR0_MASK,8,3        ## @PCIE_MSI_INTR0_MASK
	.comm	_MSI_REG_CTRL_BLOCK_SIZE,8,3    ## @MSI_REG_CTRL_BLOCK_SIZE
	.comm	_PCIE_MSI_INTR0_ENABLE,8,3      ## @PCIE_MSI_INTR0_ENABLE
	.comm	_PCI_BASE_ADDRESS_0,8,3         ## @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_1,8,3         ## @PCI_BASE_ADDRESS_1
	.comm	_PCI_INTERRUPT_LINE,8,3         ## @PCI_INTERRUPT_LINE
	.comm	_PCI_PRIMARY_BUS,8,3            ## @PCI_PRIMARY_BUS
	.comm	_PCI_COMMAND,8,3                ## @PCI_COMMAND
	.comm	_PCI_COMMAND_IO,8,3             ## @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,8,3         ## @PCI_COMMAND_MEMORY
	.comm	_PCI_COMMAND_MASTER,8,3         ## @PCI_COMMAND_MASTER
	.comm	_PCI_COMMAND_SERR,8,3           ## @PCI_COMMAND_SERR
	.comm	_PCIE_ATU_REGION_INDEX0,4,2     ## @PCIE_ATU_REGION_INDEX0
	.comm	_PCIE_ATU_TYPE_MEM,4,2          ## @PCIE_ATU_TYPE_MEM
	.comm	_PCIE_ATU_REGION_INDEX2,4,2     ## @PCIE_ATU_REGION_INDEX2
	.comm	_PCIE_ATU_TYPE_IO,4,2           ## @PCIE_ATU_TYPE_IO
	.comm	_PCI_CLASS_DEVICE,8,3           ## @PCI_CLASS_DEVICE
	.comm	_PCI_CLASS_BRIDGE_PCI,8,3       ## @PCI_CLASS_BRIDGE_PCI
	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,8,3 ## @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_PORT_LOGIC_SPEED_CHANGE,8,3    ## @PORT_LOGIC_SPEED_CHANGE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dw_pcie_setup_rc               ; -- Begin function dw_pcie_setup_rc
	.p2align	2
_dw_pcie_setup_rc:                      ; @dw_pcie_setup_rc
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #96
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x0
	bl	_to_dw_pcie_from_pp
	mov	x19, x0
	bl	_dw_pcie_dbi_ro_wr_en
	mov	x0, x19
	bl	_dw_pcie_setup
	ldr	x8, [x20, #40]
	ldr	w8, [x8, #4]
	cbnz	w8, LBB0_4
; %bb.1:
	ldr	x8, [x20]
Lloh0:
	adrp	x9, _MAX_MSI_IRQS_PER_CTRL@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MAX_MSI_IRQS_PER_CTRL@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x9, x8
	b.hi	LBB0_4
; %bb.2:
	mov	x21, #0
	udiv	x8, x8, x9
	cmp	x8, #1
	csinc	x22, x8, xzr, hi
	mov	x23, #-1
Lloh3:
	adrp	x24, _PCIE_MSI_INTR0_MASK@GOTPAGE
Lloh4:
	ldr	x24, [x24, _PCIE_MSI_INTR0_MASK@GOTPAGEOFF]
Lloh5:
	adrp	x25, _MSI_REG_CTRL_BLOCK_SIZE@GOTPAGE
Lloh6:
	ldr	x25, [x25, _MSI_REG_CTRL_BLOCK_SIZE@GOTPAGEOFF]
Lloh7:
	adrp	x26, _PCIE_MSI_INTR0_ENABLE@GOTPAGE
Lloh8:
	ldr	x26, [x26, _PCIE_MSI_INTR0_ENABLE@GOTPAGEOFF]
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #8]
	str	x23, [x8, x21, lsl #3]
	ldr	x8, [x24]
	ldr	x9, [x25]
	madd	x1, x9, x21, x8
	mov	x0, x20
	mov	w2, #4
	mov	x3, #-1
	bl	_dw_pcie_wr_own_conf
	ldr	x8, [x26]
	ldr	x9, [x25]
	madd	x1, x9, x21, x8
	mov	x0, x20
	mov	w2, #4
	mov	x3, #-1
	bl	_dw_pcie_wr_own_conf
	add	x21, x21, #1
	cmp	x21, x22
	b.ne	LBB0_3
LBB0_4:
Lloh9:
	adrp	x21, _PCI_BASE_ADDRESS_0@GOTPAGE
Lloh10:
	ldr	x21, [x21, _PCI_BASE_ADDRESS_0@GOTPAGEOFF]
	ldr	x1, [x21]
	mov	x0, x19
	mov	w2, #4
	bl	_dw_pcie_writel_dbi
Lloh11:
	adrp	x8, _PCI_BASE_ADDRESS_1@GOTPAGE
Lloh12:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_1@GOTPAGEOFF]
Lloh13:
	ldr	x1, [x8]
	mov	x0, x19
	mov	x2, #0
	bl	_dw_pcie_writel_dbi
Lloh14:
	adrp	x22, _PCI_INTERRUPT_LINE@GOTPAGE
Lloh15:
	ldr	x22, [x22, _PCI_INTERRUPT_LINE@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	and	x8, x0, #0xffffffff
	and	x8, x8, #0xffffffffffff00ff
	orr	x2, x8, #0x100
	ldr	x1, [x22]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
Lloh16:
	adrp	x22, _PCI_PRIMARY_BUS@GOTPAGE
Lloh17:
	ldr	x22, [x22, _PCI_PRIMARY_BUS@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	and	x8, x0, #0xff000000
	mov	w9, #256
	movk	w9, #255, lsl #16
	orr	x2, x8, x9
	ldr	x1, [x22]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
Lloh18:
	adrp	x22, _PCI_COMMAND@GOTPAGE
Lloh19:
	ldr	x22, [x22, _PCI_COMMAND@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	and	x8, x0, #0xffff0000
Lloh20:
	adrp	x9, _PCI_COMMAND_IO@GOTPAGE
Lloh21:
	ldr	x9, [x9, _PCI_COMMAND_IO@GOTPAGEOFF]
Lloh22:
	ldr	x9, [x9]
Lloh23:
	adrp	x10, _PCI_COMMAND_MEMORY@GOTPAGE
Lloh24:
	ldr	x10, [x10, _PCI_COMMAND_MEMORY@GOTPAGEOFF]
Lloh25:
	ldr	x10, [x10]
Lloh26:
	adrp	x11, _PCI_COMMAND_MASTER@GOTPAGE
Lloh27:
	ldr	x11, [x11, _PCI_COMMAND_MASTER@GOTPAGEOFF]
Lloh28:
	ldr	x11, [x11]
Lloh29:
	adrp	x12, _PCI_COMMAND_SERR@GOTPAGE
Lloh30:
	ldr	x12, [x12, _PCI_COMMAND_SERR@GOTPAGEOFF]
Lloh31:
	ldr	x12, [x12]
	orr	x8, x9, x8
	orr	x8, x8, x10
	orr	x8, x8, x11
	orr	x2, x8, x12
	str	x2, [sp, #8]
	ldr	x1, [x22]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
	ldr	x8, [x20, #40]
	ldr	w8, [x8]
	cbnz	w8, LBB0_7
; %bb.5:
Lloh32:
	adrp	x8, _PCIE_ATU_REGION_INDEX0@GOTPAGE
Lloh33:
	ldr	x8, [x8, _PCIE_ATU_REGION_INDEX0@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
Lloh35:
	adrp	x8, _PCIE_ATU_TYPE_MEM@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PCIE_ATU_TYPE_MEM@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	ldp	w4, w3, [x20, #32]
	ldr	w5, [x20, #28]
	mov	x0, x19
	bl	_dw_pcie_prog_outbound_atu
	ldr	w8, [x19]
	cmp	w8, #3
	b.lt	LBB0_7
; %bb.6:
Lloh38:
	adrp	x8, _PCIE_ATU_REGION_INDEX2@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PCIE_ATU_REGION_INDEX2@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
Lloh41:
	adrp	x8, _PCIE_ATU_TYPE_IO@GOTPAGE
Lloh42:
	ldr	x8, [x8, _PCIE_ATU_TYPE_IO@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	ldp	w4, w3, [x20, #20]
	ldr	w5, [x20, #16]
	mov	x0, x19
	bl	_dw_pcie_prog_outbound_atu
LBB0_7:
	ldr	x1, [x21]
	mov	x0, x20
	mov	w2, #4
	mov	x3, #0
	bl	_dw_pcie_wr_own_conf
Lloh44:
	adrp	x8, _PCI_CLASS_DEVICE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _PCI_CLASS_DEVICE@GOTPAGEOFF]
Lloh46:
	ldr	x1, [x8]
Lloh47:
	adrp	x8, _PCI_CLASS_BRIDGE_PCI@GOTPAGE
Lloh48:
	ldr	x8, [x8, _PCI_CLASS_BRIDGE_PCI@GOTPAGEOFF]
Lloh49:
	ldr	x3, [x8]
	mov	x0, x20
	mov	w2, #2
	bl	_dw_pcie_wr_own_conf
Lloh50:
	adrp	x21, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGE
Lloh51:
	ldr	x21, [x21, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGEOFF]
	ldr	x1, [x21]
	add	x3, sp, #8
	mov	x0, x20
	mov	w2, #4
	bl	_dw_pcie_rd_own_conf
Lloh52:
	adrp	x8, _PORT_LOGIC_SPEED_CHANGE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _PORT_LOGIC_SPEED_CHANGE@GOTPAGEOFF]
Lloh54:
	ldr	x8, [x8]
	ldr	x9, [sp, #8]
	orr	x3, x9, x8
	str	x3, [sp, #8]
	ldr	x1, [x21]
	mov	x0, x20
	mov	w2, #4
	bl	_dw_pcie_wr_own_conf
	mov	x0, x19
	bl	_dw_pcie_dbi_ro_wr_dis
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #96
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.cfi_endproc
                                        ; -- End function
	.comm	_MAX_MSI_IRQS_PER_CTRL,8,3      ; @MAX_MSI_IRQS_PER_CTRL
	.comm	_PCIE_MSI_INTR0_MASK,8,3        ; @PCIE_MSI_INTR0_MASK
	.comm	_MSI_REG_CTRL_BLOCK_SIZE,8,3    ; @MSI_REG_CTRL_BLOCK_SIZE
	.comm	_PCIE_MSI_INTR0_ENABLE,8,3      ; @PCIE_MSI_INTR0_ENABLE
	.comm	_PCI_BASE_ADDRESS_0,8,3         ; @PCI_BASE_ADDRESS_0
	.comm	_PCI_BASE_ADDRESS_1,8,3         ; @PCI_BASE_ADDRESS_1
	.comm	_PCI_INTERRUPT_LINE,8,3         ; @PCI_INTERRUPT_LINE
	.comm	_PCI_PRIMARY_BUS,8,3            ; @PCI_PRIMARY_BUS
	.comm	_PCI_COMMAND,8,3                ; @PCI_COMMAND
	.comm	_PCI_COMMAND_IO,8,3             ; @PCI_COMMAND_IO
	.comm	_PCI_COMMAND_MEMORY,8,3         ; @PCI_COMMAND_MEMORY
	.comm	_PCI_COMMAND_MASTER,8,3         ; @PCI_COMMAND_MASTER
	.comm	_PCI_COMMAND_SERR,8,3           ; @PCI_COMMAND_SERR
	.comm	_PCIE_ATU_REGION_INDEX0,4,2     ; @PCIE_ATU_REGION_INDEX0
	.comm	_PCIE_ATU_TYPE_MEM,4,2          ; @PCIE_ATU_TYPE_MEM
	.comm	_PCIE_ATU_REGION_INDEX2,4,2     ; @PCIE_ATU_REGION_INDEX2
	.comm	_PCIE_ATU_TYPE_IO,4,2           ; @PCIE_ATU_TYPE_IO
	.comm	_PCI_CLASS_DEVICE,8,3           ; @PCI_CLASS_DEVICE
	.comm	_PCI_CLASS_BRIDGE_PCI,8,3       ; @PCI_CLASS_BRIDGE_PCI
	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,8,3 ; @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_PORT_LOGIC_SPEED_CHANGE,8,3    ; @PORT_LOGIC_SPEED_CHANGE
.subsections_via_symbols
