	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iwl_pcie_set_pwr
_iwl_pcie_set_pwr:                      ## @iwl_pcie_set_pwr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	8(%rdi), %rax
	cmpq	$0, (%rax)
	je	LBB0_1
## %bb.6:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
LBB0_1:
	movq	%rdi, %rbx
	testl	%esi, %esi
	je	LBB0_4
## %bb.2:
	movl	(%rbx), %edi
	callq	_to_pci_dev
	movq	_PCI_D3cold@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_pci_pme_capable
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_APMG_PS_CTRL_VAL_PWR_SRC_VAUX@GOTPCREL(%rip), %rax
	jmp	LBB0_5
LBB0_4:
	movq	_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN@GOTPCREL(%rip), %rax
LBB0_5:
	movq	_APMG_PS_CTRL_REG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	(%rax), %edx
	movq	_APMG_PS_CTRL_MSK_PWR_SRC@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	notl	%ecx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	jmp	_iwl_set_bits_mask_prph         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_D3cold,4,2                 ## @PCI_D3cold
	.comm	_APMG_PS_CTRL_REG,4,2           ## @APMG_PS_CTRL_REG
	.comm	_APMG_PS_CTRL_VAL_PWR_SRC_VAUX,4,2 ## @APMG_PS_CTRL_VAL_PWR_SRC_VAUX
	.comm	_APMG_PS_CTRL_MSK_PWR_SRC,4,2   ## @APMG_PS_CTRL_MSK_PWR_SRC
	.comm	_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,4,2 ## @APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
	.no_dead_strip	_iwl_pcie_set_pwr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iwl_pcie_set_pwr
_iwl_pcie_set_pwr:                      ; @iwl_pcie_set_pwr
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	ldr	x8, [x0, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_2
; %bb.1:
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
LBB0_2:
	mov	x19, x0
	cbz	w1, LBB0_5
; %bb.3:
	ldr	w0, [x19]
	bl	_to_pci_dev
Lloh0:
	adrp	x8, _PCI_D3cold@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_D3cold@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_pci_pme_capable
	cbz	x0, LBB0_5
; %bb.4:
Lloh3:
	adrp	x8, _APMG_PS_CTRL_VAL_PWR_SRC_VAUX@GOTPAGE
Lloh4:
	ldr	x8, [x8, _APMG_PS_CTRL_VAL_PWR_SRC_VAUX@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
Lloh5:
	adrp	x8, _APMG_PS_CTRL_VAL_PWR_SRC_VMAIN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _APMG_PS_CTRL_VAL_PWR_SRC_VMAIN@GOTPAGEOFF]
LBB0_6:
Lloh7:
	adrp	x9, _APMG_PS_CTRL_REG@GOTPAGE
Lloh8:
	ldr	x9, [x9, _APMG_PS_CTRL_REG@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x9]
	ldr	w2, [x8]
Lloh10:
	adrp	x8, _APMG_PS_CTRL_MSK_PWR_SRC@GOTPAGE
Lloh11:
	ldr	x8, [x8, _APMG_PS_CTRL_MSK_PWR_SRC@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	mvn	w3, w8
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_iwl_set_bits_mask_prph
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_D3cold,4,2                 ; @PCI_D3cold
	.comm	_APMG_PS_CTRL_REG,4,2           ; @APMG_PS_CTRL_REG
	.comm	_APMG_PS_CTRL_VAL_PWR_SRC_VAUX,4,2 ; @APMG_PS_CTRL_VAL_PWR_SRC_VAUX
	.comm	_APMG_PS_CTRL_MSK_PWR_SRC,4,2   ; @APMG_PS_CTRL_MSK_PWR_SRC
	.comm	_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,4,2 ; @APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
	.no_dead_strip	_iwl_pcie_set_pwr
.subsections_via_symbols
