	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath9k_hw_def_set_gain
_ath9k_hw_def_set_gain:                 ## @ath9k_hw_def_set_gain
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r9d, %r13d
	movl	%r8d, %ebx
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	movq	%rsi, -56(%rbp)                 ## 8-byte Spill
	movq	%rdi, %r12
	callq	_ENABLE_REG_RMW_BUFFER
	movq	%r12, %rdi
	callq	_ath9k_hw_def_get_eeprom_rev
	movq	_AR5416_EEP_MINOR_VER_3@GOTPCREL(%rip), %rcx
	movslq	%ebx, %r14
	movslq	%r13d, %r15
	cmpq	(%rcx), %rax
	jl	LBB0_4
## %bb.1:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	40(%rbx), %rax
	movl	(%rax,%r15,4), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%r12, %rdi
	callq	_AR_SREV_9280_20_OR_LATER
	movq	_AR_PHY_GAIN_2GHZ@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r13
	addq	%r14, %r13
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	16(%rbx), %rax
	movl	(%rax,%r15,4), %ecx
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	_REG_RMW_FIELD
	movq	_AR_PHY_GAIN_2GHZ@GOTPCREL(%rip), %r13
	movq	(%r13), %rsi
	addq	%r14, %rsi
	movq	_AR_PHY_GAIN_2GHZ_XATTEN1_DB@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%rbx), %rax
	movl	(%rax,%r15,4), %ecx
	movq	%r12, %rdi
	callq	_REG_RMW_FIELD
	movq	(%r13), %rsi
	addq	%r14, %rsi
	movq	_AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	32(%rbx), %rax
	movl	(%rax,%r15,4), %ecx
	movq	%r12, %rdi
	callq	_REG_RMW_FIELD
	movq	(%r13), %rsi
	addq	%r14, %rsi
	movq	_AR_PHY_GAIN_2GHZ_XATTEN2_DB@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	24(%rbx), %rax
	movl	(%rax,%r15,4), %ecx
	movq	%r12, %rdi
	callq	_REG_RMW_FIELD
	jmp	LBB0_4
LBB0_3:
	movq	16(%rbx), %rax
	movl	(%rax,%r15,4), %edi
	movq	_AR_PHY_GAIN_2GHZ_BSW_MARGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	movq	_AR_PHY_GAIN_2GHZ_BSW_MARGIN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	%eax, %edx
	callq	_REG_RMW
	movq	_AR_PHY_GAIN_2GHZ@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	addq	%r14, %r13
	movq	8(%rbx), %rax
	movl	(%rax,%r15,4), %edi
	movq	_AR_PHY_GAIN_2GHZ_BSW_ATTEN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_SM
	movl	(%rbx), %ecx
	movq	%r12, %rdi
	movq	%r13, %rsi
	movl	%eax, %edx
	callq	_REG_RMW
LBB0_4:
	movq	%r12, %rdi
	callq	_AR_SREV_9280_20_OR_LATER
	movq	_AR_PHY_RXGAIN@GOTPCREL(%rip), %r13
	movq	(%r13), %rbx
	addq	%r14, %rbx
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movq	_AR9280_PHY_RXGAIN_TXRX_ATTEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movl	-44(%rbp), %ecx                 ## 4-byte Reload
	callq	_REG_RMW_FIELD
	addq	(%r13), %r14
	movq	_AR9280_PHY_RXGAIN_TXRX_MARGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movl	(%rax,%r15,4), %ecx
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_REG_RMW_FIELD
	jmp	LBB0_7
LBB0_6:
	movq	_AR_PHY_RXGAIN_TXRX_ATTEN@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_SM
	movl	(%r13), %ecx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	movl	%eax, %edx
	callq	_REG_RMW
	movq	_AR_PHY_GAIN_2GHZ@GOTPCREL(%rip), %rax
	addq	(%rax), %r14
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	movq	(%rax), %rax
	movl	(%rax,%r15,4), %edi
	movq	_AR_PHY_GAIN_2GHZ_RXTX_MARGIN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_SM
	movl	(%rbx), %ecx
	movq	%r12, %rdi
	movq	%r14, %rsi
	movl	%eax, %edx
	callq	_REG_RMW
LBB0_7:
	movq	%r12, %rdi
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_RMW_BUFFER_FLUSH           ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AR5416_EEP_MINOR_VER_3,8,3     ## @AR5416_EEP_MINOR_VER_3
	.comm	_AR_PHY_GAIN_2GHZ,8,3           ## @AR_PHY_GAIN_2GHZ
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,4,2 ## @AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN1_DB,4,2 ## @AR_PHY_GAIN_2GHZ_XATTEN1_DB
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,4,2 ## @AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN2_DB,4,2 ## @AR_PHY_GAIN_2GHZ_XATTEN2_DB
	.comm	_AR_PHY_GAIN_2GHZ_BSW_MARGIN,4,2 ## @AR_PHY_GAIN_2GHZ_BSW_MARGIN
	.comm	_AR_PHY_GAIN_2GHZ_BSW_ATTEN,4,2 ## @AR_PHY_GAIN_2GHZ_BSW_ATTEN
	.comm	_AR_PHY_RXGAIN,8,3              ## @AR_PHY_RXGAIN
	.comm	_AR9280_PHY_RXGAIN_TXRX_ATTEN,4,2 ## @AR9280_PHY_RXGAIN_TXRX_ATTEN
	.comm	_AR9280_PHY_RXGAIN_TXRX_MARGIN,4,2 ## @AR9280_PHY_RXGAIN_TXRX_MARGIN
	.comm	_AR_PHY_RXGAIN_TXRX_ATTEN,4,2   ## @AR_PHY_RXGAIN_TXRX_ATTEN
	.comm	_AR_PHY_GAIN_2GHZ_RXTX_MARGIN,4,2 ## @AR_PHY_GAIN_2GHZ_RXTX_MARGIN
	.no_dead_strip	_ath9k_hw_def_set_gain
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath9k_hw_def_set_gain
_ath9k_hw_def_set_gain:                 ; @ath9k_hw_def_set_gain
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x5
	mov	x23, x4
	mov	x22, x3
	mov	x21, x1
	mov	x19, x0
	bl	_ENABLE_REG_RMW_BUFFER
	mov	x0, x19
	bl	_ath9k_hw_def_get_eeprom_rev
Lloh0:
	adrp	x8, _AR5416_EEP_MINOR_VER_3@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AR5416_EEP_MINOR_VER_3@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	cmp	x0, x8
	b.lt	LBB0_4
; %bb.1:
	ldr	x8, [x21, #40]
	sxtw	x27, w20
	ldr	w22, [x8, w20, sxtw #2]
	mov	x0, x19
	bl	_AR_SREV_9280_20_OR_LATER
Lloh3:
	adrp	x25, _AR_PHY_GAIN_2GHZ@GOTPAGE
Lloh4:
	ldr	x25, [x25, _AR_PHY_GAIN_2GHZ@GOTPAGEOFF]
	ldr	x8, [x25]
	mov	x9, x23
	sxtw	x26, w9
	add	x24, x8, x26
	cbz	x0, LBB0_3
; %bb.2:
Lloh5:
	adrp	x8, _AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	ldr	x8, [x21, #16]
	lsl	x27, x27, #2
	ldr	w3, [x8, x27]
	mov	x0, x19
	mov	x1, x24
	bl	_REG_RMW_FIELD
	ldr	x8, [x25]
	add	x1, x8, x26
Lloh8:
	adrp	x8, _AR_PHY_GAIN_2GHZ_XATTEN1_DB@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AR_PHY_GAIN_2GHZ_XATTEN1_DB@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	ldr	x8, [x21, #8]
	ldr	w3, [x8, x27]
	mov	x0, x19
	bl	_REG_RMW_FIELD
	ldr	x8, [x25]
	add	x1, x8, x26
Lloh11:
	adrp	x8, _AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	ldr	x8, [x21, #32]
	ldr	w3, [x8, x27]
	mov	x0, x19
	bl	_REG_RMW_FIELD
	ldr	x8, [x25]
	add	x1, x8, x26
Lloh14:
	adrp	x8, _AR_PHY_GAIN_2GHZ_XATTEN2_DB@GOTPAGE
Lloh15:
	ldr	x8, [x8, _AR_PHY_GAIN_2GHZ_XATTEN2_DB@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	ldr	x8, [x21, #24]
	ldr	w3, [x8, x27]
	mov	x0, x19
	bl	_REG_RMW_FIELD
	b	LBB0_4
LBB0_3:
	ldr	x8, [x21, #16]
	lsl	x27, x27, #2
	ldr	w0, [x8, x27]
Lloh17:
	adrp	x28, _AR_PHY_GAIN_2GHZ_BSW_MARGIN@GOTPAGE
Lloh18:
	ldr	x28, [x28, _AR_PHY_GAIN_2GHZ_BSW_MARGIN@GOTPAGEOFF]
	ldr	w1, [x28]
	bl	_SM
	mov	x2, x0
	ldr	w3, [x28]
	mov	x0, x19
	mov	x1, x24
	bl	_REG_RMW
	ldr	x8, [x25]
	add	x24, x8, x26
	ldr	x8, [x21, #8]
	ldr	w0, [x8, x27]
Lloh19:
	adrp	x25, _AR_PHY_GAIN_2GHZ_BSW_ATTEN@GOTPAGE
Lloh20:
	ldr	x25, [x25, _AR_PHY_GAIN_2GHZ_BSW_ATTEN@GOTPAGEOFF]
	ldr	w1, [x25]
	bl	_SM
	mov	x2, x0
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x24
	bl	_REG_RMW
LBB0_4:
	mov	x0, x19
	bl	_AR_SREV_9280_20_OR_LATER
Lloh21:
	adrp	x25, _AR_PHY_RXGAIN@GOTPAGE
Lloh22:
	ldr	x25, [x25, _AR_PHY_RXGAIN@GOTPAGEOFF]
	ldr	x8, [x25]
	sxtw	x24, w23
	add	x23, x8, x24
	cbz	x0, LBB0_6
; %bb.5:
Lloh23:
	adrp	x8, _AR9280_PHY_RXGAIN_TXRX_ATTEN@GOTPAGE
Lloh24:
	ldr	x8, [x8, _AR9280_PHY_RXGAIN_TXRX_ATTEN@GOTPAGEOFF]
Lloh25:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x23
	mov	x3, x22
	bl	_REG_RMW_FIELD
	ldr	x8, [x25]
	add	x1, x8, x24
Lloh26:
	adrp	x8, _AR9280_PHY_RXGAIN_TXRX_MARGIN@GOTPAGE
Lloh27:
	ldr	x8, [x8, _AR9280_PHY_RXGAIN_TXRX_MARGIN@GOTPAGEOFF]
Lloh28:
	ldr	w2, [x8]
	ldr	x8, [x21]
	ldr	w3, [x8, w20, sxtw #2]
	mov	x0, x19
	bl	_REG_RMW_FIELD
	b	LBB0_7
LBB0_6:
Lloh29:
	adrp	x25, _AR_PHY_RXGAIN_TXRX_ATTEN@GOTPAGE
Lloh30:
	ldr	x25, [x25, _AR_PHY_RXGAIN_TXRX_ATTEN@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x22
	bl	_SM
	mov	x2, x0
	ldr	w3, [x25]
	mov	x0, x19
	mov	x1, x23
	bl	_REG_RMW
Lloh31:
	adrp	x8, _AR_PHY_GAIN_2GHZ@GOTPAGE
Lloh32:
	ldr	x8, [x8, _AR_PHY_GAIN_2GHZ@GOTPAGEOFF]
Lloh33:
	ldr	x8, [x8]
	add	x22, x8, x24
	ldr	x8, [x21]
	ldr	w0, [x8, w20, sxtw #2]
Lloh34:
	adrp	x20, _AR_PHY_GAIN_2GHZ_RXTX_MARGIN@GOTPAGE
Lloh35:
	ldr	x20, [x20, _AR_PHY_GAIN_2GHZ_RXTX_MARGIN@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_SM
	mov	x2, x0
	ldr	w3, [x20]
	mov	x0, x19
	mov	x1, x22
	bl	_REG_RMW
LBB0_7:
	mov	x0, x19
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	b	_REG_RMW_BUFFER_FLUSH
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.cfi_endproc
                                        ; -- End function
	.comm	_AR5416_EEP_MINOR_VER_3,8,3     ; @AR5416_EEP_MINOR_VER_3
	.comm	_AR_PHY_GAIN_2GHZ,8,3           ; @AR_PHY_GAIN_2GHZ
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,4,2 ; @AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN1_DB,4,2 ; @AR_PHY_GAIN_2GHZ_XATTEN1_DB
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,4,2 ; @AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
	.comm	_AR_PHY_GAIN_2GHZ_XATTEN2_DB,4,2 ; @AR_PHY_GAIN_2GHZ_XATTEN2_DB
	.comm	_AR_PHY_GAIN_2GHZ_BSW_MARGIN,4,2 ; @AR_PHY_GAIN_2GHZ_BSW_MARGIN
	.comm	_AR_PHY_GAIN_2GHZ_BSW_ATTEN,4,2 ; @AR_PHY_GAIN_2GHZ_BSW_ATTEN
	.comm	_AR_PHY_RXGAIN,8,3              ; @AR_PHY_RXGAIN
	.comm	_AR9280_PHY_RXGAIN_TXRX_ATTEN,4,2 ; @AR9280_PHY_RXGAIN_TXRX_ATTEN
	.comm	_AR9280_PHY_RXGAIN_TXRX_MARGIN,4,2 ; @AR9280_PHY_RXGAIN_TXRX_MARGIN
	.comm	_AR_PHY_RXGAIN_TXRX_ATTEN,4,2   ; @AR_PHY_RXGAIN_TXRX_ATTEN
	.comm	_AR_PHY_GAIN_2GHZ_RXTX_MARGIN,4,2 ; @AR_PHY_GAIN_2GHZ_RXTX_MARGIN
	.no_dead_strip	_ath9k_hw_def_set_gain
.subsections_via_symbols
