	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_irq_handler           ## -- Begin function iwl_pcie_irq_handler
	.p2align	4, 0x90
_iwl_pcie_irq_handler:                  ## @iwl_pcie_irq_handler
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r13
	movq	%rsi, %rdi
	callq	_IWL_TRANS_GET_PCIE_TRANS
	movq	%rax, %rbx
	movq	%r13, %rdi
	callq	_lock_map_acquire
	leaq	8(%rbx), %r15
	movq	%r15, %rdi
	callq	_spin_lock
	movl	20(%rbx), %edi
	callq	_likely
	movq	%r13, %rdi
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	callq	_iwl_pcie_int_cause_ict
	jmp	LBB0_3
LBB0_2:
	callq	_iwl_pcie_int_cause_non_ict
LBB0_3:
	movl	%eax, %r12d
	movq	_IWL_DL_ISR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_iwl_have_debug_level
	testq	%rax, %rax
	je	LBB0_6
## %bb.4:
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movl	(%rbx), %r15d
	movq	_CSR_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_iwl_read32
	movl	%eax, %r14d
	movq	_CSR_FH_INT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_iwl_read32
	leaq	L_.str(%rip), %rsi
	movq	%r13, %rdi
	movl	%r12d, %edx
	movl	%r15d, %ecx
	movq	-48(%rbp), %r15                 ## 8-byte Reload
	movl	%r14d, %r8d
	movl	%eax, %r9d
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movl	(%rbx), %edx
	notl	%edx
	andl	%r12d, %edx
	je	LBB0_6
## %bb.5:
	leaq	L_.str.1(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
LBB0_6:
	xorl	%edi, %edi
	andl	(%rbx), %r12d
	sete	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_10
## %bb.7:
	leaq	L_.str.2(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	_STATUS_INT_ENABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	4(%r13), %rsi
	callq	_test_bit
	testq	%rax, %rax
	je	LBB0_9
## %bb.8:
	movq	%r13, %rdi
	callq	__iwl_enable_interrupts
LBB0_9:
	movq	%r15, %rdi
	callq	_spin_unlock
	movq	_IRQ_NONE@GOTPCREL(%rip), %rbx
	jmp	LBB0_57
LBB0_10:
	cmpl	$-1, %r12d
	sete	%al
	movl	%r12d, %ecx
	andl	$-16, %ecx
	cmpl	$-1515870816, %ecx              ## imm = 0xA5A5A5A0
	sete	%cl
	orb	%al, %cl
	movzbl	%cl, %edi
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_12
## %bb.11:
	leaq	L_.str.3(%rip), %rsi
	movq	%r13, %rdi
	movl	%r12d, %edx
	callq	_IWL_WARN
	movq	%r15, %rdi
LBB0_55:
	callq	_spin_unlock
	jmp	LBB0_56
LBB0_12:
	movq	_CSR_INT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%rbx), %edx
	notl	%edx
	orl	%r12d, %edx
	movq	%r13, %rdi
	callq	_iwl_write32
	movq	_IWL_DL_ISR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_iwl_have_debug_level
	testq	%rax, %rax
	je	LBB0_14
## %bb.13:
	movq	_CSR_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_iwl_read32
	leaq	L_.str.4(%rip), %rsi
	movq	%r13, %rdi
	movl	%r12d, %edx
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
LBB0_14:
	movq	%r15, %rdi
	callq	_spin_unlock
	movq	_CSR_INT_BIT_HW_ERR@GOTPCREL(%rip), %rax
	testl	%r12d, (%rax)
	je	LBB0_16
## %bb.15:
	leaq	L_.str.5(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_ERR
	movq	%r13, %rdi
	callq	_iwl_disable_interrupts
	incl	56(%rbx)
	movq	%r13, %rdi
	callq	_iwl_pcie_irq_handle_error
LBB0_56:
	movq	_IRQ_HANDLED@GOTPCREL(%rip), %rbx
LBB0_57:
	movq	%r13, %rdi
	callq	_lock_map_release
	movl	(%rbx), %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_16:
	movq	%r13, -64(%rbp)                 ## 8-byte Spill
	movq	%r15, -48(%rbp)                 ## 8-byte Spill
	movl	%r12d, %eax
	movq	_CSR_INT_BIT_SCD@GOTPCREL(%rip), %r12
	movl	%eax, %r13d
	testl	%eax, (%r12)
	je	LBB0_18
## %bb.17:
	leaq	L_.str.6(%rip), %rsi
	movq	-64(%rbp), %rdi                 ## 8-byte Reload
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	incl	52(%rbx)
LBB0_18:
	movq	_CSR_INT_BIT_ALIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%r13d, %eax
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	je	LBB0_19
## %bb.20:
	leaq	L_.str.7(%rip), %rsi
	movq	-64(%rbp), %r15                 ## 8-byte Reload
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	incl	48(%rbx)
	movq	8(%r15), %rax
	cmpq	$0, (%rax)
	je	LBB0_22
## %bb.21:
	movl	16(%rbx), %esi
	movq	%r15, %rdi
	callq	_iwl_pcie_rxmq_restock
LBB0_22:
	movq	_CSR_INT_BIT_ALIVE@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, %r14d
	jmp	LBB0_23
LBB0_19:
	xorl	%r14d, %r14d
LBB0_23:
	orl	(%r12), %eax
	notl	%eax
	movl	%r13d, %r12d
	andl	%eax, %r12d
	movq	_CSR_INT_BIT_RF_KILL@GOTPCREL(%rip), %rbx
	testl	%r12d, (%rbx)
	je	LBB0_24
## %bb.25:
	movq	-64(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	callq	_iwl_pcie_handle_rfkill_irq
	orl	(%rbx), %r14d
	jmp	LBB0_26
LBB0_24:
	movq	-64(%rbp), %r13                 ## 8-byte Reload
LBB0_26:
	movq	_CSR_INT_BIT_CT_KILL@GOTPCREL(%rip), %rbx
	testl	%r12d, (%rbx)
	je	LBB0_28
## %bb.27:
	leaq	L_.str.8(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_ERR
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	incl	44(%rax)
	orl	(%rbx), %r14d
LBB0_28:
	movq	_CSR_INT_BIT_SW_ERR@GOTPCREL(%rip), %rbx
	testl	%r12d, (%rbx)
	je	LBB0_30
## %bb.29:
	leaq	L_.str.9(%rip), %rsi
	movq	%r13, %rdi
	movl	%r12d, %edx
	xorl	%eax, %eax
	callq	_IWL_ERR
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	incl	40(%rax)
	movq	%r13, %rdi
	callq	_iwl_pcie_irq_handle_error
	orl	(%rbx), %r14d
LBB0_30:
	movq	_CSR_INT_BIT_WAKEUP@GOTPCREL(%rip), %rbx
	testl	%r12d, (%rbx)
	je	LBB0_32
## %bb.31:
	leaq	L_.str.10(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	%r13, %rdi
	callq	_iwl_pcie_rxq_check_wrptr
	movq	%r13, %rdi
	callq	_iwl_pcie_txq_check_wrptrs
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	incl	36(%rax)
	orl	(%rbx), %r14d
LBB0_32:
	movq	_CSR_INT_BIT_FH_RX@GOTPCREL(%rip), %r15
	movq	_CSR_INT_BIT_SW_RX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%r15), %eax
	movq	_CSR_INT_BIT_RX_PERIODIC@GOTPCREL(%rip), %rbx
	orl	(%rbx), %eax
	testl	%r12d, %eax
	je	LBB0_40
## %bb.33:
	leaq	L_.str.11(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	_CSR_INT_BIT_SW_RX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%r15), %eax
	testl	%r12d, %eax
	je	LBB0_35
## %bb.34:
	orl	%eax, %r14d
	movq	_CSR_FH_INT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_FH_INT_RX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_iwl_write32
LBB0_35:
	movl	(%rbx), %edx
	testl	%r12d, %edx
	je	LBB0_37
## %bb.36:
	orl	%edx, %r14d
	movq	_CSR_INT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_iwl_write32
LBB0_37:
	movq	_CSR_INT_PERIODIC_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_CSR_INT_PERIODIC_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_iwl_write8
	movq	_CSR_INT_BIT_SW_RX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CSR_INT_BIT_FH_RX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	testl	%r12d, %eax
	je	LBB0_39
## %bb.38:
	movl	(%rbx), %esi
	movq	_CSR_INT_PERIODIC_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_iwl_write8
LBB0_39:
	movq	-56(%rbp), %rax                 ## 8-byte Reload
	incl	32(%rax)
	xorl	%eax, %eax
	callq	_local_bh_disable
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_iwl_pcie_rx_handle
	xorl	%eax, %eax
	callq	_local_bh_enable
LBB0_40:
	movq	_CSR_INT_BIT_FH_TX@GOTPCREL(%rip), %rbx
	testl	%r12d, (%rbx)
	je	LBB0_42
## %bb.41:
	movq	_CSR_FH_INT_STATUS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_FH_INT_TX_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_iwl_write32
	leaq	L_.str.12(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	incl	28(%rdi)
	orl	(%rbx), %r14d
	movl	$1, 4(%rdi)
	addq	$12, %rdi
	callq	_wake_up
LBB0_42:
	movl	%r14d, %edx
	notl	%edx
	andl	%r12d, %edx
	movq	-56(%rbp), %r15                 ## 8-byte Reload
	je	LBB0_44
## %bb.43:
	leaq	L_.str.13(%rip), %rsi
	movq	%r13, %rdi
	xorl	%eax, %eax
	callq	_IWL_ERR
	incl	24(%r15)
LBB0_44:
	movl	(%r15), %eax
	notl	%eax
	andl	%eax, %r12d
	je	LBB0_46
## %bb.45:
	leaq	L_.str.14(%rip), %rsi
	movq	%r13, %rdi
	movl	%r12d, %edx
	callq	_IWL_WARN
LBB0_46:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_spin_lock
	movq	_STATUS_INT_ENABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	leaq	4(%r13), %rsi
	callq	_test_bit
	testq	%rax, %rax
	je	LBB0_48
## %bb.47:
	movq	%r13, %rdi
	callq	__iwl_enable_interrupts
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_54
LBB0_48:
	testl	%r14d, (%rbx)
	je	LBB0_50
## %bb.49:
	movq	%r13, %rdi
	callq	_iwl_enable_fw_load_int
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_54
LBB0_50:
	movq	_CSR_INT_BIT_RF_KILL@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_52
## %bb.51:
	movq	%r13, %rdi
	callq	_iwl_enable_rfkill_int
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jmp	LBB0_54
LBB0_52:
	movq	_CSR_INT_BIT_FH_RX@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_CSR_INT_BIT_ALIVE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	testl	%r14d, %eax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_54
## %bb.53:
	movq	%r13, %rdi
	callq	_iwl_enable_fw_load_int_ctx_info
LBB0_54:
	movq	%rbx, %rdi
	jmp	LBB0_55
	.cfi_endproc
                                        ## -- End function
	.comm	_IWL_DL_ISR,4,2                 ## @IWL_DL_ISR
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n"

	.comm	_CSR_INT_MASK,4,2               ## @CSR_INT_MASK
	.comm	_CSR_FH_INT_STATUS,4,2          ## @CSR_FH_INT_STATUS
L_.str.1:                               ## @.str.1
	.asciz	"We got a masked interrupt (0x%08x)\n"

L_.str.2:                               ## @.str.2
	.asciz	"Ignore interrupt, inta == 0\n"

	.comm	_STATUS_INT_ENABLED,4,2         ## @STATUS_INT_ENABLED
	.comm	_IRQ_NONE,4,2                   ## @IRQ_NONE
L_.str.3:                               ## @.str.3
	.asciz	"HARDWARE GONE?? INTA == 0x%08x\n"

	.comm	_CSR_INT,4,2                    ## @CSR_INT
L_.str.4:                               ## @.str.4
	.asciz	"inta 0x%08x, enabled 0x%08x\n"

	.comm	_CSR_INT_BIT_HW_ERR,4,2         ## @CSR_INT_BIT_HW_ERR
L_.str.5:                               ## @.str.5
	.asciz	"Hardware error detected.  Restarting.\n"

	.comm	_CSR_INT_BIT_SCD,4,2            ## @CSR_INT_BIT_SCD
L_.str.6:                               ## @.str.6
	.asciz	"Scheduler finished to transmit the frame/frames.\n"

	.comm	_CSR_INT_BIT_ALIVE,4,2          ## @CSR_INT_BIT_ALIVE
L_.str.7:                               ## @.str.7
	.asciz	"Alive interrupt\n"

	.comm	_CSR_INT_BIT_RF_KILL,4,2        ## @CSR_INT_BIT_RF_KILL
	.comm	_CSR_INT_BIT_CT_KILL,4,2        ## @CSR_INT_BIT_CT_KILL
L_.str.8:                               ## @.str.8
	.asciz	"Microcode CT kill error detected.\n"

	.comm	_CSR_INT_BIT_SW_ERR,4,2         ## @CSR_INT_BIT_SW_ERR
L_.str.9:                               ## @.str.9
	.asciz	"Microcode SW error detected.  Restarting 0x%X.\n"

	.comm	_CSR_INT_BIT_WAKEUP,4,2         ## @CSR_INT_BIT_WAKEUP
L_.str.10:                              ## @.str.10
	.asciz	"Wakeup interrupt\n"

	.comm	_CSR_INT_BIT_FH_RX,4,2          ## @CSR_INT_BIT_FH_RX
	.comm	_CSR_INT_BIT_SW_RX,4,2          ## @CSR_INT_BIT_SW_RX
	.comm	_CSR_INT_BIT_RX_PERIODIC,4,2    ## @CSR_INT_BIT_RX_PERIODIC
L_.str.11:                              ## @.str.11
	.asciz	"Rx interrupt\n"

	.comm	_CSR_FH_INT_RX_MASK,4,2         ## @CSR_FH_INT_RX_MASK
	.comm	_CSR_INT_PERIODIC_REG,4,2       ## @CSR_INT_PERIODIC_REG
	.comm	_CSR_INT_PERIODIC_DIS,4,2       ## @CSR_INT_PERIODIC_DIS
	.comm	_CSR_INT_PERIODIC_ENA,4,2       ## @CSR_INT_PERIODIC_ENA
	.comm	_CSR_INT_BIT_FH_TX,4,2          ## @CSR_INT_BIT_FH_TX
	.comm	_CSR_FH_INT_TX_MASK,4,2         ## @CSR_FH_INT_TX_MASK
L_.str.12:                              ## @.str.12
	.asciz	"uCode load interrupt\n"

L_.str.13:                              ## @.str.13
	.asciz	"Unhandled INTA bits 0x%08x\n"

L_.str.14:                              ## @.str.14
	.asciz	"Disabled INTA bits 0x%08x were pending\n"

	.comm	_IRQ_HANDLED,4,2                ## @IRQ_HANDLED
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_irq_handler           ; -- Begin function iwl_pcie_irq_handler
	.p2align	2
_iwl_pcie_irq_handler:                  ; @iwl_pcie_irq_handler
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #128
	.cfi_def_cfa_offset 128
	stp	x28, x27, [sp, #32]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #48]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #64]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #80]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #96]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #112]            ; 16-byte Folded Spill
	add	x29, sp, #112
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x19, x1
	mov	x0, x1
	bl	_IWL_TRANS_GET_PCIE_TRANS
	mov	x21, x0
	mov	x0, x19
	bl	_lock_map_acquire
	add	x20, x21, #8
	mov	x0, x20
	bl	_spin_lock
	ldr	w0, [x21, #20]
	bl	_likely
	cbz	x0, LBB0_2
; %bb.1:
	mov	x0, x19
	bl	_iwl_pcie_int_cause_ict
	b	LBB0_3
LBB0_2:
	mov	x0, x19
	bl	_iwl_pcie_int_cause_non_ict
LBB0_3:
	mov	x22, x0
Lloh0:
	adrp	x24, _IWL_DL_ISR@GOTPAGE
Lloh1:
	ldr	x24, [x24, _IWL_DL_ISR@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_iwl_have_debug_level
	cbz	x0, LBB0_6
; %bb.4:
Lloh2:
	adrp	x8, _CSR_INT_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _CSR_INT_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	ldr	w25, [x21]
	mov	x0, x19
	bl	_iwl_read32
	mov	x23, x0
Lloh5:
	adrp	x8, _CSR_FH_INT_STATUS@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CSR_FH_INT_STATUS@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_iwl_read32
                                        ; kill: def $w0 killed $w0 def $x0
	stp	x23, x0, [sp, #16]
	stp	x22, x25, [sp]
Lloh8:
	adrp	x1, l_.str@PAGE
Lloh9:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21]
	bics	w8, w22, w8
	b.eq	LBB0_6
; %bb.5:
	str	x8, [sp]
Lloh10:
	adrp	x1, l_.str.1@PAGE
Lloh11:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
LBB0_6:
	ldr	w8, [x21]
	ands	w22, w8, w22
	cset	w0, eq
	bl	_unlikely
	cbz	x0, LBB0_10
; %bb.7:
Lloh12:
	adrp	x1, l_.str.2@PAGE
Lloh13:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
Lloh14:
	adrp	x8, _STATUS_INT_ENABLED@GOTPAGE
Lloh15:
	ldr	x8, [x8, _STATUS_INT_ENABLED@GOTPAGEOFF]
Lloh16:
	ldr	w0, [x8]
	add	x1, x19, #4
	bl	_test_bit
	cbz	x0, LBB0_9
; %bb.8:
	mov	x0, x19
	bl	__iwl_enable_interrupts
LBB0_9:
	mov	x0, x20
	bl	_spin_unlock
Lloh17:
	adrp	x20, _IRQ_NONE@GOTPAGE
Lloh18:
	ldr	x20, [x20, _IRQ_NONE@GOTPAGEOFF]
	b	LBB0_18
LBB0_10:
	cmn	w22, #1
	lsr	w8, w22, #4
	mov	w9, #23130
	movk	w9, #2650, lsl #16
	ccmp	w9, w8, #4, ne
	cset	w0, eq
	bl	_unlikely
	cbz	x0, LBB0_13
; %bb.11:
Lloh19:
	adrp	x1, l_.str.3@PAGE
Lloh20:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	mov	x2, x22
	bl	_IWL_WARN
LBB0_12:
	mov	x0, x20
	bl	_spin_unlock
	b	LBB0_17
LBB0_13:
Lloh21:
	adrp	x26, _CSR_INT@GOTPAGE
Lloh22:
	ldr	x26, [x26, _CSR_INT@GOTPAGEOFF]
	ldr	w1, [x26]
	ldr	w8, [x21]
	orn	w2, w22, w8
	mov	x0, x19
	bl	_iwl_write32
	ldr	w0, [x24]
	bl	_iwl_have_debug_level
	cbz	x0, LBB0_15
; %bb.14:
Lloh23:
	adrp	x8, _CSR_INT_MASK@GOTPAGE
Lloh24:
	ldr	x8, [x8, _CSR_INT_MASK@GOTPAGEOFF]
Lloh25:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_iwl_read32
                                        ; kill: def $w0 killed $w0 def $x0
	stp	x22, x0, [sp]
Lloh26:
	adrp	x1, l_.str.4@PAGE
Lloh27:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
LBB0_15:
	mov	x0, x20
	bl	_spin_unlock
Lloh28:
	adrp	x8, _CSR_INT_BIT_HW_ERR@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CSR_INT_BIT_HW_ERR@GOTPAGEOFF]
Lloh30:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_19
; %bb.16:
Lloh31:
	adrp	x1, l_.str.5@PAGE
Lloh32:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	mov	x0, x19
	bl	_iwl_disable_interrupts
	ldr	w8, [x21, #56]
	add	w8, w8, #1
	str	w8, [x21, #56]
	mov	x0, x19
	bl	_iwl_pcie_irq_handle_error
LBB0_17:
Lloh33:
	adrp	x20, _IRQ_HANDLED@GOTPAGE
Lloh34:
	ldr	x20, [x20, _IRQ_HANDLED@GOTPAGEOFF]
LBB0_18:
	mov	x0, x19
	bl	_lock_map_release
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #112]            ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #96]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #80]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #64]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #48]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #128
	ret
LBB0_19:
Lloh35:
	adrp	x25, _CSR_INT_BIT_SCD@GOTPAGE
Lloh36:
	ldr	x25, [x25, _CSR_INT_BIT_SCD@GOTPAGEOFF]
	ldr	w8, [x25]
	tst	w8, w22
	b.eq	LBB0_21
; %bb.20:
Lloh37:
	adrp	x1, l_.str.6@PAGE
Lloh38:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21, #52]
	add	w8, w8, #1
	str	w8, [x21, #52]
LBB0_21:
Lloh39:
	adrp	x23, _CSR_INT_BIT_ALIVE@GOTPAGE
Lloh40:
	ldr	x23, [x23, _CSR_INT_BIT_ALIVE@GOTPAGEOFF]
	ldr	w8, [x23]
	tst	w8, w22
	b.eq	LBB0_25
; %bb.22:
Lloh41:
	adrp	x1, l_.str.7@PAGE
Lloh42:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21, #48]
	add	w8, w8, #1
	str	w8, [x21, #48]
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_24
; %bb.23:
	ldr	w1, [x21, #16]
	mov	x0, x19
	bl	_iwl_pcie_rxmq_restock
LBB0_24:
	ldr	w8, [x23]
	mov	x24, x8
	b	LBB0_26
LBB0_25:
	mov	w24, #0
LBB0_26:
	ldr	w9, [x25]
	orr	w8, w8, w9
	bic	w25, w22, w8
Lloh43:
	adrp	x22, _CSR_INT_BIT_RF_KILL@GOTPAGE
Lloh44:
	ldr	x22, [x22, _CSR_INT_BIT_RF_KILL@GOTPAGEOFF]
	ldr	w8, [x22]
	tst	w25, w8
	b.eq	LBB0_28
; %bb.27:
	mov	x0, x19
	bl	_iwl_pcie_handle_rfkill_irq
	ldr	w8, [x22]
	orr	w24, w8, w24
LBB0_28:
Lloh45:
	adrp	x23, _CSR_INT_BIT_CT_KILL@GOTPAGE
Lloh46:
	ldr	x23, [x23, _CSR_INT_BIT_CT_KILL@GOTPAGEOFF]
	ldr	w8, [x23]
	tst	w8, w25
	b.eq	LBB0_30
; %bb.29:
Lloh47:
	adrp	x1, l_.str.8@PAGE
Lloh48:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	ldr	w8, [x21, #44]
	add	w8, w8, #1
	str	w8, [x21, #44]
	ldr	w8, [x23]
	orr	w24, w8, w24
LBB0_30:
Lloh49:
	adrp	x23, _CSR_INT_BIT_SW_ERR@GOTPAGE
Lloh50:
	ldr	x23, [x23, _CSR_INT_BIT_SW_ERR@GOTPAGEOFF]
	ldr	w8, [x23]
	tst	w8, w25
	b.eq	LBB0_32
; %bb.31:
	str	x25, [sp]
Lloh51:
	adrp	x1, l_.str.9@PAGE
Lloh52:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	ldr	w8, [x21, #40]
	add	w8, w8, #1
	str	w8, [x21, #40]
	mov	x0, x19
	bl	_iwl_pcie_irq_handle_error
	ldr	w8, [x23]
	orr	w24, w8, w24
LBB0_32:
Lloh53:
	adrp	x23, _CSR_INT_BIT_WAKEUP@GOTPAGE
Lloh54:
	ldr	x23, [x23, _CSR_INT_BIT_WAKEUP@GOTPAGEOFF]
	ldr	w8, [x23]
	tst	w8, w25
	b.eq	LBB0_34
; %bb.33:
Lloh55:
	adrp	x1, l_.str.10@PAGE
Lloh56:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	mov	x0, x19
	bl	_iwl_pcie_rxq_check_wrptr
	mov	x0, x19
	bl	_iwl_pcie_txq_check_wrptrs
	ldr	w8, [x21, #36]
	add	w8, w8, #1
	str	w8, [x21, #36]
	ldr	w8, [x23]
	orr	w24, w8, w24
LBB0_34:
Lloh57:
	adrp	x27, _CSR_INT_BIT_FH_RX@GOTPAGE
Lloh58:
	ldr	x27, [x27, _CSR_INT_BIT_FH_RX@GOTPAGEOFF]
	ldr	w8, [x27]
Lloh59:
	adrp	x28, _CSR_INT_BIT_SW_RX@GOTPAGE
Lloh60:
	ldr	x28, [x28, _CSR_INT_BIT_SW_RX@GOTPAGEOFF]
	ldr	w9, [x28]
	orr	w8, w9, w8
Lloh61:
	adrp	x23, _CSR_INT_BIT_RX_PERIODIC@GOTPAGE
Lloh62:
	ldr	x23, [x23, _CSR_INT_BIT_RX_PERIODIC@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w8, w8, w9
	tst	w8, w25
	b.eq	LBB0_42
; %bb.35:
Lloh63:
	adrp	x1, l_.str.11@PAGE
Lloh64:
	add	x1, x1, l_.str.11@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x27]
	ldr	w9, [x28]
	orr	w8, w9, w8
	tst	w8, w25
	b.eq	LBB0_37
; %bb.36:
	orr	w24, w8, w24
Lloh65:
	adrp	x8, _CSR_FH_INT_STATUS@GOTPAGE
Lloh66:
	ldr	x8, [x8, _CSR_FH_INT_STATUS@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
Lloh68:
	adrp	x8, _CSR_FH_INT_RX_MASK@GOTPAGE
Lloh69:
	ldr	x8, [x8, _CSR_FH_INT_RX_MASK@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_write32
LBB0_37:
	ldr	w2, [x23]
	tst	w2, w25
	b.eq	LBB0_39
; %bb.38:
	orr	w24, w2, w24
	ldr	w1, [x26]
	mov	x0, x19
	bl	_iwl_write32
LBB0_39:
Lloh71:
	adrp	x23, _CSR_INT_PERIODIC_REG@GOTPAGE
Lloh72:
	ldr	x23, [x23, _CSR_INT_PERIODIC_REG@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh73:
	adrp	x8, _CSR_INT_PERIODIC_DIS@GOTPAGE
Lloh74:
	ldr	x8, [x8, _CSR_INT_PERIODIC_DIS@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_write8
	ldr	w8, [x27]
	ldr	w9, [x28]
	orr	w8, w9, w8
	tst	w8, w25
	b.eq	LBB0_41
; %bb.40:
	ldr	w1, [x23]
Lloh76:
	adrp	x8, _CSR_INT_PERIODIC_ENA@GOTPAGE
Lloh77:
	ldr	x8, [x8, _CSR_INT_PERIODIC_ENA@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_write8
LBB0_41:
	ldr	w8, [x21, #32]
	add	w8, w8, #1
	str	w8, [x21, #32]
	bl	_local_bh_disable
	mov	x0, x19
	mov	w1, #0
	bl	_iwl_pcie_rx_handle
	bl	_local_bh_enable
LBB0_42:
Lloh79:
	adrp	x26, _CSR_INT_BIT_FH_TX@GOTPAGE
Lloh80:
	ldr	x26, [x26, _CSR_INT_BIT_FH_TX@GOTPAGEOFF]
	ldr	w8, [x26]
	tst	w8, w25
	b.eq	LBB0_44
; %bb.43:
Lloh81:
	adrp	x8, _CSR_FH_INT_STATUS@GOTPAGE
Lloh82:
	ldr	x8, [x8, _CSR_FH_INT_STATUS@GOTPAGEOFF]
Lloh83:
	ldr	w1, [x8]
Lloh84:
	adrp	x8, _CSR_FH_INT_TX_MASK@GOTPAGE
Lloh85:
	ldr	x8, [x8, _CSR_FH_INT_TX_MASK@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_write32
Lloh87:
	adrp	x1, l_.str.12@PAGE
Lloh88:
	add	x1, x1, l_.str.12@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21, #28]
	add	w8, w8, #1
	str	w8, [x21, #28]
	ldr	w8, [x26]
	orr	w24, w8, w24
	mov	w8, #1
	str	w8, [x21, #4]
	add	x0, x21, #12
	bl	_wake_up
LBB0_44:
	bics	w8, w25, w24
	b.eq	LBB0_46
; %bb.45:
	str	x8, [sp]
Lloh89:
	adrp	x1, l_.str.13@PAGE
Lloh90:
	add	x1, x1, l_.str.13@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	ldr	w8, [x21, #24]
	add	w8, w8, #1
	str	w8, [x21, #24]
LBB0_46:
	ldr	w8, [x21]
	bics	w2, w25, w8
	b.eq	LBB0_48
; %bb.47:
Lloh91:
	adrp	x1, l_.str.14@PAGE
Lloh92:
	add	x1, x1, l_.str.14@PAGEOFF
	mov	x0, x19
	bl	_IWL_WARN
LBB0_48:
	mov	x0, x20
	bl	_spin_lock
Lloh93:
	adrp	x8, _STATUS_INT_ENABLED@GOTPAGE
Lloh94:
	ldr	x8, [x8, _STATUS_INT_ENABLED@GOTPAGEOFF]
Lloh95:
	ldr	w0, [x8]
	add	x1, x19, #4
	bl	_test_bit
	cbz	x0, LBB0_50
; %bb.49:
	mov	x0, x19
	bl	__iwl_enable_interrupts
	b	LBB0_12
LBB0_50:
	ldr	w8, [x26]
	tst	w8, w24
	b.eq	LBB0_52
; %bb.51:
	mov	x0, x19
	bl	_iwl_enable_fw_load_int
	b	LBB0_12
LBB0_52:
	ldr	w8, [x22]
	tst	w8, w24
	b.eq	LBB0_54
; %bb.53:
	mov	x0, x19
	bl	_iwl_enable_rfkill_int
	b	LBB0_12
LBB0_54:
Lloh96:
	adrp	x8, _CSR_INT_BIT_ALIVE@GOTPAGE
Lloh97:
	ldr	x8, [x8, _CSR_INT_BIT_ALIVE@GOTPAGEOFF]
Lloh98:
	ldr	w8, [x8]
	ldr	w9, [x27]
	orr	w8, w9, w8
	tst	w8, w24
	b.eq	LBB0_12
; %bb.55:
	mov	x0, x19
	bl	_iwl_enable_fw_load_int_ctx_info
	b	LBB0_12
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh21, Lloh22
	.loh AdrpAdd	Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpAdd	Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpAdd	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpAdd	Lloh51, Lloh52
	.loh AdrpLdrGot	Lloh53, Lloh54
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh59, Lloh60
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpAdd	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGot	Lloh79, Lloh80
	.loh AdrpAdd	Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpAdd	Lloh89, Lloh90
	.loh AdrpAdd	Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.cfi_endproc
                                        ; -- End function
	.comm	_IWL_DL_ISR,4,2                 ; @IWL_DL_ISR
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n"

	.comm	_CSR_INT_MASK,4,2               ; @CSR_INT_MASK
	.comm	_CSR_FH_INT_STATUS,4,2          ; @CSR_FH_INT_STATUS
l_.str.1:                               ; @.str.1
	.asciz	"We got a masked interrupt (0x%08x)\n"

l_.str.2:                               ; @.str.2
	.asciz	"Ignore interrupt, inta == 0\n"

	.comm	_STATUS_INT_ENABLED,4,2         ; @STATUS_INT_ENABLED
	.comm	_IRQ_NONE,4,2                   ; @IRQ_NONE
l_.str.3:                               ; @.str.3
	.asciz	"HARDWARE GONE?? INTA == 0x%08x\n"

	.comm	_CSR_INT,4,2                    ; @CSR_INT
l_.str.4:                               ; @.str.4
	.asciz	"inta 0x%08x, enabled 0x%08x\n"

	.comm	_CSR_INT_BIT_HW_ERR,4,2         ; @CSR_INT_BIT_HW_ERR
l_.str.5:                               ; @.str.5
	.asciz	"Hardware error detected.  Restarting.\n"

	.comm	_CSR_INT_BIT_SCD,4,2            ; @CSR_INT_BIT_SCD
l_.str.6:                               ; @.str.6
	.asciz	"Scheduler finished to transmit the frame/frames.\n"

	.comm	_CSR_INT_BIT_ALIVE,4,2          ; @CSR_INT_BIT_ALIVE
l_.str.7:                               ; @.str.7
	.asciz	"Alive interrupt\n"

	.comm	_CSR_INT_BIT_RF_KILL,4,2        ; @CSR_INT_BIT_RF_KILL
	.comm	_CSR_INT_BIT_CT_KILL,4,2        ; @CSR_INT_BIT_CT_KILL
l_.str.8:                               ; @.str.8
	.asciz	"Microcode CT kill error detected.\n"

	.comm	_CSR_INT_BIT_SW_ERR,4,2         ; @CSR_INT_BIT_SW_ERR
l_.str.9:                               ; @.str.9
	.asciz	"Microcode SW error detected.  Restarting 0x%X.\n"

	.comm	_CSR_INT_BIT_WAKEUP,4,2         ; @CSR_INT_BIT_WAKEUP
l_.str.10:                              ; @.str.10
	.asciz	"Wakeup interrupt\n"

	.comm	_CSR_INT_BIT_FH_RX,4,2          ; @CSR_INT_BIT_FH_RX
	.comm	_CSR_INT_BIT_SW_RX,4,2          ; @CSR_INT_BIT_SW_RX
	.comm	_CSR_INT_BIT_RX_PERIODIC,4,2    ; @CSR_INT_BIT_RX_PERIODIC
l_.str.11:                              ; @.str.11
	.asciz	"Rx interrupt\n"

	.comm	_CSR_FH_INT_RX_MASK,4,2         ; @CSR_FH_INT_RX_MASK
	.comm	_CSR_INT_PERIODIC_REG,4,2       ; @CSR_INT_PERIODIC_REG
	.comm	_CSR_INT_PERIODIC_DIS,4,2       ; @CSR_INT_PERIODIC_DIS
	.comm	_CSR_INT_PERIODIC_ENA,4,2       ; @CSR_INT_PERIODIC_ENA
	.comm	_CSR_INT_BIT_FH_TX,4,2          ; @CSR_INT_BIT_FH_TX
	.comm	_CSR_FH_INT_TX_MASK,4,2         ; @CSR_FH_INT_TX_MASK
l_.str.12:                              ; @.str.12
	.asciz	"uCode load interrupt\n"

l_.str.13:                              ; @.str.13
	.asciz	"Unhandled INTA bits 0x%08x\n"

l_.str.14:                              ; @.str.14
	.asciz	"Disabled INTA bits 0x%08x were pending\n"

	.comm	_IRQ_HANDLED,4,2                ; @IRQ_HANDLED
.subsections_via_symbols
