	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rt61pci_init_queues
_rt61pci_init_queues:                   ## @rt61pci_init_queues
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_TX_RING_CSR0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_TX_RING_CSR0_AC0_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rax
	movl	(%rax), %edx
	leaq	-36(%rbp), %r14
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movq	_TX_RING_CSR0_AC1_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rax
	movl	16(%rax), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movq	_TX_RING_CSR0_AC2_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rax
	movl	32(%rax), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movq	_TX_RING_CSR0_AC3_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rax
	movl	48(%rax), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	_TX_RING_CSR1@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_TX_RING_CSR1_TXD_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	8(%rbx), %rax
	movl	4(%rax), %eax
	leal	3(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$2, %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	8(%rbx), %rax
	movq	8(%rax), %rax
	movq	(%rax), %r15
	movq	_AC0_BASE_CSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_AC0_BASE_CSR_RING_REGISTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	8(%rbx), %rax
	movq	24(%rax), %rax
	movq	(%rax), %r15
	movq	_AC1_BASE_CSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_AC1_BASE_CSR_RING_REGISTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	8(%rbx), %rax
	movq	40(%rax), %rax
	movq	(%rax), %r15
	movq	_AC2_BASE_CSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_AC2_BASE_CSR_RING_REGISTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	8(%rbx), %rax
	movq	56(%rax), %rax
	movq	(%rax), %r15
	movq	_AC3_BASE_CSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_AC3_BASE_CSR_RING_REGISTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	_RX_RING_CSR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_RX_RING_CSR_RING_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%rbx), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movq	_RX_RING_CSR_RXD_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%rbx), %rax
	movl	4(%rax), %eax
	leal	3(%rax), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	sarl	$2, %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movq	_RX_RING_CSR_RXD_WRITEBACK_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$4, %edx
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	(%rbx), %rax
	movq	8(%rax), %rax
	movq	(%rax), %r15
	movq	_RX_BASE_CSR@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_RX_BASE_CSR_RING_REGISTER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_rt2x00_set_field32
	movl	(%r12), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	_TX_DMA_DST_CSR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_TX_DMA_DST_CSR_DEST_AC0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$2, %edx
	callq	_rt2x00_set_field32
	movq	_TX_DMA_DST_CSR_DEST_AC1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$2, %edx
	callq	_rt2x00_set_field32
	movq	_TX_DMA_DST_CSR_DEST_AC2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$2, %edx
	callq	_rt2x00_set_field32
	movq	_TX_DMA_DST_CSR_DEST_AC3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$2, %edx
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	_LOAD_TX_RING_CSR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_LOAD_TX_RING_CSR_LOAD_TXD_AC0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_LOAD_TX_RING_CSR_LOAD_TXD_AC1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_LOAD_TX_RING_CSR_LOAD_TXD_AC2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_LOAD_TX_RING_CSR_LOAD_TXD_AC3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	_RX_CNTL_CSR@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -36(%rbp)
	movq	_RX_CNTL_CSR_LOAD_RXD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r15), %esi
	movl	-36(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	xorl	%eax, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_TX_RING_CSR0,4,2               ## @TX_RING_CSR0
	.comm	_TX_RING_CSR0_AC0_RING_SIZE,4,2 ## @TX_RING_CSR0_AC0_RING_SIZE
	.comm	_TX_RING_CSR0_AC1_RING_SIZE,4,2 ## @TX_RING_CSR0_AC1_RING_SIZE
	.comm	_TX_RING_CSR0_AC2_RING_SIZE,4,2 ## @TX_RING_CSR0_AC2_RING_SIZE
	.comm	_TX_RING_CSR0_AC3_RING_SIZE,4,2 ## @TX_RING_CSR0_AC3_RING_SIZE
	.comm	_TX_RING_CSR1,4,2               ## @TX_RING_CSR1
	.comm	_TX_RING_CSR1_TXD_SIZE,4,2      ## @TX_RING_CSR1_TXD_SIZE
	.comm	_AC0_BASE_CSR,4,2               ## @AC0_BASE_CSR
	.comm	_AC0_BASE_CSR_RING_REGISTER,4,2 ## @AC0_BASE_CSR_RING_REGISTER
	.comm	_AC1_BASE_CSR,4,2               ## @AC1_BASE_CSR
	.comm	_AC1_BASE_CSR_RING_REGISTER,4,2 ## @AC1_BASE_CSR_RING_REGISTER
	.comm	_AC2_BASE_CSR,4,2               ## @AC2_BASE_CSR
	.comm	_AC2_BASE_CSR_RING_REGISTER,4,2 ## @AC2_BASE_CSR_RING_REGISTER
	.comm	_AC3_BASE_CSR,4,2               ## @AC3_BASE_CSR
	.comm	_AC3_BASE_CSR_RING_REGISTER,4,2 ## @AC3_BASE_CSR_RING_REGISTER
	.comm	_RX_RING_CSR,4,2                ## @RX_RING_CSR
	.comm	_RX_RING_CSR_RING_SIZE,4,2      ## @RX_RING_CSR_RING_SIZE
	.comm	_RX_RING_CSR_RXD_SIZE,4,2       ## @RX_RING_CSR_RXD_SIZE
	.comm	_RX_RING_CSR_RXD_WRITEBACK_SIZE,4,2 ## @RX_RING_CSR_RXD_WRITEBACK_SIZE
	.comm	_RX_BASE_CSR,4,2                ## @RX_BASE_CSR
	.comm	_RX_BASE_CSR_RING_REGISTER,4,2  ## @RX_BASE_CSR_RING_REGISTER
	.comm	_TX_DMA_DST_CSR,4,2             ## @TX_DMA_DST_CSR
	.comm	_TX_DMA_DST_CSR_DEST_AC0,4,2    ## @TX_DMA_DST_CSR_DEST_AC0
	.comm	_TX_DMA_DST_CSR_DEST_AC1,4,2    ## @TX_DMA_DST_CSR_DEST_AC1
	.comm	_TX_DMA_DST_CSR_DEST_AC2,4,2    ## @TX_DMA_DST_CSR_DEST_AC2
	.comm	_TX_DMA_DST_CSR_DEST_AC3,4,2    ## @TX_DMA_DST_CSR_DEST_AC3
	.comm	_LOAD_TX_RING_CSR,4,2           ## @LOAD_TX_RING_CSR
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC0,4,2 ## @LOAD_TX_RING_CSR_LOAD_TXD_AC0
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC1,4,2 ## @LOAD_TX_RING_CSR_LOAD_TXD_AC1
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC2,4,2 ## @LOAD_TX_RING_CSR_LOAD_TXD_AC2
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC3,4,2 ## @LOAD_TX_RING_CSR_LOAD_TXD_AC3
	.comm	_RX_CNTL_CSR,4,2                ## @RX_CNTL_CSR
	.comm	_RX_CNTL_CSR_LOAD_RXD,4,2       ## @RX_CNTL_CSR_LOAD_RXD
	.no_dead_strip	_rt61pci_init_queues
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rt61pci_init_queues
_rt61pci_init_queues:                   ; @rt61pci_init_queues
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x20, _TX_RING_CSR0@GOTPAGE
Lloh1:
	ldr	x20, [x20, _TX_RING_CSR0@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh2:
	adrp	x8, _TX_RING_CSR0_AC0_RING_SIZE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _TX_RING_CSR0_AC0_RING_SIZE@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w2, [x8]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
Lloh5:
	adrp	x8, _TX_RING_CSR0_AC1_RING_SIZE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _TX_RING_CSR0_AC1_RING_SIZE@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w2, [x8, #16]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
Lloh8:
	adrp	x8, _TX_RING_CSR0_AC2_RING_SIZE@GOTPAGE
Lloh9:
	ldr	x8, [x8, _TX_RING_CSR0_AC2_RING_SIZE@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w2, [x8, #32]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
Lloh11:
	adrp	x8, _TX_RING_CSR0_AC3_RING_SIZE@GOTPAGE
Lloh12:
	ldr	x8, [x8, _TX_RING_CSR0_AC3_RING_SIZE@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w2, [x8, #48]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh14:
	adrp	x20, _TX_RING_CSR1@GOTPAGE
Lloh15:
	ldr	x20, [x20, _TX_RING_CSR1@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh16:
	adrp	x8, _TX_RING_CSR1_TXD_SIZE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _TX_RING_CSR1_TXD_SIZE@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	ldr	x8, [x19, #8]
	ldr	w8, [x8, #4]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w2, w8, #2
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	ldr	x20, [x8]
Lloh19:
	adrp	x21, _AC0_BASE_CSR@GOTPAGE
Lloh20:
	ldr	x21, [x21, _AC0_BASE_CSR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh21:
	adrp	x8, _AC0_BASE_CSR_RING_REGISTER@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AC0_BASE_CSR_RING_REGISTER@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	ldr	w2, [x20]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x21]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #24]
	ldr	x20, [x8]
Lloh24:
	adrp	x21, _AC1_BASE_CSR@GOTPAGE
Lloh25:
	ldr	x21, [x21, _AC1_BASE_CSR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh26:
	adrp	x8, _AC1_BASE_CSR_RING_REGISTER@GOTPAGE
Lloh27:
	ldr	x8, [x8, _AC1_BASE_CSR_RING_REGISTER@GOTPAGEOFF]
Lloh28:
	ldr	w1, [x8]
	ldr	w2, [x20]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x21]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #40]
	ldr	x20, [x8]
Lloh29:
	adrp	x21, _AC2_BASE_CSR@GOTPAGE
Lloh30:
	ldr	x21, [x21, _AC2_BASE_CSR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh31:
	adrp	x8, _AC2_BASE_CSR_RING_REGISTER@GOTPAGE
Lloh32:
	ldr	x8, [x8, _AC2_BASE_CSR_RING_REGISTER@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	ldr	w2, [x20]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x21]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #56]
	ldr	x20, [x8]
Lloh34:
	adrp	x21, _AC3_BASE_CSR@GOTPAGE
Lloh35:
	ldr	x21, [x21, _AC3_BASE_CSR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh36:
	adrp	x8, _AC3_BASE_CSR_RING_REGISTER@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AC3_BASE_CSR_RING_REGISTER@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	ldr	w2, [x20]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x21]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh39:
	adrp	x20, _RX_RING_CSR@GOTPAGE
Lloh40:
	ldr	x20, [x20, _RX_RING_CSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh41:
	adrp	x8, _RX_RING_CSR_RING_SIZE@GOTPAGE
Lloh42:
	ldr	x8, [x8, _RX_RING_CSR_RING_SIZE@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	ldr	x8, [x19]
	ldr	w2, [x8]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
Lloh44:
	adrp	x8, _RX_RING_CSR_RXD_SIZE@GOTPAGE
Lloh45:
	ldr	x8, [x8, _RX_RING_CSR_RXD_SIZE@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
	ldr	x8, [x19]
	ldr	w8, [x8, #4]
	add	w9, w8, #3
	cmp	w8, #0
	csel	w8, w9, w8, lt
	asr	w2, w8, #2
	add	x0, sp, #12
	bl	_rt2x00_set_field32
Lloh47:
	adrp	x8, _RX_RING_CSR_RXD_WRITEBACK_SIZE@GOTPAGE
Lloh48:
	ldr	x8, [x8, _RX_RING_CSR_RXD_WRITEBACK_SIZE@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #4
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	ldr	x8, [x19]
	ldr	x8, [x8, #8]
	ldr	x20, [x8]
Lloh50:
	adrp	x21, _RX_BASE_CSR@GOTPAGE
Lloh51:
	ldr	x21, [x21, _RX_BASE_CSR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh52:
	adrp	x8, _RX_BASE_CSR_RING_REGISTER@GOTPAGE
Lloh53:
	ldr	x8, [x8, _RX_BASE_CSR_RING_REGISTER@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	ldr	w2, [x20]
	add	x0, sp, #12
	bl	_rt2x00_set_field32
	ldr	w1, [x21]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh55:
	adrp	x20, _TX_DMA_DST_CSR@GOTPAGE
Lloh56:
	ldr	x20, [x20, _TX_DMA_DST_CSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh57:
	adrp	x8, _TX_DMA_DST_CSR_DEST_AC0@GOTPAGE
Lloh58:
	ldr	x8, [x8, _TX_DMA_DST_CSR_DEST_AC0@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #2
	bl	_rt2x00_set_field32
Lloh60:
	adrp	x8, _TX_DMA_DST_CSR_DEST_AC1@GOTPAGE
Lloh61:
	ldr	x8, [x8, _TX_DMA_DST_CSR_DEST_AC1@GOTPAGEOFF]
Lloh62:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #2
	bl	_rt2x00_set_field32
Lloh63:
	adrp	x8, _TX_DMA_DST_CSR_DEST_AC2@GOTPAGE
Lloh64:
	ldr	x8, [x8, _TX_DMA_DST_CSR_DEST_AC2@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #2
	bl	_rt2x00_set_field32
Lloh66:
	adrp	x8, _TX_DMA_DST_CSR_DEST_AC3@GOTPAGE
Lloh67:
	ldr	x8, [x8, _TX_DMA_DST_CSR_DEST_AC3@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #2
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh69:
	adrp	x20, _LOAD_TX_RING_CSR@GOTPAGE
Lloh70:
	ldr	x20, [x20, _LOAD_TX_RING_CSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh71:
	adrp	x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC0@GOTPAGE
Lloh72:
	ldr	x8, [x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC0@GOTPAGEOFF]
Lloh73:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh74:
	adrp	x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC1@GOTPAGE
Lloh75:
	ldr	x8, [x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC1@GOTPAGEOFF]
Lloh76:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh77:
	adrp	x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC2@GOTPAGE
Lloh78:
	ldr	x8, [x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC2@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh80:
	adrp	x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC3@GOTPAGE
Lloh81:
	ldr	x8, [x8, _LOAD_TX_RING_CSR_LOAD_TXD_AC3@GOTPAGEOFF]
Lloh82:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh83:
	adrp	x20, _RX_CNTL_CSR@GOTPAGE
Lloh84:
	ldr	x20, [x20, _RX_CNTL_CSR@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh85:
	adrp	x8, _RX_CNTL_CSR_LOAD_RXD@GOTPAGE
Lloh86:
	ldr	x8, [x8, _RX_CNTL_CSR_LOAD_RXD@GOTPAGEOFF]
Lloh87:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x20]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGot	Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGot	Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_TX_RING_CSR0,4,2               ; @TX_RING_CSR0
	.comm	_TX_RING_CSR0_AC0_RING_SIZE,4,2 ; @TX_RING_CSR0_AC0_RING_SIZE
	.comm	_TX_RING_CSR0_AC1_RING_SIZE,4,2 ; @TX_RING_CSR0_AC1_RING_SIZE
	.comm	_TX_RING_CSR0_AC2_RING_SIZE,4,2 ; @TX_RING_CSR0_AC2_RING_SIZE
	.comm	_TX_RING_CSR0_AC3_RING_SIZE,4,2 ; @TX_RING_CSR0_AC3_RING_SIZE
	.comm	_TX_RING_CSR1,4,2               ; @TX_RING_CSR1
	.comm	_TX_RING_CSR1_TXD_SIZE,4,2      ; @TX_RING_CSR1_TXD_SIZE
	.comm	_AC0_BASE_CSR,4,2               ; @AC0_BASE_CSR
	.comm	_AC0_BASE_CSR_RING_REGISTER,4,2 ; @AC0_BASE_CSR_RING_REGISTER
	.comm	_AC1_BASE_CSR,4,2               ; @AC1_BASE_CSR
	.comm	_AC1_BASE_CSR_RING_REGISTER,4,2 ; @AC1_BASE_CSR_RING_REGISTER
	.comm	_AC2_BASE_CSR,4,2               ; @AC2_BASE_CSR
	.comm	_AC2_BASE_CSR_RING_REGISTER,4,2 ; @AC2_BASE_CSR_RING_REGISTER
	.comm	_AC3_BASE_CSR,4,2               ; @AC3_BASE_CSR
	.comm	_AC3_BASE_CSR_RING_REGISTER,4,2 ; @AC3_BASE_CSR_RING_REGISTER
	.comm	_RX_RING_CSR,4,2                ; @RX_RING_CSR
	.comm	_RX_RING_CSR_RING_SIZE,4,2      ; @RX_RING_CSR_RING_SIZE
	.comm	_RX_RING_CSR_RXD_SIZE,4,2       ; @RX_RING_CSR_RXD_SIZE
	.comm	_RX_RING_CSR_RXD_WRITEBACK_SIZE,4,2 ; @RX_RING_CSR_RXD_WRITEBACK_SIZE
	.comm	_RX_BASE_CSR,4,2                ; @RX_BASE_CSR
	.comm	_RX_BASE_CSR_RING_REGISTER,4,2  ; @RX_BASE_CSR_RING_REGISTER
	.comm	_TX_DMA_DST_CSR,4,2             ; @TX_DMA_DST_CSR
	.comm	_TX_DMA_DST_CSR_DEST_AC0,4,2    ; @TX_DMA_DST_CSR_DEST_AC0
	.comm	_TX_DMA_DST_CSR_DEST_AC1,4,2    ; @TX_DMA_DST_CSR_DEST_AC1
	.comm	_TX_DMA_DST_CSR_DEST_AC2,4,2    ; @TX_DMA_DST_CSR_DEST_AC2
	.comm	_TX_DMA_DST_CSR_DEST_AC3,4,2    ; @TX_DMA_DST_CSR_DEST_AC3
	.comm	_LOAD_TX_RING_CSR,4,2           ; @LOAD_TX_RING_CSR
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC0,4,2 ; @LOAD_TX_RING_CSR_LOAD_TXD_AC0
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC1,4,2 ; @LOAD_TX_RING_CSR_LOAD_TXD_AC1
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC2,4,2 ; @LOAD_TX_RING_CSR_LOAD_TXD_AC2
	.comm	_LOAD_TX_RING_CSR_LOAD_TXD_AC3,4,2 ; @LOAD_TX_RING_CSR_LOAD_TXD_AC3
	.comm	_RX_CNTL_CSR,4,2                ; @RX_CNTL_CSR
	.comm	_RX_CNTL_CSR_LOAD_RXD,4,2       ; @RX_CNTL_CSR_LOAD_RXD
	.no_dead_strip	_rt61pci_init_queues
.subsections_via_symbols
