	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ltq_vrx200_pcie_phy_power_on
_ltq_vrx200_pcie_phy_power_on:          ## @ltq_vrx200_pcie_phy_power_on
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	callq	_phy_get_drvdata
	movq	%rax, %r14
	movl	(%rax), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.1:
	movq	%r15, %rdi
	callq	_ltq_vrx200_pcie_phy_common_setup
	movq	%r15, %rdi
	callq	_pcie_phy_36mhz_mode_setup
	movl	4(%r14), %edi
	callq	_clk_prepare_enable
	movl	%eax, %ebx
	testl	%eax, %eax
	jne	LBB0_5
## %bb.2:
	movq	%r15, %rdi
	callq	_ltq_vrx200_pcie_phy_wait_for_pll
	testq	%rax, %rax
	je	LBB0_3
## %bb.4:
	movl	4(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_5:
	movl	(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_6:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_3:
	movq	%r15, %rdi
	callq	_ltq_vrx200_pcie_phy_apply_workarounds
	xorl	%ebx, %ebx
	jmp	LBB0_6
	.cfi_endproc
                                        ## -- End function
	.no_dead_strip	_ltq_vrx200_pcie_phy_power_on
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ltq_vrx200_pcie_phy_power_on
_ltq_vrx200_pcie_phy_power_on:          ; @ltq_vrx200_pcie_phy_power_on
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	bl	_phy_get_drvdata
	mov	x19, x0
	ldr	w0, [x0]
	bl	_clk_prepare_enable
	mov	x21, x0
	cbnz	w0, LBB0_5
; %bb.1:
	mov	x0, x20
	bl	_ltq_vrx200_pcie_phy_common_setup
	mov	x0, x20
	bl	_pcie_phy_36mhz_mode_setup
	ldr	w0, [x19, #4]
	bl	_clk_prepare_enable
	mov	x21, x0
	cbnz	w0, LBB0_4
; %bb.2:
	mov	x0, x20
	bl	_ltq_vrx200_pcie_phy_wait_for_pll
	cbz	x0, LBB0_6
; %bb.3:
	ldr	w0, [x19, #4]
	bl	_clk_disable_unprepare
LBB0_4:
	ldr	w0, [x19]
	bl	_clk_disable_unprepare
LBB0_5:
	mov	x0, x21
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_6:
	mov	x0, x20
	bl	_ltq_vrx200_pcie_phy_apply_workarounds
	mov	w21, #0
	b	LBB0_5
	.cfi_endproc
                                        ; -- End function
	.no_dead_strip	_ltq_vrx200_pcie_phy_power_on
.subsections_via_symbols
