	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rtl8xxxu_gen1_disable_rf       ## -- Begin function rtl8xxxu_gen1_disable_rf
	.p2align	4, 0x90
_rtl8xxxu_gen1_disable_rf:              ## @rtl8xxxu_gen1_disable_rf
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	_REG_SPS0_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_rtl8xxxu_read8
	movl	%eax, %r14d
	movq	_REG_FPGA0_XAB_RF_PARM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	movl	%eax, %r12d
	movl	$3, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$4, %edi
	callq	_BIT
	movl	%eax, %r13d
	orl	%ebx, %r13d
	movl	$5, %edi
	callq	_BIT
	movl	%eax, %ebx
	orl	%r13d, %ebx
	notl	%ebx
	andl	%r12d, %ebx
	cmpl	$2, (%r15)
	jne	LBB0_2
## %bb.1:
	movl	$19, %edi
	callq	_BIT
	movl	%eax, %r12d
	movl	$20, %edi
	callq	_BIT
	movl	%eax, %r13d
	orl	%r12d, %r13d
	movl	$21, %edi
	callq	_BIT
	orl	%r13d, %eax
	notl	%eax
	andl	%eax, %ebx
LBB0_2:
	movq	_REG_FPGA0_XAB_RF_PARM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_OFDM0_TRX_PATH_ENABLE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	movq	_OFDM_RF_PATH_TX_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_write32
	movq	_REG_FPGA0_RF_MODE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	movq	_FPGA_RF_MODE_JAPAN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %esi
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	cmpl	$2, (%r15)
	movq	_REG_RX_WAIT_CCA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$14362016, %eax                 ## imm = 0xDB25A0
	movl	$1779104, %edx                  ## imm = 0x1B25A0
	cmovel	%eax, %edx
	movq	%r15, %rdi
	callq	_rtl8xxxu_write32
	movq	_RF_A@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_RF6052_REG_AC@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r15, %rdi
	xorl	%ecx, %ecx
	callq	_rtl8xxxu_write_rfreg
	cmpl	$2, (%r15)
	jne	LBB0_4
## %bb.3:
	movq	_RF_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	xorl	%ecx, %ecx
	callq	_rtl8xxxu_write_rfreg
LBB0_4:
	xorl	%edi, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$3, %edi
	callq	_BIT
	orl	%eax, %ebx
	notl	%ebx
	andl	%ebx, %r14d
	movq	_REG_SPS0_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rtl8xxxu_write8                ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_SPS0_CTRL,4,2              ## @REG_SPS0_CTRL
	.comm	_REG_FPGA0_XAB_RF_PARM,4,2      ## @REG_FPGA0_XAB_RF_PARM
	.comm	_REG_OFDM0_TRX_PATH_ENABLE,4,2  ## @REG_OFDM0_TRX_PATH_ENABLE
	.comm	_OFDM_RF_PATH_TX_MASK,4,2       ## @OFDM_RF_PATH_TX_MASK
	.comm	_REG_FPGA0_RF_MODE,4,2          ## @REG_FPGA0_RF_MODE
	.comm	_FPGA_RF_MODE_JAPAN,4,2         ## @FPGA_RF_MODE_JAPAN
	.comm	_REG_RX_WAIT_CCA,4,2            ## @REG_RX_WAIT_CCA
	.comm	_RF_A,4,2                       ## @RF_A
	.comm	_RF6052_REG_AC,4,2              ## @RF6052_REG_AC
	.comm	_RF_B,4,2                       ## @RF_B
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_rtl8xxxu_gen1_disable_rf       ; -- Begin function rtl8xxxu_gen1_disable_rf
	.p2align	2
_rtl8xxxu_gen1_disable_rf:              ; @rtl8xxxu_gen1_disable_rf
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x23, _REG_SPS0_CTRL@GOTPAGE
Lloh1:
	ldr	x23, [x23, _REG_SPS0_CTRL@GOTPAGEOFF]
	ldr	w1, [x23]
	bl	_rtl8xxxu_read8
	mov	x20, x0
Lloh2:
	adrp	x24, _REG_FPGA0_XAB_RF_PARM@GOTPAGE
Lloh3:
	ldr	x24, [x24, _REG_FPGA0_XAB_RF_PARM@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	mov	x21, x0
	mov	w0, #3
	bl	_BIT
	mov	x22, x0
	mov	w0, #4
	bl	_BIT
	orr	w22, w0, w22
	mov	w0, #5
	bl	_BIT
	orr	w8, w22, w0
	bic	w21, w21, w8
	ldr	w8, [x19]
	cmp	w8, #2
	b.ne	LBB0_2
; %bb.1:
	mov	w0, #19
	bl	_BIT
	mov	x22, x0
	mov	w0, #20
	bl	_BIT
	orr	w22, w0, w22
	mov	w0, #21
	bl	_BIT
	orr	w8, w22, w0
	bic	w21, w21, w8
LBB0_2:
	ldr	w1, [x24]
	mov	x0, x19
	mov	x2, x21
	bl	_rtl8xxxu_write32
Lloh4:
	adrp	x21, _REG_OFDM0_TRX_PATH_ENABLE@GOTPAGE
Lloh5:
	ldr	x21, [x21, _REG_OFDM0_TRX_PATH_ENABLE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rtl8xxxu_read32
Lloh6:
	adrp	x8, _OFDM_RF_PATH_TX_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _OFDM_RF_PATH_TX_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rtl8xxxu_write32
Lloh9:
	adrp	x21, _REG_FPGA0_RF_MODE@GOTPAGE
Lloh10:
	ldr	x21, [x21, _REG_FPGA0_RF_MODE@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rtl8xxxu_read32
Lloh11:
	adrp	x8, _FPGA_RF_MODE_JAPAN@GOTPAGE
Lloh12:
	ldr	x8, [x8, _FPGA_RF_MODE_JAPAN@GOTPAGEOFF]
Lloh13:
	ldr	w8, [x8]
	orr	w2, w8, w0
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rtl8xxxu_write32
Lloh14:
	adrp	x8, _REG_RX_WAIT_CCA@GOTPAGE
Lloh15:
	ldr	x8, [x8, _REG_RX_WAIT_CCA@GOTPAGEOFF]
	ldr	w9, [x19]
Lloh16:
	ldr	w1, [x8]
	mov	w8, #9632
	movk	w8, #27, lsl #16
	orr	w10, w8, #0xc00000
	cmp	w9, #2
	csel	w2, w10, w8, eq
	mov	x0, x19
	bl	_rtl8xxxu_write32
Lloh17:
	adrp	x8, _RF_A@GOTPAGE
Lloh18:
	ldr	x8, [x8, _RF_A@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
Lloh20:
	adrp	x21, _RF6052_REG_AC@GOTPAGE
Lloh21:
	ldr	x21, [x21, _RF6052_REG_AC@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x19
	mov	w3, #0
	bl	_rtl8xxxu_write_rfreg
	ldr	w8, [x19]
	cmp	w8, #2
	b.ne	LBB0_4
; %bb.3:
Lloh22:
	adrp	x8, _RF_B@GOTPAGE
Lloh23:
	ldr	x8, [x8, _RF_B@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	ldr	w2, [x21]
	mov	x0, x19
	mov	w3, #0
	bl	_rtl8xxxu_write_rfreg
LBB0_4:
	mov	w0, #0
	bl	_BIT
	mov	x21, x0
	mov	w0, #3
	bl	_BIT
	orr	w8, w0, w21
	bic	w2, w20, w8
	ldr	w1, [x23]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_rtl8xxxu_write8
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_SPS0_CTRL,4,2              ; @REG_SPS0_CTRL
	.comm	_REG_FPGA0_XAB_RF_PARM,4,2      ; @REG_FPGA0_XAB_RF_PARM
	.comm	_REG_OFDM0_TRX_PATH_ENABLE,4,2  ; @REG_OFDM0_TRX_PATH_ENABLE
	.comm	_OFDM_RF_PATH_TX_MASK,4,2       ; @OFDM_RF_PATH_TX_MASK
	.comm	_REG_FPGA0_RF_MODE,4,2          ; @REG_FPGA0_RF_MODE
	.comm	_FPGA_RF_MODE_JAPAN,4,2         ; @FPGA_RF_MODE_JAPAN
	.comm	_REG_RX_WAIT_CCA,4,2            ; @REG_RX_WAIT_CCA
	.comm	_RF_A,4,2                       ; @RF_A
	.comm	_RF6052_REG_AC,4,2              ; @RF6052_REG_AC
	.comm	_RF_B,4,2                       ; @RF_B
.subsections_via_symbols
