	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath10k_ahb_halt_chip
_ath10k_ahb_halt_chip:                  ## @ath10k_ahb_halt_chip
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_ath10k_ahb_priv
	movq	%rax, %r14
	movl	(%rax), %edi
	callq	_IS_ERR_OR_NULL
	testq	%rax, %rax
	jne	LBB0_22
## %bb.1:
	movl	16(%r14), %edi
	callq	_IS_ERR_OR_NULL
	testq	%rax, %rax
	jne	LBB0_22
## %bb.2:
	movl	12(%r14), %edi
	callq	_IS_ERR_OR_NULL
	testq	%rax, %rax
	jne	LBB0_22
## %bb.3:
	movl	8(%r14), %edi
	callq	_IS_ERR_OR_NULL
	testq	%rax, %rax
	jne	LBB0_22
## %bb.4:
	movl	4(%r14), %edi
	callq	_IS_ERR_OR_NULL
	testq	%rax, %rax
	je	LBB0_5
LBB0_22:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath10k_err                     ## TAILCALL
LBB0_5:
	movq	_ATH10K_AHB_WLAN_CORE_ID_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_ath10k_ahb_read32
	movl	%eax, %r15d
	testl	%eax, %eax
	je	LBB0_6
## %bb.7:
	cmpl	$1, %r15d
	jne	LBB0_23
## %bb.8:
	movq	_ATH10K_AHB_TCSR_WCSS1_HALTACK@GOTPCREL(%rip), %rax
	movq	_ATH10K_AHB_TCSR_WCSS1_HALTREQ@GOTPCREL(%rip), %rcx
	movq	_ATH10K_AHB_TCSR_WIFI1_GLB_CFG@GOTPCREL(%rip), %rsi
	jmp	LBB0_9
LBB0_6:
	movq	_ATH10K_AHB_TCSR_WCSS0_HALTACK@GOTPCREL(%rip), %rax
	movq	_ATH10K_AHB_TCSR_WCSS0_HALTREQ@GOTPCREL(%rip), %rcx
	movq	_ATH10K_AHB_TCSR_WIFI0_GLB_CFG@GOTPCREL(%rip), %rsi
LBB0_9:
	movl	(%rax), %edx
	movl	(%rcx), %r13d
	movl	(%rsi), %r12d
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_ath10k_ahb_halt_axi_bus
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_ath10k_ahb_tcsr_read32
	movq	_TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%rbx, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_ath10k_ahb_tcsr_write32
	movl	(%r14), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_11
## %bb.10:
	leaq	L_.str.2(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_ath10k_err
LBB0_11:
	movl	$1, %edi
	callq	_msleep
	movl	16(%r14), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_13
## %bb.12:
	leaq	L_.str.3(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_ath10k_err
LBB0_13:
	movl	$1, %edi
	callq	_msleep
	movl	12(%r14), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_15
## %bb.14:
	leaq	L_.str.4(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_ath10k_err
LBB0_15:
	movl	$1, %edi
	callq	_msleep
	movl	8(%r14), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_17
## %bb.16:
	leaq	L_.str.5(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_ath10k_err
LBB0_17:
	movl	$1, %edi
	callq	_msleep
	movl	4(%r14), %edi
	callq	_reset_control_assert
	testl	%eax, %eax
	je	LBB0_19
## %bb.18:
	leaq	L_.str.6(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_ath10k_err
LBB0_19:
	movl	$10, %edi
	callq	_msleep
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_ath10k_ahb_tcsr_read32
	movq	_AHB_AXI_BUS_HALT_REQ@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%rbx, %rdi
	movl	%r13d, %esi
	callq	_ath10k_ahb_tcsr_write32
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_ath10k_ahb_tcsr_read32
	movq	_TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%rbx, %rdi
	movl	%r12d, %esi
	callq	_ath10k_ahb_tcsr_write32
	movl	(%r14), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_21
## %bb.20:
	leaq	L_.str.7(%rip), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_ath10k_err
LBB0_21:
	movq	_ATH10K_DBG_AHB@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	L_.str.8(%rip), %rdx
	movq	%rbx, %rdi
	movl	%r15d, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath10k_dbg                     ## TAILCALL
LBB0_23:
	leaq	L_.str.1(%rip), %rsi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath10k_err                     ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"rst ctrl(s) is/are not initialized\n"

	.comm	_ATH10K_AHB_WLAN_CORE_ID_REG,4,2 ## @ATH10K_AHB_WLAN_CORE_ID_REG
	.comm	_ATH10K_AHB_TCSR_WIFI0_GLB_CFG,4,2 ## @ATH10K_AHB_TCSR_WIFI0_GLB_CFG
	.comm	_ATH10K_AHB_TCSR_WCSS0_HALTREQ,4,2 ## @ATH10K_AHB_TCSR_WCSS0_HALTREQ
	.comm	_ATH10K_AHB_TCSR_WCSS0_HALTACK,4,2 ## @ATH10K_AHB_TCSR_WCSS0_HALTACK
	.comm	_ATH10K_AHB_TCSR_WIFI1_GLB_CFG,4,2 ## @ATH10K_AHB_TCSR_WIFI1_GLB_CFG
	.comm	_ATH10K_AHB_TCSR_WCSS1_HALTREQ,4,2 ## @ATH10K_AHB_TCSR_WCSS1_HALTREQ
	.comm	_ATH10K_AHB_TCSR_WCSS1_HALTACK,4,2 ## @ATH10K_AHB_TCSR_WCSS1_HALTACK
L_.str.1:                               ## @.str.1
	.asciz	"invalid core id %d found, skipping reset sequence\n"

	.comm	_TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK,4,2 ## @TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK
L_.str.2:                               ## @.str.2
	.asciz	"failed to assert core cold rst: %d\n"

L_.str.3:                               ## @.str.3
	.asciz	"failed to assert radio cold rst: %d\n"

L_.str.4:                               ## @.str.4
	.asciz	"failed to assert radio warm rst: %d\n"

L_.str.5:                               ## @.str.5
	.asciz	"failed to assert radio srif rst: %d\n"

L_.str.6:                               ## @.str.6
	.asciz	"failed to assert cpu init rst: %d\n"

	.comm	_AHB_AXI_BUS_HALT_REQ,4,2       ## @AHB_AXI_BUS_HALT_REQ
L_.str.7:                               ## @.str.7
	.asciz	"failed to deassert core cold rst: %d\n"

	.comm	_ATH10K_DBG_AHB,4,2             ## @ATH10K_DBG_AHB
L_.str.8:                               ## @.str.8
	.asciz	"core %d reset done\n"

	.no_dead_strip	_ath10k_ahb_halt_chip
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath10k_ahb_halt_chip
_ath10k_ahb_halt_chip:                  ; @ath10k_ahb_halt_chip
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_ath10k_ahb_priv
	mov	x20, x0
	ldr	w0, [x0]
	bl	_IS_ERR_OR_NULL
	cbnz	x0, LBB0_5
; %bb.1:
	ldr	w0, [x20, #16]
	bl	_IS_ERR_OR_NULL
	cbnz	x0, LBB0_5
; %bb.2:
	ldr	w0, [x20, #12]
	bl	_IS_ERR_OR_NULL
	cbnz	x0, LBB0_5
; %bb.3:
	ldr	w0, [x20, #8]
	bl	_IS_ERR_OR_NULL
	cbnz	x0, LBB0_5
; %bb.4:
	ldr	w0, [x20, #4]
	bl	_IS_ERR_OR_NULL
	cbz	x0, LBB0_6
LBB0_5:
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_ath10k_err
LBB0_6:
Lloh2:
	adrp	x8, _ATH10K_AHB_WLAN_CORE_ID_REG@GOTPAGE
Lloh3:
	ldr	x8, [x8, _ATH10K_AHB_WLAN_CORE_ID_REG@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_ath10k_ahb_read32
	mov	x21, x0
	cbz	w0, LBB0_9
; %bb.7:
	cmp	w21, #1
	b.ne	LBB0_23
; %bb.8:
Lloh5:
	adrp	x8, _ATH10K_AHB_TCSR_WCSS1_HALTACK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _ATH10K_AHB_TCSR_WCSS1_HALTACK@GOTPAGEOFF]
Lloh7:
	adrp	x9, _ATH10K_AHB_TCSR_WCSS1_HALTREQ@GOTPAGE
Lloh8:
	ldr	x9, [x9, _ATH10K_AHB_TCSR_WCSS1_HALTREQ@GOTPAGEOFF]
Lloh9:
	adrp	x10, _ATH10K_AHB_TCSR_WIFI1_GLB_CFG@GOTPAGE
Lloh10:
	ldr	x10, [x10, _ATH10K_AHB_TCSR_WIFI1_GLB_CFG@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh11:
	adrp	x8, _ATH10K_AHB_TCSR_WCSS0_HALTACK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _ATH10K_AHB_TCSR_WCSS0_HALTACK@GOTPAGEOFF]
Lloh13:
	adrp	x9, _ATH10K_AHB_TCSR_WCSS0_HALTREQ@GOTPAGE
Lloh14:
	ldr	x9, [x9, _ATH10K_AHB_TCSR_WCSS0_HALTREQ@GOTPAGEOFF]
Lloh15:
	adrp	x10, _ATH10K_AHB_TCSR_WIFI0_GLB_CFG@GOTPAGE
Lloh16:
	ldr	x10, [x10, _ATH10K_AHB_TCSR_WIFI0_GLB_CFG@GOTPAGEOFF]
LBB0_10:
	ldr	w2, [x8]
	ldr	w23, [x9]
	ldr	w22, [x10]
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_ahb_halt_axi_bus
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_ahb_tcsr_read32
Lloh17:
	adrp	x24, _TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK@GOTPAGE
Lloh18:
	ldr	x24, [x24, _TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK@GOTPAGEOFF]
	ldr	w8, [x24]
	orr	w2, w8, w0
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_ahb_tcsr_write32
	ldr	w0, [x20]
	bl	_reset_control_assert
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_12
; %bb.11:
	str	x0, [sp]
Lloh19:
	adrp	x1, l_.str.2@PAGE
Lloh20:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
LBB0_12:
	mov	w0, #1
	bl	_msleep
	ldr	w0, [x20, #16]
	bl	_reset_control_assert
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_14
; %bb.13:
	str	x0, [sp]
Lloh21:
	adrp	x1, l_.str.3@PAGE
Lloh22:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
LBB0_14:
	mov	w0, #1
	bl	_msleep
	ldr	w0, [x20, #12]
	bl	_reset_control_assert
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_16
; %bb.15:
	str	x0, [sp]
Lloh23:
	adrp	x1, l_.str.4@PAGE
Lloh24:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
LBB0_16:
	mov	w0, #1
	bl	_msleep
	ldr	w0, [x20, #8]
	bl	_reset_control_assert
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_18
; %bb.17:
	str	x0, [sp]
Lloh25:
	adrp	x1, l_.str.5@PAGE
Lloh26:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
LBB0_18:
	mov	w0, #1
	bl	_msleep
	ldr	w0, [x20, #4]
	bl	_reset_control_assert
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_20
; %bb.19:
	str	x0, [sp]
Lloh27:
	adrp	x1, l_.str.6@PAGE
Lloh28:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
LBB0_20:
	mov	w0, #10
	bl	_msleep
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_ahb_tcsr_read32
Lloh29:
	adrp	x8, _AHB_AXI_BUS_HALT_REQ@GOTPAGE
Lloh30:
	ldr	x8, [x8, _AHB_AXI_BUS_HALT_REQ@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_ahb_tcsr_write32
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_ahb_tcsr_read32
	ldr	w8, [x24]
	bic	w2, w0, w8
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_ahb_tcsr_write32
	ldr	w0, [x20]
	bl	_reset_control_deassert
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_22
; %bb.21:
	str	x0, [sp]
Lloh32:
	adrp	x1, l_.str.7@PAGE
Lloh33:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
LBB0_22:
Lloh34:
	adrp	x8, _ATH10K_DBG_AHB@GOTPAGE
Lloh35:
	ldr	x8, [x8, _ATH10K_DBG_AHB@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
Lloh37:
	adrp	x2, l_.str.8@PAGE
Lloh38:
	add	x2, x2, l_.str.8@PAGEOFF
	mov	x0, x19
	mov	x3, x21
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_ath10k_dbg
LBB0_23:
	str	x21, [sp]
Lloh39:
	adrp	x1, l_.str.1@PAGE
Lloh40:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_ath10k_err
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpAdd	Lloh25, Lloh26
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpAdd	Lloh39, Lloh40
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"rst ctrl(s) is/are not initialized\n"

	.comm	_ATH10K_AHB_WLAN_CORE_ID_REG,4,2 ; @ATH10K_AHB_WLAN_CORE_ID_REG
	.comm	_ATH10K_AHB_TCSR_WIFI0_GLB_CFG,4,2 ; @ATH10K_AHB_TCSR_WIFI0_GLB_CFG
	.comm	_ATH10K_AHB_TCSR_WCSS0_HALTREQ,4,2 ; @ATH10K_AHB_TCSR_WCSS0_HALTREQ
	.comm	_ATH10K_AHB_TCSR_WCSS0_HALTACK,4,2 ; @ATH10K_AHB_TCSR_WCSS0_HALTACK
	.comm	_ATH10K_AHB_TCSR_WIFI1_GLB_CFG,4,2 ; @ATH10K_AHB_TCSR_WIFI1_GLB_CFG
	.comm	_ATH10K_AHB_TCSR_WCSS1_HALTREQ,4,2 ; @ATH10K_AHB_TCSR_WCSS1_HALTREQ
	.comm	_ATH10K_AHB_TCSR_WCSS1_HALTACK,4,2 ; @ATH10K_AHB_TCSR_WCSS1_HALTACK
l_.str.1:                               ; @.str.1
	.asciz	"invalid core id %d found, skipping reset sequence\n"

	.comm	_TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK,4,2 ; @TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK
l_.str.2:                               ; @.str.2
	.asciz	"failed to assert core cold rst: %d\n"

l_.str.3:                               ; @.str.3
	.asciz	"failed to assert radio cold rst: %d\n"

l_.str.4:                               ; @.str.4
	.asciz	"failed to assert radio warm rst: %d\n"

l_.str.5:                               ; @.str.5
	.asciz	"failed to assert radio srif rst: %d\n"

l_.str.6:                               ; @.str.6
	.asciz	"failed to assert cpu init rst: %d\n"

	.comm	_AHB_AXI_BUS_HALT_REQ,4,2       ; @AHB_AXI_BUS_HALT_REQ
l_.str.7:                               ; @.str.7
	.asciz	"failed to deassert core cold rst: %d\n"

	.comm	_ATH10K_DBG_AHB,4,2             ; @ATH10K_DBG_AHB
l_.str.8:                               ; @.str.8
	.asciz	"core %d reset done\n"

	.no_dead_strip	_ath10k_ahb_halt_chip
.subsections_via_symbols
