	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cdns_pcie_host_init_root_port
_cdns_pcie_host_init_root_port:         ## @cdns_pcie_host_init_root_port
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	leaq	8(%rdi), %r15
	movq	_CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%r12d, %edi
	callq	_CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL
	orl	%eax, %ebx
	movq	_CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_CDNS_PCIE_LM_RC_BAR_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_cdns_pcie_writel
	movl	(%r14), %edx
	cmpl	$65535, %edx                    ## imm = 0xFFFF
	je	LBB0_2
## %bb.1:
	movq	_PCI_VENDOR_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_cdns_pcie_rp_writew
LBB0_2:
	movl	4(%r14), %edx
	cmpl	$65535, %edx                    ## imm = 0xFFFF
	je	LBB0_4
## %bb.3:
	movq	_PCI_DEVICE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_cdns_pcie_rp_writew
LBB0_4:
	movq	_PCI_CLASS_REVISION@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_cdns_pcie_rp_writeb
	movq	_PCI_CLASS_PROG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_cdns_pcie_rp_writeb
	movq	_PCI_CLASS_DEVICE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCI_CLASS_BRIDGE_PCI@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_cdns_pcie_rp_writew
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED,4,2 ## @CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE,4,2 ## @CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS,4,2 ## @CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE,4,2 ## @CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS,4,2 ## @CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG,4,2    ## @CDNS_PCIE_LM_RC_BAR_CFG
	.comm	_PCI_VENDOR_ID,4,2              ## @PCI_VENDOR_ID
	.comm	_PCI_DEVICE_ID,4,2              ## @PCI_DEVICE_ID
	.comm	_PCI_CLASS_REVISION,4,2         ## @PCI_CLASS_REVISION
	.comm	_PCI_CLASS_PROG,4,2             ## @PCI_CLASS_PROG
	.comm	_PCI_CLASS_DEVICE,4,2           ## @PCI_CLASS_DEVICE
	.comm	_PCI_CLASS_BRIDGE_PCI,4,2       ## @PCI_CLASS_BRIDGE_PCI
	.no_dead_strip	_cdns_pcie_host_init_root_port
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cdns_pcie_host_init_root_port
_cdns_pcie_host_init_root_port:         ; @cdns_pcie_host_init_root_port
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	add	x19, x0, #8
Lloh0:
	adrp	x8, _CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED@GOTPAGEOFF]
Lloh2:
	ldr	w21, [x8]
	mov	x0, x21
	bl	_CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL
	mov	x22, x0
	mov	x0, x21
	bl	_CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL
Lloh3:
	adrp	x8, _CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE@GOTPAGEOFF]
	orr	w9, w0, w22
Lloh5:
	ldr	w8, [x8]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh9:
	adrp	x9, _CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE@GOTPAGE
Lloh10:
	ldr	x9, [x9, _CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
Lloh12:
	adrp	x10, _CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS@GOTPAGE
Lloh13:
	ldr	x10, [x10, _CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh14:
	ldr	w9, [x10]
	orr	w2, w8, w9
Lloh15:
	adrp	x8, _CDNS_PCIE_LM_RC_BAR_CFG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CDNS_PCIE_LM_RC_BAR_CFG@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_cdns_pcie_writel
	ldr	w2, [x20]
	mov	w21, #65535
	cmp	w2, w21
	b.eq	LBB0_2
; %bb.1:
Lloh18:
	adrp	x8, _PCI_VENDOR_ID@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PCI_VENDOR_ID@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_cdns_pcie_rp_writew
LBB0_2:
	ldr	w2, [x20, #4]
	cmp	w2, w21
	b.eq	LBB0_4
; %bb.3:
Lloh21:
	adrp	x8, _PCI_DEVICE_ID@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PCI_DEVICE_ID@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_cdns_pcie_rp_writew
LBB0_4:
Lloh24:
	adrp	x8, _PCI_CLASS_REVISION@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PCI_CLASS_REVISION@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_cdns_pcie_rp_writeb
Lloh27:
	adrp	x8, _PCI_CLASS_PROG@GOTPAGE
Lloh28:
	ldr	x8, [x8, _PCI_CLASS_PROG@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_cdns_pcie_rp_writeb
Lloh30:
	adrp	x8, _PCI_CLASS_DEVICE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _PCI_CLASS_DEVICE@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _PCI_CLASS_BRIDGE_PCI@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PCI_CLASS_BRIDGE_PCI@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_cdns_pcie_rp_writew
	mov	w0, #0
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED,4,2 ; @CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE,4,2 ; @CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS,4,2 ; @CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE,4,2 ; @CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS,4,2 ; @CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS
	.comm	_CDNS_PCIE_LM_RC_BAR_CFG,4,2    ; @CDNS_PCIE_LM_RC_BAR_CFG
	.comm	_PCI_VENDOR_ID,4,2              ; @PCI_VENDOR_ID
	.comm	_PCI_DEVICE_ID,4,2              ; @PCI_DEVICE_ID
	.comm	_PCI_CLASS_REVISION,4,2         ; @PCI_CLASS_REVISION
	.comm	_PCI_CLASS_PROG,4,2             ; @PCI_CLASS_PROG
	.comm	_PCI_CLASS_DEVICE,4,2           ; @PCI_CLASS_DEVICE
	.comm	_PCI_CLASS_BRIDGE_PCI,4,2       ; @PCI_CLASS_BRIDGE_PCI
	.no_dead_strip	_cdns_pcie_host_init_root_port
.subsections_via_symbols
