	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ar9002_hw_enable_async_fifo    ## -- Begin function ar9002_hw_enable_async_fifo
	.p2align	4, 0x90
_ar9002_hw_enable_async_fifo:           ## @ar9002_hw_enable_async_fifo
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_AR_SREV_9287_13_OR_LATER
	testq	%rax, %rax
	je	LBB0_1
## %bb.2:
	movq	_AR_MAC_PCU_ASYNC_FIFO_REG3@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	_AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_REG_SET_BIT
	movq	_AR_PHY_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_PHY_MODE_ASYNCFIFO@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_REG_SET_BIT
	movl	(%r14), %esi
	movq	_AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	%rbx, %rdi
	callq	_REG_CLR_BIT
	movl	(%r14), %esi
	movl	(%r15), %edx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_REG_SET_BIT                    ## TAILCALL
LBB0_1:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_MAC_PCU_ASYNC_FIFO_REG3,4,2 ## @AR_MAC_PCU_ASYNC_FIFO_REG3
	.comm	_AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL,4,2 ## @AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
	.comm	_AR_PHY_MODE,4,2                ## @AR_PHY_MODE
	.comm	_AR_PHY_MODE_ASYNCFIFO,4,2      ## @AR_PHY_MODE_ASYNCFIFO
	.comm	_AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET,4,2 ## @AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ar9002_hw_enable_async_fifo    ; -- Begin function ar9002_hw_enable_async_fifo
	.p2align	2
_ar9002_hw_enable_async_fifo:           ; @ar9002_hw_enable_async_fifo
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_AR_SREV_9287_13_OR_LATER
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x20, _AR_MAC_PCU_ASYNC_FIFO_REG3@GOTPAGE
Lloh1:
	ldr	x20, [x20, _AR_MAC_PCU_ASYNC_FIFO_REG3@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL@GOTPAGE
Lloh3:
	ldr	x8, [x8, _AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_REG_SET_BIT
Lloh5:
	adrp	x8, _AR_PHY_MODE@GOTPAGE
Lloh6:
	ldr	x8, [x8, _AR_PHY_MODE@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
Lloh8:
	adrp	x8, _AR_PHY_MODE_ASYNCFIFO@GOTPAGE
Lloh9:
	ldr	x8, [x8, _AR_PHY_MODE_ASYNCFIFO@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_REG_SET_BIT
	ldr	w1, [x20]
Lloh11:
	adrp	x21, _AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET@GOTPAGE
Lloh12:
	ldr	x21, [x21, _AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x19
	bl	_REG_CLR_BIT
	ldr	w1, [x20]
	ldr	w2, [x21]
	mov	x0, x19
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_REG_SET_BIT
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_MAC_PCU_ASYNC_FIFO_REG3,4,2 ; @AR_MAC_PCU_ASYNC_FIFO_REG3
	.comm	_AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL,4,2 ; @AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL
	.comm	_AR_PHY_MODE,4,2                ; @AR_PHY_MODE
	.comm	_AR_PHY_MODE_ASYNCFIFO,4,2      ; @AR_PHY_MODE_ASYNCFIFO
	.comm	_AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET,4,2 ; @AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET
.subsections_via_symbols
