	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_config_controller
_tegra_pcie_config_controller:          ## @tegra_pcie_config_controller
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	$1, %esi
	callq	_tegra_pcie_bpmp_set_ctrl_state
	testl	%eax, %eax
	je	LBB0_2
## %bb.1:
	movl	%eax, %ebx
	movl	48(%r14), %edi
	movl	52(%r14), %edx
	leaq	L_.str(%rip), %rsi
	movl	%eax, %ecx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_22
LBB0_2:
	movq	%r14, %rdi
	callq	_tegra_pcie_enable_slot_regulators
	testl	%eax, %eax
	js	LBB0_3
## %bb.4:
	movl	(%r14), %edi
	callq	_regulator_enable
	testl	%eax, %eax
	js	LBB0_5
## %bb.6:
	movl	4(%r14), %edi
	callq	_clk_prepare_enable
	testl	%eax, %eax
	je	LBB0_11
## %bb.7:
	movl	%eax, %ebx
	movl	48(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_8
LBB0_3:
	movl	%eax, %ebx
	jmp	LBB0_10
LBB0_5:
	movl	%eax, %ebx
	movl	48(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_9
LBB0_11:
	movl	8(%r14), %edi
	callq	_reset_control_deassert
	testl	%eax, %eax
	je	LBB0_14
## %bb.12:
	movl	%eax, %ebx
	movl	48(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_13
LBB0_14:
	testl	%r15d, %r15d
	je	LBB0_16
## %bb.15:
	movq	_APPL_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r14, %rdi
	callq	_appl_readl
	movq	_APPL_CTRL_HW_HOT_RST_MODE_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_APPL_CTRL_HW_HOT_RST_MODE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	notl	%esi
	andl	%eax, %esi
	movq	_APPL_CTRL_HW_HOT_RST_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %esi
	movl	(%rbx), %edx
	movq	%r14, %rdi
	callq	_appl_writel
LBB0_16:
	movq	%r14, %rdi
	callq	_tegra_pcie_enable_phy
	testl	%eax, %eax
	je	LBB0_18
## %bb.17:
	movl	%eax, %ebx
	movl	48(%r14), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	movl	8(%r14), %edi
	callq	_reset_control_assert
LBB0_13:
	movl	4(%r14), %edi
	callq	_clk_disable_unprepare
LBB0_8:
	movl	(%r14), %edi
	callq	_regulator_disable
LBB0_9:
	movq	%r14, %rdi
	callq	_tegra_pcie_disable_slot_regulators
LBB0_10:
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_tegra_pcie_bpmp_set_ctrl_state
LBB0_22:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_18:
	movq	40(%r14), %rax
	movq	_APPL_CFG_BASE_ADDR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	(%rax), %esi
	movq	_APPL_CFG_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_appl_writel
	movq	_APPL_DM_TYPE_RP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APPL_DM_TYPE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_appl_writel
	movq	_APPL_CFG_SLCG_OVERRIDE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ebx, %ebx
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	_appl_writel
	movq	_APPL_CTRL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_appl_readl
	movq	_APPL_CTRL_SYS_PRE_DET_STATE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_appl_writel
	movq	_APPL_CFG_MISC@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_appl_readl
	movq	_APPL_CFG_MISC_ARCACHE_VAL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_APPL_CFG_MISC_ARCACHE_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	orl	%eax, %esi
	movl	(%r15), %edx
	movq	%r14, %rdi
	callq	_appl_writel
	cmpl	$0, 12(%r14)
	jne	LBB0_20
## %bb.19:
	movq	_APPL_PINMUX@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%r14, %rdi
	callq	_appl_readl
	movq	_APPL_PINMUX_CLKREQ_OUT_OVRD_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_APPL_PINMUX_CLKREQ_OUT_OVRD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_appl_writel
LBB0_20:
	movq	32(%r14), %rax
	movq	_APPL_CFG_IATU_DMA_BASE_ADDR_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	andl	(%rax), %esi
	movq	_APPL_CFG_IATU_DMA_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_appl_writel
	movl	24(%r14), %edi
	callq	_reset_control_deassert
	leaq	16(%r14), %rdi
	movq	_PCI_CAP_ID_EXP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_dw_pcie_find_capability
	movl	%eax, 20(%r14)
	cmpl	$0, 12(%r14)
	jne	LBB0_22
## %bb.21:
	movq	%r14, %rdi
	callq	_disable_aspm_l11
	movq	%r14, %rdi
	callq	_disable_aspm_l12
	jmp	LBB0_22
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Failed to enable controller %u: %d\n"

L_.str.1:                               ## @.str.1
	.asciz	"Failed to enable regulator: %d\n"

L_.str.2:                               ## @.str.2
	.asciz	"Failed to enable core clock: %d\n"

L_.str.3:                               ## @.str.3
	.asciz	"Failed to deassert core APB reset: %d\n"

	.comm	_APPL_CTRL,4,2                  ## @APPL_CTRL
	.comm	_APPL_CTRL_HW_HOT_RST_MODE_MASK,4,2 ## @APPL_CTRL_HW_HOT_RST_MODE_MASK
	.comm	_APPL_CTRL_HW_HOT_RST_MODE_SHIFT,4,2 ## @APPL_CTRL_HW_HOT_RST_MODE_SHIFT
	.comm	_APPL_CTRL_HW_HOT_RST_EN,4,2    ## @APPL_CTRL_HW_HOT_RST_EN
L_.str.4:                               ## @.str.4
	.asciz	"Failed to enable PHY: %d\n"

	.comm	_APPL_CFG_BASE_ADDR_MASK,4,2    ## @APPL_CFG_BASE_ADDR_MASK
	.comm	_APPL_CFG_BASE_ADDR,4,2         ## @APPL_CFG_BASE_ADDR
	.comm	_APPL_DM_TYPE_RP,4,2            ## @APPL_DM_TYPE_RP
	.comm	_APPL_DM_TYPE,4,2               ## @APPL_DM_TYPE
	.comm	_APPL_CFG_SLCG_OVERRIDE,4,2     ## @APPL_CFG_SLCG_OVERRIDE
	.comm	_APPL_CTRL_SYS_PRE_DET_STATE,4,2 ## @APPL_CTRL_SYS_PRE_DET_STATE
	.comm	_APPL_CFG_MISC,4,2              ## @APPL_CFG_MISC
	.comm	_APPL_CFG_MISC_ARCACHE_VAL,4,2  ## @APPL_CFG_MISC_ARCACHE_VAL
	.comm	_APPL_CFG_MISC_ARCACHE_SHIFT,4,2 ## @APPL_CFG_MISC_ARCACHE_SHIFT
	.comm	_APPL_PINMUX,4,2                ## @APPL_PINMUX
	.comm	_APPL_PINMUX_CLKREQ_OUT_OVRD_EN,4,2 ## @APPL_PINMUX_CLKREQ_OUT_OVRD_EN
	.comm	_APPL_PINMUX_CLKREQ_OUT_OVRD,4,2 ## @APPL_PINMUX_CLKREQ_OUT_OVRD
	.comm	_APPL_CFG_IATU_DMA_BASE_ADDR_MASK,4,2 ## @APPL_CFG_IATU_DMA_BASE_ADDR_MASK
	.comm	_APPL_CFG_IATU_DMA_BASE_ADDR,4,2 ## @APPL_CFG_IATU_DMA_BASE_ADDR
	.comm	_PCI_CAP_ID_EXP,4,2             ## @PCI_CAP_ID_EXP
	.no_dead_strip	_tegra_pcie_config_controller
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_config_controller
_tegra_pcie_config_controller:          ; @tegra_pcie_config_controller
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x21, x1
	mov	x19, x0
	mov	w1, #1
	bl	_tegra_pcie_bpmp_set_ctrl_state
	cbz	w0, LBB0_2
; %bb.1:
	mov	x20, x0
	ldp	w0, w2, [x19, #48]
	str	x20, [sp]
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_18
LBB0_2:
	mov	x0, x19
	bl	_tegra_pcie_enable_slot_regulators
	tbnz	w0, #31, LBB0_6
; %bb.3:
	ldr	w0, [x19]
	bl	_regulator_enable
	tbnz	w0, #31, LBB0_7
; %bb.4:
	ldr	w0, [x19, #4]
	bl	_clk_prepare_enable
	cbz	w0, LBB0_8
; %bb.5:
	mov	x20, x0
	ldr	w0, [x19, #48]
Lloh2:
	adrp	x1, l_.str.2@PAGE
Lloh3:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	b	LBB0_15
LBB0_6:
	mov	x20, x0
	b	LBB0_17
LBB0_7:
	mov	x20, x0
	ldr	w0, [x19, #48]
Lloh4:
	adrp	x1, l_.str.1@PAGE
Lloh5:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	b	LBB0_16
LBB0_8:
	ldr	w0, [x19, #8]
	bl	_reset_control_deassert
	cbz	w0, LBB0_10
; %bb.9:
	mov	x20, x0
	ldr	w0, [x19, #48]
Lloh6:
	adrp	x1, l_.str.3@PAGE
Lloh7:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	b	LBB0_14
LBB0_10:
Lloh8:
	adrp	x22, _APPL_CTRL@GOTPAGE
Lloh9:
	ldr	x22, [x22, _APPL_CTRL@GOTPAGEOFF]
	cbz	w21, LBB0_12
; %bb.11:
	ldr	w1, [x22]
	mov	x0, x19
	bl	_appl_readl
Lloh10:
	adrp	x8, _APPL_CTRL_HW_HOT_RST_MODE_MASK@GOTPAGE
Lloh11:
	ldr	x8, [x8, _APPL_CTRL_HW_HOT_RST_MODE_MASK@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
Lloh13:
	adrp	x9, _APPL_CTRL_HW_HOT_RST_MODE_SHIFT@GOTPAGE
Lloh14:
	ldr	x9, [x9, _APPL_CTRL_HW_HOT_RST_MODE_SHIFT@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
Lloh16:
	adrp	x9, _APPL_CTRL_HW_HOT_RST_EN@GOTPAGE
Lloh17:
	ldr	x9, [x9, _APPL_CTRL_HW_HOT_RST_EN@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x22]
	mov	x0, x19
	bl	_appl_writel
LBB0_12:
	mov	x0, x19
	bl	_tegra_pcie_enable_phy
	cbz	w0, LBB0_19
; %bb.13:
	mov	x20, x0
	ldr	w0, [x19, #48]
Lloh19:
	adrp	x1, l_.str.4@PAGE
Lloh20:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x2, x20
	bl	_dev_err
	ldr	w0, [x19, #8]
	bl	_reset_control_assert
LBB0_14:
	ldr	w0, [x19, #4]
	bl	_clk_disable_unprepare
LBB0_15:
	ldr	w0, [x19]
	bl	_regulator_disable
LBB0_16:
	mov	x0, x19
	bl	_tegra_pcie_disable_slot_regulators
LBB0_17:
	mov	x0, x19
	mov	w1, #0
	bl	_tegra_pcie_bpmp_set_ctrl_state
LBB0_18:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_19:
	ldr	x8, [x19, #40]
Lloh21:
	adrp	x9, _APPL_CFG_BASE_ADDR_MASK@GOTPAGE
Lloh22:
	ldr	x9, [x9, _APPL_CFG_BASE_ADDR_MASK@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh23:
	ldr	w9, [x9]
	and	w1, w9, w8
Lloh24:
	adrp	x8, _APPL_CFG_BASE_ADDR@GOTPAGE
Lloh25:
	ldr	x8, [x8, _APPL_CFG_BASE_ADDR@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_appl_writel
Lloh27:
	adrp	x8, _APPL_DM_TYPE_RP@GOTPAGE
Lloh28:
	ldr	x8, [x8, _APPL_DM_TYPE_RP@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
Lloh30:
	adrp	x8, _APPL_DM_TYPE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _APPL_DM_TYPE@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_appl_writel
Lloh33:
	adrp	x8, _APPL_CFG_SLCG_OVERRIDE@GOTPAGE
Lloh34:
	ldr	x8, [x8, _APPL_CFG_SLCG_OVERRIDE@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_appl_writel
	ldr	w1, [x22]
	mov	x0, x19
	bl	_appl_readl
Lloh36:
	adrp	x8, _APPL_CTRL_SYS_PRE_DET_STATE@GOTPAGE
Lloh37:
	ldr	x8, [x8, _APPL_CTRL_SYS_PRE_DET_STATE@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x22]
	mov	x0, x19
	bl	_appl_writel
Lloh39:
	adrp	x20, _APPL_CFG_MISC@GOTPAGE
Lloh40:
	ldr	x20, [x20, _APPL_CFG_MISC@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_appl_readl
Lloh41:
	adrp	x8, _APPL_CFG_MISC_ARCACHE_VAL@GOTPAGE
Lloh42:
	ldr	x8, [x8, _APPL_CFG_MISC_ARCACHE_VAL@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
Lloh44:
	adrp	x9, _APPL_CFG_MISC_ARCACHE_SHIFT@GOTPAGE
Lloh45:
	ldr	x9, [x9, _APPL_CFG_MISC_ARCACHE_SHIFT@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	orr	w1, w8, w0
	ldr	w2, [x20]
	mov	x0, x19
	bl	_appl_writel
	ldr	w8, [x19, #12]
	cbnz	w8, LBB0_21
; %bb.20:
Lloh47:
	adrp	x20, _APPL_PINMUX@GOTPAGE
Lloh48:
	ldr	x20, [x20, _APPL_PINMUX@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_appl_readl
Lloh49:
	adrp	x8, _APPL_PINMUX_CLKREQ_OUT_OVRD_EN@GOTPAGE
Lloh50:
	ldr	x8, [x8, _APPL_PINMUX_CLKREQ_OUT_OVRD_EN@GOTPAGEOFF]
Lloh51:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh52:
	adrp	x9, _APPL_PINMUX_CLKREQ_OUT_OVRD@GOTPAGE
Lloh53:
	ldr	x9, [x9, _APPL_PINMUX_CLKREQ_OUT_OVRD@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	orr	w1, w8, w9
	ldr	w2, [x20]
	mov	x0, x19
	bl	_appl_writel
LBB0_21:
	ldr	x8, [x19, #32]
Lloh55:
	adrp	x9, _APPL_CFG_IATU_DMA_BASE_ADDR_MASK@GOTPAGE
Lloh56:
	ldr	x9, [x9, _APPL_CFG_IATU_DMA_BASE_ADDR_MASK@GOTPAGEOFF]
	ldr	w8, [x8]
Lloh57:
	ldr	w9, [x9]
	and	w1, w9, w8
Lloh58:
	adrp	x8, _APPL_CFG_IATU_DMA_BASE_ADDR@GOTPAGE
Lloh59:
	ldr	x8, [x8, _APPL_CFG_IATU_DMA_BASE_ADDR@GOTPAGEOFF]
Lloh60:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_appl_writel
	ldr	w0, [x19, #24]
	bl	_reset_control_deassert
	add	x0, x19, #16
Lloh61:
	adrp	x8, _PCI_CAP_ID_EXP@GOTPAGE
Lloh62:
	ldr	x8, [x8, _PCI_CAP_ID_EXP@GOTPAGEOFF]
Lloh63:
	ldr	w1, [x8]
	bl	_dw_pcie_find_capability
	str	w0, [x19, #20]
	ldr	w8, [x19, #12]
	cbnz	w8, LBB0_23
; %bb.22:
	mov	x0, x19
	bl	_disable_aspm_l11
	mov	x0, x19
	bl	_disable_aspm_l12
LBB0_23:
	mov	w20, #0
	b	LBB0_18
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Failed to enable controller %u: %d\n"

l_.str.1:                               ; @.str.1
	.asciz	"Failed to enable regulator: %d\n"

l_.str.2:                               ; @.str.2
	.asciz	"Failed to enable core clock: %d\n"

l_.str.3:                               ; @.str.3
	.asciz	"Failed to deassert core APB reset: %d\n"

	.comm	_APPL_CTRL,4,2                  ; @APPL_CTRL
	.comm	_APPL_CTRL_HW_HOT_RST_MODE_MASK,4,2 ; @APPL_CTRL_HW_HOT_RST_MODE_MASK
	.comm	_APPL_CTRL_HW_HOT_RST_MODE_SHIFT,4,2 ; @APPL_CTRL_HW_HOT_RST_MODE_SHIFT
	.comm	_APPL_CTRL_HW_HOT_RST_EN,4,2    ; @APPL_CTRL_HW_HOT_RST_EN
l_.str.4:                               ; @.str.4
	.asciz	"Failed to enable PHY: %d\n"

	.comm	_APPL_CFG_BASE_ADDR_MASK,4,2    ; @APPL_CFG_BASE_ADDR_MASK
	.comm	_APPL_CFG_BASE_ADDR,4,2         ; @APPL_CFG_BASE_ADDR
	.comm	_APPL_DM_TYPE_RP,4,2            ; @APPL_DM_TYPE_RP
	.comm	_APPL_DM_TYPE,4,2               ; @APPL_DM_TYPE
	.comm	_APPL_CFG_SLCG_OVERRIDE,4,2     ; @APPL_CFG_SLCG_OVERRIDE
	.comm	_APPL_CTRL_SYS_PRE_DET_STATE,4,2 ; @APPL_CTRL_SYS_PRE_DET_STATE
	.comm	_APPL_CFG_MISC,4,2              ; @APPL_CFG_MISC
	.comm	_APPL_CFG_MISC_ARCACHE_VAL,4,2  ; @APPL_CFG_MISC_ARCACHE_VAL
	.comm	_APPL_CFG_MISC_ARCACHE_SHIFT,4,2 ; @APPL_CFG_MISC_ARCACHE_SHIFT
	.comm	_APPL_PINMUX,4,2                ; @APPL_PINMUX
	.comm	_APPL_PINMUX_CLKREQ_OUT_OVRD_EN,4,2 ; @APPL_PINMUX_CLKREQ_OUT_OVRD_EN
	.comm	_APPL_PINMUX_CLKREQ_OUT_OVRD,4,2 ; @APPL_PINMUX_CLKREQ_OUT_OVRD
	.comm	_APPL_CFG_IATU_DMA_BASE_ADDR_MASK,4,2 ; @APPL_CFG_IATU_DMA_BASE_ADDR_MASK
	.comm	_APPL_CFG_IATU_DMA_BASE_ADDR,4,2 ; @APPL_CFG_IATU_DMA_BASE_ADDR
	.comm	_PCI_CAP_ID_EXP,4,2             ; @PCI_CAP_ID_EXP
	.no_dead_strip	_tegra_pcie_config_controller
.subsections_via_symbols
