	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function xgene_phy_ssc_enable
_xgene_phy_ssc_enable:                  ## @xgene_phy_ssc_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_CMU_REG35@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	leaq	-36(%rbp), %r15
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	movl	$98, %esi
	callq	_CMU_REG35_PLL_SSC_MOD_SET
	movl	%eax, -36(%rbp)
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG36@GOTPCREL(%rip), %r12
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movq	%r15, %rcx
	callq	_cmu_rd
	movl	-36(%rbp), %edi
	movl	$30, %esi
	callq	_CMU_REG36_PLL_SSC_VSTEP_SET
	movl	%eax, -36(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_CMU_REG36_PLL_SSC_EN_SET
	movl	%eax, -36(%rbp)
	movl	%eax, %edi
	movl	$1, %esi
	callq	_CMU_REG36_PLL_SSC_DSMSEL_SET
	movl	%eax, -36(%rbp)
	movl	(%r12), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %ecx
	callq	_cmu_wr
	movq	_CMU_REG5@GOTPCREL(%rip), %r15
	movl	(%r15), %edx
	movq	_CMU_REG5_PLL_RESETB_MASK@GOTPCREL(%rip), %r12
	movl	(%r12), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_cmu_clrbits
	movl	(%r15), %edx
	movl	(%r12), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_cmu_setbits
	movq	_CMU_REG32@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_CMU_REG32_FORCE_VCOCAL_START_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_cmu_toggle1to0
	addq	$16, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CMU_REG35,4,2                  ## @CMU_REG35
	.comm	_CMU_REG36,4,2                  ## @CMU_REG36
	.comm	_CMU_REG5,4,2                   ## @CMU_REG5
	.comm	_CMU_REG5_PLL_RESETB_MASK,4,2   ## @CMU_REG5_PLL_RESETB_MASK
	.comm	_CMU_REG32,4,2                  ## @CMU_REG32
	.comm	_CMU_REG32_FORCE_VCOCAL_START_MASK,4,2 ## @CMU_REG32_FORCE_VCOCAL_START_MASK
	.no_dead_strip	_xgene_phy_ssc_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function xgene_phy_ssc_enable
_xgene_phy_ssc_enable:                  ; @xgene_phy_ssc_enable
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	mov	x20, x0
Lloh0:
	adrp	x21, _CMU_REG35@GOTPAGE
Lloh1:
	ldr	x21, [x21, _CMU_REG35@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #98
	bl	_CMU_REG35_PLL_SSC_MOD_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh2:
	adrp	x21, _CMU_REG36@GOTPAGE
Lloh3:
	ldr	x21, [x21, _CMU_REG36@GOTPAGEOFF]
	ldr	w2, [x21]
	add	x3, sp, #12
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_rd
	ldr	w0, [sp, #12]
	mov	w1, #30
	bl	_CMU_REG36_PLL_SSC_VSTEP_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG36_PLL_SSC_EN_SET
	str	w0, [sp, #12]
	mov	w1, #1
	bl	_CMU_REG36_PLL_SSC_DSMSEL_SET
	mov	x3, x0
	str	w0, [sp, #12]
	ldr	w2, [x21]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_wr
Lloh4:
	adrp	x21, _CMU_REG5@GOTPAGE
Lloh5:
	ldr	x21, [x21, _CMU_REG5@GOTPAGEOFF]
	ldr	w2, [x21]
Lloh6:
	adrp	x22, _CMU_REG5_PLL_RESETB_MASK@GOTPAGE
Lloh7:
	ldr	x22, [x22, _CMU_REG5_PLL_RESETB_MASK@GOTPAGEOFF]
	ldr	w3, [x22]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_clrbits
	ldr	w2, [x21]
	ldr	w3, [x22]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_setbits
Lloh8:
	adrp	x8, _CMU_REG32@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CMU_REG32@GOTPAGEOFF]
Lloh10:
	ldr	w2, [x8]
Lloh11:
	adrp	x8, _CMU_REG32_FORCE_VCOCAL_START_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _CMU_REG32_FORCE_VCOCAL_START_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w3, [x8]
	mov	x0, x20
	mov	x1, x19
	bl	_cmu_toggle1to0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_CMU_REG35,4,2                  ; @CMU_REG35
	.comm	_CMU_REG36,4,2                  ; @CMU_REG36
	.comm	_CMU_REG5,4,2                   ; @CMU_REG5
	.comm	_CMU_REG5_PLL_RESETB_MASK,4,2   ; @CMU_REG5_PLL_RESETB_MASK
	.comm	_CMU_REG32,4,2                  ; @CMU_REG32
	.comm	_CMU_REG32_FORCE_VCOCAL_START_MASK,4,2 ; @CMU_REG32_FORCE_VCOCAL_START_MASK
	.no_dead_strip	_xgene_phy_ssc_enable
.subsections_via_symbols
