	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath10k_pci_enable_eeprom
_ath10k_pci_enable_eeprom:              ## @ath10k_pci_enable_eeprom
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_CLOCK_CONTROL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_ath10k_pci_soc_write32
	movq	_GPIO_BASE_ADDRESS@GOTPCREL(%rip), %rcx
	movq	_GPIO_PIN0_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	addq	(%rcx), %rax
	movq	%rcx, %r13
	movq	_QCA9887_1_0_I2C_SDA_GPIO_PIN@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	leaq	(%rax,%rcx,4), %r15
	movq	_QCA9887_1_0_I2C_SDA_PIN_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_GPIO_PIN0_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	movl	%eax, %ebx
	movq	_GPIO_PIN0_PAD_PULL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %r12d
	movl	$1, %edi
	callq	_SM
	orl	%eax, %ebx
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	callq	_ath10k_pci_write32
	movq	_GPIO_PIN0_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	addq	(%r13), %rax
	movq	_QCA9887_1_0_SI_CLK_GPIO_PIN@GOTPCREL(%rip), %r13
	movslq	(%r13), %rcx
	leaq	(%rax,%rcx,4), %r15
	movq	_QCA9887_1_0_SI_CLK_PIN_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_GPIO_PIN0_CONFIG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	movl	%eax, %ebx
	movq	_GPIO_PIN0_PAD_PULL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	%eax, %ebx
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	callq	_ath10k_pci_write32
	movq	_QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_GPIO_BASE_ADDRESS@GOTPCREL(%rip), %rax
	addq	(%rax), %rsi
	movb	(%r13), %cl
	shll	%cl, %r12d
	movq	%r14, %rdi
	movl	%r12d, %edx
	callq	_ath10k_pci_write32
	movq	_SI_BASE_ADDRESS@GOTPCREL(%rip), %rax
	movq	_SI_CONFIG_OFFSET@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r15
	addq	(%rax), %r15
	movq	_SI_CONFIG_ERR_INT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	movl	%eax, %r12d
	movq	_SI_CONFIG_BIDIR_OD_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	%eax, %r12d
	movq	_SI_CONFIG_I2C@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	movl	%eax, %r13d
	movq	_SI_CONFIG_POS_SAMPLE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	%eax, %r13d
	orl	%r12d, %r13d
	movq	_SI_CONFIG_INACTIVE_DATA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	movl	%eax, %ebx
	movq	_SI_CONFIG_INACTIVE_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	%eax, %ebx
	movq	_SI_CONFIG_DIVIDER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$8, %edi
	callq	_SM
	orl	%eax, %ebx
	orl	%r13d, %ebx
	movq	%r14, %rdi
	movq	%r15, %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath10k_pci_write32             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CLOCK_CONTROL_OFFSET,4,2       ## @CLOCK_CONTROL_OFFSET
	.comm	_GPIO_BASE_ADDRESS,8,3          ## @GPIO_BASE_ADDRESS
	.comm	_GPIO_PIN0_OFFSET,8,3           ## @GPIO_PIN0_OFFSET
	.comm	_QCA9887_1_0_I2C_SDA_GPIO_PIN,4,2 ## @QCA9887_1_0_I2C_SDA_GPIO_PIN
	.comm	_QCA9887_1_0_I2C_SDA_PIN_CONFIG,4,2 ## @QCA9887_1_0_I2C_SDA_PIN_CONFIG
	.comm	_GPIO_PIN0_CONFIG,4,2           ## @GPIO_PIN0_CONFIG
	.comm	_GPIO_PIN0_PAD_PULL,4,2         ## @GPIO_PIN0_PAD_PULL
	.comm	_QCA9887_1_0_SI_CLK_GPIO_PIN,4,2 ## @QCA9887_1_0_SI_CLK_GPIO_PIN
	.comm	_QCA9887_1_0_SI_CLK_PIN_CONFIG,4,2 ## @QCA9887_1_0_SI_CLK_PIN_CONFIG
	.comm	_QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,8,3 ## @QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS
	.comm	_SI_BASE_ADDRESS,8,3            ## @SI_BASE_ADDRESS
	.comm	_SI_CONFIG_OFFSET,8,3           ## @SI_CONFIG_OFFSET
	.comm	_SI_CONFIG_ERR_INT,4,2          ## @SI_CONFIG_ERR_INT
	.comm	_SI_CONFIG_BIDIR_OD_DATA,4,2    ## @SI_CONFIG_BIDIR_OD_DATA
	.comm	_SI_CONFIG_I2C,4,2              ## @SI_CONFIG_I2C
	.comm	_SI_CONFIG_POS_SAMPLE,4,2       ## @SI_CONFIG_POS_SAMPLE
	.comm	_SI_CONFIG_INACTIVE_DATA,4,2    ## @SI_CONFIG_INACTIVE_DATA
	.comm	_SI_CONFIG_INACTIVE_CLK,4,2     ## @SI_CONFIG_INACTIVE_CLK
	.comm	_SI_CONFIG_DIVIDER,4,2          ## @SI_CONFIG_DIVIDER
	.no_dead_strip	_ath10k_pci_enable_eeprom
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath10k_pci_enable_eeprom
_ath10k_pci_enable_eeprom:              ; @ath10k_pci_enable_eeprom
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x8, _CLOCK_CONTROL_OFFSET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CLOCK_CONTROL_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_ath10k_pci_soc_write32
Lloh3:
	adrp	x22, _GPIO_BASE_ADDRESS@GOTPAGE
Lloh4:
	ldr	x22, [x22, _GPIO_BASE_ADDRESS@GOTPAGEOFF]
	ldr	x8, [x22]
Lloh5:
	adrp	x23, _GPIO_PIN0_OFFSET@GOTPAGE
Lloh6:
	ldr	x23, [x23, _GPIO_PIN0_OFFSET@GOTPAGEOFF]
	ldr	x9, [x23]
	add	x8, x9, x8
Lloh7:
	adrp	x9, _QCA9887_1_0_I2C_SDA_GPIO_PIN@GOTPAGE
Lloh8:
	ldr	x9, [x9, _QCA9887_1_0_I2C_SDA_GPIO_PIN@GOTPAGEOFF]
Lloh9:
	ldrsw	x9, [x9]
	add	x20, x8, x9, lsl #2
Lloh10:
	adrp	x8, _QCA9887_1_0_I2C_SDA_PIN_CONFIG@GOTPAGE
Lloh11:
	ldr	x8, [x8, _QCA9887_1_0_I2C_SDA_PIN_CONFIG@GOTPAGEOFF]
Lloh12:
	ldr	w0, [x8]
Lloh13:
	adrp	x24, _GPIO_PIN0_CONFIG@GOTPAGE
Lloh14:
	ldr	x24, [x24, _GPIO_PIN0_CONFIG@GOTPAGEOFF]
	ldr	w1, [x24]
	bl	_SM
	mov	x21, x0
Lloh15:
	adrp	x25, _GPIO_PIN0_PAD_PULL@GOTPAGE
Lloh16:
	ldr	x25, [x25, _GPIO_PIN0_PAD_PULL@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	w26, #1
	mov	w0, #1
	bl	_SM
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_ath10k_pci_write32
	ldr	x8, [x22]
	ldr	x9, [x23]
	add	x8, x9, x8
Lloh17:
	adrp	x23, _QCA9887_1_0_SI_CLK_GPIO_PIN@GOTPAGE
Lloh18:
	ldr	x23, [x23, _QCA9887_1_0_SI_CLK_GPIO_PIN@GOTPAGEOFF]
	ldrsw	x9, [x23]
	add	x20, x8, x9, lsl #2
Lloh19:
	adrp	x8, _QCA9887_1_0_SI_CLK_PIN_CONFIG@GOTPAGE
Lloh20:
	ldr	x8, [x8, _QCA9887_1_0_SI_CLK_PIN_CONFIG@GOTPAGEOFF]
Lloh21:
	ldr	w0, [x8]
	ldr	w1, [x24]
	bl	_SM
	mov	x21, x0
	ldr	w1, [x25]
	mov	w0, #1
	bl	_SM
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	bl	_ath10k_pci_write32
	ldr	x8, [x22]
Lloh22:
	adrp	x9, _QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS@GOTPAGE
Lloh23:
	ldr	x9, [x9, _QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS@GOTPAGEOFF]
Lloh24:
	ldr	x9, [x9]
	add	x1, x9, x8
	ldr	w8, [x23]
	lsl	w2, w26, w8
	mov	x0, x19
	bl	_ath10k_pci_write32
Lloh25:
	adrp	x8, _SI_BASE_ADDRESS@GOTPAGE
Lloh26:
	ldr	x8, [x8, _SI_BASE_ADDRESS@GOTPAGEOFF]
Lloh27:
	adrp	x9, _SI_CONFIG_OFFSET@GOTPAGE
Lloh28:
	ldr	x9, [x9, _SI_CONFIG_OFFSET@GOTPAGEOFF]
Lloh29:
	ldr	x8, [x8]
Lloh30:
	ldr	x9, [x9]
	add	x20, x9, x8
Lloh31:
	adrp	x8, _SI_CONFIG_ERR_INT@GOTPAGE
Lloh32:
	ldr	x8, [x8, _SI_CONFIG_ERR_INT@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	mov	x21, x0
Lloh34:
	adrp	x8, _SI_CONFIG_BIDIR_OD_DATA@GOTPAGE
Lloh35:
	ldr	x8, [x8, _SI_CONFIG_BIDIR_OD_DATA@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	orr	w21, w0, w21
Lloh37:
	adrp	x8, _SI_CONFIG_I2C@GOTPAGE
Lloh38:
	ldr	x8, [x8, _SI_CONFIG_I2C@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	orr	w21, w21, w0
Lloh40:
	adrp	x8, _SI_CONFIG_POS_SAMPLE@GOTPAGE
Lloh41:
	ldr	x8, [x8, _SI_CONFIG_POS_SAMPLE@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	orr	w21, w21, w0
Lloh43:
	adrp	x8, _SI_CONFIG_INACTIVE_DATA@GOTPAGE
Lloh44:
	ldr	x8, [x8, _SI_CONFIG_INACTIVE_DATA@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	orr	w21, w21, w0
Lloh46:
	adrp	x8, _SI_CONFIG_INACTIVE_CLK@GOTPAGE
Lloh47:
	ldr	x8, [x8, _SI_CONFIG_INACTIVE_CLK@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	orr	w21, w21, w0
Lloh49:
	adrp	x8, _SI_CONFIG_DIVIDER@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SI_CONFIG_DIVIDER@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	mov	w0, #8
	bl	_SM
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_ath10k_pci_write32
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_CLOCK_CONTROL_OFFSET,4,2       ; @CLOCK_CONTROL_OFFSET
	.comm	_GPIO_BASE_ADDRESS,8,3          ; @GPIO_BASE_ADDRESS
	.comm	_GPIO_PIN0_OFFSET,8,3           ; @GPIO_PIN0_OFFSET
	.comm	_QCA9887_1_0_I2C_SDA_GPIO_PIN,4,2 ; @QCA9887_1_0_I2C_SDA_GPIO_PIN
	.comm	_QCA9887_1_0_I2C_SDA_PIN_CONFIG,4,2 ; @QCA9887_1_0_I2C_SDA_PIN_CONFIG
	.comm	_GPIO_PIN0_CONFIG,4,2           ; @GPIO_PIN0_CONFIG
	.comm	_GPIO_PIN0_PAD_PULL,4,2         ; @GPIO_PIN0_PAD_PULL
	.comm	_QCA9887_1_0_SI_CLK_GPIO_PIN,4,2 ; @QCA9887_1_0_SI_CLK_GPIO_PIN
	.comm	_QCA9887_1_0_SI_CLK_PIN_CONFIG,4,2 ; @QCA9887_1_0_SI_CLK_PIN_CONFIG
	.comm	_QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,8,3 ; @QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS
	.comm	_SI_BASE_ADDRESS,8,3            ; @SI_BASE_ADDRESS
	.comm	_SI_CONFIG_OFFSET,8,3           ; @SI_CONFIG_OFFSET
	.comm	_SI_CONFIG_ERR_INT,4,2          ; @SI_CONFIG_ERR_INT
	.comm	_SI_CONFIG_BIDIR_OD_DATA,4,2    ; @SI_CONFIG_BIDIR_OD_DATA
	.comm	_SI_CONFIG_I2C,4,2              ; @SI_CONFIG_I2C
	.comm	_SI_CONFIG_POS_SAMPLE,4,2       ; @SI_CONFIG_POS_SAMPLE
	.comm	_SI_CONFIG_INACTIVE_DATA,4,2    ; @SI_CONFIG_INACTIVE_DATA
	.comm	_SI_CONFIG_INACTIVE_CLK,4,2     ; @SI_CONFIG_INACTIVE_CLK
	.comm	_SI_CONFIG_DIVIDER,4,2          ; @SI_CONFIG_DIVIDER
	.no_dead_strip	_ath10k_pci_enable_eeprom
.subsections_via_symbols
