	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ar9002_hw_spur_mitigate
_ar9002_hw_spur_mitigate:               ## @ar9002_hw_spur_mitigate
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %rbx
	movq	%rdi, %r13
	movq	_AR_NO_SPUR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	%rsi, %rdi
	callq	_IS_CHAN_2GHZ
	movl	%eax, %r15d
	leaq	-64(%rbp), %rdx
	movq	%r13, %rdi
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rsi
	callq	_ath9k_hw_get_channel_centers
	movq	_AR_EEPROM_MODAL_SPURS@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jle	LBB0_1
## %bb.2:
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	movl	-64(%rbp), %r14d
	xorl	%ebx, %ebx
	jmp	LBB0_3
	.p2align	4, 0x90
LBB0_11:                                ##   in Loop: Header=BB0_3 Depth=1
	incl	%ebx
	movq	_AR_EEPROM_MODAL_SPURS@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jge	LBB0_12
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r13), %rax
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%r15d, %edx
	callq	*(%rax)
	movq	_AR_NO_SPUR@GOTPCREL(%rip), %rcx
	cmpl	%eax, (%rcx)
	je	LBB0_12
## %bb.4:                               ##   in Loop: Header=BB0_3 Depth=1
	cltq
	imulq	$1717986919, %rax, %r12         ## imm = 0x66666667
	movq	%r12, %rax
	shrq	$63, %rax
	sarq	$34, %r12
	addl	%eax, %r12d
	movq	_AR_BASE_FREQ_2GHZ@GOTPCREL(%rip), %rax
	testl	%r15d, %r15d
	jne	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	_AR_BASE_FREQ_5GHZ@GOTPCREL(%rip), %rax
LBB0_6:                                 ##   in Loop: Header=BB0_3 Depth=1
	addl	(%rax), %r12d
	subl	%r14d, %r12d
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_IS_CHAN_HT40
	testq	%rax, %rax
	je	LBB0_8
## %bb.7:                               ##   in Loop: Header=BB0_3 Depth=1
	movq	_AR_SPUR_FEEQ_BOUND_HT40@GOTPCREL(%rip), %rax
	jmp	LBB0_9
	.p2align	4, 0x90
LBB0_8:                                 ##   in Loop: Header=BB0_3 Depth=1
	movq	_AR_SPUR_FEEQ_BOUND_HT20@GOTPCREL(%rip), %rax
LBB0_9:                                 ##   in Loop: Header=BB0_3 Depth=1
	movl	(%rax), %eax
	movl	%eax, %ecx
	negl	%ecx
	cmpl	%ecx, %r12d
	jle	LBB0_11
## %bb.10:                              ##   in Loop: Header=BB0_3 Depth=1
	cmpl	%eax, %r12d
	jge	LBB0_11
	jmp	LBB0_13
LBB0_12:
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	movl	%eax, %r12d
	jmp	LBB0_13
LBB0_1:
	movl	%r14d, %r12d
LBB0_13:
	movq	_AR_NO_SPUR@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_AR_PHY_FORCE_CLKEN_CCK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR_PHY_FORCE_CLKEN_CCK_MRC_MUX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_REG_CLR_BIT
	cmpl	%r12d, %ebx
	je	LBB0_20
## %bb.14:
	movl	%r12d, %eax
	shll	$6, %eax
	leal	(%rax,%rax,4), %r14d
	xorl	%edi, %edi
	callq	_AR_PHY_TIMING_CTRL4
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_REG_READ
	movl	%eax, %ebx
	movq	%r13, %rdi
	callq	_ENABLE_REGWRITE_BUFFER
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI@GOTPCREL(%rip), %rax
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER@GOTPCREL(%rip), %rcx
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK@GOTPCREL(%rip), %rdx
	movq	_AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK@GOTPCREL(%rip), %rsi
	orl	(%rax), %ebx
	orl	(%rcx), %ebx
	orl	(%rdx), %ebx
	orl	(%rsi), %ebx
	xorl	%edi, %edi
	callq	_AR_PHY_TIMING_CTRL4
	movq	%r13, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movq	_AR_PHY_SPUR_REG_MASK_RATE_CNTL@GOTPCREL(%rip), %rax
	movq	_AR_PHY_SPUR_REG_ENABLE_MASK_PPM@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_AR_PHY_SPUR_REG_MASK_RATE_SELECT@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SPUR_RSSI_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_AR_PHY_SPUR_REG_SPUR_RSSI_THRESH@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	%eax, %ebx
	movq	_AR_PHY_SPUR_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movq	-56(%rbp), %rdi                 ## 8-byte Reload
	callq	_IS_CHAN_HT40
	testq	%rax, %rax
	movl	%r14d, -44(%rbp)                ## 4-byte Spill
	je	LBB0_15
## %bb.16:
	testl	%r12d, %r12d
	js	LBB0_17
## %bb.18:
	movl	$0, -48(%rbp)                   ## 4-byte Folded Spill
	leal	-10(%r12), %ebx
	jmp	LBB0_19
LBB0_15:
	movl	$0, -48(%rbp)                   ## 4-byte Folded Spill
	movl	%r12d, %ebx
	jmp	LBB0_19
LBB0_17:
	leal	10(%r12), %ebx
	movl	$1, -48(%rbp)                   ## 4-byte Folded Spill
LBB0_19:
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	callq	_IS_CHAN_HT40
	testq	%rax, %rax
	sete	%cl
	orb	$18, %cl
	shll	%cl, %r12d
	movslq	%r12d, %rax
	imulq	$1717986919, %rax, %r15         ## imm = 0x66666667
	movq	%r15, %rax
	shrq	$63, %rax
	sarq	$34, %r15
	addl	%eax, %r15d
	movq	_AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPCREL(%rip), %rax
	andl	(%rax), %r15d
	movq	%r14, %rdi
	callq	_IS_CHAN_2GHZ
	xorl	%ecx, %ecx
	testl	%eax, %eax
	setne	%cl
	leal	40(,%rcx,4), %ecx
	shll	$11, %ebx
	movl	%ebx, %eax
	cltd
	idivl	%ecx
	andl	$1023, %eax                     ## imm = 0x3FF
	movq	_AR_PHY_TIMING11_USE_SPUR_IN_AGC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	movq	_AR_PHY_TIMING11_SPUR_FREQ_SD@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edi
	callq	_SM
	movl	%eax, %r12d
	movq	_AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, %edi
	callq	_SM
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	_AR_PHY_TIMING11@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	movl	%ebx, %edx
	callq	_REG_WRITE
	movq	_AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	shll	%cl, %edx
	movq	_AR_PHY_SFCORR_EXT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r13, %rdi
	callq	_REG_WRITE
	movq	%r13, %rdi
	movq	%r14, %rsi
	movl	-44(%rbp), %edx                 ## 4-byte Reload
	callq	_ar5008_hw_cmn_spur_mitigate
	movq	%r13, %rdi
	callq	_REGWRITE_BUFFER_FLUSH
LBB0_20:
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR_NO_SPUR,4,2                 ## @AR_NO_SPUR
	.comm	_AR_EEPROM_MODAL_SPURS,4,2      ## @AR_EEPROM_MODAL_SPURS
	.comm	_AR_BASE_FREQ_2GHZ,4,2          ## @AR_BASE_FREQ_2GHZ
	.comm	_AR_BASE_FREQ_5GHZ,4,2          ## @AR_BASE_FREQ_5GHZ
	.comm	_AR_SPUR_FEEQ_BOUND_HT40,4,2    ## @AR_SPUR_FEEQ_BOUND_HT40
	.comm	_AR_SPUR_FEEQ_BOUND_HT20,4,2    ## @AR_SPUR_FEEQ_BOUND_HT20
	.comm	_AR_PHY_FORCE_CLKEN_CCK,4,2     ## @AR_PHY_FORCE_CLKEN_CCK
	.comm	_AR_PHY_FORCE_CLKEN_CCK_MRC_MUX,4,2 ## @AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK,4,2 ## @AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_CNTL,4,2 ## @AR_PHY_SPUR_REG_MASK_RATE_CNTL
	.comm	_AR_PHY_SPUR_REG_ENABLE_MASK_PPM,4,2 ## @AR_PHY_SPUR_REG_ENABLE_MASK_PPM
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_SELECT,4,2 ## @AR_PHY_SPUR_REG_MASK_RATE_SELECT
	.comm	_AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI,4,2 ## @AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
	.comm	_SPUR_RSSI_THRESH,4,2           ## @SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG_SPUR_RSSI_THRESH,4,2 ## @AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG,4,2            ## @AR_PHY_SPUR_REG
	.comm	_AR_PHY_TIMING11_SPUR_DELTA_PHASE,4,2 ## @AR_PHY_TIMING11_SPUR_DELTA_PHASE
	.comm	_AR_PHY_TIMING11_USE_SPUR_IN_AGC,4,2 ## @AR_PHY_TIMING11_USE_SPUR_IN_AGC
	.comm	_AR_PHY_TIMING11_SPUR_FREQ_SD,4,2 ## @AR_PHY_TIMING11_SPUR_FREQ_SD
	.comm	_AR_PHY_TIMING11,4,2            ## @AR_PHY_TIMING11
	.comm	_AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S,4,2 ## @AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
	.comm	_AR_PHY_SFCORR_EXT,4,2          ## @AR_PHY_SFCORR_EXT
	.no_dead_strip	_ar9002_hw_spur_mitigate
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ar9002_hw_spur_mitigate
_ar9002_hw_spur_mitigate:               ; @ar9002_hw_spur_mitigate
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _AR_NO_SPUR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AR_NO_SPUR@GOTPAGEOFF]
Lloh2:
	ldr	w23, [x8]
	mov	x0, x1
	bl	_IS_CHAN_2GHZ
	mov	x21, x0
	add	x2, sp, #8
	mov	x0, x19
	mov	x24, x20
	mov	x1, x20
	bl	_ath9k_hw_get_channel_centers
Lloh3:
	adrp	x26, _AR_EEPROM_MODAL_SPURS@GOTPAGE
Lloh4:
	ldr	x26, [x26, _AR_EEPROM_MODAL_SPURS@GOTPAGEOFF]
	ldr	w8, [x26]
	cmp	w8, #1
	b.lt	LBB0_9
; %bb.1:
	str	w23, [sp, #4]                   ; 4-byte Folded Spill
	mov	w22, #0
	ldr	w27, [sp, #8]
	mov	w28, #26215
	movk	w28, #26214, lsl #16
Lloh5:
	adrp	x25, _AR_BASE_FREQ_5GHZ@GOTPAGE
Lloh6:
	ldr	x25, [x25, _AR_BASE_FREQ_5GHZ@GOTPAGEOFF]
Lloh7:
	adrp	x20, _AR_BASE_FREQ_2GHZ@GOTPAGE
Lloh8:
	ldr	x20, [x20, _AR_BASE_FREQ_2GHZ@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	x8, [x8]
	mov	x0, x19
	mov	x1, x22
	mov	x2, x21
	blr	x8
Lloh9:
	adrp	x8, _AR_NO_SPUR@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AR_NO_SPUR@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
	cmp	w8, w0
	b.eq	LBB0_8
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	smull	x8, w0, w28
	lsr	x9, x8, #63
	asr	x8, x8, #34
	cmp	w21, #0
	csel	x10, x25, x20, eq
	ldr	w10, [x10]
	add	w8, w8, w9
	add	w8, w10, w8
	sub	w23, w8, w27
	mov	x0, x24
	bl	_IS_CHAN_HT40
	cbz	x0, LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
Lloh12:
	adrp	x8, _AR_SPUR_FEEQ_BOUND_HT40@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AR_SPUR_FEEQ_BOUND_HT40@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:                                 ;   in Loop: Header=BB0_2 Depth=1
Lloh14:
	adrp	x8, _AR_SPUR_FEEQ_BOUND_HT20@GOTPAGE
Lloh15:
	ldr	x8, [x8, _AR_SPUR_FEEQ_BOUND_HT20@GOTPAGEOFF]
LBB0_6:                                 ;   in Loop: Header=BB0_2 Depth=1
	ldr	w8, [x8]
	neg	w9, w8
	cmp	w23, w9
	ccmp	w23, w8, #0, gt
	b.lt	LBB0_9
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	add	w22, w22, #1
	ldr	w8, [x26]
	cmp	w22, w8
	b.lt	LBB0_2
LBB0_8:
	ldr	w23, [sp, #4]                   ; 4-byte Folded Reload
LBB0_9:
Lloh16:
	adrp	x8, _AR_NO_SPUR@GOTPAGE
Lloh17:
	ldr	x8, [x8, _AR_NO_SPUR@GOTPAGEOFF]
Lloh18:
	ldr	w20, [x8]
Lloh19:
	adrp	x8, _AR_PHY_FORCE_CLKEN_CCK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _AR_PHY_FORCE_CLKEN_CCK@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
Lloh22:
	adrp	x8, _AR_PHY_FORCE_CLKEN_CCK_MRC_MUX@GOTPAGE
Lloh23:
	ldr	x8, [x8, _AR_PHY_FORCE_CLKEN_CCK_MRC_MUX@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_REG_CLR_BIT
	cmp	w20, w23
	b.eq	LBB0_11
; %bb.10:
	add	w8, w23, w23, lsl #2
	lsl	w21, w8, #6
	mov	w0, #0
	bl	_AR_PHY_TIMING_CTRL4
	mov	x1, x0
	mov	x0, x19
	bl	_REG_READ
	mov	x22, x0
	mov	x0, x19
	bl	_ENABLE_REGWRITE_BUFFER
Lloh25:
	adrp	x8, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI@GOTPAGEOFF]
Lloh27:
	adrp	x9, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER@GOTPAGE
Lloh28:
	ldr	x9, [x9, _AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
Lloh30:
	ldr	w9, [x9]
Lloh31:
	adrp	x10, _AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK@GOTPAGE
Lloh32:
	ldr	x10, [x10, _AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK@GOTPAGEOFF]
Lloh33:
	adrp	x11, _AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK@GOTPAGE
Lloh34:
	ldr	x11, [x11, _AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK@GOTPAGEOFF]
Lloh35:
	ldr	w10, [x10]
Lloh36:
	ldr	w11, [x11]
	orr	w8, w8, w22
	orr	w8, w8, w9
	orr	w8, w8, w10
	orr	w22, w8, w11
	mov	w0, #0
	bl	_AR_PHY_TIMING_CTRL4
	mov	x1, x0
	mov	x0, x19
	mov	x2, x22
	bl	_REG_WRITE
Lloh37:
	adrp	x8, _AR_PHY_SPUR_REG_MASK_RATE_CNTL@GOTPAGE
Lloh38:
	ldr	x8, [x8, _AR_PHY_SPUR_REG_MASK_RATE_CNTL@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
Lloh40:
	adrp	x9, _AR_PHY_SPUR_REG_ENABLE_MASK_PPM@GOTPAGE
Lloh41:
	ldr	x9, [x9, _AR_PHY_SPUR_REG_ENABLE_MASK_PPM@GOTPAGEOFF]
Lloh42:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh43:
	adrp	x9, _AR_PHY_SPUR_REG_MASK_RATE_SELECT@GOTPAGE
Lloh44:
	ldr	x9, [x9, _AR_PHY_SPUR_REG_MASK_RATE_SELECT@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh46:
	adrp	x9, _AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI@GOTPAGE
Lloh47:
	ldr	x9, [x9, _AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI@GOTPAGEOFF]
Lloh48:
	ldr	w9, [x9]
	orr	w20, w8, w9
Lloh49:
	adrp	x8, _SPUR_RSSI_THRESH@GOTPAGE
Lloh50:
	ldr	x8, [x8, _SPUR_RSSI_THRESH@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
Lloh52:
	adrp	x8, _AR_PHY_SPUR_REG_SPUR_RSSI_THRESH@GOTPAGE
Lloh53:
	ldr	x8, [x8, _AR_PHY_SPUR_REG_SPUR_RSSI_THRESH@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	bl	_SM
	orr	w2, w20, w0
Lloh55:
	adrp	x8, _AR_PHY_SPUR_REG@GOTPAGE
Lloh56:
	ldr	x8, [x8, _AR_PHY_SPUR_REG@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_WRITE
	mov	x25, x24
	mov	x0, x24
	bl	_IS_CHAN_HT40
	sub	w8, w23, #10
	add	w9, w23, #10
	mov	w10, #1
	tst	w23, #0x80000000
	csel	w10, wzr, w10, eq
	csel	w8, w8, w9, eq
	cmp	x0, #0
	csel	w24, wzr, w10, eq
	csel	w20, w23, w8, eq
	mov	x0, x25
	bl	_IS_CHAN_HT40
	cmp	x0, #0
	mov	w8, #18
	cinc	w8, w8, eq
	lsl	w8, w23, w8
	mov	w9, #26215
	movk	w9, #26214, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #63
	asr	x8, x8, #34
Lloh58:
	adrp	x23, _AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPAGE
Lloh59:
	ldr	x23, [x23, _AR_PHY_TIMING11_SPUR_DELTA_PHASE@GOTPAGEOFF]
	ldr	w10, [x23]
	add	w8, w8, w9
	and	w22, w10, w8
	mov	x0, x25
	bl	_IS_CHAN_2GHZ
	mov	w8, #44
	mov	w9, #40
	cmp	w0, #0
	csel	w8, w9, w8, eq
	lsl	w9, w20, #11
	sdiv	w8, w9, w8
	and	w0, w8, #0x3ff
Lloh60:
	adrp	x8, _AR_PHY_TIMING11_USE_SPUR_IN_AGC@GOTPAGE
Lloh61:
	ldr	x8, [x8, _AR_PHY_TIMING11_USE_SPUR_IN_AGC@GOTPAGEOFF]
Lloh62:
	ldr	w20, [x8]
Lloh63:
	adrp	x8, _AR_PHY_TIMING11_SPUR_FREQ_SD@GOTPAGE
Lloh64:
	ldr	x8, [x8, _AR_PHY_TIMING11_SPUR_FREQ_SD@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	bl	_SM
	orr	w20, w0, w20
	ldr	w1, [x23]
	mov	x0, x22
	bl	_SM
	orr	w2, w20, w0
Lloh66:
	adrp	x8, _AR_PHY_TIMING11@GOTPAGE
Lloh67:
	ldr	x8, [x8, _AR_PHY_TIMING11@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_WRITE
Lloh69:
	adrp	x8, _AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S@GOTPAGE
Lloh70:
	ldr	x8, [x8, _AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	lsl	w2, w24, w8
Lloh72:
	adrp	x8, _AR_PHY_SFCORR_EXT@GOTPAGE
Lloh73:
	ldr	x8, [x8, _AR_PHY_SFCORR_EXT@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_REG_WRITE
	mov	x0, x19
	mov	x1, x25
	mov	x2, x21
	bl	_ar5008_hw_cmn_spur_mitigate
	mov	x0, x19
	bl	_REGWRITE_BUFFER_FLUSH
LBB0_11:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh35
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_AR_NO_SPUR,4,2                 ; @AR_NO_SPUR
	.comm	_AR_EEPROM_MODAL_SPURS,4,2      ; @AR_EEPROM_MODAL_SPURS
	.comm	_AR_BASE_FREQ_2GHZ,4,2          ; @AR_BASE_FREQ_2GHZ
	.comm	_AR_BASE_FREQ_5GHZ,4,2          ; @AR_BASE_FREQ_5GHZ
	.comm	_AR_SPUR_FEEQ_BOUND_HT40,4,2    ; @AR_SPUR_FEEQ_BOUND_HT40
	.comm	_AR_SPUR_FEEQ_BOUND_HT20,4,2    ; @AR_SPUR_FEEQ_BOUND_HT20
	.comm	_AR_PHY_FORCE_CLKEN_CCK,4,2     ; @AR_PHY_FORCE_CLKEN_CCK
	.comm	_AR_PHY_FORCE_CLKEN_CCK_MRC_MUX,4,2 ; @AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
	.comm	_AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK,4,2 ; @AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_CNTL,4,2 ; @AR_PHY_SPUR_REG_MASK_RATE_CNTL
	.comm	_AR_PHY_SPUR_REG_ENABLE_MASK_PPM,4,2 ; @AR_PHY_SPUR_REG_ENABLE_MASK_PPM
	.comm	_AR_PHY_SPUR_REG_MASK_RATE_SELECT,4,2 ; @AR_PHY_SPUR_REG_MASK_RATE_SELECT
	.comm	_AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI,4,2 ; @AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
	.comm	_SPUR_RSSI_THRESH,4,2           ; @SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG_SPUR_RSSI_THRESH,4,2 ; @AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
	.comm	_AR_PHY_SPUR_REG,4,2            ; @AR_PHY_SPUR_REG
	.comm	_AR_PHY_TIMING11_SPUR_DELTA_PHASE,4,2 ; @AR_PHY_TIMING11_SPUR_DELTA_PHASE
	.comm	_AR_PHY_TIMING11_USE_SPUR_IN_AGC,4,2 ; @AR_PHY_TIMING11_USE_SPUR_IN_AGC
	.comm	_AR_PHY_TIMING11_SPUR_FREQ_SD,4,2 ; @AR_PHY_TIMING11_SPUR_FREQ_SD
	.comm	_AR_PHY_TIMING11,4,2            ; @AR_PHY_TIMING11
	.comm	_AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S,4,2 ; @AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
	.comm	_AR_PHY_SFCORR_EXT,4,2          ; @AR_PHY_SFCORR_EXT
	.no_dead_strip	_ar9002_hw_spur_mitigate
.subsections_via_symbols
