	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_irq_msix_handler      ## -- Begin function iwl_pcie_irq_msix_handler
	.p2align	4, 0x90
_iwl_pcie_irq_msix_handler:             ## @iwl_pcie_irq_msix_handler
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rsi, %r12
	movq	%rsi, %rdi
	callq	_iwl_pcie_get_trans_pcie
	movq	%rax, %rbx
	movq	72(%rax), %r15
	movq	%r15, %rdi
	callq	_lock_map_acquire
	movq	%rbx, -48(%rbp)                 ## 8-byte Spill
	addq	$40, %rbx
	movq	%rbx, %rdi
	callq	_spin_lock
	movq	_CSR_MSIX_FH_INT_CAUSES_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	movl	%eax, %r13d
	movq	_CSR_MSIX_HW_INT_CAUSES_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	movl	%eax, %r14d
	movq	_CSR_MSIX_FH_INT_CAUSES_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r13d, %edx
	callq	_iwl_write32
	movq	_CSR_MSIX_HW_INT_CAUSES_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_iwl_write32
	movq	%rbx, %rdi
	callq	_spin_unlock
	movl	16(%r15), %edi
	movq	%r12, %rsi
	movl	$1, %edx
	movl	%r13d, %ecx
	movl	%r14d, %r8d
	callq	_trace_iwlwifi_dev_irq_msix
	xorl	%edi, %edi
	movl	%r14d, %eax
	orl	%r13d, %eax
	sete	%dil
	callq	_unlikely
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	leaq	L_.str(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	_IRQ_NONE@GOTPCREL(%rip), %rbx
	jmp	LBB0_42
LBB0_2:
	movq	_IWL_DL_ISR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_iwl_have_debug_level
	testq	%rax, %rax
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	je	LBB0_5
## %bb.3:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	(%rax), %ebx
	movq	_CSR_MSIX_FH_INT_MASK_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	leaq	L_.str.1(%rip), %rsi
	movq	%r15, %rdi
	movl	%r13d, %edx
	movl	%ebx, %ecx
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	%eax, %r8d
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movl	(%rbx), %eax
	notl	%eax
	movl	%r13d, %edx
	andl	%eax, %edx
	je	LBB0_5
## %bb.4:
	leaq	L_.str.2(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
LBB0_5:
	movl	%r13d, %eax
	movl	(%rbx), %r13d
	andl	%eax, %r13d
	movl	4(%rbx), %eax
	movq	_IWL_SHARED_IRQ_NON_RX@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_8
## %bb.6:
	movq	_MSIX_FH_INT_CAUSES_Q0@GOTPCREL(%rip), %rcx
	testl	%r13d, (%rcx)
	je	LBB0_8
## %bb.7:
	xorl	%eax, %eax
	callq	_local_bh_disable
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	_iwl_pcie_rx_handle
	xorl	%eax, %eax
	callq	_local_bh_enable
	movl	4(%rbx), %eax
LBB0_8:
	movq	_IWL_SHARED_IRQ_FIRST_RSS@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_11
## %bb.9:
	movq	_MSIX_FH_INT_CAUSES_Q1@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_11
## %bb.10:
	xorl	%eax, %eax
	callq	_local_bh_disable
	movq	%r15, %rdi
	movl	$1, %esi
	callq	_iwl_pcie_rx_handle
	xorl	%eax, %eax
	callq	_local_bh_enable
LBB0_11:
	movq	_MSIX_FH_INT_CAUSES_D2S_CH0_NUM@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	je	LBB0_13
## %bb.12:
	leaq	L_.str.3(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	incl	64(%rbx)
	movl	$1, 8(%rbx)
	leaq	36(%rbx), %rdi
	callq	_wake_up
LBB0_13:
	movq	_MSIX_FH_INT_CAUSES_FH_ERR@GOTPCREL(%rip), %rax
	testl	%r13d, (%rax)
	jne	LBB0_16
## %bb.14:
	movq	_MSIX_HW_INT_CAUSES_REG_SW_ERR@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	jne	LBB0_16
## %bb.15:
	movq	_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_17
LBB0_16:
	leaq	L_.str.4(%rip), %rsi
	movq	%r15, %rdi
	movl	%r13d, %edx
	xorl	%eax, %eax
	callq	_IWL_ERR
	incl	52(%rbx)
	movq	%r15, %rdi
	callq	_iwl_pcie_irq_handle_error
LBB0_17:
	movq	_IWL_DL_ISR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_iwl_have_debug_level
	testq	%rax, %rax
	je	LBB0_20
## %bb.18:
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movl	12(%rax), %ebx
	movq	_CSR_MSIX_HW_INT_MASK_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	leaq	L_.str.5(%rip), %rsi
	movq	%r15, %rdi
	movl	%r14d, %edx
	movl	%ebx, %ecx
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	movl	%eax, %r8d
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movl	12(%rbx), %eax
	notl	%eax
	movl	%r14d, %edx
	andl	%eax, %edx
	je	LBB0_20
## %bb.19:
	leaq	L_.str.6(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
LBB0_20:
	movl	%r14d, %eax
	movl	12(%rbx), %r14d
	andl	%eax, %r14d
	movq	_MSIX_HW_INT_CAUSES_REG_ALIVE@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_23
## %bb.21:
	leaq	L_.str.7(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	incl	60(%rbx)
	movq	8(%r15), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_23
## %bb.22:
	movl	32(%rbx), %esi
	movq	%r15, %rdi
	callq	_iwl_pcie_rxmq_restock
LBB0_23:
	movq	8(%r15), %rax
	movq	(%rax), %rax
	movq	_IWL_DEVICE_FAMILY_22560@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_27
## %bb.24:
	movq	_MSIX_HW_INT_CAUSES_REG_IPC@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_27
## %bb.25:
	movq	_CSR_IML_RESP_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	movl	%eax, %ebx
	leaq	L_.str.8(%rip), %rsi
	movq	%r15, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	_IWL_IMAGE_RESP_FAIL@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jne	LBB0_32
## %bb.26:
	incl	52(%rbx)
	movq	%r15, %rdi
	callq	_iwl_pcie_irq_handle_error
	jmp	LBB0_32
LBB0_27:
	movq	_MSIX_HW_INT_CAUSES_REG_WAKEUP@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_32
## %bb.28:
	movq	24(%rbx), %rax
	movl	(%rax), %edi
	callq	_le32_to_cpu
	movq	_IWL_D3_SLEEP_STATUS_SUSPEND@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_30
## %bb.29:
	movq	_IWL_D3_SLEEP_STATUS_RESUME@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_30
## %bb.31:
	leaq	L_.str.10(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	%r15, %rdi
	callq	_iwl_pcie_rxq_check_wrptr
	movq	%r15, %rdi
	callq	_iwl_pcie_txq_check_wrptrs
	incl	56(%rbx)
	jmp	LBB0_32
LBB0_30:
	leaq	L_.str.9(%rip), %rsi
	movq	%r15, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movl	$1, 16(%rbx)
	movq	%rbx, %rdi
	addq	$20, %rdi
	callq	_wake_up
LBB0_32:
	movq	_MSIX_HW_INT_CAUSES_REG_IML@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_35
## %bb.33:
	movq	_CSR_IML_RESP_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_iwl_read32
	movl	%eax, %ebx
	leaq	L_.str.8(%rip), %rsi
	movq	%r15, %rdi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_IWL_DEBUG_ISR
	movq	_IWL_IMAGE_RESP_FAIL@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	movq	-48(%rbp), %rbx                 ## 8-byte Reload
	jne	LBB0_35
## %bb.34:
	incl	52(%rbx)
	movq	%r15, %rdi
	callq	_iwl_pcie_irq_handle_error
LBB0_35:
	movq	_MSIX_HW_INT_CAUSES_REG_CT_KILL@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_37
## %bb.36:
	leaq	L_.str.11(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_ERR
	incl	48(%rbx)
LBB0_37:
	movq	_MSIX_HW_INT_CAUSES_REG_RF_KILL@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_39
## %bb.38:
	movq	%r15, %rdi
	callq	_iwl_pcie_handle_rfkill_irq
LBB0_39:
	movq	_MSIX_HW_INT_CAUSES_REG_HW_ERR@GOTPCREL(%rip), %rax
	testl	%r14d, (%rax)
	je	LBB0_41
## %bb.40:
	leaq	L_.str.12(%rip), %rsi
	movq	%r15, %rdi
	xorl	%eax, %eax
	callq	_IWL_ERR
	incl	44(%rbx)
	movl	$1, 4(%r15)
	movq	%r15, %rdi
	callq	_iwl_pcie_irq_handle_error
LBB0_41:
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	_iwl_pcie_clear_irq
	movq	_IRQ_HANDLED@GOTPCREL(%rip), %rbx
LBB0_42:
	movq	%r15, %rdi
	callq	_lock_map_release
	movl	(%rbx), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CSR_MSIX_FH_INT_CAUSES_AD,4,2  ## @CSR_MSIX_FH_INT_CAUSES_AD
	.comm	_CSR_MSIX_HW_INT_CAUSES_AD,4,2  ## @CSR_MSIX_HW_INT_CAUSES_AD
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Ignore interrupt, inta == 0\n"

	.comm	_IRQ_NONE,4,2                   ## @IRQ_NONE
	.comm	_IWL_DL_ISR,4,2                 ## @IWL_DL_ISR
L_.str.1:                               ## @.str.1
	.asciz	"ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n"

	.comm	_CSR_MSIX_FH_INT_MASK_AD,4,2    ## @CSR_MSIX_FH_INT_MASK_AD
L_.str.2:                               ## @.str.2
	.asciz	"We got a masked interrupt (0x%08x)\n"

	.comm	_IWL_SHARED_IRQ_NON_RX,4,2      ## @IWL_SHARED_IRQ_NON_RX
	.comm	_MSIX_FH_INT_CAUSES_Q0,4,2      ## @MSIX_FH_INT_CAUSES_Q0
	.comm	_IWL_SHARED_IRQ_FIRST_RSS,4,2   ## @IWL_SHARED_IRQ_FIRST_RSS
	.comm	_MSIX_FH_INT_CAUSES_Q1,4,2      ## @MSIX_FH_INT_CAUSES_Q1
	.comm	_MSIX_FH_INT_CAUSES_D2S_CH0_NUM,4,2 ## @MSIX_FH_INT_CAUSES_D2S_CH0_NUM
L_.str.3:                               ## @.str.3
	.asciz	"uCode load interrupt\n"

	.comm	_MSIX_FH_INT_CAUSES_FH_ERR,4,2  ## @MSIX_FH_INT_CAUSES_FH_ERR
	.comm	_MSIX_HW_INT_CAUSES_REG_SW_ERR,4,2 ## @MSIX_HW_INT_CAUSES_REG_SW_ERR
	.comm	_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2,4,2 ## @MSIX_HW_INT_CAUSES_REG_SW_ERR_V2
L_.str.4:                               ## @.str.4
	.asciz	"Microcode SW error detected. Restarting 0x%X.\n"

L_.str.5:                               ## @.str.5
	.asciz	"ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n"

	.comm	_CSR_MSIX_HW_INT_MASK_AD,4,2    ## @CSR_MSIX_HW_INT_MASK_AD
L_.str.6:                               ## @.str.6
	.asciz	"We got a masked interrupt 0x%08x\n"

	.comm	_MSIX_HW_INT_CAUSES_REG_ALIVE,4,2 ## @MSIX_HW_INT_CAUSES_REG_ALIVE
L_.str.7:                               ## @.str.7
	.asciz	"Alive interrupt\n"

	.comm	_IWL_DEVICE_FAMILY_22560,8,3    ## @IWL_DEVICE_FAMILY_22560
	.comm	_MSIX_HW_INT_CAUSES_REG_IPC,4,2 ## @MSIX_HW_INT_CAUSES_REG_IPC
	.comm	_CSR_IML_RESP_ADDR,4,2          ## @CSR_IML_RESP_ADDR
L_.str.8:                               ## @.str.8
	.asciz	"IML transfer status: %d\n"

	.comm	_IWL_IMAGE_RESP_FAIL,4,2        ## @IWL_IMAGE_RESP_FAIL
	.comm	_MSIX_HW_INT_CAUSES_REG_WAKEUP,4,2 ## @MSIX_HW_INT_CAUSES_REG_WAKEUP
	.comm	_IWL_D3_SLEEP_STATUS_SUSPEND,4,2 ## @IWL_D3_SLEEP_STATUS_SUSPEND
	.comm	_IWL_D3_SLEEP_STATUS_RESUME,4,2 ## @IWL_D3_SLEEP_STATUS_RESUME
L_.str.9:                               ## @.str.9
	.asciz	"Sx interrupt: sleep notification = 0x%x\n"

L_.str.10:                              ## @.str.10
	.asciz	"Wakeup interrupt\n"

	.comm	_MSIX_HW_INT_CAUSES_REG_IML,4,2 ## @MSIX_HW_INT_CAUSES_REG_IML
	.comm	_MSIX_HW_INT_CAUSES_REG_CT_KILL,4,2 ## @MSIX_HW_INT_CAUSES_REG_CT_KILL
L_.str.11:                              ## @.str.11
	.asciz	"Microcode CT kill error detected.\n"

	.comm	_MSIX_HW_INT_CAUSES_REG_RF_KILL,4,2 ## @MSIX_HW_INT_CAUSES_REG_RF_KILL
	.comm	_MSIX_HW_INT_CAUSES_REG_HW_ERR,4,2 ## @MSIX_HW_INT_CAUSES_REG_HW_ERR
L_.str.12:                              ## @.str.12
	.asciz	"Hardware error detected. Restarting.\n"

	.comm	_IRQ_HANDLED,4,2                ## @IRQ_HANDLED
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_iwl_pcie_irq_msix_handler      ; -- Begin function iwl_pcie_irq_msix_handler
	.p2align	2
_iwl_pcie_irq_msix_handler:             ; @iwl_pcie_irq_msix_handler
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x1
	mov	x0, x1
	bl	_iwl_pcie_get_trans_pcie
	mov	x21, x0
	ldr	x19, [x0, #72]
	mov	x0, x19
	bl	_lock_map_acquire
	add	x24, x21, #40
	mov	x0, x24
	bl	_spin_lock
Lloh0:
	adrp	x25, _CSR_MSIX_FH_INT_CAUSES_AD@GOTPAGE
Lloh1:
	ldr	x25, [x25, _CSR_MSIX_FH_INT_CAUSES_AD@GOTPAGEOFF]
	ldr	w1, [x25]
	mov	x0, x19
	bl	_iwl_read32
	mov	x23, x0
Lloh2:
	adrp	x26, _CSR_MSIX_HW_INT_CAUSES_AD@GOTPAGE
Lloh3:
	ldr	x26, [x26, _CSR_MSIX_HW_INT_CAUSES_AD@GOTPAGEOFF]
	ldr	w1, [x26]
	mov	x0, x19
	bl	_iwl_read32
	mov	x22, x0
	ldr	w1, [x25]
	mov	x0, x19
	mov	x2, x23
	bl	_iwl_write32
	ldr	w1, [x26]
	mov	x0, x19
	mov	x2, x22
	bl	_iwl_write32
	mov	x0, x24
	bl	_spin_unlock
	ldr	w0, [x19, #16]
	mov	x1, x20
	mov	w2, #1
	mov	x3, x23
	mov	x4, x22
	bl	_trace_iwlwifi_dev_irq_msix
	orr	w8, w22, w23
	cmp	w8, #0
	cset	w0, eq
	bl	_unlikely
	cbz	x0, LBB0_2
; %bb.1:
Lloh4:
	adrp	x1, l_.str@PAGE
Lloh5:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
Lloh6:
	adrp	x20, _IRQ_NONE@GOTPAGE
Lloh7:
	ldr	x20, [x20, _IRQ_NONE@GOTPAGEOFF]
	b	LBB0_42
LBB0_2:
Lloh8:
	adrp	x24, _IWL_DL_ISR@GOTPAGE
Lloh9:
	ldr	x24, [x24, _IWL_DL_ISR@GOTPAGEOFF]
	ldr	w0, [x24]
	bl	_iwl_have_debug_level
	cbz	x0, LBB0_5
; %bb.3:
Lloh10:
	adrp	x8, _CSR_MSIX_FH_INT_MASK_AD@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CSR_MSIX_FH_INT_MASK_AD@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	ldr	w25, [x21]
	mov	x0, x19
	bl	_iwl_read32
                                        ; kill: def $w0 killed $w0 def $x0
	stp	x25, x0, [sp, #8]
	str	x23, [sp]
Lloh13:
	adrp	x1, l_.str.1@PAGE
Lloh14:
	add	x1, x1, l_.str.1@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21]
	bics	w8, w23, w8
	b.eq	LBB0_5
; %bb.4:
	str	x8, [sp]
Lloh15:
	adrp	x1, l_.str.2@PAGE
Lloh16:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
LBB0_5:
	ldp	w9, w8, [x21]
	and	w23, w9, w23
Lloh17:
	adrp	x9, _IWL_SHARED_IRQ_NON_RX@GOTPAGE
Lloh18:
	ldr	x9, [x9, _IWL_SHARED_IRQ_NON_RX@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_8
; %bb.6:
Lloh20:
	adrp	x9, _MSIX_FH_INT_CAUSES_Q0@GOTPAGE
Lloh21:
	ldr	x9, [x9, _MSIX_FH_INT_CAUSES_Q0@GOTPAGEOFF]
Lloh22:
	ldr	w9, [x9]
	tst	w9, w23
	b.eq	LBB0_8
; %bb.7:
	bl	_local_bh_disable
	mov	x0, x19
	mov	w1, #0
	bl	_iwl_pcie_rx_handle
	bl	_local_bh_enable
	ldr	w8, [x21, #4]
LBB0_8:
Lloh23:
	adrp	x9, _IWL_SHARED_IRQ_FIRST_RSS@GOTPAGE
Lloh24:
	ldr	x9, [x9, _IWL_SHARED_IRQ_FIRST_RSS@GOTPAGEOFF]
Lloh25:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_11
; %bb.9:
Lloh26:
	adrp	x8, _MSIX_FH_INT_CAUSES_Q1@GOTPAGE
Lloh27:
	ldr	x8, [x8, _MSIX_FH_INT_CAUSES_Q1@GOTPAGEOFF]
Lloh28:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_11
; %bb.10:
	bl	_local_bh_disable
	mov	x0, x19
	mov	w1, #1
	bl	_iwl_pcie_rx_handle
	bl	_local_bh_enable
LBB0_11:
Lloh29:
	adrp	x8, _MSIX_FH_INT_CAUSES_D2S_CH0_NUM@GOTPAGE
Lloh30:
	ldr	x8, [x8, _MSIX_FH_INT_CAUSES_D2S_CH0_NUM@GOTPAGEOFF]
Lloh31:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_13
; %bb.12:
Lloh32:
	adrp	x1, l_.str.3@PAGE
Lloh33:
	add	x1, x1, l_.str.3@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21, #64]
	add	w8, w8, #1
	str	w8, [x21, #64]
	mov	w8, #1
	str	w8, [x21, #8]
	add	x0, x21, #36
	bl	_wake_up
LBB0_13:
Lloh34:
	adrp	x8, _MSIX_FH_INT_CAUSES_FH_ERR@GOTPAGE
Lloh35:
	ldr	x8, [x8, _MSIX_FH_INT_CAUSES_FH_ERR@GOTPAGEOFF]
Lloh36:
	ldr	w8, [x8]
	tst	w8, w23
	b.ne	LBB0_16
; %bb.14:
Lloh37:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_SW_ERR@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_SW_ERR@GOTPAGEOFF]
Lloh39:
	ldr	w8, [x8]
	tst	w8, w22
	b.ne	LBB0_16
; %bb.15:
Lloh40:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_SW_ERR_V2@GOTPAGE
Lloh41:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_SW_ERR_V2@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
	tst	w8, w22
	b.eq	LBB0_17
LBB0_16:
	str	x23, [sp]
Lloh43:
	adrp	x1, l_.str.4@PAGE
Lloh44:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	ldr	w8, [x21, #52]
	add	w8, w8, #1
	str	w8, [x21, #52]
	mov	x0, x19
	bl	_iwl_pcie_irq_handle_error
LBB0_17:
	ldr	w0, [x24]
	bl	_iwl_have_debug_level
	cbz	x0, LBB0_20
; %bb.18:
Lloh45:
	adrp	x8, _CSR_MSIX_HW_INT_MASK_AD@GOTPAGE
Lloh46:
	ldr	x8, [x8, _CSR_MSIX_HW_INT_MASK_AD@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	ldr	w23, [x21, #12]
	mov	x0, x19
	bl	_iwl_read32
                                        ; kill: def $w0 killed $w0 def $x0
	stp	x23, x0, [sp, #8]
	str	x22, [sp]
Lloh48:
	adrp	x1, l_.str.5@PAGE
Lloh49:
	add	x1, x1, l_.str.5@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21, #12]
	bics	w8, w22, w8
	b.eq	LBB0_20
; %bb.19:
	str	x8, [sp]
Lloh50:
	adrp	x1, l_.str.6@PAGE
Lloh51:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
LBB0_20:
	ldr	w8, [x21, #12]
	and	w23, w8, w22
Lloh52:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_ALIVE@GOTPAGE
Lloh53:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_ALIVE@GOTPAGEOFF]
Lloh54:
	ldr	w8, [x8]
	tst	w23, w8
	b.eq	LBB0_23
; %bb.21:
Lloh55:
	adrp	x1, l_.str.7@PAGE
Lloh56:
	add	x1, x1, l_.str.7@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	ldr	w8, [x21, #60]
	add	w8, w8, #1
	str	w8, [x21, #60]
	ldr	x8, [x19, #8]
	ldr	x8, [x8, #8]
	cbz	x8, LBB0_23
; %bb.22:
	ldr	w1, [x21, #32]
	mov	x0, x19
	bl	_iwl_pcie_rxmq_restock
LBB0_23:
	ldr	x8, [x19, #8]
	ldr	x8, [x8]
Lloh57:
	adrp	x9, _IWL_DEVICE_FAMILY_22560@GOTPAGE
Lloh58:
	ldr	x9, [x9, _IWL_DEVICE_FAMILY_22560@GOTPAGEOFF]
Lloh59:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_27
; %bb.24:
Lloh60:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_IPC@GOTPAGE
Lloh61:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_IPC@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_27
; %bb.25:
Lloh63:
	adrp	x8, _CSR_IML_RESP_ADDR@GOTPAGE
Lloh64:
	ldr	x8, [x8, _CSR_IML_RESP_ADDR@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_iwl_read32
	mov	x22, x0
	str	x22, [sp]
Lloh66:
	adrp	x1, l_.str.8@PAGE
Lloh67:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
Lloh68:
	adrp	x8, _IWL_IMAGE_RESP_FAIL@GOTPAGE
Lloh69:
	ldr	x8, [x8, _IWL_IMAGE_RESP_FAIL@GOTPAGEOFF]
Lloh70:
	ldr	w8, [x8]
	cmp	w22, w8
	b.ne	LBB0_32
; %bb.26:
	ldr	w8, [x21, #52]
	add	w8, w8, #1
	str	w8, [x21, #52]
	mov	x0, x19
	bl	_iwl_pcie_irq_handle_error
	b	LBB0_32
LBB0_27:
Lloh71:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_WAKEUP@GOTPAGE
Lloh72:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_WAKEUP@GOTPAGEOFF]
Lloh73:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_32
; %bb.28:
	ldr	x8, [x21, #24]
	ldr	w0, [x8]
	bl	_le32_to_cpu
                                        ; kill: def $w0 killed $w0 def $x0
Lloh74:
	adrp	x8, _IWL_D3_SLEEP_STATUS_SUSPEND@GOTPAGE
Lloh75:
	ldr	x8, [x8, _IWL_D3_SLEEP_STATUS_SUSPEND@GOTPAGEOFF]
Lloh76:
	ldr	w8, [x8]
	cmp	w0, w8
	b.eq	LBB0_31
; %bb.29:
Lloh77:
	adrp	x8, _IWL_D3_SLEEP_STATUS_RESUME@GOTPAGE
Lloh78:
	ldr	x8, [x8, _IWL_D3_SLEEP_STATUS_RESUME@GOTPAGEOFF]
Lloh79:
	ldr	w8, [x8]
	cmp	w0, w8
	b.eq	LBB0_31
; %bb.30:
Lloh80:
	adrp	x1, l_.str.10@PAGE
Lloh81:
	add	x1, x1, l_.str.10@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	mov	x0, x19
	bl	_iwl_pcie_rxq_check_wrptr
	mov	x0, x19
	bl	_iwl_pcie_txq_check_wrptrs
	ldr	w8, [x21, #56]
	add	w8, w8, #1
	str	w8, [x21, #56]
	b	LBB0_32
LBB0_31:
	str	x0, [sp]
Lloh82:
	adrp	x1, l_.str.9@PAGE
Lloh83:
	add	x1, x1, l_.str.9@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
	mov	w8, #1
	str	w8, [x21, #16]
	add	x0, x21, #20
	bl	_wake_up
LBB0_32:
Lloh84:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_IML@GOTPAGE
Lloh85:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_IML@GOTPAGEOFF]
Lloh86:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_35
; %bb.33:
Lloh87:
	adrp	x8, _CSR_IML_RESP_ADDR@GOTPAGE
Lloh88:
	ldr	x8, [x8, _CSR_IML_RESP_ADDR@GOTPAGEOFF]
Lloh89:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_iwl_read32
	mov	x22, x0
	str	x22, [sp]
Lloh90:
	adrp	x1, l_.str.8@PAGE
Lloh91:
	add	x1, x1, l_.str.8@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
Lloh92:
	adrp	x8, _IWL_IMAGE_RESP_FAIL@GOTPAGE
Lloh93:
	ldr	x8, [x8, _IWL_IMAGE_RESP_FAIL@GOTPAGEOFF]
Lloh94:
	ldr	w8, [x8]
	cmp	w22, w8
	b.ne	LBB0_35
; %bb.34:
	ldr	w8, [x21, #52]
	add	w8, w8, #1
	str	w8, [x21, #52]
	mov	x0, x19
	bl	_iwl_pcie_irq_handle_error
LBB0_35:
Lloh95:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_CT_KILL@GOTPAGE
Lloh96:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_CT_KILL@GOTPAGEOFF]
Lloh97:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_37
; %bb.36:
Lloh98:
	adrp	x1, l_.str.11@PAGE
Lloh99:
	add	x1, x1, l_.str.11@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	ldr	w8, [x21, #48]
	add	w8, w8, #1
	str	w8, [x21, #48]
LBB0_37:
Lloh100:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_RF_KILL@GOTPAGE
Lloh101:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_RF_KILL@GOTPAGEOFF]
Lloh102:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_39
; %bb.38:
	mov	x0, x19
	bl	_iwl_pcie_handle_rfkill_irq
LBB0_39:
Lloh103:
	adrp	x8, _MSIX_HW_INT_CAUSES_REG_HW_ERR@GOTPAGE
Lloh104:
	ldr	x8, [x8, _MSIX_HW_INT_CAUSES_REG_HW_ERR@GOTPAGEOFF]
Lloh105:
	ldr	w8, [x8]
	tst	w8, w23
	b.eq	LBB0_41
; %bb.40:
Lloh106:
	adrp	x1, l_.str.12@PAGE
Lloh107:
	add	x1, x1, l_.str.12@PAGEOFF
	mov	x0, x19
	bl	_IWL_ERR
	ldr	w8, [x21, #44]
	add	w8, w8, #1
	str	w8, [x21, #44]
	mov	w8, #1
	str	w8, [x19, #4]
	mov	x0, x19
	bl	_iwl_pcie_irq_handle_error
LBB0_41:
	mov	x0, x19
	mov	x1, x20
	bl	_iwl_pcie_clear_irq
Lloh108:
	adrp	x20, _IRQ_HANDLED@GOTPAGE
Lloh109:
	ldr	x20, [x20, _IRQ_HANDLED@GOTPAGEOFF]
LBB0_42:
	mov	x0, x19
	bl	_lock_map_release
	ldr	w0, [x20]
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh31
	.loh AdrpAdd	Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpAdd	Lloh43, Lloh44
	.loh AdrpAdd	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpAdd	Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpAdd	Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpAdd	Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh71, Lloh72, Lloh73
	.loh AdrpLdrGotLdr	Lloh74, Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.loh AdrpAdd	Lloh80, Lloh81
	.loh AdrpAdd	Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpAdd	Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpAdd	Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpAdd	Lloh106, Lloh107
	.loh AdrpLdrGot	Lloh108, Lloh109
	.cfi_endproc
                                        ; -- End function
	.comm	_CSR_MSIX_FH_INT_CAUSES_AD,4,2  ; @CSR_MSIX_FH_INT_CAUSES_AD
	.comm	_CSR_MSIX_HW_INT_CAUSES_AD,4,2  ; @CSR_MSIX_HW_INT_CAUSES_AD
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Ignore interrupt, inta == 0\n"

	.comm	_IRQ_NONE,4,2                   ; @IRQ_NONE
	.comm	_IWL_DL_ISR,4,2                 ; @IWL_DL_ISR
l_.str.1:                               ; @.str.1
	.asciz	"ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n"

	.comm	_CSR_MSIX_FH_INT_MASK_AD,4,2    ; @CSR_MSIX_FH_INT_MASK_AD
l_.str.2:                               ; @.str.2
	.asciz	"We got a masked interrupt (0x%08x)\n"

	.comm	_IWL_SHARED_IRQ_NON_RX,4,2      ; @IWL_SHARED_IRQ_NON_RX
	.comm	_MSIX_FH_INT_CAUSES_Q0,4,2      ; @MSIX_FH_INT_CAUSES_Q0
	.comm	_IWL_SHARED_IRQ_FIRST_RSS,4,2   ; @IWL_SHARED_IRQ_FIRST_RSS
	.comm	_MSIX_FH_INT_CAUSES_Q1,4,2      ; @MSIX_FH_INT_CAUSES_Q1
	.comm	_MSIX_FH_INT_CAUSES_D2S_CH0_NUM,4,2 ; @MSIX_FH_INT_CAUSES_D2S_CH0_NUM
l_.str.3:                               ; @.str.3
	.asciz	"uCode load interrupt\n"

	.comm	_MSIX_FH_INT_CAUSES_FH_ERR,4,2  ; @MSIX_FH_INT_CAUSES_FH_ERR
	.comm	_MSIX_HW_INT_CAUSES_REG_SW_ERR,4,2 ; @MSIX_HW_INT_CAUSES_REG_SW_ERR
	.comm	_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2,4,2 ; @MSIX_HW_INT_CAUSES_REG_SW_ERR_V2
l_.str.4:                               ; @.str.4
	.asciz	"Microcode SW error detected. Restarting 0x%X.\n"

l_.str.5:                               ; @.str.5
	.asciz	"ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n"

	.comm	_CSR_MSIX_HW_INT_MASK_AD,4,2    ; @CSR_MSIX_HW_INT_MASK_AD
l_.str.6:                               ; @.str.6
	.asciz	"We got a masked interrupt 0x%08x\n"

	.comm	_MSIX_HW_INT_CAUSES_REG_ALIVE,4,2 ; @MSIX_HW_INT_CAUSES_REG_ALIVE
l_.str.7:                               ; @.str.7
	.asciz	"Alive interrupt\n"

	.comm	_IWL_DEVICE_FAMILY_22560,8,3    ; @IWL_DEVICE_FAMILY_22560
	.comm	_MSIX_HW_INT_CAUSES_REG_IPC,4,2 ; @MSIX_HW_INT_CAUSES_REG_IPC
	.comm	_CSR_IML_RESP_ADDR,4,2          ; @CSR_IML_RESP_ADDR
l_.str.8:                               ; @.str.8
	.asciz	"IML transfer status: %d\n"

	.comm	_IWL_IMAGE_RESP_FAIL,4,2        ; @IWL_IMAGE_RESP_FAIL
	.comm	_MSIX_HW_INT_CAUSES_REG_WAKEUP,4,2 ; @MSIX_HW_INT_CAUSES_REG_WAKEUP
	.comm	_IWL_D3_SLEEP_STATUS_SUSPEND,4,2 ; @IWL_D3_SLEEP_STATUS_SUSPEND
	.comm	_IWL_D3_SLEEP_STATUS_RESUME,4,2 ; @IWL_D3_SLEEP_STATUS_RESUME
l_.str.9:                               ; @.str.9
	.asciz	"Sx interrupt: sleep notification = 0x%x\n"

l_.str.10:                              ; @.str.10
	.asciz	"Wakeup interrupt\n"

	.comm	_MSIX_HW_INT_CAUSES_REG_IML,4,2 ; @MSIX_HW_INT_CAUSES_REG_IML
	.comm	_MSIX_HW_INT_CAUSES_REG_CT_KILL,4,2 ; @MSIX_HW_INT_CAUSES_REG_CT_KILL
l_.str.11:                              ; @.str.11
	.asciz	"Microcode CT kill error detected.\n"

	.comm	_MSIX_HW_INT_CAUSES_REG_RF_KILL,4,2 ; @MSIX_HW_INT_CAUSES_REG_RF_KILL
	.comm	_MSIX_HW_INT_CAUSES_REG_HW_ERR,4,2 ; @MSIX_HW_INT_CAUSES_REG_HW_ERR
l_.str.12:                              ; @.str.12
	.asciz	"Hardware error detected. Restarting.\n"

	.comm	_IRQ_HANDLED,4,2                ; @IRQ_HANDLED
.subsections_via_symbols
