	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dra7xx_pcie_ep_init
_dra7xx_pcie_ep_init:                   ## @dra7xx_pcie_ep_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_to_dw_pcie_from_ep
	movq	%rax, %r15
	movq	%rax, %rdi
	callq	_to_dra7xx_pcie
	movq	%rax, %r14
	movq	_BAR_0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_BAR_5@GOTPCREL(%rip), %r12
	cmpl	(%r12), %ebx
	ja	LBB0_3
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_dw_pcie_ep_reset_bar
	incl	%ebx
	cmpl	(%r12), %ebx
	jbe	LBB0_1
LBB0_3:
	movq	%r14, %rdi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_dra7xx_pcie_enable_wrapper_interrupts ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_BAR_0,4,2                      ## @BAR_0
	.comm	_BAR_5,4,2                      ## @BAR_5
	.no_dead_strip	_dra7xx_pcie_ep_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dra7xx_pcie_ep_init
_dra7xx_pcie_ep_init:                   ; @dra7xx_pcie_ep_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	bl	_to_dw_pcie_from_ep
	mov	x19, x0
	bl	_to_dra7xx_pcie
	mov	x20, x0
Lloh0:
	adrp	x8, _BAR_0@GOTPAGE
Lloh1:
	ldr	x8, [x8, _BAR_0@GOTPAGEOFF]
Lloh2:
	ldr	w21, [x8]
Lloh3:
	adrp	x22, _BAR_5@GOTPAGE
Lloh4:
	ldr	x22, [x22, _BAR_5@GOTPAGEOFF]
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w8, [x22]
	cmp	w21, w8
	b.hi	LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	mov	x0, x19
	mov	x1, x21
	bl	_dw_pcie_ep_reset_bar
	add	w21, w21, #1
	b	LBB0_1
LBB0_3:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_dra7xx_pcie_enable_wrapper_interrupts
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_BAR_0,4,2                      ; @BAR_0
	.comm	_BAR_5,4,2                      ; @BAR_5
	.no_dead_strip	_dra7xx_pcie_ep_init
.subsections_via_symbols
