	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pci_quirk_enable_intel_spt_pch_acs
_pci_quirk_enable_intel_spt_pch_acs:    ## @pci_quirk_enable_intel_spt_pch_acs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_pci_quirk_intel_spt_pch_acs_match
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	movq	_PCI_EXT_CAP_ID_ACS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_pci_find_ext_capability
	testl	%eax, %eax
	je	LBB0_1
## %bb.3:
	movslq	%eax, %r14
	movq	_PCI_ACS_CAP@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	%r14, %rsi
	leaq	-32(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_pci_read_config_dword
	movq	_INTEL_SPT_ACS_CTRL@GOTPCREL(%rip), %r15
	movq	(%r15), %rsi
	addq	%r14, %rsi
	leaq	-28(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_pci_read_config_dword
	movl	-32(%rbp), %edx
	movq	_PCI_ACS_SV@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%edx, %eax
	orl	-28(%rbp), %eax
	movq	_PCI_ACS_RR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	andl	%edx, %ecx
	movq	_PCI_ACS_CR@GOTPCREL(%rip), %rsi
	movl	(%rsi), %esi
	andl	%edx, %esi
	orl	%ecx, %esi
	orl	%eax, %esi
	movq	_PCI_ACS_UF@GOTPCREL(%rip), %rax
	andl	(%rax), %edx
	orl	%esi, %edx
	movl	%edx, -28(%rbp)
	addq	(%r15), %r14
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_pci_write_config_dword
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
	callq	_pci_info
	xorl	%eax, %eax
	jmp	LBB0_4
LBB0_1:
	movq	_ENOTTY@GOTPCREL(%rip), %rcx
	xorl	%eax, %eax
	subl	(%rcx), %eax
LBB0_4:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_ENOTTY,4,2                     ## @ENOTTY
	.comm	_PCI_EXT_CAP_ID_ACS,4,2         ## @PCI_EXT_CAP_ID_ACS
	.comm	_PCI_ACS_CAP,8,3                ## @PCI_ACS_CAP
	.comm	_INTEL_SPT_ACS_CTRL,8,3         ## @INTEL_SPT_ACS_CTRL
	.comm	_PCI_ACS_SV,4,2                 ## @PCI_ACS_SV
	.comm	_PCI_ACS_RR,4,2                 ## @PCI_ACS_RR
	.comm	_PCI_ACS_CR,4,2                 ## @PCI_ACS_CR
	.comm	_PCI_ACS_UF,4,2                 ## @PCI_ACS_UF
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Intel SPT PCH root port ACS workaround enabled\n"

	.no_dead_strip	_pci_quirk_enable_intel_spt_pch_acs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pci_quirk_enable_intel_spt_pch_acs
_pci_quirk_enable_intel_spt_pch_acs:    ; @pci_quirk_enable_intel_spt_pch_acs
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_pci_quirk_intel_spt_pch_acs_match
	cbz	w0, LBB0_3
; %bb.1:
Lloh0:
	adrp	x8, _PCI_EXT_CAP_ID_ACS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_EXT_CAP_ID_ACS@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_pci_find_ext_capability
                                        ; kill: def $w0 killed $w0 def $x0
	cbz	w0, LBB0_3
; %bb.2:
	sxtw	x20, w0
Lloh3:
	adrp	x8, _PCI_ACS_CAP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_ACS_CAP@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	add	x1, x8, x20
	add	x2, sp, #12
	mov	x0, x19
	bl	_pci_read_config_dword
Lloh6:
	adrp	x21, _INTEL_SPT_ACS_CTRL@GOTPAGE
Lloh7:
	ldr	x21, [x21, _INTEL_SPT_ACS_CTRL@GOTPAGEOFF]
	ldr	x8, [x21]
	add	x1, x8, x20
	add	x2, sp, #8
	mov	x0, x19
	bl	_pci_read_config_dword
	ldp	w10, w8, [sp, #8]
Lloh8:
	adrp	x9, _PCI_ACS_SV@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PCI_ACS_SV@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	and	w9, w9, w8
	orr	w9, w10, w9
Lloh11:
	adrp	x10, _PCI_ACS_RR@GOTPAGE
Lloh12:
	ldr	x10, [x10, _PCI_ACS_RR@GOTPAGEOFF]
Lloh13:
	ldr	w10, [x10]
	and	w10, w10, w8
Lloh14:
	adrp	x11, _PCI_ACS_CR@GOTPAGE
Lloh15:
	ldr	x11, [x11, _PCI_ACS_CR@GOTPAGEOFF]
	orr	w9, w10, w9
Lloh16:
	ldr	w10, [x11]
	and	w10, w10, w8
	orr	w9, w10, w9
Lloh17:
	adrp	x10, _PCI_ACS_UF@GOTPAGE
Lloh18:
	ldr	x10, [x10, _PCI_ACS_UF@GOTPAGEOFF]
Lloh19:
	ldr	w10, [x10]
	and	w8, w10, w8
	orr	w2, w8, w9
	str	w2, [sp, #8]
	ldr	x8, [x21]
	add	x1, x8, x20
	mov	x0, x19
	bl	_pci_write_config_dword
Lloh20:
	adrp	x1, l_.str@PAGE
Lloh21:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_pci_info
	mov	w0, #0
	b	LBB0_4
LBB0_3:
Lloh22:
	adrp	x8, _ENOTTY@GOTPAGE
Lloh23:
	ldr	x8, [x8, _ENOTTY@GOTPAGEOFF]
Lloh24:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_4:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.cfi_endproc
                                        ; -- End function
	.comm	_ENOTTY,4,2                     ; @ENOTTY
	.comm	_PCI_EXT_CAP_ID_ACS,4,2         ; @PCI_EXT_CAP_ID_ACS
	.comm	_PCI_ACS_CAP,8,3                ; @PCI_ACS_CAP
	.comm	_INTEL_SPT_ACS_CTRL,8,3         ; @INTEL_SPT_ACS_CTRL
	.comm	_PCI_ACS_SV,4,2                 ; @PCI_ACS_SV
	.comm	_PCI_ACS_RR,4,2                 ; @PCI_ACS_RR
	.comm	_PCI_ACS_CR,4,2                 ; @PCI_ACS_CR
	.comm	_PCI_ACS_UF,4,2                 ; @PCI_ACS_UF
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Intel SPT PCH root port ACS workaround enabled\n"

	.no_dead_strip	_pci_quirk_enable_intel_spt_pch_acs
.subsections_via_symbols
