	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rtl88e_dm_fast_training_init
_rtl88e_dm_fast_training_init:          ## @rtl88e_dm_fast_training_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r13
	callq	_rtl_priv
	movl	%eax, %edi
	callq	_rtl_dm
	movq	40(%rax), %rcx
	movq	32(%rax), %rdx
	movq	16(%rax), %rsi
	movq	24(%rax), %rdi
	movq	$0, (%rcx)
	movq	$0, (%rdx)
	movq	$0, (%rdi)
	movq	$0, (%rsi)
	movq	$0, 8(%rcx)
	movq	$0, 8(%rdx)
	movq	$0, 8(%rdi)
	movq	$0, 8(%rsi)
	movq	$0, 16(%rcx)
	movq	$0, 16(%rdx)
	movq	$0, 16(%rdi)
	movq	$0, 16(%rsi)
	movq	$0, 24(%rcx)
	movq	$0, 24(%rdx)
	movq	$0, 24(%rdi)
	movq	$0, 24(%rsi)
	movq	$0, 32(%rcx)
	movq	$0, 32(%rdx)
	movq	$0, 32(%rdi)
	movq	$0, 32(%rsi)
	movq	$0, 40(%rcx)
	movq	$0, 40(%rdx)
	movq	$0, 40(%rdi)
	movq	$0, 40(%rsi)
	movq	$0, 8(%rax)
	movq	_FAT_NORMAL_STATE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	movl	%ecx, (%rax)
	movq	_DM_REG_ANTSEL_PIN_11N@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MASKDWORD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	callq	_rtl_get_bbreg
	movl	%eax, %r14d
	movl	(%r15), %r15d
	movl	(%rbx), %r12d
	movl	$23, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$25, %edi
	callq	_BIT
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movq	%r13, %rdi
	movl	%r15d, %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_ANT_TRAIN_PARA2_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rax, %r14
	movq	_MASKDWORD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	callq	_rtl_get_bbreg
	movl	%eax, %r12d
	movl	(%r14), %r14d
	movl	(%rbx), %r15d
	movl	$16, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$17, %edi
	callq	_BIT
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
	movl	%ebx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_ANT_TRAIN_PARA2_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MASKLWORD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_ANT_TRAIN_PARA1_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MASKDWORD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_PIN_CTRL_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$9, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$8, %edi
	callq	_BIT
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_RX_ANT_CTRL_11N@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	movl	$10, %edi
	callq	_BIT
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_LNA_SWITCH_11N@GOTPCREL(%rip), %r14
	movl	(%r14), %ebx
	movl	$22, %edi
	callq	_BIT
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movl	(%r14), %ebx
	movl	$31, %edi
	callq	_BIT
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_ANTDIV_PARA1_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MASKDWORD@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$160, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_ANT_MAPPING1_11N@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MASKBYTE0@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movl	(%rbx), %esi
	movq	_MASKBYTE1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_TX_ANT_CTRL_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$21, %edi
	callq	_BIT
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movl	(%r15), %r14d
	movl	$5, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$4, %edi
	callq	_BIT
	orl	%eax, %ebx
	movl	$3, %edi
	callq	_BIT
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	xorl	%ecx, %ecx
	callq	_rtl_set_bbreg
	movl	(%r15), %r14d
	movl	$8, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_BIT
	orl	%eax, %ebx
	movl	$6, %edi
	callq	_BIT
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movl	(%r15), %r14d
	movl	$2, %edi
	callq	_BIT
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_BIT
	orl	%eax, %ebx
	xorl	%edi, %edi
	callq	_BIT
	orl	%eax, %ebx
	movq	%r13, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movl	$1, %ecx
	callq	_rtl_set_bbreg
	movq	_DM_REG_IGI_A_11N@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$7, %edi
	callq	_BIT
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	movl	$1, %ecx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rtl_set_bbreg                  ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_FAT_NORMAL_STATE,4,2           ## @FAT_NORMAL_STATE
	.comm	_DM_REG_ANTSEL_PIN_11N,4,2      ## @DM_REG_ANTSEL_PIN_11N
	.comm	_MASKDWORD,4,2                  ## @MASKDWORD
	.comm	_DM_REG_ANT_TRAIN_PARA2_11N,4,2 ## @DM_REG_ANT_TRAIN_PARA2_11N
	.comm	_MASKLWORD,4,2                  ## @MASKLWORD
	.comm	_DM_REG_ANT_TRAIN_PARA1_11N,4,2 ## @DM_REG_ANT_TRAIN_PARA1_11N
	.comm	_DM_REG_PIN_CTRL_11N,4,2        ## @DM_REG_PIN_CTRL_11N
	.comm	_DM_REG_RX_ANT_CTRL_11N,4,2     ## @DM_REG_RX_ANT_CTRL_11N
	.comm	_DM_REG_LNA_SWITCH_11N,4,2      ## @DM_REG_LNA_SWITCH_11N
	.comm	_DM_REG_ANTDIV_PARA1_11N,4,2    ## @DM_REG_ANTDIV_PARA1_11N
	.comm	_DM_REG_ANT_MAPPING1_11N,4,2    ## @DM_REG_ANT_MAPPING1_11N
	.comm	_MASKBYTE0,4,2                  ## @MASKBYTE0
	.comm	_MASKBYTE1,4,2                  ## @MASKBYTE1
	.comm	_DM_REG_TX_ANT_CTRL_11N,4,2     ## @DM_REG_TX_ANT_CTRL_11N
	.comm	_DM_REG_IGI_A_11N,4,2           ## @DM_REG_IGI_A_11N
	.no_dead_strip	_rtl88e_dm_fast_training_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rtl88e_dm_fast_training_init
_rtl88e_dm_fast_training_init:          ; @rtl88e_dm_fast_training_init
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_rtl_priv
	bl	_rtl_dm
	ldp	x9, x8, [x0, #32]
	ldp	x11, x10, [x0, #16]
	str	xzr, [x8]
	str	xzr, [x9]
	str	xzr, [x10]
	str	xzr, [x11]
	str	xzr, [x8, #8]
	str	xzr, [x9, #8]
	str	xzr, [x10, #8]
	str	xzr, [x11, #8]
	str	xzr, [x8, #16]
	str	xzr, [x9, #16]
	str	xzr, [x10, #16]
	str	xzr, [x11, #16]
	str	xzr, [x8, #24]
	str	xzr, [x9, #24]
	str	xzr, [x10, #24]
	str	xzr, [x11, #24]
	str	xzr, [x8, #32]
	str	xzr, [x9, #32]
	str	xzr, [x10, #32]
	str	xzr, [x11, #32]
	str	xzr, [x8, #40]
	str	xzr, [x9, #40]
	str	xzr, [x10, #40]
	str	xzr, [x11, #40]
	str	xzr, [x0, #8]
Lloh0:
	adrp	x8, _FAT_NORMAL_STATE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _FAT_NORMAL_STATE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x0]
Lloh3:
	adrp	x21, _DM_REG_ANTSEL_PIN_11N@GOTPAGE
Lloh4:
	ldr	x21, [x21, _DM_REG_ANTSEL_PIN_11N@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh5:
	adrp	x24, _MASKDWORD@GOTPAGE
Lloh6:
	ldr	x24, [x24, _MASKDWORD@GOTPAGEOFF]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_rtl_get_bbreg
	mov	x20, x0
	ldr	w21, [x21]
	ldr	w22, [x24]
	mov	w0, #23
	bl	_BIT
	mov	x23, x0
	mov	w0, #25
	bl	_BIT
	orr	w8, w23, w20
	orr	w3, w8, w0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_rtl_set_bbreg
Lloh7:
	adrp	x25, _DM_REG_ANT_TRAIN_PARA2_11N@GOTPAGE
Lloh8:
	ldr	x25, [x25, _DM_REG_ANT_TRAIN_PARA2_11N@GOTPAGEOFF]
	ldr	w1, [x25]
	ldr	w2, [x24]
	mov	x0, x19
	bl	_rtl_get_bbreg
	mov	x20, x0
	ldr	w21, [x25]
	ldr	w22, [x24]
	mov	w0, #16
	bl	_BIT
	mov	x23, x0
	mov	w0, #17
	bl	_BIT
	orr	w8, w23, w20
	orr	w3, w8, w0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_rtl_set_bbreg
	ldr	w1, [x25]
Lloh9:
	adrp	x8, _MASKLWORD@GOTPAGE
Lloh10:
	ldr	x8, [x8, _MASKLWORD@GOTPAGEOFF]
Lloh11:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #0
	bl	_rtl_set_bbreg
Lloh12:
	adrp	x8, _DM_REG_ANT_TRAIN_PARA1_11N@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DM_REG_ANT_TRAIN_PARA1_11N@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	ldr	w2, [x24]
	mov	x0, x19
	mov	w3, #0
	bl	_rtl_set_bbreg
Lloh15:
	adrp	x8, _DM_REG_PIN_CTRL_11N@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DM_REG_PIN_CTRL_11N@GOTPAGEOFF]
Lloh17:
	ldr	w20, [x8]
	mov	w0, #9
	bl	_BIT
	mov	x21, x0
	mov	w0, #8
	bl	_BIT
	orr	w2, w0, w21
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_rtl_set_bbreg
Lloh18:
	adrp	x22, _DM_REG_RX_ANT_CTRL_11N@GOTPAGE
Lloh19:
	ldr	x22, [x22, _DM_REG_RX_ANT_CTRL_11N@GOTPAGEOFF]
	ldr	w20, [x22]
	mov	w0, #10
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_rtl_set_bbreg
Lloh20:
	adrp	x21, _DM_REG_LNA_SWITCH_11N@GOTPAGE
Lloh21:
	ldr	x21, [x21, _DM_REG_LNA_SWITCH_11N@GOTPAGEOFF]
	ldr	w20, [x21]
	mov	w0, #22
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_rtl_set_bbreg
	ldr	w20, [x21]
	mov	w0, #31
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	bl	_rtl_set_bbreg
Lloh22:
	adrp	x8, _DM_REG_ANTDIV_PARA1_11N@GOTPAGE
Lloh23:
	ldr	x8, [x8, _DM_REG_ANTDIV_PARA1_11N@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	ldr	w2, [x24]
	mov	x0, x19
	mov	w3, #160
	bl	_rtl_set_bbreg
Lloh25:
	adrp	x20, _DM_REG_ANT_MAPPING1_11N@GOTPAGE
Lloh26:
	ldr	x20, [x20, _DM_REG_ANT_MAPPING1_11N@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh27:
	adrp	x8, _MASKBYTE0@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MASKBYTE0@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #1
	bl	_rtl_set_bbreg
	ldr	w1, [x20]
Lloh30:
	adrp	x8, _MASKBYTE1@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MASKBYTE1@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #2
	bl	_rtl_set_bbreg
Lloh33:
	adrp	x8, _DM_REG_TX_ANT_CTRL_11N@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DM_REG_TX_ANT_CTRL_11N@GOTPAGEOFF]
Lloh35:
	ldr	w20, [x8]
	mov	w0, #21
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	bl	_rtl_set_bbreg
	ldr	w20, [x22]
	mov	w0, #5
	bl	_BIT
	mov	x21, x0
	mov	w0, #4
	bl	_BIT
	orr	w21, w0, w21
	mov	w0, #3
	bl	_BIT
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #0
	bl	_rtl_set_bbreg
	ldr	w20, [x22]
	mov	w0, #8
	bl	_BIT
	mov	x21, x0
	mov	w0, #7
	bl	_BIT
	orr	w21, w0, w21
	mov	w0, #6
	bl	_BIT
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	bl	_rtl_set_bbreg
	ldr	w20, [x22]
	mov	w0, #2
	bl	_BIT
	mov	x21, x0
	mov	w0, #1
	bl	_BIT
	orr	w21, w0, w21
	mov	w0, #0
	bl	_BIT
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	bl	_rtl_set_bbreg
Lloh36:
	adrp	x8, _DM_REG_IGI_A_11N@GOTPAGE
Lloh37:
	ldr	x8, [x8, _DM_REG_IGI_A_11N@GOTPAGEOFF]
Lloh38:
	ldr	w20, [x8]
	mov	w0, #7
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	mov	w3, #1
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_rtl_set_bbreg
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_FAT_NORMAL_STATE,4,2           ; @FAT_NORMAL_STATE
	.comm	_DM_REG_ANTSEL_PIN_11N,4,2      ; @DM_REG_ANTSEL_PIN_11N
	.comm	_MASKDWORD,4,2                  ; @MASKDWORD
	.comm	_DM_REG_ANT_TRAIN_PARA2_11N,4,2 ; @DM_REG_ANT_TRAIN_PARA2_11N
	.comm	_MASKLWORD,4,2                  ; @MASKLWORD
	.comm	_DM_REG_ANT_TRAIN_PARA1_11N,4,2 ; @DM_REG_ANT_TRAIN_PARA1_11N
	.comm	_DM_REG_PIN_CTRL_11N,4,2        ; @DM_REG_PIN_CTRL_11N
	.comm	_DM_REG_RX_ANT_CTRL_11N,4,2     ; @DM_REG_RX_ANT_CTRL_11N
	.comm	_DM_REG_LNA_SWITCH_11N,4,2      ; @DM_REG_LNA_SWITCH_11N
	.comm	_DM_REG_ANTDIV_PARA1_11N,4,2    ; @DM_REG_ANTDIV_PARA1_11N
	.comm	_DM_REG_ANT_MAPPING1_11N,4,2    ; @DM_REG_ANT_MAPPING1_11N
	.comm	_MASKBYTE0,4,2                  ; @MASKBYTE0
	.comm	_MASKBYTE1,4,2                  ; @MASKBYTE1
	.comm	_DM_REG_TX_ANT_CTRL_11N,4,2     ; @DM_REG_TX_ANT_CTRL_11N
	.comm	_DM_REG_IGI_A_11N,4,2           ; @DM_REG_IGI_A_11N
	.no_dead_strip	_rtl88e_dm_fast_training_init
.subsections_via_symbols
