	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath10k_hw_qca6174_enable_pll_clock
_ath10k_hw_qca6174_enable_pll_clock:    ## @ath10k_hw_qca6174_enable_pll_clock
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$40, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	(%rax), %r15
	testq	%r15, %r15
	je	LBB0_34
## %bb.1:
	movq	8(%rax), %rbx
	testq	%rbx, %rbx
	je	LBB0_34
## %bb.2:
	movq	16(%rax), %r13
	testq	%r13, %r13
	je	LBB0_34
## %bb.3:
	movq	%rdi, %r12
	movq	_RTC_SOC_BASE_ADDRESS@GOTPCREL(%rip), %rcx
	movq	_EFUSE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	orl	(%rcx), %esi
	leaq	-44(%rbp), %rdx
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.4:
	movl	-44(%rbp), %edi
	movq	_EFUSE_XTAL_SEL@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_MS
	movq	_ATH10K_HW_REFCLK_COUNT@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jg	LBB0_34
## %bb.5:
	movq	%rbx, -72(%rbp)                 ## 8-byte Spill
	movq	%r13, -80(%rbp)                 ## 8-byte Spill
	movq	16(%r12), %rbx
	movl	-44(%rbp), %edi
	movl	(%r14), %esi
	callq	_MS
	movl	%eax, %r14d
	movq	_BB_PLL_CONFIG_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_RTC_SOC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.6:
	movslq	%r14d, %rax
	movq	_BB_PLL_CONFIG_FRAC_MASK@GOTPCREL(%rip), %rcx
	movq	_BB_PLL_CONFIG_OUTDIV_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%edx, -44(%rbp)
	leaq	(%rax,%rax,4), %rax
	movq	%rax, -64(%rbp)                 ## 8-byte Spill
	movl	(%rbx,%rax,4), %edi
	movq	_BB_PLL_CONFIG_FRAC@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	movl	%eax, %r14d
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	-64(%rbp), %rax                 ## 8-byte Reload
	movl	4(%rbx,%rax,4), %edi
	movq	%rax, %rbx
	movq	_BB_PLL_CONFIG_OUTDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	%eax, %r14d
	orl	-44(%rbp), %r14d
	movl	%r14d, -44(%rbp)
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%r14d, %edx
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.7:
	movq	-56(%rbp), %r14                 ## 8-byte Reload
	movq	_RTC_WMAC_BASE_ADDRESS@GOTPCREL(%rip), %rcx
	movq	_WLAN_PLL_SETTLE_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	orl	(%rcx), %r13d
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.8:
	movq	_WLAN_PLL_SETTLE_TIME_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movl	8(%r14,%rbx,4), %edi
	movq	_WLAN_PLL_SETTLE_TIME@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	-44(%rbp), %eax
	movl	%eax, -44(%rbp)
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.9:
	movq	_SOC_CORE_CLK_CTRL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_RTC_SOC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.10:
	movq	_SOC_CORE_CLK_CTRL_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movq	_SOC_CORE_CLK_CTRL_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	-44(%rbp), %eax
	movl	%eax, -44(%rbp)
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.11:
	movl	$1, -48(%rbp)
	leaq	-48(%rbp), %rdx
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	$4, %ecx
	callq	_ath10k_bmi_write_memory
	testl	%eax, %eax
	jne	LBB0_34
## %bb.12:
	movq	_WLAN_PLL_CONTROL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_RTC_WMAC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.13:
	movq	%r14, %r15
	movq	%rbx, %r14
	movl	12(%r15,%rbx,4), %edi
	movq	_WLAN_PLL_CONTROL_REFDIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	movl	%eax, %ebx
	movl	16(%r15,%r14,4), %edi
	movq	_WLAN_PLL_CONTROL_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_SM
	orl	%eax, %ebx
	movq	_WLAN_PLL_CONTROL_NOPWD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	%eax, %ebx
	orl	-44(%rbp), %ebx
	movl	%ebx, -44(%rbp)
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%ebx, %edx
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	je	LBB0_14
LBB0_34:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
LBB0_35:
	subl	(%rax), %ebx
LBB0_36:
	movl	%ebx, %eax
	addq	$40, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_14:
	movq	_RTC_SYNC_STATUS_OFFSET@GOTPCREL(%rip), %r15
	movl	(%r15), %ebx
	movq	_RTC_WMAC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$100001, %r13d                  ## imm = 0x186A1
	movq	_RTC_SYNC_STATUS_PLL_CHANGING@GOTPCREL(%rip), %r14
LBB0_15:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	%ebx, %esi
	leaq	-44(%rbp), %rdx
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.16:                              ##   in Loop: Header=BB0_15 Depth=1
	movl	-44(%rbp), %edi
	movl	(%r14), %esi
	callq	_MS
	testl	%eax, %eax
	je	LBB0_18
## %bb.17:                              ##   in Loop: Header=BB0_15 Depth=1
	movl	$10, %edi
	callq	_udelay
	decl	%r13d
	cmpl	$1, %r13d
	ja	LBB0_15
LBB0_18:
	movl	-44(%rbp), %edi
	movl	(%r14), %esi
	callq	_MS
	testl	%eax, %eax
	jne	LBB0_34
## %bb.19:
	movq	_WLAN_PLL_CONTROL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %r13d
	movq	_RTC_WMAC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %r13d
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%r13d, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.20:
	movq	_WLAN_PLL_CONTROL_BYPASS_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movq	_WLAN_PLL_CONTROL_BYPASS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_SM
	orl	-44(%rbp), %eax
	movl	%eax, -44(%rbp)
	movq	%r12, %rdi
	movl	%r13d, %esi
	movl	%eax, %edx
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	je	LBB0_22
## %bb.21:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	jmp	LBB0_35
LBB0_22:
	movl	(%r15), %ebx
	movq	_RTC_WMAC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$100001, %r13d                  ## imm = 0x186A1
	leaq	-44(%rbp), %r15
LBB0_23:                                ## =>This Inner Loop Header: Depth=1
	movq	%r12, %rdi
	movl	%ebx, %esi
	movq	%r15, %rdx
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.24:                              ##   in Loop: Header=BB0_23 Depth=1
	movl	-44(%rbp), %edi
	movl	(%r14), %esi
	callq	_MS
	testl	%eax, %eax
	je	LBB0_26
## %bb.25:                              ##   in Loop: Header=BB0_23 Depth=1
	movl	$10, %edi
	callq	_udelay
	decl	%r13d
	cmpl	$1, %r13d
	ja	LBB0_23
LBB0_26:
	movl	-44(%rbp), %edi
	movl	(%r14), %esi
	callq	_MS
	testl	%eax, %eax
	jne	LBB0_34
## %bb.27:
	movq	_SOC_CPU_CLOCK_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RTC_SOC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.28:
	movq	_SOC_CPU_CLOCK_STANDARD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	notl	%eax
	andl	%eax, -44(%rbp)
	movq	_SOC_CPU_CLOCK_STANDARD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1, %edi
	callq	_SM
	orl	-44(%rbp), %eax
	movl	%eax, -44(%rbp)
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.29:
	movq	_WLAN_PLL_CONTROL_OFFSET@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_RTC_WMAC_BASE_ADDRESS@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_ath10k_bmi_read_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.30:
	movq	_WLAN_PLL_CONTROL_NOPWD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	-44(%rbp), %edx
	movl	%edx, -44(%rbp)
	movq	%r12, %rdi
	movl	%ebx, %esi
	callq	_ath10k_bmi_write_soc_reg
	testl	%eax, %eax
	jne	LBB0_34
## %bb.31:
	movl	$1, -48(%rbp)
	leaq	-48(%rbp), %rdx
	movq	%r12, %rdi
	movq	-72(%rbp), %rsi                 ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	movl	$4, %ecx
	callq	_ath10k_bmi_write_memory
	testl	%eax, %eax
	jne	LBB0_34
## %bb.32:
	leaq	8(%r12), %rdx
	movq	%r12, %rdi
	movq	-80(%rbp), %rsi                 ## 8-byte Reload
                                        ## kill: def $esi killed $esi killed $rsi
	movl	$4, %ecx
	callq	_ath10k_bmi_write_memory
	testl	%eax, %eax
	jne	LBB0_34
## %bb.33:
	xorl	%ebx, %ebx
	jmp	LBB0_36
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_RTC_SOC_BASE_ADDRESS,4,2       ## @RTC_SOC_BASE_ADDRESS
	.comm	_EFUSE_OFFSET,4,2               ## @EFUSE_OFFSET
	.comm	_EFUSE_XTAL_SEL,4,2             ## @EFUSE_XTAL_SEL
	.comm	_ATH10K_HW_REFCLK_COUNT,4,2     ## @ATH10K_HW_REFCLK_COUNT
	.comm	_BB_PLL_CONFIG_OFFSET,4,2       ## @BB_PLL_CONFIG_OFFSET
	.comm	_BB_PLL_CONFIG_FRAC_MASK,4,2    ## @BB_PLL_CONFIG_FRAC_MASK
	.comm	_BB_PLL_CONFIG_OUTDIV_MASK,4,2  ## @BB_PLL_CONFIG_OUTDIV_MASK
	.comm	_BB_PLL_CONFIG_FRAC,4,2         ## @BB_PLL_CONFIG_FRAC
	.comm	_BB_PLL_CONFIG_OUTDIV,4,2       ## @BB_PLL_CONFIG_OUTDIV
	.comm	_RTC_WMAC_BASE_ADDRESS,4,2      ## @RTC_WMAC_BASE_ADDRESS
	.comm	_WLAN_PLL_SETTLE_OFFSET,4,2     ## @WLAN_PLL_SETTLE_OFFSET
	.comm	_WLAN_PLL_SETTLE_TIME_MASK,4,2  ## @WLAN_PLL_SETTLE_TIME_MASK
	.comm	_WLAN_PLL_SETTLE_TIME,4,2       ## @WLAN_PLL_SETTLE_TIME
	.comm	_SOC_CORE_CLK_CTRL_OFFSET,4,2   ## @SOC_CORE_CLK_CTRL_OFFSET
	.comm	_SOC_CORE_CLK_CTRL_DIV_MASK,4,2 ## @SOC_CORE_CLK_CTRL_DIV_MASK
	.comm	_SOC_CORE_CLK_CTRL_DIV,4,2      ## @SOC_CORE_CLK_CTRL_DIV
	.comm	_WLAN_PLL_CONTROL_OFFSET,4,2    ## @WLAN_PLL_CONTROL_OFFSET
	.comm	_WLAN_PLL_CONTROL_REFDIV,4,2    ## @WLAN_PLL_CONTROL_REFDIV
	.comm	_WLAN_PLL_CONTROL_DIV,4,2       ## @WLAN_PLL_CONTROL_DIV
	.comm	_WLAN_PLL_CONTROL_NOPWD,4,2     ## @WLAN_PLL_CONTROL_NOPWD
	.comm	_RTC_SYNC_STATUS_OFFSET,4,2     ## @RTC_SYNC_STATUS_OFFSET
	.comm	_RTC_SYNC_STATUS_PLL_CHANGING,4,2 ## @RTC_SYNC_STATUS_PLL_CHANGING
	.comm	_WLAN_PLL_CONTROL_BYPASS_MASK,4,2 ## @WLAN_PLL_CONTROL_BYPASS_MASK
	.comm	_WLAN_PLL_CONTROL_BYPASS,4,2    ## @WLAN_PLL_CONTROL_BYPASS
	.comm	_SOC_CPU_CLOCK_OFFSET,4,2       ## @SOC_CPU_CLOCK_OFFSET
	.comm	_SOC_CPU_CLOCK_STANDARD_MASK,4,2 ## @SOC_CPU_CLOCK_STANDARD_MASK
	.comm	_SOC_CPU_CLOCK_STANDARD,4,2     ## @SOC_CPU_CLOCK_STANDARD
	.comm	_WLAN_PLL_CONTROL_NOPWD_MASK,4,2 ## @WLAN_PLL_CONTROL_NOPWD_MASK
	.no_dead_strip	_ath10k_hw_qca6174_enable_pll_clock
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath10k_hw_qca6174_enable_pll_clock
_ath10k_hw_qca6174_enable_pll_clock:    ; @ath10k_hw_qca6174_enable_pll_clock
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	ldr	x8, [x0]
	ldr	x22, [x8]
	cbz	x22, LBB0_14
; %bb.1:
	ldr	x21, [x8, #8]
	cbz	x21, LBB0_14
; %bb.2:
	ldr	x20, [x8, #16]
	cbz	x20, LBB0_14
; %bb.3:
	mov	x19, x0
Lloh0:
	adrp	x25, _RTC_SOC_BASE_ADDRESS@GOTPAGE
Lloh1:
	ldr	x25, [x25, _RTC_SOC_BASE_ADDRESS@GOTPAGEOFF]
	ldr	w8, [x25]
Lloh2:
	adrp	x9, _EFUSE_OFFSET@GOTPAGE
Lloh3:
	ldr	x9, [x9, _EFUSE_OFFSET@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
	orr	w1, w9, w8
	add	x2, sp, #12
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.4:
	ldr	w0, [sp, #12]
Lloh5:
	adrp	x23, _EFUSE_XTAL_SEL@GOTPAGE
Lloh6:
	ldr	x23, [x23, _EFUSE_XTAL_SEL@GOTPAGEOFF]
	ldr	w1, [x23]
	bl	_MS
Lloh7:
	adrp	x8, _ATH10K_HW_REFCLK_COUNT@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ATH10K_HW_REFCLK_COUNT@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	cmp	w0, w8
	b.gt	LBB0_14
; %bb.5:
	ldr	x26, [x19, #16]
	ldr	w0, [sp, #12]
	ldr	w1, [x23]
	bl	_MS
	mov	x24, x0
	ldr	w8, [x25]
Lloh10:
	adrp	x9, _BB_PLL_CONFIG_OFFSET@GOTPAGE
Lloh11:
	ldr	x9, [x9, _BB_PLL_CONFIG_OFFSET@GOTPAGEOFF]
Lloh12:
	ldr	w9, [x9]
	orr	w23, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.6:
	sxtw	x27, w24
Lloh13:
	adrp	x8, _BB_PLL_CONFIG_FRAC_MASK@GOTPAGE
Lloh14:
	ldr	x8, [x8, _BB_PLL_CONFIG_FRAC_MASK@GOTPAGEOFF]
Lloh15:
	adrp	x9, _BB_PLL_CONFIG_OUTDIV_MASK@GOTPAGE
Lloh16:
	ldr	x9, [x9, _BB_PLL_CONFIG_OUTDIV_MASK@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
Lloh18:
	ldr	w9, [x9]
	orr	w8, w9, w8
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
	mov	w8, #20
	madd	x28, x27, x8, x26
	ldr	w0, [x28]
Lloh19:
	adrp	x8, _BB_PLL_CONFIG_FRAC@GOTPAGE
Lloh20:
	ldr	x8, [x8, _BB_PLL_CONFIG_FRAC@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	bl	_SM
	mov	x24, x0
	ldr	w0, [x28, #4]
Lloh22:
	adrp	x8, _BB_PLL_CONFIG_OUTDIV@GOTPAGE
Lloh23:
	ldr	x8, [x8, _BB_PLL_CONFIG_OUTDIV@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	bl	_SM
	orr	w8, w0, w24
	ldr	w9, [sp, #12]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_bmi_write_soc_reg
	cbnz	w0, LBB0_14
; %bb.7:
Lloh25:
	adrp	x24, _RTC_WMAC_BASE_ADDRESS@GOTPAGE
Lloh26:
	ldr	x24, [x24, _RTC_WMAC_BASE_ADDRESS@GOTPAGEOFF]
	ldr	w8, [x24]
Lloh27:
	adrp	x9, _WLAN_PLL_SETTLE_OFFSET@GOTPAGE
Lloh28:
	ldr	x9, [x9, _WLAN_PLL_SETTLE_OFFSET@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w23, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.8:
Lloh30:
	adrp	x8, _WLAN_PLL_SETTLE_TIME_MASK@GOTPAGE
Lloh31:
	ldr	x8, [x8, _WLAN_PLL_SETTLE_TIME_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
	mov	w8, #20
	madd	x8, x27, x8, x26
	ldr	w0, [x8, #8]
Lloh33:
	adrp	x8, _WLAN_PLL_SETTLE_TIME@GOTPAGE
Lloh34:
	ldr	x8, [x8, _WLAN_PLL_SETTLE_TIME@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	bl	_SM
	ldr	w8, [sp, #12]
	orr	w2, w8, w0
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_bmi_write_soc_reg
	cbnz	w0, LBB0_14
; %bb.9:
	ldr	w8, [x25]
Lloh36:
	adrp	x9, _SOC_CORE_CLK_CTRL_OFFSET@GOTPAGE
Lloh37:
	ldr	x9, [x9, _SOC_CORE_CLK_CTRL_OFFSET@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w23, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.10:
Lloh39:
	adrp	x8, _SOC_CORE_CLK_CTRL_DIV_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _SOC_CORE_CLK_CTRL_DIV_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
Lloh42:
	adrp	x8, _SOC_CORE_CLK_CTRL_DIV@GOTPAGE
Lloh43:
	ldr	x8, [x8, _SOC_CORE_CLK_CTRL_DIV@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
	mov	w28, #1
	mov	w0, #1
	bl	_SM
	ldr	w8, [sp, #12]
	orr	w2, w8, w0
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x23
	bl	_ath10k_bmi_write_soc_reg
	cbnz	w0, LBB0_14
; %bb.11:
	mov	x23, x26
	str	w28, [sp, #8]
	add	x2, sp, #8
	mov	x0, x19
	mov	x1, x22
	mov	w3, #4
	bl	_ath10k_bmi_write_memory
	cbnz	w0, LBB0_14
; %bb.12:
	ldr	w8, [x24]
Lloh45:
	adrp	x26, _WLAN_PLL_CONTROL_OFFSET@GOTPAGE
Lloh46:
	ldr	x26, [x26, _WLAN_PLL_CONTROL_OFFSET@GOTPAGEOFF]
	ldr	w9, [x26]
	orr	w22, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.13:
	mov	w8, #20
	madd	x27, x27, x8, x23
	ldr	w0, [x27, #12]
Lloh47:
	adrp	x8, _WLAN_PLL_CONTROL_REFDIV@GOTPAGE
Lloh48:
	ldr	x8, [x8, _WLAN_PLL_CONTROL_REFDIV@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
	bl	_SM
	mov	x23, x0
	ldr	w0, [x27, #16]
Lloh50:
	adrp	x8, _WLAN_PLL_CONTROL_DIV@GOTPAGE
Lloh51:
	ldr	x8, [x8, _WLAN_PLL_CONTROL_DIV@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
	bl	_SM
	orr	w23, w0, w23
Lloh53:
	adrp	x8, _WLAN_PLL_CONTROL_NOPWD@GOTPAGE
Lloh54:
	ldr	x8, [x8, _WLAN_PLL_CONTROL_NOPWD@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	orr	w8, w23, w0
	ldr	w9, [sp, #12]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_write_soc_reg
	cbz	w0, LBB0_16
LBB0_14:
Lloh56:
	adrp	x8, _EINVAL@GOTPAGE
Lloh57:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh58:
	ldr	w8, [x8]
	neg	w0, w8
LBB0_15:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
LBB0_16:
	mov	w23, #34465
	movk	w23, #1, lsl #16
Lloh59:
	adrp	x9, _RTC_SYNC_STATUS_OFFSET@GOTPAGE
Lloh60:
	ldr	x9, [x9, _RTC_SYNC_STATUS_OFFSET@GOTPAGEOFF]
	ldr	w8, [x24]
Lloh61:
	ldr	w9, [x9]
	orr	w22, w9, w8
Lloh62:
	adrp	x27, _RTC_SYNC_STATUS_PLL_CHANGING@GOTPAGE
Lloh63:
	ldr	x27, [x27, _RTC_SYNC_STATUS_PLL_CHANGING@GOTPAGEOFF]
	mov	w28, #34465
	movk	w28, #1, lsl #16
LBB0_17:                                ; =>This Inner Loop Header: Depth=1
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.18:                               ;   in Loop: Header=BB0_17 Depth=1
	ldr	w0, [sp, #12]
	ldr	w1, [x27]
	bl	_MS
	cbz	w0, LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_17 Depth=1
	mov	w0, #10
	bl	_udelay
	sub	w28, w28, #1
	cmp	w28, #1
	b.hi	LBB0_17
LBB0_20:
	ldr	w0, [sp, #12]
	ldr	w1, [x27]
	bl	_MS
	cbnz	w0, LBB0_14
; %bb.21:
	ldr	w8, [x24]
	ldr	w9, [x26]
	orr	w22, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.22:
Lloh64:
	adrp	x8, _WLAN_PLL_CONTROL_BYPASS_MASK@GOTPAGE
Lloh65:
	ldr	x8, [x8, _WLAN_PLL_CONTROL_BYPASS_MASK@GOTPAGEOFF]
Lloh66:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
Lloh67:
	adrp	x8, _WLAN_PLL_CONTROL_BYPASS@GOTPAGE
Lloh68:
	ldr	x8, [x8, _WLAN_PLL_CONTROL_BYPASS@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	bl	_SM
	ldr	w8, [sp, #12]
	orr	w2, w8, w0
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_write_soc_reg
	cbnz	w0, LBB0_14
; %bb.23:
	ldr	w8, [x24]
Lloh70:
	adrp	x9, _RTC_SYNC_STATUS_OFFSET@GOTPAGE
Lloh71:
	ldr	x9, [x9, _RTC_SYNC_STATUS_OFFSET@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	orr	w22, w9, w8
LBB0_24:                                ; =>This Inner Loop Header: Depth=1
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.25:                               ;   in Loop: Header=BB0_24 Depth=1
	ldr	w0, [sp, #12]
	ldr	w1, [x27]
	bl	_MS
	cbz	w0, LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_24 Depth=1
	mov	w0, #10
	bl	_udelay
	sub	w23, w23, #1
	cmp	w23, #1
	b.hi	LBB0_24
LBB0_27:
	ldr	w0, [sp, #12]
	ldr	w1, [x27]
	bl	_MS
	cbnz	w0, LBB0_14
; %bb.28:
	ldr	w8, [x25]
Lloh73:
	adrp	x9, _SOC_CPU_CLOCK_OFFSET@GOTPAGE
Lloh74:
	ldr	x9, [x9, _SOC_CPU_CLOCK_OFFSET@GOTPAGEOFF]
Lloh75:
	ldr	w9, [x9]
	orr	w22, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.29:
Lloh76:
	adrp	x8, _SOC_CPU_CLOCK_STANDARD_MASK@GOTPAGE
Lloh77:
	ldr	x8, [x8, _SOC_CPU_CLOCK_STANDARD_MASK@GOTPAGEOFF]
Lloh78:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w8, w9, w8
	str	w8, [sp, #12]
Lloh79:
	adrp	x8, _SOC_CPU_CLOCK_STANDARD@GOTPAGE
Lloh80:
	ldr	x8, [x8, _SOC_CPU_CLOCK_STANDARD@GOTPAGEOFF]
Lloh81:
	ldr	w1, [x8]
	mov	w0, #1
	bl	_SM
	ldr	w8, [sp, #12]
	orr	w2, w8, w0
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_write_soc_reg
	cbnz	w0, LBB0_14
; %bb.30:
	ldr	w8, [x24]
	ldr	w9, [x26]
	orr	w22, w9, w8
	add	x2, sp, #12
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_read_soc_reg
	cbnz	w0, LBB0_14
; %bb.31:
Lloh82:
	adrp	x8, _WLAN_PLL_CONTROL_NOPWD_MASK@GOTPAGE
Lloh83:
	ldr	x8, [x8, _WLAN_PLL_CONTROL_NOPWD_MASK@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	ldr	w9, [sp, #12]
	bic	w2, w9, w8
	str	w2, [sp, #12]
	mov	x0, x19
	mov	x1, x22
	bl	_ath10k_bmi_write_soc_reg
	cbnz	w0, LBB0_14
; %bb.32:
	mov	w8, #1
	str	w8, [sp, #8]
	add	x2, sp, #8
	mov	x0, x19
	mov	x1, x21
	mov	w3, #4
	bl	_ath10k_bmi_write_memory
	cbnz	w0, LBB0_14
; %bb.33:
	add	x2, x19, #8
	mov	x0, x19
	mov	x1, x20
	mov	w3, #4
	bl	_ath10k_bmi_write_memory
	cbnz	w0, LBB0_14
	b	LBB0_15
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh17
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_RTC_SOC_BASE_ADDRESS,4,2       ; @RTC_SOC_BASE_ADDRESS
	.comm	_EFUSE_OFFSET,4,2               ; @EFUSE_OFFSET
	.comm	_EFUSE_XTAL_SEL,4,2             ; @EFUSE_XTAL_SEL
	.comm	_ATH10K_HW_REFCLK_COUNT,4,2     ; @ATH10K_HW_REFCLK_COUNT
	.comm	_BB_PLL_CONFIG_OFFSET,4,2       ; @BB_PLL_CONFIG_OFFSET
	.comm	_BB_PLL_CONFIG_FRAC_MASK,4,2    ; @BB_PLL_CONFIG_FRAC_MASK
	.comm	_BB_PLL_CONFIG_OUTDIV_MASK,4,2  ; @BB_PLL_CONFIG_OUTDIV_MASK
	.comm	_BB_PLL_CONFIG_FRAC,4,2         ; @BB_PLL_CONFIG_FRAC
	.comm	_BB_PLL_CONFIG_OUTDIV,4,2       ; @BB_PLL_CONFIG_OUTDIV
	.comm	_RTC_WMAC_BASE_ADDRESS,4,2      ; @RTC_WMAC_BASE_ADDRESS
	.comm	_WLAN_PLL_SETTLE_OFFSET,4,2     ; @WLAN_PLL_SETTLE_OFFSET
	.comm	_WLAN_PLL_SETTLE_TIME_MASK,4,2  ; @WLAN_PLL_SETTLE_TIME_MASK
	.comm	_WLAN_PLL_SETTLE_TIME,4,2       ; @WLAN_PLL_SETTLE_TIME
	.comm	_SOC_CORE_CLK_CTRL_OFFSET,4,2   ; @SOC_CORE_CLK_CTRL_OFFSET
	.comm	_SOC_CORE_CLK_CTRL_DIV_MASK,4,2 ; @SOC_CORE_CLK_CTRL_DIV_MASK
	.comm	_SOC_CORE_CLK_CTRL_DIV,4,2      ; @SOC_CORE_CLK_CTRL_DIV
	.comm	_WLAN_PLL_CONTROL_OFFSET,4,2    ; @WLAN_PLL_CONTROL_OFFSET
	.comm	_WLAN_PLL_CONTROL_REFDIV,4,2    ; @WLAN_PLL_CONTROL_REFDIV
	.comm	_WLAN_PLL_CONTROL_DIV,4,2       ; @WLAN_PLL_CONTROL_DIV
	.comm	_WLAN_PLL_CONTROL_NOPWD,4,2     ; @WLAN_PLL_CONTROL_NOPWD
	.comm	_RTC_SYNC_STATUS_OFFSET,4,2     ; @RTC_SYNC_STATUS_OFFSET
	.comm	_RTC_SYNC_STATUS_PLL_CHANGING,4,2 ; @RTC_SYNC_STATUS_PLL_CHANGING
	.comm	_WLAN_PLL_CONTROL_BYPASS_MASK,4,2 ; @WLAN_PLL_CONTROL_BYPASS_MASK
	.comm	_WLAN_PLL_CONTROL_BYPASS,4,2    ; @WLAN_PLL_CONTROL_BYPASS
	.comm	_SOC_CPU_CLOCK_OFFSET,4,2       ; @SOC_CPU_CLOCK_OFFSET
	.comm	_SOC_CPU_CLOCK_STANDARD_MASK,4,2 ; @SOC_CPU_CLOCK_STANDARD_MASK
	.comm	_SOC_CPU_CLOCK_STANDARD,4,2     ; @SOC_CPU_CLOCK_STANDARD
	.comm	_WLAN_PLL_CONTROL_NOPWD_MASK,4,2 ; @WLAN_PLL_CONTROL_NOPWD_MASK
	.no_dead_strip	_ath10k_hw_qca6174_enable_pll_clock
.subsections_via_symbols
