	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_wcn36xx_dxe_init               ## -- Begin function wcn36xx_dxe_init
	.p2align	4, 0x90
_wcn36xx_dxe_init:                      ## @wcn36xx_dxe_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	movq	_WCN36XX_DXE_REG_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_WCN36XX_DXE_REG_CSR_RESET@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_INT_CH3_MASK@GOTPCREL(%rip), %rax
	movq	_WCN36XX_DXE_INT_CH1_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	shll	$16, %edx
	movq	_WCN36XX_DXE_INT_CH0_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	_WCN36XX_DXE_INT_CH4_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	cmpq	$0, 48(%r12)
	jne	LBB0_1
## %bb.2:
	movq	_WCN36XX_CCU_DXE_INT_SELECT_RIVA@GOTPCREL(%rip), %rax
	jmp	LBB0_3
LBB0_1:
	movq	_WCN36XX_CCU_DXE_INT_SELECT_PRONTO@GOTPCREL(%rip), %rax
LBB0_3:
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_wcn36xx_ccu_write_register
	movl	8(%r12), %edi
	movq	%r12, %rsi
	callq	_wcn36xx_dxe_init_descs
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %ebx
	movl	8(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_16
LBB0_5:
	leaq	44(%r12), %rsi
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_init_tx_bd
	movq	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	(%r12), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_CH_DEST_ADDR_TX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WCN36XX_DXE_WQ_TX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_REG_CH_EN@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_read_register
	movq	_WCN36XX_INT_MASK_CHAN_TX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_enable_ch_int
	movl	8(%r12), %edi
	leaq	16(%r12), %r14
	movq	%r14, %rsi
	callq	_wcn36xx_dxe_init_descs
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movl	%eax, %ebx
	movl	8(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_15
LBB0_7:
	leaq	40(%r12), %rsi
	movq	%r14, %rdi
	callq	_wcn36xx_dxe_init_tx_bd
	movq	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	16(%r12), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_CH_DEST_ADDR_TX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WCN36XX_DXE_WQ_TX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movl	(%r15), %esi
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_read_register
	movq	_WCN36XX_INT_MASK_CHAN_TX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_enable_ch_int
	movl	8(%r12), %edi
	leaq	24(%r12), %r15
	movq	%r15, %rsi
	callq	_wcn36xx_dxe_init_descs
	testl	%eax, %eax
	je	LBB0_9
## %bb.8:
	movl	%eax, %ebx
	movl	8(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	jmp	LBB0_14
LBB0_9:
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_wcn36xx_dxe_ch_alloc_skb
	movq	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	24(%r12), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_CH_SRC_ADDR_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WCN36XX_DXE_WQ_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_CH_DEST_ADDR_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	24(%r12), %rax
	movq	8(%rax), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_REG_CTL_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WCN36XX_DXE_CH_DEFAULT_CTL_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_INT_MASK_CHAN_RX_L@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_enable_ch_int
	movl	8(%r12), %edi
	leaq	32(%r12), %r13
	movq	%r13, %rsi
	callq	_wcn36xx_dxe_init_descs
	testl	%eax, %eax
	je	LBB0_11
## %bb.10:
	movl	%eax, %ebx
	movl	8(%r12), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
LBB0_13:
	movl	8(%r12), %edi
	movq	%r15, %rsi
	callq	_wcn36xx_dxe_deinit_descs
LBB0_14:
	movl	8(%r12), %edi
	movq	%r14, %rsi
	callq	_wcn36xx_dxe_deinit_descs
LBB0_15:
	movl	8(%r12), %edi
	movq	%r12, %rsi
	callq	_wcn36xx_dxe_deinit_descs
LBB0_16:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_11:
	movq	%r12, %rdi
	movq	%r13, %rsi
	callq	_wcn36xx_dxe_ch_alloc_skb
	movq	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	32(%r12), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_CH_SRC_ADDR_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WCN36XX_DXE_WQ_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_CH_DEST_ADDR_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	32(%r12), %rax
	movq	8(%rax), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_DXE_REG_CTL_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_WCN36XX_DXE_CH_DEFAULT_CTL_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_write_register
	movq	_WCN36XX_INT_MASK_CHAN_RX_H@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_enable_ch_int
	movq	%r12, %rdi
	callq	_wcn36xx_dxe_request_irqs
	xorl	%ebx, %ebx
	testl	%eax, %eax
	jns	LBB0_16
## %bb.12:
	movl	8(%r12), %edi
	movq	%r13, %rsi
	movl	%eax, %ebx
	callq	_wcn36xx_dxe_deinit_descs
	jmp	LBB0_13
	.cfi_endproc
                                        ## -- End function
	.comm	_WCN36XX_DXE_REG_RESET,4,2      ## @WCN36XX_DXE_REG_RESET
	.comm	_WCN36XX_DXE_REG_CSR_RESET,4,2  ## @WCN36XX_DXE_REG_CSR_RESET
	.comm	_WCN36XX_DXE_INT_CH3_MASK,4,2   ## @WCN36XX_DXE_INT_CH3_MASK
	.comm	_WCN36XX_DXE_INT_CH1_MASK,4,2   ## @WCN36XX_DXE_INT_CH1_MASK
	.comm	_WCN36XX_DXE_INT_CH0_MASK,4,2   ## @WCN36XX_DXE_INT_CH0_MASK
	.comm	_WCN36XX_DXE_INT_CH4_MASK,4,2   ## @WCN36XX_DXE_INT_CH4_MASK
	.comm	_WCN36XX_CCU_DXE_INT_SELECT_PRONTO,4,2 ## @WCN36XX_CCU_DXE_INT_SELECT_PRONTO
	.comm	_WCN36XX_CCU_DXE_INT_SELECT_RIVA,4,2 ## @WCN36XX_CCU_DXE_INT_SELECT_RIVA
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Error allocating descriptor\n"

	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L,4,2 ## @WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_TX_L,4,2 ## @WCN36XX_DXE_CH_DEST_ADDR_TX_L
	.comm	_WCN36XX_DXE_WQ_TX_L,4,2        ## @WCN36XX_DXE_WQ_TX_L
	.comm	_WCN36XX_DXE_REG_CH_EN,4,2      ## @WCN36XX_DXE_REG_CH_EN
	.comm	_WCN36XX_INT_MASK_CHAN_TX_L,4,2 ## @WCN36XX_INT_MASK_CHAN_TX_L
	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H,4,2 ## @WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_TX_H,4,2 ## @WCN36XX_DXE_CH_DEST_ADDR_TX_H
	.comm	_WCN36XX_DXE_WQ_TX_H,4,2        ## @WCN36XX_DXE_WQ_TX_H
	.comm	_WCN36XX_INT_MASK_CHAN_TX_H,4,2 ## @WCN36XX_INT_MASK_CHAN_TX_H
	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L,4,2 ## @WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L
	.comm	_WCN36XX_DXE_CH_SRC_ADDR_RX_L,4,2 ## @WCN36XX_DXE_CH_SRC_ADDR_RX_L
	.comm	_WCN36XX_DXE_WQ_RX_L,4,2        ## @WCN36XX_DXE_WQ_RX_L
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_RX_L,4,2 ## @WCN36XX_DXE_CH_DEST_ADDR_RX_L
	.comm	_WCN36XX_DXE_REG_CTL_RX_L,4,2   ## @WCN36XX_DXE_REG_CTL_RX_L
	.comm	_WCN36XX_DXE_CH_DEFAULT_CTL_RX_L,4,2 ## @WCN36XX_DXE_CH_DEFAULT_CTL_RX_L
	.comm	_WCN36XX_INT_MASK_CHAN_RX_L,4,2 ## @WCN36XX_INT_MASK_CHAN_RX_L
	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H,4,2 ## @WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H
	.comm	_WCN36XX_DXE_CH_SRC_ADDR_RX_H,4,2 ## @WCN36XX_DXE_CH_SRC_ADDR_RX_H
	.comm	_WCN36XX_DXE_WQ_RX_H,4,2        ## @WCN36XX_DXE_WQ_RX_H
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_RX_H,4,2 ## @WCN36XX_DXE_CH_DEST_ADDR_RX_H
	.comm	_WCN36XX_DXE_REG_CTL_RX_H,4,2   ## @WCN36XX_DXE_REG_CTL_RX_H
	.comm	_WCN36XX_DXE_CH_DEFAULT_CTL_RX_H,4,2 ## @WCN36XX_DXE_CH_DEFAULT_CTL_RX_H
	.comm	_WCN36XX_INT_MASK_CHAN_RX_H,4,2 ## @WCN36XX_INT_MASK_CHAN_RX_H
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_wcn36xx_dxe_init               ; -- Begin function wcn36xx_dxe_init
	.p2align	2
_wcn36xx_dxe_init:                      ; @wcn36xx_dxe_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _WCN36XX_DXE_REG_RESET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _WCN36XX_DXE_REG_RESET@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
Lloh3:
	adrp	x8, _WCN36XX_DXE_REG_CSR_RESET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _WCN36XX_DXE_REG_CSR_RESET@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	bl	_wcn36xx_dxe_write_register
Lloh6:
	adrp	x8, _WCN36XX_DXE_INT_CH3_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _WCN36XX_DXE_INT_CH3_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
Lloh9:
	adrp	x9, _WCN36XX_DXE_INT_CH1_MASK@GOTPAGE
Lloh10:
	ldr	x9, [x9, _WCN36XX_DXE_INT_CH1_MASK@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh12:
	adrp	x9, _WCN36XX_DXE_INT_CH0_MASK@GOTPAGE
Lloh13:
	ldr	x9, [x9, _WCN36XX_DXE_INT_CH0_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
Lloh15:
	adrp	x10, _WCN36XX_DXE_INT_CH4_MASK@GOTPAGE
Lloh16:
	ldr	x10, [x10, _WCN36XX_DXE_INT_CH4_MASK@GOTPAGEOFF]
	orr	w8, w9, w8, lsl #16
Lloh17:
	ldr	w9, [x10]
	orr	w2, w8, w9
	str	w2, [sp, #12]
Lloh18:
	adrp	x8, _WCN36XX_CCU_DXE_INT_SELECT_RIVA@GOTPAGE
Lloh19:
	ldr	x8, [x8, _WCN36XX_CCU_DXE_INT_SELECT_RIVA@GOTPAGEOFF]
	ldr	x9, [x19, #48]
Lloh20:
	adrp	x10, _WCN36XX_CCU_DXE_INT_SELECT_PRONTO@GOTPAGE
Lloh21:
	ldr	x10, [x10, _WCN36XX_CCU_DXE_INT_SELECT_PRONTO@GOTPAGEOFF]
	cmp	x9, #0
	csel	x8, x8, x10, eq
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wcn36xx_ccu_write_register
	ldr	w0, [x19, #8]
	mov	x1, x19
	bl	_wcn36xx_dxe_init_descs
	cbz	w0, LBB0_2
; %bb.1:
	mov	x22, x0
	ldr	w0, [x19, #8]
Lloh22:
	adrp	x1, l_.str@PAGE
Lloh23:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_11
LBB0_2:
	add	x1, x19, #44
	mov	x0, x19
	bl	_wcn36xx_dxe_init_tx_bd
Lloh24:
	adrp	x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L@GOTPAGE
Lloh25:
	ldr	x8, [x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	ldr	x8, [x19]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh27:
	adrp	x8, _WCN36XX_DXE_CH_DEST_ADDR_TX_L@GOTPAGE
Lloh28:
	ldr	x8, [x8, _WCN36XX_DXE_CH_DEST_ADDR_TX_L@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
Lloh30:
	adrp	x8, _WCN36XX_DXE_WQ_TX_L@GOTPAGE
Lloh31:
	ldr	x8, [x8, _WCN36XX_DXE_WQ_TX_L@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh33:
	adrp	x21, _WCN36XX_DXE_REG_CH_EN@GOTPAGE
Lloh34:
	ldr	x21, [x21, _WCN36XX_DXE_REG_CH_EN@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_wcn36xx_dxe_read_register
Lloh35:
	adrp	x8, _WCN36XX_INT_MASK_CHAN_TX_L@GOTPAGE
Lloh36:
	ldr	x8, [x8, _WCN36XX_INT_MASK_CHAN_TX_L@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_enable_ch_int
	ldr	w0, [x19, #8]
	add	x20, x19, #16
	mov	x1, x20
	bl	_wcn36xx_dxe_init_descs
	cbz	w0, LBB0_4
; %bb.3:
	mov	x22, x0
	ldr	w0, [x19, #8]
Lloh38:
	adrp	x1, l_.str@PAGE
Lloh39:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_10
LBB0_4:
	add	x1, x19, #40
	mov	x0, x20
	bl	_wcn36xx_dxe_init_tx_bd
Lloh40:
	adrp	x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H@GOTPAGE
Lloh41:
	ldr	x8, [x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh43:
	adrp	x8, _WCN36XX_DXE_CH_DEST_ADDR_TX_H@GOTPAGE
Lloh44:
	ldr	x8, [x8, _WCN36XX_DXE_CH_DEST_ADDR_TX_H@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	adrp	x8, _WCN36XX_DXE_WQ_TX_H@GOTPAGE
Lloh47:
	ldr	x8, [x8, _WCN36XX_DXE_WQ_TX_H@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_wcn36xx_dxe_read_register
Lloh49:
	adrp	x8, _WCN36XX_INT_MASK_CHAN_TX_H@GOTPAGE
Lloh50:
	ldr	x8, [x8, _WCN36XX_INT_MASK_CHAN_TX_H@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_enable_ch_int
	ldr	w0, [x19, #8]
	add	x21, x19, #24
	mov	x1, x21
	bl	_wcn36xx_dxe_init_descs
	cbz	w0, LBB0_6
; %bb.5:
	mov	x22, x0
	ldr	w0, [x19, #8]
Lloh52:
	adrp	x1, l_.str@PAGE
Lloh53:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_9
LBB0_6:
	mov	x0, x19
	mov	x1, x21
	bl	_wcn36xx_dxe_ch_alloc_skb
Lloh54:
	adrp	x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L@GOTPAGE
Lloh55:
	ldr	x8, [x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L@GOTPAGEOFF]
Lloh56:
	ldr	w1, [x8]
	ldr	x8, [x19, #24]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh57:
	adrp	x8, _WCN36XX_DXE_CH_SRC_ADDR_RX_L@GOTPAGE
Lloh58:
	ldr	x8, [x8, _WCN36XX_DXE_CH_SRC_ADDR_RX_L@GOTPAGEOFF]
Lloh59:
	ldr	w1, [x8]
Lloh60:
	adrp	x8, _WCN36XX_DXE_WQ_RX_L@GOTPAGE
Lloh61:
	ldr	x8, [x8, _WCN36XX_DXE_WQ_RX_L@GOTPAGEOFF]
Lloh62:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh63:
	adrp	x8, _WCN36XX_DXE_CH_DEST_ADDR_RX_L@GOTPAGE
Lloh64:
	ldr	x8, [x8, _WCN36XX_DXE_CH_DEST_ADDR_RX_L@GOTPAGEOFF]
Lloh65:
	ldr	w1, [x8]
	ldr	x8, [x19, #24]
	ldr	x8, [x8, #8]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh66:
	adrp	x8, _WCN36XX_DXE_REG_CTL_RX_L@GOTPAGE
Lloh67:
	ldr	x8, [x8, _WCN36XX_DXE_REG_CTL_RX_L@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
Lloh69:
	adrp	x8, _WCN36XX_DXE_CH_DEFAULT_CTL_RX_L@GOTPAGE
Lloh70:
	ldr	x8, [x8, _WCN36XX_DXE_CH_DEFAULT_CTL_RX_L@GOTPAGEOFF]
Lloh71:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh72:
	adrp	x8, _WCN36XX_INT_MASK_CHAN_RX_L@GOTPAGE
Lloh73:
	ldr	x8, [x8, _WCN36XX_INT_MASK_CHAN_RX_L@GOTPAGEOFF]
Lloh74:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_enable_ch_int
	ldr	w0, [x19, #8]
	add	x23, x19, #32
	mov	x1, x23
	bl	_wcn36xx_dxe_init_descs
	cbz	w0, LBB0_12
; %bb.7:
	mov	x22, x0
	ldr	w0, [x19, #8]
Lloh75:
	adrp	x1, l_.str@PAGE
Lloh76:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
LBB0_8:
	ldr	w0, [x19, #8]
	mov	x1, x21
	bl	_wcn36xx_dxe_deinit_descs
LBB0_9:
	ldr	w0, [x19, #8]
	mov	x1, x20
	bl	_wcn36xx_dxe_deinit_descs
LBB0_10:
	ldr	w0, [x19, #8]
	mov	x1, x19
	bl	_wcn36xx_dxe_deinit_descs
LBB0_11:
	mov	x0, x22
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_12:
	mov	x0, x19
	mov	x1, x23
	bl	_wcn36xx_dxe_ch_alloc_skb
Lloh77:
	adrp	x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H@GOTPAGE
Lloh78:
	ldr	x8, [x8, _WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H@GOTPAGEOFF]
Lloh79:
	ldr	w1, [x8]
	ldr	x8, [x19, #32]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh80:
	adrp	x8, _WCN36XX_DXE_CH_SRC_ADDR_RX_H@GOTPAGE
Lloh81:
	ldr	x8, [x8, _WCN36XX_DXE_CH_SRC_ADDR_RX_H@GOTPAGEOFF]
Lloh82:
	ldr	w1, [x8]
Lloh83:
	adrp	x8, _WCN36XX_DXE_WQ_RX_H@GOTPAGE
Lloh84:
	ldr	x8, [x8, _WCN36XX_DXE_WQ_RX_H@GOTPAGEOFF]
Lloh85:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh86:
	adrp	x8, _WCN36XX_DXE_CH_DEST_ADDR_RX_H@GOTPAGE
Lloh87:
	ldr	x8, [x8, _WCN36XX_DXE_CH_DEST_ADDR_RX_H@GOTPAGEOFF]
Lloh88:
	ldr	w1, [x8]
	ldr	x8, [x19, #32]
	ldr	x8, [x8, #8]
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh89:
	adrp	x8, _WCN36XX_DXE_REG_CTL_RX_H@GOTPAGE
Lloh90:
	ldr	x8, [x8, _WCN36XX_DXE_REG_CTL_RX_H@GOTPAGEOFF]
Lloh91:
	ldr	w1, [x8]
Lloh92:
	adrp	x8, _WCN36XX_DXE_CH_DEFAULT_CTL_RX_H@GOTPAGE
Lloh93:
	ldr	x8, [x8, _WCN36XX_DXE_CH_DEFAULT_CTL_RX_H@GOTPAGEOFF]
Lloh94:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_write_register
Lloh95:
	adrp	x8, _WCN36XX_INT_MASK_CHAN_RX_H@GOTPAGE
Lloh96:
	ldr	x8, [x8, _WCN36XX_INT_MASK_CHAN_RX_H@GOTPAGEOFF]
Lloh97:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_wcn36xx_dxe_enable_ch_int
	mov	x0, x19
	bl	_wcn36xx_dxe_request_irqs
	tbnz	w0, #31, LBB0_14
; %bb.13:
	mov	w22, #0
	b	LBB0_11
LBB0_14:
	mov	x22, x0
	ldr	w0, [x19, #8]
	mov	x1, x23
	bl	_wcn36xx_dxe_deinit_descs
	b	LBB0_8
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpAdd	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpAdd	Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpAdd	Lloh75, Lloh76
	.loh AdrpLdrGotLdr	Lloh95, Lloh96, Lloh97
	.loh AdrpLdrGotLdr	Lloh92, Lloh93, Lloh94
	.loh AdrpLdrGotLdr	Lloh89, Lloh90, Lloh91
	.loh AdrpLdrGotLdr	Lloh86, Lloh87, Lloh88
	.loh AdrpLdrGotLdr	Lloh83, Lloh84, Lloh85
	.loh AdrpLdrGotLdr	Lloh80, Lloh81, Lloh82
	.loh AdrpLdrGotLdr	Lloh77, Lloh78, Lloh79
	.cfi_endproc
                                        ; -- End function
	.comm	_WCN36XX_DXE_REG_RESET,4,2      ; @WCN36XX_DXE_REG_RESET
	.comm	_WCN36XX_DXE_REG_CSR_RESET,4,2  ; @WCN36XX_DXE_REG_CSR_RESET
	.comm	_WCN36XX_DXE_INT_CH3_MASK,4,2   ; @WCN36XX_DXE_INT_CH3_MASK
	.comm	_WCN36XX_DXE_INT_CH1_MASK,4,2   ; @WCN36XX_DXE_INT_CH1_MASK
	.comm	_WCN36XX_DXE_INT_CH0_MASK,4,2   ; @WCN36XX_DXE_INT_CH0_MASK
	.comm	_WCN36XX_DXE_INT_CH4_MASK,4,2   ; @WCN36XX_DXE_INT_CH4_MASK
	.comm	_WCN36XX_CCU_DXE_INT_SELECT_PRONTO,4,2 ; @WCN36XX_CCU_DXE_INT_SELECT_PRONTO
	.comm	_WCN36XX_CCU_DXE_INT_SELECT_RIVA,4,2 ; @WCN36XX_CCU_DXE_INT_SELECT_RIVA
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Error allocating descriptor\n"

	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L,4,2 ; @WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_TX_L,4,2 ; @WCN36XX_DXE_CH_DEST_ADDR_TX_L
	.comm	_WCN36XX_DXE_WQ_TX_L,4,2        ; @WCN36XX_DXE_WQ_TX_L
	.comm	_WCN36XX_DXE_REG_CH_EN,4,2      ; @WCN36XX_DXE_REG_CH_EN
	.comm	_WCN36XX_INT_MASK_CHAN_TX_L,4,2 ; @WCN36XX_INT_MASK_CHAN_TX_L
	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H,4,2 ; @WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_TX_H,4,2 ; @WCN36XX_DXE_CH_DEST_ADDR_TX_H
	.comm	_WCN36XX_DXE_WQ_TX_H,4,2        ; @WCN36XX_DXE_WQ_TX_H
	.comm	_WCN36XX_INT_MASK_CHAN_TX_H,4,2 ; @WCN36XX_INT_MASK_CHAN_TX_H
	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L,4,2 ; @WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L
	.comm	_WCN36XX_DXE_CH_SRC_ADDR_RX_L,4,2 ; @WCN36XX_DXE_CH_SRC_ADDR_RX_L
	.comm	_WCN36XX_DXE_WQ_RX_L,4,2        ; @WCN36XX_DXE_WQ_RX_L
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_RX_L,4,2 ; @WCN36XX_DXE_CH_DEST_ADDR_RX_L
	.comm	_WCN36XX_DXE_REG_CTL_RX_L,4,2   ; @WCN36XX_DXE_REG_CTL_RX_L
	.comm	_WCN36XX_DXE_CH_DEFAULT_CTL_RX_L,4,2 ; @WCN36XX_DXE_CH_DEFAULT_CTL_RX_L
	.comm	_WCN36XX_INT_MASK_CHAN_RX_L,4,2 ; @WCN36XX_INT_MASK_CHAN_RX_L
	.comm	_WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H,4,2 ; @WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H
	.comm	_WCN36XX_DXE_CH_SRC_ADDR_RX_H,4,2 ; @WCN36XX_DXE_CH_SRC_ADDR_RX_H
	.comm	_WCN36XX_DXE_WQ_RX_H,4,2        ; @WCN36XX_DXE_WQ_RX_H
	.comm	_WCN36XX_DXE_CH_DEST_ADDR_RX_H,4,2 ; @WCN36XX_DXE_CH_DEST_ADDR_RX_H
	.comm	_WCN36XX_DXE_REG_CTL_RX_H,4,2   ; @WCN36XX_DXE_REG_CTL_RX_H
	.comm	_WCN36XX_DXE_CH_DEFAULT_CTL_RX_H,4,2 ; @WCN36XX_DXE_CH_DEFAULT_CTL_RX_H
	.comm	_WCN36XX_INT_MASK_CHAN_RX_H,4,2 ; @WCN36XX_INT_MASK_CHAN_RX_H
.subsections_via_symbols
