	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mobiveil_pcie_enable_msi
_mobiveil_pcie_enable_msi:              ## @mobiveil_pcie_enable_msi
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	movq	24(%rdi), %r14
	movq	_PCI_NUM_MSI@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 16(%rdi)
	movq	%r14, 8(%rdi)
	movq	%r14, %rdi
	callq	_lower_32_bits
	movq	_MSI_BASE_LO_OFFSET@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel_relaxed
	movq	%r14, %rdi
	callq	_upper_32_bits
	movq	_MSI_BASE_HI_OFFSET@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rsi
	addq	(%rbx), %rsi
	movl	%eax, %edi
	callq	_writel_relaxed
	movq	_MSI_SIZE_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%rbx), %rsi
	movl	$4096, %edi                     ## imm = 0x1000
	callq	_writel_relaxed
	movq	_MSI_ENABLE_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%rbx), %rsi
	movl	$1, %edi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_writel_relaxed                 ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_NUM_MSI,4,2                ## @PCI_NUM_MSI
	.comm	_MSI_BASE_LO_OFFSET,8,3         ## @MSI_BASE_LO_OFFSET
	.comm	_MSI_BASE_HI_OFFSET,8,3         ## @MSI_BASE_HI_OFFSET
	.comm	_MSI_SIZE_OFFSET,8,3            ## @MSI_SIZE_OFFSET
	.comm	_MSI_ENABLE_OFFSET,8,3          ## @MSI_ENABLE_OFFSET
	.no_dead_strip	_mobiveil_pcie_enable_msi
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mobiveil_pcie_enable_msi
_mobiveil_pcie_enable_msi:              ; @mobiveil_pcie_enable_msi
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x20, [x0, #24]
Lloh0:
	adrp	x8, _PCI_NUM_MSI@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_NUM_MSI@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [x0, #16]
	str	x20, [x0, #8]
	mov	x0, x20
	bl	_lower_32_bits
	ldr	x8, [x19]
Lloh3:
	adrp	x9, _MSI_BASE_LO_OFFSET@GOTPAGE
Lloh4:
	ldr	x9, [x9, _MSI_BASE_LO_OFFSET@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	mov	x0, x20
	bl	_upper_32_bits
	ldr	x8, [x19]
Lloh6:
	adrp	x9, _MSI_BASE_HI_OFFSET@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MSI_BASE_HI_OFFSET@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	add	x1, x9, x8
	bl	_writel_relaxed
	ldr	x8, [x19]
Lloh9:
	adrp	x9, _MSI_SIZE_OFFSET@GOTPAGE
Lloh10:
	ldr	x9, [x9, _MSI_SIZE_OFFSET@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #4096
	bl	_writel_relaxed
	ldr	x8, [x19]
Lloh12:
	adrp	x9, _MSI_ENABLE_OFFSET@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MSI_ENABLE_OFFSET@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	w0, #1
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_writel_relaxed
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_NUM_MSI,4,2                ; @PCI_NUM_MSI
	.comm	_MSI_BASE_LO_OFFSET,8,3         ; @MSI_BASE_LO_OFFSET
	.comm	_MSI_BASE_HI_OFFSET,8,3         ; @MSI_BASE_HI_OFFSET
	.comm	_MSI_SIZE_OFFSET,8,3            ; @MSI_SIZE_OFFSET
	.comm	_MSI_ENABLE_OFFSET,8,3          ; @MSI_ENABLE_OFFSET
	.no_dead_strip	_mobiveil_pcie_enable_msi
.subsections_via_symbols
