	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function meson8b_init_prg_eth
_meson8b_init_prg_eth:                  ## @meson8b_init_prg_eth
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	(%rdi), %edi
	leal	-128(%rdi), %eax
	cmpl	$4, %eax
	ja	LBB0_9
## %bb.1:
	xorl	%ebx, %ebx
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_2:
	movl	4(%r14), %ebx
	sarl	%ebx
LBB0_3:
	movq	_PRG_ETH0@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_PRG_ETH0_INVERTED_RMII_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	callq	_meson8b_dwmac_mask_bits
	movl	(%r15), %esi
	movq	_PRG_ETH0_TXDLY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PRG_ETH0_TXDLY_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %ebx
	movq	%r14, %rdi
	movl	%ebx, %ecx
	callq	_meson8b_dwmac_mask_bits
	movl	12(%r14), %edi
	movl	$125000000, %esi                ## imm = 0x7735940
	callq	_clk_set_rate
	testl	%eax, %eax
	je	LBB0_5
## %bb.4:
	movl	%eax, %ebx
	movl	8(%r14), %edi
	leaq	L_.str(%rip), %rsi
	jmp	LBB0_7
LBB0_5:
	movl	12(%r14), %edi
	callq	_clk_prepare_enable
	movl	8(%r14), %edi
	testl	%eax, %eax
	je	LBB0_10
## %bb.6:
	movl	%eax, %ebx
	leaq	L_.str.1(%rip), %rsi
LBB0_7:
	xorl	%eax, %eax
	callq	_dev_err
	jmp	LBB0_12
LBB0_9:
	movl	8(%r14), %r14d
                                        ## kill: def $edi killed $edi killed $rdi
	callq	_phy_modes
	leaq	L_.str.2(%rip), %rsi
	xorl	%ebx, %ebx
	movl	%r14d, %edi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	subl	(%rax), %ebx
	jmp	LBB0_12
LBB0_8:
	movq	_PRG_ETH0@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_PRG_ETH0_INVERTED_RMII_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	movl	%ecx, %edx
	callq	_meson8b_dwmac_mask_bits
	movl	(%rbx), %esi
	movq	_PRG_ETH0_TXDLY_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	xorl	%ecx, %ecx
	callq	_meson8b_dwmac_mask_bits
	jmp	LBB0_11
LBB0_10:
	movq	_clk_disable_unprepare@GOTPCREL(%rip), %rax
	movslq	(%rax), %rsi
	movl	12(%r14), %edx
	callq	_devm_add_action_or_reset
LBB0_11:
	movq	_PRG_ETH0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PRG_ETH0_TX_AND_PHY_REF_CLK@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movq	%r14, %rdi
	movl	%ecx, %edx
	callq	_meson8b_dwmac_mask_bits
	xorl	%ebx, %ebx
LBB0_12:
	movl	%ebx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_8, LBB0_8-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
LJTI0_0:
	.long	L0_0_set_8
	.long	L0_0_set_3
	.long	L0_0_set_2
	.long	L0_0_set_3
	.long	L0_0_set_2
	.end_data_region
                                        ## -- End function
	.comm	_PRG_ETH0,4,2                   ## @PRG_ETH0
	.comm	_PRG_ETH0_INVERTED_RMII_CLK,4,2 ## @PRG_ETH0_INVERTED_RMII_CLK
	.comm	_PRG_ETH0_TXDLY_MASK,4,2        ## @PRG_ETH0_TXDLY_MASK
	.comm	_PRG_ETH0_TXDLY_SHIFT,4,2       ## @PRG_ETH0_TXDLY_SHIFT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"failed to set RGMII TX clock\n"

L_.str.1:                               ## @.str.1
	.asciz	"failed to enable the RGMII TX clock\n"

	.comm	_clk_disable_unprepare,4,2      ## @clk_disable_unprepare
L_.str.2:                               ## @.str.2
	.asciz	"unsupported phy-mode %s\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PRG_ETH0_TX_AND_PHY_REF_CLK,4,2 ## @PRG_ETH0_TX_AND_PHY_REF_CLK
	.no_dead_strip	_meson8b_init_prg_eth
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function meson8b_init_prg_eth
_meson8b_init_prg_eth:                  ; @meson8b_init_prg_eth
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0]
	sub	w8, w0, #128
	cmp	w8, #4
	b.hi	LBB0_7
; %bb.1:
	mov	w20, #0
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
Lloh2:
	adrp	x21, _PRG_ETH0@GOTPAGE
Lloh3:
	ldr	x21, [x21, _PRG_ETH0@GOTPAGEOFF]
	br	x10
LBB0_2:
	ldr	w8, [x19, #4]
	asr	w20, w8, #1
LBB0_3:
	ldr	w1, [x21]
Lloh4:
	adrp	x8, _PRG_ETH0_INVERTED_RMII_CLK@GOTPAGE
Lloh5:
	ldr	x8, [x8, _PRG_ETH0_INVERTED_RMII_CLK@GOTPAGEOFF]
Lloh6:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #0
	bl	_meson8b_dwmac_mask_bits
Lloh7:
	adrp	x8, _PRG_ETH0_TXDLY_MASK@GOTPAGE
Lloh8:
	ldr	x8, [x8, _PRG_ETH0_TXDLY_MASK@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh9:
	ldr	w2, [x8]
Lloh10:
	adrp	x8, _PRG_ETH0_TXDLY_SHIFT@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PRG_ETH0_TXDLY_SHIFT@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	lsl	w3, w20, w8
	mov	x0, x19
	bl	_meson8b_dwmac_mask_bits
	ldr	w0, [x19, #12]
	mov	w1, #22848
	movk	w1, #1907, lsl #16
	bl	_clk_set_rate
	cbz	w0, LBB0_5
; %bb.4:
	mov	x20, x0
	ldr	w0, [x19, #8]
Lloh13:
	adrp	x1, l_.str@PAGE
Lloh14:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
	b	LBB0_11
LBB0_5:
	ldr	w0, [x19, #12]
	bl	_clk_prepare_enable
	mov	x20, x0
	ldr	w0, [x19, #8]
	cbz	w20, LBB0_9
; %bb.6:
Lloh15:
	adrp	x1, l_.str.1@PAGE
Lloh16:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_err
	b	LBB0_11
LBB0_7:
	ldr	w19, [x19, #8]
	bl	_phy_modes
                                        ; kill: def $w0 killed $w0 def $x0
	str	x0, [sp]
Lloh17:
	adrp	x1, l_.str.2@PAGE
Lloh18:
	add	x1, x1, l_.str.2@PAGEOFF
	mov	x0, x19
	bl	_dev_err
Lloh19:
	adrp	x8, _EINVAL@GOTPAGE
Lloh20:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_11
LBB0_8:
	ldr	w1, [x21]
Lloh22:
	adrp	x8, _PRG_ETH0_INVERTED_RMII_CLK@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PRG_ETH0_INVERTED_RMII_CLK@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_meson8b_dwmac_mask_bits
	ldr	w1, [x21]
Lloh25:
	adrp	x8, _PRG_ETH0_TXDLY_MASK@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PRG_ETH0_TXDLY_MASK@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #0
	bl	_meson8b_dwmac_mask_bits
	b	LBB0_10
LBB0_9:
Lloh28:
	adrp	x8, _clk_disable_unprepare@GOTPAGE
Lloh29:
	ldr	x8, [x8, _clk_disable_unprepare@GOTPAGEOFF]
Lloh30:
	ldrsw	x1, [x8]
	ldr	w2, [x19, #12]
	bl	_devm_add_action_or_reset
LBB0_10:
	ldr	w1, [x21]
Lloh31:
	adrp	x8, _PRG_ETH0_TX_AND_PHY_REF_CLK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PRG_ETH0_TX_AND_PHY_REF_CLK@GOTPAGEOFF]
Lloh33:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x2
	bl	_meson8b_dwmac_mask_bits
	mov	w20, #0
LBB0_11:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpAdd	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_8-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_3-LBB0_2)>>2
	.byte	(LBB0_2-LBB0_2)>>2
                                        ; -- End function
	.comm	_PRG_ETH0,4,2                   ; @PRG_ETH0
	.comm	_PRG_ETH0_INVERTED_RMII_CLK,4,2 ; @PRG_ETH0_INVERTED_RMII_CLK
	.comm	_PRG_ETH0_TXDLY_MASK,4,2        ; @PRG_ETH0_TXDLY_MASK
	.comm	_PRG_ETH0_TXDLY_SHIFT,4,2       ; @PRG_ETH0_TXDLY_SHIFT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"failed to set RGMII TX clock\n"

l_.str.1:                               ; @.str.1
	.asciz	"failed to enable the RGMII TX clock\n"

	.comm	_clk_disable_unprepare,4,2      ; @clk_disable_unprepare
l_.str.2:                               ; @.str.2
	.asciz	"unsupported phy-mode %s\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PRG_ETH0_TX_AND_PHY_REF_CLK,4,2 ; @PRG_ETH0_TX_AND_PHY_REF_CLK
	.no_dead_strip	_meson8b_init_prg_eth
.subsections_via_symbols
