	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ocelot_port_adjust_link
_ocelot_port_adjust_link:               ## @ocelot_port_adjust_link
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	callq	_netdev_priv
	movq	(%rbx), %rdi
	movl	(%rdi), %edx
	leal	-128(%rdx), %ecx
	cmpl	$3, %ecx
	ja	LBB0_4
## %bb.1:
	movq	%rax, %r13
	xorl	%r15d, %r15d
	movq	_OCELOT_SPEED_10@GOTPCREL(%rip), %rax
	leaq	LJTI0_0(%rip), %rdx
	movslq	(%rdx,%rcx,4), %rcx
	addq	%rdx, %rcx
	jmpq	*%rcx
LBB0_3:
	movq	_DEV_MAC_MODE_CFG_GIGA_MODE_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_OCELOT_SPEED_2500@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_4:
	leaq	L_.str(%rip), %rsi
	movq	%rbx, %rdi
                                        ## kill: def $edx killed $edx killed $rdx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_netdev_err                     ## TAILCALL
LBB0_2:
	movq	_DEV_MAC_MODE_CFG_GIGA_MODE_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_OCELOT_SPEED_1000@GOTPCREL(%rip), %rax
	jmp	LBB0_6
LBB0_5:
	movq	_OCELOT_SPEED_100@GOTPCREL(%rip), %rax
LBB0_6:
	movq	8(%r13), %r12
	movl	(%r13), %ecx
	movl	%ecx, -44(%rbp)                 ## 4-byte Spill
	movl	(%rax), %r14d
	callq	_phy_print_status
	movq	(%rbx), %rax
	cmpl	$0, 4(%rax)
	je	LBB0_7
## %bb.8:
	movq	_DEV_MAC_MODE_CFG_FDX_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movq	_DEV_MAC_MODE_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	movl	%r15d, %esi
	callq	_ocelot_port_writel
	movl	$5, %edi
	callq	_DEV_MAC_IFG_CFG_TX_IFG
	movq	_DEV_MAC_IFG_CFG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_ocelot_port_writel
	movl	$67, %edi
	callq	_DEV_MAC_HDX_CFG_LATE_COL_POS
	movq	_DEV_MAC_HDX_CFG_SEED_LOAD@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DEV_MAC_HDX_CFG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_ocelot_port_writel
	movl	$1, %edi
	callq	_mdelay
	movl	$67, %edi
	callq	_DEV_MAC_HDX_CFG_LATE_COL_POS
	movl	(%rbx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_ocelot_port_writel
	movq	_DEV_PORT_MISC_HDX_FAST_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DEV_PORT_MISC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_ocelot_port_writel
	movq	_PCS1G_MODE_CFG_SGMII_MODE_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCS1G_MODE_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_ocelot_port_writel
	movq	_PCS1G_SD_CFG_SD_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCS1G_SD_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_ocelot_port_writel
	movq	_PCS1G_CFG_PCS_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCS1G_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_ocelot_port_writel
	movq	_PCS1G_ANEG_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_ocelot_port_writel
	movq	_PCS1G_LB_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_ocelot_port_writel
	movq	_VLAN_ETH_FRAME_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_DEV_MAC_MAXLEN_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_ocelot_port_writel
	movq	_ETH_P_8021AD@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DEV_MAC_TAGS_CFG_TAG_ID
	movq	_DEV_MAC_TAGS_CFG_VLAN_AWR_ENA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_DEV_MAC_TAGS_CFG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_ocelot_port_writel
	movq	_DEV_MAC_ENA_CFG_RX_ENA@GOTPCREL(%rip), %rax
	movq	_DEV_MAC_ENA_CFG_TX_ENA@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	orl	(%rax), %esi
	movq	_DEV_MAC_ENA_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	callq	_ocelot_port_writel
	movl	%r14d, %edi
	callq	_DEV_CLOCK_CFG_LINK_SPEED
	movq	_DEV_CLOCK_CFG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_ocelot_port_writel
	movq	_DEV_MAC_FC_MAC_HIGH_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_ocelot_port_writel
	movq	_DEV_MAC_FC_MAC_LOW_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r13, %rdi
	xorl	%esi, %esi
	callq	_ocelot_port_writel
	movl	%r14d, %edi
	callq	_ANA_PFC_PFC_CFG_FC_LINK_SPEED
	movq	_ANA_PFC_PFC_CFG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	-44(%rbp), %r13d                ## 4-byte Reload
	movl	%r13d, %ecx
	callq	_ocelot_write_gix
	movq	_SYS_PAUSE_CFG_PAUSE_ENA@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$101, %edi
	callq	_SYS_PAUSE_CFG_PAUSE_STOP
	movl	%eax, %ebx
	movl	$152, %edi
	callq	_SYS_PAUSE_CFG_PAUSE_START
	orl	%eax, %ebx
	orl	%r15d, %ebx
	movq	_SYS_PAUSE_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%r13d, %ecx
	callq	_ocelot_write_rix
	movq	_QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$1, %edi
	callq	_QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG
	orl	%eax, %ebx
	movq	_QSYS_SWITCH_PORT_MODE_PORT_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_QSYS_SWITCH_PORT_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%r13d, %ecx
	callq	_ocelot_write_rix
	movl	$65535, %edi                    ## imm = 0xFFFF
	callq	_SYS_MAC_FC_CFG_PAUSE_VAL_CFG
	movl	%eax, %ebx
	movq	_SYS_MAC_FC_CFG_RX_FC_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SYS_MAC_FC_CFG_TX_FC_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_SYS_MAC_FC_CFG_ZERO_PAUSE_ENA@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	$7, %edi
	callq	_SYS_MAC_FC_CFG_FC_LATENCY_CFG
	movl	%eax, %r15d
	movl	%r14d, %edi
	callq	_SYS_MAC_FC_CFG_FC_LINK_SPEED
	orl	%eax, %r15d
	orl	%ebx, %r15d
	movq	_SYS_MAC_FC_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r15d, %esi
	movl	%r13d, %ecx
	callq	_ocelot_write_rix
	movq	_ANA_POL_FLOWC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	%r13d, %ecx
	callq	_ocelot_write_rix
	movl	(%r12), %eax
	movq	_VLAN_ETH_FRAME_LEN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	leal	(%rcx,%rcx,8), %edi
	subl	%edi, %eax
	movq	_OCELOT_BUFFER_CELL_SZ@GOTPCREL(%rip), %rcx
	cltd
	idivl	(%rcx)
	movl	%eax, %ebx
	callq	_ocelot_wm_enc
	movq	_SYS_ATOP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	movl	%r13d, %ecx
	callq	_ocelot_write_rix
	movl	%ebx, %edi
	callq	_ocelot_wm_enc
	movq	_SYS_ATOP_TOT_CFG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ocelot_write                   ## TAILCALL
LBB0_7:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_3, LBB0_3-LJTI0_0
.set L0_0_set_2, LBB0_2-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_6, LBB0_6-LJTI0_0
LJTI0_0:
	.long	L0_0_set_3
	.long	L0_0_set_2
	.long	L0_0_set_5
	.long	L0_0_set_6
	.end_data_region
                                        ## -- End function
	.comm	_OCELOT_SPEED_10,4,2            ## @OCELOT_SPEED_10
	.comm	_OCELOT_SPEED_100,4,2           ## @OCELOT_SPEED_100
	.comm	_OCELOT_SPEED_1000,4,2          ## @OCELOT_SPEED_1000
	.comm	_DEV_MAC_MODE_CFG_GIGA_MODE_ENA,4,2 ## @DEV_MAC_MODE_CFG_GIGA_MODE_ENA
	.comm	_OCELOT_SPEED_2500,4,2          ## @OCELOT_SPEED_2500
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unsupported PHY speed: %d\n"

	.comm	_DEV_MAC_MODE_CFG_FDX_ENA,4,2   ## @DEV_MAC_MODE_CFG_FDX_ENA
	.comm	_DEV_MAC_MODE_CFG,4,2           ## @DEV_MAC_MODE_CFG
	.comm	_DEV_MAC_IFG_CFG,4,2            ## @DEV_MAC_IFG_CFG
	.comm	_DEV_MAC_HDX_CFG_SEED_LOAD,4,2  ## @DEV_MAC_HDX_CFG_SEED_LOAD
	.comm	_DEV_MAC_HDX_CFG,4,2            ## @DEV_MAC_HDX_CFG
	.comm	_DEV_PORT_MISC_HDX_FAST_DIS,4,2 ## @DEV_PORT_MISC_HDX_FAST_DIS
	.comm	_DEV_PORT_MISC,4,2              ## @DEV_PORT_MISC
	.comm	_PCS1G_MODE_CFG_SGMII_MODE_ENA,4,2 ## @PCS1G_MODE_CFG_SGMII_MODE_ENA
	.comm	_PCS1G_MODE_CFG,4,2             ## @PCS1G_MODE_CFG
	.comm	_PCS1G_SD_CFG_SD_SEL,4,2        ## @PCS1G_SD_CFG_SD_SEL
	.comm	_PCS1G_SD_CFG,4,2               ## @PCS1G_SD_CFG
	.comm	_PCS1G_CFG_PCS_ENA,4,2          ## @PCS1G_CFG_PCS_ENA
	.comm	_PCS1G_CFG,4,2                  ## @PCS1G_CFG
	.comm	_PCS1G_ANEG_CFG,4,2             ## @PCS1G_ANEG_CFG
	.comm	_PCS1G_LB_CFG,4,2               ## @PCS1G_LB_CFG
	.comm	_VLAN_ETH_FRAME_LEN,4,2         ## @VLAN_ETH_FRAME_LEN
	.comm	_DEV_MAC_MAXLEN_CFG,4,2         ## @DEV_MAC_MAXLEN_CFG
	.comm	_ETH_P_8021AD,4,2               ## @ETH_P_8021AD
	.comm	_DEV_MAC_TAGS_CFG_VLAN_AWR_ENA,4,2 ## @DEV_MAC_TAGS_CFG_VLAN_AWR_ENA
	.comm	_DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,4,2 ## @DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA
	.comm	_DEV_MAC_TAGS_CFG,4,2           ## @DEV_MAC_TAGS_CFG
	.comm	_DEV_MAC_ENA_CFG_RX_ENA,4,2     ## @DEV_MAC_ENA_CFG_RX_ENA
	.comm	_DEV_MAC_ENA_CFG_TX_ENA,4,2     ## @DEV_MAC_ENA_CFG_TX_ENA
	.comm	_DEV_MAC_ENA_CFG,4,2            ## @DEV_MAC_ENA_CFG
	.comm	_DEV_CLOCK_CFG,4,2              ## @DEV_CLOCK_CFG
	.comm	_DEV_MAC_FC_MAC_HIGH_CFG,4,2    ## @DEV_MAC_FC_MAC_HIGH_CFG
	.comm	_DEV_MAC_FC_MAC_LOW_CFG,4,2     ## @DEV_MAC_FC_MAC_LOW_CFG
	.comm	_ANA_PFC_PFC_CFG,4,2            ## @ANA_PFC_PFC_CFG
	.comm	_SYS_PAUSE_CFG_PAUSE_ENA,4,2    ## @SYS_PAUSE_CFG_PAUSE_ENA
	.comm	_SYS_PAUSE_CFG,4,2              ## @SYS_PAUSE_CFG
	.comm	_QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,4,2 ## @QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
	.comm	_QSYS_SWITCH_PORT_MODE_PORT_ENA,4,2 ## @QSYS_SWITCH_PORT_MODE_PORT_ENA
	.comm	_QSYS_SWITCH_PORT_MODE,4,2      ## @QSYS_SWITCH_PORT_MODE
	.comm	_SYS_MAC_FC_CFG_RX_FC_ENA,4,2   ## @SYS_MAC_FC_CFG_RX_FC_ENA
	.comm	_SYS_MAC_FC_CFG_TX_FC_ENA,4,2   ## @SYS_MAC_FC_CFG_TX_FC_ENA
	.comm	_SYS_MAC_FC_CFG_ZERO_PAUSE_ENA,4,2 ## @SYS_MAC_FC_CFG_ZERO_PAUSE_ENA
	.comm	_SYS_MAC_FC_CFG,4,2             ## @SYS_MAC_FC_CFG
	.comm	_ANA_POL_FLOWC,4,2              ## @ANA_POL_FLOWC
	.comm	_OCELOT_BUFFER_CELL_SZ,4,2      ## @OCELOT_BUFFER_CELL_SZ
	.comm	_SYS_ATOP,4,2                   ## @SYS_ATOP
	.comm	_SYS_ATOP_TOT_CFG,4,2           ## @SYS_ATOP_TOT_CFG
	.no_dead_strip	_ocelot_port_adjust_link
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ocelot_port_adjust_link
_ocelot_port_adjust_link:               ; @ocelot_port_adjust_link
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x23, x0
	bl	_netdev_priv
	mov	x22, x0
	ldr	x0, [x23]
	ldr	w2, [x0]
	sub	w9, w2, #128
	cmp	w9, #3
	b.hi	LBB0_3
; %bb.1:
	mov	w24, #0
Lloh0:
	adrp	x8, _OCELOT_SPEED_10@GOTPAGE
Lloh1:
	ldr	x8, [x8, _OCELOT_SPEED_10@GOTPAGEOFF]
Lloh2:
	adrp	x10, lJTI0_0@PAGE
Lloh3:
	add	x10, x10, lJTI0_0@PAGEOFF
	adr	x11, LBB0_2
	ldrb	w12, [x10, x9]
	add	x11, x11, x12, lsl #2
	br	x11
LBB0_2:
Lloh4:
	adrp	x8, _DEV_MAC_MODE_CFG_GIGA_MODE_ENA@GOTPAGE
Lloh5:
	ldr	x8, [x8, _DEV_MAC_MODE_CFG_GIGA_MODE_ENA@GOTPAGEOFF]
Lloh6:
	ldr	w24, [x8]
Lloh7:
	adrp	x8, _OCELOT_SPEED_2500@GOTPAGE
Lloh8:
	ldr	x8, [x8, _OCELOT_SPEED_2500@GOTPAGEOFF]
	b	LBB0_6
LBB0_3:
Lloh9:
	adrp	x1, l_.str@PAGE
Lloh10:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x23
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_netdev_err
LBB0_4:
Lloh11:
	adrp	x8, _DEV_MAC_MODE_CFG_GIGA_MODE_ENA@GOTPAGE
Lloh12:
	ldr	x8, [x8, _DEV_MAC_MODE_CFG_GIGA_MODE_ENA@GOTPAGEOFF]
Lloh13:
	ldr	w24, [x8]
Lloh14:
	adrp	x8, _OCELOT_SPEED_1000@GOTPAGE
Lloh15:
	ldr	x8, [x8, _OCELOT_SPEED_1000@GOTPAGEOFF]
	b	LBB0_6
LBB0_5:
	mov	w24, #0
Lloh16:
	adrp	x8, _OCELOT_SPEED_100@GOTPAGE
Lloh17:
	ldr	x8, [x8, _OCELOT_SPEED_100@GOTPAGEOFF]
LBB0_6:
	ldr	x19, [x22, #8]
	ldr	w20, [x22]
	ldr	w21, [x8]
	bl	_phy_print_status
	ldr	x8, [x23]
	ldr	w8, [x8, #4]
	cbz	w8, LBB0_8
; %bb.7:
Lloh18:
	adrp	x8, _DEV_MAC_MODE_CFG_FDX_ENA@GOTPAGE
Lloh19:
	ldr	x8, [x8, _DEV_MAC_MODE_CFG_FDX_ENA@GOTPAGEOFF]
Lloh20:
	ldr	w8, [x8]
	orr	w1, w8, w24
Lloh21:
	adrp	x8, _DEV_MAC_MODE_CFG@GOTPAGE
Lloh22:
	ldr	x8, [x8, _DEV_MAC_MODE_CFG@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
	mov	w0, #5
	bl	_DEV_MAC_IFG_CFG_TX_IFG
	mov	x1, x0
Lloh24:
	adrp	x8, _DEV_MAC_IFG_CFG@GOTPAGE
Lloh25:
	ldr	x8, [x8, _DEV_MAC_IFG_CFG@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
	mov	w0, #67
	bl	_DEV_MAC_HDX_CFG_LATE_COL_POS
Lloh27:
	adrp	x8, _DEV_MAC_HDX_CFG_SEED_LOAD@GOTPAGE
Lloh28:
	ldr	x8, [x8, _DEV_MAC_HDX_CFG_SEED_LOAD@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	orr	w1, w8, w0
Lloh30:
	adrp	x23, _DEV_MAC_HDX_CFG@GOTPAGE
Lloh31:
	ldr	x23, [x23, _DEV_MAC_HDX_CFG@GOTPAGEOFF]
	ldr	w2, [x23]
	mov	x0, x22
	bl	_ocelot_port_writel
	mov	w0, #1
	bl	_mdelay
	mov	w0, #67
	bl	_DEV_MAC_HDX_CFG_LATE_COL_POS
	mov	x1, x0
	ldr	w2, [x23]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh32:
	adrp	x8, _DEV_PORT_MISC_HDX_FAST_DIS@GOTPAGE
Lloh33:
	ldr	x8, [x8, _DEV_PORT_MISC_HDX_FAST_DIS@GOTPAGEOFF]
Lloh34:
	ldr	w1, [x8]
Lloh35:
	adrp	x8, _DEV_PORT_MISC@GOTPAGE
Lloh36:
	ldr	x8, [x8, _DEV_PORT_MISC@GOTPAGEOFF]
Lloh37:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh38:
	adrp	x8, _PCS1G_MODE_CFG_SGMII_MODE_ENA@GOTPAGE
Lloh39:
	ldr	x8, [x8, _PCS1G_MODE_CFG_SGMII_MODE_ENA@GOTPAGEOFF]
Lloh40:
	ldr	w1, [x8]
Lloh41:
	adrp	x8, _PCS1G_MODE_CFG@GOTPAGE
Lloh42:
	ldr	x8, [x8, _PCS1G_MODE_CFG@GOTPAGEOFF]
Lloh43:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh44:
	adrp	x8, _PCS1G_SD_CFG_SD_SEL@GOTPAGE
Lloh45:
	ldr	x8, [x8, _PCS1G_SD_CFG_SD_SEL@GOTPAGEOFF]
Lloh46:
	ldr	w1, [x8]
Lloh47:
	adrp	x8, _PCS1G_SD_CFG@GOTPAGE
Lloh48:
	ldr	x8, [x8, _PCS1G_SD_CFG@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh50:
	adrp	x8, _PCS1G_CFG_PCS_ENA@GOTPAGE
Lloh51:
	ldr	x8, [x8, _PCS1G_CFG_PCS_ENA@GOTPAGEOFF]
Lloh52:
	ldr	w1, [x8]
Lloh53:
	adrp	x8, _PCS1G_CFG@GOTPAGE
Lloh54:
	ldr	x8, [x8, _PCS1G_CFG@GOTPAGEOFF]
Lloh55:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh56:
	adrp	x8, _PCS1G_ANEG_CFG@GOTPAGE
Lloh57:
	ldr	x8, [x8, _PCS1G_ANEG_CFG@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	mov	x0, x22
	mov	w1, #0
	bl	_ocelot_port_writel
Lloh59:
	adrp	x8, _PCS1G_LB_CFG@GOTPAGE
Lloh60:
	ldr	x8, [x8, _PCS1G_LB_CFG@GOTPAGEOFF]
Lloh61:
	ldr	w2, [x8]
	mov	x0, x22
	mov	w1, #0
	bl	_ocelot_port_writel
Lloh62:
	adrp	x23, _VLAN_ETH_FRAME_LEN@GOTPAGE
Lloh63:
	ldr	x23, [x23, _VLAN_ETH_FRAME_LEN@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh64:
	adrp	x8, _DEV_MAC_MAXLEN_CFG@GOTPAGE
Lloh65:
	ldr	x8, [x8, _DEV_MAC_MAXLEN_CFG@GOTPAGEOFF]
Lloh66:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh67:
	adrp	x8, _ETH_P_8021AD@GOTPAGE
Lloh68:
	ldr	x8, [x8, _ETH_P_8021AD@GOTPAGEOFF]
Lloh69:
	ldr	w0, [x8]
	bl	_DEV_MAC_TAGS_CFG_TAG_ID
Lloh70:
	adrp	x8, _DEV_MAC_TAGS_CFG_VLAN_AWR_ENA@GOTPAGE
Lloh71:
	ldr	x8, [x8, _DEV_MAC_TAGS_CFG_VLAN_AWR_ENA@GOTPAGEOFF]
Lloh72:
	ldr	w8, [x8]
Lloh73:
	adrp	x9, _DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA@GOTPAGE
Lloh74:
	ldr	x9, [x9, _DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA@GOTPAGEOFF]
	orr	w8, w8, w0
Lloh75:
	ldr	w9, [x9]
	orr	w1, w8, w9
Lloh76:
	adrp	x8, _DEV_MAC_TAGS_CFG@GOTPAGE
Lloh77:
	ldr	x8, [x8, _DEV_MAC_TAGS_CFG@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh79:
	adrp	x8, _DEV_MAC_ENA_CFG_RX_ENA@GOTPAGE
Lloh80:
	ldr	x8, [x8, _DEV_MAC_ENA_CFG_RX_ENA@GOTPAGEOFF]
Lloh81:
	adrp	x9, _DEV_MAC_ENA_CFG_TX_ENA@GOTPAGE
Lloh82:
	ldr	x9, [x9, _DEV_MAC_ENA_CFG_TX_ENA@GOTPAGEOFF]
Lloh83:
	ldr	w8, [x8]
Lloh84:
	ldr	w9, [x9]
	orr	w1, w9, w8
Lloh85:
	adrp	x8, _DEV_MAC_ENA_CFG@GOTPAGE
Lloh86:
	ldr	x8, [x8, _DEV_MAC_ENA_CFG@GOTPAGEOFF]
Lloh87:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
	mov	x0, x21
	bl	_DEV_CLOCK_CFG_LINK_SPEED
	mov	x1, x0
Lloh88:
	adrp	x8, _DEV_CLOCK_CFG@GOTPAGE
Lloh89:
	ldr	x8, [x8, _DEV_CLOCK_CFG@GOTPAGEOFF]
Lloh90:
	ldr	w2, [x8]
	mov	x0, x22
	bl	_ocelot_port_writel
Lloh91:
	adrp	x8, _DEV_MAC_FC_MAC_HIGH_CFG@GOTPAGE
Lloh92:
	ldr	x8, [x8, _DEV_MAC_FC_MAC_HIGH_CFG@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
	mov	x0, x22
	mov	w1, #0
	bl	_ocelot_port_writel
Lloh94:
	adrp	x8, _DEV_MAC_FC_MAC_LOW_CFG@GOTPAGE
Lloh95:
	ldr	x8, [x8, _DEV_MAC_FC_MAC_LOW_CFG@GOTPAGEOFF]
Lloh96:
	ldr	w2, [x8]
	mov	x0, x22
	mov	w1, #0
	bl	_ocelot_port_writel
	mov	x0, x21
	bl	_ANA_PFC_PFC_CFG_FC_LINK_SPEED
	mov	x1, x0
Lloh97:
	adrp	x8, _ANA_PFC_PFC_CFG@GOTPAGE
Lloh98:
	ldr	x8, [x8, _ANA_PFC_PFC_CFG@GOTPAGEOFF]
Lloh99:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x20
	bl	_ocelot_write_gix
Lloh100:
	adrp	x8, _SYS_PAUSE_CFG_PAUSE_ENA@GOTPAGE
Lloh101:
	ldr	x8, [x8, _SYS_PAUSE_CFG_PAUSE_ENA@GOTPAGEOFF]
Lloh102:
	ldr	w22, [x8]
	mov	w0, #101
	bl	_SYS_PAUSE_CFG_PAUSE_STOP
	orr	w22, w0, w22
	mov	w0, #152
	bl	_SYS_PAUSE_CFG_PAUSE_START
	orr	w1, w22, w0
Lloh103:
	adrp	x8, _SYS_PAUSE_CFG@GOTPAGE
Lloh104:
	ldr	x8, [x8, _SYS_PAUSE_CFG@GOTPAGEOFF]
Lloh105:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x20
	bl	_ocelot_write_rix
Lloh106:
	adrp	x8, _QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE@GOTPAGE
Lloh107:
	ldr	x8, [x8, _QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE@GOTPAGEOFF]
Lloh108:
	ldr	w22, [x8]
	mov	w0, #1
	bl	_QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG
Lloh109:
	adrp	x8, _QSYS_SWITCH_PORT_MODE_PORT_ENA@GOTPAGE
Lloh110:
	ldr	x8, [x8, _QSYS_SWITCH_PORT_MODE_PORT_ENA@GOTPAGEOFF]
	orr	w9, w0, w22
Lloh111:
	ldr	w8, [x8]
	orr	w1, w9, w8
Lloh112:
	adrp	x8, _QSYS_SWITCH_PORT_MODE@GOTPAGE
Lloh113:
	ldr	x8, [x8, _QSYS_SWITCH_PORT_MODE@GOTPAGEOFF]
Lloh114:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x20
	bl	_ocelot_write_rix
	mov	w0, #65535
	bl	_SYS_MAC_FC_CFG_PAUSE_VAL_CFG
Lloh115:
	adrp	x8, _SYS_MAC_FC_CFG_RX_FC_ENA@GOTPAGE
Lloh116:
	ldr	x8, [x8, _SYS_MAC_FC_CFG_RX_FC_ENA@GOTPAGEOFF]
Lloh117:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh118:
	adrp	x9, _SYS_MAC_FC_CFG_TX_FC_ENA@GOTPAGE
Lloh119:
	ldr	x9, [x9, _SYS_MAC_FC_CFG_TX_FC_ENA@GOTPAGEOFF]
Lloh120:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh121:
	adrp	x9, _SYS_MAC_FC_CFG_ZERO_PAUSE_ENA@GOTPAGE
Lloh122:
	ldr	x9, [x9, _SYS_MAC_FC_CFG_ZERO_PAUSE_ENA@GOTPAGEOFF]
Lloh123:
	ldr	w9, [x9]
	orr	w22, w8, w9
	mov	w0, #7
	bl	_SYS_MAC_FC_CFG_FC_LATENCY_CFG
	orr	w22, w22, w0
	mov	x0, x21
	bl	_SYS_MAC_FC_CFG_FC_LINK_SPEED
	orr	w1, w22, w0
Lloh124:
	adrp	x8, _SYS_MAC_FC_CFG@GOTPAGE
Lloh125:
	ldr	x8, [x8, _SYS_MAC_FC_CFG@GOTPAGEOFF]
Lloh126:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x20
	bl	_ocelot_write_rix
Lloh127:
	adrp	x8, _ANA_POL_FLOWC@GOTPAGE
Lloh128:
	ldr	x8, [x8, _ANA_POL_FLOWC@GOTPAGEOFF]
Lloh129:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	mov	x3, x20
	bl	_ocelot_write_rix
	ldr	w8, [x19]
	ldr	w9, [x23]
	add	w0, w9, w9, lsl #3
	sub	w8, w8, w0
Lloh130:
	adrp	x9, _OCELOT_BUFFER_CELL_SZ@GOTPAGE
Lloh131:
	ldr	x9, [x9, _OCELOT_BUFFER_CELL_SZ@GOTPAGEOFF]
Lloh132:
	ldr	w9, [x9]
	sdiv	w21, w8, w9
	bl	_ocelot_wm_enc
	mov	x1, x0
Lloh133:
	adrp	x8, _SYS_ATOP@GOTPAGE
Lloh134:
	ldr	x8, [x8, _SYS_ATOP@GOTPAGEOFF]
Lloh135:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x3, x20
	bl	_ocelot_write_rix
	mov	x0, x21
	bl	_ocelot_wm_enc
	mov	x1, x0
Lloh136:
	adrp	x8, _SYS_ATOP_TOT_CFG@GOTPAGE
Lloh137:
	ldr	x8, [x8, _SYS_ATOP_TOT_CFG@GOTPAGEOFF]
Lloh138:
	ldr	w2, [x8]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_ocelot_write
LBB0_8:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh136, Lloh137, Lloh138
	.loh AdrpLdrGotLdr	Lloh133, Lloh134, Lloh135
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGotLdr	Lloh118, Lloh119, Lloh120
	.loh AdrpLdrGotLdr	Lloh115, Lloh116, Lloh117
	.loh AdrpLdrGotLdr	Lloh112, Lloh113, Lloh114
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh83
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_5-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
                                        ; -- End function
	.comm	_OCELOT_SPEED_10,4,2            ; @OCELOT_SPEED_10
	.comm	_OCELOT_SPEED_100,4,2           ; @OCELOT_SPEED_100
	.comm	_OCELOT_SPEED_1000,4,2          ; @OCELOT_SPEED_1000
	.comm	_DEV_MAC_MODE_CFG_GIGA_MODE_ENA,4,2 ; @DEV_MAC_MODE_CFG_GIGA_MODE_ENA
	.comm	_OCELOT_SPEED_2500,4,2          ; @OCELOT_SPEED_2500
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unsupported PHY speed: %d\n"

	.comm	_DEV_MAC_MODE_CFG_FDX_ENA,4,2   ; @DEV_MAC_MODE_CFG_FDX_ENA
	.comm	_DEV_MAC_MODE_CFG,4,2           ; @DEV_MAC_MODE_CFG
	.comm	_DEV_MAC_IFG_CFG,4,2            ; @DEV_MAC_IFG_CFG
	.comm	_DEV_MAC_HDX_CFG_SEED_LOAD,4,2  ; @DEV_MAC_HDX_CFG_SEED_LOAD
	.comm	_DEV_MAC_HDX_CFG,4,2            ; @DEV_MAC_HDX_CFG
	.comm	_DEV_PORT_MISC_HDX_FAST_DIS,4,2 ; @DEV_PORT_MISC_HDX_FAST_DIS
	.comm	_DEV_PORT_MISC,4,2              ; @DEV_PORT_MISC
	.comm	_PCS1G_MODE_CFG_SGMII_MODE_ENA,4,2 ; @PCS1G_MODE_CFG_SGMII_MODE_ENA
	.comm	_PCS1G_MODE_CFG,4,2             ; @PCS1G_MODE_CFG
	.comm	_PCS1G_SD_CFG_SD_SEL,4,2        ; @PCS1G_SD_CFG_SD_SEL
	.comm	_PCS1G_SD_CFG,4,2               ; @PCS1G_SD_CFG
	.comm	_PCS1G_CFG_PCS_ENA,4,2          ; @PCS1G_CFG_PCS_ENA
	.comm	_PCS1G_CFG,4,2                  ; @PCS1G_CFG
	.comm	_PCS1G_ANEG_CFG,4,2             ; @PCS1G_ANEG_CFG
	.comm	_PCS1G_LB_CFG,4,2               ; @PCS1G_LB_CFG
	.comm	_VLAN_ETH_FRAME_LEN,4,2         ; @VLAN_ETH_FRAME_LEN
	.comm	_DEV_MAC_MAXLEN_CFG,4,2         ; @DEV_MAC_MAXLEN_CFG
	.comm	_ETH_P_8021AD,4,2               ; @ETH_P_8021AD
	.comm	_DEV_MAC_TAGS_CFG_VLAN_AWR_ENA,4,2 ; @DEV_MAC_TAGS_CFG_VLAN_AWR_ENA
	.comm	_DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,4,2 ; @DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA
	.comm	_DEV_MAC_TAGS_CFG,4,2           ; @DEV_MAC_TAGS_CFG
	.comm	_DEV_MAC_ENA_CFG_RX_ENA,4,2     ; @DEV_MAC_ENA_CFG_RX_ENA
	.comm	_DEV_MAC_ENA_CFG_TX_ENA,4,2     ; @DEV_MAC_ENA_CFG_TX_ENA
	.comm	_DEV_MAC_ENA_CFG,4,2            ; @DEV_MAC_ENA_CFG
	.comm	_DEV_CLOCK_CFG,4,2              ; @DEV_CLOCK_CFG
	.comm	_DEV_MAC_FC_MAC_HIGH_CFG,4,2    ; @DEV_MAC_FC_MAC_HIGH_CFG
	.comm	_DEV_MAC_FC_MAC_LOW_CFG,4,2     ; @DEV_MAC_FC_MAC_LOW_CFG
	.comm	_ANA_PFC_PFC_CFG,4,2            ; @ANA_PFC_PFC_CFG
	.comm	_SYS_PAUSE_CFG_PAUSE_ENA,4,2    ; @SYS_PAUSE_CFG_PAUSE_ENA
	.comm	_SYS_PAUSE_CFG,4,2              ; @SYS_PAUSE_CFG
	.comm	_QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,4,2 ; @QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
	.comm	_QSYS_SWITCH_PORT_MODE_PORT_ENA,4,2 ; @QSYS_SWITCH_PORT_MODE_PORT_ENA
	.comm	_QSYS_SWITCH_PORT_MODE,4,2      ; @QSYS_SWITCH_PORT_MODE
	.comm	_SYS_MAC_FC_CFG_RX_FC_ENA,4,2   ; @SYS_MAC_FC_CFG_RX_FC_ENA
	.comm	_SYS_MAC_FC_CFG_TX_FC_ENA,4,2   ; @SYS_MAC_FC_CFG_TX_FC_ENA
	.comm	_SYS_MAC_FC_CFG_ZERO_PAUSE_ENA,4,2 ; @SYS_MAC_FC_CFG_ZERO_PAUSE_ENA
	.comm	_SYS_MAC_FC_CFG,4,2             ; @SYS_MAC_FC_CFG
	.comm	_ANA_POL_FLOWC,4,2              ; @ANA_POL_FLOWC
	.comm	_OCELOT_BUFFER_CELL_SZ,4,2      ; @OCELOT_BUFFER_CELL_SZ
	.comm	_SYS_ATOP,4,2                   ; @SYS_ATOP
	.comm	_SYS_ATOP_TOT_CFG,4,2           ; @SYS_ATOP_TOT_CFG
	.no_dead_strip	_ocelot_port_adjust_link
.subsections_via_symbols
