	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iwl_pcie_apm_init
_iwl_pcie_apm_init:                     ## @iwl_pcie_apm_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	leaq	L_.str(%rip), %rsi
	callq	_IWL_DEBUG_INFO
	movq	16(%rbx), %rax
	movq	(%rax), %rax
	movq	_IWL_DEVICE_FAMILY_8000@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_2
## %bb.1:
	movq	_CSR_GIO_CHICKEN_BITS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bit
LBB0_2:
	movq	_CSR_GIO_CHICKEN_BITS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bit
	movq	_CSR_DBG_HPET_MEM_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_DBG_HPET_MEM_REG_VAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bit
	movq	_CSR_HW_IF_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bit
	movq	%rbx, %rdi
	callq	_iwl_pcie_apm_config
	movq	16(%rbx), %rsi
	movq	8(%rsi), %rax
	cmpq	$0, (%rax)
	je	LBB0_4
## %bb.3:
	movq	_CSR_ANA_PLL_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR50_ANA_PLL_CFG_VAL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bit
	movq	16(%rbx), %rsi
LBB0_4:
	movq	%rbx, %rdi
	callq	_iwl_finish_nic_init
	movl	%eax, %r14d
	testl	%eax, %eax
	jne	LBB0_10
## %bb.5:
	movq	8(%rbx), %rax
	cmpq	$0, 8(%rax)
	je	LBB0_7
## %bb.6:
	movq	_OSC_CLK@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_read_prph
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_read_prph
	movl	(%r15), %esi
	movq	_OSC_CLK_FORCE_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bits_prph
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_read_prph
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_read_prph
	movq	8(%rbx), %rax
LBB0_7:
	cmpl	$0, (%rax)
	jne	LBB0_9
## %bb.8:
	movq	_APMG_CLK_EN_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_CLK_VAL_DMA_CLK_RQT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_write_prph
	movl	$20, %edi
	callq	_udelay
	movq	_APMG_PCIDEV_STT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bits_prph
	movq	_APMG_RTC_INT_STT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_RTC_INT_STT_RFKILL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_write_prph
LBB0_9:
	movq	_STATUS_DEVICE_ENABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%rbx, %rsi
	callq	_set_bit
LBB0_10:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Init card's basic functions\n"

	.comm	_IWL_DEVICE_FAMILY_8000,8,3     ## @IWL_DEVICE_FAMILY_8000
	.comm	_CSR_GIO_CHICKEN_BITS,4,2       ## @CSR_GIO_CHICKEN_BITS
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER,4,2 ## @CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX,4,2 ## @CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
	.comm	_CSR_DBG_HPET_MEM_REG,4,2       ## @CSR_DBG_HPET_MEM_REG
	.comm	_CSR_DBG_HPET_MEM_REG_VAL,4,2   ## @CSR_DBG_HPET_MEM_REG_VAL
	.comm	_CSR_HW_IF_CONFIG_REG,4,2       ## @CSR_HW_IF_CONFIG_REG
	.comm	_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A,4,2 ## @CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
	.comm	_CSR_ANA_PLL_CFG,4,2            ## @CSR_ANA_PLL_CFG
	.comm	_CSR50_ANA_PLL_CFG_VAL,4,2      ## @CSR50_ANA_PLL_CFG_VAL
	.comm	_OSC_CLK,4,2                    ## @OSC_CLK
	.comm	_OSC_CLK_FORCE_CONTROL,4,2      ## @OSC_CLK_FORCE_CONTROL
	.comm	_APMG_CLK_EN_REG,4,2            ## @APMG_CLK_EN_REG
	.comm	_APMG_CLK_VAL_DMA_CLK_RQT,4,2   ## @APMG_CLK_VAL_DMA_CLK_RQT
	.comm	_APMG_PCIDEV_STT_REG,4,2        ## @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS,4,2 ## @APMG_PCIDEV_STT_VAL_L1_ACT_DIS
	.comm	_APMG_RTC_INT_STT_REG,4,2       ## @APMG_RTC_INT_STT_REG
	.comm	_APMG_RTC_INT_STT_RFKILL,4,2    ## @APMG_RTC_INT_STT_RFKILL
	.comm	_STATUS_DEVICE_ENABLED,4,2      ## @STATUS_DEVICE_ENABLED
	.no_dead_strip	_iwl_pcie_apm_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iwl_pcie_apm_init
_iwl_pcie_apm_init:                     ; @iwl_pcie_apm_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	bl	_IWL_DEBUG_INFO
	ldr	x8, [x19, #16]
	ldr	x8, [x8]
Lloh2:
	adrp	x9, _IWL_DEVICE_FAMILY_8000@GOTPAGE
Lloh3:
	ldr	x9, [x9, _IWL_DEVICE_FAMILY_8000@GOTPAGEOFF]
Lloh4:
	ldr	x9, [x9]
Lloh5:
	adrp	x20, _CSR_GIO_CHICKEN_BITS@GOTPAGE
Lloh6:
	ldr	x20, [x20, _CSR_GIO_CHICKEN_BITS@GOTPAGEOFF]
	cmp	x8, x9
	b.ge	LBB0_2
; %bb.1:
	ldr	w1, [x20]
Lloh7:
	adrp	x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER@GOTPAGE
Lloh8:
	ldr	x8, [x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bit
LBB0_2:
	ldr	w1, [x20]
Lloh10:
	adrp	x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bit
Lloh13:
	adrp	x8, _CSR_DBG_HPET_MEM_REG@GOTPAGE
Lloh14:
	ldr	x8, [x8, _CSR_DBG_HPET_MEM_REG@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
Lloh16:
	adrp	x8, _CSR_DBG_HPET_MEM_REG_VAL@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CSR_DBG_HPET_MEM_REG_VAL@GOTPAGEOFF]
Lloh18:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bit
Lloh19:
	adrp	x8, _CSR_HW_IF_CONFIG_REG@GOTPAGE
Lloh20:
	ldr	x8, [x8, _CSR_HW_IF_CONFIG_REG@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
Lloh22:
	adrp	x8, _CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A@GOTPAGEOFF]
Lloh24:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bit
	mov	x0, x19
	bl	_iwl_pcie_apm_config
	ldr	x1, [x19, #16]
	ldr	x8, [x1, #8]
	ldr	x8, [x8]
	cbz	x8, LBB0_4
; %bb.3:
Lloh25:
	adrp	x8, _CSR_ANA_PLL_CFG@GOTPAGE
Lloh26:
	ldr	x8, [x8, _CSR_ANA_PLL_CFG@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
Lloh28:
	adrp	x8, _CSR50_ANA_PLL_CFG_VAL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CSR50_ANA_PLL_CFG_VAL@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bit
	ldr	x1, [x19, #16]
LBB0_4:
	mov	x0, x19
	bl	_iwl_finish_nic_init
	mov	x20, x0
	cbnz	w0, LBB0_10
; %bb.5:
	ldr	x8, [x19, #8]
	ldr	x9, [x8, #8]
	cbz	x9, LBB0_7
; %bb.6:
Lloh31:
	adrp	x21, _OSC_CLK@GOTPAGE
Lloh32:
	ldr	x21, [x21, _OSC_CLK@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_iwl_read_prph
	ldr	w1, [x21]
	mov	x0, x19
	bl	_iwl_read_prph
	ldr	w1, [x21]
Lloh33:
	adrp	x8, _OSC_CLK_FORCE_CONTROL@GOTPAGE
Lloh34:
	ldr	x8, [x8, _OSC_CLK_FORCE_CONTROL@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bits_prph
	ldr	w1, [x21]
	mov	x0, x19
	bl	_iwl_read_prph
	ldr	w1, [x21]
	mov	x0, x19
	bl	_iwl_read_prph
	ldr	x8, [x19, #8]
LBB0_7:
	ldr	w8, [x8]
	cbnz	w8, LBB0_9
; %bb.8:
Lloh36:
	adrp	x8, _APMG_CLK_EN_REG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _APMG_CLK_EN_REG@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x8, _APMG_CLK_VAL_DMA_CLK_RQT@GOTPAGE
Lloh40:
	ldr	x8, [x8, _APMG_CLK_VAL_DMA_CLK_RQT@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_write_prph
	mov	w0, #20
	bl	_udelay
Lloh42:
	adrp	x8, _APMG_PCIDEV_STT_REG@GOTPAGE
Lloh43:
	ldr	x8, [x8, _APMG_PCIDEV_STT_REG@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x8]
Lloh45:
	adrp	x8, _APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPAGE
Lloh46:
	ldr	x8, [x8, _APMG_PCIDEV_STT_VAL_L1_ACT_DIS@GOTPAGEOFF]
Lloh47:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bits_prph
Lloh48:
	adrp	x8, _APMG_RTC_INT_STT_REG@GOTPAGE
Lloh49:
	ldr	x8, [x8, _APMG_RTC_INT_STT_REG@GOTPAGEOFF]
Lloh50:
	ldr	w1, [x8]
Lloh51:
	adrp	x8, _APMG_RTC_INT_STT_RFKILL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _APMG_RTC_INT_STT_RFKILL@GOTPAGEOFF]
Lloh53:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_write_prph
LBB0_9:
Lloh54:
	adrp	x8, _STATUS_DEVICE_ENABLED@GOTPAGE
Lloh55:
	ldr	x8, [x8, _STATUS_DEVICE_ENABLED@GOTPAGEOFF]
Lloh56:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_set_bit
LBB0_10:
	mov	x0, x20
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh48, Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Init card's basic functions\n"

	.comm	_IWL_DEVICE_FAMILY_8000,8,3     ; @IWL_DEVICE_FAMILY_8000
	.comm	_CSR_GIO_CHICKEN_BITS,4,2       ; @CSR_GIO_CHICKEN_BITS
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER,4,2 ; @CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
	.comm	_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX,4,2 ; @CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
	.comm	_CSR_DBG_HPET_MEM_REG,4,2       ; @CSR_DBG_HPET_MEM_REG
	.comm	_CSR_DBG_HPET_MEM_REG_VAL,4,2   ; @CSR_DBG_HPET_MEM_REG_VAL
	.comm	_CSR_HW_IF_CONFIG_REG,4,2       ; @CSR_HW_IF_CONFIG_REG
	.comm	_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A,4,2 ; @CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
	.comm	_CSR_ANA_PLL_CFG,4,2            ; @CSR_ANA_PLL_CFG
	.comm	_CSR50_ANA_PLL_CFG_VAL,4,2      ; @CSR50_ANA_PLL_CFG_VAL
	.comm	_OSC_CLK,4,2                    ; @OSC_CLK
	.comm	_OSC_CLK_FORCE_CONTROL,4,2      ; @OSC_CLK_FORCE_CONTROL
	.comm	_APMG_CLK_EN_REG,4,2            ; @APMG_CLK_EN_REG
	.comm	_APMG_CLK_VAL_DMA_CLK_RQT,4,2   ; @APMG_CLK_VAL_DMA_CLK_RQT
	.comm	_APMG_PCIDEV_STT_REG,4,2        ; @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_L1_ACT_DIS,4,2 ; @APMG_PCIDEV_STT_VAL_L1_ACT_DIS
	.comm	_APMG_RTC_INT_STT_REG,4,2       ; @APMG_RTC_INT_STT_REG
	.comm	_APMG_RTC_INT_STT_RFKILL,4,2    ; @APMG_RTC_INT_STT_RFKILL
	.comm	_STATUS_DEVICE_ENABLED,4,2      ; @STATUS_DEVICE_ENABLED
	.no_dead_strip	_iwl_pcie_apm_init
.subsections_via_symbols
