	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_rp_irq_handler
_tegra_pcie_rp_irq_handler:             ## @tegra_pcie_rp_irq_handler
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	leaq	8(%rdi), %r14
	movq	_APPL_INTR_STATUS_L0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_appl_readl
	movl	%eax, %ebx
	movq	_APPL_INTR_STATUS_L0_LINK_STATE_INT@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_3
## %bb.1:
	movq	_APPL_INTR_STATUS_L1_0_0@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movl	%eax, %ebx
	movq	_APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_3
## %bb.2:
	movl	(%r12), %edx
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_appl_writel
	movq	_APPL_CAR_RESET_OVRD@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movq	_APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%rbx), %edx
	movq	%r15, %rdi
	callq	_appl_writel
	movl	$1, %edi
	callq	_udelay
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	orl	(%r12), %eax
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_appl_writel
	movq	_PORT_LOGIC_GEN2_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movl	%eax, %ebx
	movq	_PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movl	(%r12), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_dw_pcie_writel_dbi
LBB0_3:
	movq	_APPL_INTR_STATUS_L0_INT_INT@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_8
## %bb.4:
	movq	_APPL_INTR_STATUS_L1_8_0@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movl	%eax, %ebx
	movq	_APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	testl	%ebx, %esi
	je	LBB0_6
## %bb.5:
	leaq	12(%r15), %r12
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_appl_writel
	movq	%r12, %rdi
	callq	_apply_bad_link_workaround
LBB0_6:
	movq	_APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	testl	%ebx, %esi
	je	LBB0_8
## %bb.7:
	movl	(%r13), %edx
	movq	%r15, %rdi
	callq	_appl_writel
	movq	_PCI_EXP_LNKSTA@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	(%r15), %rsi
	movq	%r14, %rdi
	callq	_dw_pcie_readw_dbi
	movl	8(%r15), %edi
	movq	_PCI_EXP_LNKSTA_CLS@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	leaq	L_.str(%rip), %rsi
	movl	%eax, %edx
	callq	_dev_dbg
LBB0_8:
	movq	_APPL_INTR_STATUS_L0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movq	_APPL_INTR_STATUS_L0_CDM_REG_CHK_INT@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_16
## %bb.9:
	movq	_APPL_INTR_STATUS_L1_18@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movl	%eax, %r15d
	movq	_PCIE_PL_CHK_REG_CONTROL_STATUS@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movl	%eax, %ebx
	movq	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_11
## %bb.10:
	movl	(%r14), %edi
	leaq	L_.str.1(%rip), %rsi
	callq	_dev_info
	movq	_PCIE_PL_CHK_REG_CHK_REG_COMPLETE@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_11:
	movq	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_13
## %bb.12:
	movl	(%r14), %edi
	leaq	L_.str.2(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_err
	movq	_PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_13:
	movq	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR@GOTPCREL(%rip), %rax
	testl	%r15d, (%rax)
	je	LBB0_15
## %bb.14:
	movl	(%r14), %edi
	leaq	L_.str.3(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_err
	movq	_PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
LBB0_15:
	movl	(%r12), %esi
	movq	%r14, %rdi
	movl	%ebx, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCIE_PL_CHK_REG_ERR_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_dw_pcie_readl_dbi
	movl	(%r14), %edi
	leaq	L_.str.4(%rip), %rsi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	_dev_err
LBB0_16:
	movq	_IRQ_HANDLED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_APPL_INTR_STATUS_L0,4,2        ## @APPL_INTR_STATUS_L0
	.comm	_APPL_INTR_STATUS_L0_LINK_STATE_INT,4,2 ## @APPL_INTR_STATUS_L0_LINK_STATE_INT
	.comm	_APPL_INTR_STATUS_L1_0_0,4,2    ## @APPL_INTR_STATUS_L1_0_0
	.comm	_APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED,4,2 ## @APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED
	.comm	_APPL_CAR_RESET_OVRD,4,2        ## @APPL_CAR_RESET_OVRD
	.comm	_APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N,4,2 ## @APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N
	.comm	_PORT_LOGIC_GEN2_CTRL,4,2       ## @PORT_LOGIC_GEN2_CTRL
	.comm	_PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE,4,2 ## @PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE
	.comm	_APPL_INTR_STATUS_L0_INT_INT,4,2 ## @APPL_INTR_STATUS_L0_INT_INT
	.comm	_APPL_INTR_STATUS_L1_8_0,4,2    ## @APPL_INTR_STATUS_L1_8_0
	.comm	_APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,4,2 ## @APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS
	.comm	_APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,4,2 ## @APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS
	.comm	_PCI_EXP_LNKSTA,8,3             ## @PCI_EXP_LNKSTA
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Link Speed : Gen-%u\n"

	.comm	_PCI_EXP_LNKSTA_CLS,4,2         ## @PCI_EXP_LNKSTA_CLS
	.comm	_APPL_INTR_STATUS_L0_CDM_REG_CHK_INT,4,2 ## @APPL_INTR_STATUS_L0_CDM_REG_CHK_INT
	.comm	_APPL_INTR_STATUS_L1_18,4,2     ## @APPL_INTR_STATUS_L1_18
	.comm	_PCIE_PL_CHK_REG_CONTROL_STATUS,4,2 ## @PCIE_PL_CHK_REG_CONTROL_STATUS
	.comm	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT,4,2 ## @APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT
L_.str.1:                               ## @.str.1
	.asciz	"CDM check complete\n"

	.comm	_PCIE_PL_CHK_REG_CHK_REG_COMPLETE,4,2 ## @PCIE_PL_CHK_REG_CHK_REG_COMPLETE
	.comm	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR,4,2 ## @APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR
L_.str.2:                               ## @.str.2
	.asciz	"CDM comparison mismatch\n"

	.comm	_PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR,4,2 ## @PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR
	.comm	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR,4,2 ## @APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR
L_.str.3:                               ## @.str.3
	.asciz	"CDM Logic error\n"

	.comm	_PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR,4,2 ## @PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR
	.comm	_PCIE_PL_CHK_REG_ERR_ADDR,4,2   ## @PCIE_PL_CHK_REG_ERR_ADDR
L_.str.4:                               ## @.str.4
	.asciz	"CDM Error Address Offset = 0x%08X\n"

	.comm	_IRQ_HANDLED,4,2                ## @IRQ_HANDLED
	.no_dead_strip	_tegra_pcie_rp_irq_handler
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_rp_irq_handler
_tegra_pcie_rp_irq_handler:             ; @tegra_pcie_rp_irq_handler
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x0
	add	x19, x0, #8
Lloh0:
	adrp	x23, _APPL_INTR_STATUS_L0@GOTPAGE
Lloh1:
	ldr	x23, [x23, _APPL_INTR_STATUS_L0@GOTPAGEOFF]
	ldr	w1, [x23]
	bl	_appl_readl
Lloh2:
	adrp	x8, _APPL_INTR_STATUS_L0_LINK_STATE_INT@GOTPAGE
Lloh3:
	ldr	x8, [x8, _APPL_INTR_STATUS_L0_LINK_STATE_INT@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_3
; %bb.1:
Lloh5:
	adrp	x22, _APPL_INTR_STATUS_L1_0_0@GOTPAGE
Lloh6:
	ldr	x22, [x22, _APPL_INTR_STATUS_L1_0_0@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x20
	bl	_appl_readl
	mov	x21, x0
Lloh7:
	adrp	x8, _APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED@GOTPAGE
Lloh8:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_4
; %bb.2:
	ldr	w2, [x22]
	mov	x0, x20
	mov	x1, x21
	bl	_appl_writel
Lloh10:
	adrp	x21, _APPL_CAR_RESET_OVRD@GOTPAGE
Lloh11:
	ldr	x21, [x21, _APPL_CAR_RESET_OVRD@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x20
	bl	_appl_readl
Lloh12:
	adrp	x22, _APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N@GOTPAGE
Lloh13:
	ldr	x22, [x22, _APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N@GOTPAGEOFF]
	ldr	w8, [x22]
	bic	w1, w0, w8
	ldr	w2, [x21]
	mov	x0, x20
	bl	_appl_writel
	mov	w0, #1
	bl	_udelay
	ldr	w1, [x21]
	mov	x0, x20
	bl	_appl_readl
	ldr	w8, [x22]
	orr	w1, w8, w0
	ldr	w2, [x21]
	mov	x0, x20
	bl	_appl_writel
Lloh14:
	adrp	x22, _PORT_LOGIC_GEN2_CTRL@GOTPAGE
Lloh15:
	ldr	x22, [x22, _PORT_LOGIC_GEN2_CTRL@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh16:
	adrp	x8, _PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	orr	w21, w8, w0
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x21
	bl	_dw_pcie_writel_dbi
	b	LBB0_4
LBB0_3:
	mov	x21, x0
LBB0_4:
Lloh19:
	adrp	x8, _APPL_INTR_STATUS_L0_INT_INT@GOTPAGE
Lloh20:
	ldr	x8, [x8, _APPL_INTR_STATUS_L0_INT_INT@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_9
; %bb.5:
Lloh22:
	adrp	x24, _APPL_INTR_STATUS_L1_8_0@GOTPAGE
Lloh23:
	ldr	x24, [x24, _APPL_INTR_STATUS_L1_8_0@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x20
	bl	_appl_readl
	mov	x21, x0
Lloh24:
	adrp	x8, _APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS@GOTPAGE
Lloh25:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	tst	w1, w0
	b.eq	LBB0_7
; %bb.6:
	add	x22, x20, #12
	ldr	w2, [x24]
	mov	x0, x20
	bl	_appl_writel
	mov	x0, x22
	bl	_apply_bad_link_workaround
LBB0_7:
Lloh27:
	adrp	x8, _APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS@GOTPAGE
Lloh28:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	tst	w1, w21
	b.eq	LBB0_9
; %bb.8:
	ldr	w2, [x24]
	mov	x0, x20
	bl	_appl_writel
	ldr	x8, [x20]
Lloh30:
	adrp	x9, _PCI_EXP_LNKSTA@GOTPAGE
Lloh31:
	ldr	x9, [x9, _PCI_EXP_LNKSTA@GOTPAGEOFF]
Lloh32:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x19
	bl	_dw_pcie_readw_dbi
	ldr	w8, [x20, #8]
Lloh33:
	adrp	x9, _PCI_EXP_LNKSTA_CLS@GOTPAGE
Lloh34:
	ldr	x9, [x9, _PCI_EXP_LNKSTA_CLS@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	and	w2, w9, w0
Lloh36:
	adrp	x1, l_.str@PAGE
Lloh37:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x8
	bl	_dev_dbg
LBB0_9:
	ldr	w1, [x23]
	mov	x0, x20
	bl	_appl_readl
Lloh38:
	adrp	x8, _APPL_INTR_STATUS_L0_CDM_REG_CHK_INT@GOTPAGE
Lloh39:
	ldr	x8, [x8, _APPL_INTR_STATUS_L0_CDM_REG_CHK_INT@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	tst	w8, w0
	b.eq	LBB0_17
; %bb.10:
Lloh41:
	adrp	x8, _APPL_INTR_STATUS_L1_18@GOTPAGE
Lloh42:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_18@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_appl_readl
	mov	x21, x0
Lloh44:
	adrp	x22, _PCIE_PL_CHK_REG_CONTROL_STATUS@GOTPAGE
Lloh45:
	ldr	x22, [x22, _PCIE_PL_CHK_REG_CONTROL_STATUS@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	mov	x20, x0
Lloh46:
	adrp	x8, _APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT@GOTPAGE
Lloh47:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_12
; %bb.11:
	ldr	w0, [x19]
Lloh49:
	adrp	x1, l_.str.1@PAGE
Lloh50:
	add	x1, x1, l_.str.1@PAGEOFF
	bl	_dev_info
Lloh51:
	adrp	x8, _PCIE_PL_CHK_REG_CHK_REG_COMPLETE@GOTPAGE
Lloh52:
	ldr	x8, [x8, _PCIE_PL_CHK_REG_CHK_REG_COMPLETE@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_12:
Lloh54:
	adrp	x8, _APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR@GOTPAGE
Lloh55:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_14
; %bb.13:
	ldr	w0, [x19]
Lloh57:
	adrp	x1, l_.str.2@PAGE
Lloh58:
	add	x1, x1, l_.str.2@PAGEOFF
	bl	_dev_err
Lloh59:
	adrp	x8, _PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR@GOTPAGE
Lloh60:
	ldr	x8, [x8, _PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR@GOTPAGEOFF]
Lloh61:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_14:
Lloh62:
	adrp	x8, _APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR@GOTPAGE
Lloh63:
	ldr	x8, [x8, _APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR@GOTPAGEOFF]
Lloh64:
	ldr	w8, [x8]
	tst	w8, w21
	b.eq	LBB0_16
; %bb.15:
	ldr	w0, [x19]
Lloh65:
	adrp	x1, l_.str.3@PAGE
Lloh66:
	add	x1, x1, l_.str.3@PAGEOFF
	bl	_dev_err
Lloh67:
	adrp	x8, _PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR@GOTPAGE
Lloh68:
	ldr	x8, [x8, _PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR@GOTPAGEOFF]
Lloh69:
	ldr	w8, [x8]
	orr	w20, w8, w20
LBB0_16:
	ldr	w1, [x22]
	mov	x0, x19
	mov	x2, x20
	bl	_dw_pcie_writel_dbi
Lloh70:
	adrp	x8, _PCIE_PL_CHK_REG_ERR_ADDR@GOTPAGE
Lloh71:
	ldr	x8, [x8, _PCIE_PL_CHK_REG_ERR_ADDR@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
                                        ; kill: def $w0 killed $w0 def $x0
	ldr	w8, [x19]
	str	x0, [sp]
Lloh73:
	adrp	x1, l_.str.4@PAGE
Lloh74:
	add	x1, x1, l_.str.4@PAGEOFF
	mov	x0, x8
	bl	_dev_err
LBB0_17:
Lloh75:
	adrp	x8, _IRQ_HANDLED@GOTPAGE
Lloh76:
	ldr	x8, [x8, _IRQ_HANDLED@GOTPAGEOFF]
Lloh77:
	ldr	w0, [x8]
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpAdd	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpAdd	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpAdd	Lloh65, Lloh66
	.loh AdrpAdd	Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.cfi_endproc
                                        ; -- End function
	.comm	_APPL_INTR_STATUS_L0,4,2        ; @APPL_INTR_STATUS_L0
	.comm	_APPL_INTR_STATUS_L0_LINK_STATE_INT,4,2 ; @APPL_INTR_STATUS_L0_LINK_STATE_INT
	.comm	_APPL_INTR_STATUS_L1_0_0,4,2    ; @APPL_INTR_STATUS_L1_0_0
	.comm	_APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED,4,2 ; @APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED
	.comm	_APPL_CAR_RESET_OVRD,4,2        ; @APPL_CAR_RESET_OVRD
	.comm	_APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N,4,2 ; @APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N
	.comm	_PORT_LOGIC_GEN2_CTRL,4,2       ; @PORT_LOGIC_GEN2_CTRL
	.comm	_PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE,4,2 ; @PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE
	.comm	_APPL_INTR_STATUS_L0_INT_INT,4,2 ; @APPL_INTR_STATUS_L0_INT_INT
	.comm	_APPL_INTR_STATUS_L1_8_0,4,2    ; @APPL_INTR_STATUS_L1_8_0
	.comm	_APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,4,2 ; @APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS
	.comm	_APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,4,2 ; @APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS
	.comm	_PCI_EXP_LNKSTA,8,3             ; @PCI_EXP_LNKSTA
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Link Speed : Gen-%u\n"

	.comm	_PCI_EXP_LNKSTA_CLS,4,2         ; @PCI_EXP_LNKSTA_CLS
	.comm	_APPL_INTR_STATUS_L0_CDM_REG_CHK_INT,4,2 ; @APPL_INTR_STATUS_L0_CDM_REG_CHK_INT
	.comm	_APPL_INTR_STATUS_L1_18,4,2     ; @APPL_INTR_STATUS_L1_18
	.comm	_PCIE_PL_CHK_REG_CONTROL_STATUS,4,2 ; @PCIE_PL_CHK_REG_CONTROL_STATUS
	.comm	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT,4,2 ; @APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT
l_.str.1:                               ; @.str.1
	.asciz	"CDM check complete\n"

	.comm	_PCIE_PL_CHK_REG_CHK_REG_COMPLETE,4,2 ; @PCIE_PL_CHK_REG_CHK_REG_COMPLETE
	.comm	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR,4,2 ; @APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR
l_.str.2:                               ; @.str.2
	.asciz	"CDM comparison mismatch\n"

	.comm	_PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR,4,2 ; @PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR
	.comm	_APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR,4,2 ; @APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR
l_.str.3:                               ; @.str.3
	.asciz	"CDM Logic error\n"

	.comm	_PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR,4,2 ; @PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR
	.comm	_PCIE_PL_CHK_REG_ERR_ADDR,4,2   ; @PCIE_PL_CHK_REG_ERR_ADDR
l_.str.4:                               ; @.str.4
	.asciz	"CDM Error Address Offset = 0x%08X\n"

	.comm	_IRQ_HANDLED,4,2                ; @IRQ_HANDLED
	.no_dead_strip	_tegra_pcie_rp_irq_handler
.subsections_via_symbols
