	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function il4965_alive_notify
_il4965_alive_notify:                   ## @il4965_alive_notify
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	addq	$8, %rdi
	movq	%rdi, -48(%rbp)                 ## 8-byte Spill
	callq	_spin_lock_irqsave
	movq	_IL49_SCD_SRAM_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_il_rd_prph
	movq	%rax, %r12
	movq	%rax, (%r15)
	movq	_IL49_SCD_CONTEXT_DATA_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%r12, %rbx
	addq	%rax, %rbx
	movq	_IL49_SCD_TX_STTS_BITMAP_OFFSET@GOTPCREL(%rip), %r14
	cmpq	(%r14), %rax
	jge	LBB0_1
	.p2align	4, 0x90
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_il_write_targ_mem
	addq	$4, %rbx
	movq	(%r15), %r12
	movq	(%r14), %rax
	addq	%r12, %rax
	cmpq	%rax, %rbx
	jl	LBB0_18
LBB0_1:
	movq	_IL49_SCD_TRANSLATE_TBL_OFFSET@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rax
	addq	%r12, %rax
	cmpq	%rax, %rbx
	jge	LBB0_3
## %bb.19:                              ##   in Loop: Header=BB0_2 Depth=1
	movq	%r15, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_il_write_targ_mem
	addq	$4, %rbx
	movq	(%r15), %r12
	jmp	LBB0_2
LBB0_3:
	movl	48(%r15), %edi
	callq	_IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE
	addq	%r12, %rax
	cmpq	%rax, %rbx
	jge	LBB0_6
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	_il_write_targ_mem
	addq	$4, %rbx
	movq	(%r15), %r14
	movl	48(%r15), %edi
	callq	_IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE
	addq	%r14, %rax
	cmpq	%rax, %rbx
	jl	LBB0_4
LBB0_6:
	movq	_IL49_SCD_DRAM_BASE_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	52(%r15), %edx
	sarl	$10, %edx
	movq	%r15, %rdi
	callq	_il_wr_prph
	movq	_FH49_TCSR_CHNL_NUM@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_9
## %bb.7:
	xorl	%ebx, %ebx
	movq	_FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPCREL(%rip), %r12
	movq	_FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_8:                                 ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	_FH49_TCSR_CHNL_TX_CONFIG_REG
	movl	(%r13), %edx
	orl	(%r12), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_il_wr
	incl	%ebx
	cmpl	(%r14), %ebx
	jl	LBB0_8
LBB0_9:
	movq	_FH49_TX_CHICKEN_BITS_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_il_rd
	movl	(%rbx), %esi
	movq	_FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_il_wr
	movq	_IL49_SCD_QUEUECHAIN_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%r12d, %r12d
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_il_wr_prph
	movl	48(%r15), %ecx
	testl	%ecx, %ecx
	jle	LBB0_12
## %bb.10:
	movq	_IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK@GOTPCREL(%rip), %r14
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_11:                                ## =>This Inner Loop Header: Depth=1
	movl	%ebx, %edi
	callq	_IL49_SCD_QUEUE_RDPTR
	movq	%r15, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_il_wr_prph
	movq	_HBUS_TARG_WRPTR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_il_wr
	movq	(%r15), %r13
	movl	%ebx, %edi
	callq	_IL49_SCD_CONTEXT_QUEUE_OFFSET
	movq	_SCD_WIN_SIZE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	shll	%cl, %edx
	addq	%rax, %r13
	movq	_IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK@GOTPCREL(%rip), %rax
	andl	(%rax), %edx
	movq	%r15, %rdi
	movq	%r13, %rsi
	callq	_il_write_targ_mem
	movq	(%r15), %r13
	movl	%ebx, %edi
	callq	_IL49_SCD_CONTEXT_QUEUE_OFFSET
	movq	_SCD_FRAME_LIMIT@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS@GOTPCREL(%rip), %rcx
	movzbl	(%rcx), %ecx
	shll	%cl, %edx
	leaq	(%rax,%r13), %rsi
	addq	$8, %rsi
	andl	(%r14), %edx
	movq	%r15, %rdi
	callq	_il_write_targ_mem
	incl	%ebx
	movl	48(%r15), %ecx
	addl	$256, %r12d                     ## imm = 0x100
	cmpl	%ecx, %ebx
	jl	LBB0_11
LBB0_12:
	movq	_IL49_SCD_INTERRUPT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$-1, %edx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %edx
	notl	%edx
	movq	%r15, %rdi
	callq	_il_wr_prph
	xorl	%edi, %edi
	movl	$6, %esi
	callq	_IL_MASK
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_il4965_txq_set_sched
	movq	_IL_DEFAULT_CMD_QUEUE_NUM@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_il4965_set_wr_ptrs
	movq	40(%r15), %rdi
	xorl	%esi, %esi
	movl	$8, %edx
	callq	_memset
	movq	32(%r15), %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	movq	32(%r15), %rdi
	addq	$4, %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	movq	32(%r15), %rdi
	addq	$8, %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	movq	32(%r15), %rdi
	addq	$12, %rdi
	xorl	%esi, %esi
	callq	_atomic_set
	movq	$0, 24(%r15)
	movq	_default_queue_to_tx_fifo@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	callq	_ARRAY_SIZE
	xorl	%edi, %edi
	cmpl	$7, %eax
	setne	%dil
	callq	_BUILD_BUG_ON
	movq	(%r14), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_17
## %bb.13:
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
	jmp	LBB0_14
	.p2align	4, 0x90
LBB0_16:                                ##   in Loop: Header=BB0_14 Depth=1
	incq	%rbx
	movq	(%r14), %rdi
	callq	_ARRAY_SIZE
	cltq
	addq	$4, %r13
	cmpq	%rax, %rbx
	jge	LBB0_17
LBB0_14:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r14), %rax
	movl	(%rax,%r13), %r12d
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_il_txq_ctx_activate
	movq	_IL_TX_FIFO_UNUSED@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r12d
	je	LBB0_16
## %bb.15:                              ##   in Loop: Header=BB0_14 Depth=1
	movq	16(%r15), %rsi
	addq	%r13, %rsi
	movq	%r15, %rdi
	movl	%r12d, %edx
	xorl	%ecx, %ecx
	callq	_il4965_tx_queue_set_status
	jmp	LBB0_16
LBB0_17:
	movq	-48(%rbp), %rdi                 ## 8-byte Reload
	callq	_spin_unlock_irqrestore
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IL49_SCD_SRAM_BASE_ADDR,4,2    ## @IL49_SCD_SRAM_BASE_ADDR
	.comm	_IL49_SCD_CONTEXT_DATA_OFFSET,8,3 ## @IL49_SCD_CONTEXT_DATA_OFFSET
	.comm	_IL49_SCD_TX_STTS_BITMAP_OFFSET,8,3 ## @IL49_SCD_TX_STTS_BITMAP_OFFSET
	.comm	_IL49_SCD_TRANSLATE_TBL_OFFSET,8,3 ## @IL49_SCD_TRANSLATE_TBL_OFFSET
	.comm	_IL49_SCD_DRAM_BASE_ADDR,4,2    ## @IL49_SCD_DRAM_BASE_ADDR
	.comm	_FH49_TCSR_CHNL_NUM,4,2         ## @FH49_TCSR_CHNL_NUM
	.comm	_FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE,4,2 ## @FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
	.comm	_FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE,4,2 ## @FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
	.comm	_FH49_TX_CHICKEN_BITS_REG,4,2   ## @FH49_TX_CHICKEN_BITS_REG
	.comm	_FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN,8,3 ## @FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
	.comm	_IL49_SCD_QUEUECHAIN_SEL,4,2    ## @IL49_SCD_QUEUECHAIN_SEL
	.comm	_HBUS_TARG_WRPTR,4,2            ## @HBUS_TARG_WRPTR
	.comm	_SCD_WIN_SIZE,4,2               ## @SCD_WIN_SIZE
	.comm	_IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS,4,2 ## @IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS
	.comm	_IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK,4,2 ## @IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK
	.comm	_SCD_FRAME_LIMIT,4,2            ## @SCD_FRAME_LIMIT
	.comm	_IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS,4,2 ## @IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
	.comm	_IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK,4,2 ## @IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
	.comm	_IL49_SCD_INTERRUPT_MASK,4,2    ## @IL49_SCD_INTERRUPT_MASK
	.comm	_IL_DEFAULT_CMD_QUEUE_NUM,4,2   ## @IL_DEFAULT_CMD_QUEUE_NUM
	.comm	_default_queue_to_tx_fifo,8,3   ## @default_queue_to_tx_fifo
	.comm	_IL_TX_FIFO_UNUSED,4,2          ## @IL_TX_FIFO_UNUSED
	.no_dead_strip	_il4965_alive_notify
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function il4965_alive_notify
_il4965_alive_notify:                   ; @il4965_alive_notify
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x0
	add	x25, x0, #8
	mov	x0, x25
	bl	_spin_lock_irqsave
Lloh0:
	adrp	x8, _IL49_SCD_SRAM_BASE_ADDR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _IL49_SCD_SRAM_BASE_ADDR@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x20
	bl	_il_rd_prph
	str	x0, [x20]
Lloh3:
	adrp	x8, _IL49_SCD_CONTEXT_DATA_OFFSET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _IL49_SCD_CONTEXT_DATA_OFFSET@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	add	x21, x8, x0
Lloh6:
	adrp	x19, _IL49_SCD_TX_STTS_BITMAP_OFFSET@GOTPAGE
Lloh7:
	ldr	x19, [x19, _IL49_SCD_TX_STTS_BITMAP_OFFSET@GOTPAGEOFF]
	ldr	x9, [x19]
	cmp	x8, x9
	b.ge	LBB0_2
LBB0_1:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	mov	x1, x21
	mov	w2, #0
	bl	_il_write_targ_mem
	add	x21, x21, #4
	ldr	x22, [x20]
	ldr	x8, [x19]
	add	x8, x8, x22
	cmp	x21, x8
	b.lt	LBB0_1
	b	LBB0_3
LBB0_2:
	mov	x22, x0
LBB0_3:
Lloh8:
	adrp	x19, _IL49_SCD_TRANSLATE_TBL_OFFSET@GOTPAGE
Lloh9:
	ldr	x19, [x19, _IL49_SCD_TRANSLATE_TBL_OFFSET@GOTPAGEOFF]
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	add	x8, x8, x22
	cmp	x21, x8
	b.ge	LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	x0, x20
	mov	x1, x21
	mov	w2, #0
	bl	_il_write_targ_mem
	add	x21, x21, #4
	ldr	x22, [x20]
	b	LBB0_4
LBB0_6:
	ldr	w0, [x20, #48]
	bl	_IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE
	add	x8, x0, x22
	cmp	x21, x8
	b.ge	LBB0_8
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	mov	x1, x21
	mov	w2, #0
	bl	_il_write_targ_mem
	add	x21, x21, #4
	ldr	x19, [x20]
	ldr	w0, [x20, #48]
	bl	_IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE
	add	x8, x0, x19
	cmp	x21, x8
	b.lt	LBB0_7
LBB0_8:
Lloh10:
	adrp	x8, _IL49_SCD_DRAM_BASE_ADDR@GOTPAGE
Lloh11:
	ldr	x8, [x8, _IL49_SCD_DRAM_BASE_ADDR@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	ldr	w8, [x20, #52]
	asr	w2, w8, #10
	mov	x0, x20
	bl	_il_wr_prph
Lloh13:
	adrp	x19, _FH49_TCSR_CHNL_NUM@GOTPAGE
Lloh14:
	ldr	x19, [x19, _FH49_TCSR_CHNL_NUM@GOTPAGEOFF]
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_11
; %bb.9:
	mov	w21, #0
Lloh15:
	adrp	x22, _FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPAGE
Lloh16:
	ldr	x22, [x22, _FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE@GOTPAGEOFF]
Lloh17:
	adrp	x23, _FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE@GOTPAGE
Lloh18:
	ldr	x23, [x23, _FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE@GOTPAGEOFF]
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x21
	bl	_FH49_TCSR_CHNL_TX_CONFIG_REG
	mov	x1, x0
	ldr	w8, [x22]
	ldr	w9, [x23]
	orr	w2, w9, w8
	mov	x0, x20
	bl	_il_wr
	add	w21, w21, #1
	ldr	w8, [x19]
	cmp	w21, w8
	b.lt	LBB0_10
LBB0_11:
Lloh19:
	adrp	x19, _FH49_TX_CHICKEN_BITS_REG@GOTPAGE
Lloh20:
	ldr	x19, [x19, _FH49_TX_CHICKEN_BITS_REG@GOTPAGEOFF]
	ldr	w1, [x19]
	mov	x0, x20
	bl	_il_rd
	ldr	w1, [x19]
Lloh21:
	adrp	x8, _FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN@GOTPAGE
Lloh22:
	ldr	x8, [x8, _FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x20
	bl	_il_wr
Lloh24:
	adrp	x8, _IL49_SCD_QUEUECHAIN_SEL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _IL49_SCD_QUEUECHAIN_SEL@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_il_wr_prph
	ldr	w8, [x20, #48]
	cmp	w8, #1
	b.lt	LBB0_15
; %bb.12:
	str	x25, [sp, #8]                   ; 8-byte Folded Spill
	mov	w21, #0
	mov	w22, #0
Lloh27:
	adrp	x24, _SCD_WIN_SIZE@GOTPAGE
Lloh28:
	ldr	x24, [x24, _SCD_WIN_SIZE@GOTPAGEOFF]
Lloh29:
	adrp	x25, _IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS@GOTPAGE
Lloh30:
	ldr	x25, [x25, _IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS@GOTPAGEOFF]
Lloh31:
	adrp	x26, _IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK@GOTPAGE
Lloh32:
	ldr	x26, [x26, _IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK@GOTPAGEOFF]
Lloh33:
	adrp	x27, _SCD_FRAME_LIMIT@GOTPAGE
Lloh34:
	ldr	x27, [x27, _SCD_FRAME_LIMIT@GOTPAGEOFF]
Lloh35:
	adrp	x28, _IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS@GOTPAGE
Lloh36:
	ldr	x28, [x28, _IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS@GOTPAGEOFF]
Lloh37:
	adrp	x19, _IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK@GOTPAGE
Lloh38:
	ldr	x19, [x19, _IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK@GOTPAGEOFF]
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x22
	bl	_IL49_SCD_QUEUE_RDPTR
	mov	x1, x0
	mov	x0, x20
	mov	w2, #0
	bl	_il_wr_prph
Lloh39:
	adrp	x8, _HBUS_TARG_WRPTR@GOTPAGE
Lloh40:
	ldr	x8, [x8, _HBUS_TARG_WRPTR@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x20
	mov	x2, x21
	bl	_il_wr
	ldr	x23, [x20]
	mov	x0, x22
	bl	_IL49_SCD_CONTEXT_QUEUE_OFFSET
	add	x1, x0, x23
	ldr	w8, [x24]
	ldr	w9, [x25]
	lsl	w8, w8, w9
	ldr	w9, [x26]
	and	w2, w8, w9
	mov	x0, x20
	bl	_il_write_targ_mem
	ldr	x23, [x20]
	mov	x0, x22
	bl	_IL49_SCD_CONTEXT_QUEUE_OFFSET
	add	x8, x23, x0
	add	x1, x8, #8
	ldr	w8, [x27]
	ldr	w9, [x28]
	lsl	w8, w8, w9
	ldr	w9, [x19]
	and	w2, w8, w9
	mov	x0, x20
	bl	_il_write_targ_mem
	add	w22, w22, #1
	ldr	w8, [x20, #48]
	add	w21, w21, #256
	cmp	w22, w8
	b.lt	LBB0_13
; %bb.14:
	ldr	x25, [sp, #8]                   ; 8-byte Folded Reload
LBB0_15:
Lloh42:
	adrp	x9, _IL49_SCD_INTERRUPT_MASK@GOTPAGE
Lloh43:
	ldr	x9, [x9, _IL49_SCD_INTERRUPT_MASK@GOTPAGEOFF]
Lloh44:
	ldr	w1, [x9]
	mov	w9, #-1
	lsl	w8, w9, w8
	mvn	w2, w8
	mov	x0, x20
	bl	_il_wr_prph
	mov	w0, #0
	mov	w1, #6
	bl	_IL_MASK
	mov	x1, x0
	mov	x0, x20
	bl	_il4965_txq_set_sched
Lloh45:
	adrp	x8, _IL_DEFAULT_CMD_QUEUE_NUM@GOTPAGE
Lloh46:
	ldr	x8, [x8, _IL_DEFAULT_CMD_QUEUE_NUM@GOTPAGEOFF]
Lloh47:
	ldr	w1, [x8]
	mov	x0, x20
	mov	w2, #0
	bl	_il4965_set_wr_ptrs
	ldr	x0, [x20, #40]
	mov	w1, #0
	mov	w2, #8
	bl	_memset
	ldr	x0, [x20, #32]
	mov	w1, #0
	bl	_atomic_set
	ldr	x8, [x20, #32]
	add	x0, x8, #4
	mov	w1, #0
	bl	_atomic_set
	ldr	x8, [x20, #32]
	add	x0, x8, #8
	mov	w1, #0
	bl	_atomic_set
	ldr	x8, [x20, #32]
	add	x0, x8, #12
	mov	w1, #0
	bl	_atomic_set
	str	xzr, [x20, #24]
Lloh48:
	adrp	x19, _default_queue_to_tx_fifo@GOTPAGE
Lloh49:
	ldr	x19, [x19, _default_queue_to_tx_fifo@GOTPAGEOFF]
	ldr	x0, [x19]
	bl	_ARRAY_SIZE
	cmp	w0, #7
	cset	w0, ne
	bl	_BUILD_BUG_ON
	ldr	x0, [x19]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_20
; %bb.16:
	mov	x23, #0
	mov	x21, #0
Lloh50:
	adrp	x24, _IL_TX_FIFO_UNUSED@GOTPAGE
Lloh51:
	ldr	x24, [x24, _IL_TX_FIFO_UNUSED@GOTPAGEOFF]
	b	LBB0_18
LBB0_17:                                ;   in Loop: Header=BB0_18 Depth=1
	add	x21, x21, #1
	ldr	x0, [x19]
	bl	_ARRAY_SIZE
	add	x23, x23, #4
	cmp	x21, w0, sxtw
	b.ge	LBB0_20
LBB0_18:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x19]
	ldr	w22, [x8, x23]
	mov	x0, x20
	mov	x1, x21
	bl	_il_txq_ctx_activate
	ldr	w8, [x24]
	cmp	w22, w8
	b.eq	LBB0_17
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=1
	ldr	x8, [x20, #16]
	add	x1, x8, x23
	mov	x0, x20
	mov	x2, x22
	mov	w3, #0
	bl	_il4965_tx_queue_set_status
	b	LBB0_17
LBB0_20:
	mov	x0, x25
	bl	_spin_unlock_irqrestore
	mov	w0, #0
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh47
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGot	Lloh50, Lloh51
	.cfi_endproc
                                        ; -- End function
	.comm	_IL49_SCD_SRAM_BASE_ADDR,4,2    ; @IL49_SCD_SRAM_BASE_ADDR
	.comm	_IL49_SCD_CONTEXT_DATA_OFFSET,8,3 ; @IL49_SCD_CONTEXT_DATA_OFFSET
	.comm	_IL49_SCD_TX_STTS_BITMAP_OFFSET,8,3 ; @IL49_SCD_TX_STTS_BITMAP_OFFSET
	.comm	_IL49_SCD_TRANSLATE_TBL_OFFSET,8,3 ; @IL49_SCD_TRANSLATE_TBL_OFFSET
	.comm	_IL49_SCD_DRAM_BASE_ADDR,4,2    ; @IL49_SCD_DRAM_BASE_ADDR
	.comm	_FH49_TCSR_CHNL_NUM,4,2         ; @FH49_TCSR_CHNL_NUM
	.comm	_FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE,4,2 ; @FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
	.comm	_FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE,4,2 ; @FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE
	.comm	_FH49_TX_CHICKEN_BITS_REG,4,2   ; @FH49_TX_CHICKEN_BITS_REG
	.comm	_FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN,8,3 ; @FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN
	.comm	_IL49_SCD_QUEUECHAIN_SEL,4,2    ; @IL49_SCD_QUEUECHAIN_SEL
	.comm	_HBUS_TARG_WRPTR,4,2            ; @HBUS_TARG_WRPTR
	.comm	_SCD_WIN_SIZE,4,2               ; @SCD_WIN_SIZE
	.comm	_IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS,4,2 ; @IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS
	.comm	_IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK,4,2 ; @IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK
	.comm	_SCD_FRAME_LIMIT,4,2            ; @SCD_FRAME_LIMIT
	.comm	_IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS,4,2 ; @IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS
	.comm	_IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK,4,2 ; @IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK
	.comm	_IL49_SCD_INTERRUPT_MASK,4,2    ; @IL49_SCD_INTERRUPT_MASK
	.comm	_IL_DEFAULT_CMD_QUEUE_NUM,4,2   ; @IL_DEFAULT_CMD_QUEUE_NUM
	.comm	_default_queue_to_tx_fifo,8,3   ; @default_queue_to_tx_fifo
	.comm	_IL_TX_FIFO_UNUSED,4,2          ; @IL_TX_FIFO_UNUSED
	.no_dead_strip	_il4965_alive_notify
.subsections_via_symbols
