	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlxsw_sx_from_ptys_supported_port
_mlxsw_sx_from_ptys_supported_port:     ## @mlxsw_sx_from_ptys_supported_port
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPCREL(%rip), %rax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ecx
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPCREL(%rip), %rax
	orl	(%rax), %ecx
	testl	%edi, %ecx
	je	LBB0_2
## %bb.1:
	movq	_SUPPORTED_FIBRE@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_2:
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPCREL(%rip), %rcx
	movq	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	orl	(%rcx), %eax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	andl	%edi, %eax
	je	LBB0_5
## %bb.3:
	movq	_SUPPORTED_Backplane@GOTPCREL(%rip), %rax
LBB0_4:
	movl	(%rax), %eax
LBB0_5:
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_SGMII,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_SGMII
	.comm	_SUPPORTED_FIBRE,4,2            ## @SUPPORTED_FIBRE
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,4,2 ## @MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX
	.comm	_SUPPORTED_Backplane,4,2        ## @SUPPORTED_Backplane
	.no_dead_strip	_mlxsw_sx_from_ptys_supported_port
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlxsw_sx_from_ptys_supported_port
_mlxsw_sx_from_ptys_supported_port:     ; @mlxsw_sx_from_ptys_supported_port
	.cfi_startproc
; %bb.0:
Lloh0:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
Lloh3:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPAGE
Lloh4:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR@GOTPAGEOFF]
Lloh5:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh6:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPAGE
Lloh7:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
Lloh9:
	adrp	x10, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPAGE
Lloh10:
	ldr	x10, [x10, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh11:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh12:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPAGE
Lloh13:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh15:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPAGE
Lloh16:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_SGMII@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	orr	w8, w8, w9
	tst	w8, w0
	b.eq	LBB0_2
; %bb.1:
Lloh18:
	adrp	x8, _SUPPORTED_FIBRE@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SUPPORTED_FIBRE@GOTPAGEOFF]
Lloh20:
	ldr	w0, [x8]
	ret
LBB0_2:
Lloh21:
	adrp	x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPAGE
Lloh22:
	ldr	x8, [x8, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPAGE
Lloh25:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	adrp	x10, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPAGE
Lloh31:
	ldr	x10, [x10, _MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh32:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh33:
	adrp	x9, _MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX@GOTPAGE
Lloh34:
	ldr	x9, [x9, _MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh36:
	adrp	x9, _SUPPORTED_Backplane@GOTPAGE
Lloh37:
	ldr	x9, [x9, _SUPPORTED_Backplane@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	tst	w8, w0
	csel	w0, wzr, w9, eq
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.cfi_endproc
                                        ; -- End function
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_SGMII,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_SGMII
	.comm	_SUPPORTED_FIBRE,4,2            ; @SUPPORTED_FIBRE
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4
	.comm	_MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,4,2 ; @MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX
	.comm	_SUPPORTED_Backplane,4,2        ; @SUPPORTED_Backplane
	.no_dead_strip	_mlxsw_sx_from_ptys_supported_port
.subsections_via_symbols
