	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_prepare_host
_tegra_pcie_prepare_host:               ## @tegra_pcie_prepare_host
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_to_dw_pcie_from_pp
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_to_tegra_pcie
	movq	%rax, %r15
	movq	_PCI_IO_BASE@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_IO_BASE_IO_DECODE@GOTPCREL(%rip), %rcx
	movq	_IO_BASE_IO_DECODE_BIT8@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PCI_PREF_MEMORY_BASE@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCI_BASE_ADDRESS_0@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PORT_LOGIC_ACK_F_ASPM_CTRL@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_N_FTS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_N_FTS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_N_FTS_VAL@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	shll	%cl, %edx
	notl	%esi
	andl	%eax, %esi
	orl	%esi, %edx
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PORT_LOGIC_GEN2_CTRL@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_FTS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	_FTS_VAL@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_AMBA_ERROR_RESPONSE_CRS_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_AMBA_ERROR_RESPONSE_CRS_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %esi
	movq	_AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	shll	%cl, %edx
	notl	%esi
	andl	%eax, %esi
	orl	%esi, %edx
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movl	(%r15), %eax
	testl	%eax, %eax
	je	LBB0_3
## %bb.1:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
	addl	(%rcx), %eax
	je	LBB0_3
## %bb.2:
	movq	_PCI_EXP_LNKCAP@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	addq	24(%r15), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PCI_EXP_LNKCAP_SLS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	orl	(%r15), %edx
	movq	(%r12), %rsi
	addq	24(%r15), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
LBB0_3:
	movq	_PCI_EXP_LNKCAP@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	addq	24(%r15), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PCI_EXP_LNKCAP_MLW@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	notl	%esi
	andl	%eax, %esi
	movl	4(%r15), %edx
	movq	_PCI_EXP_LNKSTA_NLW_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edx
	orl	%esi, %edx
	movq	(%r12), %rsi
	addq	24(%r15), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	movq	%r15, %rdi
	callq	_config_gen3_gen4_eq_presets
	movq	%r15, %rdi
	callq	_init_host_aspm
	movq	_GEN3_RELATED_OFF@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	cmpq	$0, 16(%r15)
	je	LBB0_5
## %bb.4:
	movq	_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF@GOTPCREL(%rip), %r12
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_CFG_TIMER_CTRL_ACK_NAK_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	btsl	%ecx, %eax
	movq	(%r12), %rsi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi
LBB0_5:
	movq	%r14, %rdi
	callq	_dw_pcie_setup_rc
	movl	8(%r15), %edi
	movq	_GEN4_CORE_CLK_FREQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_clk_set_rate
	movq	_APPL_PINMUX@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movq	_APPL_PINMUX_PEX_RST@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	notl	%esi
	andl	%eax, %esi
	movl	(%r12), %edx
	movq	%r15, %rdi
	callq	_appl_writel
	movl	$100, %edi
	movl	$200, %esi
	callq	_usleep_range
	movq	_APPL_CTRL@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	movq	_APPL_CTRL_LTSSM_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_appl_writel
	movl	(%r12), %esi
	movq	%r15, %rdi
	callq	_appl_readl
	orl	(%r14), %eax
	movl	(%r12), %edx
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_appl_writel
	movl	$100, %edi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_msleep                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_IO_BASE,8,3                ## @PCI_IO_BASE
	.comm	_IO_BASE_IO_DECODE,4,2          ## @IO_BASE_IO_DECODE
	.comm	_IO_BASE_IO_DECODE_BIT8,4,2     ## @IO_BASE_IO_DECODE_BIT8
	.comm	_PCI_PREF_MEMORY_BASE,8,3       ## @PCI_PREF_MEMORY_BASE
	.comm	_CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE,4,2 ## @CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE
	.comm	_CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE,4,2 ## @CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE
	.comm	_PCI_BASE_ADDRESS_0,8,3         ## @PCI_BASE_ADDRESS_0
	.comm	_PORT_LOGIC_ACK_F_ASPM_CTRL,8,3 ## @PORT_LOGIC_ACK_F_ASPM_CTRL
	.comm	_N_FTS_MASK,4,2                 ## @N_FTS_MASK
	.comm	_N_FTS_SHIFT,4,2                ## @N_FTS_SHIFT
	.comm	_N_FTS_VAL,4,2                  ## @N_FTS_VAL
	.comm	_PORT_LOGIC_GEN2_CTRL,8,3       ## @PORT_LOGIC_GEN2_CTRL
	.comm	_FTS_MASK,4,2                   ## @FTS_MASK
	.comm	_FTS_VAL,4,2                    ## @FTS_VAL
	.comm	_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT,8,3 ## @PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT
	.comm	_AMBA_ERROR_RESPONSE_CRS_MASK,4,2 ## @AMBA_ERROR_RESPONSE_CRS_MASK
	.comm	_AMBA_ERROR_RESPONSE_CRS_SHIFT,4,2 ## @AMBA_ERROR_RESPONSE_CRS_SHIFT
	.comm	_AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001,4,2 ## @AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PCI_EXP_LNKCAP,8,3             ## @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_SLS,4,2         ## @PCI_EXP_LNKCAP_SLS
	.comm	_PCI_EXP_LNKCAP_MLW,4,2         ## @PCI_EXP_LNKCAP_MLW
	.comm	_PCI_EXP_LNKSTA_NLW_SHIFT,4,2   ## @PCI_EXP_LNKSTA_NLW_SHIFT
	.comm	_GEN3_RELATED_OFF,8,3           ## @GEN3_RELATED_OFF
	.comm	_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,4,2 ## @GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL
	.comm	_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF,8,3 ## @CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF
	.comm	_CFG_TIMER_CTRL_ACK_NAK_SHIFT,4,2 ## @CFG_TIMER_CTRL_ACK_NAK_SHIFT
	.comm	_GEN4_CORE_CLK_FREQ,4,2         ## @GEN4_CORE_CLK_FREQ
	.comm	_APPL_PINMUX,4,2                ## @APPL_PINMUX
	.comm	_APPL_PINMUX_PEX_RST,4,2        ## @APPL_PINMUX_PEX_RST
	.comm	_APPL_CTRL,4,2                  ## @APPL_CTRL
	.comm	_APPL_CTRL_LTSSM_EN,4,2         ## @APPL_CTRL_LTSSM_EN
	.no_dead_strip	_tegra_pcie_prepare_host
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_prepare_host
_tegra_pcie_prepare_host:               ; @tegra_pcie_prepare_host
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x20, x0
	bl	_to_dw_pcie_from_pp
	mov	x21, x0
	bl	_to_tegra_pcie
	mov	x19, x0
Lloh0:
	adrp	x22, _PCI_IO_BASE@GOTPAGE
Lloh1:
	ldr	x22, [x22, _PCI_IO_BASE@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh2:
	adrp	x8, _IO_BASE_IO_DECODE@GOTPAGE
Lloh3:
	ldr	x8, [x8, _IO_BASE_IO_DECODE@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
Lloh5:
	adrp	x9, _IO_BASE_IO_DECODE_BIT8@GOTPAGE
Lloh6:
	ldr	x9, [x9, _IO_BASE_IO_DECODE_BIT8@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w8, w9, w8
	bic	w2, w0, w8
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
Lloh8:
	adrp	x22, _PCI_PREF_MEMORY_BASE@GOTPAGE
Lloh9:
	ldr	x22, [x22, _PCI_PREF_MEMORY_BASE@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh10:
	adrp	x8, _CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh13:
	adrp	x9, _CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE@GOTPAGE
Lloh14:
	ldr	x9, [x9, _CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
Lloh16:
	adrp	x8, _PCI_BASE_ADDRESS_0@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PCI_BASE_ADDRESS_0@GOTPAGEOFF]
Lloh18:
	ldr	x1, [x8]
	mov	x0, x21
	mov	w2, #0
	bl	_dw_pcie_writel_dbi
Lloh19:
	adrp	x22, _PORT_LOGIC_ACK_F_ASPM_CTRL@GOTPAGE
Lloh20:
	ldr	x22, [x22, _PORT_LOGIC_ACK_F_ASPM_CTRL@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh21:
	adrp	x8, _N_FTS_MASK@GOTPAGE
Lloh22:
	ldr	x8, [x8, _N_FTS_MASK@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _N_FTS_SHIFT@GOTPAGE
Lloh25:
	ldr	x9, [x9, _N_FTS_SHIFT@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
Lloh27:
	adrp	x10, _N_FTS_VAL@GOTPAGE
Lloh28:
	ldr	x10, [x10, _N_FTS_VAL@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	lsl	w9, w10, w9
	orr	w2, w8, w9
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
Lloh30:
	adrp	x22, _PORT_LOGIC_GEN2_CTRL@GOTPAGE
Lloh31:
	ldr	x22, [x22, _PORT_LOGIC_GEN2_CTRL@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh32:
	adrp	x8, _FTS_MASK@GOTPAGE
Lloh33:
	ldr	x8, [x8, _FTS_MASK@GOTPAGEOFF]
Lloh34:
	ldr	w8, [x8]
	bic	w8, w0, w8
Lloh35:
	adrp	x9, _FTS_VAL@GOTPAGE
Lloh36:
	ldr	x9, [x9, _FTS_VAL@GOTPAGEOFF]
Lloh37:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
Lloh38:
	adrp	x22, _PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT@GOTPAGE
Lloh39:
	ldr	x22, [x22, _PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh40:
	adrp	x8, _AMBA_ERROR_RESPONSE_CRS_MASK@GOTPAGE
Lloh41:
	ldr	x8, [x8, _AMBA_ERROR_RESPONSE_CRS_MASK@GOTPAGEOFF]
Lloh42:
	ldr	w8, [x8]
Lloh43:
	adrp	x9, _AMBA_ERROR_RESPONSE_CRS_SHIFT@GOTPAGE
Lloh44:
	ldr	x9, [x9, _AMBA_ERROR_RESPONSE_CRS_SHIFT@GOTPAGEOFF]
Lloh45:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	bic	w8, w0, w8
Lloh46:
	adrp	x10, _AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001@GOTPAGE
Lloh47:
	ldr	x10, [x10, _AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	lsl	w9, w10, w9
	orr	w2, w8, w9
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
	ldr	w8, [x19]
Lloh49:
	adrp	x22, _PCI_EXP_LNKCAP@GOTPAGE
Lloh50:
	ldr	x22, [x22, _PCI_EXP_LNKCAP@GOTPAGEOFF]
	cbz	w8, LBB0_3
; %bb.1:
Lloh51:
	adrp	x9, _EINVAL@GOTPAGE
Lloh52:
	ldr	x9, [x9, _EINVAL@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	cmn	w8, w9
	b.eq	LBB0_3
; %bb.2:
	ldr	x8, [x19, #24]
	ldr	x9, [x22]
	add	x1, x9, x8
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh54:
	adrp	x8, _PCI_EXP_LNKCAP_SLS@GOTPAGE
Lloh55:
	ldr	x8, [x8, _PCI_EXP_LNKCAP_SLS@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19]
	orr	w2, w8, w9
	ldr	x8, [x19, #24]
	ldr	x9, [x22]
	add	x1, x9, x8
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
LBB0_3:
	ldr	x8, [x19, #24]
	ldr	x9, [x22]
	add	x1, x9, x8
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh57:
	adrp	x8, _PCI_EXP_LNKCAP_MLW@GOTPAGE
Lloh58:
	ldr	x8, [x8, _PCI_EXP_LNKCAP_MLW@GOTPAGEOFF]
Lloh59:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x19, #4]
Lloh60:
	adrp	x10, _PCI_EXP_LNKSTA_NLW_SHIFT@GOTPAGE
Lloh61:
	ldr	x10, [x10, _PCI_EXP_LNKSTA_NLW_SHIFT@GOTPAGEOFF]
Lloh62:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w2, w9, w8
	ldr	x8, [x19, #24]
	ldr	x9, [x22]
	add	x1, x9, x8
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
	mov	x0, x19
	bl	_config_gen3_gen4_eq_presets
	mov	x0, x19
	bl	_init_host_aspm
Lloh63:
	adrp	x22, _GEN3_RELATED_OFF@GOTPAGE
Lloh64:
	ldr	x22, [x22, _GEN3_RELATED_OFF@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh65:
	adrp	x8, _GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL@GOTPAGE
Lloh66:
	ldr	x8, [x8, _GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL@GOTPAGEOFF]
Lloh67:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
	ldr	x8, [x19, #16]
	cbz	x8, LBB0_5
; %bb.4:
Lloh68:
	adrp	x22, _CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF@GOTPAGE
Lloh69:
	ldr	x22, [x22, _CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF@GOTPAGEOFF]
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_readl_dbi
Lloh70:
	adrp	x8, _CFG_TIMER_CTRL_ACK_NAK_SHIFT@GOTPAGE
Lloh71:
	ldr	x8, [x8, _CFG_TIMER_CTRL_ACK_NAK_SHIFT@GOTPAGEOFF]
Lloh72:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w8, w9, w8
	orr	w2, w8, w0
	ldr	x1, [x22]
	mov	x0, x21
	bl	_dw_pcie_writel_dbi
LBB0_5:
	mov	x0, x20
	bl	_dw_pcie_setup_rc
	ldr	w0, [x19, #8]
Lloh73:
	adrp	x8, _GEN4_CORE_CLK_FREQ@GOTPAGE
Lloh74:
	ldr	x8, [x8, _GEN4_CORE_CLK_FREQ@GOTPAGEOFF]
Lloh75:
	ldr	w1, [x8]
	bl	_clk_set_rate
Lloh76:
	adrp	x20, _APPL_PINMUX@GOTPAGE
Lloh77:
	ldr	x20, [x20, _APPL_PINMUX@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_appl_readl
Lloh78:
	adrp	x21, _APPL_PINMUX_PEX_RST@GOTPAGE
Lloh79:
	ldr	x21, [x21, _APPL_PINMUX_PEX_RST@GOTPAGEOFF]
	ldr	w8, [x21]
	bic	w1, w0, w8
	ldr	w2, [x20]
	mov	x0, x19
	bl	_appl_writel
	mov	w0, #100
	mov	w1, #200
	bl	_usleep_range
Lloh80:
	adrp	x22, _APPL_CTRL@GOTPAGE
Lloh81:
	ldr	x22, [x22, _APPL_CTRL@GOTPAGEOFF]
	ldr	w1, [x22]
	mov	x0, x19
	bl	_appl_readl
Lloh82:
	adrp	x8, _APPL_CTRL_LTSSM_EN@GOTPAGE
Lloh83:
	ldr	x8, [x8, _APPL_CTRL_LTSSM_EN@GOTPAGEOFF]
Lloh84:
	ldr	w8, [x8]
	orr	w1, w8, w0
	ldr	w2, [x22]
	mov	x0, x19
	bl	_appl_writel
	ldr	w1, [x20]
	mov	x0, x19
	bl	_appl_readl
	ldr	w8, [x21]
	orr	w1, w8, w0
	ldr	w2, [x20]
	mov	x0, x19
	bl	_appl_writel
	mov	w0, #100
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_msleep
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh32, Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGot	Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGot	Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_IO_BASE,8,3                ; @PCI_IO_BASE
	.comm	_IO_BASE_IO_DECODE,4,2          ; @IO_BASE_IO_DECODE
	.comm	_IO_BASE_IO_DECODE_BIT8,4,2     ; @IO_BASE_IO_DECODE_BIT8
	.comm	_PCI_PREF_MEMORY_BASE,8,3       ; @PCI_PREF_MEMORY_BASE
	.comm	_CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE,4,2 ; @CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE
	.comm	_CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE,4,2 ; @CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE
	.comm	_PCI_BASE_ADDRESS_0,8,3         ; @PCI_BASE_ADDRESS_0
	.comm	_PORT_LOGIC_ACK_F_ASPM_CTRL,8,3 ; @PORT_LOGIC_ACK_F_ASPM_CTRL
	.comm	_N_FTS_MASK,4,2                 ; @N_FTS_MASK
	.comm	_N_FTS_SHIFT,4,2                ; @N_FTS_SHIFT
	.comm	_N_FTS_VAL,4,2                  ; @N_FTS_VAL
	.comm	_PORT_LOGIC_GEN2_CTRL,8,3       ; @PORT_LOGIC_GEN2_CTRL
	.comm	_FTS_MASK,4,2                   ; @FTS_MASK
	.comm	_FTS_VAL,4,2                    ; @FTS_VAL
	.comm	_PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT,8,3 ; @PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT
	.comm	_AMBA_ERROR_RESPONSE_CRS_MASK,4,2 ; @AMBA_ERROR_RESPONSE_CRS_MASK
	.comm	_AMBA_ERROR_RESPONSE_CRS_SHIFT,4,2 ; @AMBA_ERROR_RESPONSE_CRS_SHIFT
	.comm	_AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001,4,2 ; @AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PCI_EXP_LNKCAP,8,3             ; @PCI_EXP_LNKCAP
	.comm	_PCI_EXP_LNKCAP_SLS,4,2         ; @PCI_EXP_LNKCAP_SLS
	.comm	_PCI_EXP_LNKCAP_MLW,4,2         ; @PCI_EXP_LNKCAP_MLW
	.comm	_PCI_EXP_LNKSTA_NLW_SHIFT,4,2   ; @PCI_EXP_LNKSTA_NLW_SHIFT
	.comm	_GEN3_RELATED_OFF,8,3           ; @GEN3_RELATED_OFF
	.comm	_GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,4,2 ; @GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL
	.comm	_CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF,8,3 ; @CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF
	.comm	_CFG_TIMER_CTRL_ACK_NAK_SHIFT,4,2 ; @CFG_TIMER_CTRL_ACK_NAK_SHIFT
	.comm	_GEN4_CORE_CLK_FREQ,4,2         ; @GEN4_CORE_CLK_FREQ
	.comm	_APPL_PINMUX,4,2                ; @APPL_PINMUX
	.comm	_APPL_PINMUX_PEX_RST,4,2        ; @APPL_PINMUX_PEX_RST
	.comm	_APPL_CTRL,4,2                  ; @APPL_CTRL
	.comm	_APPL_CTRL_LTSSM_EN,4,2         ; @APPL_CTRL_LTSSM_EN
	.no_dead_strip	_tegra_pcie_prepare_host
.subsections_via_symbols
