	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rockchip_pcie_ep_clear_bar
_rockchip_pcie_ep_clear_bar:            ## @rockchip_pcie_ep_clear_bar
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movl	%esi, %ebx
	callq	_epc_get_drvdata
	movq	%rax, %r15
	movl	(%r14), %r13d
	movq	_BAR_4@GOTPCREL(%rip), %r14
	cmpl	(%r14), %r13d
	movl	%ebx, -52(%rbp)                 ## 4-byte Spill
	movl	%ebx, %edi
	jae	LBB0_2
## %bb.1:
	callq	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0
	movl	%eax, %esi
	movl	%r13d, %ebx
	jmp	LBB0_3
LBB0_2:
	callq	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1
	movl	%eax, %esi
	movl	%r13d, %ebx
	subl	(%r14), %ebx
LBB0_3:
	movl	%esi, -48(%rbp)                 ## 4-byte Spill
	movq	_ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movq	%r15, %rdi
	callq	_rockchip_pcie_read
	movl	%eax, %r14d
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK
	movl	%eax, %r12d
	movl	%ebx, %edi
	callq	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK
	orl	%eax, %r12d
	notl	%r12d
	andl	%r14d, %r12d
	movl	%ebx, %edi
	movl	-44(%rbp), %esi                 ## 4-byte Reload
	callq	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL
	orl	%eax, %r12d
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	callq	_rockchip_pcie_write
	movl	-52(%rbp), %ebx                 ## 4-byte Reload
	movl	%ebx, %edi
	movl	%r13d, %esi
	callq	_ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_rockchip_pcie_write
	movl	%ebx, %edi
	movl	%r13d, %esi
	callq	_ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1
	movq	%r15, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rockchip_pcie_write            ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_BAR_4,4,2                      ## @BAR_4
	.comm	_ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED,4,2 ## @ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED
	.no_dead_strip	_rockchip_pcie_ep_clear_bar
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rockchip_pcie_ep_clear_bar
_rockchip_pcie_ep_clear_bar:            ; @rockchip_pcie_ep_clear_bar
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x21, x2
	mov	x19, x1
	bl	_epc_get_drvdata
	mov	x20, x0
	ldr	w21, [x21]
Lloh0:
	adrp	x23, _BAR_4@GOTPAGE
Lloh1:
	ldr	x23, [x23, _BAR_4@GOTPAGEOFF]
	ldr	w8, [x23]
	mov	x0, x19
	cmp	w21, w8
	b.hs	LBB0_2
; %bb.1:
	bl	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0
	mov	x22, x0
	mov	x23, x21
	b	LBB0_3
LBB0_2:
	bl	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1
	mov	x22, x0
	ldr	w8, [x23]
	sub	w23, w21, w8
LBB0_3:
Lloh2:
	adrp	x8, _ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED@GOTPAGE
Lloh3:
	ldr	x8, [x8, _ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED@GOTPAGEOFF]
Lloh4:
	ldr	w24, [x8]
	mov	x0, x20
	mov	x1, x22
	bl	_rockchip_pcie_read
	mov	x25, x0
	mov	x0, x23
	bl	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK
	mov	x26, x0
	mov	x0, x23
	bl	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK
	orr	w8, w0, w26
	bic	w25, w25, w8
	mov	x0, x23
	mov	x1, x24
	bl	_ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL
	orr	w1, w25, w0
	mov	x0, x20
	mov	x2, x22
	bl	_rockchip_pcie_write
	mov	x0, x19
	mov	x1, x21
	bl	_ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0
	mov	x2, x0
	mov	x0, x20
	mov	w1, #0
	bl	_rockchip_pcie_write
	mov	x0, x19
	mov	x1, x21
	bl	_ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1
	mov	x2, x0
	mov	x0, x20
	mov	w1, #0
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_rockchip_pcie_write
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.cfi_endproc
                                        ; -- End function
	.comm	_BAR_4,4,2                      ; @BAR_4
	.comm	_ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED,4,2 ; @ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED
	.no_dead_strip	_rockchip_pcie_ep_clear_bar
.subsections_via_symbols
