	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function imx6_setup_phy_mpll
_imx6_setup_phy_mpll:                   ## @imx6_setup_phy_mpll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	16(%rdi), %edi
	callq	_clk_get_rate
	movq	8(%rbx), %rcx
	movq	_IMX6_PCIE_FLAG_IMX6_PHY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	testl	%edx, (%rcx)
	je	LBB0_1
## %bb.2:
	xorl	%r14d, %r14d
	movl	$0, %r15d
	cmpq	$100000000, %rax                ## imm = 0x5F5E100
	je	LBB0_6
## %bb.3:
	cmpq	$125000000, %rax                ## imm = 0x7735940
	je	LBB0_7
## %bb.4:
	cmpq	$200000000, %rax                ## imm = 0xBEBC200
	jne	LBB0_8
## %bb.5:
	movl	$1, %r15d
LBB0_6:
	movq	_PCIE_PHY_MPLL_OVRD_IN_LO@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	leaq	-44(%rbp), %r12
	movq	%rbx, %rdi
	movq	%r12, %rdx
	callq	_pcie_phy_read
	movq	_PCIE_PHY_MPLL_MULTIPLIER_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_PCIE_PHY_MPLL_MULTIPLIER_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	notl	%eax
	movl	$25, %edx
	shll	%cl, %edx
	andl	-44(%rbp), %eax
	orl	%eax, %edx
	movq	_PCIE_PHY_MPLL_MULTIPLIER_OVRD@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movl	%edx, -44(%rbp)
	movl	(%r13), %esi
	movq	%rbx, %rdi
	callq	_pcie_phy_write
	movq	_PCIE_PHY_ATEOVRD@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%rbx, %rdi
	movq	%r12, %rdx
	callq	_pcie_phy_read
	movq	_PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	_PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %eax
	notl	%eax
	shll	%cl, %r15d
	andl	-44(%rbp), %eax
	orl	%eax, %r15d
	movq	_PCIE_PHY_ATEOVRD_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r15d
	movl	%r15d, -44(%rbp)
	movl	(%r13), %esi
	movq	%rbx, %rdi
	movl	%r15d, %edx
	callq	_pcie_phy_write
	jmp	LBB0_7
LBB0_1:
	xorl	%r14d, %r14d
	jmp	LBB0_7
LBB0_8:
	movq	(%rbx), %rcx
	movl	(%rcx), %edi
	leaq	L_.str(%rip), %rsi
	movq	%rax, %rdx
	callq	_dev_err
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
	subl	(%rax), %r14d
LBB0_7:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_IMX6_PCIE_FLAG_IMX6_PHY,4,2    ## @IMX6_PCIE_FLAG_IMX6_PHY
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Unsupported PHY reference clock rate %lu\n"

	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PCIE_PHY_MPLL_OVRD_IN_LO,4,2   ## @PCIE_PHY_MPLL_OVRD_IN_LO
	.comm	_PCIE_PHY_MPLL_MULTIPLIER_MASK,4,2 ## @PCIE_PHY_MPLL_MULTIPLIER_MASK
	.comm	_PCIE_PHY_MPLL_MULTIPLIER_SHIFT,4,2 ## @PCIE_PHY_MPLL_MULTIPLIER_SHIFT
	.comm	_PCIE_PHY_MPLL_MULTIPLIER_OVRD,4,2 ## @PCIE_PHY_MPLL_MULTIPLIER_OVRD
	.comm	_PCIE_PHY_ATEOVRD,4,2           ## @PCIE_PHY_ATEOVRD
	.comm	_PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK,4,2 ## @PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK
	.comm	_PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT,4,2 ## @PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT
	.comm	_PCIE_PHY_ATEOVRD_EN,4,2        ## @PCIE_PHY_ATEOVRD_EN
	.no_dead_strip	_imx6_setup_phy_mpll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function imx6_setup_phy_mpll
_imx6_setup_phy_mpll:                   ; @imx6_setup_phy_mpll
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0, #16]
	bl	_clk_get_rate
	ldr	x8, [x19, #8]
	ldr	w8, [x8]
Lloh0:
	adrp	x9, _IMX6_PCIE_FLAG_IMX6_PHY@GOTPAGE
Lloh1:
	ldr	x9, [x9, _IMX6_PCIE_FLAG_IMX6_PHY@GOTPAGEOFF]
Lloh2:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_6
; %bb.1:
	mov	x2, x0
	mov	w20, #0
	mov	w8, #57600
	movk	w8, #1525, lsl #16
	cmp	x0, x8
	b.eq	LBB0_5
; %bb.2:
	mov	w8, #22848
	movk	w8, #1907, lsl #16
	cmp	x2, x8
	b.eq	LBB0_7
; %bb.3:
	mov	w8, #49664
	movk	w8, #3051, lsl #16
	cmp	x2, x8
	b.ne	LBB0_8
; %bb.4:
	mov	w20, #1
LBB0_5:
Lloh3:
	adrp	x21, _PCIE_PHY_MPLL_OVRD_IN_LO@GOTPAGE
Lloh4:
	ldr	x21, [x21, _PCIE_PHY_MPLL_OVRD_IN_LO@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_pcie_phy_read
Lloh5:
	adrp	x8, _PCIE_PHY_MPLL_MULTIPLIER_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCIE_PHY_MPLL_MULTIPLIER_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
Lloh8:
	adrp	x9, _PCIE_PHY_MPLL_MULTIPLIER_SHIFT@GOTPAGE
Lloh9:
	ldr	x9, [x9, _PCIE_PHY_MPLL_MULTIPLIER_SHIFT@GOTPAGEOFF]
Lloh10:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	ldr	w10, [sp, #12]
	bic	w8, w10, w8
	mov	w10, #25
	lsl	w9, w10, w9
	orr	w8, w8, w9
Lloh11:
	adrp	x9, _PCIE_PHY_MPLL_MULTIPLIER_OVRD@GOTPAGE
Lloh12:
	ldr	x9, [x9, _PCIE_PHY_MPLL_MULTIPLIER_OVRD@GOTPAGEOFF]
Lloh13:
	ldr	w9, [x9]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_pcie_phy_write
Lloh14:
	adrp	x21, _PCIE_PHY_ATEOVRD@GOTPAGE
Lloh15:
	ldr	x21, [x21, _PCIE_PHY_ATEOVRD@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #12
	mov	x0, x19
	bl	_pcie_phy_read
Lloh16:
	adrp	x8, _PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
Lloh19:
	adrp	x9, _PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	lsl	w8, w8, w9
	ldr	w10, [sp, #12]
	bic	w8, w10, w8
	lsl	w9, w20, w9
	orr	w8, w8, w9
Lloh22:
	adrp	x9, _PCIE_PHY_ATEOVRD_EN@GOTPAGE
Lloh23:
	ldr	x9, [x9, _PCIE_PHY_ATEOVRD_EN@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w2, w8, w9
	str	w2, [sp, #12]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_pcie_phy_write
LBB0_6:
	mov	w20, #0
LBB0_7:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_8:
	ldr	x8, [x19]
	ldr	w0, [x8]
Lloh25:
	adrp	x1, l_.str@PAGE
Lloh26:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh27:
	adrp	x8, _EINVAL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_7
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpAdd	Lloh25, Lloh26
	.cfi_endproc
                                        ; -- End function
	.comm	_IMX6_PCIE_FLAG_IMX6_PHY,4,2    ; @IMX6_PCIE_FLAG_IMX6_PHY
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Unsupported PHY reference clock rate %lu\n"

	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PCIE_PHY_MPLL_OVRD_IN_LO,4,2   ; @PCIE_PHY_MPLL_OVRD_IN_LO
	.comm	_PCIE_PHY_MPLL_MULTIPLIER_MASK,4,2 ; @PCIE_PHY_MPLL_MULTIPLIER_MASK
	.comm	_PCIE_PHY_MPLL_MULTIPLIER_SHIFT,4,2 ; @PCIE_PHY_MPLL_MULTIPLIER_SHIFT
	.comm	_PCIE_PHY_MPLL_MULTIPLIER_OVRD,4,2 ; @PCIE_PHY_MPLL_MULTIPLIER_OVRD
	.comm	_PCIE_PHY_ATEOVRD,4,2           ; @PCIE_PHY_ATEOVRD
	.comm	_PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK,4,2 ; @PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK
	.comm	_PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT,4,2 ; @PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT
	.comm	_PCIE_PHY_ATEOVRD_EN,4,2        ; @PCIE_PHY_ATEOVRD_EN
	.no_dead_strip	_imx6_setup_phy_mpll
.subsections_via_symbols
