	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function cpsw_rx_vlan_encap
_cpsw_rx_vlan_encap:                    ## @cpsw_rx_vlan_encap
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movl	8(%rdi), %edi
	callq	_netdev_priv
	movq	%rax, %r15
	movq	8(%rax), %r13
	movq	(%r14), %rax
	movl	(%rax), %r12d
	movq	_CPSW_RX_VLAN_ENCAP_HDR_SIZE@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	%r14, %rdi
	callq	_skb_pull
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r12d, %ebx
	sarl	%cl, %ebx
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	je	LBB0_6
## %bb.1:
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	je	LBB0_6
## %bb.2:
	movq	_CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%r12d, %eax
	sarl	%cl, %eax
	movq	_VLAN_VID_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	je	LBB0_6
## %bb.3:
	cmpq	$0, 8(%r13)
	je	LBB0_5
## %bb.4:
	movq	(%r13), %rcx
	movq	(%r15), %rdx
	cmpl	(%rcx,%rdx,4), %eax
	je	LBB0_6
LBB0_5:
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %r12d
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %r12d
	movq	_VLAN_PRIO_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	shll	%cl, %r12d
	orl	%eax, %r12d
	movq	_ETH_P_8021Q@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_htons
	movq	%r14, %rdi
	movl	%eax, %esi
	movl	%r12d, %edx
	callq	___vlan_hwaccel_put_tag
	movq	_CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jne	LBB0_6
## %bb.7:
	movq	(%r14), %rsi
	movq	_VLAN_HLEN@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	addq	%rsi, %rdi
	movq	_ETH_ALEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	addl	%edx, %edx
	callq	_memmove
	movq	(%rbx), %rsi
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_skb_pull                       ## TAILCALL
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_SIZE,8,3 ## @CPSW_RX_VLAN_ENCAP_HDR_SIZE
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT
	.comm	_VLAN_VID_MASK,4,2              ## @VLAN_VID_MASK
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK
	.comm	_VLAN_PRIO_SHIFT,4,2            ## @VLAN_PRIO_SHIFT
	.comm	_ETH_P_8021Q,4,2                ## @ETH_P_8021Q
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG,4,2 ## @CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG
	.comm	_VLAN_HLEN,8,3                  ## @VLAN_HLEN
	.comm	_ETH_ALEN,4,2                   ## @ETH_ALEN
	.no_dead_strip	_cpsw_rx_vlan_encap
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function cpsw_rx_vlan_encap
_cpsw_rx_vlan_encap:                    ; @cpsw_rx_vlan_encap
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	ldr	w0, [x0, #8]
	bl	_netdev_priv
	mov	x20, x0
	ldr	x23, [x0, #8]
	ldr	x8, [x19]
	ldr	w22, [x8]
Lloh0:
	adrp	x8, _CPSW_RX_VLAN_ENCAP_HDR_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CPSW_RX_VLAN_ENCAP_HDR_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	x1, [x8]
	mov	x0, x19
	bl	_skb_pull
Lloh3:
	adrp	x8, _CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	asr	w8, w22, w8
Lloh6:
	adrp	x9, _CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK@GOTPAGE
Lloh7:
	ldr	x9, [x9, _CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	and	w21, w8, w9
Lloh9:
	adrp	x8, _CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV@GOTPAGEOFF]
Lloh11:
	ldr	w8, [x8]
Lloh12:
	adrp	x9, _CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG@GOTPAGE
Lloh13:
	ldr	x9, [x9, _CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG@GOTPAGEOFF]
Lloh14:
	ldr	w9, [x9]
	cmp	w21, w8
	ccmp	w21, w9, #4, ne
	b.eq	LBB0_6
; %bb.1:
Lloh15:
	adrp	x8, _CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT@GOTPAGE
Lloh16:
	ldr	x8, [x8, _CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	w8, [x8]
	asr	w8, w22, w8
Lloh18:
	adrp	x9, _VLAN_VID_MASK@GOTPAGE
Lloh19:
	ldr	x9, [x9, _VLAN_VID_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	ands	w8, w8, w9
	b.eq	LBB0_6
; %bb.2:
	ldr	x9, [x23, #8]
	cbz	x9, LBB0_4
; %bb.3:
	ldr	x9, [x23]
	ldr	x10, [x20]
	ldr	w9, [x9, x10, lsl #2]
	cmp	w8, w9
	b.eq	LBB0_6
LBB0_4:
Lloh21:
	adrp	x9, _CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT@GOTPAGE
Lloh22:
	ldr	x9, [x9, _CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w9, [x9]
	asr	w9, w22, w9
Lloh24:
	adrp	x10, _CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK@GOTPAGE
Lloh25:
	ldr	x10, [x10, _CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK@GOTPAGEOFF]
Lloh26:
	ldr	w10, [x10]
	and	w9, w9, w10
Lloh27:
	adrp	x10, _VLAN_PRIO_SHIFT@GOTPAGE
Lloh28:
	ldr	x10, [x10, _VLAN_PRIO_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w20, w9, w8
Lloh30:
	adrp	x8, _ETH_P_8021Q@GOTPAGE
Lloh31:
	ldr	x8, [x8, _ETH_P_8021Q@GOTPAGEOFF]
Lloh32:
	ldr	w0, [x8]
	bl	_htons
	mov	x1, x0
	mov	x0, x19
	mov	x2, x20
	bl	___vlan_hwaccel_put_tag
Lloh33:
	adrp	x8, _CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	cmp	w21, w8
	b.ne	LBB0_6
; %bb.5:
	ldr	x1, [x19]
Lloh36:
	adrp	x20, _VLAN_HLEN@GOTPAGE
Lloh37:
	ldr	x20, [x20, _VLAN_HLEN@GOTPAGEOFF]
	ldr	x8, [x20]
	add	x0, x8, x1
Lloh38:
	adrp	x8, _ETH_ALEN@GOTPAGE
Lloh39:
	ldr	x8, [x8, _ETH_ALEN@GOTPAGEOFF]
Lloh40:
	ldr	w8, [x8]
	lsl	w2, w8, #1
	bl	_memmove
	ldr	x1, [x20]
	mov	x0, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_skb_pull
LBB0_6:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.cfi_endproc
                                        ; -- End function
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_SIZE,8,3 ; @CPSW_RX_VLAN_ENCAP_HDR_SIZE
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT
	.comm	_VLAN_VID_MASK,4,2              ; @VLAN_VID_MASK
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK
	.comm	_VLAN_PRIO_SHIFT,4,2            ; @VLAN_PRIO_SHIFT
	.comm	_ETH_P_8021Q,4,2                ; @ETH_P_8021Q
	.comm	_CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG,4,2 ; @CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG
	.comm	_VLAN_HLEN,8,3                  ; @VLAN_HLEN
	.comm	_ETH_ALEN,4,2                   ; @ETH_ALEN
	.no_dead_strip	_cpsw_rx_vlan_encap
.subsections_via_symbols
