	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rt61pci_mcu_request
_rt61pci_mcu_request:                   ## @rt61pci_mcu_request
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, %r12d
	movl	%ecx, %r13d
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %rbx
	callq	_mutex_lock
	leaq	-44(%rbp), %rsi
	movq	%rbx, %rdi
	callq	_WAIT_FOR_MCU
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movq	_H2M_MAILBOX_CSR_OWNER@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%r15d, -48(%rbp)                ## 4-byte Spill
	leaq	-44(%rbp), %r15
	movq	%r15, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movq	_H2M_MAILBOX_CSR_CMD_TOKEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r14d, %edx
	callq	_rt2x00_set_field32
	movq	_H2M_MAILBOX_CSR_ARG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r13d, %edx
	callq	_rt2x00_set_field32
	movq	_H2M_MAILBOX_CSR_ARG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%r12d, %edx
	callq	_rt2x00_set_field32
	movq	_H2M_MAILBOX_CSR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-44(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
	movq	_HOST_CMD_CSR@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_read
	movl	%eax, -44(%rbp)
	movq	_HOST_CMD_CSR_HOST_COMMAND@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	-48(%rbp), %edx                 ## 4-byte Reload
	callq	_rt2x00_set_field32
	movq	_HOST_CMD_CSR_INTERRUPT_MCU@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$1, %edx
	callq	_rt2x00_set_field32
	movl	(%r14), %esi
	movl	-44(%rbp), %edx
	movq	%rbx, %rdi
	callq	_rt2x00mmio_register_write
LBB0_2:
	movq	%rbx, %rdi
	callq	_mutex_unlock
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_H2M_MAILBOX_CSR_OWNER,4,2      ## @H2M_MAILBOX_CSR_OWNER
	.comm	_H2M_MAILBOX_CSR_CMD_TOKEN,4,2  ## @H2M_MAILBOX_CSR_CMD_TOKEN
	.comm	_H2M_MAILBOX_CSR_ARG0,4,2       ## @H2M_MAILBOX_CSR_ARG0
	.comm	_H2M_MAILBOX_CSR_ARG1,4,2       ## @H2M_MAILBOX_CSR_ARG1
	.comm	_H2M_MAILBOX_CSR,4,2            ## @H2M_MAILBOX_CSR
	.comm	_HOST_CMD_CSR,4,2               ## @HOST_CMD_CSR
	.comm	_HOST_CMD_CSR_HOST_COMMAND,4,2  ## @HOST_CMD_CSR_HOST_COMMAND
	.comm	_HOST_CMD_CSR_INTERRUPT_MCU,4,2 ## @HOST_CMD_CSR_INTERRUPT_MCU
	.no_dead_strip	_rt61pci_mcu_request
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rt61pci_mcu_request
_rt61pci_mcu_request:                   ; @rt61pci_mcu_request
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x4
	mov	x22, x3
	mov	x23, x2
	mov	x20, x1
	mov	x19, x0
	bl	_mutex_lock
	add	x1, sp, #12
	mov	x0, x19
	bl	_WAIT_FOR_MCU
	cbz	x0, LBB0_2
; %bb.1:
Lloh0:
	adrp	x8, _H2M_MAILBOX_CSR_OWNER@GOTPAGE
Lloh1:
	ldr	x8, [x8, _H2M_MAILBOX_CSR_OWNER@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
Lloh3:
	adrp	x8, _H2M_MAILBOX_CSR_CMD_TOKEN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _H2M_MAILBOX_CSR_CMD_TOKEN@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	x2, x23
	bl	_rt2x00_set_field32
Lloh6:
	adrp	x8, _H2M_MAILBOX_CSR_ARG0@GOTPAGE
Lloh7:
	ldr	x8, [x8, _H2M_MAILBOX_CSR_ARG0@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	x2, x22
	bl	_rt2x00_set_field32
Lloh9:
	adrp	x8, _H2M_MAILBOX_CSR_ARG1@GOTPAGE
Lloh10:
	ldr	x8, [x8, _H2M_MAILBOX_CSR_ARG1@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	x2, x21
	bl	_rt2x00_set_field32
Lloh12:
	adrp	x8, _H2M_MAILBOX_CSR@GOTPAGE
Lloh13:
	ldr	x8, [x8, _H2M_MAILBOX_CSR@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
Lloh15:
	adrp	x21, _HOST_CMD_CSR@GOTPAGE
Lloh16:
	ldr	x21, [x21, _HOST_CMD_CSR@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_rt2x00mmio_register_read
	str	w0, [sp, #12]
Lloh17:
	adrp	x8, _HOST_CMD_CSR_HOST_COMMAND@GOTPAGE
Lloh18:
	ldr	x8, [x8, _HOST_CMD_CSR_HOST_COMMAND@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	x2, x20
	bl	_rt2x00_set_field32
Lloh20:
	adrp	x8, _HOST_CMD_CSR_INTERRUPT_MCU@GOTPAGE
Lloh21:
	ldr	x8, [x8, _HOST_CMD_CSR_INTERRUPT_MCU@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	add	x0, sp, #12
	mov	w2, #1
	bl	_rt2x00_set_field32
	ldr	w1, [x21]
	ldr	w2, [sp, #12]
	mov	x0, x19
	bl	_rt2x00mmio_register_write
LBB0_2:
	mov	x0, x19
	bl	_mutex_unlock
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_H2M_MAILBOX_CSR_OWNER,4,2      ; @H2M_MAILBOX_CSR_OWNER
	.comm	_H2M_MAILBOX_CSR_CMD_TOKEN,4,2  ; @H2M_MAILBOX_CSR_CMD_TOKEN
	.comm	_H2M_MAILBOX_CSR_ARG0,4,2       ; @H2M_MAILBOX_CSR_ARG0
	.comm	_H2M_MAILBOX_CSR_ARG1,4,2       ; @H2M_MAILBOX_CSR_ARG1
	.comm	_H2M_MAILBOX_CSR,4,2            ; @H2M_MAILBOX_CSR
	.comm	_HOST_CMD_CSR,4,2               ; @HOST_CMD_CSR
	.comm	_HOST_CMD_CSR_HOST_COMMAND,4,2  ; @HOST_CMD_CSR_HOST_COMMAND
	.comm	_HOST_CMD_CSR_INTERRUPT_MCU,4,2 ; @HOST_CMD_CSR_INTERRUPT_MCU
	.no_dead_strip	_rt61pci_mcu_request
.subsections_via_symbols
