	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function qed_fill_link_capability
_qed_fill_link_capability:              ## @qed_fill_link_capability
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	subq	$32, %rsp
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r14
	movl	%edx, %r15d
	movq	%rsi, %rbx
	movq	%rdi, %r12
	leaq	-48(%rbp), %rdx
	callq	_qed_mcp_get_media_type
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	$129, -48(%rbp)
LBB0_2:
	leaq	-52(%rbp), %rdx
	leaq	-36(%rbp), %rcx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_qed_mcp_get_transceiver_data
	testq	%rax, %rax
	je	LBB0_4
## %bb.3:
	movq	_ETH_TRANSCEIVER_STATE_UNPLUGGED@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -36(%rbp)
LBB0_4:
	leaq	-44(%rbp), %rdx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_qed_mcp_trans_speed_mask
	testq	%rax, %rax
	je	LBB0_6
## %bb.5:
	movl	$-1, -44(%rbp)
LBB0_6:
	leaq	-40(%rbp), %rdx
	movq	%r12, %rdi
	movq	%rbx, %rsi
	callq	_qed_mcp_get_board_config
	testq	%rax, %rax
	je	LBB0_7
## %bb.8:
	movq	_NVM_CFG1_PORT_PORT_TYPE_UNDEFINED@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, -40(%rbp)
	jmp	LBB0_9
LBB0_7:
	movl	-40(%rbp), %ebx
LBB0_9:
	movl	(%r12), %edi
	movq	_NETIF_MSG_DRV@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	-48(%rbp), %ecx
	movl	-52(%rbp), %r8d
	movl	-36(%rbp), %r9d
	movl	-44(%rbp), %r10d
	leaq	L_.str(%rip), %rdx
	xorl	%eax, %eax
	pushq	%rbx
	pushq	%r10
	callq	_DP_VERBOSE
	addq	$16, %rsp
	movl	-48(%rbp), %eax
	addl	$-128, %eax
	cmpl	$8, %eax
	ja	LBB0_79
## %bb.10:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_36:
	movq	_QED_LM_FIBRE_BIT@GOTPCREL(%rip), %rcx
	movl	(%r14), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r14)
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_40
## %bb.37:
	movl	-36(%rbp), %ecx
	movq	_ETH_TRANSCEIVER_TYPE_1G_LX@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	je	LBB0_39
## %bb.38:
	movq	_ETH_TRANSCEIVER_TYPE_1G_SX@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_40
LBB0_39:
	movq	_QED_LM_1000baseKX_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_40:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_49
## %bb.41:
	movl	-36(%rbp), %ecx
	movq	_ETH_TRANSCEIVER_TYPE_10G_SR@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_43
## %bb.42:
	movq	_QED_LM_10000baseSR_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_43:
	movq	_ETH_TRANSCEIVER_TYPE_10G_LR@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_45
## %bb.44:
	movq	_QED_LM_10000baseLR_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_45:
	movq	_ETH_TRANSCEIVER_TYPE_10G_LRM@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_47
## %bb.46:
	movq	_QED_LM_10000baseLRM_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_47:
	movq	_ETH_TRANSCEIVER_TYPE_10G_ER@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_49
## %bb.48:
	movq	_QED_LM_10000baseR_FEC_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_49:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_51
## %bb.50:
	movq	_QED_LM_20000baseKR2_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_51:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_54
## %bb.52:
	movl	-36(%rbp), %ecx
	movq	_ETH_TRANSCEIVER_TYPE_25G_SR@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_54
## %bb.53:
	movq	_QED_LM_25000baseSR_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_54:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_59
## %bb.55:
	movl	-36(%rbp), %ecx
	movq	_ETH_TRANSCEIVER_TYPE_40G_LR4@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_57
## %bb.56:
	movq	_QED_LM_40000baseLR4_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_57:
	movq	_ETH_TRANSCEIVER_TYPE_40G_SR4@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_59
## %bb.58:
	movq	_QED_LM_40000baseSR4_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_59:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_61
## %bb.60:
	movq	_QED_LM_50000baseKR2_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_61:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_79
## %bb.62:
	movl	-36(%rbp), %ecx
	movq	_ETH_TRANSCEIVER_TYPE_100G_SR4@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_79
## %bb.63:
	movq	_QED_LM_100000baseSR4_Full_BIT@GOTPCREL(%rip), %rcx
	jmp	LBB0_25
LBB0_78:
	movl	(%r12), %edi
	movq	_QED_MSG_DEBUG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	L_.str.1(%rip), %rdx
	xorl	%eax, %eax
	callq	_DP_VERBOSE
	jmp	LBB0_79
LBB0_64:
	movq	_QED_LM_Backplane_BIT@GOTPCREL(%rip), %rcx
	movl	(%r14), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r14)
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_66
## %bb.65:
	movq	_QED_LM_20000baseKR2_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_66:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_68
## %bb.67:
	movq	_QED_LM_1000baseKX_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_68:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_70
## %bb.69:
	movq	_QED_LM_10000baseKR_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_70:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_72
## %bb.71:
	movq	_QED_LM_25000baseKR_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_72:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_74
## %bb.73:
	movq	_QED_LM_40000baseKR4_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_74:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_76
## %bb.75:
	movq	_QED_LM_50000baseKR2_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_76:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_79
## %bb.77:
	movq	_QED_LM_100000baseKR4_Full_BIT@GOTPCREL(%rip), %rcx
	jmp	LBB0_25
LBB0_11:
	movq	_QED_LM_FIBRE_BIT@GOTPCREL(%rip), %rcx
	movl	(%r14), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r14)
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_13
## %bb.12:
	movq	_QED_LM_20000baseKR2_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_13:
	andl	-44(%rbp), %r15d
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_15
## %bb.14:
	movq	_QED_LM_1000baseKX_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_15:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_17
## %bb.16:
	movq	_QED_LM_10000baseCR_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_17:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_19
## %bb.18:
	movq	_QED_LM_40000baseCR4_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_19:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_21
## %bb.20:
	movq	_QED_LM_25000baseCR_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_21:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_23
## %bb.22:
	movq	_QED_LM_50000baseCR2_Full_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_23:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPCREL(%rip), %rcx
	testl	%r15d, (%rcx)
	je	LBB0_79
## %bb.24:
	movq	_QED_LM_100000baseCR4_Full_BIT@GOTPCREL(%rip), %rcx
	jmp	LBB0_25
LBB0_26:
	movq	_QED_LM_TP_BIT@GOTPCREL(%rip), %rcx
	movl	(%r14), %eax
	orl	(%rcx), %eax
	movl	%eax, (%r14)
	movl	-40(%rbp), %ecx
	movq	_NVM_CFG1_PORT_PORT_TYPE_EXT_PHY@GOTPCREL(%rip), %rdx
	testl	%ecx, (%rdx)
	je	LBB0_31
## %bb.27:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPCREL(%rip), %rdx
	testl	%r15d, (%rdx)
	je	LBB0_29
## %bb.28:
	movq	_QED_LM_1000baseT_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_29:
	movq	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPCREL(%rip), %rdx
	testl	%r15d, (%rdx)
	je	LBB0_31
## %bb.30:
	movq	_QED_LM_10000baseT_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_31:
	movq	_NVM_CFG1_PORT_PORT_TYPE_MODULE@GOTPCREL(%rip), %rdx
	testl	%ecx, (%rdx)
	je	LBB0_79
## %bb.32:
	movq	_QED_LM_FIBRE_BIT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%r14)
	movl	-36(%rbp), %ecx
	movq	_ETH_TRANSCEIVER_TYPE_1000BASET@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_34
## %bb.33:
	movq	_QED_LM_1000baseT_Full_BIT@GOTPCREL(%rip), %rdx
	orl	(%rdx), %eax
	movl	%eax, (%r14)
LBB0_34:
	movq	_ETH_TRANSCEIVER_TYPE_10G_BASET@GOTPCREL(%rip), %rdx
	cmpl	(%rdx), %ecx
	jne	LBB0_79
## %bb.35:
	movq	_QED_LM_10000baseT_Full_BIT@GOTPCREL(%rip), %rcx
LBB0_25:
	orl	(%rcx), %eax
	movl	%eax, (%r14)
LBB0_79:
	addq	$32, %rsp
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_36, LBB0_36-LJTI0_0
.set L0_0_set_78, LBB0_78-LJTI0_0
.set L0_0_set_64, LBB0_64-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_26, LBB0_26-LJTI0_0
LJTI0_0:
	.long	L0_0_set_36
	.long	L0_0_set_78
	.long	L0_0_set_36
	.long	L0_0_set_36
	.long	L0_0_set_78
	.long	L0_0_set_36
	.long	L0_0_set_64
	.long	L0_0_set_11
	.long	L0_0_set_26
	.end_data_region
                                        ## -- End function
	.comm	_ETH_TRANSCEIVER_STATE_UNPLUGGED,4,2 ## @ETH_TRANSCEIVER_STATE_UNPLUGGED
	.comm	_NVM_CFG1_PORT_PORT_TYPE_UNDEFINED,4,2 ## @NVM_CFG1_PORT_PORT_TYPE_UNDEFINED
	.comm	_NETIF_MSG_DRV,4,2              ## @NETIF_MSG_DRV
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n"

	.comm	_QED_LM_FIBRE_BIT,4,2           ## @QED_LM_FIBRE_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G
	.comm	_QED_LM_20000baseKR2_Full_BIT,4,2 ## @QED_LM_20000baseKR2_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
	.comm	_QED_LM_1000baseKX_Full_BIT,4,2 ## @QED_LM_1000baseKX_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
	.comm	_QED_LM_10000baseCR_Full_BIT,4,2 ## @QED_LM_10000baseCR_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
	.comm	_QED_LM_40000baseCR4_Full_BIT,4,2 ## @QED_LM_40000baseCR4_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
	.comm	_QED_LM_25000baseCR_Full_BIT,4,2 ## @QED_LM_25000baseCR_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
	.comm	_QED_LM_50000baseCR2_Full_BIT,4,2 ## @QED_LM_50000baseCR2_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G,4,2 ## @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
	.comm	_QED_LM_100000baseCR4_Full_BIT,4,2 ## @QED_LM_100000baseCR4_Full_BIT
	.comm	_QED_LM_TP_BIT,4,2              ## @QED_LM_TP_BIT
	.comm	_NVM_CFG1_PORT_PORT_TYPE_EXT_PHY,4,2 ## @NVM_CFG1_PORT_PORT_TYPE_EXT_PHY
	.comm	_QED_LM_1000baseT_Full_BIT,4,2  ## @QED_LM_1000baseT_Full_BIT
	.comm	_QED_LM_10000baseT_Full_BIT,4,2 ## @QED_LM_10000baseT_Full_BIT
	.comm	_NVM_CFG1_PORT_PORT_TYPE_MODULE,4,2 ## @NVM_CFG1_PORT_PORT_TYPE_MODULE
	.comm	_ETH_TRANSCEIVER_TYPE_1000BASET,4,2 ## @ETH_TRANSCEIVER_TYPE_1000BASET
	.comm	_ETH_TRANSCEIVER_TYPE_10G_BASET,4,2 ## @ETH_TRANSCEIVER_TYPE_10G_BASET
	.comm	_ETH_TRANSCEIVER_TYPE_1G_LX,4,2 ## @ETH_TRANSCEIVER_TYPE_1G_LX
	.comm	_ETH_TRANSCEIVER_TYPE_1G_SX,4,2 ## @ETH_TRANSCEIVER_TYPE_1G_SX
	.comm	_ETH_TRANSCEIVER_TYPE_10G_SR,4,2 ## @ETH_TRANSCEIVER_TYPE_10G_SR
	.comm	_QED_LM_10000baseSR_Full_BIT,4,2 ## @QED_LM_10000baseSR_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_10G_LR,4,2 ## @ETH_TRANSCEIVER_TYPE_10G_LR
	.comm	_QED_LM_10000baseLR_Full_BIT,4,2 ## @QED_LM_10000baseLR_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_10G_LRM,4,2 ## @ETH_TRANSCEIVER_TYPE_10G_LRM
	.comm	_QED_LM_10000baseLRM_Full_BIT,4,2 ## @QED_LM_10000baseLRM_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_10G_ER,4,2 ## @ETH_TRANSCEIVER_TYPE_10G_ER
	.comm	_QED_LM_10000baseR_FEC_BIT,4,2  ## @QED_LM_10000baseR_FEC_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_25G_SR,4,2 ## @ETH_TRANSCEIVER_TYPE_25G_SR
	.comm	_QED_LM_25000baseSR_Full_BIT,4,2 ## @QED_LM_25000baseSR_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_40G_LR4,4,2 ## @ETH_TRANSCEIVER_TYPE_40G_LR4
	.comm	_QED_LM_40000baseLR4_Full_BIT,4,2 ## @QED_LM_40000baseLR4_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_40G_SR4,4,2 ## @ETH_TRANSCEIVER_TYPE_40G_SR4
	.comm	_QED_LM_40000baseSR4_Full_BIT,4,2 ## @QED_LM_40000baseSR4_Full_BIT
	.comm	_QED_LM_50000baseKR2_Full_BIT,4,2 ## @QED_LM_50000baseKR2_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_100G_SR4,4,2 ## @ETH_TRANSCEIVER_TYPE_100G_SR4
	.comm	_QED_LM_100000baseSR4_Full_BIT,4,2 ## @QED_LM_100000baseSR4_Full_BIT
	.comm	_QED_LM_Backplane_BIT,4,2       ## @QED_LM_Backplane_BIT
	.comm	_QED_LM_10000baseKR_Full_BIT,4,2 ## @QED_LM_10000baseKR_Full_BIT
	.comm	_QED_LM_25000baseKR_Full_BIT,4,2 ## @QED_LM_25000baseKR_Full_BIT
	.comm	_QED_LM_40000baseKR4_Full_BIT,4,2 ## @QED_LM_40000baseKR4_Full_BIT
	.comm	_QED_LM_100000baseKR4_Full_BIT,4,2 ## @QED_LM_100000baseKR4_Full_BIT
	.comm	_QED_MSG_DEBUG,4,2              ## @QED_MSG_DEBUG
L_.str.1:                               ## @.str.1
	.asciz	"Unknown media and transceiver type;\n"

	.no_dead_strip	_qed_fill_link_capability
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function qed_fill_link_capability
_qed_fill_link_capability:              ; @qed_fill_link_capability
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x3
	mov	x20, x2
	mov	x22, x1
	mov	x21, x0
	sub	x2, x29, #36
	bl	_qed_mcp_get_media_type
	cbz	x0, LBB0_2
; %bb.1:
	mov	w8, #129
	stur	w8, [x29, #-36]
LBB0_2:
	sub	x2, x29, #40
	sub	x3, x29, #44
	mov	x0, x21
	mov	x1, x22
	bl	_qed_mcp_get_transceiver_data
	cbz	x0, LBB0_4
; %bb.3:
Lloh0:
	adrp	x8, _ETH_TRANSCEIVER_STATE_UNPLUGGED@GOTPAGE
Lloh1:
	ldr	x8, [x8, _ETH_TRANSCEIVER_STATE_UNPLUGGED@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	stur	w8, [x29, #-44]
LBB0_4:
	add	x2, sp, #48
	mov	x0, x21
	mov	x1, x22
	bl	_qed_mcp_trans_speed_mask
	cbz	x0, LBB0_6
; %bb.5:
	mov	w8, #-1
	str	w8, [sp, #48]
LBB0_6:
	add	x2, sp, #44
	mov	x0, x21
	mov	x1, x22
	bl	_qed_mcp_get_board_config
	cbz	x0, LBB0_8
; %bb.7:
Lloh3:
	adrp	x8, _NVM_CFG1_PORT_PORT_TYPE_UNDEFINED@GOTPAGE
Lloh4:
	ldr	x8, [x8, _NVM_CFG1_PORT_PORT_TYPE_UNDEFINED@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	str	w8, [sp, #44]
	b	LBB0_9
LBB0_8:
	ldr	w8, [sp, #44]
LBB0_9:
Lloh6:
	adrp	x9, _NETIF_MSG_DRV@GOTPAGE
Lloh7:
	ldr	x9, [x9, _NETIF_MSG_DRV@GOTPAGEOFF]
	ldr	w0, [x21]
Lloh8:
	ldr	w1, [x9]
	ldp	w10, w9, [x29, #-40]
	ldur	w11, [x29, #-44]
	ldr	w12, [sp, #48]
	stp	x12, x8, [sp, #24]
	stp	x10, x11, [sp, #8]
	str	x9, [sp]
Lloh9:
	adrp	x2, l_.str@PAGE
Lloh10:
	add	x2, x2, l_.str@PAGEOFF
	bl	_DP_VERBOSE
	ldur	w8, [x29, #-36]
	sub	w8, w8, #128
	cmp	w8, #8
	b.hi	LBB0_79
; %bb.10:
Lloh11:
	adrp	x9, lJTI0_0@PAGE
Lloh12:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_11
	ldrh	w11, [x9, x8, lsl #1]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_11:
Lloh13:
	adrp	x8, _QED_LM_FIBRE_BIT@GOTPAGE
Lloh14:
	ldr	x8, [x8, _QED_LM_FIBRE_BIT@GOTPAGEOFF]
Lloh15:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
Lloh16:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh17:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
Lloh18:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_15
; %bb.12:
	ldur	w9, [x29, #-44]
Lloh19:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_1G_LX@GOTPAGE
Lloh20:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_1G_LX@GOTPAGEOFF]
Lloh21:
	ldr	w10, [x10]
	cmp	w9, w10
	b.eq	LBB0_14
; %bb.13:
Lloh22:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_1G_SX@GOTPAGE
Lloh23:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_1G_SX@GOTPAGEOFF]
Lloh24:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_15
LBB0_14:
Lloh25:
	adrp	x9, _QED_LM_1000baseKX_Full_BIT@GOTPAGE
Lloh26:
	ldr	x9, [x9, _QED_LM_1000baseKX_Full_BIT@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_15:
Lloh28:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh29:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh30:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_24
; %bb.16:
	ldur	w9, [x29, #-44]
Lloh31:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_10G_SR@GOTPAGE
Lloh32:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_10G_SR@GOTPAGEOFF]
Lloh33:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_18
; %bb.17:
Lloh34:
	adrp	x10, _QED_LM_10000baseSR_Full_BIT@GOTPAGE
Lloh35:
	ldr	x10, [x10, _QED_LM_10000baseSR_Full_BIT@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_18:
Lloh37:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_10G_LR@GOTPAGE
Lloh38:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_10G_LR@GOTPAGEOFF]
Lloh39:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_20
; %bb.19:
Lloh40:
	adrp	x10, _QED_LM_10000baseLR_Full_BIT@GOTPAGE
Lloh41:
	ldr	x10, [x10, _QED_LM_10000baseLR_Full_BIT@GOTPAGEOFF]
Lloh42:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_20:
Lloh43:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_10G_LRM@GOTPAGE
Lloh44:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_10G_LRM@GOTPAGEOFF]
Lloh45:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_22
; %bb.21:
Lloh46:
	adrp	x10, _QED_LM_10000baseLRM_Full_BIT@GOTPAGE
Lloh47:
	ldr	x10, [x10, _QED_LM_10000baseLRM_Full_BIT@GOTPAGEOFF]
Lloh48:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_22:
Lloh49:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_10G_ER@GOTPAGE
Lloh50:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_10G_ER@GOTPAGEOFF]
Lloh51:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_24
; %bb.23:
Lloh52:
	adrp	x9, _QED_LM_10000baseR_FEC_BIT@GOTPAGE
Lloh53:
	ldr	x9, [x9, _QED_LM_10000baseR_FEC_BIT@GOTPAGEOFF]
Lloh54:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_24:
Lloh55:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGE
Lloh56:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGEOFF]
Lloh57:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_26
; %bb.25:
Lloh58:
	adrp	x9, _QED_LM_20000baseKR2_Full_BIT@GOTPAGE
Lloh59:
	ldr	x9, [x9, _QED_LM_20000baseKR2_Full_BIT@GOTPAGEOFF]
Lloh60:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_26:
Lloh61:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh62:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
Lloh63:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_29
; %bb.27:
	ldur	w9, [x29, #-44]
Lloh64:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_25G_SR@GOTPAGE
Lloh65:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_25G_SR@GOTPAGEOFF]
Lloh66:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_29
; %bb.28:
Lloh67:
	adrp	x9, _QED_LM_25000baseSR_Full_BIT@GOTPAGE
Lloh68:
	ldr	x9, [x9, _QED_LM_25000baseSR_Full_BIT@GOTPAGEOFF]
Lloh69:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_29:
Lloh70:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh71:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh72:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_34
; %bb.30:
	ldur	w9, [x29, #-44]
Lloh73:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_40G_LR4@GOTPAGE
Lloh74:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_40G_LR4@GOTPAGEOFF]
Lloh75:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_32
; %bb.31:
Lloh76:
	adrp	x10, _QED_LM_40000baseLR4_Full_BIT@GOTPAGE
Lloh77:
	ldr	x10, [x10, _QED_LM_40000baseLR4_Full_BIT@GOTPAGEOFF]
Lloh78:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_32:
Lloh79:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_40G_SR4@GOTPAGE
Lloh80:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_40G_SR4@GOTPAGEOFF]
Lloh81:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_34
; %bb.33:
Lloh82:
	adrp	x9, _QED_LM_40000baseSR4_Full_BIT@GOTPAGE
Lloh83:
	ldr	x9, [x9, _QED_LM_40000baseSR4_Full_BIT@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_34:
Lloh85:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGE
Lloh86:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGEOFF]
Lloh87:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_36
; %bb.35:
Lloh88:
	adrp	x9, _QED_LM_50000baseKR2_Full_BIT@GOTPAGE
Lloh89:
	ldr	x9, [x9, _QED_LM_50000baseKR2_Full_BIT@GOTPAGEOFF]
Lloh90:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_36:
Lloh91:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGE
Lloh92:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGEOFF]
Lloh93:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_79
; %bb.37:
	ldur	w9, [x29, #-44]
Lloh94:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_100G_SR4@GOTPAGE
Lloh95:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_100G_SR4@GOTPAGEOFF]
Lloh96:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_79
; %bb.38:
Lloh97:
	adrp	x9, _QED_LM_100000baseSR4_Full_BIT@GOTPAGE
Lloh98:
	ldr	x9, [x9, _QED_LM_100000baseSR4_Full_BIT@GOTPAGEOFF]
	b	LBB0_78
LBB0_39:
	ldr	w0, [x21]
Lloh99:
	adrp	x8, _QED_MSG_DEBUG@GOTPAGE
Lloh100:
	ldr	x8, [x8, _QED_MSG_DEBUG@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
Lloh102:
	adrp	x2, l_.str.1@PAGE
Lloh103:
	add	x2, x2, l_.str.1@PAGEOFF
	bl	_DP_VERBOSE
	b	LBB0_79
LBB0_40:
Lloh104:
	adrp	x8, _QED_LM_Backplane_BIT@GOTPAGE
Lloh105:
	ldr	x8, [x8, _QED_LM_Backplane_BIT@GOTPAGEOFF]
Lloh106:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
Lloh107:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGE
Lloh108:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGEOFF]
Lloh109:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_42
; %bb.41:
Lloh110:
	adrp	x9, _QED_LM_20000baseKR2_Full_BIT@GOTPAGE
Lloh111:
	ldr	x9, [x9, _QED_LM_20000baseKR2_Full_BIT@GOTPAGEOFF]
Lloh112:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_42:
Lloh113:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh114:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
Lloh115:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_44
; %bb.43:
Lloh116:
	adrp	x9, _QED_LM_1000baseKX_Full_BIT@GOTPAGE
Lloh117:
	ldr	x9, [x9, _QED_LM_1000baseKX_Full_BIT@GOTPAGEOFF]
Lloh118:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_44:
Lloh119:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh120:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh121:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_46
; %bb.45:
Lloh122:
	adrp	x9, _QED_LM_10000baseKR_Full_BIT@GOTPAGE
Lloh123:
	ldr	x9, [x9, _QED_LM_10000baseKR_Full_BIT@GOTPAGEOFF]
Lloh124:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_46:
Lloh125:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh126:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
Lloh127:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_48
; %bb.47:
Lloh128:
	adrp	x9, _QED_LM_25000baseKR_Full_BIT@GOTPAGE
Lloh129:
	ldr	x9, [x9, _QED_LM_25000baseKR_Full_BIT@GOTPAGEOFF]
Lloh130:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_48:
Lloh131:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh132:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh133:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_50
; %bb.49:
Lloh134:
	adrp	x9, _QED_LM_40000baseKR4_Full_BIT@GOTPAGE
Lloh135:
	ldr	x9, [x9, _QED_LM_40000baseKR4_Full_BIT@GOTPAGEOFF]
Lloh136:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_50:
Lloh137:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGE
Lloh138:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGEOFF]
Lloh139:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_52
; %bb.51:
Lloh140:
	adrp	x9, _QED_LM_50000baseKR2_Full_BIT@GOTPAGE
Lloh141:
	ldr	x9, [x9, _QED_LM_50000baseKR2_Full_BIT@GOTPAGEOFF]
Lloh142:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_52:
Lloh143:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGE
Lloh144:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGEOFF]
Lloh145:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_79
; %bb.53:
Lloh146:
	adrp	x9, _QED_LM_100000baseKR4_Full_BIT@GOTPAGE
Lloh147:
	ldr	x9, [x9, _QED_LM_100000baseKR4_Full_BIT@GOTPAGEOFF]
	b	LBB0_78
LBB0_54:
Lloh148:
	adrp	x8, _QED_LM_FIBRE_BIT@GOTPAGE
Lloh149:
	ldr	x8, [x8, _QED_LM_FIBRE_BIT@GOTPAGEOFF]
Lloh150:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
Lloh151:
	adrp	x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGE
Lloh152:
	ldr	x9, [x9, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G@GOTPAGEOFF]
Lloh153:
	ldr	w9, [x9]
	tst	w9, w20
	b.eq	LBB0_56
; %bb.55:
Lloh154:
	adrp	x9, _QED_LM_20000baseKR2_Full_BIT@GOTPAGE
Lloh155:
	ldr	x9, [x9, _QED_LM_20000baseKR2_Full_BIT@GOTPAGEOFF]
Lloh156:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x19]
LBB0_56:
	ldr	w9, [sp, #48]
	and	w9, w9, w20
Lloh157:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh158:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
Lloh159:
	ldr	w10, [x10]
	tst	w9, w10
	b.eq	LBB0_58
; %bb.57:
Lloh160:
	adrp	x10, _QED_LM_1000baseKX_Full_BIT@GOTPAGE
Lloh161:
	ldr	x10, [x10, _QED_LM_1000baseKX_Full_BIT@GOTPAGEOFF]
Lloh162:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_58:
Lloh163:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh164:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh165:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_60
; %bb.59:
Lloh166:
	adrp	x10, _QED_LM_10000baseCR_Full_BIT@GOTPAGE
Lloh167:
	ldr	x10, [x10, _QED_LM_10000baseCR_Full_BIT@GOTPAGEOFF]
Lloh168:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_60:
Lloh169:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGE
Lloh170:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G@GOTPAGEOFF]
Lloh171:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_62
; %bb.61:
Lloh172:
	adrp	x10, _QED_LM_40000baseCR4_Full_BIT@GOTPAGE
Lloh173:
	ldr	x10, [x10, _QED_LM_40000baseCR4_Full_BIT@GOTPAGEOFF]
Lloh174:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_62:
Lloh175:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGE
Lloh176:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G@GOTPAGEOFF]
Lloh177:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_64
; %bb.63:
Lloh178:
	adrp	x10, _QED_LM_25000baseCR_Full_BIT@GOTPAGE
Lloh179:
	ldr	x10, [x10, _QED_LM_25000baseCR_Full_BIT@GOTPAGEOFF]
Lloh180:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_64:
Lloh181:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGE
Lloh182:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G@GOTPAGEOFF]
Lloh183:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_66
; %bb.65:
Lloh184:
	adrp	x10, _QED_LM_50000baseCR2_Full_BIT@GOTPAGE
Lloh185:
	ldr	x10, [x10, _QED_LM_50000baseCR2_Full_BIT@GOTPAGEOFF]
Lloh186:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_66:
Lloh187:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGE
Lloh188:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G@GOTPAGEOFF]
Lloh189:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_79
; %bb.67:
Lloh190:
	adrp	x9, _QED_LM_100000baseCR4_Full_BIT@GOTPAGE
Lloh191:
	ldr	x9, [x9, _QED_LM_100000baseCR4_Full_BIT@GOTPAGEOFF]
	b	LBB0_78
LBB0_68:
Lloh192:
	adrp	x8, _QED_LM_TP_BIT@GOTPAGE
Lloh193:
	ldr	x8, [x8, _QED_LM_TP_BIT@GOTPAGEOFF]
Lloh194:
	ldr	w8, [x8]
	ldr	w9, [x19]
	orr	w8, w9, w8
	str	w8, [x19]
	ldr	w9, [sp, #44]
Lloh195:
	adrp	x10, _NVM_CFG1_PORT_PORT_TYPE_EXT_PHY@GOTPAGE
Lloh196:
	ldr	x10, [x10, _NVM_CFG1_PORT_PORT_TYPE_EXT_PHY@GOTPAGEOFF]
Lloh197:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_73
; %bb.69:
Lloh198:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGE
Lloh199:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G@GOTPAGEOFF]
Lloh200:
	ldr	w10, [x10]
	tst	w10, w20
	b.eq	LBB0_71
; %bb.70:
Lloh201:
	adrp	x10, _QED_LM_1000baseT_Full_BIT@GOTPAGE
Lloh202:
	ldr	x10, [x10, _QED_LM_1000baseT_Full_BIT@GOTPAGEOFF]
Lloh203:
	ldr	w10, [x10]
	orr	w8, w10, w8
	str	w8, [x19]
LBB0_71:
Lloh204:
	adrp	x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGE
Lloh205:
	ldr	x10, [x10, _NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G@GOTPAGEOFF]
Lloh206:
	ldr	w10, [x10]
	tst	w10, w20
	b.eq	LBB0_73
; %bb.72:
Lloh207:
	adrp	x10, _QED_LM_10000baseT_Full_BIT@GOTPAGE
Lloh208:
	ldr	x10, [x10, _QED_LM_10000baseT_Full_BIT@GOTPAGEOFF]
Lloh209:
	ldr	w10, [x10]
	orr	w8, w8, w10
	str	w8, [x19]
LBB0_73:
Lloh210:
	adrp	x10, _NVM_CFG1_PORT_PORT_TYPE_MODULE@GOTPAGE
Lloh211:
	ldr	x10, [x10, _NVM_CFG1_PORT_PORT_TYPE_MODULE@GOTPAGEOFF]
Lloh212:
	ldr	w10, [x10]
	tst	w10, w9
	b.eq	LBB0_79
; %bb.74:
Lloh213:
	adrp	x9, _QED_LM_FIBRE_BIT@GOTPAGE
Lloh214:
	ldr	x9, [x9, _QED_LM_FIBRE_BIT@GOTPAGEOFF]
Lloh215:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
	ldur	w9, [x29, #-44]
Lloh216:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_1000BASET@GOTPAGE
Lloh217:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_1000BASET@GOTPAGEOFF]
Lloh218:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_76
; %bb.75:
Lloh219:
	adrp	x10, _QED_LM_1000baseT_Full_BIT@GOTPAGE
Lloh220:
	ldr	x10, [x10, _QED_LM_1000baseT_Full_BIT@GOTPAGEOFF]
Lloh221:
	ldr	w10, [x10]
	orr	w8, w10, w8
	str	w8, [x19]
LBB0_76:
Lloh222:
	adrp	x10, _ETH_TRANSCEIVER_TYPE_10G_BASET@GOTPAGE
Lloh223:
	ldr	x10, [x10, _ETH_TRANSCEIVER_TYPE_10G_BASET@GOTPAGEOFF]
Lloh224:
	ldr	w10, [x10]
	cmp	w9, w10
	b.ne	LBB0_79
; %bb.77:
Lloh225:
	adrp	x9, _QED_LM_10000baseT_Full_BIT@GOTPAGE
Lloh226:
	ldr	x9, [x9, _QED_LM_10000baseT_Full_BIT@GOTPAGEOFF]
LBB0_78:
	ldr	w9, [x9]
	orr	w8, w8, w9
	str	w8, [x19]
LBB0_79:
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGot	Lloh97, Lloh98
	.loh AdrpAdd	Lloh102, Lloh103
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh107, Lloh108, Lloh109
	.loh AdrpLdrGotLdr	Lloh104, Lloh105, Lloh106
	.loh AdrpLdrGotLdr	Lloh110, Lloh111, Lloh112
	.loh AdrpLdrGotLdr	Lloh113, Lloh114, Lloh115
	.loh AdrpLdrGotLdr	Lloh116, Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh119, Lloh120, Lloh121
	.loh AdrpLdrGotLdr	Lloh122, Lloh123, Lloh124
	.loh AdrpLdrGotLdr	Lloh125, Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh128, Lloh129, Lloh130
	.loh AdrpLdrGotLdr	Lloh131, Lloh132, Lloh133
	.loh AdrpLdrGotLdr	Lloh134, Lloh135, Lloh136
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGot	Lloh146, Lloh147
	.loh AdrpLdrGotLdr	Lloh151, Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh148, Lloh149, Lloh150
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh174
	.loh AdrpLdrGotLdr	Lloh175, Lloh176, Lloh177
	.loh AdrpLdrGotLdr	Lloh178, Lloh179, Lloh180
	.loh AdrpLdrGotLdr	Lloh181, Lloh182, Lloh183
	.loh AdrpLdrGotLdr	Lloh184, Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh187, Lloh188, Lloh189
	.loh AdrpLdrGot	Lloh190, Lloh191
	.loh AdrpLdrGotLdr	Lloh195, Lloh196, Lloh197
	.loh AdrpLdrGotLdr	Lloh192, Lloh193, Lloh194
	.loh AdrpLdrGotLdr	Lloh198, Lloh199, Lloh200
	.loh AdrpLdrGotLdr	Lloh201, Lloh202, Lloh203
	.loh AdrpLdrGotLdr	Lloh204, Lloh205, Lloh206
	.loh AdrpLdrGotLdr	Lloh207, Lloh208, Lloh209
	.loh AdrpLdrGotLdr	Lloh210, Lloh211, Lloh212
	.loh AdrpLdrGotLdr	Lloh216, Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh213, Lloh214, Lloh215
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh222, Lloh223, Lloh224
	.loh AdrpLdrGot	Lloh225, Lloh226
	.cfi_endproc
	.section	__TEXT,__const
	.p2align	1
lJTI0_0:
	.short	(LBB0_11-LBB0_11)>>2
	.short	(LBB0_39-LBB0_11)>>2
	.short	(LBB0_11-LBB0_11)>>2
	.short	(LBB0_11-LBB0_11)>>2
	.short	(LBB0_39-LBB0_11)>>2
	.short	(LBB0_11-LBB0_11)>>2
	.short	(LBB0_40-LBB0_11)>>2
	.short	(LBB0_54-LBB0_11)>>2
	.short	(LBB0_68-LBB0_11)>>2
                                        ; -- End function
	.comm	_ETH_TRANSCEIVER_STATE_UNPLUGGED,4,2 ; @ETH_TRANSCEIVER_STATE_UNPLUGGED
	.comm	_NVM_CFG1_PORT_PORT_TYPE_UNDEFINED,4,2 ; @NVM_CFG1_PORT_PORT_TYPE_UNDEFINED
	.comm	_NETIF_MSG_DRV,4,2              ; @NETIF_MSG_DRV
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Media_type = 0x%x tcvr_state = 0x%x tcvr_type = 0x%x speed_mask = 0x%x board_cfg = 0x%x\n"

	.comm	_QED_LM_FIBRE_BIT,4,2           ; @QED_LM_FIBRE_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G
	.comm	_QED_LM_20000baseKR2_Full_BIT,4,2 ; @QED_LM_20000baseKR2_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G
	.comm	_QED_LM_1000baseKX_Full_BIT,4,2 ; @QED_LM_1000baseKX_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G
	.comm	_QED_LM_10000baseCR_Full_BIT,4,2 ; @QED_LM_10000baseCR_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G
	.comm	_QED_LM_40000baseCR4_Full_BIT,4,2 ; @QED_LM_40000baseCR4_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G
	.comm	_QED_LM_25000baseCR_Full_BIT,4,2 ; @QED_LM_25000baseCR_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G
	.comm	_QED_LM_50000baseCR2_Full_BIT,4,2 ; @QED_LM_50000baseCR2_Full_BIT
	.comm	_NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G,4,2 ; @NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G
	.comm	_QED_LM_100000baseCR4_Full_BIT,4,2 ; @QED_LM_100000baseCR4_Full_BIT
	.comm	_QED_LM_TP_BIT,4,2              ; @QED_LM_TP_BIT
	.comm	_NVM_CFG1_PORT_PORT_TYPE_EXT_PHY,4,2 ; @NVM_CFG1_PORT_PORT_TYPE_EXT_PHY
	.comm	_QED_LM_1000baseT_Full_BIT,4,2  ; @QED_LM_1000baseT_Full_BIT
	.comm	_QED_LM_10000baseT_Full_BIT,4,2 ; @QED_LM_10000baseT_Full_BIT
	.comm	_NVM_CFG1_PORT_PORT_TYPE_MODULE,4,2 ; @NVM_CFG1_PORT_PORT_TYPE_MODULE
	.comm	_ETH_TRANSCEIVER_TYPE_1000BASET,4,2 ; @ETH_TRANSCEIVER_TYPE_1000BASET
	.comm	_ETH_TRANSCEIVER_TYPE_10G_BASET,4,2 ; @ETH_TRANSCEIVER_TYPE_10G_BASET
	.comm	_ETH_TRANSCEIVER_TYPE_1G_LX,4,2 ; @ETH_TRANSCEIVER_TYPE_1G_LX
	.comm	_ETH_TRANSCEIVER_TYPE_1G_SX,4,2 ; @ETH_TRANSCEIVER_TYPE_1G_SX
	.comm	_ETH_TRANSCEIVER_TYPE_10G_SR,4,2 ; @ETH_TRANSCEIVER_TYPE_10G_SR
	.comm	_QED_LM_10000baseSR_Full_BIT,4,2 ; @QED_LM_10000baseSR_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_10G_LR,4,2 ; @ETH_TRANSCEIVER_TYPE_10G_LR
	.comm	_QED_LM_10000baseLR_Full_BIT,4,2 ; @QED_LM_10000baseLR_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_10G_LRM,4,2 ; @ETH_TRANSCEIVER_TYPE_10G_LRM
	.comm	_QED_LM_10000baseLRM_Full_BIT,4,2 ; @QED_LM_10000baseLRM_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_10G_ER,4,2 ; @ETH_TRANSCEIVER_TYPE_10G_ER
	.comm	_QED_LM_10000baseR_FEC_BIT,4,2  ; @QED_LM_10000baseR_FEC_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_25G_SR,4,2 ; @ETH_TRANSCEIVER_TYPE_25G_SR
	.comm	_QED_LM_25000baseSR_Full_BIT,4,2 ; @QED_LM_25000baseSR_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_40G_LR4,4,2 ; @ETH_TRANSCEIVER_TYPE_40G_LR4
	.comm	_QED_LM_40000baseLR4_Full_BIT,4,2 ; @QED_LM_40000baseLR4_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_40G_SR4,4,2 ; @ETH_TRANSCEIVER_TYPE_40G_SR4
	.comm	_QED_LM_40000baseSR4_Full_BIT,4,2 ; @QED_LM_40000baseSR4_Full_BIT
	.comm	_QED_LM_50000baseKR2_Full_BIT,4,2 ; @QED_LM_50000baseKR2_Full_BIT
	.comm	_ETH_TRANSCEIVER_TYPE_100G_SR4,4,2 ; @ETH_TRANSCEIVER_TYPE_100G_SR4
	.comm	_QED_LM_100000baseSR4_Full_BIT,4,2 ; @QED_LM_100000baseSR4_Full_BIT
	.comm	_QED_LM_Backplane_BIT,4,2       ; @QED_LM_Backplane_BIT
	.comm	_QED_LM_10000baseKR_Full_BIT,4,2 ; @QED_LM_10000baseKR_Full_BIT
	.comm	_QED_LM_25000baseKR_Full_BIT,4,2 ; @QED_LM_25000baseKR_Full_BIT
	.comm	_QED_LM_40000baseKR4_Full_BIT,4,2 ; @QED_LM_40000baseKR4_Full_BIT
	.comm	_QED_LM_100000baseKR4_Full_BIT,4,2 ; @QED_LM_100000baseKR4_Full_BIT
	.comm	_QED_MSG_DEBUG,4,2              ; @QED_MSG_DEBUG
l_.str.1:                               ; @.str.1
	.asciz	"Unknown media and transceiver type;\n"

	.no_dead_strip	_qed_fill_link_capability
.subsections_via_symbols
