	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function __hw_perf_event_init
___hw_perf_event_init:                  ## @__hw_perf_event_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movl	72(%rdi), %edi
	callq	_to_arm_pmu
	movq	%rax, %r15
	movq	$0, 64(%rbx)
	movq	%rbx, %rdi
	callq	*(%rax)
	movl	%eax, %r14d
	testl	%eax, %eax
	js	LBB0_1
## %bb.2:
	movl	$-1, 16(%rbx)
	movq	$0, 24(%rbx)
	xorps	%xmm0, %xmm0
	movups	%xmm0, 48(%rbx)
	movq	8(%r15), %rcx
	testq	%rcx, %rcx
	je	LBB0_3
## %bb.4:
	leaq	16(%rbx), %rdi
	leaq	8(%rbx), %rsi
	callq	*%rcx
	testq	%rax, %rax
	je	LBB0_5
## %bb.13:
	leaq	L_.str.1(%rip), %rdi
	xorl	%r14d, %r14d
	xorl	%eax, %eax
	callq	_pr_debug
	movq	_EOPNOTSUPP@GOTPCREL(%rip), %rax
	jmp	LBB0_11
LBB0_1:
	movl	8(%rbx), %edx
	movl	12(%rbx), %esi
	leaq	L_.str(%rip), %rdi
	xorl	%eax, %eax
	callq	_pr_debug
	jmp	LBB0_12
LBB0_3:
	xorl	%eax, %eax
	jmp	LBB0_6
LBB0_5:
	movq	24(%rbx), %rax
LBB0_6:
	movl	%r14d, %ecx
	orq	%rax, %rcx
	movq	%rcx, 24(%rbx)
	movq	%rbx, %rdi
	callq	_is_sampling_event
	testl	%eax, %eax
	jne	LBB0_8
## %bb.7:
	movq	%rbx, %rdi
	callq	_arm_pmu_event_max_period
	sarl	%eax
	movl	%eax, 32(%rbx)
	movl	%eax, 36(%rbx)
	leaq	40(%rbx), %rdi
	movl	%eax, %esi
	callq	_local64_set
LBB0_8:
	xorl	%r14d, %r14d
	cmpq	%rbx, (%rbx)
	je	LBB0_12
## %bb.9:
	movq	%rbx, %rdi
	callq	_validate_group
	testq	%rax, %rax
	je	LBB0_12
## %bb.10:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%r14d, %r14d
LBB0_11:
	subl	(%rax), %r14d
LBB0_12:
	movl	%r14d, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"event %x:%llx not supported\n"

L_.str.1:                               ## @.str.1
	.asciz	"ARM performance counters do not support mode exclusion\n"

	.comm	_EOPNOTSUPP,4,2                 ## @EOPNOTSUPP
	.comm	_EINVAL,4,2                     ## @EINVAL
	.no_dead_strip	___hw_perf_event_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function __hw_perf_event_init
___hw_perf_event_init:                  ; @__hw_perf_event_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0, #72]
	bl	_to_arm_pmu
	mov	x21, x0
	str	xzr, [x19, #64]
	ldr	x8, [x0]
	mov	x0, x19
	blr	x8
	mov	x20, x0
	tbnz	w0, #31, LBB0_4
; %bb.1:
	mov	w8, #-1
	str	w8, [x19, #16]
	str	xzr, [x19, #24]
	stp	xzr, xzr, [x19, #48]
	ldr	x8, [x21, #8]
	cbz	x8, LBB0_6
; %bb.2:
	add	x0, x19, #16
	add	x1, x19, #8
	blr	x8
	cbz	x0, LBB0_5
; %bb.3:
Lloh0:
	adrp	x0, l_.str.1@PAGE
Lloh1:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_pr_debug
Lloh2:
	adrp	x8, _EOPNOTSUPP@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EOPNOTSUPP@GOTPAGEOFF]
	b	LBB0_11
LBB0_4:
	ldp	w9, w8, [x19, #8]
	stp	x8, x9, [sp]
Lloh4:
	adrp	x0, l_.str@PAGE
Lloh5:
	add	x0, x0, l_.str@PAGEOFF
	bl	_pr_debug
	b	LBB0_13
LBB0_5:
	ldr	x8, [x19, #24]
LBB0_6:
	mov	w9, w20
	orr	x8, x8, x9
	str	x8, [x19, #24]
	mov	x0, x19
	bl	_is_sampling_event
	cbnz	w0, LBB0_8
; %bb.7:
	mov	x0, x19
	bl	_arm_pmu_event_max_period
	asr	w1, w0, #1
	stp	w1, w1, [x19, #32]
	add	x0, x19, #40
	bl	_local64_set
LBB0_8:
	ldr	x8, [x19]
	cmp	x8, x19
	b.eq	LBB0_12
; %bb.9:
	mov	x0, x19
	bl	_validate_group
	cbz	x0, LBB0_12
; %bb.10:
Lloh6:
	adrp	x8, _EINVAL@GOTPAGE
Lloh7:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_11:
	ldr	w8, [x8]
	neg	w20, w8
	b	LBB0_13
LBB0_12:
	mov	w20, #0
LBB0_13:
	mov	x0, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"event %x:%llx not supported\n"

l_.str.1:                               ; @.str.1
	.asciz	"ARM performance counters do not support mode exclusion\n"

	.comm	_EOPNOTSUPP,4,2                 ; @EOPNOTSUPP
	.comm	_EINVAL,4,2                     ; @EINVAL
	.no_dead_strip	___hw_perf_event_init
.subsections_via_symbols
