	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_defaults_set
_mvpp2_defaults_set:                    ## @mvpp2_defaults_set
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	8(%rdi), %rax
	movq	(%rax), %rax
	movq	_MVPP21@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_2
## %bb.1:
	movq	_MVPP2_GMAC_PORT_FIFO_CFG_1_REG@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	32(%r14), %rdi
	callq	_readl
	movq	_MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$58, %edi
	callq	_MVPP2_GMAC_TX_FIFO_MIN_TH_MASK
	orl	%eax, %ebx
	movq	(%r15), %rsi
	addq	32(%r14), %rsi
	movl	%ebx, %edi
	callq	_writel
LBB0_2:
	movq	%r14, %rdi
	callq	_mvpp2_egress_port
	movq	8(%r14), %rdi
	movq	_MVPP2_TXP_SCHED_PORT_INDEX_REG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edx
	callq	_mvpp2_write
	movq	8(%r14), %rdi
	movq	_MVPP2_TXP_SCHED_CMD_1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%ebx, %ebx
	xorl	%edx, %edx
	callq	_mvpp2_write
	movq	8(%r14), %rdi
	movq	_MVPP2_TXP_SCHED_FIXED_PRIO_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_mvpp2_write
	movq	_MVPP2_MAX_TXQ@GOTPCREL(%rip), %r12
	cmpl	$0, (%r12)
	jle	LBB0_4
	.p2align	4, 0x90
LBB0_3:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %r15
	movl	%ebx, %edi
	callq	_MVPP2_TXQ_SCHED_TOKEN_CNTR_REG
	movq	%r15, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_mvpp2_write
	incl	%ebx
	cmpl	(%r12), %ebx
	jl	LBB0_3
LBB0_4:
	movq	8(%r14), %rdi
	movq	_MVPP2_TXP_SCHED_PERIOD_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	8(%rdi), %eax
	movq	_USEC_PER_SEC@GOTPCREL(%rip), %rcx
	cltd
	idivl	(%rcx)
	movl	%eax, %edx
	callq	_mvpp2_write
	movq	8(%r14), %rdi
	movq	_MVPP2_TXP_SCHED_REFILL_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_mvpp2_read
	movq	_MVPP2_TXP_REFILL_PERIOD_ALL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	notl	%ebx
	andl	%eax, %ebx
	movl	$1, %edi
	callq	_MVPP2_TXP_REFILL_PERIOD_MASK
	orl	%eax, %ebx
	movq	_MVPP2_TXP_REFILL_TOKENS_ALL_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	8(%r14), %rdi
	movl	(%r15), %esi
	movl	%ebx, %edx
	callq	_mvpp2_write
	movq	_MVPP2_TXP_TOKEN_SIZE_MAX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	8(%r14), %rdi
	movq	_MVPP2_TXP_SCHED_TOKEN_SIZE_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_mvpp2_write
	movq	8(%r14), %r15
	movl	24(%r14), %edi
	callq	_MVPP2_RX_CTRL_REG
	movl	%eax, %r12d
	movq	_MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$256, %edi                      ## imm = 0x100
	callq	_MVPP2_RX_LOW_LATENCY_PKT_SIZE
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	callq	_mvpp2_write
	cmpl	$0, (%r14)
	jle	LBB0_7
## %bb.5:
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	8(%r14), %r15
	movq	16(%r14), %rax
	movq	(%rax,%r13,8), %rax
	movl	(%rax), %r12d
	movl	%r12d, %edi
	callq	_MVPP2_RXQ_CONFIG_REG
	movq	%r15, %rdi
	movl	%eax, %esi
	callq	_mvpp2_read
	movl	%eax, %ebx
	movq	_MVPP2_SNOOP_PKT_SIZE_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_MVPP2_SNOOP_BUF_HDR_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	8(%r14), %r15
	movl	%r12d, %edi
	callq	_MVPP2_RXQ_CONFIG_REG
	movq	%r15, %rdi
	movl	%eax, %esi
	movl	%ebx, %edx
	callq	_mvpp2_write
	incq	%r13
	movslq	(%r14), %rax
	cmpq	%rax, %r13
	jl	LBB0_6
LBB0_7:
	movq	%r14, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvpp2_interrupts_disable       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP21,8,3                     ## @MVPP21
	.comm	_MVPP2_GMAC_PORT_FIFO_CFG_1_REG,8,3 ## @MVPP2_GMAC_PORT_FIFO_CFG_1_REG
	.comm	_MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK,4,2 ## @MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK
	.comm	_MVPP2_TXP_SCHED_PORT_INDEX_REG,4,2 ## @MVPP2_TXP_SCHED_PORT_INDEX_REG
	.comm	_MVPP2_TXP_SCHED_CMD_1_REG,4,2  ## @MVPP2_TXP_SCHED_CMD_1_REG
	.comm	_MVPP2_TXP_SCHED_FIXED_PRIO_REG,4,2 ## @MVPP2_TXP_SCHED_FIXED_PRIO_REG
	.comm	_MVPP2_MAX_TXQ,4,2              ## @MVPP2_MAX_TXQ
	.comm	_MVPP2_TXP_SCHED_PERIOD_REG,4,2 ## @MVPP2_TXP_SCHED_PERIOD_REG
	.comm	_USEC_PER_SEC,4,2               ## @USEC_PER_SEC
	.comm	_MVPP2_TXP_SCHED_REFILL_REG,4,2 ## @MVPP2_TXP_SCHED_REFILL_REG
	.comm	_MVPP2_TXP_REFILL_PERIOD_ALL_MASK,4,2 ## @MVPP2_TXP_REFILL_PERIOD_ALL_MASK
	.comm	_MVPP2_TXP_REFILL_TOKENS_ALL_MASK,4,2 ## @MVPP2_TXP_REFILL_TOKENS_ALL_MASK
	.comm	_MVPP2_TXP_TOKEN_SIZE_MAX,4,2   ## @MVPP2_TXP_TOKEN_SIZE_MAX
	.comm	_MVPP2_TXP_SCHED_TOKEN_SIZE_REG,4,2 ## @MVPP2_TXP_SCHED_TOKEN_SIZE_REG
	.comm	_MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK,4,2 ## @MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK
	.comm	_MVPP2_SNOOP_PKT_SIZE_MASK,4,2  ## @MVPP2_SNOOP_PKT_SIZE_MASK
	.comm	_MVPP2_SNOOP_BUF_HDR_MASK,4,2   ## @MVPP2_SNOOP_BUF_HDR_MASK
	.no_dead_strip	_mvpp2_defaults_set
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_defaults_set
_mvpp2_defaults_set:                    ; @mvpp2_defaults_set
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x8, [x8]
Lloh0:
	adrp	x9, _MVPP21@GOTPAGE
Lloh1:
	ldr	x9, [x9, _MVPP21@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_2
; %bb.1:
	ldr	x8, [x19, #32]
Lloh3:
	adrp	x20, _MVPP2_GMAC_PORT_FIFO_CFG_1_REG@GOTPAGE
Lloh4:
	ldr	x20, [x20, _MVPP2_GMAC_PORT_FIFO_CFG_1_REG@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh5:
	adrp	x8, _MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #58
	bl	_MVPP2_GMAC_TX_FIFO_MIN_TH_MASK
	orr	w0, w21, w0
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x1, x9, x8
	bl	_writel
LBB0_2:
	mov	x0, x19
	bl	_mvpp2_egress_port
	mov	x2, x0
	ldr	x0, [x19, #8]
Lloh8:
	adrp	x8, _MVPP2_TXP_SCHED_PORT_INDEX_REG@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_PORT_INDEX_REG@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	bl	_mvpp2_write
	ldr	x0, [x19, #8]
Lloh11:
	adrp	x8, _MVPP2_TXP_SCHED_CMD_1_REG@GOTPAGE
Lloh12:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_CMD_1_REG@GOTPAGEOFF]
Lloh13:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_mvpp2_write
	ldr	x0, [x19, #8]
Lloh14:
	adrp	x8, _MVPP2_TXP_SCHED_FIXED_PRIO_REG@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_FIXED_PRIO_REG@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_mvpp2_write
Lloh17:
	adrp	x22, _MVPP2_MAX_TXQ@GOTPAGE
Lloh18:
	ldr	x22, [x22, _MVPP2_MAX_TXQ@GOTPAGEOFF]
	ldr	w8, [x22]
	cmp	w8, #1
	b.lt	LBB0_5
; %bb.3:
	mov	w20, #0
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x21, [x19, #8]
	mov	x0, x20
	bl	_MVPP2_TXQ_SCHED_TOKEN_CNTR_REG
	mov	x1, x0
	mov	x0, x21
	mov	w2, #0
	bl	_mvpp2_write
	add	w20, w20, #1
	ldr	w8, [x22]
	cmp	w20, w8
	b.lt	LBB0_4
LBB0_5:
	ldr	x0, [x19, #8]
Lloh19:
	adrp	x8, _MVPP2_TXP_SCHED_PERIOD_REG@GOTPAGE
Lloh20:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_PERIOD_REG@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	ldr	w8, [x0, #8]
Lloh22:
	adrp	x9, _USEC_PER_SEC@GOTPAGE
Lloh23:
	ldr	x9, [x9, _USEC_PER_SEC@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	sdiv	w2, w8, w9
	bl	_mvpp2_write
	ldr	x0, [x19, #8]
Lloh25:
	adrp	x20, _MVPP2_TXP_SCHED_REFILL_REG@GOTPAGE
Lloh26:
	ldr	x20, [x20, _MVPP2_TXP_SCHED_REFILL_REG@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_mvpp2_read
Lloh27:
	adrp	x8, _MVPP2_TXP_REFILL_PERIOD_ALL_MASK@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MVPP2_TXP_REFILL_PERIOD_ALL_MASK@GOTPAGEOFF]
Lloh29:
	ldr	w8, [x8]
	bic	w21, w0, w8
	mov	w0, #1
	bl	_MVPP2_TXP_REFILL_PERIOD_MASK
	orr	w8, w21, w0
Lloh30:
	adrp	x9, _MVPP2_TXP_REFILL_TOKENS_ALL_MASK@GOTPAGE
Lloh31:
	ldr	x9, [x9, _MVPP2_TXP_REFILL_TOKENS_ALL_MASK@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	orr	w2, w8, w9
	ldr	x0, [x19, #8]
	ldr	w1, [x20]
	bl	_mvpp2_write
Lloh33:
	adrp	x8, _MVPP2_TXP_TOKEN_SIZE_MAX@GOTPAGE
Lloh34:
	ldr	x8, [x8, _MVPP2_TXP_TOKEN_SIZE_MAX@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	ldr	x0, [x19, #8]
Lloh36:
	adrp	x8, _MVPP2_TXP_SCHED_TOKEN_SIZE_REG@GOTPAGE
Lloh37:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_TOKEN_SIZE_REG@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	bl	_mvpp2_write
	ldr	x20, [x19, #8]
	ldr	w0, [x19, #24]
	bl	_MVPP2_RX_CTRL_REG
	mov	x21, x0
Lloh39:
	adrp	x8, _MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK@GOTPAGE
Lloh40:
	ldr	x8, [x8, _MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK@GOTPAGEOFF]
Lloh41:
	ldr	w22, [x8]
	mov	w0, #256
	bl	_MVPP2_RX_LOW_LATENCY_PKT_SIZE
	orr	w2, w0, w22
	mov	x0, x20
	mov	x1, x21
	bl	_mvpp2_write
	ldr	w8, [x19]
	cmp	w8, #1
	b.lt	LBB0_8
; %bb.6:
	mov	x23, #0
Lloh42:
	adrp	x24, _MVPP2_SNOOP_PKT_SIZE_MASK@GOTPAGE
Lloh43:
	ldr	x24, [x24, _MVPP2_SNOOP_PKT_SIZE_MASK@GOTPAGEOFF]
Lloh44:
	adrp	x25, _MVPP2_SNOOP_BUF_HDR_MASK@GOTPAGE
Lloh45:
	ldr	x25, [x25, _MVPP2_SNOOP_BUF_HDR_MASK@GOTPAGEOFF]
LBB0_7:                                 ; =>This Inner Loop Header: Depth=1
	ldp	x20, x8, [x19, #8]
	ldr	x8, [x8, x23, lsl #3]
	ldr	w21, [x8]
	mov	x0, x21
	bl	_MVPP2_RXQ_CONFIG_REG
	mov	x1, x0
	mov	x0, x20
	bl	_mvpp2_read
	ldr	w8, [x24]
	ldr	w9, [x25]
	orr	w8, w8, w0
	orr	w20, w8, w9
	ldr	x22, [x19, #8]
	mov	x0, x21
	bl	_MVPP2_RXQ_CONFIG_REG
	mov	x1, x0
	mov	x0, x22
	mov	x2, x20
	bl	_mvpp2_write
	add	x23, x23, #1
	ldrsw	x8, [x19]
	cmp	x23, x8
	b.lt	LBB0_7
LBB0_8:
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_mvpp2_interrupts_disable
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh42, Lloh43
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP21,8,3                     ; @MVPP21
	.comm	_MVPP2_GMAC_PORT_FIFO_CFG_1_REG,8,3 ; @MVPP2_GMAC_PORT_FIFO_CFG_1_REG
	.comm	_MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK,4,2 ; @MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK
	.comm	_MVPP2_TXP_SCHED_PORT_INDEX_REG,4,2 ; @MVPP2_TXP_SCHED_PORT_INDEX_REG
	.comm	_MVPP2_TXP_SCHED_CMD_1_REG,4,2  ; @MVPP2_TXP_SCHED_CMD_1_REG
	.comm	_MVPP2_TXP_SCHED_FIXED_PRIO_REG,4,2 ; @MVPP2_TXP_SCHED_FIXED_PRIO_REG
	.comm	_MVPP2_MAX_TXQ,4,2              ; @MVPP2_MAX_TXQ
	.comm	_MVPP2_TXP_SCHED_PERIOD_REG,4,2 ; @MVPP2_TXP_SCHED_PERIOD_REG
	.comm	_USEC_PER_SEC,4,2               ; @USEC_PER_SEC
	.comm	_MVPP2_TXP_SCHED_REFILL_REG,4,2 ; @MVPP2_TXP_SCHED_REFILL_REG
	.comm	_MVPP2_TXP_REFILL_PERIOD_ALL_MASK,4,2 ; @MVPP2_TXP_REFILL_PERIOD_ALL_MASK
	.comm	_MVPP2_TXP_REFILL_TOKENS_ALL_MASK,4,2 ; @MVPP2_TXP_REFILL_TOKENS_ALL_MASK
	.comm	_MVPP2_TXP_TOKEN_SIZE_MAX,4,2   ; @MVPP2_TXP_TOKEN_SIZE_MAX
	.comm	_MVPP2_TXP_SCHED_TOKEN_SIZE_REG,4,2 ; @MVPP2_TXP_SCHED_TOKEN_SIZE_REG
	.comm	_MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK,4,2 ; @MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK
	.comm	_MVPP2_SNOOP_PKT_SIZE_MASK,4,2  ; @MVPP2_SNOOP_PKT_SIZE_MASK
	.comm	_MVPP2_SNOOP_BUF_HDR_MASK,4,2   ; @MVPP2_SNOOP_BUF_HDR_MASK
	.no_dead_strip	_mvpp2_defaults_set
.subsections_via_symbols
