	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function pcie_phy_36mhz_mode_setup
_pcie_phy_36mhz_mode_setup:             ## @pcie_phy_36mhz_mode_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_phy_get_drvdata
	movq	%rax, %r12
	movl	(%rax), %edi
	movq	_PCIE_PHY_PLL_CTRL3@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r12), %edi
	movl	(%rbx), %esi
	movq	_PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_CTRL2@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	_PCIE_PHY_PLL_CTRL2_PLL_SDM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r12), %edi
	movl	(%r13), %esi
	movq	_PCIE_PHY_PLL_CTRL2_CONST_SDM_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r12), %r14d
	movq	_PCIE_PHY_PLL_A_CTRL3@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movq	_PCIE_PHY_PLL_A_CTRL3_MMD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_A_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	xorl	%ecx, %ecx
	callq	_regmap_update_bits
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$14564, %edx                    ## imm = 0x38E4
	callq	_regmap_write
	movl	(%r12), %r15d
	movl	(%r13), %r14d
	movq	_PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	%ebx, %edi
	movl	$238, %esi
	callq	_FIELD_PREP
	movl	%r15d, %edi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_CTRL7@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$2, %edx
	callq	_regmap_write
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_CTRL6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$14852, %edx                    ## imm = 0x3A04
	callq	_regmap_write
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_CTRL5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$64227, %edx                    ## imm = 0xFAE3
	callq	_regmap_write
	movl	(%r12), %edi
	movq	_PCIE_PHY_PLL_CTRL4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$7026, %edx                     ## imm = 0x1B72
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_regmap_write                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_PHY_PLL_CTRL3,4,2         ## @PCIE_PHY_PLL_CTRL3
	.comm	_PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN,4,2 ## @PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN
	.comm	_PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK,4,2 ## @PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK
	.comm	_PCIE_PHY_PLL_CTRL2,4,2         ## @PCIE_PHY_PLL_CTRL2
	.comm	_PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,4,2 ## @PCIE_PHY_PLL_CTRL2_PLL_SDM_EN
	.comm	_PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,4,2 ## @PCIE_PHY_PLL_CTRL2_CONST_SDM_EN
	.comm	_PCIE_PHY_PLL_A_CTRL3,4,2       ## @PCIE_PHY_PLL_A_CTRL3
	.comm	_PCIE_PHY_PLL_A_CTRL3_MMD_MASK,4,2 ## @PCIE_PHY_PLL_A_CTRL3_MMD_MASK
	.comm	_PCIE_PHY_PLL_A_CTRL2,4,2       ## @PCIE_PHY_PLL_A_CTRL2
	.comm	_PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN,4,2 ## @PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN
	.comm	_PCIE_PHY_PLL_CTRL1,4,2         ## @PCIE_PHY_PLL_CTRL1
	.comm	_PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,4,2 ## @PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK
	.comm	_PCIE_PHY_PLL_CTRL7,4,2         ## @PCIE_PHY_PLL_CTRL7
	.comm	_PCIE_PHY_PLL_CTRL6,4,2         ## @PCIE_PHY_PLL_CTRL6
	.comm	_PCIE_PHY_PLL_CTRL5,4,2         ## @PCIE_PHY_PLL_CTRL5
	.comm	_PCIE_PHY_PLL_CTRL4,4,2         ## @PCIE_PHY_PLL_CTRL4
	.no_dead_strip	_pcie_phy_36mhz_mode_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function pcie_phy_36mhz_mode_setup
_pcie_phy_36mhz_mode_setup:             ; @pcie_phy_36mhz_mode_setup
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	bl	_phy_get_drvdata
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x20, _PCIE_PHY_PLL_CTRL3@GOTPAGE
Lloh1:
	ldr	x20, [x20, _PCIE_PHY_PLL_CTRL3@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh2:
	adrp	x8, _PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN@GOTPAGE
Lloh3:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN@GOTPAGEOFF]
Lloh4:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x20]
Lloh5:
	adrp	x8, _PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh8:
	adrp	x23, _PCIE_PHY_PLL_CTRL2@GOTPAGE
Lloh9:
	ldr	x23, [x23, _PCIE_PHY_PLL_CTRL2@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh10:
	adrp	x8, _PCIE_PHY_PLL_CTRL2_PLL_SDM_EN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL2_PLL_SDM_EN@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w0, [x19]
	ldr	w1, [x23]
Lloh13:
	adrp	x8, _PCIE_PHY_PLL_CTRL2_CONST_SDM_EN@GOTPAGE
Lloh14:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL2_CONST_SDM_EN@GOTPAGEOFF]
Lloh15:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w20, [x19]
Lloh16:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL3@GOTPAGE
Lloh17:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL3@GOTPAGEOFF]
Lloh18:
	ldr	w21, [x8]
Lloh19:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL3_MMD_MASK@GOTPAGE
Lloh20:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL3_MMD_MASK@GOTPAGEOFF]
Lloh21:
	ldr	w22, [x8]
	mov	x0, x22
	mov	w1, #1
	bl	_FIELD_PREP
	mov	x3, x0
	mov	x0, x20
	mov	x1, x21
	mov	x2, x22
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh22:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL2@GOTPAGE
Lloh23:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL2@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
Lloh25:
	adrp	x8, _PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN@GOTPAGE
Lloh26:
	ldr	x8, [x8, _PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN@GOTPAGEOFF]
Lloh27:
	ldr	w2, [x8]
	mov	w3, #0
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh28:
	adrp	x8, _PCIE_PHY_PLL_CTRL1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL1@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	mov	w2, #14564
	bl	_regmap_write
	ldr	w20, [x19]
	ldr	w21, [x23]
Lloh31:
	adrp	x8, _PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK@GOTPAGEOFF]
Lloh33:
	ldr	w22, [x8]
	mov	x0, x22
	mov	w1, #238
	bl	_FIELD_PREP
	mov	x3, x0
	mov	x0, x20
	mov	x1, x21
	mov	x2, x22
	bl	_regmap_update_bits
	ldr	w0, [x19]
Lloh34:
	adrp	x8, _PCIE_PHY_PLL_CTRL7@GOTPAGE
Lloh35:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL7@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	mov	w2, #2
	bl	_regmap_write
	ldr	w0, [x19]
Lloh37:
	adrp	x8, _PCIE_PHY_PLL_CTRL6@GOTPAGE
Lloh38:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL6@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	w2, #14852
	bl	_regmap_write
	ldr	w0, [x19]
Lloh40:
	adrp	x8, _PCIE_PHY_PLL_CTRL5@GOTPAGE
Lloh41:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL5@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
	mov	w2, #64227
	bl	_regmap_write
	ldr	w0, [x19]
Lloh43:
	adrp	x8, _PCIE_PHY_PLL_CTRL4@GOTPAGE
Lloh44:
	ldr	x8, [x8, _PCIE_PHY_PLL_CTRL4@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
	mov	w2, #7026
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_regmap_write
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_PHY_PLL_CTRL3,4,2         ; @PCIE_PHY_PLL_CTRL3
	.comm	_PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN,4,2 ; @PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN
	.comm	_PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK,4,2 ; @PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK
	.comm	_PCIE_PHY_PLL_CTRL2,4,2         ; @PCIE_PHY_PLL_CTRL2
	.comm	_PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,4,2 ; @PCIE_PHY_PLL_CTRL2_PLL_SDM_EN
	.comm	_PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,4,2 ; @PCIE_PHY_PLL_CTRL2_CONST_SDM_EN
	.comm	_PCIE_PHY_PLL_A_CTRL3,4,2       ; @PCIE_PHY_PLL_A_CTRL3
	.comm	_PCIE_PHY_PLL_A_CTRL3_MMD_MASK,4,2 ; @PCIE_PHY_PLL_A_CTRL3_MMD_MASK
	.comm	_PCIE_PHY_PLL_A_CTRL2,4,2       ; @PCIE_PHY_PLL_A_CTRL2
	.comm	_PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN,4,2 ; @PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN
	.comm	_PCIE_PHY_PLL_CTRL1,4,2         ; @PCIE_PHY_PLL_CTRL1
	.comm	_PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,4,2 ; @PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK
	.comm	_PCIE_PHY_PLL_CTRL7,4,2         ; @PCIE_PHY_PLL_CTRL7
	.comm	_PCIE_PHY_PLL_CTRL6,4,2         ; @PCIE_PHY_PLL_CTRL6
	.comm	_PCIE_PHY_PLL_CTRL5,4,2         ; @PCIE_PHY_PLL_CTRL5
	.comm	_PCIE_PHY_PLL_CTRL4,4,2         ; @PCIE_PHY_PLL_CTRL4
	.no_dead_strip	_pcie_phy_36mhz_mode_setup
.subsections_via_symbols
