	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function sun6i_dphy_power_on
_sun6i_dphy_power_on:                   ## @sun6i_dphy_power_on
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	callq	_phy_get_drvdata
	movq	%rax, %r13
	movq	8(%rax), %rdi
	decq	%rdi
	xorl	%esi, %esi
	callq	_GENMASK
	movl	%eax, -44(%rbp)                 ## 4-byte Spill
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_TX_CTL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movl	(%r13), %r14d
	movq	_SUN6I_DPHY_TX_TIME0_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$14, %edi
	callq	_SUN6I_DPHY_TX_TIME0_LP_CLK_DIV
	movl	%eax, %ebx
	movl	$6, %edi
	callq	_SUN6I_DPHY_TX_TIME0_HS_PREPARE
	orl	%eax, %ebx
	movl	$10, %edi
	callq	_SUN6I_DPHY_TX_TIME0_HS_TRAIL
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r13), %r15d
	movq	_SUN6I_DPHY_TX_TIME1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	$7, %edi
	callq	_SUN6I_DPHY_TX_TIME1_CLK_PREPARE
	movl	%eax, %r14d
	movl	$50, %edi
	callq	_SUN6I_DPHY_TX_TIME1_CLK_ZERO
	orl	%eax, %r14d
	movl	$3, %edi
	callq	_SUN6I_DPHY_TX_TIME1_CLK_PRE
	movl	%eax, %ebx
	movl	$10, %edi
	callq	_SUN6I_DPHY_TX_TIME1_CLK_POST
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movl	%r15d, %edi
	movl	%r12d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r13), %r14d
	movq	_SUN6I_DPHY_TX_TIME2_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	$30, %edi
	callq	_SUN6I_DPHY_TX_TIME2_CLK_TRAIL
	movl	%r14d, %edi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_regmap_write
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_TX_TIME3_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	xorl	%edx, %edx
	callq	_regmap_write
	movl	(%r13), %r14d
	movq	_SUN6I_DPHY_TX_TIME4_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$3, %edi
	callq	_SUN6I_DPHY_TX_TIME4_HS_TX_ANA0
	movl	%eax, %ebx
	movl	$3, %edi
	callq	_SUN6I_DPHY_TX_TIME4_HS_TX_ANA1
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r13), %r14d
	movq	_SUN6I_DPHY_GCTL_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	8(%r13), %rdi
	callq	_SUN6I_DPHY_GCTL_LANE_NUM
	movq	_SUN6I_DPHY_GCTL_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%r14d, %edi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_regmap_write
	movl	(%r13), %eax
	movl	%eax, -48(%rbp)                 ## 4-byte Spill
	movq	_SUN6I_DPHY_ANA0_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_SUN6I_DPHY_ANA0_REG_PWS@GOTPCREL(%rip), %rax
	movq	_SUN6I_DPHY_ANA0_REG_DMPC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %r12d
	orl	(%rax), %r12d
	movl	$7, %edi
	callq	_SUN6I_DPHY_ANA0_REG_SLV
	movl	%eax, %ebx
	movl	-44(%rbp), %r15d                ## 4-byte Reload
	movl	%r15d, %edi
	callq	_SUN6I_DPHY_ANA0_REG_DMPD
	orl	%eax, %ebx
	movl	%r15d, %edi
	callq	_SUN6I_DPHY_ANA0_REG_DEN
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movl	-48(%rbp), %edi                 ## 4-byte Reload
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r13), %r14d
	movq	_SUN6I_DPHY_ANA1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %r15d
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA1_REG_CSMPS
	movl	%eax, %ebx
	movl	$7, %edi
	callq	_SUN6I_DPHY_ANA1_REG_SVTT
	orl	%eax, %ebx
	movl	%r14d, %edi
	movl	%r15d, %esi
	movl	%ebx, %edx
	callq	_regmap_write
	movl	(%r13), %r15d
	movq	_SUN6I_DPHY_ANA4_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_CKDV
	movl	%eax, %r14d
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_TMSC
	orl	%eax, %r14d
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_TMSD
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_TXDNSC
	orl	%eax, %ebx
	orl	%r14d, %ebx
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_TXDNSD
	movl	%eax, %r14d
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_TXPUSC
	orl	%eax, %r14d
	movl	$1, %edi
	callq	_SUN6I_DPHY_ANA4_REG_TXPUSD
	orl	%eax, %r14d
	orl	%ebx, %r14d
	movq	_SUN6I_DPHY_ANA4_REG_DMPLVC@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_SUN6I_DPHY_ANA4_REG_DMPLVD
	orl	%eax, %r14d
	movl	%r15d, %edi
	movl	%r12d, %esi
	movl	%r14d, %edx
	callq	_regmap_write
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_ANA2_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN6I_DPHY_ANA2_REG_ENIB@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_regmap_write
	movl	$5, %edi
	callq	_udelay
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_ANA3_REG@GOTPCREL(%rip), %rbx
	movq	_SUN6I_DPHY_ANA3_EN_LDOR@GOTPCREL(%rip), %rax
	movq	_SUN6I_DPHY_ANA3_EN_LDOC@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movl	(%rbx), %esi
	movq	_SUN6I_DPHY_ANA3_EN_LDOD@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	callq	_regmap_write
	movl	$1, %edi
	callq	_udelay
	movl	(%r13), %r15d
	movl	(%rbx), %r14d
	movq	_SUN6I_DPHY_ANA3_EN_VTTC@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movq	_SUN6I_DPHY_ANA3_EN_VTTD_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	orl	%ebx, %r12d
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_SUN6I_DPHY_ANA3_EN_VTTD
	orl	%eax, %ebx
	movl	%r15d, %edi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_regmap_update_bits
	movl	$1, %edi
	callq	_udelay
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_ANA3_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN6I_DPHY_ANA3_EN_DIV@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$1, %edi
	callq	_udelay
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_ANA2_REG@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_SUN6I_DPHY_ANA2_EN_CK_CPU@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	$1, %edi
	callq	_udelay
	movl	(%r13), %edi
	movq	_SUN6I_DPHY_ANA1_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SUN6I_DPHY_ANA1_REG_VTTMODE@GOTPCREL(%rip), %rax
	movl	(%rax), %ecx
	movl	%ecx, %edx
	callq	_regmap_update_bits
	movl	(%r13), %r15d
	movl	(%rbx), %r14d
	movq	_SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	-44(%rbp), %edi                 ## 4-byte Reload
	callq	_SUN6I_DPHY_ANA2_EN_P2S_CPU
	movl	%r15d, %edi
	movl	%r14d, %esi
	movl	%ebx, %edx
	movl	%eax, %ecx
	callq	_regmap_update_bits
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_SUN6I_DPHY_TX_CTL_REG,4,2      ## @SUN6I_DPHY_TX_CTL_REG
	.comm	_SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT,4,2 ## @SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT
	.comm	_SUN6I_DPHY_TX_TIME0_REG,4,2    ## @SUN6I_DPHY_TX_TIME0_REG
	.comm	_SUN6I_DPHY_TX_TIME1_REG,4,2    ## @SUN6I_DPHY_TX_TIME1_REG
	.comm	_SUN6I_DPHY_TX_TIME2_REG,4,2    ## @SUN6I_DPHY_TX_TIME2_REG
	.comm	_SUN6I_DPHY_TX_TIME3_REG,4,2    ## @SUN6I_DPHY_TX_TIME3_REG
	.comm	_SUN6I_DPHY_TX_TIME4_REG,4,2    ## @SUN6I_DPHY_TX_TIME4_REG
	.comm	_SUN6I_DPHY_GCTL_REG,4,2        ## @SUN6I_DPHY_GCTL_REG
	.comm	_SUN6I_DPHY_GCTL_EN,4,2         ## @SUN6I_DPHY_GCTL_EN
	.comm	_SUN6I_DPHY_ANA0_REG,4,2        ## @SUN6I_DPHY_ANA0_REG
	.comm	_SUN6I_DPHY_ANA0_REG_PWS,4,2    ## @SUN6I_DPHY_ANA0_REG_PWS
	.comm	_SUN6I_DPHY_ANA0_REG_DMPC,4,2   ## @SUN6I_DPHY_ANA0_REG_DMPC
	.comm	_SUN6I_DPHY_ANA1_REG,4,2        ## @SUN6I_DPHY_ANA1_REG
	.comm	_SUN6I_DPHY_ANA4_REG,4,2        ## @SUN6I_DPHY_ANA4_REG
	.comm	_SUN6I_DPHY_ANA4_REG_DMPLVC,4,2 ## @SUN6I_DPHY_ANA4_REG_DMPLVC
	.comm	_SUN6I_DPHY_ANA2_REG,4,2        ## @SUN6I_DPHY_ANA2_REG
	.comm	_SUN6I_DPHY_ANA2_REG_ENIB,4,2   ## @SUN6I_DPHY_ANA2_REG_ENIB
	.comm	_SUN6I_DPHY_ANA3_REG,4,2        ## @SUN6I_DPHY_ANA3_REG
	.comm	_SUN6I_DPHY_ANA3_EN_LDOR,4,2    ## @SUN6I_DPHY_ANA3_EN_LDOR
	.comm	_SUN6I_DPHY_ANA3_EN_LDOC,4,2    ## @SUN6I_DPHY_ANA3_EN_LDOC
	.comm	_SUN6I_DPHY_ANA3_EN_LDOD,4,2    ## @SUN6I_DPHY_ANA3_EN_LDOD
	.comm	_SUN6I_DPHY_ANA3_EN_VTTC,4,2    ## @SUN6I_DPHY_ANA3_EN_VTTC
	.comm	_SUN6I_DPHY_ANA3_EN_VTTD_MASK,4,2 ## @SUN6I_DPHY_ANA3_EN_VTTD_MASK
	.comm	_SUN6I_DPHY_ANA3_EN_DIV,4,2     ## @SUN6I_DPHY_ANA3_EN_DIV
	.comm	_SUN6I_DPHY_ANA2_EN_CK_CPU,4,2  ## @SUN6I_DPHY_ANA2_EN_CK_CPU
	.comm	_SUN6I_DPHY_ANA1_REG_VTTMODE,4,2 ## @SUN6I_DPHY_ANA1_REG_VTTMODE
	.comm	_SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,4,2 ## @SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK
	.no_dead_strip	_sun6i_dphy_power_on
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function sun6i_dphy_power_on
_sun6i_dphy_power_on:                   ; @sun6i_dphy_power_on
	.cfi_startproc
; %bb.0:
	stp	x28, x27, [sp, #-96]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	bl	_phy_get_drvdata
	mov	x19, x0
	ldr	x8, [x0, #8]
	sub	x0, x8, #1
	mov	w1, #0
	bl	_GENMASK
	mov	x20, x0
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _SUN6I_DPHY_TX_CTL_REG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _SUN6I_DPHY_TX_CTL_REG@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
Lloh3:
	adrp	x8, _SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT@GOTPAGE
Lloh4:
	ldr	x8, [x8, _SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	bl	_regmap_write
	ldr	w21, [x19]
Lloh6:
	adrp	x8, _SUN6I_DPHY_TX_TIME0_REG@GOTPAGE
Lloh7:
	ldr	x8, [x8, _SUN6I_DPHY_TX_TIME0_REG@GOTPAGEOFF]
Lloh8:
	ldr	w22, [x8]
	mov	w0, #14
	bl	_SUN6I_DPHY_TX_TIME0_LP_CLK_DIV
	mov	x23, x0
	mov	w0, #6
	bl	_SUN6I_DPHY_TX_TIME0_HS_PREPARE
	orr	w23, w0, w23
	mov	w0, #10
	bl	_SUN6I_DPHY_TX_TIME0_HS_TRAIL
	orr	w2, w23, w0
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w21, [x19]
Lloh9:
	adrp	x8, _SUN6I_DPHY_TX_TIME1_REG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _SUN6I_DPHY_TX_TIME1_REG@GOTPAGEOFF]
Lloh11:
	ldr	w22, [x8]
	mov	w0, #7
	bl	_SUN6I_DPHY_TX_TIME1_CLK_PREPARE
	mov	x23, x0
	mov	w0, #50
	bl	_SUN6I_DPHY_TX_TIME1_CLK_ZERO
	orr	w23, w0, w23
	mov	w0, #3
	bl	_SUN6I_DPHY_TX_TIME1_CLK_PRE
	orr	w23, w23, w0
	mov	w0, #10
	bl	_SUN6I_DPHY_TX_TIME1_CLK_POST
	orr	w2, w23, w0
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w21, [x19]
Lloh12:
	adrp	x8, _SUN6I_DPHY_TX_TIME2_REG@GOTPAGE
Lloh13:
	ldr	x8, [x8, _SUN6I_DPHY_TX_TIME2_REG@GOTPAGEOFF]
Lloh14:
	ldr	w22, [x8]
	mov	w0, #30
	bl	_SUN6I_DPHY_TX_TIME2_CLK_TRAIL
	mov	x2, x0
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w0, [x19]
Lloh15:
	adrp	x8, _SUN6I_DPHY_TX_TIME3_REG@GOTPAGE
Lloh16:
	ldr	x8, [x8, _SUN6I_DPHY_TX_TIME3_REG@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	mov	w2, #0
	bl	_regmap_write
	ldr	w21, [x19]
Lloh18:
	adrp	x8, _SUN6I_DPHY_TX_TIME4_REG@GOTPAGE
Lloh19:
	ldr	x8, [x8, _SUN6I_DPHY_TX_TIME4_REG@GOTPAGEOFF]
Lloh20:
	ldr	w22, [x8]
	mov	w0, #3
	bl	_SUN6I_DPHY_TX_TIME4_HS_TX_ANA0
	mov	x23, x0
	mov	w0, #3
	bl	_SUN6I_DPHY_TX_TIME4_HS_TX_ANA1
	orr	w2, w0, w23
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w21, [x19]
Lloh21:
	adrp	x8, _SUN6I_DPHY_GCTL_REG@GOTPAGE
Lloh22:
	ldr	x8, [x8, _SUN6I_DPHY_GCTL_REG@GOTPAGEOFF]
Lloh23:
	ldr	w22, [x8]
	ldr	x0, [x19, #8]
	bl	_SUN6I_DPHY_GCTL_LANE_NUM
Lloh24:
	adrp	x8, _SUN6I_DPHY_GCTL_EN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SUN6I_DPHY_GCTL_EN@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	orr	w2, w8, w0
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w21, [x19]
Lloh27:
	adrp	x8, _SUN6I_DPHY_ANA0_REG@GOTPAGE
Lloh28:
	ldr	x8, [x8, _SUN6I_DPHY_ANA0_REG@GOTPAGEOFF]
Lloh29:
	adrp	x9, _SUN6I_DPHY_ANA0_REG_PWS@GOTPAGE
Lloh30:
	ldr	x9, [x9, _SUN6I_DPHY_ANA0_REG_PWS@GOTPAGEOFF]
Lloh31:
	ldr	w22, [x8]
Lloh32:
	ldr	w8, [x9]
Lloh33:
	adrp	x9, _SUN6I_DPHY_ANA0_REG_DMPC@GOTPAGE
Lloh34:
	ldr	x9, [x9, _SUN6I_DPHY_ANA0_REG_DMPC@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w23, w9, w8
	mov	w0, #7
	bl	_SUN6I_DPHY_ANA0_REG_SLV
	orr	w23, w23, w0
	mov	x0, x20
	bl	_SUN6I_DPHY_ANA0_REG_DMPD
	orr	w23, w23, w0
	mov	x0, x20
	bl	_SUN6I_DPHY_ANA0_REG_DEN
	orr	w2, w23, w0
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w21, [x19]
Lloh36:
	adrp	x24, _SUN6I_DPHY_ANA1_REG@GOTPAGE
Lloh37:
	ldr	x24, [x24, _SUN6I_DPHY_ANA1_REG@GOTPAGEOFF]
	ldr	w22, [x24]
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA1_REG_CSMPS
	mov	x23, x0
	mov	w0, #7
	bl	_SUN6I_DPHY_ANA1_REG_SVTT
	orr	w2, w0, w23
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w21, [x19]
Lloh38:
	adrp	x8, _SUN6I_DPHY_ANA4_REG@GOTPAGE
Lloh39:
	ldr	x8, [x8, _SUN6I_DPHY_ANA4_REG@GOTPAGEOFF]
Lloh40:
	ldr	w22, [x8]
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_CKDV
	mov	x23, x0
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_TMSC
	orr	w23, w0, w23
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_TMSD
	orr	w23, w23, w0
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_TXDNSC
	orr	w23, w23, w0
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_TXDNSD
	orr	w23, w23, w0
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_TXPUSC
	orr	w23, w23, w0
	mov	w0, #1
	bl	_SUN6I_DPHY_ANA4_REG_TXPUSD
	orr	w8, w23, w0
Lloh41:
	adrp	x9, _SUN6I_DPHY_ANA4_REG_DMPLVC@GOTPAGE
Lloh42:
	ldr	x9, [x9, _SUN6I_DPHY_ANA4_REG_DMPLVC@GOTPAGEOFF]
Lloh43:
	ldr	w9, [x9]
	orr	w23, w8, w9
	mov	x0, x20
	bl	_SUN6I_DPHY_ANA4_REG_DMPLVD
	orr	w2, w23, w0
	mov	x0, x21
	mov	x1, x22
	bl	_regmap_write
	ldr	w0, [x19]
Lloh44:
	adrp	x25, _SUN6I_DPHY_ANA2_REG@GOTPAGE
Lloh45:
	ldr	x25, [x25, _SUN6I_DPHY_ANA2_REG@GOTPAGEOFF]
	ldr	w1, [x25]
Lloh46:
	adrp	x8, _SUN6I_DPHY_ANA2_REG_ENIB@GOTPAGE
Lloh47:
	ldr	x8, [x8, _SUN6I_DPHY_ANA2_REG_ENIB@GOTPAGEOFF]
Lloh48:
	ldr	w2, [x8]
	bl	_regmap_write
	mov	w0, #5
	bl	_udelay
	ldr	w0, [x19]
Lloh49:
	adrp	x26, _SUN6I_DPHY_ANA3_REG@GOTPAGE
Lloh50:
	ldr	x26, [x26, _SUN6I_DPHY_ANA3_REG@GOTPAGEOFF]
	ldr	w1, [x26]
Lloh51:
	adrp	x8, _SUN6I_DPHY_ANA3_EN_LDOR@GOTPAGE
Lloh52:
	ldr	x8, [x8, _SUN6I_DPHY_ANA3_EN_LDOR@GOTPAGEOFF]
Lloh53:
	ldr	w8, [x8]
Lloh54:
	adrp	x9, _SUN6I_DPHY_ANA3_EN_LDOC@GOTPAGE
Lloh55:
	ldr	x9, [x9, _SUN6I_DPHY_ANA3_EN_LDOC@GOTPAGEOFF]
Lloh56:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh57:
	adrp	x9, _SUN6I_DPHY_ANA3_EN_LDOD@GOTPAGE
Lloh58:
	ldr	x9, [x9, _SUN6I_DPHY_ANA3_EN_LDOD@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w2, w8, w9
	bl	_regmap_write
	mov	w0, #1
	bl	_udelay
	ldr	w21, [x19]
Lloh60:
	adrp	x8, _SUN6I_DPHY_ANA3_EN_VTTC@GOTPAGE
Lloh61:
	ldr	x8, [x8, _SUN6I_DPHY_ANA3_EN_VTTC@GOTPAGEOFF]
	ldr	w22, [x26]
Lloh62:
	ldr	w27, [x8]
Lloh63:
	adrp	x8, _SUN6I_DPHY_ANA3_EN_VTTD_MASK@GOTPAGE
Lloh64:
	ldr	x8, [x8, _SUN6I_DPHY_ANA3_EN_VTTD_MASK@GOTPAGEOFF]
Lloh65:
	ldr	w8, [x8]
	orr	w23, w8, w27
	mov	x0, x20
	bl	_SUN6I_DPHY_ANA3_EN_VTTD
	orr	w3, w0, w27
	mov	x0, x21
	mov	x1, x22
	mov	x2, x23
	bl	_regmap_update_bits
	mov	w0, #1
	bl	_udelay
	ldr	w0, [x19]
	ldr	w1, [x26]
Lloh66:
	adrp	x8, _SUN6I_DPHY_ANA3_EN_DIV@GOTPAGE
Lloh67:
	ldr	x8, [x8, _SUN6I_DPHY_ANA3_EN_DIV@GOTPAGEOFF]
Lloh68:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #1
	bl	_udelay
	ldr	w0, [x19]
	ldr	w1, [x25]
Lloh69:
	adrp	x8, _SUN6I_DPHY_ANA2_EN_CK_CPU@GOTPAGE
Lloh70:
	ldr	x8, [x8, _SUN6I_DPHY_ANA2_EN_CK_CPU@GOTPAGEOFF]
Lloh71:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	mov	w0, #1
	bl	_udelay
	ldr	w0, [x19]
	ldr	w1, [x24]
Lloh72:
	adrp	x8, _SUN6I_DPHY_ANA1_REG_VTTMODE@GOTPAGE
Lloh73:
	ldr	x8, [x8, _SUN6I_DPHY_ANA1_REG_VTTMODE@GOTPAGEOFF]
Lloh74:
	ldr	w2, [x8]
	mov	x3, x2
	bl	_regmap_update_bits
	ldr	w19, [x19]
	ldr	w21, [x25]
Lloh75:
	adrp	x8, _SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK@GOTPAGE
Lloh76:
	ldr	x8, [x8, _SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK@GOTPAGEOFF]
Lloh77:
	ldr	w22, [x8]
	mov	x0, x20
	bl	_SUN6I_DPHY_ANA2_EN_P2S_CPU
	mov	x3, x0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_regmap_update_bits
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp], #96             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh38, Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh29, Lloh30, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh31
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_SUN6I_DPHY_TX_CTL_REG,4,2      ; @SUN6I_DPHY_TX_CTL_REG
	.comm	_SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT,4,2 ; @SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT
	.comm	_SUN6I_DPHY_TX_TIME0_REG,4,2    ; @SUN6I_DPHY_TX_TIME0_REG
	.comm	_SUN6I_DPHY_TX_TIME1_REG,4,2    ; @SUN6I_DPHY_TX_TIME1_REG
	.comm	_SUN6I_DPHY_TX_TIME2_REG,4,2    ; @SUN6I_DPHY_TX_TIME2_REG
	.comm	_SUN6I_DPHY_TX_TIME3_REG,4,2    ; @SUN6I_DPHY_TX_TIME3_REG
	.comm	_SUN6I_DPHY_TX_TIME4_REG,4,2    ; @SUN6I_DPHY_TX_TIME4_REG
	.comm	_SUN6I_DPHY_GCTL_REG,4,2        ; @SUN6I_DPHY_GCTL_REG
	.comm	_SUN6I_DPHY_GCTL_EN,4,2         ; @SUN6I_DPHY_GCTL_EN
	.comm	_SUN6I_DPHY_ANA0_REG,4,2        ; @SUN6I_DPHY_ANA0_REG
	.comm	_SUN6I_DPHY_ANA0_REG_PWS,4,2    ; @SUN6I_DPHY_ANA0_REG_PWS
	.comm	_SUN6I_DPHY_ANA0_REG_DMPC,4,2   ; @SUN6I_DPHY_ANA0_REG_DMPC
	.comm	_SUN6I_DPHY_ANA1_REG,4,2        ; @SUN6I_DPHY_ANA1_REG
	.comm	_SUN6I_DPHY_ANA4_REG,4,2        ; @SUN6I_DPHY_ANA4_REG
	.comm	_SUN6I_DPHY_ANA4_REG_DMPLVC,4,2 ; @SUN6I_DPHY_ANA4_REG_DMPLVC
	.comm	_SUN6I_DPHY_ANA2_REG,4,2        ; @SUN6I_DPHY_ANA2_REG
	.comm	_SUN6I_DPHY_ANA2_REG_ENIB,4,2   ; @SUN6I_DPHY_ANA2_REG_ENIB
	.comm	_SUN6I_DPHY_ANA3_REG,4,2        ; @SUN6I_DPHY_ANA3_REG
	.comm	_SUN6I_DPHY_ANA3_EN_LDOR,4,2    ; @SUN6I_DPHY_ANA3_EN_LDOR
	.comm	_SUN6I_DPHY_ANA3_EN_LDOC,4,2    ; @SUN6I_DPHY_ANA3_EN_LDOC
	.comm	_SUN6I_DPHY_ANA3_EN_LDOD,4,2    ; @SUN6I_DPHY_ANA3_EN_LDOD
	.comm	_SUN6I_DPHY_ANA3_EN_VTTC,4,2    ; @SUN6I_DPHY_ANA3_EN_VTTC
	.comm	_SUN6I_DPHY_ANA3_EN_VTTD_MASK,4,2 ; @SUN6I_DPHY_ANA3_EN_VTTD_MASK
	.comm	_SUN6I_DPHY_ANA3_EN_DIV,4,2     ; @SUN6I_DPHY_ANA3_EN_DIV
	.comm	_SUN6I_DPHY_ANA2_EN_CK_CPU,4,2  ; @SUN6I_DPHY_ANA2_EN_CK_CPU
	.comm	_SUN6I_DPHY_ANA1_REG_VTTMODE,4,2 ; @SUN6I_DPHY_ANA1_REG_VTTMODE
	.comm	_SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,4,2 ; @SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK
	.no_dead_strip	_sun6i_dphy_power_on
.subsections_via_symbols
