	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function iwl_pcie_apm_lp_xtal_enable
_iwl_pcie_apm_lp_xtal_enable:           ## @iwl_pcie_apm_lp_xtal_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_CSR_GP_CNTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	movq	_CSR_GP_CNTRL_REG_FLAG_XTAL_ON@GOTPCREL(%rip), %r13
	movl	(%r13), %edx
	callq	___iwl_trans_pcie_set_bit
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_sw_reset
	movq	(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_iwl_finish_nic_init
	movl	%eax, %edi
	callq	_WARN_ON
	testq	%rax, %rax
	je	LBB0_2
## %bb.1:
	movl	(%r12), %esi
	movl	(%r13), %edx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	___iwl_trans_pcie_clear_bit     ## TAILCALL
LBB0_2:
	movq	_APMG_PCIDEV_STT_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_APMG_PCIDEV_STT_VAL_PERSIST_DIS@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_clear_bits_prph
	movq	_SHR_APMG_XTAL_CFG_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_read_shr
	movl	%eax, %r14d
	movl	(%r15), %esi
	movq	_SHR_APMG_XTAL_CFG_XTAL_ON_REQ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	orl	%r14d, %edx
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_write_shr
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_sw_reset
	movq	_SHR_APMG_GP1_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_read_shr
	movq	_SHR_APMG_GP1_WF_XTAL_LP_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %esi
	movq	_SHR_APMG_GP1_CHICKEN_BIT_SELECT@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_iwl_trans_pcie_write_shr
	movq	_SHR_APMG_DL_CFG_REG@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_read_shr
	movl	(%r15), %esi
	movq	_SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movq	%rbx, %rdi
	callq	_iwl_trans_pcie_write_shr
	movq	_CSR_HW_IF_CONFIG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_HW_IF_CONFIG_REG_PERSIST_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_iwl_set_bit
	movl	(%r12), %r15d
	movq	(%rbx), %rax
	movq	(%rax), %rax
	movl	(%rax), %edi
	callq	_BIT
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	callq	_iwl_clear_bit
	movq	_CSR_MONITOR_CFG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_MONITOR_XTAL_RESOURCES@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	___iwl_trans_pcie_set_bit
	movl	(%r12), %esi
	movl	(%r13), %edx
	movq	%rbx, %rdi
	callq	___iwl_trans_pcie_clear_bit
	movl	$10, %edi
	callq	_udelay
	movq	_SHR_APMG_XTAL_CFG_REG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_SHR_APMG_XTAL_CFG_XTAL_ON_REQ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	notl	%edx
	andl	%r14d, %edx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_iwl_trans_pcie_write_shr       ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_CSR_GP_CNTRL,4,2               ## @CSR_GP_CNTRL
	.comm	_CSR_GP_CNTRL_REG_FLAG_XTAL_ON,4,2 ## @CSR_GP_CNTRL_REG_FLAG_XTAL_ON
	.comm	_APMG_PCIDEV_STT_REG,4,2        ## @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_PERSIST_DIS,4,2 ## @APMG_PCIDEV_STT_VAL_PERSIST_DIS
	.comm	_SHR_APMG_XTAL_CFG_REG,4,2      ## @SHR_APMG_XTAL_CFG_REG
	.comm	_SHR_APMG_XTAL_CFG_XTAL_ON_REQ,4,2 ## @SHR_APMG_XTAL_CFG_XTAL_ON_REQ
	.comm	_SHR_APMG_GP1_REG,4,2           ## @SHR_APMG_GP1_REG
	.comm	_SHR_APMG_GP1_WF_XTAL_LP_EN,4,2 ## @SHR_APMG_GP1_WF_XTAL_LP_EN
	.comm	_SHR_APMG_GP1_CHICKEN_BIT_SELECT,4,2 ## @SHR_APMG_GP1_CHICKEN_BIT_SELECT
	.comm	_SHR_APMG_DL_CFG_REG,4,2        ## @SHR_APMG_DL_CFG_REG
	.comm	_SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP,4,2 ## @SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
	.comm	_CSR_HW_IF_CONFIG_REG,4,2       ## @CSR_HW_IF_CONFIG_REG
	.comm	_CSR_HW_IF_CONFIG_REG_PERSIST_MODE,4,2 ## @CSR_HW_IF_CONFIG_REG_PERSIST_MODE
	.comm	_CSR_MONITOR_CFG_REG,4,2        ## @CSR_MONITOR_CFG_REG
	.comm	_CSR_MONITOR_XTAL_RESOURCES,4,2 ## @CSR_MONITOR_XTAL_RESOURCES
	.no_dead_strip	_iwl_pcie_apm_lp_xtal_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function iwl_pcie_apm_lp_xtal_enable
_iwl_pcie_apm_lp_xtal_enable:           ; @iwl_pcie_apm_lp_xtal_enable
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x22, _CSR_GP_CNTRL@GOTPAGE
Lloh1:
	ldr	x22, [x22, _CSR_GP_CNTRL@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh2:
	adrp	x23, _CSR_GP_CNTRL_REG_FLAG_XTAL_ON@GOTPAGE
Lloh3:
	ldr	x23, [x23, _CSR_GP_CNTRL_REG_FLAG_XTAL_ON@GOTPAGEOFF]
	ldr	w2, [x23]
	bl	___iwl_trans_pcie_set_bit
	mov	x0, x19
	bl	_iwl_trans_pcie_sw_reset
	ldr	x1, [x19]
	mov	x0, x19
	bl	_iwl_finish_nic_init
	bl	_WARN_ON
	cbz	x0, LBB0_2
; %bb.1:
	ldr	w1, [x22]
	ldr	w2, [x23]
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	___iwl_trans_pcie_clear_bit
LBB0_2:
Lloh4:
	adrp	x8, _APMG_PCIDEV_STT_REG@GOTPAGE
Lloh5:
	ldr	x8, [x8, _APMG_PCIDEV_STT_REG@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
Lloh7:
	adrp	x8, _APMG_PCIDEV_STT_VAL_PERSIST_DIS@GOTPAGE
Lloh8:
	ldr	x8, [x8, _APMG_PCIDEV_STT_VAL_PERSIST_DIS@GOTPAGEOFF]
Lloh9:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_clear_bits_prph
Lloh10:
	adrp	x24, _SHR_APMG_XTAL_CFG_REG@GOTPAGE
Lloh11:
	ldr	x24, [x24, _SHR_APMG_XTAL_CFG_REG@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_iwl_trans_pcie_read_shr
	mov	x20, x0
	ldr	w1, [x24]
Lloh12:
	adrp	x25, _SHR_APMG_XTAL_CFG_XTAL_ON_REQ@GOTPAGE
Lloh13:
	ldr	x25, [x25, _SHR_APMG_XTAL_CFG_XTAL_ON_REQ@GOTPAGEOFF]
	ldr	w8, [x25]
	orr	w2, w8, w0
	mov	x0, x19
	bl	_iwl_trans_pcie_write_shr
	mov	x0, x19
	bl	_iwl_trans_pcie_sw_reset
Lloh14:
	adrp	x21, _SHR_APMG_GP1_REG@GOTPAGE
Lloh15:
	ldr	x21, [x21, _SHR_APMG_GP1_REG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_iwl_trans_pcie_read_shr
	ldr	w1, [x21]
Lloh16:
	adrp	x8, _SHR_APMG_GP1_WF_XTAL_LP_EN@GOTPAGE
Lloh17:
	ldr	x8, [x8, _SHR_APMG_GP1_WF_XTAL_LP_EN@GOTPAGEOFF]
Lloh18:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh19:
	adrp	x9, _SHR_APMG_GP1_CHICKEN_BIT_SELECT@GOTPAGE
Lloh20:
	ldr	x9, [x9, _SHR_APMG_GP1_CHICKEN_BIT_SELECT@GOTPAGEOFF]
Lloh21:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_iwl_trans_pcie_write_shr
Lloh22:
	adrp	x21, _SHR_APMG_DL_CFG_REG@GOTPAGE
Lloh23:
	ldr	x21, [x21, _SHR_APMG_DL_CFG_REG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_iwl_trans_pcie_read_shr
	ldr	w1, [x21]
Lloh24:
	adrp	x8, _SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP@GOTPAGE
Lloh25:
	ldr	x8, [x8, _SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	bic	w2, w0, w8
	mov	x0, x19
	bl	_iwl_trans_pcie_write_shr
Lloh27:
	adrp	x8, _CSR_HW_IF_CONFIG_REG@GOTPAGE
Lloh28:
	ldr	x8, [x8, _CSR_HW_IF_CONFIG_REG@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
Lloh30:
	adrp	x8, _CSR_HW_IF_CONFIG_REG_PERSIST_MODE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CSR_HW_IF_CONFIG_REG_PERSIST_MODE@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_iwl_set_bit
	ldr	w21, [x22]
	ldr	x8, [x19]
	ldr	x8, [x8]
	ldr	w0, [x8]
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_iwl_clear_bit
Lloh33:
	adrp	x8, _CSR_MONITOR_CFG_REG@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CSR_MONITOR_CFG_REG@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
Lloh36:
	adrp	x8, _CSR_MONITOR_XTAL_RESOURCES@GOTPAGE
Lloh37:
	ldr	x8, [x8, _CSR_MONITOR_XTAL_RESOURCES@GOTPAGEOFF]
Lloh38:
	ldr	w2, [x8]
	mov	x0, x19
	bl	___iwl_trans_pcie_set_bit
	ldr	w1, [x22]
	ldr	w2, [x23]
	mov	x0, x19
	bl	___iwl_trans_pcie_clear_bit
	mov	w0, #10
	bl	_udelay
	ldr	w1, [x24]
	ldr	w8, [x25]
	bic	w2, w20, w8
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_iwl_trans_pcie_write_shr
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.cfi_endproc
                                        ; -- End function
	.comm	_CSR_GP_CNTRL,4,2               ; @CSR_GP_CNTRL
	.comm	_CSR_GP_CNTRL_REG_FLAG_XTAL_ON,4,2 ; @CSR_GP_CNTRL_REG_FLAG_XTAL_ON
	.comm	_APMG_PCIDEV_STT_REG,4,2        ; @APMG_PCIDEV_STT_REG
	.comm	_APMG_PCIDEV_STT_VAL_PERSIST_DIS,4,2 ; @APMG_PCIDEV_STT_VAL_PERSIST_DIS
	.comm	_SHR_APMG_XTAL_CFG_REG,4,2      ; @SHR_APMG_XTAL_CFG_REG
	.comm	_SHR_APMG_XTAL_CFG_XTAL_ON_REQ,4,2 ; @SHR_APMG_XTAL_CFG_XTAL_ON_REQ
	.comm	_SHR_APMG_GP1_REG,4,2           ; @SHR_APMG_GP1_REG
	.comm	_SHR_APMG_GP1_WF_XTAL_LP_EN,4,2 ; @SHR_APMG_GP1_WF_XTAL_LP_EN
	.comm	_SHR_APMG_GP1_CHICKEN_BIT_SELECT,4,2 ; @SHR_APMG_GP1_CHICKEN_BIT_SELECT
	.comm	_SHR_APMG_DL_CFG_REG,4,2        ; @SHR_APMG_DL_CFG_REG
	.comm	_SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP,4,2 ; @SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
	.comm	_CSR_HW_IF_CONFIG_REG,4,2       ; @CSR_HW_IF_CONFIG_REG
	.comm	_CSR_HW_IF_CONFIG_REG_PERSIST_MODE,4,2 ; @CSR_HW_IF_CONFIG_REG_PERSIST_MODE
	.comm	_CSR_MONITOR_CFG_REG,4,2        ; @CSR_MONITOR_CFG_REG
	.comm	_CSR_MONITOR_XTAL_RESOURCES,4,2 ; @CSR_MONITOR_XTAL_RESOURCES
	.no_dead_strip	_iwl_pcie_apm_lp_xtal_enable
.subsections_via_symbols
