	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function vxge_print_parm
_vxge_print_parm:                       ## @vxge_print_parm
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r14d
	movq	%rdi, %r15
	movq	_VXGE_TRACE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	(%r15), %rcx
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str(%rip), %rsi
	xorl	%eax, %eax
	callq	_vxge_debug_init
	movl	24(%r15), %eax
	cmpl	$134, %eax
	je	LBB0_1
## %bb.2:
	cmpl	$133, %eax
	jne	LBB0_5
## %bb.3:
	leaq	L_.str.2(%rip), %rsi
	jmp	LBB0_4
LBB0_1:
	leaq	L_.str.1(%rip), %rsi
LBB0_4:
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	xorl	%eax, %eax
	callq	_vxge_debug_init
LBB0_5:
	cmpq	$0, 40(%r15)
	leaq	L_.str.4(%rip), %rax
	leaq	L_.str.3(%rip), %rsi
	cmoveq	%rax, %rsi
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	xorl	%eax, %eax
	callq	_vxge_debug_init
	movl	28(%r15), %eax
	addl	$-128, %eax
	cmpl	$4, %eax
	ja	LBB0_12
## %bb.6:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_9:
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.6(%rip), %rsi
	jmp	LBB0_13
LBB0_12:
	movq	_VXGE_ERR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.9(%rip), %rsi
LBB0_13:
	xorl	%eax, %eax
	callq	_vxge_debug_init
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.5(%rip), %rsi
	xorl	%eax, %eax
	callq	_vxge_debug_init
	movl	$0, 28(%r15)
	cmpq	$0, 32(%r15)
	jne	LBB0_15
	jmp	LBB0_16
LBB0_11:
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.8(%rip), %rsi
	jmp	LBB0_8
LBB0_10:
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.7(%rip), %rsi
	jmp	LBB0_8
LBB0_7:
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.5(%rip), %rsi
LBB0_8:
	xorl	%eax, %eax
	callq	_vxge_debug_init
	cmpq	$0, 32(%r15)
	je	LBB0_16
LBB0_15:
	movl	(%rbx), %edi
	movq	16(%r15), %rax
	movl	(%rax), %edx
	leaq	L_.str.10(%rip), %rsi
	xorl	%eax, %eax
	callq	_vxge_debug_init
LBB0_16:
	movq	_VXGE_HW_MAX_VIRTUAL_PATHS@GOTPCREL(%rip), %r12
	cmpl	$0, (%r12)
	jle	LBB0_20
## %bb.17:
	xorl	%r13d, %r13d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_18:                                ## =>This Inner Loop Header: Depth=1
	movl	%r14d, %edi
	movl	%ebx, %esi
	movl	$1, %edx
	callq	_vxge_bVALn
	testl	%eax, %eax
	jne	LBB0_21
## %bb.19:                              ##   in Loop: Header=BB0_18 Depth=1
	incl	%ebx
	addq	$24, %r13
	cmpl	(%r12), %ebx
	jl	LBB0_18
LBB0_20:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_21:
	movq	_VXGE_TRACE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edi
	movq	8(%r15), %rax
	movq	16(%r15), %rcx
	movl	(%rcx), %edx
	movq	(%rax), %rax
	movl	16(%rax,%r13), %ecx
	leaq	L_.str.11(%rip), %rsi
	callq	_vxge_debug_ll_config
	movl	(%rbx), %edi
	movq	8(%r15), %rax
	movq	16(%r15), %rcx
	movl	(%rcx), %edx
	movq	(%rax), %rax
	cmpq	$0, 8(%rax,%r13)
	leaq	L_.str.14(%rip), %rax
	leaq	L_.str.13(%rip), %rcx
	cmoveq	%rax, %rcx
	leaq	L_.str.12(%rip), %rsi
	xorl	%eax, %eax
	callq	_vxge_debug_init
	movl	(%rbx), %edi
	movq	8(%r15), %rax
	movq	16(%r15), %rcx
	movl	(%rcx), %edx
	movq	(%rax), %rax
	movl	(%rax,%r13), %ecx
	leaq	L_.str.15(%rip), %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_vxge_debug_ll_config           ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_10, LBB0_10-LJTI0_0
.set L0_0_set_7, LBB0_7-LJTI0_0
LJTI0_0:
	.long	L0_0_set_9
	.long	L0_0_set_9
	.long	L0_0_set_11
	.long	L0_0_set_10
	.long	L0_0_set_7
	.end_data_region
                                        ## -- End function
	.comm	_VXGE_TRACE,4,2                 ## @VXGE_TRACE
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s: %d Vpath(s) opened"

L_.str.1:                               ## @.str.1
	.asciz	"%s: Interrupt type INTA"

L_.str.2:                               ## @.str.2
	.asciz	"%s: Interrupt type MSI-X"

L_.str.3:                               ## @.str.3
	.asciz	"%s: RTH steering enabled for TCP_IPV4"

L_.str.4:                               ## @.str.4
	.asciz	"%s: RTH steering disabled"

L_.str.5:                               ## @.str.5
	.asciz	"%s: Tx steering disabled"

L_.str.6:                               ## @.str.6
	.asciz	"%s: Unsupported tx steering option"

L_.str.7:                               ## @.str.7
	.asciz	"%s: Tx multiqueue steering enabled"

L_.str.8:                               ## @.str.8
	.asciz	"%s: Tx port steering enabled"

	.comm	_VXGE_ERR,4,2                   ## @VXGE_ERR
L_.str.9:                               ## @.str.9
	.asciz	"%s: Unsupported tx steering type"

L_.str.10:                              ## @.str.10
	.asciz	"%s: MAC Address learning enabled"

	.comm	_VXGE_HW_MAX_VIRTUAL_PATHS,4,2  ## @VXGE_HW_MAX_VIRTUAL_PATHS
L_.str.11:                              ## @.str.11
	.asciz	"%s: MTU size - %d"

L_.str.12:                              ## @.str.12
	.asciz	"%s: VLAN tag stripping %s"

L_.str.13:                              ## @.str.13
	.asciz	"Enabled"

L_.str.14:                              ## @.str.14
	.asciz	"Disabled"

L_.str.15:                              ## @.str.15
	.asciz	"%s: Max frags : %d"

	.no_dead_strip	_vxge_print_parm
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function vxge_print_parm
_vxge_print_parm:                       ; @vxge_print_parm
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #80
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x22, _VXGE_TRACE@GOTPAGE
Lloh1:
	ldr	x22, [x22, _VXGE_TRACE@GOTPAGEOFF]
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
	ldr	x8, [x19]
	str	x8, [sp]
Lloh2:
	adrp	x1, l_.str@PAGE
Lloh3:
	add	x1, x1, l_.str@PAGEOFF
	bl	_vxge_debug_init
	ldr	w8, [x19, #24]
	cmp	w8, #134
	b.eq	LBB0_3
; %bb.1:
	cmp	w8, #133
	b.ne	LBB0_5
; %bb.2:
Lloh4:
	adrp	x1, l_.str.2@PAGE
Lloh5:
	add	x1, x1, l_.str.2@PAGEOFF
	b	LBB0_4
LBB0_3:
Lloh6:
	adrp	x1, l_.str.1@PAGE
Lloh7:
	add	x1, x1, l_.str.1@PAGEOFF
LBB0_4:
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
	bl	_vxge_debug_init
LBB0_5:
Lloh8:
	adrp	x8, l_.str.3@PAGE
Lloh9:
	add	x8, x8, l_.str.3@PAGEOFF
Lloh10:
	adrp	x9, l_.str.4@PAGE
Lloh11:
	add	x9, x9, l_.str.4@PAGEOFF
	ldr	x10, [x19, #40]
	cmp	x10, #0
	csel	x1, x9, x8, eq
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
	bl	_vxge_debug_init
	ldr	w8, [x19, #28]
	sub	w8, w8, #128
	cmp	w8, #4
	b.hi	LBB0_8
; %bb.6:
Lloh12:
	adrp	x9, lJTI0_0@PAGE
Lloh13:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_7
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_7:
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh14:
	adrp	x1, l_.str.6@PAGE
Lloh15:
	add	x1, x1, l_.str.6@PAGEOFF
	b	LBB0_9
LBB0_8:
Lloh16:
	adrp	x8, _VXGE_ERR@GOTPAGE
Lloh17:
	ldr	x8, [x8, _VXGE_ERR@GOTPAGEOFF]
Lloh18:
	ldr	w0, [x8]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh19:
	adrp	x1, l_.str.9@PAGE
Lloh20:
	add	x1, x1, l_.str.9@PAGEOFF
LBB0_9:
	bl	_vxge_debug_init
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh21:
	adrp	x1, l_.str.5@PAGE
Lloh22:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_vxge_debug_init
	str	wzr, [x19, #28]
	ldr	x8, [x19, #32]
	cbz	x8, LBB0_11
LBB0_10:
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh23:
	adrp	x1, l_.str.10@PAGE
Lloh24:
	add	x1, x1, l_.str.10@PAGEOFF
	bl	_vxge_debug_init
LBB0_11:
Lloh25:
	adrp	x24, _VXGE_HW_MAX_VIRTUAL_PATHS@GOTPAGE
Lloh26:
	ldr	x24, [x24, _VXGE_HW_MAX_VIRTUAL_PATHS@GOTPAGEOFF]
	ldr	w8, [x24]
	cmp	w8, #1
	b.lt	LBB0_15
; %bb.12:
	mov	x23, #0
	mov	w21, #0
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	mov	x1, x21
	mov	w2, #1
	bl	_vxge_bVALn
	cbnz	w0, LBB0_16
; %bb.14:                               ;   in Loop: Header=BB0_13 Depth=1
	add	w21, w21, #1
	ldr	w8, [x24]
	add	x23, x23, #24
	cmp	w21, w8
	b.lt	LBB0_13
LBB0_15:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	ret
LBB0_16:
	ldr	w0, [x22]
	ldp	x9, x8, [x19, #8]
	ldr	w2, [x8]
	ldr	x8, [x9]
	add	x8, x8, x23
	ldr	w3, [x8, #16]
Lloh27:
	adrp	x1, l_.str.11@PAGE
Lloh28:
	add	x1, x1, l_.str.11@PAGEOFF
	bl	_vxge_debug_ll_config
	ldr	w0, [x22]
	ldp	x9, x8, [x19, #8]
	ldr	w2, [x8]
	ldr	x8, [x9]
	add	x8, x8, x23
	ldr	x8, [x8, #8]
Lloh29:
	adrp	x9, l_.str.13@PAGE
Lloh30:
	add	x9, x9, l_.str.13@PAGEOFF
Lloh31:
	adrp	x10, l_.str.14@PAGE
Lloh32:
	add	x10, x10, l_.str.14@PAGEOFF
	cmp	x8, #0
	csel	x8, x10, x9, eq
	str	x8, [sp]
Lloh33:
	adrp	x1, l_.str.12@PAGE
Lloh34:
	add	x1, x1, l_.str.12@PAGEOFF
	bl	_vxge_debug_init
	ldr	w0, [x22]
	ldp	x9, x8, [x19, #8]
	ldr	w2, [x8]
	ldr	x8, [x9]
	ldr	w3, [x8, x23]
Lloh35:
	adrp	x1, l_.str.15@PAGE
Lloh36:
	add	x1, x1, l_.str.15@PAGEOFF
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #80
	b	_vxge_debug_ll_config
LBB0_17:
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh37:
	adrp	x1, l_.str.8@PAGE
Lloh38:
	add	x1, x1, l_.str.8@PAGEOFF
	b	LBB0_20
LBB0_18:
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh39:
	adrp	x1, l_.str.7@PAGE
Lloh40:
	add	x1, x1, l_.str.7@PAGEOFF
	b	LBB0_20
LBB0_19:
	ldr	w0, [x22]
	ldr	x8, [x19, #16]
	ldr	w2, [x8]
Lloh41:
	adrp	x1, l_.str.5@PAGE
Lloh42:
	add	x1, x1, l_.str.5@PAGEOFF
LBB0_20:
	bl	_vxge_debug_init
	ldr	x8, [x19, #32]
	cbnz	x8, LBB0_10
	b	LBB0_11
	.loh AdrpAdd	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpAdd	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpAdd	Lloh10, Lloh11
	.loh AdrpAdd	Lloh8, Lloh9
	.loh AdrpAdd	Lloh12, Lloh13
	.loh AdrpAdd	Lloh14, Lloh15
	.loh AdrpAdd	Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpAdd	Lloh21, Lloh22
	.loh AdrpAdd	Lloh23, Lloh24
	.loh AdrpLdrGot	Lloh25, Lloh26
	.loh AdrpAdd	Lloh35, Lloh36
	.loh AdrpAdd	Lloh33, Lloh34
	.loh AdrpAdd	Lloh31, Lloh32
	.loh AdrpAdd	Lloh29, Lloh30
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpAdd	Lloh39, Lloh40
	.loh AdrpAdd	Lloh41, Lloh42
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_7-LBB0_7)>>2
	.byte	(LBB0_7-LBB0_7)>>2
	.byte	(LBB0_17-LBB0_7)>>2
	.byte	(LBB0_18-LBB0_7)>>2
	.byte	(LBB0_19-LBB0_7)>>2
                                        ; -- End function
	.comm	_VXGE_TRACE,4,2                 ; @VXGE_TRACE
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s: %d Vpath(s) opened"

l_.str.1:                               ; @.str.1
	.asciz	"%s: Interrupt type INTA"

l_.str.2:                               ; @.str.2
	.asciz	"%s: Interrupt type MSI-X"

l_.str.3:                               ; @.str.3
	.asciz	"%s: RTH steering enabled for TCP_IPV4"

l_.str.4:                               ; @.str.4
	.asciz	"%s: RTH steering disabled"

l_.str.5:                               ; @.str.5
	.asciz	"%s: Tx steering disabled"

l_.str.6:                               ; @.str.6
	.asciz	"%s: Unsupported tx steering option"

l_.str.7:                               ; @.str.7
	.asciz	"%s: Tx multiqueue steering enabled"

l_.str.8:                               ; @.str.8
	.asciz	"%s: Tx port steering enabled"

	.comm	_VXGE_ERR,4,2                   ; @VXGE_ERR
l_.str.9:                               ; @.str.9
	.asciz	"%s: Unsupported tx steering type"

l_.str.10:                              ; @.str.10
	.asciz	"%s: MAC Address learning enabled"

	.comm	_VXGE_HW_MAX_VIRTUAL_PATHS,4,2  ; @VXGE_HW_MAX_VIRTUAL_PATHS
l_.str.11:                              ; @.str.11
	.asciz	"%s: MTU size - %d"

l_.str.12:                              ; @.str.12
	.asciz	"%s: VLAN tag stripping %s"

l_.str.13:                              ; @.str.13
	.asciz	"Enabled"

l_.str.14:                              ; @.str.14
	.asciz	"Disabled"

l_.str.15:                              ; @.str.15
	.asciz	"%s: Max frags : %d"

	.no_dead_strip	_vxge_print_parm
.subsections_via_symbols
