	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function wl18xx_pre_upload
_wl18xx_pre_upload:                     ## @wl18xx_pre_upload
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_WL18XX_PHY_INIT_MEM_SIZE@GOTPCREL(%rip), %rax
	xorl	%edi, %edi
	cmpl	$4, (%rax)
	setb	%dil
	callq	_BUILD_BUG_ON
	movq	_PART_BOOT@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	shlq	$2, %rsi
	addq	(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_wlcore_set_partition
	testl	%eax, %eax
	js	LBB0_14
## %bb.1:
	movq	_WL18XX_EEPROMLESS_IND@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%edx, %esi
	callq	_wlcore_write32
	testl	%eax, %eax
	js	LBB0_14
## %bb.2:
	movq	_REG_CHIP_ID_B@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-32(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_wlcore_read_reg
	testl	%eax, %eax
	js	LBB0_14
## %bb.3:
	movq	_DEBUG_BOOT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	-32(%rbp), %edx
	leaq	L_.str(%rip), %rsi
	callq	_wl1271_debug
	movq	_WL18XX_SCR_PAD2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-32(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_wlcore_read32
	testl	%eax, %eax
	js	LBB0_14
## %bb.4:
	movq	_PART_PHY_INIT@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	shlq	$2, %rsi
	addq	(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_wlcore_set_partition
	testl	%eax, %eax
	js	LBB0_14
## %bb.5:
	movq	_WL18XX_PHY_FPGA_SPARE_1@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MEM_FDSP_CLK_120_DISABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_wlcore_write32
	testl	%eax, %eax
	js	LBB0_14
## %bb.6:
	movl	(%r15), %esi
	movq	_MEM_FDSP_CODERAM_FUNC_CLK_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_wlcore_write32
	testl	%eax, %eax
	js	LBB0_14
## %bb.7:
	movl	(%r15), %esi
	movq	_MEM_FDSP_CLK_120_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_wlcore_write32
	testl	%eax, %eax
	js	LBB0_14
## %bb.8:
	movl	8(%rbx), %edi
	callq	_irq_get_trigger_type
	movq	_IRQ_TYPE_LEVEL_LOW@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	je	LBB0_10
## %bb.9:
	movq	_IRQ_TYPE_EDGE_FALLING@GOTPCREL(%rip), %rcx
	cmpl	(%rcx), %eax
	jne	LBB0_14
LBB0_10:
	leaq	L_.str.1(%rip), %rdi
	movl	%eax, %esi
	callq	_wl1271_info
	movq	_PART_TOP_PRCM_ELP_SOC@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	shlq	$2, %rsi
	addq	(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_wlcore_set_partition
	testl	%eax, %eax
	js	LBB0_14
## %bb.11:
	movq	_TOP_FN0_CCCR_REG_32@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	leaq	-28(%rbp), %rdx
	movq	%rbx, %rdi
	callq	_wl18xx_top_reg_read
	testl	%eax, %eax
	js	LBB0_14
## %bb.12:
	movl	$1, %edi
	callq	_BIT
	orl	-28(%rbp), %eax
	movl	%eax, -28(%rbp)
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_wl18xx_top_reg_write
	testl	%eax, %eax
	js	LBB0_14
## %bb.13:
	movq	(%r14), %rsi
	shlq	$2, %rsi
	addq	(%rbx), %rsi
	movq	%rbx, %rdi
	callq	_wlcore_set_partition
LBB0_14:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_WL18XX_PHY_INIT_MEM_SIZE,4,2   ## @WL18XX_PHY_INIT_MEM_SIZE
	.comm	_PART_BOOT,8,3                  ## @PART_BOOT
	.comm	_WL18XX_EEPROMLESS_IND,4,2      ## @WL18XX_EEPROMLESS_IND
	.comm	_REG_CHIP_ID_B,4,2              ## @REG_CHIP_ID_B
	.comm	_DEBUG_BOOT,4,2                 ## @DEBUG_BOOT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"chip id 0x%x"

	.comm	_WL18XX_SCR_PAD2,4,2            ## @WL18XX_SCR_PAD2
	.comm	_PART_PHY_INIT,8,3              ## @PART_PHY_INIT
	.comm	_WL18XX_PHY_FPGA_SPARE_1,4,2    ## @WL18XX_PHY_FPGA_SPARE_1
	.comm	_MEM_FDSP_CLK_120_DISABLE,4,2   ## @MEM_FDSP_CLK_120_DISABLE
	.comm	_MEM_FDSP_CODERAM_FUNC_CLK_SEL,4,2 ## @MEM_FDSP_CODERAM_FUNC_CLK_SEL
	.comm	_MEM_FDSP_CLK_120_ENABLE,4,2    ## @MEM_FDSP_CLK_120_ENABLE
	.comm	_IRQ_TYPE_LEVEL_LOW,4,2         ## @IRQ_TYPE_LEVEL_LOW
	.comm	_IRQ_TYPE_EDGE_FALLING,4,2      ## @IRQ_TYPE_EDGE_FALLING
L_.str.1:                               ## @.str.1
	.asciz	"using inverted interrupt logic: %d"

	.comm	_PART_TOP_PRCM_ELP_SOC,8,3      ## @PART_TOP_PRCM_ELP_SOC
	.comm	_TOP_FN0_CCCR_REG_32,4,2        ## @TOP_FN0_CCCR_REG_32
	.no_dead_strip	_wl18xx_pre_upload
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function wl18xx_pre_upload
_wl18xx_pre_upload:                     ; @wl18xx_pre_upload
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x8, _WL18XX_PHY_INIT_MEM_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _WL18XX_PHY_INIT_MEM_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	cmp	w8, #4
	cset	w0, lo
	bl	_BUILD_BUG_ON
	ldr	x8, [x19]
Lloh3:
	adrp	x9, _PART_BOOT@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PART_BOOT@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	add	x1, x8, x9, lsl #2
	mov	x0, x19
	bl	_wlcore_set_partition
	tbnz	w0, #31, LBB0_14
; %bb.1:
Lloh6:
	adrp	x8, _WL18XX_EEPROMLESS_IND@GOTPAGE
Lloh7:
	ldr	x8, [x8, _WL18XX_EEPROMLESS_IND@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x1
	bl	_wlcore_write32
	tbnz	w0, #31, LBB0_14
; %bb.2:
Lloh9:
	adrp	x8, _REG_CHIP_ID_B@GOTPAGE
Lloh10:
	ldr	x8, [x8, _REG_CHIP_ID_B@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	add	x2, sp, #12
	mov	x0, x19
	bl	_wlcore_read_reg
	tbnz	w0, #31, LBB0_14
; %bb.3:
Lloh12:
	adrp	x8, _DEBUG_BOOT@GOTPAGE
Lloh13:
	ldr	x8, [x8, _DEBUG_BOOT@GOTPAGEOFF]
Lloh14:
	ldr	w0, [x8]
	ldr	w2, [sp, #12]
Lloh15:
	adrp	x1, l_.str@PAGE
Lloh16:
	add	x1, x1, l_.str@PAGEOFF
	bl	_wl1271_debug
Lloh17:
	adrp	x8, _WL18XX_SCR_PAD2@GOTPAGE
Lloh18:
	ldr	x8, [x8, _WL18XX_SCR_PAD2@GOTPAGEOFF]
Lloh19:
	ldr	w1, [x8]
	add	x2, sp, #12
	mov	x0, x19
	bl	_wlcore_read32
	tbnz	w0, #31, LBB0_14
; %bb.4:
	ldr	x8, [x19]
Lloh20:
	adrp	x20, _PART_PHY_INIT@GOTPAGE
Lloh21:
	ldr	x20, [x20, _PART_PHY_INIT@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x1, x8, x9, lsl #2
	mov	x0, x19
	bl	_wlcore_set_partition
	tbnz	w0, #31, LBB0_14
; %bb.5:
Lloh22:
	adrp	x21, _WL18XX_PHY_FPGA_SPARE_1@GOTPAGE
Lloh23:
	ldr	x21, [x21, _WL18XX_PHY_FPGA_SPARE_1@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh24:
	adrp	x8, _MEM_FDSP_CLK_120_DISABLE@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MEM_FDSP_CLK_120_DISABLE@GOTPAGEOFF]
Lloh26:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wlcore_write32
	tbnz	w0, #31, LBB0_14
; %bb.6:
	ldr	w1, [x21]
Lloh27:
	adrp	x8, _MEM_FDSP_CODERAM_FUNC_CLK_SEL@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MEM_FDSP_CODERAM_FUNC_CLK_SEL@GOTPAGEOFF]
Lloh29:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wlcore_write32
	tbnz	w0, #31, LBB0_14
; %bb.7:
	ldr	w1, [x21]
Lloh30:
	adrp	x8, _MEM_FDSP_CLK_120_ENABLE@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MEM_FDSP_CLK_120_ENABLE@GOTPAGEOFF]
Lloh32:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_wlcore_write32
	tbnz	w0, #31, LBB0_14
; %bb.8:
	ldr	w0, [x19, #8]
	bl	_irq_get_trigger_type
	mov	x1, x0
Lloh33:
	adrp	x8, _IRQ_TYPE_LEVEL_LOW@GOTPAGE
Lloh34:
	ldr	x8, [x8, _IRQ_TYPE_LEVEL_LOW@GOTPAGEOFF]
Lloh35:
	ldr	w8, [x8]
	cmp	w0, w8
	b.eq	LBB0_10
; %bb.9:
Lloh36:
	adrp	x8, _IRQ_TYPE_EDGE_FALLING@GOTPAGE
Lloh37:
	ldr	x8, [x8, _IRQ_TYPE_EDGE_FALLING@GOTPAGEOFF]
Lloh38:
	ldr	w8, [x8]
	cmp	w1, w8
	b.ne	LBB0_15
LBB0_10:
Lloh39:
	adrp	x0, l_.str.1@PAGE
Lloh40:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_wl1271_info
	ldr	x8, [x19]
Lloh41:
	adrp	x9, _PART_TOP_PRCM_ELP_SOC@GOTPAGE
Lloh42:
	ldr	x9, [x9, _PART_TOP_PRCM_ELP_SOC@GOTPAGEOFF]
Lloh43:
	ldr	x9, [x9]
	add	x1, x8, x9, lsl #2
	mov	x0, x19
	bl	_wlcore_set_partition
	tbnz	w0, #31, LBB0_14
; %bb.11:
Lloh44:
	adrp	x21, _TOP_FN0_CCCR_REG_32@GOTPAGE
Lloh45:
	ldr	x21, [x21, _TOP_FN0_CCCR_REG_32@GOTPAGEOFF]
	ldr	w1, [x21]
	add	x2, sp, #8
	mov	x0, x19
	bl	_wl18xx_top_reg_read
	tbnz	w0, #31, LBB0_14
; %bb.12:
	mov	w0, #1
	bl	_BIT
	ldr	w8, [sp, #8]
	orr	w2, w8, w0
	str	w2, [sp, #8]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_wl18xx_top_reg_write
	tbnz	w0, #31, LBB0_14
; %bb.13:
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x1, x8, x9, lsl #2
	mov	x0, x19
	bl	_wlcore_set_partition
LBB0_14:
	mov	x1, x0
LBB0_15:
	mov	x0, x1
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpAdd	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh44, Lloh45
	.cfi_endproc
                                        ; -- End function
	.comm	_WL18XX_PHY_INIT_MEM_SIZE,4,2   ; @WL18XX_PHY_INIT_MEM_SIZE
	.comm	_PART_BOOT,8,3                  ; @PART_BOOT
	.comm	_WL18XX_EEPROMLESS_IND,4,2      ; @WL18XX_EEPROMLESS_IND
	.comm	_REG_CHIP_ID_B,4,2              ; @REG_CHIP_ID_B
	.comm	_DEBUG_BOOT,4,2                 ; @DEBUG_BOOT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"chip id 0x%x"

	.comm	_WL18XX_SCR_PAD2,4,2            ; @WL18XX_SCR_PAD2
	.comm	_PART_PHY_INIT,8,3              ; @PART_PHY_INIT
	.comm	_WL18XX_PHY_FPGA_SPARE_1,4,2    ; @WL18XX_PHY_FPGA_SPARE_1
	.comm	_MEM_FDSP_CLK_120_DISABLE,4,2   ; @MEM_FDSP_CLK_120_DISABLE
	.comm	_MEM_FDSP_CODERAM_FUNC_CLK_SEL,4,2 ; @MEM_FDSP_CODERAM_FUNC_CLK_SEL
	.comm	_MEM_FDSP_CLK_120_ENABLE,4,2    ; @MEM_FDSP_CLK_120_ENABLE
	.comm	_IRQ_TYPE_LEVEL_LOW,4,2         ; @IRQ_TYPE_LEVEL_LOW
	.comm	_IRQ_TYPE_EDGE_FALLING,4,2      ; @IRQ_TYPE_EDGE_FALLING
l_.str.1:                               ; @.str.1
	.asciz	"using inverted interrupt logic: %d"

	.comm	_PART_TOP_PRCM_ELP_SOC,8,3      ; @PART_TOP_PRCM_ELP_SOC
	.comm	_TOP_FN0_CCCR_REG_32,4,2        ; @TOP_FN0_CCCR_REG_32
	.no_dead_strip	_wl18xx_pre_upload
.subsections_via_symbols
