	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function _iwl_enable_interrupts
__iwl_enable_interrupts:                ## @_iwl_enable_interrupts
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	callq	_IWL_TRANS_GET_PCIE_TRANS
	movq	%rax, %rbx
	leaq	L_.str(%rip), %rsi
	movq	%r14, %rdi
	callq	_IWL_DEBUG_ISR
	movq	_STATUS_INT_ENABLED@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	%r14, %rsi
	callq	_set_bit
	cmpl	$0, 20(%rbx)
	je	LBB0_1
## %bb.3:
	movl	8(%rbx), %edx
	movl	12(%rbx), %eax
	movl	%eax, (%rbx)
	movl	%edx, 4(%rbx)
	movq	_CSR_MSIX_FH_INT_MASK_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	notl	%edx
	movq	%r14, %rdi
	callq	_iwl_write32
	movq	_CSR_MSIX_HW_INT_MASK_AD@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%rbx), %edx
	notl	%edx
	jmp	LBB0_2
LBB0_1:
	movq	_CSR_INI_SET_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movl	%edx, 16(%rbx)
	movq	_CSR_INT_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
LBB0_2:
	movq	%r14, %rdi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_iwl_write32                    ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Enabling interrupts\n"

	.comm	_STATUS_INT_ENABLED,4,2         ## @STATUS_INT_ENABLED
	.comm	_CSR_INI_SET_MASK,4,2           ## @CSR_INI_SET_MASK
	.comm	_CSR_INT_MASK,4,2               ## @CSR_INT_MASK
	.comm	_CSR_MSIX_FH_INT_MASK_AD,4,2    ## @CSR_MSIX_FH_INT_MASK_AD
	.comm	_CSR_MSIX_HW_INT_MASK_AD,4,2    ## @CSR_MSIX_HW_INT_MASK_AD
	.no_dead_strip	__iwl_enable_interrupts
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function _iwl_enable_interrupts
__iwl_enable_interrupts:                ; @_iwl_enable_interrupts
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_IWL_TRANS_GET_PCIE_TRANS
	mov	x20, x0
Lloh0:
	adrp	x1, l_.str@PAGE
Lloh1:
	add	x1, x1, l_.str@PAGEOFF
	mov	x0, x19
	bl	_IWL_DEBUG_ISR
Lloh2:
	adrp	x8, _STATUS_INT_ENABLED@GOTPAGE
Lloh3:
	ldr	x8, [x8, _STATUS_INT_ENABLED@GOTPAGEOFF]
Lloh4:
	ldr	w0, [x8]
	mov	x1, x19
	bl	_set_bit
	ldr	w8, [x20, #20]
	cbz	w8, LBB0_2
; %bb.1:
	ldr	d0, [x20, #8]
	rev64.2s	v1, v0
	str	d1, [x20]
Lloh5:
	adrp	x8, _CSR_MSIX_FH_INT_MASK_AD@GOTPAGE
Lloh6:
	ldr	x8, [x8, _CSR_MSIX_FH_INT_MASK_AD@GOTPAGEOFF]
Lloh7:
	ldr	w1, [x8]
	fmov	w8, s0
	mvn	w2, w8
	mov	x0, x19
	bl	_iwl_write32
Lloh8:
	adrp	x8, _CSR_MSIX_HW_INT_MASK_AD@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CSR_MSIX_HW_INT_MASK_AD@GOTPAGEOFF]
Lloh10:
	ldr	w1, [x8]
	ldr	w8, [x20]
	mvn	w2, w8
	b	LBB0_3
LBB0_2:
Lloh11:
	adrp	x8, _CSR_INI_SET_MASK@GOTPAGE
Lloh12:
	ldr	x8, [x8, _CSR_INI_SET_MASK@GOTPAGEOFF]
Lloh13:
	ldr	w2, [x8]
	str	w2, [x20, #16]
Lloh14:
	adrp	x8, _CSR_INT_MASK@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CSR_INT_MASK@GOTPAGEOFF]
Lloh16:
	ldr	w1, [x8]
LBB0_3:
	mov	x0, x19
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_iwl_write32
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh11, Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Enabling interrupts\n"

	.comm	_STATUS_INT_ENABLED,4,2         ; @STATUS_INT_ENABLED
	.comm	_CSR_INI_SET_MASK,4,2           ; @CSR_INI_SET_MASK
	.comm	_CSR_INT_MASK,4,2               ; @CSR_INT_MASK
	.comm	_CSR_MSIX_FH_INT_MASK_AD,4,2    ; @CSR_MSIX_FH_INT_MASK_AD
	.comm	_CSR_MSIX_HW_INT_MASK_AD,4,2    ; @CSR_MSIX_HW_INT_MASK_AD
	.no_dead_strip	__iwl_enable_interrupts
.subsections_via_symbols
