	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function exynos4210_phy_pwr
_exynos4210_phy_pwr:                    ## @exynos4210_phy_pwr
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%esi, %r15d
	movq	(%rdi), %rax
	movq	8(%rdi), %r12
	movl	(%rax), %eax
	addl	$-128, %eax
	cmpl	$3, %eax
	ja	LBB0_1
## %bb.2:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_6:
	movq	_EXYNOS_4210_UPHYPWR_HSIC1@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPCREL(%rip), %rax
	movq	_EXYNOS_4210_URSTCON_HOST_LINK_P2@GOTPCREL(%rip), %rcx
	jmp	LBB0_7
LBB0_1:
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	jmp	LBB0_8
LBB0_5:
	movq	_EXYNOS_4210_UPHYPWR_HSIC0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPCREL(%rip), %rax
	movq	_EXYNOS_4210_URSTCON_HOST_LINK_P1@GOTPCREL(%rip), %rcx
LBB0_7:
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	jmp	LBB0_8
LBB0_4:
	movq	_EXYNOS_4210_URSTCON_PHY1_ALL@GOTPCREL(%rip), %rax
	movq	_EXYNOS_4210_URSTCON_PHY1_P0@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_EXYNOS_4210_UPHYPWR_PHY1@GOTPCREL(%rip), %rax
	movq	_EXYNOS_4210_URSTCON_HOST_LINK_ALL@GOTPCREL(%rip), %rcx
	orl	(%rcx), %ebx
	movl	(%rax), %r14d
	movq	_EXYNOS_4210_URSTCON_HOST_LINK_P0@GOTPCREL(%rip), %rax
	orl	(%rax), %ebx
	movq	_EXYNOS_4210_UPHY1CON@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	addq	8(%r12), %rsi
	movl	%r15d, %edi
	callq	_writel
	jmp	LBB0_8
LBB0_3:
	movq	_EXYNOS_4210_UPHYPWR_PHY0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_EXYNOS_4210_URSTCON_PHY0@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
LBB0_8:
	movq	8(%r12), %rdi
	testl	%r15d, %r15d
	je	LBB0_10
## %bb.9:
	movq	_EXYNOS_4210_UPHYCLK@GOTPCREL(%rip), %r15
	addq	(%r15), %rdi
	callq	_readl
	movq	_EXYNOS_4210_UPHYCLK_PHYFSEL_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	(%r12), %edi
	movq	_EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %edi
	orl	%edx, %edi
	movq	(%r15), %rsi
	addq	8(%r12), %rsi
	callq	_writel
	movq	_EXYNOS_4210_UPHYPWR@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	8(%r12), %rdi
	callq	_readl
	notl	%r14d
	andl	%eax, %r14d
	movq	(%r15), %rsi
	addq	8(%r12), %rsi
	movl	%r14d, %edi
	callq	_writel
	movq	_EXYNOS_4210_UPHYRST@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	addq	8(%r12), %rdi
	callq	_readl
	movl	%eax, %r14d
	movl	%eax, %edi
	orl	%ebx, %edi
	movq	(%r15), %rsi
	addq	8(%r12), %rsi
	callq	_writel
	movl	$10, %edi
	callq	_udelay
	notl	%ebx
	andl	%r14d, %ebx
	movq	(%r15), %rsi
	addq	8(%r12), %rsi
	movl	%ebx, %edi
	callq	_writel
	movl	$80, %edi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_udelay                         ## TAILCALL
LBB0_10:
	movq	_EXYNOS_4210_UPHYPWR@GOTPCREL(%rip), %rbx
	addq	(%rbx), %rdi
	callq	_readl
	orl	%eax, %r14d
	movq	(%rbx), %rsi
	addq	8(%r12), %rsi
	movl	%r14d, %edi
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_6, LBB0_6-LJTI0_0
.set L0_0_set_5, LBB0_5-LJTI0_0
.set L0_0_set_4, LBB0_4-LJTI0_0
.set L0_0_set_3, LBB0_3-LJTI0_0
LJTI0_0:
	.long	L0_0_set_6
	.long	L0_0_set_5
	.long	L0_0_set_4
	.long	L0_0_set_3
	.end_data_region
                                        ## -- End function
	.comm	_EXYNOS_4210_UPHYPWR_PHY0,4,2   ## @EXYNOS_4210_UPHYPWR_PHY0
	.comm	_EXYNOS_4210_URSTCON_PHY0,4,2   ## @EXYNOS_4210_URSTCON_PHY0
	.comm	_EXYNOS_4210_UPHYPWR_PHY1,4,2   ## @EXYNOS_4210_UPHYPWR_PHY1
	.comm	_EXYNOS_4210_URSTCON_PHY1_ALL,4,2 ## @EXYNOS_4210_URSTCON_PHY1_ALL
	.comm	_EXYNOS_4210_URSTCON_PHY1_P0,4,2 ## @EXYNOS_4210_URSTCON_PHY1_P0
	.comm	_EXYNOS_4210_URSTCON_PHY1_P1P2,4,2 ## @EXYNOS_4210_URSTCON_PHY1_P1P2
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_ALL,4,2 ## @EXYNOS_4210_URSTCON_HOST_LINK_ALL
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_P0,4,2 ## @EXYNOS_4210_URSTCON_HOST_LINK_P0
	.comm	_EXYNOS_4210_UPHY1CON,8,3       ## @EXYNOS_4210_UPHY1CON
	.comm	_EXYNOS_4210_UPHYPWR_HSIC0,4,2  ## @EXYNOS_4210_UPHYPWR_HSIC0
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_P1,4,2 ## @EXYNOS_4210_URSTCON_HOST_LINK_P1
	.comm	_EXYNOS_4210_UPHYPWR_HSIC1,4,2  ## @EXYNOS_4210_UPHYPWR_HSIC1
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_P2,4,2 ## @EXYNOS_4210_URSTCON_HOST_LINK_P2
	.comm	_EXYNOS_4210_UPHYCLK,8,3        ## @EXYNOS_4210_UPHYCLK
	.comm	_EXYNOS_4210_UPHYCLK_PHYFSEL_MASK,4,2 ## @EXYNOS_4210_UPHYCLK_PHYFSEL_MASK
	.comm	_EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET,4,2 ## @EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET
	.comm	_EXYNOS_4210_UPHYPWR,8,3        ## @EXYNOS_4210_UPHYPWR
	.comm	_EXYNOS_4210_UPHYRST,8,3        ## @EXYNOS_4210_UPHYRST
	.no_dead_strip	_exynos4210_phy_pwr
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function exynos4210_phy_pwr
_exynos4210_phy_pwr:                    ; @exynos4210_phy_pwr
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x1
	ldp	x8, x20, [x0]
	ldr	w8, [x8]
	sub	w8, w8, #128
	cmp	w8, #3
	b.hi	LBB0_3
; %bb.1:
Lloh0:
	adrp	x9, lJTI0_0@PAGE
Lloh1:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_2
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_2:
Lloh2:
	adrp	x8, _EXYNOS_4210_UPHYPWR_HSIC1@GOTPAGE
Lloh3:
	ldr	x8, [x8, _EXYNOS_4210_UPHYPWR_HSIC1@GOTPAGEOFF]
Lloh4:
	adrp	x9, _EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPAGE
Lloh5:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPAGEOFF]
Lloh6:
	ldr	w21, [x8]
Lloh7:
	ldr	w8, [x9]
Lloh8:
	adrp	x9, _EXYNOS_4210_URSTCON_HOST_LINK_P2@GOTPAGE
Lloh9:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_HOST_LINK_P2@GOTPAGEOFF]
	b	LBB0_5
LBB0_3:
	mov	w21, #0
	mov	w22, #0
	ldr	x8, [x20, #8]
	cbnz	w19, LBB0_7
	b	LBB0_9
LBB0_4:
Lloh10:
	adrp	x8, _EXYNOS_4210_UPHYPWR_HSIC0@GOTPAGE
Lloh11:
	ldr	x8, [x8, _EXYNOS_4210_UPHYPWR_HSIC0@GOTPAGEOFF]
Lloh12:
	adrp	x9, _EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPAGE
Lloh13:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPAGEOFF]
Lloh14:
	ldr	w21, [x8]
Lloh15:
	ldr	w8, [x9]
Lloh16:
	adrp	x9, _EXYNOS_4210_URSTCON_HOST_LINK_P1@GOTPAGE
Lloh17:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_HOST_LINK_P1@GOTPAGEOFF]
LBB0_5:
	ldr	w9, [x9]
	orr	w22, w9, w8
	ldr	x8, [x20, #8]
	cbnz	w19, LBB0_7
	b	LBB0_9
LBB0_6:
Lloh18:
	adrp	x8, _EXYNOS_4210_UPHYPWR_PHY1@GOTPAGE
Lloh19:
	ldr	x8, [x8, _EXYNOS_4210_UPHYPWR_PHY1@GOTPAGEOFF]
Lloh20:
	ldr	w21, [x8]
Lloh21:
	adrp	x8, _EXYNOS_4210_URSTCON_PHY1_ALL@GOTPAGE
Lloh22:
	ldr	x8, [x8, _EXYNOS_4210_URSTCON_PHY1_ALL@GOTPAGEOFF]
Lloh23:
	ldr	w8, [x8]
Lloh24:
	adrp	x9, _EXYNOS_4210_URSTCON_PHY1_P0@GOTPAGE
Lloh25:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_PHY1_P0@GOTPAGEOFF]
Lloh26:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh27:
	adrp	x9, _EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPAGE
Lloh28:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_PHY1_P1P2@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
Lloh30:
	adrp	x10, _EXYNOS_4210_URSTCON_HOST_LINK_ALL@GOTPAGE
Lloh31:
	ldr	x10, [x10, _EXYNOS_4210_URSTCON_HOST_LINK_ALL@GOTPAGEOFF]
	orr	w8, w8, w9
Lloh32:
	ldr	w9, [x10]
	orr	w8, w8, w9
Lloh33:
	adrp	x9, _EXYNOS_4210_URSTCON_HOST_LINK_P0@GOTPAGE
Lloh34:
	ldr	x9, [x9, _EXYNOS_4210_URSTCON_HOST_LINK_P0@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w22, w8, w9
	ldr	x8, [x20, #8]
Lloh36:
	adrp	x9, _EXYNOS_4210_UPHY1CON@GOTPAGE
Lloh37:
	ldr	x9, [x9, _EXYNOS_4210_UPHY1CON@GOTPAGEOFF]
Lloh38:
	ldr	x9, [x9]
	add	x1, x9, x8
	mov	x0, x19
	bl	_writel
	ldr	x8, [x20, #8]
	cbz	w19, LBB0_9
LBB0_7:
Lloh39:
	adrp	x19, _EXYNOS_4210_UPHYCLK@GOTPAGE
Lloh40:
	ldr	x19, [x19, _EXYNOS_4210_UPHYCLK@GOTPAGEOFF]
	ldr	x9, [x19]
	add	x0, x9, x8
	bl	_readl
Lloh41:
	adrp	x8, _EXYNOS_4210_UPHYCLK_PHYFSEL_MASK@GOTPAGE
Lloh42:
	ldr	x8, [x8, _EXYNOS_4210_UPHYCLK_PHYFSEL_MASK@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	bic	w8, w0, w8
	ldr	w9, [x20]
Lloh44:
	adrp	x10, _EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET@GOTPAGE
Lloh45:
	ldr	x10, [x10, _EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET@GOTPAGEOFF]
Lloh46:
	ldr	w10, [x10]
	lsl	w9, w9, w10
	orr	w0, w9, w8
	ldr	x8, [x20, #8]
	ldr	x9, [x19]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x20, #8]
Lloh47:
	adrp	x19, _EXYNOS_4210_UPHYPWR@GOTPAGE
Lloh48:
	ldr	x19, [x19, _EXYNOS_4210_UPHYPWR@GOTPAGEOFF]
	ldr	x9, [x19]
	add	x0, x9, x8
	bl	_readl
	bic	w0, w0, w21
	ldr	x8, [x20, #8]
	ldr	x9, [x19]
	add	x1, x9, x8
	bl	_writel
	ldr	x8, [x20, #8]
Lloh49:
	adrp	x21, _EXYNOS_4210_UPHYRST@GOTPAGE
Lloh50:
	ldr	x21, [x21, _EXYNOS_4210_UPHYRST@GOTPAGEOFF]
	ldr	x9, [x21]
	add	x0, x9, x8
	bl	_readl
	mov	x19, x0
	orr	w0, w0, w22
	ldr	x8, [x20, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	mov	w0, #10
	bl	_udelay
	bic	w0, w19, w22
	ldr	x8, [x20, #8]
	ldr	x9, [x21]
	add	x1, x9, x8
	bl	_writel
	mov	w0, #80
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_udelay
LBB0_8:
Lloh51:
	adrp	x8, _EXYNOS_4210_UPHYPWR_PHY0@GOTPAGE
Lloh52:
	ldr	x8, [x8, _EXYNOS_4210_UPHYPWR_PHY0@GOTPAGEOFF]
Lloh53:
	ldr	w21, [x8]
Lloh54:
	adrp	x8, _EXYNOS_4210_URSTCON_PHY0@GOTPAGE
Lloh55:
	ldr	x8, [x8, _EXYNOS_4210_URSTCON_PHY0@GOTPAGEOFF]
Lloh56:
	ldr	w22, [x8]
	ldr	x8, [x20, #8]
	cbnz	w19, LBB0_7
LBB0_9:
Lloh57:
	adrp	x19, _EXYNOS_4210_UPHYPWR@GOTPAGE
Lloh58:
	ldr	x19, [x19, _EXYNOS_4210_UPHYPWR@GOTPAGEOFF]
	ldr	x9, [x19]
	add	x0, x9, x8
	bl	_readl
	orr	w0, w0, w21
	ldr	x8, [x20, #8]
	ldr	x9, [x19]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh6
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh14
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh57, Lloh58
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_2-LBB0_2)>>2
	.byte	(LBB0_4-LBB0_2)>>2
	.byte	(LBB0_6-LBB0_2)>>2
	.byte	(LBB0_8-LBB0_2)>>2
                                        ; -- End function
	.comm	_EXYNOS_4210_UPHYPWR_PHY0,4,2   ; @EXYNOS_4210_UPHYPWR_PHY0
	.comm	_EXYNOS_4210_URSTCON_PHY0,4,2   ; @EXYNOS_4210_URSTCON_PHY0
	.comm	_EXYNOS_4210_UPHYPWR_PHY1,4,2   ; @EXYNOS_4210_UPHYPWR_PHY1
	.comm	_EXYNOS_4210_URSTCON_PHY1_ALL,4,2 ; @EXYNOS_4210_URSTCON_PHY1_ALL
	.comm	_EXYNOS_4210_URSTCON_PHY1_P0,4,2 ; @EXYNOS_4210_URSTCON_PHY1_P0
	.comm	_EXYNOS_4210_URSTCON_PHY1_P1P2,4,2 ; @EXYNOS_4210_URSTCON_PHY1_P1P2
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_ALL,4,2 ; @EXYNOS_4210_URSTCON_HOST_LINK_ALL
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_P0,4,2 ; @EXYNOS_4210_URSTCON_HOST_LINK_P0
	.comm	_EXYNOS_4210_UPHY1CON,8,3       ; @EXYNOS_4210_UPHY1CON
	.comm	_EXYNOS_4210_UPHYPWR_HSIC0,4,2  ; @EXYNOS_4210_UPHYPWR_HSIC0
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_P1,4,2 ; @EXYNOS_4210_URSTCON_HOST_LINK_P1
	.comm	_EXYNOS_4210_UPHYPWR_HSIC1,4,2  ; @EXYNOS_4210_UPHYPWR_HSIC1
	.comm	_EXYNOS_4210_URSTCON_HOST_LINK_P2,4,2 ; @EXYNOS_4210_URSTCON_HOST_LINK_P2
	.comm	_EXYNOS_4210_UPHYCLK,8,3        ; @EXYNOS_4210_UPHYCLK
	.comm	_EXYNOS_4210_UPHYCLK_PHYFSEL_MASK,4,2 ; @EXYNOS_4210_UPHYCLK_PHYFSEL_MASK
	.comm	_EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET,4,2 ; @EXYNOS_4210_UPHYCLK_PHYFSEL_OFFSET
	.comm	_EXYNOS_4210_UPHYPWR,8,3        ; @EXYNOS_4210_UPHYPWR
	.comm	_EXYNOS_4210_UPHYRST,8,3        ; @EXYNOS_4210_UPHYRST
	.no_dead_strip	_exynos4210_phy_pwr
.subsections_via_symbols
