	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_port_enable
_mvpp2_port_enable:                     ## @mvpp2_port_enable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	cmpq	$0, (%rdi)
	je	LBB0_1
LBB0_3:
	movq	_MVPP2_GMAC_CTRL_0_REG@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	8(%rbx), %rdi
	addq	$8, %rbx
	callq	_readl
	movl	%eax, %edi
	movq	_MVPP2_GMAC_PORT_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	movq	_MVPP2_GMAC_MIB_CNTR_EN_MASK@GOTPCREL(%rip), %rax
	orl	(%rax), %edi
	jmp	LBB0_4
LBB0_1:
	movl	16(%rbx), %edi
	callq	_mvpp2_is_xlg
	testq	%rax, %rax
	je	LBB0_3
## %bb.2:
	movq	_MVPP22_XLG_CTRL0_REG@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	addq	8(%rbx), %rdi
	addq	$8, %rbx
	callq	_readl
	movq	_MVPP22_XLG_CTRL0_PORT_EN@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_MVPP22_XLG_CTRL0_MIB_CNT_DIS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	notl	%edi
	andl	%eax, %edi
LBB0_4:
	movq	(%r14), %rsi
	addq	(%rbx), %rsi
	popq	%rbx
	popq	%r14
	popq	%rbp
	jmp	_writel                         ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP22_XLG_CTRL0_REG,8,3       ## @MVPP22_XLG_CTRL0_REG
	.comm	_MVPP22_XLG_CTRL0_PORT_EN,4,2   ## @MVPP22_XLG_CTRL0_PORT_EN
	.comm	_MVPP22_XLG_CTRL0_MIB_CNT_DIS,4,2 ## @MVPP22_XLG_CTRL0_MIB_CNT_DIS
	.comm	_MVPP2_GMAC_CTRL_0_REG,8,3      ## @MVPP2_GMAC_CTRL_0_REG
	.comm	_MVPP2_GMAC_PORT_EN_MASK,4,2    ## @MVPP2_GMAC_PORT_EN_MASK
	.comm	_MVPP2_GMAC_MIB_CNTR_EN_MASK,4,2 ## @MVPP2_GMAC_MIB_CNTR_EN_MASK
	.no_dead_strip	_mvpp2_port_enable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_port_enable
_mvpp2_port_enable:                     ; @mvpp2_port_enable
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	ldr	x8, [x0]
	cbz	x8, LBB0_2
LBB0_1:
	ldr	x8, [x19, #8]!
Lloh0:
	adrp	x20, _MVPP2_GMAC_CTRL_0_REG@GOTPAGE
Lloh1:
	ldr	x20, [x20, _MVPP2_GMAC_CTRL_0_REG@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh2:
	adrp	x8, _MVPP2_GMAC_PORT_EN_MASK@GOTPAGE
Lloh3:
	ldr	x8, [x8, _MVPP2_GMAC_PORT_EN_MASK@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh5:
	adrp	x9, _MVPP2_GMAC_MIB_CNTR_EN_MASK@GOTPAGE
Lloh6:
	ldr	x9, [x9, _MVPP2_GMAC_MIB_CNTR_EN_MASK@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	orr	w0, w8, w9
	b	LBB0_4
LBB0_2:
	ldr	w0, [x19, #16]
	bl	_mvpp2_is_xlg
	cbz	x0, LBB0_1
; %bb.3:
	ldr	x8, [x19, #8]!
Lloh8:
	adrp	x20, _MVPP22_XLG_CTRL0_REG@GOTPAGE
Lloh9:
	ldr	x20, [x20, _MVPP22_XLG_CTRL0_REG@GOTPAGEOFF]
	ldr	x9, [x20]
	add	x0, x9, x8
	bl	_readl
Lloh10:
	adrp	x8, _MVPP22_XLG_CTRL0_PORT_EN@GOTPAGE
Lloh11:
	ldr	x8, [x8, _MVPP22_XLG_CTRL0_PORT_EN@GOTPAGEOFF]
Lloh12:
	ldr	w8, [x8]
	orr	w8, w8, w0
Lloh13:
	adrp	x9, _MVPP22_XLG_CTRL0_MIB_CNT_DIS@GOTPAGE
Lloh14:
	ldr	x9, [x9, _MVPP22_XLG_CTRL0_MIB_CNT_DIS@GOTPAGEOFF]
Lloh15:
	ldr	w9, [x9]
	bic	w0, w8, w9
LBB0_4:
	ldr	x8, [x19]
	ldr	x9, [x20]
	add	x1, x9, x8
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	b	_writel
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP22_XLG_CTRL0_REG,8,3       ; @MVPP22_XLG_CTRL0_REG
	.comm	_MVPP22_XLG_CTRL0_PORT_EN,4,2   ; @MVPP22_XLG_CTRL0_PORT_EN
	.comm	_MVPP22_XLG_CTRL0_MIB_CNT_DIS,4,2 ; @MVPP22_XLG_CTRL0_MIB_CNT_DIS
	.comm	_MVPP2_GMAC_CTRL_0_REG,8,3      ; @MVPP2_GMAC_CTRL_0_REG
	.comm	_MVPP2_GMAC_PORT_EN_MASK,4,2    ; @MVPP2_GMAC_PORT_EN_MASK
	.comm	_MVPP2_GMAC_MIB_CNTR_EN_MASK,4,2 ; @MVPP2_GMAC_MIB_CNTR_EN_MASK
	.no_dead_strip	_mvpp2_port_enable
.subsections_via_symbols
