	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pciehp_is_native               ## -- Begin function pciehp_is_native
	.p2align	4, 0x90
_pciehp_is_native:                      ## @pciehp_is_native
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %r14
	movq	_CONFIG_HOTPLUG_PCI_PCIE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_IS_ENABLED
	xorl	%ebx, %ebx
	testl	%eax, %eax
	je	LBB0_4
## %bb.1:
	movq	_PCI_EXP_SLTCAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	leaq	-20(%rbp), %rdx
	movq	%r14, %rdi
	callq	_pcie_capability_read_dword
	movq	_PCI_EXP_SLTCAP_HPC@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	testl	%eax, -20(%rbp)
	je	LBB0_4
## %bb.2:
	movq	_pcie_ports_native@GOTPCREL(%rip), %rax
	movl	$1, %ebx
	cmpq	$0, (%rax)
	jne	LBB0_4
## %bb.3:
	movl	(%r14), %edi
	callq	_pci_find_host_bridge
	movl	(%rax), %ebx
LBB0_4:
	movl	%ebx, %eax
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CONFIG_HOTPLUG_PCI_PCIE,4,2    ## @CONFIG_HOTPLUG_PCI_PCIE
	.comm	_PCI_EXP_SLTCAP,4,2             ## @PCI_EXP_SLTCAP
	.comm	_PCI_EXP_SLTCAP_HPC,4,2         ## @PCI_EXP_SLTCAP_HPC
	.comm	_pcie_ports_native,8,3          ## @pcie_ports_native
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_pciehp_is_native               ; -- Begin function pciehp_is_native
	.p2align	2
_pciehp_is_native:                      ; @pciehp_is_native
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
Lloh0:
	adrp	x8, _CONFIG_HOTPLUG_PCI_PCIE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CONFIG_HOTPLUG_PCI_PCIE@GOTPAGEOFF]
Lloh2:
	ldr	w0, [x8]
	bl	_IS_ENABLED
	cbz	w0, LBB0_6
; %bb.1:
Lloh3:
	adrp	x8, _PCI_EXP_SLTCAP@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_EXP_SLTCAP@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	add	x2, sp, #12
	mov	x0, x19
	bl	_pcie_capability_read_dword
	ldr	w8, [sp, #12]
Lloh6:
	adrp	x9, _PCI_EXP_SLTCAP_HPC@GOTPAGE
Lloh7:
	ldr	x9, [x9, _PCI_EXP_SLTCAP_HPC@GOTPAGEOFF]
Lloh8:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_4
; %bb.2:
Lloh9:
	adrp	x8, _pcie_ports_native@GOTPAGE
Lloh10:
	ldr	x8, [x8, _pcie_ports_native@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	cbz	x8, LBB0_5
; %bb.3:
	mov	w0, #1
	b	LBB0_6
LBB0_4:
	mov	w0, #0
	b	LBB0_6
LBB0_5:
	ldr	w0, [x19]
	bl	_pci_find_host_bridge
	ldr	w0, [x0]
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.cfi_endproc
                                        ; -- End function
	.comm	_CONFIG_HOTPLUG_PCI_PCIE,4,2    ; @CONFIG_HOTPLUG_PCI_PCIE
	.comm	_PCI_EXP_SLTCAP,4,2             ; @PCI_EXP_SLTCAP
	.comm	_PCI_EXP_SLTCAP_HPC,4,2         ; @PCI_EXP_SLTCAP_HPC
	.comm	_pcie_ports_native,8,3          ; @pcie_ports_native
.subsections_via_symbols
