	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ath5k_hw_commit_eeprom_settings
_ath5k_hw_commit_eeprom_settings:       ## @ath5k_hw_commit_eeprom_settings
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	(%rdi), %rax
	movq	_AR5K_AR5210@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_20
## %bb.1:
	movq	%rsi, %r15
	movq	%rdi, %r12
	callq	_ath5k_eeprom_mode_from_channel
	movq	%rax, %r14
	cmpl	$2484, (%r15)                   ## imm = 0x9B4
	movl	40(%r12), %eax
	jne	LBB0_3
## %bb.2:
	subl	44(%r12), %eax
LBB0_3:
	cltq
	imulq	$1717986919, %rax, %rbx         ## imm = 0x66666667
	movq	%rbx, %rax
	shrq	$63, %rax
	sarq	$33, %rbx
	addl	%eax, %ebx
	movq	8(%r12), %rax
	movq	_AR5K_SREV_PHY_5212A@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_5
## %bb.4:
	movl	%ebx, 32(%r12)
	movl	48(%r12), %eax
	movl	%eax, 36(%r12)
	jmp	LBB0_9
LBB0_5:
	movq	8(%r15), %rax
	movq	_AR5K_MODE_11G@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_7
## %bb.6:
	xorl	%edi, %edi
	subl	48(%r12), %edi
	movq	_AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_AR5K_REG_SM
	movl	%eax, %r13d
	negl	%ebx
	movq	_AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	%ebx, %edi
	callq	_AR5K_REG_SM
	orl	%eax, %r13d
	movq	_AR5K_PHY_TX_PWR_ADJ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	movl	%r13d, %esi
	jmp	LBB0_8
LBB0_7:
	movq	_AR5K_PHY_TX_PWR_ADJ@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%esi, %esi
LBB0_8:
	callq	_ath5k_hw_reg_write
LBB0_9:
	movq	%r12, %rdi
	movq	%r14, %rsi
	callq	_ath5k_hw_set_antenna_switch
	movq	192(%r12), %rax
	movl	(%rax,%r14,4), %edi
	callq	_AR5K_PHY_NF_SVAL
	movq	_AR5K_PHY_NFTHRES@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r12, %rdi
	movl	%eax, %esi
	callq	_ath5k_hw_reg_write
	movq	16(%r12), %rax
	movq	_AR5K_BWMODE_40MHZ@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_11
## %bb.10:
	movq	24(%r12), %rax
	movq	_AR5K_EEPROM_VERSION_5_0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_13
LBB0_11:
	movq	_AR5K_PHY_SETTLING@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_SETTLING_SWITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	144(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_PHY_GAIN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_GAIN_TXRX_ATTEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	136(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_PHY_DESIRED_SIZE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR5K_PHY_DESIRED_SIZE_ADC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	128(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movl	(%rbx), %esi
	movq	_AR5K_PHY_DESIRED_SIZE_PGA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	120(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	24(%r12), %rax
	movq	_AR5K_EEPROM_VERSION_4_1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_15
## %bb.12:
	movq	_AR5K_PHY_GAIN_2GHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	112(%r12), %rax
	jmp	LBB0_14
LBB0_13:
	movq	_AR5K_PHY_SETTLING@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_SETTLING_SWITCH@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	184(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_PHY_GAIN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_GAIN_TXRX_ATTEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	176(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_PHY_DESIRED_SIZE@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR5K_PHY_DESIRED_SIZE_ADC@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	168(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movl	(%rbx), %esi
	movq	_AR5K_PHY_DESIRED_SIZE_PGA@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	160(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_PHY_GAIN_2GHZ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	152(%r12), %rax
LBB0_14:
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
LBB0_15:
	movq	56(%r12), %rax
	movq	64(%r12), %rcx
	movl	(%rax,%r14,4), %eax
	movl	%eax, %edx
	shll	$24, %edx
	shll	$16, %eax
	orl	%edx, %eax
	movl	(%rcx,%r14,4), %ecx
	movl	%ecx, %esi
	shll	$8, %esi
	orl	%ecx, %esi
	orl	%eax, %esi
	movq	_AR5K_PHY_RF_CTL4@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_ath5k_hw_reg_write
	movq	_AR5K_PHY_RF_CTL3@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_RF_CTL3_TXE2XLNA_ON@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	104(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	_AR5K_PHY_NF@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_AR5K_PHY_NF_THRESH62@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	96(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	_ath5k_hw_chan_has_spur_noise
	movq	_AR5K_PHY_OFDM_SELFCORR@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movq	_AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	_AR5K_INIT_CYCRSSI_THR1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	testq	%rax, %rax
	je	LBB0_17
## %bb.16:
	movq	88(%r12), %rax
	addq	(%rax,%r14,8), %rcx
LBB0_17:
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movq	24(%r12), %rax
	movq	_AR5K_EEPROM_VERSION_4_0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jl	LBB0_19
## %bb.18:
	movq	_AR5K_PHY_IQ@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_AR5K_PHY_IQ_CORR_Q_I_COFF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	80(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movl	(%rbx), %esi
	movq	_AR5K_PHY_IQ_CORR_Q_Q_COFF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	72(%r12), %rax
	movq	(%rax,%r14,8), %rcx
	movq	%r12, %rdi
	callq	_AR5K_REG_WRITE_BITS
	movl	(%rbx), %esi
	movq	_AR5K_PHY_IQ_CORR_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	callq	_AR5K_REG_ENABLE_BITS
	movq	24(%r12), %rax
LBB0_19:
	movq	_AR5K_EEPROM_VERSION_5_1@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jge	LBB0_21
LBB0_20:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_21:
	movq	_AR5K_PHY_HEAVY_CLIP_ENABLE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r12, %rdi
	xorl	%esi, %esi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_ath5k_hw_reg_write             ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_AR5K_AR5210,8,3                ## @AR5K_AR5210
	.comm	_AR5K_SREV_PHY_5212A,8,3        ## @AR5K_SREV_PHY_5212A
	.comm	_AR5K_MODE_11G,8,3              ## @AR5K_MODE_11G
	.comm	_AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA,4,2 ## @AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA
	.comm	_AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX,4,2 ## @AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX
	.comm	_AR5K_PHY_TX_PWR_ADJ,4,2        ## @AR5K_PHY_TX_PWR_ADJ
	.comm	_AR5K_PHY_NFTHRES,4,2           ## @AR5K_PHY_NFTHRES
	.comm	_AR5K_BWMODE_40MHZ,8,3          ## @AR5K_BWMODE_40MHZ
	.comm	_AR5K_EEPROM_VERSION_5_0,8,3    ## @AR5K_EEPROM_VERSION_5_0
	.comm	_AR5K_PHY_SETTLING,4,2          ## @AR5K_PHY_SETTLING
	.comm	_AR5K_PHY_SETTLING_SWITCH,4,2   ## @AR5K_PHY_SETTLING_SWITCH
	.comm	_AR5K_PHY_GAIN,4,2              ## @AR5K_PHY_GAIN
	.comm	_AR5K_PHY_GAIN_TXRX_ATTEN,4,2   ## @AR5K_PHY_GAIN_TXRX_ATTEN
	.comm	_AR5K_PHY_DESIRED_SIZE,4,2      ## @AR5K_PHY_DESIRED_SIZE
	.comm	_AR5K_PHY_DESIRED_SIZE_ADC,4,2  ## @AR5K_PHY_DESIRED_SIZE_ADC
	.comm	_AR5K_PHY_DESIRED_SIZE_PGA,4,2  ## @AR5K_PHY_DESIRED_SIZE_PGA
	.comm	_AR5K_PHY_GAIN_2GHZ,4,2         ## @AR5K_PHY_GAIN_2GHZ
	.comm	_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,4,2 ## @AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
	.comm	_AR5K_EEPROM_VERSION_4_1,8,3    ## @AR5K_EEPROM_VERSION_4_1
	.comm	_AR5K_PHY_RF_CTL4,4,2           ## @AR5K_PHY_RF_CTL4
	.comm	_AR5K_PHY_RF_CTL3,4,2           ## @AR5K_PHY_RF_CTL3
	.comm	_AR5K_PHY_RF_CTL3_TXE2XLNA_ON,4,2 ## @AR5K_PHY_RF_CTL3_TXE2XLNA_ON
	.comm	_AR5K_PHY_NF,4,2                ## @AR5K_PHY_NF
	.comm	_AR5K_PHY_NF_THRESH62,4,2       ## @AR5K_PHY_NF_THRESH62
	.comm	_AR5K_PHY_OFDM_SELFCORR,4,2     ## @AR5K_PHY_OFDM_SELFCORR
	.comm	_AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,4,2 ## @AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1
	.comm	_AR5K_INIT_CYCRSSI_THR1,8,3     ## @AR5K_INIT_CYCRSSI_THR1
	.comm	_AR5K_EEPROM_VERSION_4_0,8,3    ## @AR5K_EEPROM_VERSION_4_0
	.comm	_AR5K_PHY_IQ,4,2                ## @AR5K_PHY_IQ
	.comm	_AR5K_PHY_IQ_CORR_Q_I_COFF,4,2  ## @AR5K_PHY_IQ_CORR_Q_I_COFF
	.comm	_AR5K_PHY_IQ_CORR_Q_Q_COFF,4,2  ## @AR5K_PHY_IQ_CORR_Q_Q_COFF
	.comm	_AR5K_PHY_IQ_CORR_ENABLE,4,2    ## @AR5K_PHY_IQ_CORR_ENABLE
	.comm	_AR5K_EEPROM_VERSION_5_1,8,3    ## @AR5K_EEPROM_VERSION_5_1
	.comm	_AR5K_PHY_HEAVY_CLIP_ENABLE,4,2 ## @AR5K_PHY_HEAVY_CLIP_ENABLE
	.no_dead_strip	_ath5k_hw_commit_eeprom_settings
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ath5k_hw_commit_eeprom_settings
_ath5k_hw_commit_eeprom_settings:       ; @ath5k_hw_commit_eeprom_settings
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _AR5K_AR5210@GOTPAGE
Lloh1:
	ldr	x9, [x9, _AR5K_AR5210@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	cmp	x8, x9
	b.eq	LBB0_20
; %bb.1:
	mov	x21, x1
	mov	x19, x0
	bl	_ath5k_eeprom_mode_from_channel
	mov	x20, x0
	ldr	w9, [x21]
	ldr	w8, [x19, #40]
	cmp	w9, #2484
	b.ne	LBB0_3
; %bb.2:
	ldr	w9, [x19, #44]
	sub	w8, w8, w9
LBB0_3:
	mov	w9, #26215
	movk	w9, #26214, lsl #16
	smull	x8, w8, w9
	lsr	x9, x8, #63
	asr	x8, x8, #33
	add	w23, w8, w9
	ldr	x8, [x19, #8]
Lloh3:
	adrp	x9, _AR5K_SREV_PHY_5212A@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AR5K_SREV_PHY_5212A@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_5
; %bb.4:
	ldr	w8, [x19, #48]
	stp	w23, w8, [x19, #32]
	b	LBB0_9
LBB0_5:
	ldr	x8, [x21, #8]
Lloh6:
	adrp	x9, _AR5K_MODE_11G@GOTPAGE
Lloh7:
	ldr	x9, [x9, _AR5K_MODE_11G@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_7
; %bb.6:
	ldr	w8, [x19, #48]
	neg	w0, w8
Lloh9:
	adrp	x8, _AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA@GOTPAGE
Lloh10:
	ldr	x8, [x8, _AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	mov	x22, x0
	neg	w0, w23
Lloh12:
	adrp	x8, _AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	bl	_AR5K_REG_SM
	orr	w1, w0, w22
Lloh15:
	adrp	x8, _AR5K_PHY_TX_PWR_ADJ@GOTPAGE
Lloh16:
	ldr	x8, [x8, _AR5K_PHY_TX_PWR_ADJ@GOTPAGEOFF]
Lloh17:
	ldr	w2, [x8]
	mov	x0, x19
	b	LBB0_8
LBB0_7:
Lloh18:
	adrp	x8, _AR5K_PHY_TX_PWR_ADJ@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AR5K_PHY_TX_PWR_ADJ@GOTPAGEOFF]
Lloh20:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
LBB0_8:
	bl	_ath5k_hw_reg_write
LBB0_9:
	mov	x0, x19
	mov	x1, x20
	bl	_ath5k_hw_set_antenna_switch
	ldr	x8, [x19, #192]
	ldr	w0, [x8, x20, lsl #2]
	bl	_AR5K_PHY_NF_SVAL
	mov	x1, x0
Lloh21:
	adrp	x8, _AR5K_PHY_NFTHRES@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AR5K_PHY_NFTHRES@GOTPAGEOFF]
Lloh23:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ath5k_hw_reg_write
	ldr	x8, [x19, #16]
Lloh24:
	adrp	x9, _AR5K_BWMODE_40MHZ@GOTPAGE
Lloh25:
	ldr	x9, [x9, _AR5K_BWMODE_40MHZ@GOTPAGEOFF]
Lloh26:
	ldr	x9, [x9]
	lsl	x22, x20, #3
	cmp	x8, x9
	b.ne	LBB0_11
; %bb.10:
	ldr	x8, [x19, #24]
Lloh27:
	adrp	x9, _AR5K_EEPROM_VERSION_5_0@GOTPAGE
Lloh28:
	ldr	x9, [x9, _AR5K_EEPROM_VERSION_5_0@GOTPAGEOFF]
Lloh29:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_13
LBB0_11:
Lloh30:
	adrp	x8, _AR5K_PHY_SETTLING@GOTPAGE
Lloh31:
	ldr	x8, [x8, _AR5K_PHY_SETTLING@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
Lloh33:
	adrp	x8, _AR5K_PHY_SETTLING_SWITCH@GOTPAGE
Lloh34:
	ldr	x8, [x8, _AR5K_PHY_SETTLING_SWITCH@GOTPAGEOFF]
Lloh35:
	ldr	w2, [x8]
	ldr	x8, [x19, #144]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
Lloh36:
	adrp	x8, _AR5K_PHY_GAIN@GOTPAGE
Lloh37:
	ldr	x8, [x8, _AR5K_PHY_GAIN@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
Lloh39:
	adrp	x8, _AR5K_PHY_GAIN_TXRX_ATTEN@GOTPAGE
Lloh40:
	ldr	x8, [x8, _AR5K_PHY_GAIN_TXRX_ATTEN@GOTPAGEOFF]
Lloh41:
	ldr	w2, [x8]
	ldr	x8, [x19, #136]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
Lloh42:
	adrp	x23, _AR5K_PHY_DESIRED_SIZE@GOTPAGE
Lloh43:
	ldr	x23, [x23, _AR5K_PHY_DESIRED_SIZE@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh44:
	adrp	x8, _AR5K_PHY_DESIRED_SIZE_ADC@GOTPAGE
Lloh45:
	ldr	x8, [x8, _AR5K_PHY_DESIRED_SIZE_ADC@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	ldr	x8, [x19, #128]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	w1, [x23]
Lloh47:
	adrp	x8, _AR5K_PHY_DESIRED_SIZE_PGA@GOTPAGE
Lloh48:
	ldr	x8, [x8, _AR5K_PHY_DESIRED_SIZE_PGA@GOTPAGEOFF]
Lloh49:
	ldr	w2, [x8]
	ldr	x8, [x19, #120]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	x8, [x19, #24]
Lloh50:
	adrp	x9, _AR5K_EEPROM_VERSION_4_1@GOTPAGE
Lloh51:
	ldr	x9, [x9, _AR5K_EEPROM_VERSION_4_1@GOTPAGEOFF]
Lloh52:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_15
; %bb.12:
Lloh53:
	adrp	x8, _AR5K_PHY_GAIN_2GHZ@GOTPAGE
Lloh54:
	ldr	x8, [x8, _AR5K_PHY_GAIN_2GHZ@GOTPAGEOFF]
Lloh55:
	ldr	w1, [x8]
Lloh56:
	adrp	x8, _AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX@GOTPAGE
Lloh57:
	ldr	x8, [x8, _AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX@GOTPAGEOFF]
Lloh58:
	ldr	w2, [x8]
	ldr	x8, [x19, #112]
	ldr	x3, [x8, x20, lsl #3]
	b	LBB0_14
LBB0_13:
Lloh59:
	adrp	x8, _AR5K_PHY_SETTLING@GOTPAGE
Lloh60:
	ldr	x8, [x8, _AR5K_PHY_SETTLING@GOTPAGEOFF]
Lloh61:
	ldr	w1, [x8]
Lloh62:
	adrp	x8, _AR5K_PHY_SETTLING_SWITCH@GOTPAGE
Lloh63:
	ldr	x8, [x8, _AR5K_PHY_SETTLING_SWITCH@GOTPAGEOFF]
Lloh64:
	ldr	w2, [x8]
	ldr	x8, [x19, #184]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
Lloh65:
	adrp	x8, _AR5K_PHY_GAIN@GOTPAGE
Lloh66:
	ldr	x8, [x8, _AR5K_PHY_GAIN@GOTPAGEOFF]
Lloh67:
	ldr	w1, [x8]
Lloh68:
	adrp	x8, _AR5K_PHY_GAIN_TXRX_ATTEN@GOTPAGE
Lloh69:
	ldr	x8, [x8, _AR5K_PHY_GAIN_TXRX_ATTEN@GOTPAGEOFF]
Lloh70:
	ldr	w2, [x8]
	ldr	x8, [x19, #176]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
Lloh71:
	adrp	x23, _AR5K_PHY_DESIRED_SIZE@GOTPAGE
Lloh72:
	ldr	x23, [x23, _AR5K_PHY_DESIRED_SIZE@GOTPAGEOFF]
	ldr	w1, [x23]
Lloh73:
	adrp	x8, _AR5K_PHY_DESIRED_SIZE_ADC@GOTPAGE
Lloh74:
	ldr	x8, [x8, _AR5K_PHY_DESIRED_SIZE_ADC@GOTPAGEOFF]
Lloh75:
	ldr	w2, [x8]
	ldr	x8, [x19, #168]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	w1, [x23]
Lloh76:
	adrp	x8, _AR5K_PHY_DESIRED_SIZE_PGA@GOTPAGE
Lloh77:
	ldr	x8, [x8, _AR5K_PHY_DESIRED_SIZE_PGA@GOTPAGEOFF]
Lloh78:
	ldr	w2, [x8]
	ldr	x8, [x19, #160]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
Lloh79:
	adrp	x8, _AR5K_PHY_GAIN_2GHZ@GOTPAGE
Lloh80:
	ldr	x8, [x8, _AR5K_PHY_GAIN_2GHZ@GOTPAGEOFF]
Lloh81:
	ldr	w1, [x8]
Lloh82:
	adrp	x8, _AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX@GOTPAGE
Lloh83:
	ldr	x8, [x8, _AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX@GOTPAGEOFF]
Lloh84:
	ldr	w2, [x8]
	ldr	x8, [x19, #152]
	ldr	x3, [x8, x22]
LBB0_14:
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
LBB0_15:
	lsl	x8, x20, #2
	ldp	x9, x10, [x19, #56]
	ldr	w9, [x9, x8]
	lsl	w11, w9, #24
	ldr	w8, [x10, x8]
	orr	w9, w11, w9, lsl #16
	orr	w9, w9, w8
	orr	w1, w9, w8, lsl #8
Lloh85:
	adrp	x8, _AR5K_PHY_RF_CTL4@GOTPAGE
Lloh86:
	ldr	x8, [x8, _AR5K_PHY_RF_CTL4@GOTPAGEOFF]
Lloh87:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ath5k_hw_reg_write
Lloh88:
	adrp	x8, _AR5K_PHY_RF_CTL3@GOTPAGE
Lloh89:
	ldr	x8, [x8, _AR5K_PHY_RF_CTL3@GOTPAGEOFF]
Lloh90:
	ldr	w1, [x8]
Lloh91:
	adrp	x8, _AR5K_PHY_RF_CTL3_TXE2XLNA_ON@GOTPAGE
Lloh92:
	ldr	x8, [x8, _AR5K_PHY_RF_CTL3_TXE2XLNA_ON@GOTPAGEOFF]
Lloh93:
	ldr	w2, [x8]
	ldr	x8, [x19, #104]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
Lloh94:
	adrp	x8, _AR5K_PHY_NF@GOTPAGE
Lloh95:
	ldr	x8, [x8, _AR5K_PHY_NF@GOTPAGEOFF]
Lloh96:
	ldr	w1, [x8]
Lloh97:
	adrp	x8, _AR5K_PHY_NF_THRESH62@GOTPAGE
Lloh98:
	ldr	x8, [x8, _AR5K_PHY_NF_THRESH62@GOTPAGEOFF]
Lloh99:
	ldr	w2, [x8]
	ldr	x8, [x19, #96]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	mov	x0, x19
	mov	x1, x21
	bl	_ath5k_hw_chan_has_spur_noise
Lloh100:
	adrp	x8, _AR5K_PHY_OFDM_SELFCORR@GOTPAGE
Lloh101:
	ldr	x8, [x8, _AR5K_PHY_OFDM_SELFCORR@GOTPAGEOFF]
Lloh102:
	ldr	w1, [x8]
Lloh103:
	adrp	x8, _AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1@GOTPAGE
Lloh104:
	ldr	x8, [x8, _AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1@GOTPAGEOFF]
Lloh105:
	ldr	w2, [x8]
Lloh106:
	adrp	x8, _AR5K_INIT_CYCRSSI_THR1@GOTPAGE
Lloh107:
	ldr	x8, [x8, _AR5K_INIT_CYCRSSI_THR1@GOTPAGEOFF]
Lloh108:
	ldr	x3, [x8]
	cbz	x0, LBB0_17
; %bb.16:
	ldr	x8, [x19, #88]
	ldr	x8, [x8, x20, lsl #3]
	add	x3, x8, x3
LBB0_17:
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	x8, [x19, #24]
Lloh109:
	adrp	x9, _AR5K_EEPROM_VERSION_4_0@GOTPAGE
Lloh110:
	ldr	x9, [x9, _AR5K_EEPROM_VERSION_4_0@GOTPAGEOFF]
Lloh111:
	ldr	x9, [x9]
	cmp	x8, x9
	b.lt	LBB0_19
; %bb.18:
Lloh112:
	adrp	x20, _AR5K_PHY_IQ@GOTPAGE
Lloh113:
	ldr	x20, [x20, _AR5K_PHY_IQ@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh114:
	adrp	x8, _AR5K_PHY_IQ_CORR_Q_I_COFF@GOTPAGE
Lloh115:
	ldr	x8, [x8, _AR5K_PHY_IQ_CORR_Q_I_COFF@GOTPAGEOFF]
Lloh116:
	ldr	w2, [x8]
	ldr	x8, [x19, #80]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	w1, [x20]
Lloh117:
	adrp	x8, _AR5K_PHY_IQ_CORR_Q_Q_COFF@GOTPAGE
Lloh118:
	ldr	x8, [x8, _AR5K_PHY_IQ_CORR_Q_Q_COFF@GOTPAGEOFF]
Lloh119:
	ldr	w2, [x8]
	ldr	x8, [x19, #72]
	ldr	x3, [x8, x22]
	mov	x0, x19
	bl	_AR5K_REG_WRITE_BITS
	ldr	w1, [x20]
Lloh120:
	adrp	x8, _AR5K_PHY_IQ_CORR_ENABLE@GOTPAGE
Lloh121:
	ldr	x8, [x8, _AR5K_PHY_IQ_CORR_ENABLE@GOTPAGEOFF]
Lloh122:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_AR5K_REG_ENABLE_BITS
	ldr	x8, [x19, #24]
LBB0_19:
Lloh123:
	adrp	x9, _AR5K_EEPROM_VERSION_5_1@GOTPAGE
Lloh124:
	ldr	x9, [x9, _AR5K_EEPROM_VERSION_5_1@GOTPAGEOFF]
Lloh125:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ge	LBB0_21
LBB0_20:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_21:
Lloh126:
	adrp	x8, _AR5K_PHY_HEAVY_CLIP_ENABLE@GOTPAGE
Lloh127:
	ldr	x8, [x8, _AR5K_PHY_HEAVY_CLIP_ENABLE@GOTPAGEOFF]
Lloh128:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_ath5k_hw_reg_write
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh50, Lloh51, Lloh52
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh49
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGot	Lloh42, Lloh43
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh56, Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh53, Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGot	Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh68, Lloh69, Lloh70
	.loh AdrpLdrGotLdr	Lloh65, Lloh66, Lloh67
	.loh AdrpLdrGotLdr	Lloh62, Lloh63, Lloh64
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh106, Lloh107, Lloh108
	.loh AdrpLdrGotLdr	Lloh103, Lloh104, Lloh105
	.loh AdrpLdrGotLdr	Lloh100, Lloh101, Lloh102
	.loh AdrpLdrGotLdr	Lloh97, Lloh98, Lloh99
	.loh AdrpLdrGotLdr	Lloh94, Lloh95, Lloh96
	.loh AdrpLdrGotLdr	Lloh91, Lloh92, Lloh93
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh109, Lloh110, Lloh111
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGot	Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh126, Lloh127, Lloh128
	.cfi_endproc
                                        ; -- End function
	.comm	_AR5K_AR5210,8,3                ; @AR5K_AR5210
	.comm	_AR5K_SREV_PHY_5212A,8,3        ; @AR5K_SREV_PHY_5212A
	.comm	_AR5K_MODE_11G,8,3              ; @AR5K_MODE_11G
	.comm	_AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA,4,2 ; @AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA
	.comm	_AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX,4,2 ; @AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX
	.comm	_AR5K_PHY_TX_PWR_ADJ,4,2        ; @AR5K_PHY_TX_PWR_ADJ
	.comm	_AR5K_PHY_NFTHRES,4,2           ; @AR5K_PHY_NFTHRES
	.comm	_AR5K_BWMODE_40MHZ,8,3          ; @AR5K_BWMODE_40MHZ
	.comm	_AR5K_EEPROM_VERSION_5_0,8,3    ; @AR5K_EEPROM_VERSION_5_0
	.comm	_AR5K_PHY_SETTLING,4,2          ; @AR5K_PHY_SETTLING
	.comm	_AR5K_PHY_SETTLING_SWITCH,4,2   ; @AR5K_PHY_SETTLING_SWITCH
	.comm	_AR5K_PHY_GAIN,4,2              ; @AR5K_PHY_GAIN
	.comm	_AR5K_PHY_GAIN_TXRX_ATTEN,4,2   ; @AR5K_PHY_GAIN_TXRX_ATTEN
	.comm	_AR5K_PHY_DESIRED_SIZE,4,2      ; @AR5K_PHY_DESIRED_SIZE
	.comm	_AR5K_PHY_DESIRED_SIZE_ADC,4,2  ; @AR5K_PHY_DESIRED_SIZE_ADC
	.comm	_AR5K_PHY_DESIRED_SIZE_PGA,4,2  ; @AR5K_PHY_DESIRED_SIZE_PGA
	.comm	_AR5K_PHY_GAIN_2GHZ,4,2         ; @AR5K_PHY_GAIN_2GHZ
	.comm	_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,4,2 ; @AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX
	.comm	_AR5K_EEPROM_VERSION_4_1,8,3    ; @AR5K_EEPROM_VERSION_4_1
	.comm	_AR5K_PHY_RF_CTL4,4,2           ; @AR5K_PHY_RF_CTL4
	.comm	_AR5K_PHY_RF_CTL3,4,2           ; @AR5K_PHY_RF_CTL3
	.comm	_AR5K_PHY_RF_CTL3_TXE2XLNA_ON,4,2 ; @AR5K_PHY_RF_CTL3_TXE2XLNA_ON
	.comm	_AR5K_PHY_NF,4,2                ; @AR5K_PHY_NF
	.comm	_AR5K_PHY_NF_THRESH62,4,2       ; @AR5K_PHY_NF_THRESH62
	.comm	_AR5K_PHY_OFDM_SELFCORR,4,2     ; @AR5K_PHY_OFDM_SELFCORR
	.comm	_AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,4,2 ; @AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1
	.comm	_AR5K_INIT_CYCRSSI_THR1,8,3     ; @AR5K_INIT_CYCRSSI_THR1
	.comm	_AR5K_EEPROM_VERSION_4_0,8,3    ; @AR5K_EEPROM_VERSION_4_0
	.comm	_AR5K_PHY_IQ,4,2                ; @AR5K_PHY_IQ
	.comm	_AR5K_PHY_IQ_CORR_Q_I_COFF,4,2  ; @AR5K_PHY_IQ_CORR_Q_I_COFF
	.comm	_AR5K_PHY_IQ_CORR_Q_Q_COFF,4,2  ; @AR5K_PHY_IQ_CORR_Q_Q_COFF
	.comm	_AR5K_PHY_IQ_CORR_ENABLE,4,2    ; @AR5K_PHY_IQ_CORR_ENABLE
	.comm	_AR5K_EEPROM_VERSION_5_1,8,3    ; @AR5K_EEPROM_VERSION_5_1
	.comm	_AR5K_PHY_HEAVY_CLIP_ENABLE,4,2 ; @AR5K_PHY_HEAVY_CLIP_ENABLE
	.no_dead_strip	_ath5k_hw_commit_eeprom_settings
.subsections_via_symbols
