	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dw_pcie_setup                  ## -- Begin function dw_pcie_setup
	.p2align	4, 0x90
_dw_pcie_setup:                         ## @dw_pcie_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	8(%rdi), %rax
	movq	(%rax), %r14
	movl	(%rdi), %eax
	cmpl	$18441, %eax                    ## imm = 0x4809
	jle	LBB0_1
LBB0_3:
	movl	$1, 4(%rbx)
	cmpq	$0, 24(%rbx)
	jne	LBB0_5
## %bb.4:
	movq	_DEFAULT_DBI_ATU_OFFSET@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	addq	16(%rbx), %rax
	movq	%rax, 24(%rbx)
	jmp	LBB0_5
LBB0_1:
	testl	%eax, %eax
	je	LBB0_2
LBB0_5:
	movq	8(%rbx), %rdi
	cmpl	$0, 4(%rbx)
	leaq	L_.str.2(%rip), %rax
	leaq	L_.str.1(%rip), %rdx
	cmoveq	%rax, %rdx
	leaq	L_.str(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_dbg
	leaq	L_.str.3(%rip), %rsi
	leaq	-28(%rbp), %rdx
	movq	%r14, %rdi
	callq	_of_property_read_u32
	testl	%eax, %eax
	je	LBB0_7
## %bb.6:
	movq	8(%rbx), %rdi
	leaq	L_.str.4(%rip), %rsi
	xorl	%eax, %eax
	callq	_dev_dbg
	jmp	LBB0_19
LBB0_7:
	movq	_PCIE_PORT_LINK_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movl	-28(%rbp), %edx
	leal	-1(%rdx), %ecx
	cmpl	$8, %ecx
	jae	LBB0_8
## %bb.9:
	movl	$139, %esi
	btl	%ecx, %esi
	jb	LBB0_10
LBB0_8:
	movq	8(%rbx), %rdi
	leaq	L_.str.5(%rip), %rsi
                                        ## kill: def $edx killed $edx killed $rdx
	callq	_dev_err
LBB0_19:
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_2:
	movq	%rbx, %rdi
	callq	_dw_pcie_iatu_unroll_enabled
	testq	%rax, %rax
	jne	LBB0_3
	jmp	LBB0_5
LBB0_10:
	movq	_PORT_LINK_MODE_MASK@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	notl	%edx
	andl	%edx, %eax
	movslq	%ecx, %rcx
	leaq	l_switch.table.dw_pcie_setup(%rip), %rdx
	movq	(%rdx,%rcx,8), %rcx
	orl	(%rcx), %eax
	movl	(%r15), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi
	movq	_PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PORT_LOGIC_LINK_WIDTH_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	notl	%edx
	andl	%eax, %edx
	movl	-28(%rbp), %eax
	decl	%eax
	cmpl	$7, %eax
	ja	LBB0_17
## %bb.11:
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_12:
	movq	_PORT_LOGIC_LINK_WIDTH_1_LANES@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_13:
	movq	_PORT_LOGIC_LINK_WIDTH_2_LANES@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_14:
	movq	_PORT_LOGIC_LINK_WIDTH_4_LANES@GOTPCREL(%rip), %rax
	jmp	LBB0_16
LBB0_15:
	movq	_PORT_LOGIC_LINK_WIDTH_8_LANES@GOTPCREL(%rip), %rax
LBB0_16:
	orl	(%rax), %edx
LBB0_17:
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_writel_dbi
	leaq	L_.str.6(%rip), %rsi
	movq	%r14, %rdi
	callq	_of_property_read_bool
	testq	%rax, %rax
	je	LBB0_19
## %bb.18:
	movq	_PCIE_PL_CHK_REG_CONTROL_STATUS@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%rbx, %rdi
	callq	_dw_pcie_readl_dbi
	movq	_PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_PCIE_PL_CHK_REG_CHK_REG_START@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	(%r14), %esi
	movq	%rbx, %rdi
	movl	%eax, %edx
	callq	_dw_pcie_writel_dbi
	jmp	LBB0_19
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_15, LBB0_15-LJTI0_0
LJTI0_0:
	.long	L0_0_set_12
	.long	L0_0_set_13
	.long	L0_0_set_17
	.long	L0_0_set_14
	.long	L0_0_set_17
	.long	L0_0_set_17
	.long	L0_0_set_17
	.long	L0_0_set_15
	.end_data_region
                                        ## -- End function
	.comm	_DEFAULT_DBI_ATU_OFFSET,8,3     ## @DEFAULT_DBI_ATU_OFFSET
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"iATU unroll: %s\n"

L_.str.1:                               ## @.str.1
	.asciz	"enabled"

L_.str.2:                               ## @.str.2
	.asciz	"disabled"

L_.str.3:                               ## @.str.3
	.asciz	"num-lanes"

L_.str.4:                               ## @.str.4
	.asciz	"property num-lanes isn't found\n"

	.comm	_PCIE_PORT_LINK_CONTROL,4,2     ## @PCIE_PORT_LINK_CONTROL
	.comm	_PORT_LINK_MODE_MASK,4,2        ## @PORT_LINK_MODE_MASK
	.comm	_PORT_LINK_MODE_1_LANES,4,2     ## @PORT_LINK_MODE_1_LANES
	.comm	_PORT_LINK_MODE_2_LANES,4,2     ## @PORT_LINK_MODE_2_LANES
	.comm	_PORT_LINK_MODE_4_LANES,4,2     ## @PORT_LINK_MODE_4_LANES
	.comm	_PORT_LINK_MODE_8_LANES,4,2     ## @PORT_LINK_MODE_8_LANES
L_.str.5:                               ## @.str.5
	.asciz	"num-lanes %u: invalid value\n"

	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,4,2 ## @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_PORT_LOGIC_LINK_WIDTH_MASK,4,2 ## @PORT_LOGIC_LINK_WIDTH_MASK
	.comm	_PORT_LOGIC_LINK_WIDTH_1_LANES,4,2 ## @PORT_LOGIC_LINK_WIDTH_1_LANES
	.comm	_PORT_LOGIC_LINK_WIDTH_2_LANES,4,2 ## @PORT_LOGIC_LINK_WIDTH_2_LANES
	.comm	_PORT_LOGIC_LINK_WIDTH_4_LANES,4,2 ## @PORT_LOGIC_LINK_WIDTH_4_LANES
	.comm	_PORT_LOGIC_LINK_WIDTH_8_LANES,4,2 ## @PORT_LOGIC_LINK_WIDTH_8_LANES
L_.str.6:                               ## @.str.6
	.asciz	"snps,enable-cdm-check"

	.comm	_PCIE_PL_CHK_REG_CONTROL_STATUS,4,2 ## @PCIE_PL_CHK_REG_CONTROL_STATUS
	.comm	_PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS,4,2 ## @PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS
	.comm	_PCIE_PL_CHK_REG_CHK_REG_START,4,2 ## @PCIE_PL_CHK_REG_CHK_REG_START
	.section	__DATA,__const
	.p2align	3                               ## @switch.table.dw_pcie_setup
l_switch.table.dw_pcie_setup:
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_2_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_4_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_8_LANES

.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_dw_pcie_setup                  ; -- Begin function dw_pcie_setup
	.p2align	2
_dw_pcie_setup:                         ; @dw_pcie_setup
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0, #8]
	ldr	x20, [x8]
	ldr	w8, [x0]
	mov	w9, #18441
	cmp	w8, w9
	b.le	LBB0_3
LBB0_1:
	mov	w8, #1
	str	w8, [x19, #4]
	ldr	x8, [x19, #24]
	cbnz	x8, LBB0_4
; %bb.2:
	ldr	x8, [x19, #16]
Lloh0:
	adrp	x9, _DEFAULT_DBI_ATU_OFFSET@GOTPAGE
Lloh1:
	ldr	x9, [x9, _DEFAULT_DBI_ATU_OFFSET@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	add	x8, x9, x8
	str	x8, [x19, #24]
	b	LBB0_4
LBB0_3:
	cbz	w8, LBB0_10
LBB0_4:
	ldr	x0, [x19, #8]
	ldr	w8, [x19, #4]
Lloh3:
	adrp	x9, l_.str.1@PAGE
Lloh4:
	add	x9, x9, l_.str.1@PAGEOFF
Lloh5:
	adrp	x10, l_.str.2@PAGE
Lloh6:
	add	x10, x10, l_.str.2@PAGEOFF
	cmp	w8, #0
	csel	x8, x10, x9, eq
	str	x8, [sp]
Lloh7:
	adrp	x1, l_.str@PAGE
Lloh8:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_dbg
Lloh9:
	adrp	x1, l_.str.3@PAGE
Lloh10:
	add	x1, x1, l_.str.3@PAGEOFF
	add	x2, sp, #12
	mov	x0, x20
	bl	_of_property_read_u32
	cbz	w0, LBB0_6
; %bb.5:
	ldr	x0, [x19, #8]
Lloh11:
	adrp	x1, l_.str.4@PAGE
Lloh12:
	add	x1, x1, l_.str.4@PAGEOFF
	bl	_dev_dbg
	b	LBB0_9
LBB0_6:
Lloh13:
	adrp	x21, _PCIE_PORT_LINK_CONTROL@GOTPAGE
Lloh14:
	ldr	x21, [x21, _PCIE_PORT_LINK_CONTROL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
	ldr	w2, [sp, #12]
	sub	w8, w2, #1
	cmp	w8, #8
	b.hs	LBB0_8
; %bb.7:
	mov	w9, #139
	lsr	w9, w9, w8
	tbnz	w9, #0, LBB0_11
LBB0_8:
	ldr	x0, [x19, #8]
Lloh15:
	adrp	x1, l_.str.5@PAGE
Lloh16:
	add	x1, x1, l_.str.5@PAGEOFF
	bl	_dev_err
LBB0_9:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
LBB0_10:
	mov	x0, x19
	bl	_dw_pcie_iatu_unroll_enabled
	cbnz	x0, LBB0_1
	b	LBB0_4
LBB0_11:
Lloh17:
	adrp	x9, _PORT_LINK_MODE_MASK@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PORT_LINK_MODE_MASK@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
Lloh20:
	adrp	x10, l_switch.table.dw_pcie_setup@PAGE
Lloh21:
	add	x10, x10, l_switch.table.dw_pcie_setup@PAGEOFF
	bic	w9, w0, w9
	ldr	x8, [x10, w8, sxtw #3]
	ldr	w8, [x8]
	orr	w2, w8, w9
	ldr	w1, [x21]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
Lloh22:
	adrp	x21, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGE
Lloh23:
	ldr	x21, [x21, _PCIE_LINK_WIDTH_SPEED_CONTROL@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh24:
	adrp	x8, _PORT_LOGIC_LINK_WIDTH_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PORT_LOGIC_LINK_WIDTH_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
	bic	w2, w0, w8
	ldr	w8, [sp, #12]
	sub	w8, w8, #1
	cmp	w8, #7
	b.hi	LBB0_18
; %bb.12:
Lloh27:
	adrp	x9, lJTI0_0@PAGE
Lloh28:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_13
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_13:
Lloh29:
	adrp	x8, _PORT_LOGIC_LINK_WIDTH_1_LANES@GOTPAGE
Lloh30:
	ldr	x8, [x8, _PORT_LOGIC_LINK_WIDTH_1_LANES@GOTPAGEOFF]
	b	LBB0_17
LBB0_14:
Lloh31:
	adrp	x8, _PORT_LOGIC_LINK_WIDTH_2_LANES@GOTPAGE
Lloh32:
	ldr	x8, [x8, _PORT_LOGIC_LINK_WIDTH_2_LANES@GOTPAGEOFF]
	b	LBB0_17
LBB0_15:
Lloh33:
	adrp	x8, _PORT_LOGIC_LINK_WIDTH_4_LANES@GOTPAGE
Lloh34:
	ldr	x8, [x8, _PORT_LOGIC_LINK_WIDTH_4_LANES@GOTPAGEOFF]
	b	LBB0_17
LBB0_16:
Lloh35:
	adrp	x8, _PORT_LOGIC_LINK_WIDTH_8_LANES@GOTPAGE
Lloh36:
	ldr	x8, [x8, _PORT_LOGIC_LINK_WIDTH_8_LANES@GOTPAGEOFF]
LBB0_17:
	ldr	w8, [x8]
	orr	w2, w8, w2
LBB0_18:
	ldr	w1, [x21]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
Lloh37:
	adrp	x1, l_.str.6@PAGE
Lloh38:
	add	x1, x1, l_.str.6@PAGEOFF
	mov	x0, x20
	bl	_of_property_read_bool
	cbz	x0, LBB0_9
; %bb.19:
Lloh39:
	adrp	x20, _PCIE_PL_CHK_REG_CONTROL_STATUS@GOTPAGE
Lloh40:
	ldr	x20, [x20, _PCIE_PL_CHK_REG_CONTROL_STATUS@GOTPAGEOFF]
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_readl_dbi
Lloh41:
	adrp	x8, _PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS@GOTPAGE
Lloh42:
	ldr	x8, [x8, _PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
Lloh44:
	adrp	x9, _PCIE_PL_CHK_REG_CHK_REG_START@GOTPAGE
Lloh45:
	ldr	x9, [x9, _PCIE_PL_CHK_REG_CHK_REG_START@GOTPAGEOFF]
Lloh46:
	ldr	w9, [x9]
	orr	w8, w8, w0
	orr	w2, w8, w9
	ldr	w1, [x20]
	mov	x0, x19
	bl	_dw_pcie_writel_dbi
	b	LBB0_9
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh7, Lloh8
	.loh AdrpAdd	Lloh5, Lloh6
	.loh AdrpAdd	Lloh3, Lloh4
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpAdd	Lloh15, Lloh16
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpAdd	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpAdd	Lloh27, Lloh28
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGot	Lloh33, Lloh34
	.loh AdrpLdrGot	Lloh35, Lloh36
	.loh AdrpAdd	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_13-LBB0_13)>>2
	.byte	(LBB0_14-LBB0_13)>>2
	.byte	(LBB0_18-LBB0_13)>>2
	.byte	(LBB0_15-LBB0_13)>>2
	.byte	(LBB0_18-LBB0_13)>>2
	.byte	(LBB0_18-LBB0_13)>>2
	.byte	(LBB0_18-LBB0_13)>>2
	.byte	(LBB0_16-LBB0_13)>>2
                                        ; -- End function
	.comm	_DEFAULT_DBI_ATU_OFFSET,8,3     ; @DEFAULT_DBI_ATU_OFFSET
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"iATU unroll: %s\n"

l_.str.1:                               ; @.str.1
	.asciz	"enabled"

l_.str.2:                               ; @.str.2
	.asciz	"disabled"

l_.str.3:                               ; @.str.3
	.asciz	"num-lanes"

l_.str.4:                               ; @.str.4
	.asciz	"property num-lanes isn't found\n"

	.comm	_PCIE_PORT_LINK_CONTROL,4,2     ; @PCIE_PORT_LINK_CONTROL
	.comm	_PORT_LINK_MODE_MASK,4,2        ; @PORT_LINK_MODE_MASK
	.comm	_PORT_LINK_MODE_1_LANES,4,2     ; @PORT_LINK_MODE_1_LANES
	.comm	_PORT_LINK_MODE_2_LANES,4,2     ; @PORT_LINK_MODE_2_LANES
	.comm	_PORT_LINK_MODE_4_LANES,4,2     ; @PORT_LINK_MODE_4_LANES
	.comm	_PORT_LINK_MODE_8_LANES,4,2     ; @PORT_LINK_MODE_8_LANES
l_.str.5:                               ; @.str.5
	.asciz	"num-lanes %u: invalid value\n"

	.comm	_PCIE_LINK_WIDTH_SPEED_CONTROL,4,2 ; @PCIE_LINK_WIDTH_SPEED_CONTROL
	.comm	_PORT_LOGIC_LINK_WIDTH_MASK,4,2 ; @PORT_LOGIC_LINK_WIDTH_MASK
	.comm	_PORT_LOGIC_LINK_WIDTH_1_LANES,4,2 ; @PORT_LOGIC_LINK_WIDTH_1_LANES
	.comm	_PORT_LOGIC_LINK_WIDTH_2_LANES,4,2 ; @PORT_LOGIC_LINK_WIDTH_2_LANES
	.comm	_PORT_LOGIC_LINK_WIDTH_4_LANES,4,2 ; @PORT_LOGIC_LINK_WIDTH_4_LANES
	.comm	_PORT_LOGIC_LINK_WIDTH_8_LANES,4,2 ; @PORT_LOGIC_LINK_WIDTH_8_LANES
l_.str.6:                               ; @.str.6
	.asciz	"snps,enable-cdm-check"

	.comm	_PCIE_PL_CHK_REG_CONTROL_STATUS,4,2 ; @PCIE_PL_CHK_REG_CONTROL_STATUS
	.comm	_PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS,4,2 ; @PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS
	.comm	_PCIE_PL_CHK_REG_CHK_REG_START,4,2 ; @PCIE_PL_CHK_REG_CHK_REG_START
	.section	__DATA,__const
	.p2align	3                               ; @switch.table.dw_pcie_setup
l_switch.table.dw_pcie_setup:
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_2_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_4_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_1_LANES
	.quad	_PORT_LINK_MODE_8_LANES

.subsections_via_symbols
