	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mlxsw_pci_config_profile
_mlxsw_pci_config_profile:              ## @mlxsw_pci_config_profile
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rcx, %r12
	movq	%rdx, %rbx
	movq	%rsi, %r13
	movq	%rdi, %r15
	movq	%rsi, %rdi
	callq	_mlxsw_cmd_mbox_zero
	cmpq	$0, 216(%rbx)
	je	LBB0_2
## %bb.1:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set
	movl	208(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_vepa_channels_set
LBB0_2:
	cmpq	$0, 200(%rbx)
	je	LBB0_4
## %bb.3:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_mid_set
	movl	192(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_mid_set
LBB0_4:
	cmpq	$0, 184(%rbx)
	je	LBB0_6
## %bb.5:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_pgt_set
	movl	176(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_pgt_set
LBB0_6:
	cmpq	$0, 168(%rbx)
	je	LBB0_8
## %bb.7:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_system_port_set
	movl	160(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_system_port_set
LBB0_8:
	cmpq	$0, 152(%rbx)
	je	LBB0_10
## %bb.9:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set
	movl	144(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_vlan_groups_set
LBB0_10:
	cmpq	$0, 136(%rbx)
	je	LBB0_12
## %bb.11:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_regions_set
	movl	128(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_regions_set
LBB0_12:
	cmpq	$0, 120(%rbx)
	je	LBB0_14
## %bb.13:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_flood_tables_set
	movl	116(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_flood_tables_set
	movl	112(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set
	movl	108(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set
	movl	104(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set
	movl	100(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set
	movl	96(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set
LBB0_14:
	cmpq	$0, 88(%rbx)
	je	LBB0_16
## %bb.15:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_flood_mode_set
	movl	80(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_flood_mode_set
LBB0_16:
	cmpq	$0, 72(%rbx)
	je	LBB0_18
## %bb.17:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set
	movl	64(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_ib_mc_set
LBB0_18:
	cmpq	$0, 56(%rbx)
	je	LBB0_20
## %bb.19:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_max_pkey_set
	movl	48(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_max_pkey_set
LBB0_20:
	cmpq	$0, 40(%rbx)
	je	LBB0_22
## %bb.21:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_ar_sec_set
	movl	32(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_ar_sec_set
LBB0_22:
	cmpq	$0, 24(%rbx)
	je	LBB0_24
## %bb.23:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set
	movl	16(%rbx), %esi
	movq	%r13, %rdi
	callq	_mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set
LBB0_24:
	cmpq	$0, 8(%rbx)
	je	LBB0_28
## %bb.25:
	movq	_KVD_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_MLXSW_RES_VALID
	testq	%rax, %rax
	je	LBB0_28
## %bb.26:
	movq	%r15, %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	callq	_mlxsw_pci_profile_get_kvd_sizes
	testl	%eax, %eax
	je	LBB0_27
## %bb.34:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_27:
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set
	movq	_KVD_LINEAR_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_MLXSW_RES_GET
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_mlxsw_cmd_mbox_config_profile_kvd_linear_size_set
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set
	movq	_KVD_SINGLE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_MLXSW_RES_GET
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set
	movq	%r13, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set
	movq	_KVD_DOUBLE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_MLXSW_RES_GET
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set
LBB0_28:
	movq	_MLXSW_CONFIG_PROFILE_SWID_COUNT@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	movq	%r15, %rdx
	movq	%r13, %r12
	jle	LBB0_31
## %bb.29:
	movq	%rbx, %r15
	xorl	%r14d, %r14d
	xorl	%ebx, %ebx
	.p2align	4, 0x90
LBB0_30:                                ## =>This Inner Loop Header: Depth=1
	movq	(%r15), %rcx
	addq	%r14, %rcx
	movq	%rdx, %r13
	movq	%rdx, %rdi
	movq	%r12, %rsi
	movl	%ebx, %edx
	callq	_mlxsw_pci_config_profile_swid_config
	movq	%r13, %rdx
	movq	_MLXSW_CONFIG_PROFILE_SWID_COUNT@GOTPCREL(%rip), %rax
	incq	%rbx
	movslq	(%rax), %rax
	addq	$4, %r14
	cmpq	%rax, %rbx
	jl	LBB0_30
LBB0_31:
	movq	(%rdx), %rax
	movq	_MLXSW_PCI_CQE_V0@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	movq	%rdx, %r15
	jle	LBB0_33
## %bb.32:
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_set_cqe_version_set
	movq	%r12, %rdi
	movl	$1, %esi
	callq	_mlxsw_cmd_mbox_config_profile_cqe_version_set
LBB0_33:
	movl	8(%r15), %edi
	movq	%r12, %rsi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mlxsw_cmd_config_profile_set   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_KVD_SIZE,4,2                   ## @KVD_SIZE
	.comm	_KVD_LINEAR_SIZE,4,2            ## @KVD_LINEAR_SIZE
	.comm	_KVD_SINGLE_SIZE,4,2            ## @KVD_SINGLE_SIZE
	.comm	_KVD_DOUBLE_SIZE,4,2            ## @KVD_DOUBLE_SIZE
	.comm	_MLXSW_CONFIG_PROFILE_SWID_COUNT,4,2 ## @MLXSW_CONFIG_PROFILE_SWID_COUNT
	.comm	_MLXSW_PCI_CQE_V0,8,3           ## @MLXSW_PCI_CQE_V0
	.no_dead_strip	_mlxsw_pci_config_profile
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mlxsw_pci_config_profile
_mlxsw_pci_config_profile:              ; @mlxsw_pci_config_profile
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x22, x3
	mov	x21, x2
	mov	x19, x1
	mov	x20, x0
	mov	x0, x1
	bl	_mlxsw_cmd_mbox_zero
	ldr	x8, [x21, #216]
	cbz	x8, LBB0_2
; %bb.1:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_vepa_channels_set
	ldr	w1, [x21, #208]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_vepa_channels_set
LBB0_2:
	ldr	x8, [x21, #200]
	cbz	x8, LBB0_4
; %bb.3:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_mid_set
	ldr	w1, [x21, #192]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_mid_set
LBB0_4:
	ldr	x8, [x21, #184]
	cbz	x8, LBB0_6
; %bb.5:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_pgt_set
	ldr	w1, [x21, #176]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_pgt_set
LBB0_6:
	ldr	x8, [x21, #168]
	cbz	x8, LBB0_8
; %bb.7:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_system_port_set
	ldr	w1, [x21, #160]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_system_port_set
LBB0_8:
	ldr	x8, [x21, #152]
	cbz	x8, LBB0_10
; %bb.9:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_vlan_groups_set
	ldr	w1, [x21, #144]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_vlan_groups_set
LBB0_10:
	ldr	x8, [x21, #136]
	cbz	x8, LBB0_12
; %bb.11:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_regions_set
	ldr	w1, [x21, #128]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_regions_set
LBB0_12:
	ldr	x8, [x21, #120]
	cbz	x8, LBB0_14
; %bb.13:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_flood_tables_set
	ldr	w1, [x21, #116]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_flood_tables_set
	ldr	w1, [x21, #112]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_vid_flood_tables_set
	ldr	w1, [x21, #108]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_fid_offset_flood_tables_set
	ldr	w1, [x21, #104]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_fid_offset_flood_table_size_set
	ldr	w1, [x21, #100]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_fid_flood_tables_set
	ldr	w1, [x21, #96]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_fid_flood_table_size_set
LBB0_14:
	ldr	x8, [x21, #88]
	cbz	x8, LBB0_16
; %bb.15:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_flood_mode_set
	ldr	w1, [x21, #80]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_flood_mode_set
LBB0_16:
	ldr	x8, [x21, #72]
	cbz	x8, LBB0_18
; %bb.17:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_ib_mc_set
	ldr	w1, [x21, #64]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_ib_mc_set
LBB0_18:
	ldr	x8, [x21, #56]
	cbz	x8, LBB0_20
; %bb.19:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_max_pkey_set
	ldr	w1, [x21, #48]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_max_pkey_set
LBB0_20:
	ldr	x8, [x21, #40]
	cbz	x8, LBB0_22
; %bb.21:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_ar_sec_set
	ldr	w1, [x21, #32]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_ar_sec_set
LBB0_22:
	ldr	x8, [x21, #24]
	cbz	x8, LBB0_24
; %bb.23:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_adaptive_routing_group_cap_set
	ldr	w1, [x21, #16]
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_adaptive_routing_group_cap_set
LBB0_24:
	ldr	x8, [x21, #8]
	cbz	x8, LBB0_29
; %bb.25:
Lloh0:
	adrp	x8, _KVD_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _KVD_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	x0, x22
	bl	_MLXSW_RES_VALID
	cbz	x0, LBB0_29
; %bb.26:
	mov	x0, x20
	mov	x1, x21
	mov	x2, x22
	bl	_mlxsw_pci_profile_get_kvd_sizes
	cbz	w0, LBB0_28
; %bb.27:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_28:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_kvd_linear_size_set
Lloh3:
	adrp	x8, _KVD_LINEAR_SIZE@GOTPAGE
Lloh4:
	ldr	x8, [x8, _KVD_LINEAR_SIZE@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x22
	bl	_MLXSW_RES_GET
	mov	x1, x0
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_kvd_linear_size_set
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_kvd_hash_single_size_set
Lloh6:
	adrp	x8, _KVD_SINGLE_SIZE@GOTPAGE
Lloh7:
	ldr	x8, [x8, _KVD_SINGLE_SIZE@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x22
	bl	_MLXSW_RES_GET
	mov	x1, x0
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_kvd_hash_single_size_set
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_kvd_hash_double_size_set
Lloh9:
	adrp	x8, _KVD_DOUBLE_SIZE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _KVD_DOUBLE_SIZE@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x22
	bl	_MLXSW_RES_GET
	mov	x1, x0
	mov	x0, x19
	bl	_mlxsw_cmd_mbox_config_profile_kvd_hash_double_size_set
LBB0_29:
Lloh12:
	adrp	x23, _MLXSW_CONFIG_PROFILE_SWID_COUNT@GOTPAGE
Lloh13:
	ldr	x23, [x23, _MLXSW_CONFIG_PROFILE_SWID_COUNT@GOTPAGEOFF]
	ldr	w8, [x23]
	cmp	w8, #1
	b.lt	LBB0_32
; %bb.30:
	mov	x24, #0
	mov	x22, #0
LBB0_31:                                ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x21]
	add	x3, x8, x24
	mov	x0, x20
	mov	x1, x19
	mov	x2, x22
	bl	_mlxsw_pci_config_profile_swid_config
	add	x22, x22, #1
	ldrsw	x8, [x23]
	add	x24, x24, #4
	cmp	x22, x8
	b.lt	LBB0_31
LBB0_32:
	ldr	x8, [x20]
Lloh14:
	adrp	x9, _MLXSW_PCI_CQE_V0@GOTPAGE
Lloh15:
	ldr	x9, [x9, _MLXSW_PCI_CQE_V0@GOTPAGEOFF]
Lloh16:
	ldr	x9, [x9]
	cmp	x8, x9
	b.le	LBB0_34
; %bb.33:
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_set_cqe_version_set
	mov	x0, x19
	mov	w1, #1
	bl	_mlxsw_cmd_mbox_config_profile_cqe_version_set
LBB0_34:
	ldr	w0, [x20, #8]
	mov	x1, x19
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_mlxsw_cmd_config_profile_set
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.cfi_endproc
                                        ; -- End function
	.comm	_KVD_SIZE,4,2                   ; @KVD_SIZE
	.comm	_KVD_LINEAR_SIZE,4,2            ; @KVD_LINEAR_SIZE
	.comm	_KVD_SINGLE_SIZE,4,2            ; @KVD_SINGLE_SIZE
	.comm	_KVD_DOUBLE_SIZE,4,2            ; @KVD_DOUBLE_SIZE
	.comm	_MLXSW_CONFIG_PROFILE_SWID_COUNT,4,2 ; @MLXSW_CONFIG_PROFILE_SWID_COUNT
	.comm	_MLXSW_PCI_CQE_V0,8,3           ; @MLXSW_PCI_CQE_V0
	.no_dead_strip	_mlxsw_pci_config_profile
.subsections_via_symbols
