	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function quirk_intel_mc_errata
_quirk_intel_mc_errata:                 ## @quirk_intel_mc_errata
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -24
	movq	_pcie_bus_config@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	_PCIE_BUS_TUNE_OFF@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_9
## %bb.1:
	movq	_PCIE_BUS_DEFAULT@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	je	LBB0_9
## %bb.2:
	movq	%rdi, %rbx
	leaq	-12(%rbp), %rdx
	movl	$72, %esi
	callq	_pci_read_config_word
	testl	%eax, %eax
	je	LBB0_5
## %bb.3:
	leaq	L_.str(%rip), %rsi
LBB0_4:
	movq	%rbx, %rdi
	callq	_pci_err
	jmp	LBB0_9
LBB0_5:
	movl	-12(%rbp), %edx
	testl	$1024, %edx                     ## imm = 0x400
	je	LBB0_9
## %bb.6:
	andl	$-1025, %edx                    ## imm = 0xFBFF
	movl	%edx, -12(%rbp)
	movq	%rbx, %rdi
	movl	$72, %esi
	callq	_pci_write_config_word
	testl	%eax, %eax
	je	LBB0_8
## %bb.7:
	leaq	L_.str.1(%rip), %rsi
	jmp	LBB0_4
LBB0_8:
	leaq	L_.str.2(%rip), %rdi
	callq	_pr_info_once
LBB0_9:
	addq	$8, %rsp
	popq	%rbx
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_pcie_bus_config,8,3            ## @pcie_bus_config
	.comm	_PCIE_BUS_TUNE_OFF,8,3          ## @PCIE_BUS_TUNE_OFF
	.comm	_PCIE_BUS_DEFAULT,8,3           ## @PCIE_BUS_DEFAULT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Error attempting to read the read completion coalescing register\n"

L_.str.1:                               ## @.str.1
	.asciz	"Error attempting to write the read completion coalescing register\n"

L_.str.2:                               ## @.str.2
	.asciz	"Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"

	.no_dead_strip	_quirk_intel_mc_errata
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function quirk_intel_mc_errata
_quirk_intel_mc_errata:                 ; @quirk_intel_mc_errata
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
Lloh0:
	adrp	x8, _pcie_bus_config@GOTPAGE
Lloh1:
	ldr	x8, [x8, _pcie_bus_config@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
Lloh3:
	adrp	x9, _PCIE_BUS_TUNE_OFF@GOTPAGE
Lloh4:
	ldr	x9, [x9, _PCIE_BUS_TUNE_OFF@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
Lloh6:
	adrp	x10, _PCIE_BUS_DEFAULT@GOTPAGE
Lloh7:
	ldr	x10, [x10, _PCIE_BUS_DEFAULT@GOTPAGEOFF]
Lloh8:
	ldr	x10, [x10]
	cmp	x8, x9
	ccmp	x8, x10, #4, ne
	b.eq	LBB0_8
; %bb.1:
	mov	x19, x0
	add	x2, sp, #12
	mov	w1, #72
	bl	_pci_read_config_word
	cbz	w0, LBB0_4
; %bb.2:
Lloh9:
	adrp	x1, l_.str@PAGE
Lloh10:
	add	x1, x1, l_.str@PAGEOFF
LBB0_3:
	mov	x0, x19
	bl	_pci_err
	b	LBB0_8
LBB0_4:
	ldr	w8, [sp, #12]
	tbz	w8, #10, LBB0_8
; %bb.5:
	and	w2, w8, #0xfffffbff
	str	w2, [sp, #12]
	mov	x0, x19
	mov	w1, #72
	bl	_pci_write_config_word
	cbz	w0, LBB0_7
; %bb.6:
Lloh11:
	adrp	x1, l_.str.1@PAGE
Lloh12:
	add	x1, x1, l_.str.1@PAGEOFF
	b	LBB0_3
LBB0_7:
Lloh13:
	adrp	x0, l_.str.2@PAGE
Lloh14:
	add	x0, x0, l_.str.2@PAGEOFF
	bl	_pr_info_once
LBB0_8:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpAdd	Lloh9, Lloh10
	.loh AdrpAdd	Lloh11, Lloh12
	.loh AdrpAdd	Lloh13, Lloh14
	.cfi_endproc
                                        ; -- End function
	.comm	_pcie_bus_config,8,3            ; @pcie_bus_config
	.comm	_PCIE_BUS_TUNE_OFF,8,3          ; @PCIE_BUS_TUNE_OFF
	.comm	_PCIE_BUS_DEFAULT,8,3           ; @PCIE_BUS_DEFAULT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Error attempting to read the read completion coalescing register\n"

l_.str.1:                               ; @.str.1
	.asciz	"Error attempting to write the read completion coalescing register\n"

l_.str.2:                               ; @.str.2
	.asciz	"Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"

	.no_dead_strip	_quirk_intel_mc_errata
.subsections_via_symbols
