	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dw_pcie_prog_inbound_atu_unroll
_dw_pcie_prog_inbound_atu_unroll:       ## @dw_pcie_prog_inbound_atu_unroll
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r8d, -44(%rbp)                 ## 4-byte Spill
	movl	%ecx, %r13d
	movl	%edx, %r15d
	movl	%esi, %r14d
	movq	%rdi, %rbx
	movq	_PCIE_ATU_UNR_LOWER_TARGET@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%ecx, %edi
	callq	_lower_32_bits
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_dw_pcie_writel_ib_unroll
	movq	_PCIE_ATU_UNR_UPPER_TARGET@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	%r13d, %edi
	callq	_upper_32_bits
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_dw_pcie_writel_ib_unroll
	movl	-44(%rbp), %eax                 ## 4-byte Reload
	cmpl	$128, %eax
	je	LBB0_1
## %bb.2:
	cmpl	$129, %eax
	jne	LBB0_12
## %bb.3:
	movq	_PCIE_ATU_TYPE_IO@GOTPCREL(%rip), %rax
	jmp	LBB0_4
LBB0_1:
	movq	_PCIE_ATU_TYPE_MEM@GOTPCREL(%rip), %rax
LBB0_4:
	movl	(%rax), %ecx
	movq	_PCIE_ATU_UNR_REGION_CTRL1@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_dw_pcie_writel_ib_unroll
	movq	_PCIE_ATU_UNR_REGION_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	_PCIE_ATU_ENABLE@GOTPCREL(%rip), %rcx
	movq	_PCIE_ATU_BAR_MODE_ENABLE@GOTPCREL(%rip), %rax
	shll	$8, %r15d
	orl	(%rcx), %r15d
	orl	(%rax), %r15d
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%r15d, %ecx
	callq	_dw_pcie_writel_ib_unroll
	movq	_LINK_WAIT_MAX_IATU_RETRIES@GOTPCREL(%rip), %r12
	cmpq	$0, (%r12)
	jle	LBB0_9
## %bb.5:
	movq	_LINK_WAIT_IATU@GOTPCREL(%rip), %r13
	xorl	%r15d, %r15d
	.p2align	4, 0x90
LBB0_6:                                 ## =>This Inner Loop Header: Depth=1
	movq	_PCIE_ATU_UNR_REGION_CTRL2@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_dw_pcie_readl_ib_unroll
	movq	_PCIE_ATU_ENABLE@GOTPCREL(%rip), %rcx
	movslq	(%rcx), %rcx
	testq	%rcx, %rax
	jne	LBB0_7
## %bb.8:                               ##   in Loop: Header=BB0_6 Depth=1
	movl	(%r13), %edi
	callq	_mdelay
	incq	%r15
	cmpq	(%r12), %r15
	jl	LBB0_6
LBB0_9:
	movl	(%rbx), %edi
	leaq	L_.str(%rip), %rsi
	callq	_dev_err
	movq	_EBUSY@GOTPCREL(%rip), %rcx
	jmp	LBB0_10
LBB0_12:
	movq	_EINVAL@GOTPCREL(%rip), %rcx
LBB0_10:
	xorl	%eax, %eax
	subl	(%rcx), %eax
	jmp	LBB0_11
LBB0_7:
	xorl	%eax, %eax
LBB0_11:
                                        ## kill: def $eax killed $eax killed $rax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_ATU_UNR_LOWER_TARGET,4,2  ## @PCIE_ATU_UNR_LOWER_TARGET
	.comm	_PCIE_ATU_UNR_UPPER_TARGET,4,2  ## @PCIE_ATU_UNR_UPPER_TARGET
	.comm	_PCIE_ATU_TYPE_MEM,4,2          ## @PCIE_ATU_TYPE_MEM
	.comm	_PCIE_ATU_TYPE_IO,4,2           ## @PCIE_ATU_TYPE_IO
	.comm	_EINVAL,4,2                     ## @EINVAL
	.comm	_PCIE_ATU_UNR_REGION_CTRL1,4,2  ## @PCIE_ATU_UNR_REGION_CTRL1
	.comm	_PCIE_ATU_UNR_REGION_CTRL2,4,2  ## @PCIE_ATU_UNR_REGION_CTRL2
	.comm	_PCIE_ATU_ENABLE,4,2            ## @PCIE_ATU_ENABLE
	.comm	_PCIE_ATU_BAR_MODE_ENABLE,4,2   ## @PCIE_ATU_BAR_MODE_ENABLE
	.comm	_LINK_WAIT_MAX_IATU_RETRIES,8,3 ## @LINK_WAIT_MAX_IATU_RETRIES
	.comm	_LINK_WAIT_IATU,4,2             ## @LINK_WAIT_IATU
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Inbound iATU is not being enabled\n"

	.comm	_EBUSY,4,2                      ## @EBUSY
	.no_dead_strip	_dw_pcie_prog_inbound_atu_unroll
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dw_pcie_prog_inbound_atu_unroll
_dw_pcie_prog_inbound_atu_unroll:       ; @dw_pcie_prog_inbound_atu_unroll
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x22, x4
	mov	x23, x3
	mov	x21, x2
	mov	x20, x1
	mov	x19, x0
Lloh0:
	adrp	x8, _PCIE_ATU_UNR_LOWER_TARGET@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_ATU_UNR_LOWER_TARGET@GOTPAGEOFF]
Lloh2:
	ldr	w24, [x8]
	mov	x0, x3
	bl	_lower_32_bits
	mov	x3, x0
	mov	x0, x19
	mov	x1, x20
	mov	x2, x24
	bl	_dw_pcie_writel_ib_unroll
Lloh3:
	adrp	x8, _PCIE_ATU_UNR_UPPER_TARGET@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_ATU_UNR_UPPER_TARGET@GOTPAGEOFF]
Lloh5:
	ldr	w24, [x8]
	mov	x0, x23
	bl	_upper_32_bits
	mov	x3, x0
	mov	x0, x19
	mov	x1, x20
	mov	x2, x24
	bl	_dw_pcie_writel_ib_unroll
	cmp	w22, #128
	b.eq	LBB0_3
; %bb.1:
	cmp	w22, #129
	b.ne	LBB0_9
; %bb.2:
Lloh6:
	adrp	x8, _PCIE_ATU_TYPE_IO@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCIE_ATU_TYPE_IO@GOTPAGEOFF]
	b	LBB0_4
LBB0_3:
Lloh8:
	adrp	x8, _PCIE_ATU_TYPE_MEM@GOTPAGE
Lloh9:
	ldr	x8, [x8, _PCIE_ATU_TYPE_MEM@GOTPAGEOFF]
LBB0_4:
	ldr	w3, [x8]
Lloh10:
	adrp	x8, _PCIE_ATU_UNR_REGION_CTRL1@GOTPAGE
Lloh11:
	ldr	x8, [x8, _PCIE_ATU_UNR_REGION_CTRL1@GOTPAGEOFF]
Lloh12:
	ldr	w2, [x8]
	mov	x0, x19
	mov	x1, x20
	bl	_dw_pcie_writel_ib_unroll
Lloh13:
	adrp	x22, _PCIE_ATU_UNR_REGION_CTRL2@GOTPAGE
Lloh14:
	ldr	x22, [x22, _PCIE_ATU_UNR_REGION_CTRL2@GOTPAGEOFF]
	ldr	w2, [x22]
Lloh15:
	adrp	x23, _PCIE_ATU_ENABLE@GOTPAGE
Lloh16:
	ldr	x23, [x23, _PCIE_ATU_ENABLE@GOTPAGEOFF]
	ldr	w8, [x23]
Lloh17:
	adrp	x9, _PCIE_ATU_BAR_MODE_ENABLE@GOTPAGE
Lloh18:
	ldr	x9, [x9, _PCIE_ATU_BAR_MODE_ENABLE@GOTPAGEOFF]
Lloh19:
	ldr	w9, [x9]
	orr	w8, w8, w21, lsl #8
	orr	w3, w8, w9
	mov	x0, x19
	mov	x1, x20
	bl	_dw_pcie_writel_ib_unroll
Lloh20:
	adrp	x21, _LINK_WAIT_MAX_IATU_RETRIES@GOTPAGE
Lloh21:
	ldr	x21, [x21, _LINK_WAIT_MAX_IATU_RETRIES@GOTPAGEOFF]
	ldr	x8, [x21]
	cmp	x8, #1
	b.lt	LBB0_8
; %bb.5:
	mov	x24, #0
Lloh22:
	adrp	x25, _LINK_WAIT_IATU@GOTPAGE
Lloh23:
	ldr	x25, [x25, _LINK_WAIT_IATU@GOTPAGEOFF]
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w2, [x22]
	mov	x0, x19
	mov	x1, x20
	bl	_dw_pcie_readl_ib_unroll
	ldrsw	x8, [x23]
	tst	x0, x8
	b.ne	LBB0_11
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=1
	ldr	w0, [x25]
	bl	_mdelay
	add	x24, x24, #1
	ldr	x8, [x21]
	cmp	x24, x8
	b.lt	LBB0_6
LBB0_8:
	ldr	w0, [x19]
Lloh24:
	adrp	x1, l_.str@PAGE
Lloh25:
	add	x1, x1, l_.str@PAGEOFF
	bl	_dev_err
Lloh26:
	adrp	x8, _EBUSY@GOTPAGE
Lloh27:
	ldr	x8, [x8, _EBUSY@GOTPAGEOFF]
	b	LBB0_10
LBB0_9:
Lloh28:
	adrp	x8, _EINVAL@GOTPAGE
Lloh29:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
LBB0_10:
	ldr	w8, [x8]
	neg	w0, w8
	b	LBB0_12
LBB0_11:
	mov	w0, #0
LBB0_12:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh17, Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpAdd	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh28, Lloh29
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_ATU_UNR_LOWER_TARGET,4,2  ; @PCIE_ATU_UNR_LOWER_TARGET
	.comm	_PCIE_ATU_UNR_UPPER_TARGET,4,2  ; @PCIE_ATU_UNR_UPPER_TARGET
	.comm	_PCIE_ATU_TYPE_MEM,4,2          ; @PCIE_ATU_TYPE_MEM
	.comm	_PCIE_ATU_TYPE_IO,4,2           ; @PCIE_ATU_TYPE_IO
	.comm	_EINVAL,4,2                     ; @EINVAL
	.comm	_PCIE_ATU_UNR_REGION_CTRL1,4,2  ; @PCIE_ATU_UNR_REGION_CTRL1
	.comm	_PCIE_ATU_UNR_REGION_CTRL2,4,2  ; @PCIE_ATU_UNR_REGION_CTRL2
	.comm	_PCIE_ATU_ENABLE,4,2            ; @PCIE_ATU_ENABLE
	.comm	_PCIE_ATU_BAR_MODE_ENABLE,4,2   ; @PCIE_ATU_BAR_MODE_ENABLE
	.comm	_LINK_WAIT_MAX_IATU_RETRIES,8,3 ; @LINK_WAIT_MAX_IATU_RETRIES
	.comm	_LINK_WAIT_IATU,4,2             ; @LINK_WAIT_IATU
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Inbound iATU is not being enabled\n"

	.comm	_EBUSY,4,2                      ; @EBUSY
	.no_dead_strip	_dw_pcie_prog_inbound_atu_unroll
.subsections_via_symbols
