	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function tegra_pcie_msi_teardown
_tegra_pcie_msi_teardown:               ## @tegra_pcie_msi_teardown
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_PAGE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	24(%rdi), %edx
	movl	(%rdi), %edi
	movl	20(%r14), %ecx
	movq	_DMA_ATTR_NO_KERNEL_MAPPING@GOTPCREL(%rip), %rax
	movl	(%rax), %r8d
	callq	_dma_free_attrs
	movq	8(%r14), %rdi
	testq	%rdi, %rdi
	jle	LBB0_2
## %bb.1:
	movq	%r14, %rsi
	callq	_free_irq
LBB0_2:
	movq	_INT_PCI_MSI_NR@GOTPCREL(%rip), %r15
	cmpl	$0, (%r15)
	je	LBB0_7
## %bb.3:
	xorl	%ebx, %ebx
	jmp	LBB0_4
	.p2align	4, 0x90
LBB0_6:                                 ##   in Loop: Header=BB0_4 Depth=1
	incl	%ebx
	cmpl	(%r15), %ebx
	jae	LBB0_7
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	16(%r14), %edi
	movl	%ebx, %esi
	callq	_irq_find_mapping
	testl	%eax, %eax
	je	LBB0_6
## %bb.5:                               ##   in Loop: Header=BB0_4 Depth=1
	movl	%eax, %edi
	callq	_irq_dispose_mapping
	jmp	LBB0_6
LBB0_7:
	movl	16(%r14), %edi
	addq	$8, %rsp
	popq	%rbx
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_irq_domain_remove              ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PAGE_SIZE,4,2                  ## @PAGE_SIZE
	.comm	_DMA_ATTR_NO_KERNEL_MAPPING,4,2 ## @DMA_ATTR_NO_KERNEL_MAPPING
	.comm	_INT_PCI_MSI_NR,4,2             ## @INT_PCI_MSI_NR
	.no_dead_strip	_tegra_pcie_msi_teardown
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function tegra_pcie_msi_teardown
_tegra_pcie_msi_teardown:               ; @tegra_pcie_msi_teardown
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	w0, [x0]
Lloh0:
	adrp	x8, _PAGE_SIZE@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PAGE_SIZE@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldp	w3, w2, [x19, #20]
Lloh3:
	adrp	x8, _DMA_ATTR_NO_KERNEL_MAPPING@GOTPAGE
Lloh4:
	ldr	x8, [x8, _DMA_ATTR_NO_KERNEL_MAPPING@GOTPAGEOFF]
Lloh5:
	ldr	w4, [x8]
	bl	_dma_free_attrs
	ldr	x0, [x19, #8]
	cmp	x0, #1
	b.lt	LBB0_2
; %bb.1:
	mov	x1, x19
	bl	_free_irq
LBB0_2:
Lloh6:
	adrp	x21, _INT_PCI_MSI_NR@GOTPAGE
Lloh7:
	ldr	x21, [x21, _INT_PCI_MSI_NR@GOTPAGEOFF]
	ldr	w8, [x21]
	cbz	w8, LBB0_7
; %bb.3:
	mov	w20, #0
	b	LBB0_5
LBB0_4:                                 ;   in Loop: Header=BB0_5 Depth=1
	add	w20, w20, #1
	ldr	w8, [x21]
	cmp	w20, w8
	b.hs	LBB0_7
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x19, #16]
	mov	x1, x20
	bl	_irq_find_mapping
	cbz	w0, LBB0_4
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	bl	_irq_dispose_mapping
	b	LBB0_4
LBB0_7:
	ldr	w0, [x19, #16]
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_irq_domain_remove
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh6, Lloh7
	.cfi_endproc
                                        ; -- End function
	.comm	_PAGE_SIZE,4,2                  ; @PAGE_SIZE
	.comm	_DMA_ATTR_NO_KERNEL_MAPPING,4,2 ; @DMA_ATTR_NO_KERNEL_MAPPING
	.comm	_INT_PCI_MSI_NR,4,2             ; @INT_PCI_MSI_NR
	.no_dead_strip	_tegra_pcie_msi_teardown
.subsections_via_symbols
