	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function set_hca_ctrl
_set_hca_ctrl:                          ## @set_hca_ctrl
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	subq	$16, %rsp
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdi, %rbx
	callq	_mlx5_core_is_pf
	testl	%eax, %eax
	je	LBB0_1
## %bb.2:
	leaq	-24(%rbp), %r14
	movq	%r14, %rdi
	xorl	%esi, %esi
	movl	$4, %edx
	callq	_memset
	movq	_MLX5_SET_HOST_ENDIANNESS@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, -24(%rbp)
	movq	_MLX5_REG_HOST_ENDIANNESS@GOTPCREL(%rip), %rax
	movl	(%rax), %r9d
	leaq	-32(%rbp), %rcx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movl	$4, %edx
	movl	$4, %r8d
	pushq	$1
	pushq	$0
	callq	_mlx5_core_access_reg
	addq	$16, %rsp
	jmp	LBB0_3
LBB0_1:
	xorl	%eax, %eax
LBB0_3:
	addq	$16, %rsp
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MLX5_SET_HOST_ENDIANNESS,4,2   ## @MLX5_SET_HOST_ENDIANNESS
	.comm	_MLX5_REG_HOST_ENDIANNESS,4,2   ## @MLX5_REG_HOST_ENDIANNESS
	.no_dead_strip	_set_hca_ctrl
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function set_hca_ctrl
_set_hca_ctrl:                          ; @set_hca_ctrl
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #48
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x0
	bl	_mlx5_core_is_pf
	cbz	w0, LBB0_2
; %bb.1:
	add	x0, sp, #8
	mov	w1, #0
	mov	w2, #4
	bl	_memset
Lloh0:
	adrp	x8, _MLX5_SET_HOST_ENDIANNESS@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MLX5_SET_HOST_ENDIANNESS@GOTPAGEOFF]
Lloh2:
	ldr	w8, [x8]
	str	w8, [sp, #8]
Lloh3:
	adrp	x8, _MLX5_REG_HOST_ENDIANNESS@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MLX5_REG_HOST_ENDIANNESS@GOTPAGEOFF]
Lloh5:
	ldr	w5, [x8]
	add	x1, sp, #8
	mov	x3, sp
	mov	x0, x19
	mov	w2, #4
	mov	w4, #4
	mov	w6, #0
	mov	w7, #1
	bl	_mlx5_core_access_reg
LBB0_2:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #48
	ret
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_MLX5_SET_HOST_ENDIANNESS,4,2   ; @MLX5_SET_HOST_ENDIANNESS
	.comm	_MLX5_REG_HOST_ENDIANNESS,4,2   ; @MLX5_REG_HOST_ENDIANNESS
	.no_dead_strip	_set_hca_ctrl
.subsections_via_symbols
