	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mt7603_mac_init
_mt7603_mac_init:                       ## @mt7603_mac_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r15
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)
	movq	_ETH_ALEN@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	shlq	$2, %rax
	callq	____chkstk_darwin
	addq	$15, %rax
	andq	$-16, %rax
	subq	%rax, %rsp
	movq	%rsp, -56(%rbp)                 ## 8-byte Spill
	movq	_MT_AGG_BA_SIZE_LIMIT_0@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movl	%eax, %r13d
	movl	$1, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movq	_MT_AGG_BA_SIZE_LIMIT_SHIFT@GOTPCREL(%rip), %r14
	movb	(%r14), %cl
	shll	%cl, %eax
	orl	%eax, %r13d
	movl	$2, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movb	(%r14), %cl
	addb	%cl, %cl
	shll	%cl, %eax
	orl	%eax, %r13d
	movl	$3, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movl	(%r14), %ecx
	leal	(%rcx,%rcx,2), %ecx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %eax
	orl	%eax, %r13d
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%r13d, %edx
	callq	_mt76_wr
	movq	_MT_AGG_BA_SIZE_LIMIT_1@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movl	$4, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movl	%eax, %r13d
	movl	$5, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movb	(%r14), %cl
	shll	%cl, %eax
	orl	%eax, %r13d
	movl	$6, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movb	(%r14), %cl
	addb	%cl, %cl
	shll	%cl, %eax
	orl	%eax, %r13d
	movl	$7, %edi
	callq	_MT_AGG_SIZE_LIMIT
	movl	(%r14), %ecx
	leal	(%rcx,%rcx,2), %ecx
                                        ## kill: def $cl killed $cl killed $ecx
	shll	%cl, %eax
	orl	%eax, %r13d
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%r13d, %edx
	callq	_mt76_wr
	movq	_MT_AGG_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	xorl	%edi, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	movl	%eax, %r13d
	movl	$1, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	orl	%eax, %r13d
	movl	$2, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	movl	%eax, %r14d
	movl	$3, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	orl	%eax, %r14d
	orl	%r13d, %r14d
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%r14d, %edx
	callq	_mt76_wr
	movq	_MT_AGG_LIMIT_1@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	xorl	%edi, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	movl	%eax, %r13d
	movl	$1, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	orl	%eax, %r13d
	movl	$2, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	movl	%eax, %r14d
	movl	$3, %edi
	callq	_MT_AGG_LIMIT_AC
	movl	%eax, %edi
	movl	$24, %esi
	callq	_FIELD_PREP
	orl	%eax, %r14d
	orl	%r13d, %r14d
	movq	%r15, %rdi
	movl	%r12d, %esi
	movl	%r14d, %edx
	callq	_mt76_wr
	movq	_MT_AGG_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_MT_AGG_CONTROL_BAR_RATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$75, %esi
	callq	_FIELD_PREP
	movl	%eax, %r12d
	movq	_MT_AGG_CONTROL_CFEND_RATE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$105, %esi
	callq	_FIELD_PREP
	orl	%eax, %r12d
	movq	_MT_AGG_CONTROL_NO_BA_AR_RULE@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	callq	_mt76_wr
	movq	_MT_AGG_RETRY_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_MT_AGG_RETRY_CONTROL_BAR_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	%eax, %r12d
	movq	_MT_AGG_RETRY_CONTROL_RTS_LIMIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$15, %esi
	callq	_FIELD_PREP
	orl	%eax, %r12d
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	callq	_mt76_wr
	movq	_MT_DMA_DCR0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_MT_DMA_DCR0_RX_VEC_DROP@GOTPCREL(%rip), %rax
	movl	(%rax), %r12d
	movq	_MT_DMA_DCR0_MAX_RX_LEN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4096, %esi                     ## imm = 0x1000
	callq	_FIELD_PREP
	orl	%eax, %r12d
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	callq	_mt76_wr
	movq	_MT_DMA_VCFR0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	xorl	%edi, %edi
	callq	_BIT
	movl	%eax, %r12d
	movl	$13, %edi
	callq	_BIT
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_mt76_rmw
	movq	_MT_DMA_TMCFR0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	xorl	%edi, %edi
	callq	_BIT
	movl	%eax, %r12d
	movl	$1, %edi
	callq	_BIT
	orl	%eax, %r12d
	movl	$13, %edi
	callq	_BIT
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%eax, %ecx
	callq	_mt76_rmw
	movq	_MT_WF_RMAC_TMR_PA@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	$31, %edi
	callq	_BIT
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_clear
	movq	_MT_WF_RMACDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_WF_RMACDR_MAXLEN_20BIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mt76_set
	movq	_MT_WF_RMAC_MAXMINLEN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$16777215, %edx                 ## imm = 0xFFFFFF
	movl	$102400, %ecx                   ## imm = 0x19000
	callq	_mt76_rmw
	movq	_MT_WF_RFCR1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	_mt76_wr
	movq	_MT_TMAC_TCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_TMAC_TCR_RX_RIFS_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mt76_set
	movq	%r15, %rdi
	callq	_mt7603_set_tmac_template
	movq	_MT_CLIENT_BASE_PHYS_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	callq	_mt7603_reg_map
	movq	_MT_CLIENT_RXINF@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	_MT_CLIENT_RXINF_RXSH_GROUPS@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r15, %rdi
	movq	%rax, %rsi
	callq	_mt76_set
	movq	_MT_DMA_DCR1@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movl	$13, %edi
	movl	$11, %esi
	callq	_GENMASK
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%eax, %edx
	callq	_mt76_set
	movq	_MT_AGG_PCR_RTS@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_AGG_PCR_RTS_PKT_THR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$3, %ecx
	callq	_mt76_rmw_field
	movq	_MT_TMAC_PCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_TMAC_PCR_SPE_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mt76_set
	movq	_MT_TXREQ@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_TXREQ_CCA_SRC_SEL@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_mt76_rmw_field
	movq	_MT_RXREQ@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$4, %edx
	callq	_mt76_wr
	movq	_MT_DMA_RCFR0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	$-1073741824, %edx              ## imm = 0xC0000000
	callq	_mt76_wr
	movq	_MT_DMA_TCFR0@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_MT_DMA_TCFR_TXS_AGGR_TIMEOUT@GOTPCREL(%rip), %r13
	movl	(%r13), %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movq	_MT_DMA_TCFR_TXS_AGGR_COUNT@GOTPCREL(%rip), %r12
	orl	(%r12), %eax
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_DMA_TCFR1@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movl	(%r13), %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	orl	(%r12), %eax
	movq	_MT_DMA_TCFR_TXS_BIT_MAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mt76_wr
	movq	_MT_MCU_PCIE_REMAP_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MT_PSE_WTBL_2_PHYS_ADDR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mt76_wr
	movq	_MT7603_WTBL_SIZE@GOTPCREL(%rip), %r14
	cmpl	$0, (%r14)
	jle	LBB0_2
	.p2align	4, 0x90
LBB0_1:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_mt7603_wtbl_clear
	incl	%ebx
	cmpl	(%r14), %ebx
	jl	LBB0_1
LBB0_2:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	movq	%rbx, %rdi
	callq	_eth_broadcast_addr
	movq	_MT7603_WTBL_RESERVED@GOTPCREL(%rip), %r14
	movq	(%r14), %rsi
	movq	%r15, %rdi
	movl	$-1, %edx
	movq	%rbx, %rcx
	callq	_mt7603_wtbl_init
	movq	(%r14), %rax
	movq	%rax, (%r15)
	movq	8(%r15), %rax
	movq	(%r14), %rcx
	movl	(%rax,%rcx,4), %edi
	movq	%r15, %rsi
	callq	_rcu_assign_pointer
	movq	_MT_LPON_BTEIR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_LPON_BTEIR_MBSS_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_mt76_rmw_field
	movq	_MT_WF_RMACDR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_WF_RMACDR_MBSSID_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	_mt76_rmw_field
	movq	_MT_AGG_ARUCR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	xorl	%edi, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$7, %esi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$2, %esi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	movl	$2, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$2, %esi
	callq	_FIELD_PREP
	movl	%eax, %r12d
	movl	$3, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$2, %esi
	callq	_FIELD_PREP
	orl	%eax, %r12d
	orl	%ebx, %r12d
	movl	$4, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	movl	$6, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movl	$7, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	%eax, %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_mt76_wr
	movq	_MT_AGG_ARDCR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	xorl	%edi, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movq	_MT7603_RATE_RETRY@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movl	$1, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	movl	$2, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	movl	%eax, %r12d
	movl	$3, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	orl	%eax, %r12d
	orl	%ebx, %r12d
	movl	$4, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movl	$5, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	movl	$6, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movl	$7, %edi
	callq	_MT_AGG_ARxCR_LIMIT
	movl	(%r13), %esi
	decl	%esi
	movl	%eax, %edi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_mt76_wr
	movq	_MT_AGG_ARCR@GOTPCREL(%rip), %rax
	movl	(%rax), %r14d
	movq	_MT_AGG_ARCR_RTS_RATE_THR@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$2, %esi
	callq	_FIELD_PREP
	movl	%eax, %r12d
	movq	_MT_AGG_ARCR_RATE_DOWN_RATIO_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %r12d
	movq	_MT_AGG_ARCR_RATE_DOWN_RATIO@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$1, %esi
	callq	_FIELD_PREP
	movl	%eax, %ebx
	movq	_MT_AGG_ARCR_RATE_UP_EXTRA_TH@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	$4, %esi
	callq	_FIELD_PREP
	orl	%eax, %ebx
	orl	%r12d, %ebx
	movq	%r15, %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_mt76_wr
	movq	_MT_WTBL_RMVTCR@GOTPCREL(%rip), %rax
	movq	(%rax), %rsi
	movq	_MT_WTBL_RMVTCR_RX_MV_MODE@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mt76_set
	movq	_MT_SEC_SCR@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	movq	_MT_SEC_SCR_MASK_ORDER@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r15, %rdi
	callq	_mt76_clear
	movl	(%rbx), %ebx
	movl	$18, %edi
	callq	_BIT
	movq	%r15, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_mt76_clear
	xorl	%edi, %edi
	callq	_MT_LPON_SBTOR
	movq	_MT_LPON_SBTOR_TIME_OFFSET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movq	%rax, %rsi
	movl	$4116, %ecx                     ## imm = 0x1014
	callq	_mt76_rmw_field
	movl	$1, %edi
	callq	_MT_LPON_SBTOR
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movq	%rax, %rsi
	movl	$8232, %ecx                     ## imm = 0x2028
	callq	_mt76_rmw_field
	movl	$2, %edi
	callq	_MT_LPON_SBTOR
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movq	%rax, %rsi
	movl	$12348, %ecx                    ## imm = 0x303C
	callq	_mt76_rmw_field
	movl	$3, %edi
	callq	_MT_LPON_SBTOR
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movq	%rax, %rsi
	movl	$16464, %ecx                    ## imm = 0x4050
	callq	_mt76_rmw_field
	movl	$4, %edi
	callq	_MT_LPON_SBTOR
	movl	(%rbx), %edx
	movq	%r15, %rdi
	movq	%rax, %rsi
	movl	$20580, %ecx                    ## imm = 0x5064
	callq	_mt76_rmw_field
	movq	___stack_chk_guard@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	cmpq	-48(%rbp), %rax
	jne	LBB0_4
## %bb.3:
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_4:
	callq	___stack_chk_fail
	.cfi_endproc
                                        ## -- End function
	.comm	_ETH_ALEN,4,2                   ## @ETH_ALEN
	.comm	_MT_AGG_BA_SIZE_LIMIT_0,4,2     ## @MT_AGG_BA_SIZE_LIMIT_0
	.comm	_MT_AGG_BA_SIZE_LIMIT_SHIFT,4,2 ## @MT_AGG_BA_SIZE_LIMIT_SHIFT
	.comm	_MT_AGG_BA_SIZE_LIMIT_1,4,2     ## @MT_AGG_BA_SIZE_LIMIT_1
	.comm	_MT_AGG_LIMIT,4,2               ## @MT_AGG_LIMIT
	.comm	_MT_AGG_LIMIT_1,4,2             ## @MT_AGG_LIMIT_1
	.comm	_MT_AGG_CONTROL,4,2             ## @MT_AGG_CONTROL
	.comm	_MT_AGG_CONTROL_BAR_RATE,4,2    ## @MT_AGG_CONTROL_BAR_RATE
	.comm	_MT_AGG_CONTROL_CFEND_RATE,4,2  ## @MT_AGG_CONTROL_CFEND_RATE
	.comm	_MT_AGG_CONTROL_NO_BA_AR_RULE,4,2 ## @MT_AGG_CONTROL_NO_BA_AR_RULE
	.comm	_MT_AGG_RETRY_CONTROL,4,2       ## @MT_AGG_RETRY_CONTROL
	.comm	_MT_AGG_RETRY_CONTROL_BAR_LIMIT,4,2 ## @MT_AGG_RETRY_CONTROL_BAR_LIMIT
	.comm	_MT_AGG_RETRY_CONTROL_RTS_LIMIT,4,2 ## @MT_AGG_RETRY_CONTROL_RTS_LIMIT
	.comm	_MT_DMA_DCR0,4,2                ## @MT_DMA_DCR0
	.comm	_MT_DMA_DCR0_RX_VEC_DROP,4,2    ## @MT_DMA_DCR0_RX_VEC_DROP
	.comm	_MT_DMA_DCR0_MAX_RX_LEN,4,2     ## @MT_DMA_DCR0_MAX_RX_LEN
	.comm	_MT_DMA_VCFR0,4,2               ## @MT_DMA_VCFR0
	.comm	_MT_DMA_TMCFR0,4,2              ## @MT_DMA_TMCFR0
	.comm	_MT_WF_RMAC_TMR_PA,4,2          ## @MT_WF_RMAC_TMR_PA
	.comm	_MT_WF_RMACDR,8,3               ## @MT_WF_RMACDR
	.comm	_MT_WF_RMACDR_MAXLEN_20BIT,4,2  ## @MT_WF_RMACDR_MAXLEN_20BIT
	.comm	_MT_WF_RMAC_MAXMINLEN,4,2       ## @MT_WF_RMAC_MAXMINLEN
	.comm	_MT_WF_RFCR1,4,2                ## @MT_WF_RFCR1
	.comm	_MT_TMAC_TCR,8,3                ## @MT_TMAC_TCR
	.comm	_MT_TMAC_TCR_RX_RIFS_MODE,4,2   ## @MT_TMAC_TCR_RX_RIFS_MODE
	.comm	_MT_CLIENT_BASE_PHYS_ADDR,4,2   ## @MT_CLIENT_BASE_PHYS_ADDR
	.comm	_MT_CLIENT_RXINF,8,3            ## @MT_CLIENT_RXINF
	.comm	_MT_CLIENT_RXINF_RXSH_GROUPS,4,2 ## @MT_CLIENT_RXINF_RXSH_GROUPS
	.comm	_MT_DMA_DCR1,8,3                ## @MT_DMA_DCR1
	.comm	_MT_AGG_PCR_RTS,8,3             ## @MT_AGG_PCR_RTS
	.comm	_MT_AGG_PCR_RTS_PKT_THR,4,2     ## @MT_AGG_PCR_RTS_PKT_THR
	.comm	_MT_TMAC_PCR,8,3                ## @MT_TMAC_PCR
	.comm	_MT_TMAC_PCR_SPE_EN,4,2         ## @MT_TMAC_PCR_SPE_EN
	.comm	_MT_TXREQ,8,3                   ## @MT_TXREQ
	.comm	_MT_TXREQ_CCA_SRC_SEL,4,2       ## @MT_TXREQ_CCA_SRC_SEL
	.comm	_MT_RXREQ,4,2                   ## @MT_RXREQ
	.comm	_MT_DMA_RCFR0,4,2               ## @MT_DMA_RCFR0
	.comm	_MT_DMA_TCFR0,4,2               ## @MT_DMA_TCFR0
	.comm	_MT_DMA_TCFR_TXS_AGGR_TIMEOUT,4,2 ## @MT_DMA_TCFR_TXS_AGGR_TIMEOUT
	.comm	_MT_DMA_TCFR_TXS_AGGR_COUNT,4,2 ## @MT_DMA_TCFR_TXS_AGGR_COUNT
	.comm	_MT_DMA_TCFR1,4,2               ## @MT_DMA_TCFR1
	.comm	_MT_DMA_TCFR_TXS_BIT_MAP,4,2    ## @MT_DMA_TCFR_TXS_BIT_MAP
	.comm	_MT_MCU_PCIE_REMAP_1,4,2        ## @MT_MCU_PCIE_REMAP_1
	.comm	_MT_PSE_WTBL_2_PHYS_ADDR,4,2    ## @MT_PSE_WTBL_2_PHYS_ADDR
	.comm	_MT7603_WTBL_SIZE,4,2           ## @MT7603_WTBL_SIZE
	.comm	_MT7603_WTBL_RESERVED,8,3       ## @MT7603_WTBL_RESERVED
	.comm	_MT_LPON_BTEIR,8,3              ## @MT_LPON_BTEIR
	.comm	_MT_LPON_BTEIR_MBSS_MODE,4,2    ## @MT_LPON_BTEIR_MBSS_MODE
	.comm	_MT_WF_RMACDR_MBSSID_MASK,4,2   ## @MT_WF_RMACDR_MBSSID_MASK
	.comm	_MT_AGG_ARUCR,4,2               ## @MT_AGG_ARUCR
	.comm	_MT_AGG_ARDCR,4,2               ## @MT_AGG_ARDCR
	.comm	_MT7603_RATE_RETRY,4,2          ## @MT7603_RATE_RETRY
	.comm	_MT_AGG_ARCR,4,2                ## @MT_AGG_ARCR
	.comm	_MT_AGG_ARCR_RTS_RATE_THR,4,2   ## @MT_AGG_ARCR_RTS_RATE_THR
	.comm	_MT_AGG_ARCR_RATE_DOWN_RATIO_EN,4,2 ## @MT_AGG_ARCR_RATE_DOWN_RATIO_EN
	.comm	_MT_AGG_ARCR_RATE_DOWN_RATIO,4,2 ## @MT_AGG_ARCR_RATE_DOWN_RATIO
	.comm	_MT_AGG_ARCR_RATE_UP_EXTRA_TH,4,2 ## @MT_AGG_ARCR_RATE_UP_EXTRA_TH
	.comm	_MT_WTBL_RMVTCR,8,3             ## @MT_WTBL_RMVTCR
	.comm	_MT_WTBL_RMVTCR_RX_MV_MODE,4,2  ## @MT_WTBL_RMVTCR_RX_MV_MODE
	.comm	_MT_SEC_SCR,4,2                 ## @MT_SEC_SCR
	.comm	_MT_SEC_SCR_MASK_ORDER,4,2      ## @MT_SEC_SCR_MASK_ORDER
	.comm	_MT_LPON_SBTOR_TIME_OFFSET,4,2  ## @MT_LPON_SBTOR_TIME_OFFSET
	.no_dead_strip	_mt7603_mac_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mt7603_mac_init
_mt7603_mac_init:                       ; @mt7603_mac_init
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	sub	sp, sp, #16
	mov	x19, x0
Lloh0:
	adrp	x8, ___stack_chk_guard@GOTPAGE
Lloh1:
	ldr	x8, [x8, ___stack_chk_guard@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
	stur	x8, [x29, #-56]
Lloh3:
	adrp	x8, _ETH_ALEN@GOTPAGE
Lloh4:
	ldr	x8, [x8, _ETH_ALEN@GOTPAGEOFF]
Lloh5:
	ldr	w8, [x8]
	lsl	x8, x8, #2
	mov	x9, x8
Lloh6:
	adrp	x16, ___chkstk_darwin@GOTPAGE
Lloh7:
	ldr	x16, [x16, ___chkstk_darwin@GOTPAGEOFF]
	blr	x16
	mov	x9, sp
	add	x8, x8, #15
	and	x8, x8, #0x7fffffff0
	sub	x20, x9, x8
	mov	sp, x20
Lloh8:
	adrp	x8, _MT_AGG_BA_SIZE_LIMIT_0@GOTPAGE
Lloh9:
	ldr	x8, [x8, _MT_AGG_BA_SIZE_LIMIT_0@GOTPAGEOFF]
Lloh10:
	ldr	w21, [x8]
	mov	w0, #0
	bl	_MT_AGG_SIZE_LIMIT
	mov	x22, x0
	mov	w0, #1
	bl	_MT_AGG_SIZE_LIMIT
Lloh11:
	adrp	x23, _MT_AGG_BA_SIZE_LIMIT_SHIFT@GOTPAGE
Lloh12:
	ldr	x23, [x23, _MT_AGG_BA_SIZE_LIMIT_SHIFT@GOTPAGEOFF]
	ldr	w8, [x23]
	lsl	w8, w0, w8
	orr	w22, w8, w22
	mov	w0, #2
	bl	_MT_AGG_SIZE_LIMIT
	ldr	w8, [x23]
	lsl	w8, w8, #1
	lsl	w8, w0, w8
	orr	w22, w22, w8
	mov	w0, #3
	bl	_MT_AGG_SIZE_LIMIT
	ldr	w8, [x23]
	add	w8, w8, w8, lsl #1
	lsl	w8, w0, w8
	orr	w2, w22, w8
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh13:
	adrp	x8, _MT_AGG_BA_SIZE_LIMIT_1@GOTPAGE
Lloh14:
	ldr	x8, [x8, _MT_AGG_BA_SIZE_LIMIT_1@GOTPAGEOFF]
Lloh15:
	ldr	w21, [x8]
	mov	w0, #4
	bl	_MT_AGG_SIZE_LIMIT
	mov	x22, x0
	mov	w0, #5
	bl	_MT_AGG_SIZE_LIMIT
	ldr	w8, [x23]
	lsl	w8, w0, w8
	orr	w22, w8, w22
	mov	w0, #6
	bl	_MT_AGG_SIZE_LIMIT
	ldr	w8, [x23]
	lsl	w8, w8, #1
	lsl	w8, w0, w8
	orr	w22, w22, w8
	mov	w0, #7
	bl	_MT_AGG_SIZE_LIMIT
	ldr	w8, [x23]
	add	w8, w8, w8, lsl #1
	lsl	w8, w0, w8
	orr	w2, w22, w8
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh16:
	adrp	x8, _MT_AGG_LIMIT@GOTPAGE
Lloh17:
	ldr	x8, [x8, _MT_AGG_LIMIT@GOTPAGEOFF]
Lloh18:
	ldr	w21, [x8]
	mov	w0, #0
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	mov	x22, x0
	mov	w0, #1
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	orr	w22, w0, w22
	mov	w0, #2
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	orr	w22, w22, w0
	mov	w0, #3
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	orr	w2, w22, w0
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh19:
	adrp	x8, _MT_AGG_LIMIT_1@GOTPAGE
Lloh20:
	ldr	x8, [x8, _MT_AGG_LIMIT_1@GOTPAGEOFF]
Lloh21:
	ldr	w21, [x8]
	mov	w0, #0
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	mov	x22, x0
	mov	w0, #1
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	orr	w22, w0, w22
	mov	w0, #2
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	orr	w22, w22, w0
	mov	w0, #3
	bl	_MT_AGG_LIMIT_AC
	mov	w1, #24
	bl	_FIELD_PREP
	orr	w2, w22, w0
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh22:
	adrp	x8, _MT_AGG_CONTROL@GOTPAGE
Lloh23:
	ldr	x8, [x8, _MT_AGG_CONTROL@GOTPAGEOFF]
Lloh24:
	ldr	w21, [x8]
Lloh25:
	adrp	x8, _MT_AGG_CONTROL_BAR_RATE@GOTPAGE
Lloh26:
	ldr	x8, [x8, _MT_AGG_CONTROL_BAR_RATE@GOTPAGEOFF]
Lloh27:
	ldr	w0, [x8]
	mov	w1, #75
	bl	_FIELD_PREP
	mov	x22, x0
Lloh28:
	adrp	x8, _MT_AGG_CONTROL_CFEND_RATE@GOTPAGE
Lloh29:
	ldr	x8, [x8, _MT_AGG_CONTROL_CFEND_RATE@GOTPAGEOFF]
Lloh30:
	ldr	w0, [x8]
	mov	w1, #105
	bl	_FIELD_PREP
	orr	w8, w0, w22
Lloh31:
	adrp	x9, _MT_AGG_CONTROL_NO_BA_AR_RULE@GOTPAGE
Lloh32:
	ldr	x9, [x9, _MT_AGG_CONTROL_NO_BA_AR_RULE@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh34:
	adrp	x8, _MT_AGG_RETRY_CONTROL@GOTPAGE
Lloh35:
	ldr	x8, [x8, _MT_AGG_RETRY_CONTROL@GOTPAGEOFF]
Lloh36:
	ldr	w21, [x8]
Lloh37:
	adrp	x8, _MT_AGG_RETRY_CONTROL_BAR_LIMIT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MT_AGG_RETRY_CONTROL_BAR_LIMIT@GOTPAGEOFF]
Lloh39:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_FIELD_PREP
	mov	x22, x0
Lloh40:
	adrp	x8, _MT_AGG_RETRY_CONTROL_RTS_LIMIT@GOTPAGE
Lloh41:
	ldr	x8, [x8, _MT_AGG_RETRY_CONTROL_RTS_LIMIT@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
	mov	w1, #15
	bl	_FIELD_PREP
	orr	w2, w0, w22
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh43:
	adrp	x8, _MT_DMA_DCR0@GOTPAGE
Lloh44:
	ldr	x8, [x8, _MT_DMA_DCR0@GOTPAGEOFF]
Lloh45:
	ldr	w21, [x8]
Lloh46:
	adrp	x8, _MT_DMA_DCR0_RX_VEC_DROP@GOTPAGE
Lloh47:
	ldr	x8, [x8, _MT_DMA_DCR0_RX_VEC_DROP@GOTPAGEOFF]
Lloh48:
	ldr	w22, [x8]
Lloh49:
	adrp	x8, _MT_DMA_DCR0_MAX_RX_LEN@GOTPAGE
Lloh50:
	ldr	x8, [x8, _MT_DMA_DCR0_MAX_RX_LEN@GOTPAGEOFF]
Lloh51:
	ldr	w0, [x8]
	mov	w1, #4096
	bl	_FIELD_PREP
	orr	w2, w0, w22
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh52:
	adrp	x8, _MT_DMA_VCFR0@GOTPAGE
Lloh53:
	ldr	x8, [x8, _MT_DMA_VCFR0@GOTPAGEOFF]
Lloh54:
	ldr	w21, [x8]
	mov	w0, #0
	bl	_BIT
	mov	x22, x0
	mov	w0, #13
	bl	_BIT
	mov	x3, x0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_mt76_rmw
Lloh55:
	adrp	x8, _MT_DMA_TMCFR0@GOTPAGE
Lloh56:
	ldr	x8, [x8, _MT_DMA_TMCFR0@GOTPAGEOFF]
Lloh57:
	ldr	w21, [x8]
	mov	w0, #0
	bl	_BIT
	mov	x22, x0
	mov	w0, #1
	bl	_BIT
	orr	w22, w0, w22
	mov	w0, #13
	bl	_BIT
	mov	x3, x0
	mov	x0, x19
	mov	x1, x21
	mov	x2, x22
	bl	_mt76_rmw
Lloh58:
	adrp	x8, _MT_WF_RMAC_TMR_PA@GOTPAGE
Lloh59:
	ldr	x8, [x8, _MT_WF_RMAC_TMR_PA@GOTPAGEOFF]
Lloh60:
	ldr	w21, [x8]
	mov	w0, #31
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_clear
Lloh61:
	adrp	x22, _MT_WF_RMACDR@GOTPAGE
Lloh62:
	ldr	x22, [x22, _MT_WF_RMACDR@GOTPAGEOFF]
	ldr	x1, [x22]
Lloh63:
	adrp	x8, _MT_WF_RMACDR_MAXLEN_20BIT@GOTPAGE
Lloh64:
	ldr	x8, [x8, _MT_WF_RMACDR_MAXLEN_20BIT@GOTPAGEOFF]
Lloh65:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_set
Lloh66:
	adrp	x8, _MT_WF_RMAC_MAXMINLEN@GOTPAGE
Lloh67:
	ldr	x8, [x8, _MT_WF_RMAC_MAXMINLEN@GOTPAGEOFF]
Lloh68:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #16777215
	mov	w3, #36864
	movk	w3, #1, lsl #16
	bl	_mt76_rmw
Lloh69:
	adrp	x8, _MT_WF_RFCR1@GOTPAGE
Lloh70:
	ldr	x8, [x8, _MT_WF_RFCR1@GOTPAGEOFF]
Lloh71:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_mt76_wr
Lloh72:
	adrp	x8, _MT_TMAC_TCR@GOTPAGE
Lloh73:
	ldr	x8, [x8, _MT_TMAC_TCR@GOTPAGEOFF]
Lloh74:
	ldr	x1, [x8]
Lloh75:
	adrp	x8, _MT_TMAC_TCR_RX_RIFS_MODE@GOTPAGE
Lloh76:
	ldr	x8, [x8, _MT_TMAC_TCR_RX_RIFS_MODE@GOTPAGEOFF]
Lloh77:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_set
	mov	x0, x19
	bl	_mt7603_set_tmac_template
Lloh78:
	adrp	x8, _MT_CLIENT_BASE_PHYS_ADDR@GOTPAGE
Lloh79:
	ldr	x8, [x8, _MT_CLIENT_BASE_PHYS_ADDR@GOTPAGEOFF]
Lloh80:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mt7603_reg_map
Lloh81:
	adrp	x8, _MT_CLIENT_RXINF@GOTPAGE
Lloh82:
	ldr	x8, [x8, _MT_CLIENT_RXINF@GOTPAGEOFF]
Lloh83:
	ldr	x8, [x8]
	add	x1, x8, x0
Lloh84:
	adrp	x8, _MT_CLIENT_RXINF_RXSH_GROUPS@GOTPAGE
Lloh85:
	ldr	x8, [x8, _MT_CLIENT_RXINF_RXSH_GROUPS@GOTPAGEOFF]
Lloh86:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_set
Lloh87:
	adrp	x8, _MT_DMA_DCR1@GOTPAGE
Lloh88:
	ldr	x8, [x8, _MT_DMA_DCR1@GOTPAGEOFF]
Lloh89:
	ldr	x21, [x8]
	mov	w0, #13
	mov	w1, #11
	bl	_GENMASK
	mov	x2, x0
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_set
Lloh90:
	adrp	x8, _MT_AGG_PCR_RTS@GOTPAGE
Lloh91:
	ldr	x8, [x8, _MT_AGG_PCR_RTS@GOTPAGEOFF]
Lloh92:
	ldr	x1, [x8]
Lloh93:
	adrp	x8, _MT_AGG_PCR_RTS_PKT_THR@GOTPAGE
Lloh94:
	ldr	x8, [x8, _MT_AGG_PCR_RTS_PKT_THR@GOTPAGEOFF]
Lloh95:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #3
	bl	_mt76_rmw_field
Lloh96:
	adrp	x8, _MT_TMAC_PCR@GOTPAGE
Lloh97:
	ldr	x8, [x8, _MT_TMAC_PCR@GOTPAGEOFF]
Lloh98:
	ldr	x1, [x8]
Lloh99:
	adrp	x8, _MT_TMAC_PCR_SPE_EN@GOTPAGE
Lloh100:
	ldr	x8, [x8, _MT_TMAC_PCR_SPE_EN@GOTPAGEOFF]
Lloh101:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_set
Lloh102:
	adrp	x8, _MT_TXREQ@GOTPAGE
Lloh103:
	ldr	x8, [x8, _MT_TXREQ@GOTPAGEOFF]
Lloh104:
	ldr	x1, [x8]
Lloh105:
	adrp	x8, _MT_TXREQ_CCA_SRC_SEL@GOTPAGE
Lloh106:
	ldr	x8, [x8, _MT_TXREQ_CCA_SRC_SEL@GOTPAGEOFF]
Lloh107:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #2
	bl	_mt76_rmw_field
Lloh108:
	adrp	x8, _MT_RXREQ@GOTPAGE
Lloh109:
	ldr	x8, [x8, _MT_RXREQ@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #4
	bl	_mt76_wr
Lloh111:
	adrp	x8, _MT_DMA_RCFR0@GOTPAGE
Lloh112:
	ldr	x8, [x8, _MT_DMA_RCFR0@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #-1073741824
	bl	_mt76_wr
Lloh114:
	adrp	x8, _MT_DMA_TCFR0@GOTPAGE
Lloh115:
	ldr	x8, [x8, _MT_DMA_TCFR0@GOTPAGEOFF]
Lloh116:
	ldr	w21, [x8]
Lloh117:
	adrp	x23, _MT_DMA_TCFR_TXS_AGGR_TIMEOUT@GOTPAGE
Lloh118:
	ldr	x23, [x23, _MT_DMA_TCFR_TXS_AGGR_TIMEOUT@GOTPAGEOFF]
	ldr	w0, [x23]
	mov	w1, #1
	bl	_FIELD_PREP
Lloh119:
	adrp	x24, _MT_DMA_TCFR_TXS_AGGR_COUNT@GOTPAGE
Lloh120:
	ldr	x24, [x24, _MT_DMA_TCFR_TXS_AGGR_COUNT@GOTPAGEOFF]
	ldr	w8, [x24]
	orr	w2, w8, w0
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh121:
	adrp	x8, _MT_DMA_TCFR1@GOTPAGE
Lloh122:
	ldr	x8, [x8, _MT_DMA_TCFR1@GOTPAGEOFF]
Lloh123:
	ldr	w21, [x8]
	ldr	w0, [x23]
	mov	w1, #1
	bl	_FIELD_PREP
	ldr	w8, [x24]
	orr	w8, w8, w0
Lloh124:
	adrp	x9, _MT_DMA_TCFR_TXS_BIT_MAP@GOTPAGE
Lloh125:
	ldr	x9, [x9, _MT_DMA_TCFR_TXS_BIT_MAP@GOTPAGEOFF]
Lloh126:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	mov	x1, x21
	bl	_mt76_wr
Lloh127:
	adrp	x8, _MT_MCU_PCIE_REMAP_1@GOTPAGE
Lloh128:
	ldr	x8, [x8, _MT_MCU_PCIE_REMAP_1@GOTPAGEOFF]
Lloh129:
	ldr	w1, [x8]
Lloh130:
	adrp	x8, _MT_PSE_WTBL_2_PHYS_ADDR@GOTPAGE
Lloh131:
	ldr	x8, [x8, _MT_PSE_WTBL_2_PHYS_ADDR@GOTPAGEOFF]
Lloh132:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_wr
Lloh133:
	adrp	x23, _MT7603_WTBL_SIZE@GOTPAGE
Lloh134:
	ldr	x23, [x23, _MT7603_WTBL_SIZE@GOTPAGEOFF]
	ldr	w8, [x23]
	cmp	w8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	w21, #0
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x19
	mov	x1, x21
	bl	_mt7603_wtbl_clear
	add	w21, w21, #1
	ldr	w8, [x23]
	cmp	w21, w8
	b.lt	LBB0_2
LBB0_3:
	mov	x0, x20
	bl	_eth_broadcast_addr
Lloh135:
	adrp	x21, _MT7603_WTBL_RESERVED@GOTPAGE
Lloh136:
	ldr	x21, [x21, _MT7603_WTBL_RESERVED@GOTPAGEOFF]
	ldr	x1, [x21]
	mov	x0, x19
	mov	w2, #-1
	mov	x3, x20
	bl	_mt7603_wtbl_init
	ldr	x8, [x21]
	str	x8, [x19]
	ldr	x8, [x19, #8]
	ldr	x9, [x21]
	ldr	w0, [x8, x9, lsl #2]
	mov	x1, x19
	bl	_rcu_assign_pointer
Lloh137:
	adrp	x8, _MT_LPON_BTEIR@GOTPAGE
Lloh138:
	ldr	x8, [x8, _MT_LPON_BTEIR@GOTPAGEOFF]
Lloh139:
	ldr	x1, [x8]
Lloh140:
	adrp	x8, _MT_LPON_BTEIR_MBSS_MODE@GOTPAGE
Lloh141:
	ldr	x8, [x8, _MT_LPON_BTEIR_MBSS_MODE@GOTPAGEOFF]
Lloh142:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #2
	bl	_mt76_rmw_field
	ldr	x1, [x22]
Lloh143:
	adrp	x8, _MT_WF_RMACDR_MBSSID_MASK@GOTPAGE
Lloh144:
	ldr	x8, [x8, _MT_WF_RMACDR_MBSSID_MASK@GOTPAGEOFF]
Lloh145:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w3, #2
	bl	_mt76_rmw_field
Lloh146:
	adrp	x8, _MT_AGG_ARUCR@GOTPAGE
Lloh147:
	ldr	x8, [x8, _MT_AGG_ARUCR@GOTPAGEOFF]
Lloh148:
	ldr	w20, [x8]
	mov	w0, #0
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #7
	bl	_FIELD_PREP
	mov	x21, x0
	mov	w0, #1
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #2
	bl	_FIELD_PREP
	orr	w21, w0, w21
	mov	w0, #2
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #2
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #3
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #2
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #4
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #5
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #6
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #7
	bl	_MT_AGG_ARxCR_LIMIT
	mov	w1, #1
	bl	_FIELD_PREP
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh149:
	adrp	x8, _MT_AGG_ARDCR@GOTPAGE
Lloh150:
	ldr	x8, [x8, _MT_AGG_ARDCR@GOTPAGEOFF]
Lloh151:
	ldr	w20, [x8]
	mov	w0, #0
	bl	_MT_AGG_ARxCR_LIMIT
Lloh152:
	adrp	x22, _MT7603_RATE_RETRY@GOTPAGE
Lloh153:
	ldr	x22, [x22, _MT7603_RATE_RETRY@GOTPAGEOFF]
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	mov	x21, x0
	mov	w0, #1
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w21, w0, w21
	mov	w0, #2
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #3
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #4
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #5
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #6
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
	mov	w0, #7
	bl	_MT_AGG_ARxCR_LIMIT
	ldr	w8, [x22]
	sub	w1, w8, #1
	bl	_FIELD_PREP
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh154:
	adrp	x8, _MT_AGG_ARCR@GOTPAGE
Lloh155:
	ldr	x8, [x8, _MT_AGG_ARCR@GOTPAGEOFF]
Lloh156:
	ldr	w20, [x8]
Lloh157:
	adrp	x8, _MT_AGG_ARCR_RTS_RATE_THR@GOTPAGE
Lloh158:
	ldr	x8, [x8, _MT_AGG_ARCR_RTS_RATE_THR@GOTPAGEOFF]
Lloh159:
	ldr	w0, [x8]
	mov	w1, #2
	bl	_FIELD_PREP
Lloh160:
	adrp	x8, _MT_AGG_ARCR_RATE_DOWN_RATIO_EN@GOTPAGE
Lloh161:
	ldr	x8, [x8, _MT_AGG_ARCR_RATE_DOWN_RATIO_EN@GOTPAGEOFF]
Lloh162:
	ldr	w8, [x8]
	orr	w21, w8, w0
Lloh163:
	adrp	x8, _MT_AGG_ARCR_RATE_DOWN_RATIO@GOTPAGE
Lloh164:
	ldr	x8, [x8, _MT_AGG_ARCR_RATE_DOWN_RATIO@GOTPAGEOFF]
Lloh165:
	ldr	w0, [x8]
	mov	w1, #1
	bl	_FIELD_PREP
	orr	w21, w21, w0
Lloh166:
	adrp	x8, _MT_AGG_ARCR_RATE_UP_EXTRA_TH@GOTPAGE
Lloh167:
	ldr	x8, [x8, _MT_AGG_ARCR_RATE_UP_EXTRA_TH@GOTPAGEOFF]
Lloh168:
	ldr	w0, [x8]
	mov	w1, #4
	bl	_FIELD_PREP
	orr	w2, w21, w0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_wr
Lloh169:
	adrp	x8, _MT_WTBL_RMVTCR@GOTPAGE
Lloh170:
	ldr	x8, [x8, _MT_WTBL_RMVTCR@GOTPAGEOFF]
Lloh171:
	ldr	x1, [x8]
Lloh172:
	adrp	x8, _MT_WTBL_RMVTCR_RX_MV_MODE@GOTPAGE
Lloh173:
	ldr	x8, [x8, _MT_WTBL_RMVTCR_RX_MV_MODE@GOTPAGEOFF]
Lloh174:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_set
Lloh175:
	adrp	x20, _MT_SEC_SCR@GOTPAGE
Lloh176:
	ldr	x20, [x20, _MT_SEC_SCR@GOTPAGEOFF]
	ldr	w1, [x20]
Lloh177:
	adrp	x8, _MT_SEC_SCR_MASK_ORDER@GOTPAGE
Lloh178:
	ldr	x8, [x8, _MT_SEC_SCR_MASK_ORDER@GOTPAGEOFF]
Lloh179:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt76_clear
	ldr	w20, [x20]
	mov	w0, #18
	bl	_BIT
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mt76_clear
	mov	w0, #0
	bl	_MT_LPON_SBTOR
	mov	x1, x0
Lloh180:
	adrp	x20, _MT_LPON_SBTOR_TIME_OFFSET@GOTPAGE
Lloh181:
	ldr	x20, [x20, _MT_LPON_SBTOR_TIME_OFFSET@GOTPAGEOFF]
	ldr	w2, [x20]
	mov	x0, x19
	mov	w3, #4116
	bl	_mt76_rmw_field
	mov	w0, #1
	bl	_MT_LPON_SBTOR
	mov	x1, x0
	ldr	w2, [x20]
	mov	x0, x19
	mov	w3, #8232
	bl	_mt76_rmw_field
	mov	w0, #2
	bl	_MT_LPON_SBTOR
	mov	x1, x0
	ldr	w2, [x20]
	mov	x0, x19
	mov	w3, #12348
	bl	_mt76_rmw_field
	mov	w0, #3
	bl	_MT_LPON_SBTOR
	mov	x1, x0
	ldr	w2, [x20]
	mov	x0, x19
	mov	w3, #16464
	bl	_mt76_rmw_field
	mov	w0, #4
	bl	_MT_LPON_SBTOR
	mov	x1, x0
	ldr	w2, [x20]
	mov	x0, x19
	mov	w3, #20580
	bl	_mt76_rmw_field
	ldur	x8, [x29, #-56]
Lloh182:
	adrp	x9, ___stack_chk_guard@GOTPAGE
Lloh183:
	ldr	x9, [x9, ___stack_chk_guard@GOTPAGEOFF]
Lloh184:
	ldr	x9, [x9]
	cmp	x9, x8
	b.ne	LBB0_5
; %bb.4:
	sub	sp, x29, #48
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
LBB0_5:
	bl	___stack_chk_fail
	.loh AdrpLdrGot	Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGotLdr	Lloh127, Lloh128, Lloh129
	.loh AdrpLdrGotLdr	Lloh124, Lloh125, Lloh126
	.loh AdrpLdrGotLdr	Lloh121, Lloh122, Lloh123
	.loh AdrpLdrGot	Lloh119, Lloh120
	.loh AdrpLdrGot	Lloh117, Lloh118
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGotLdr	Lloh84, Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh81, Lloh82, Lloh83
	.loh AdrpLdrGotLdr	Lloh78, Lloh79, Lloh80
	.loh AdrpLdrGotLdr	Lloh75, Lloh76, Lloh77
	.loh AdrpLdrGotLdr	Lloh72, Lloh73, Lloh74
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh10
	.loh AdrpLdrGot	Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh182, Lloh183, Lloh184
	.loh AdrpLdrGot	Lloh180, Lloh181
	.loh AdrpLdrGotLdr	Lloh177, Lloh178, Lloh179
	.loh AdrpLdrGot	Lloh175, Lloh176
	.loh AdrpLdrGotLdr	Lloh172, Lloh173, Lloh174
	.loh AdrpLdrGotLdr	Lloh169, Lloh170, Lloh171
	.loh AdrpLdrGotLdr	Lloh166, Lloh167, Lloh168
	.loh AdrpLdrGotLdr	Lloh163, Lloh164, Lloh165
	.loh AdrpLdrGotLdr	Lloh160, Lloh161, Lloh162
	.loh AdrpLdrGotLdr	Lloh157, Lloh158, Lloh159
	.loh AdrpLdrGotLdr	Lloh154, Lloh155, Lloh156
	.loh AdrpLdrGot	Lloh152, Lloh153
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGotLdr	Lloh137, Lloh138, Lloh139
	.loh AdrpLdrGot	Lloh135, Lloh136
	.cfi_endproc
                                        ; -- End function
	.comm	_ETH_ALEN,4,2                   ; @ETH_ALEN
	.comm	_MT_AGG_BA_SIZE_LIMIT_0,4,2     ; @MT_AGG_BA_SIZE_LIMIT_0
	.comm	_MT_AGG_BA_SIZE_LIMIT_SHIFT,4,2 ; @MT_AGG_BA_SIZE_LIMIT_SHIFT
	.comm	_MT_AGG_BA_SIZE_LIMIT_1,4,2     ; @MT_AGG_BA_SIZE_LIMIT_1
	.comm	_MT_AGG_LIMIT,4,2               ; @MT_AGG_LIMIT
	.comm	_MT_AGG_LIMIT_1,4,2             ; @MT_AGG_LIMIT_1
	.comm	_MT_AGG_CONTROL,4,2             ; @MT_AGG_CONTROL
	.comm	_MT_AGG_CONTROL_BAR_RATE,4,2    ; @MT_AGG_CONTROL_BAR_RATE
	.comm	_MT_AGG_CONTROL_CFEND_RATE,4,2  ; @MT_AGG_CONTROL_CFEND_RATE
	.comm	_MT_AGG_CONTROL_NO_BA_AR_RULE,4,2 ; @MT_AGG_CONTROL_NO_BA_AR_RULE
	.comm	_MT_AGG_RETRY_CONTROL,4,2       ; @MT_AGG_RETRY_CONTROL
	.comm	_MT_AGG_RETRY_CONTROL_BAR_LIMIT,4,2 ; @MT_AGG_RETRY_CONTROL_BAR_LIMIT
	.comm	_MT_AGG_RETRY_CONTROL_RTS_LIMIT,4,2 ; @MT_AGG_RETRY_CONTROL_RTS_LIMIT
	.comm	_MT_DMA_DCR0,4,2                ; @MT_DMA_DCR0
	.comm	_MT_DMA_DCR0_RX_VEC_DROP,4,2    ; @MT_DMA_DCR0_RX_VEC_DROP
	.comm	_MT_DMA_DCR0_MAX_RX_LEN,4,2     ; @MT_DMA_DCR0_MAX_RX_LEN
	.comm	_MT_DMA_VCFR0,4,2               ; @MT_DMA_VCFR0
	.comm	_MT_DMA_TMCFR0,4,2              ; @MT_DMA_TMCFR0
	.comm	_MT_WF_RMAC_TMR_PA,4,2          ; @MT_WF_RMAC_TMR_PA
	.comm	_MT_WF_RMACDR,8,3               ; @MT_WF_RMACDR
	.comm	_MT_WF_RMACDR_MAXLEN_20BIT,4,2  ; @MT_WF_RMACDR_MAXLEN_20BIT
	.comm	_MT_WF_RMAC_MAXMINLEN,4,2       ; @MT_WF_RMAC_MAXMINLEN
	.comm	_MT_WF_RFCR1,4,2                ; @MT_WF_RFCR1
	.comm	_MT_TMAC_TCR,8,3                ; @MT_TMAC_TCR
	.comm	_MT_TMAC_TCR_RX_RIFS_MODE,4,2   ; @MT_TMAC_TCR_RX_RIFS_MODE
	.comm	_MT_CLIENT_BASE_PHYS_ADDR,4,2   ; @MT_CLIENT_BASE_PHYS_ADDR
	.comm	_MT_CLIENT_RXINF,8,3            ; @MT_CLIENT_RXINF
	.comm	_MT_CLIENT_RXINF_RXSH_GROUPS,4,2 ; @MT_CLIENT_RXINF_RXSH_GROUPS
	.comm	_MT_DMA_DCR1,8,3                ; @MT_DMA_DCR1
	.comm	_MT_AGG_PCR_RTS,8,3             ; @MT_AGG_PCR_RTS
	.comm	_MT_AGG_PCR_RTS_PKT_THR,4,2     ; @MT_AGG_PCR_RTS_PKT_THR
	.comm	_MT_TMAC_PCR,8,3                ; @MT_TMAC_PCR
	.comm	_MT_TMAC_PCR_SPE_EN,4,2         ; @MT_TMAC_PCR_SPE_EN
	.comm	_MT_TXREQ,8,3                   ; @MT_TXREQ
	.comm	_MT_TXREQ_CCA_SRC_SEL,4,2       ; @MT_TXREQ_CCA_SRC_SEL
	.comm	_MT_RXREQ,4,2                   ; @MT_RXREQ
	.comm	_MT_DMA_RCFR0,4,2               ; @MT_DMA_RCFR0
	.comm	_MT_DMA_TCFR0,4,2               ; @MT_DMA_TCFR0
	.comm	_MT_DMA_TCFR_TXS_AGGR_TIMEOUT,4,2 ; @MT_DMA_TCFR_TXS_AGGR_TIMEOUT
	.comm	_MT_DMA_TCFR_TXS_AGGR_COUNT,4,2 ; @MT_DMA_TCFR_TXS_AGGR_COUNT
	.comm	_MT_DMA_TCFR1,4,2               ; @MT_DMA_TCFR1
	.comm	_MT_DMA_TCFR_TXS_BIT_MAP,4,2    ; @MT_DMA_TCFR_TXS_BIT_MAP
	.comm	_MT_MCU_PCIE_REMAP_1,4,2        ; @MT_MCU_PCIE_REMAP_1
	.comm	_MT_PSE_WTBL_2_PHYS_ADDR,4,2    ; @MT_PSE_WTBL_2_PHYS_ADDR
	.comm	_MT7603_WTBL_SIZE,4,2           ; @MT7603_WTBL_SIZE
	.comm	_MT7603_WTBL_RESERVED,8,3       ; @MT7603_WTBL_RESERVED
	.comm	_MT_LPON_BTEIR,8,3              ; @MT_LPON_BTEIR
	.comm	_MT_LPON_BTEIR_MBSS_MODE,4,2    ; @MT_LPON_BTEIR_MBSS_MODE
	.comm	_MT_WF_RMACDR_MBSSID_MASK,4,2   ; @MT_WF_RMACDR_MBSSID_MASK
	.comm	_MT_AGG_ARUCR,4,2               ; @MT_AGG_ARUCR
	.comm	_MT_AGG_ARDCR,4,2               ; @MT_AGG_ARDCR
	.comm	_MT7603_RATE_RETRY,4,2          ; @MT7603_RATE_RETRY
	.comm	_MT_AGG_ARCR,4,2                ; @MT_AGG_ARCR
	.comm	_MT_AGG_ARCR_RTS_RATE_THR,4,2   ; @MT_AGG_ARCR_RTS_RATE_THR
	.comm	_MT_AGG_ARCR_RATE_DOWN_RATIO_EN,4,2 ; @MT_AGG_ARCR_RATE_DOWN_RATIO_EN
	.comm	_MT_AGG_ARCR_RATE_DOWN_RATIO,4,2 ; @MT_AGG_ARCR_RATE_DOWN_RATIO
	.comm	_MT_AGG_ARCR_RATE_UP_EXTRA_TH,4,2 ; @MT_AGG_ARCR_RATE_UP_EXTRA_TH
	.comm	_MT_WTBL_RMVTCR,8,3             ; @MT_WTBL_RMVTCR
	.comm	_MT_WTBL_RMVTCR_RX_MV_MODE,4,2  ; @MT_WTBL_RMVTCR_RX_MV_MODE
	.comm	_MT_SEC_SCR,4,2                 ; @MT_SEC_SCR
	.comm	_MT_SEC_SCR_MASK_ORDER,4,2      ; @MT_SEC_SCR_MASK_ORDER
	.comm	_MT_LPON_SBTOR_TIME_OFFSET,4,2  ; @MT_LPON_SBTOR_TIME_OFFSET
	.no_dead_strip	_mt7603_mac_init
.subsections_via_symbols
