	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rtl8192e_set_tx_power
_rtl8192e_set_tx_power:                 ## @rtl8192e_set_tx_power
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, -44(%rbp)                 ## 4-byte Spill
	movq	%rdi, %r15
	movl	%esi, %edi
	callq	_rtl8xxxu_gen2_channel_to_group
	movq	(%r15), %rcx
	movslq	%eax, %r12
	movl	(%rcx,%r12,4), %ebx
	movq	_REG_TX_AGC_A_CCK1_MCS32@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	andl	$-65281, %eax                   ## imm = 0xFFFF00FF
	movl	%ebx, %r14d
	shll	$8, %r14d
	orl	%r14d, %eax
	movl	(%r13), %esi
	movq	%r15, %rdi
	movl	%eax, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_B_CCK11_A_CCK2_11@GOTPCREL(%rip), %r13
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	movzbl	%al, %eax
	movl	%ebx, %ecx
	shll	$16, %ecx
	orl	%r14d, %ecx
	shll	$24, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movl	(%r13), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	8(%r15), %rax
	movq	56(%r15), %rcx
	movl	(%rax,%r12,4), %ebx
	addl	8(%rcx), %ebx
	movl	%ebx, %eax
	shll	$8, %eax
	orl	%ebx, %eax
	movl	%ebx, %ecx
	shll	$16, %ecx
	shll	$24, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movq	_REG_TX_AGC_A_RATE18_06@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_A_RATE54_24@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	8(%r15), %rax
	movq	%r12, %r14
	movl	(%rax,%r12,4), %ebx
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_2
## %bb.1:
	movq	48(%r15), %rax
	jmp	LBB0_3
LBB0_2:
	movq	40(%r15), %rax
LBB0_3:
	addq	$8, %rax
	addl	(%rax), %ebx
	movl	%ebx, %eax
	shll	$8, %eax
	orl	%ebx, %eax
	movl	%ebx, %ecx
	shll	$16, %ecx
	shll	$24, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movq	_REG_TX_AGC_A_MCS03_MCS00@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_A_MCS07_MCS04@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_A_MCS11_MCS08@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_A_MCS15_MCS12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	cmpl	$2, 16(%r15)
	jl	LBB0_8
## %bb.4:
	movq	24(%r15), %rax
	movq	%r14, %r12
	movl	(%rax,%r14,4), %ebx
	movq	_REG_TX_AGC_B_CCK1_55_MCS32@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	movzbl	%al, %eax
	movl	%ebx, %ecx
	shll	$8, %ecx
	movl	%ebx, %esi
	shll	$16, %esi
	orl	%ecx, %esi
	movl	%ebx, %edx
	shll	$24, %edx
	orl	%esi, %edx
	orl	%eax, %edx
	movl	(%r14), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_write32
	movl	(%r13), %esi
	movq	%r15, %rdi
	callq	_rtl8xxxu_read32
	andl	$-256, %eax
	orl	%eax, %ebx
	movl	(%r13), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	32(%r15), %rax
	movq	56(%r15), %rcx
	movl	(%rax,%r12,4), %ebx
	addl	16(%rcx), %ebx
	movl	%ebx, %eax
	shll	$8, %eax
	orl	%ebx, %eax
	movl	%ebx, %ecx
	shll	$16, %ecx
	shll	$24, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movq	_REG_TX_AGC_B_RATE18_06@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_B_RATE54_24@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	32(%r15), %rax
	movl	(%rax,%r12,4), %ebx
	cmpl	$0, -44(%rbp)                   ## 4-byte Folded Reload
	je	LBB0_6
## %bb.5:
	movq	48(%r15), %rax
	jmp	LBB0_7
LBB0_8:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_6:
	movq	40(%r15), %rax
LBB0_7:
	addq	$16, %rax
	addl	(%rax), %ebx
	movl	%ebx, %eax
	shll	$8, %eax
	orl	%ebx, %eax
	movl	%ebx, %ecx
	shll	$16, %ecx
	shll	$24, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movq	_REG_TX_AGC_B_MCS03_MCS00@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_B_MCS07_MCS04@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_B_MCS11_MCS08@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	callq	_rtl8xxxu_write32
	movq	_REG_TX_AGC_B_MCS15_MCS12@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r15, %rdi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_rtl8xxxu_write32               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_REG_TX_AGC_A_CCK1_MCS32,4,2    ## @REG_TX_AGC_A_CCK1_MCS32
	.comm	_REG_TX_AGC_B_CCK11_A_CCK2_11,4,2 ## @REG_TX_AGC_B_CCK11_A_CCK2_11
	.comm	_REG_TX_AGC_A_RATE18_06,4,2     ## @REG_TX_AGC_A_RATE18_06
	.comm	_REG_TX_AGC_A_RATE54_24,4,2     ## @REG_TX_AGC_A_RATE54_24
	.comm	_REG_TX_AGC_A_MCS03_MCS00,4,2   ## @REG_TX_AGC_A_MCS03_MCS00
	.comm	_REG_TX_AGC_A_MCS07_MCS04,4,2   ## @REG_TX_AGC_A_MCS07_MCS04
	.comm	_REG_TX_AGC_A_MCS11_MCS08,4,2   ## @REG_TX_AGC_A_MCS11_MCS08
	.comm	_REG_TX_AGC_A_MCS15_MCS12,4,2   ## @REG_TX_AGC_A_MCS15_MCS12
	.comm	_REG_TX_AGC_B_CCK1_55_MCS32,4,2 ## @REG_TX_AGC_B_CCK1_55_MCS32
	.comm	_REG_TX_AGC_B_RATE18_06,4,2     ## @REG_TX_AGC_B_RATE18_06
	.comm	_REG_TX_AGC_B_RATE54_24,4,2     ## @REG_TX_AGC_B_RATE54_24
	.comm	_REG_TX_AGC_B_MCS03_MCS00,4,2   ## @REG_TX_AGC_B_MCS03_MCS00
	.comm	_REG_TX_AGC_B_MCS07_MCS04,4,2   ## @REG_TX_AGC_B_MCS07_MCS04
	.comm	_REG_TX_AGC_B_MCS11_MCS08,4,2   ## @REG_TX_AGC_B_MCS11_MCS08
	.comm	_REG_TX_AGC_B_MCS15_MCS12,4,2   ## @REG_TX_AGC_B_MCS15_MCS12
	.no_dead_strip	_rtl8192e_set_tx_power
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rtl8192e_set_tx_power
_rtl8192e_set_tx_power:                 ; @rtl8192e_set_tx_power
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x20, x2
	mov	x19, x0
	mov	x0, x1
	bl	_rtl8xxxu_gen2_channel_to_group
	mov	x21, x0
	ldr	x8, [x19]
	sbfiz	x24, x21, #2, #32
	ldr	w22, [x8, x24]
Lloh0:
	adrp	x23, _REG_TX_AGC_A_CCK1_MCS32@GOTPAGE
Lloh1:
	ldr	x23, [x23, _REG_TX_AGC_A_CCK1_MCS32@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	and	w8, w0, #0xffff00ff
	lsl	w25, w22, #8
	orr	w2, w8, w25
	ldr	w1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_write32
Lloh2:
	adrp	x23, _REG_TX_AGC_B_CCK11_A_CCK2_11@GOTPAGE
Lloh3:
	ldr	x23, [x23, _REG_TX_AGC_B_CCK11_A_CCK2_11@GOTPAGEOFF]
	ldr	w1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	orr	w8, w25, w22, lsl #16
	orr	w2, w8, w22, lsl #24
	bfxil	w2, w0, #0, #8
	ldr	w1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_write32
	ldr	x8, [x19, #8]
	ldr	w8, [x8, x24]
	ldr	x9, [x19, #56]
	ldr	w9, [x9, #8]
	add	w8, w8, w9
	orr	w9, w8, w8, lsl #8
	orr	w9, w9, w8, lsl #16
	orr	w22, w9, w8, lsl #24
Lloh4:
	adrp	x8, _REG_TX_AGC_A_RATE18_06@GOTPAGE
Lloh5:
	ldr	x8, [x8, _REG_TX_AGC_A_RATE18_06@GOTPAGEOFF]
Lloh6:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_rtl8xxxu_write32
Lloh7:
	adrp	x8, _REG_TX_AGC_A_RATE54_24@GOTPAGE
Lloh8:
	ldr	x8, [x8, _REG_TX_AGC_A_RATE54_24@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_rtl8xxxu_write32
	ldr	x8, [x19, #8]
	ldr	w8, [x8, x24]
	cbz	w20, LBB0_2
; %bb.1:
	ldr	x9, [x19, #48]
	b	LBB0_3
LBB0_2:
	ldr	x9, [x19, #40]
LBB0_3:
	add	x9, x9, #8
	ldr	w9, [x9]
	add	w8, w8, w9
	orr	w9, w8, w8, lsl #8
	orr	w9, w9, w8, lsl #16
	orr	w22, w9, w8, lsl #24
Lloh10:
	adrp	x8, _REG_TX_AGC_A_MCS03_MCS00@GOTPAGE
Lloh11:
	ldr	x8, [x8, _REG_TX_AGC_A_MCS03_MCS00@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_rtl8xxxu_write32
Lloh13:
	adrp	x8, _REG_TX_AGC_A_MCS07_MCS04@GOTPAGE
Lloh14:
	ldr	x8, [x8, _REG_TX_AGC_A_MCS07_MCS04@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_rtl8xxxu_write32
Lloh16:
	adrp	x8, _REG_TX_AGC_A_MCS11_MCS08@GOTPAGE
Lloh17:
	ldr	x8, [x8, _REG_TX_AGC_A_MCS11_MCS08@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_rtl8xxxu_write32
Lloh19:
	adrp	x8, _REG_TX_AGC_A_MCS15_MCS12@GOTPAGE
Lloh20:
	ldr	x8, [x8, _REG_TX_AGC_A_MCS15_MCS12@GOTPAGEOFF]
Lloh21:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x22
	bl	_rtl8xxxu_write32
	ldr	w8, [x19, #16]
	cmp	w8, #2
	b.lt	LBB0_6
; %bb.4:
	sxtw	x8, w21
	ldr	x9, [x19, #24]
	lsl	x22, x8, #2
	ldr	w21, [x9, x22]
Lloh22:
	adrp	x24, _REG_TX_AGC_B_CCK1_55_MCS32@GOTPAGE
Lloh23:
	ldr	x24, [x24, _REG_TX_AGC_B_CCK1_55_MCS32@GOTPAGEOFF]
	ldr	w1, [x24]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	lsl	w8, w21, #8
	orr	w8, w8, w21, lsl #16
	orr	w2, w8, w21, lsl #24
	bfxil	w2, w0, #0, #8
	ldr	w1, [x24]
	mov	x0, x19
	bl	_rtl8xxxu_write32
	ldr	w1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_read32
	and	w8, w0, #0xffffff00
	orr	w2, w8, w21
	ldr	w1, [x23]
	mov	x0, x19
	bl	_rtl8xxxu_write32
	ldr	x8, [x19, #32]
	ldr	w8, [x8, x22]
	ldr	x9, [x19, #56]
	ldr	w9, [x9, #16]
	add	w8, w8, w9
	orr	w9, w8, w8, lsl #8
	orr	w9, w9, w8, lsl #16
	orr	w21, w9, w8, lsl #24
Lloh24:
	adrp	x8, _REG_TX_AGC_B_RATE18_06@GOTPAGE
Lloh25:
	ldr	x8, [x8, _REG_TX_AGC_B_RATE18_06@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_rtl8xxxu_write32
Lloh27:
	adrp	x8, _REG_TX_AGC_B_RATE54_24@GOTPAGE
Lloh28:
	ldr	x8, [x8, _REG_TX_AGC_B_RATE54_24@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x21
	bl	_rtl8xxxu_write32
	ldr	x8, [x19, #32]
	ldr	w8, [x8, x22]
	cbz	w20, LBB0_7
; %bb.5:
	ldr	x9, [x19, #48]
	b	LBB0_8
LBB0_6:
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	ret
LBB0_7:
	ldr	x9, [x19, #40]
LBB0_8:
	add	x9, x9, #16
	ldr	w9, [x9]
	add	w8, w8, w9
	orr	w9, w8, w8, lsl #8
	orr	w9, w9, w8, lsl #16
	orr	w20, w9, w8, lsl #24
Lloh30:
	adrp	x8, _REG_TX_AGC_B_MCS03_MCS00@GOTPAGE
Lloh31:
	ldr	x8, [x8, _REG_TX_AGC_B_MCS03_MCS00@GOTPAGEOFF]
Lloh32:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_rtl8xxxu_write32
Lloh33:
	adrp	x8, _REG_TX_AGC_B_MCS07_MCS04@GOTPAGE
Lloh34:
	ldr	x8, [x8, _REG_TX_AGC_B_MCS07_MCS04@GOTPAGEOFF]
Lloh35:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_rtl8xxxu_write32
Lloh36:
	adrp	x8, _REG_TX_AGC_B_MCS11_MCS08@GOTPAGE
Lloh37:
	ldr	x8, [x8, _REG_TX_AGC_B_MCS11_MCS08@GOTPAGEOFF]
Lloh38:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	bl	_rtl8xxxu_write32
Lloh39:
	adrp	x8, _REG_TX_AGC_B_MCS15_MCS12@GOTPAGE
Lloh40:
	ldr	x8, [x8, _REG_TX_AGC_B_MCS15_MCS12@GOTPAGEOFF]
Lloh41:
	ldr	w1, [x8]
	mov	x0, x19
	mov	x2, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_rtl8xxxu_write32
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh4, Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.cfi_endproc
                                        ; -- End function
	.comm	_REG_TX_AGC_A_CCK1_MCS32,4,2    ; @REG_TX_AGC_A_CCK1_MCS32
	.comm	_REG_TX_AGC_B_CCK11_A_CCK2_11,4,2 ; @REG_TX_AGC_B_CCK11_A_CCK2_11
	.comm	_REG_TX_AGC_A_RATE18_06,4,2     ; @REG_TX_AGC_A_RATE18_06
	.comm	_REG_TX_AGC_A_RATE54_24,4,2     ; @REG_TX_AGC_A_RATE54_24
	.comm	_REG_TX_AGC_A_MCS03_MCS00,4,2   ; @REG_TX_AGC_A_MCS03_MCS00
	.comm	_REG_TX_AGC_A_MCS07_MCS04,4,2   ; @REG_TX_AGC_A_MCS07_MCS04
	.comm	_REG_TX_AGC_A_MCS11_MCS08,4,2   ; @REG_TX_AGC_A_MCS11_MCS08
	.comm	_REG_TX_AGC_A_MCS15_MCS12,4,2   ; @REG_TX_AGC_A_MCS15_MCS12
	.comm	_REG_TX_AGC_B_CCK1_55_MCS32,4,2 ; @REG_TX_AGC_B_CCK1_55_MCS32
	.comm	_REG_TX_AGC_B_RATE18_06,4,2     ; @REG_TX_AGC_B_RATE18_06
	.comm	_REG_TX_AGC_B_RATE54_24,4,2     ; @REG_TX_AGC_B_RATE54_24
	.comm	_REG_TX_AGC_B_MCS03_MCS00,4,2   ; @REG_TX_AGC_B_MCS03_MCS00
	.comm	_REG_TX_AGC_B_MCS07_MCS04,4,2   ; @REG_TX_AGC_B_MCS07_MCS04
	.comm	_REG_TX_AGC_B_MCS11_MCS08,4,2   ; @REG_TX_AGC_B_MCS11_MCS08
	.comm	_REG_TX_AGC_B_MCS15_MCS12,4,2   ; @REG_TX_AGC_B_MCS15_MCS12
	.no_dead_strip	_rtl8192e_set_tx_power
.subsections_via_symbols
