	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvpp2_egress_disable
_mvpp2_egress_disable:                  ## @mvpp2_egress_disable
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	callq	_mvpp2_egress_port
	movl	(%r14), %edi
	movq	_MVPP2_TXP_SCHED_PORT_INDEX_REG@GOTPCREL(%rip), %rcx
	movl	(%rcx), %esi
	movl	%eax, %edx
	callq	_mvpp2_write
	movl	(%r14), %edi
	movq	_MVPP2_TXP_SCHED_Q_CMD_REG@GOTPCREL(%rip), %r12
	movl	(%r12), %esi
	callq	_mvpp2_read
	movl	%eax, %ebx
	movq	_MVPP2_TXP_SCHED_ENQ_MASK@GOTPCREL(%rip), %rax
	andl	(%rax), %ebx
	je	LBB0_2
## %bb.1:
	movl	(%r14), %edi
	movl	(%r12), %esi
	movq	_MVPP2_TXP_SCHED_DISQ_OFFSET@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	%ebx, %edx
	shll	%cl, %edx
	callq	_mvpp2_write
LBB0_2:
	movq	_MVPP2_TX_DISABLE_TIMEOUT_MSEC@GOTPCREL(%rip), %r13
	cmpl	$0, (%r13)
	jle	LBB0_7
## %bb.3:
	xorl	%r15d, %r15d
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	$1, %edi
	callq	_mdelay
	movl	(%r14), %edi
	movl	(%r12), %esi
	callq	_mvpp2_read
	movl	%eax, %ebx
	movq	_MVPP2_TXP_SCHED_ENQ_MASK@GOTPCREL(%rip), %rax
	testl	%ebx, (%rax)
	je	LBB0_6
## %bb.4:                               ##   in Loop: Header=BB0_5 Depth=1
	incl	%r15d
	cmpl	(%r13), %r15d
	jl	LBB0_5
LBB0_7:
	movl	4(%r14), %edi
	leaq	L_.str(%rip), %rsi
	movl	%ebx, %edx
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_netdev_warn                    ## TAILCALL
LBB0_6:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_MVPP2_TXP_SCHED_PORT_INDEX_REG,4,2 ## @MVPP2_TXP_SCHED_PORT_INDEX_REG
	.comm	_MVPP2_TXP_SCHED_Q_CMD_REG,4,2  ## @MVPP2_TXP_SCHED_Q_CMD_REG
	.comm	_MVPP2_TXP_SCHED_ENQ_MASK,4,2   ## @MVPP2_TXP_SCHED_ENQ_MASK
	.comm	_MVPP2_TXP_SCHED_DISQ_OFFSET,4,2 ## @MVPP2_TXP_SCHED_DISQ_OFFSET
	.comm	_MVPP2_TX_DISABLE_TIMEOUT_MSEC,4,2 ## @MVPP2_TX_DISABLE_TIMEOUT_MSEC
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Tx stop timed out, status=0x%08x\n"

	.no_dead_strip	_mvpp2_egress_disable
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvpp2_egress_disable
_mvpp2_egress_disable:                  ; @mvpp2_egress_disable
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
	bl	_mvpp2_egress_port
	mov	x2, x0
	ldr	w0, [x19]
Lloh0:
	adrp	x8, _MVPP2_TXP_SCHED_PORT_INDEX_REG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_PORT_INDEX_REG@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	bl	_mvpp2_write
	ldr	w0, [x19]
Lloh3:
	adrp	x21, _MVPP2_TXP_SCHED_Q_CMD_REG@GOTPAGE
Lloh4:
	ldr	x21, [x21, _MVPP2_TXP_SCHED_Q_CMD_REG@GOTPAGEOFF]
	ldr	w1, [x21]
	bl	_mvpp2_read
Lloh5:
	adrp	x22, _MVPP2_TXP_SCHED_ENQ_MASK@GOTPAGE
Lloh6:
	ldr	x22, [x22, _MVPP2_TXP_SCHED_ENQ_MASK@GOTPAGEOFF]
	ldr	w8, [x22]
	ands	w20, w8, w0
	b.eq	LBB0_2
; %bb.1:
	ldr	w0, [x19]
	ldr	w1, [x21]
Lloh7:
	adrp	x8, _MVPP2_TXP_SCHED_DISQ_OFFSET@GOTPAGE
Lloh8:
	ldr	x8, [x8, _MVPP2_TXP_SCHED_DISQ_OFFSET@GOTPAGEOFF]
Lloh9:
	ldr	w8, [x8]
	lsl	w2, w20, w8
	bl	_mvpp2_write
LBB0_2:
Lloh10:
	adrp	x23, _MVPP2_TX_DISABLE_TIMEOUT_MSEC@GOTPAGE
Lloh11:
	ldr	x23, [x23, _MVPP2_TX_DISABLE_TIMEOUT_MSEC@GOTPAGEOFF]
	ldr	w8, [x23]
	cmp	w8, #1
	b.lt	LBB0_6
; %bb.3:
	mov	w24, #0
LBB0_4:                                 ; =>This Inner Loop Header: Depth=1
	mov	w0, #1
	bl	_mdelay
	ldr	w0, [x19]
	ldr	w1, [x21]
	bl	_mvpp2_read
	ldr	w8, [x22]
	tst	w8, w0
	b.eq	LBB0_7
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	mov	x20, x0
	add	w24, w24, #1
	ldr	w8, [x23]
	cmp	w24, w8
	b.lt	LBB0_4
LBB0_6:
	ldr	w0, [x19, #4]
Lloh12:
	adrp	x1, l_.str@PAGE
Lloh13:
	add	x1, x1, l_.str@PAGEOFF
	mov	x2, x20
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	b	_netdev_warn
LBB0_7:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGot	Lloh3, Lloh4
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpAdd	Lloh12, Lloh13
	.cfi_endproc
                                        ; -- End function
	.comm	_MVPP2_TXP_SCHED_PORT_INDEX_REG,4,2 ; @MVPP2_TXP_SCHED_PORT_INDEX_REG
	.comm	_MVPP2_TXP_SCHED_Q_CMD_REG,4,2  ; @MVPP2_TXP_SCHED_Q_CMD_REG
	.comm	_MVPP2_TXP_SCHED_ENQ_MASK,4,2   ; @MVPP2_TXP_SCHED_ENQ_MASK
	.comm	_MVPP2_TXP_SCHED_DISQ_OFFSET,4,2 ; @MVPP2_TXP_SCHED_DISQ_OFFSET
	.comm	_MVPP2_TX_DISABLE_TIMEOUT_MSEC,4,2 ; @MVPP2_TX_DISABLE_TIMEOUT_MSEC
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Tx stop timed out, status=0x%08x\n"

	.no_dead_strip	_mvpp2_egress_disable
.subsections_via_symbols
