	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function rockchip_pcie_ep_write_header
_rockchip_pcie_ep_write_header:         ## @rockchip_pcie_ep_write_header
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r12
	movq	%rsi, %r15
	callq	_epc_get_drvdata
	movq	%rax, %r14
	testq	%r15, %r15
	jne	LBB0_2
## %bb.1:
	movl	(%r12), %r13d
	movl	$15, %edi
	xorl	%esi, %esi
	callq	_GENMASK
	andl	%eax, %r13d
	movl	4(%r12), %ebx
	movl	$31, %edi
	movl	$16, %esi
	callq	_GENMASK
	andl	%eax, %ebx
	shll	$16, %ebx
	orl	%r13d, %ebx
	movq	_PCIE_CORE_CONFIG_VENDOR@GOTPCREL(%rip), %rax
	movq	(%rax), %rdx
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_rockchip_pcie_write
LBB0_2:
	movl	8(%r12), %ebx
	shll	$16, %ebx
	movq	%r15, %rdi
	callq	_ROCKCHIP_PCIE_EP_FUNC_BASE
	movq	_PCI_VENDOR_ID@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_rockchip_pcie_write
	movl	16(%r12), %eax
	movl	20(%r12), %ecx
	shll	$8, %eax
	orl	12(%r12), %eax
	shll	$16, %ecx
	movl	24(%r12), %ebx
	shll	$24, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	movq	%r15, %rdi
	callq	_ROCKCHIP_PCIE_EP_FUNC_BASE
	movq	_PCI_REVISION_ID@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_rockchip_pcie_write
	movl	28(%r12), %ebx
	movq	%r15, %rdi
	callq	_ROCKCHIP_PCIE_EP_FUNC_BASE
	movq	_PCI_CACHE_LINE_SIZE@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_rockchip_pcie_write
	movl	32(%r12), %ebx
	shll	$16, %ebx
	movq	%r15, %rdi
	callq	_ROCKCHIP_PCIE_EP_FUNC_BASE
	movq	_PCI_SUBSYSTEM_VENDOR_ID@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_rockchip_pcie_write
	movl	36(%r12), %ebx
	shll	$8, %ebx
	movq	%r15, %rdi
	callq	_ROCKCHIP_PCIE_EP_FUNC_BASE
	movq	_PCI_INTERRUPT_LINE@GOTPCREL(%rip), %rcx
	addq	(%rcx), %rax
	movq	%r14, %rdi
	movl	%ebx, %esi
	movq	%rax, %rdx
	callq	_rockchip_pcie_write
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_CORE_CONFIG_VENDOR,8,3    ## @PCIE_CORE_CONFIG_VENDOR
	.comm	_PCI_VENDOR_ID,8,3              ## @PCI_VENDOR_ID
	.comm	_PCI_REVISION_ID,8,3            ## @PCI_REVISION_ID
	.comm	_PCI_CACHE_LINE_SIZE,8,3        ## @PCI_CACHE_LINE_SIZE
	.comm	_PCI_SUBSYSTEM_VENDOR_ID,8,3    ## @PCI_SUBSYSTEM_VENDOR_ID
	.comm	_PCI_INTERRUPT_LINE,8,3         ## @PCI_INTERRUPT_LINE
	.no_dead_strip	_rockchip_pcie_ep_write_header
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function rockchip_pcie_ep_write_header
_rockchip_pcie_ep_write_header:         ; @rockchip_pcie_ep_write_header
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x21, x2
	mov	x20, x1
	bl	_epc_get_drvdata
	mov	x19, x0
	cbnz	x20, LBB0_2
; %bb.1:
	ldr	w22, [x21]
	mov	w0, #15
	mov	w1, #0
	bl	_GENMASK
	and	w22, w0, w22
	ldr	w23, [x21, #4]
	mov	w0, #31
	mov	w1, #16
	bl	_GENMASK
	and	w8, w0, w23
	orr	w1, w22, w8, lsl #16
Lloh0:
	adrp	x8, _PCIE_CORE_CONFIG_VENDOR@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_CORE_CONFIG_VENDOR@GOTPAGEOFF]
Lloh2:
	ldr	x2, [x8]
	mov	x0, x19
	bl	_rockchip_pcie_write
LBB0_2:
	ldr	w8, [x21, #8]
	lsl	w22, w8, #16
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_EP_FUNC_BASE
Lloh3:
	adrp	x8, _PCI_VENDOR_ID@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_VENDOR_ID@GOTPAGEOFF]
Lloh5:
	ldr	x8, [x8]
	add	x2, x8, x0
	mov	x0, x19
	mov	x1, x22
	bl	_rockchip_pcie_write
	ldp	w8, w9, [x21, #12]
	orr	w8, w8, w9, lsl #8
	ldp	w9, w10, [x21, #20]
	orr	w8, w8, w9, lsl #16
	orr	w22, w8, w10, lsl #24
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_EP_FUNC_BASE
Lloh6:
	adrp	x8, _PCI_REVISION_ID@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCI_REVISION_ID@GOTPAGEOFF]
Lloh8:
	ldr	x8, [x8]
	add	x2, x8, x0
	mov	x0, x19
	mov	x1, x22
	bl	_rockchip_pcie_write
	ldr	w22, [x21, #28]
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_EP_FUNC_BASE
Lloh9:
	adrp	x8, _PCI_CACHE_LINE_SIZE@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCI_CACHE_LINE_SIZE@GOTPAGEOFF]
Lloh11:
	ldr	x8, [x8]
	add	x2, x8, x0
	mov	x0, x19
	mov	x1, x22
	bl	_rockchip_pcie_write
	ldr	w8, [x21, #32]
	lsl	w22, w8, #16
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_EP_FUNC_BASE
Lloh12:
	adrp	x8, _PCI_SUBSYSTEM_VENDOR_ID@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PCI_SUBSYSTEM_VENDOR_ID@GOTPAGEOFF]
Lloh14:
	ldr	x8, [x8]
	add	x2, x8, x0
	mov	x0, x19
	mov	x1, x22
	bl	_rockchip_pcie_write
	ldr	w8, [x21, #36]
	lsl	w21, w8, #8
	mov	x0, x20
	bl	_ROCKCHIP_PCIE_EP_FUNC_BASE
Lloh15:
	adrp	x8, _PCI_INTERRUPT_LINE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCI_INTERRUPT_LINE@GOTPAGEOFF]
Lloh17:
	ldr	x8, [x8]
	add	x2, x8, x0
	mov	x0, x19
	mov	x1, x21
	bl	_rockchip_pcie_write
	mov	w0, #0
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_CORE_CONFIG_VENDOR,8,3    ; @PCIE_CORE_CONFIG_VENDOR
	.comm	_PCI_VENDOR_ID,8,3              ; @PCI_VENDOR_ID
	.comm	_PCI_REVISION_ID,8,3            ; @PCI_REVISION_ID
	.comm	_PCI_CACHE_LINE_SIZE,8,3        ; @PCI_CACHE_LINE_SIZE
	.comm	_PCI_SUBSYSTEM_VENDOR_ID,8,3    ; @PCI_SUBSYSTEM_VENDOR_ID
	.comm	_PCI_INTERRUPT_LINE,8,3         ; @PCI_INTERRUPT_LINE
	.no_dead_strip	_rockchip_pcie_ep_write_header
.subsections_via_symbols
