	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvebu_pcie_setup_wins
_mvebu_pcie_setup_wins:                 ## @mvebu_pcie_setup_wins
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	xorl	%r12d, %r12d
	xorl	%eax, %eax
	callq	_mv_mbus_dram_info
	movq	%rax, %r14
	movl	$1, %edi
	callq	_PCIE_BAR_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$1, %edi
	callq	_PCIE_BAR_LO_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$1, %edi
	callq	_PCIE_BAR_HI_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$2, %edi
	callq	_PCIE_BAR_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$2, %edi
	callq	_PCIE_BAR_LO_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$2, %edi
	callq	_PCIE_BAR_HI_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	xorl	%edi, %edi
	callq	_PCIE_WIN04_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	xorl	%edi, %edi
	callq	_PCIE_WIN04_BASE_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	xorl	%edi, %edi
	callq	_PCIE_WIN04_REMAP_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$1, %edi
	callq	_PCIE_WIN04_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$1, %edi
	callq	_PCIE_WIN04_BASE_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$1, %edi
	callq	_PCIE_WIN04_REMAP_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$2, %edi
	callq	_PCIE_WIN04_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$2, %edi
	callq	_PCIE_WIN04_BASE_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$2, %edi
	callq	_PCIE_WIN04_REMAP_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$3, %edi
	callq	_PCIE_WIN04_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$3, %edi
	callq	_PCIE_WIN04_BASE_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$3, %edi
	callq	_PCIE_WIN04_REMAP_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$4, %edi
	callq	_PCIE_WIN04_CTRL_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$4, %edi
	callq	_PCIE_WIN04_BASE_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$4, %edi
	callq	_PCIE_WIN04_REMAP_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movq	_PCIE_WIN5_CTRL_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_mvebu_writel
	movq	_PCIE_WIN5_BASE_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_mvebu_writel
	movq	_PCIE_WIN5_REMAP_OFF@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, -56(%rbp)                 ## 8-byte Spill
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	_mvebu_writel
	cmpl	$0, (%r14)
	jle	LBB0_3
## %bb.1:
	xorl	%r13d, %r13d
	movl	$8, %r15d
	xorl	%r12d, %r12d
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%r12, -64(%rbp)                 ## 8-byte Spill
	movq	-48(%rbp), %rax                 ## 8-byte Reload
	movq	8(%rax), %r14
	movzwl	-6(%r14,%r15), %ebx
	shll	$16, %ebx
	movl	%r13d, %edi
	callq	_PCIE_WIN04_BASE_OFF
	movq	-56(%rbp), %r12                 ## 8-byte Reload
	movq	%r12, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	%r13d, %edi
	callq	_PCIE_WIN04_REMAP_OFF
	movq	%r12, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	-4(%r14,%r15), %eax
	movl	(%r14,%r15), %ecx
	decl	%eax
	andl	$-65536, %eax                   ## imm = 0xFFFF0000
	shll	$8, %ecx
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movl	4(%rdx), %ebx
	shll	$4, %ebx
	orl	%ecx, %ebx
	orl	%eax, %ebx
	orl	$1, %ebx
	movl	%r13d, %edi
	callq	_PCIE_WIN04_CTRL_OFF
	movq	%r12, %rdi
	movq	-64(%rbp), %r12                 ## 8-byte Reload
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	addl	-4(%r14,%r15), %r12d
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	incq	%r13
	movslq	(%r14), %rax
	addq	$12, %r15
	cmpq	%rax, %r13
	jl	LBB0_2
LBB0_3:
	movq	-56(%rbp), %rbx                 ## 8-byte Reload
	leal	-1(%r12), %eax
	testl	%eax, %r12d
	movq	%r12, %r15
	je	LBB0_5
## %bb.4:
	movl	%r15d, %edi
	callq	_fls
	movl	$1, %r15d
	movl	%eax, %ecx
	shll	%cl, %r15d
LBB0_5:
	movq	8(%r14), %rax
	movl	(%rax), %r14d
	movl	$1, %edi
	callq	_PCIE_BAR_LO_OFF
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	movl	$1, %edi
	callq	_PCIE_BAR_HI_OFF
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movl	%eax, %edx
	callq	_mvebu_writel
	decl	%r15d
	andl	$-65536, %r15d                  ## imm = 0xFFFF0000
	orl	$1, %r15d
	movl	$1, %edi
	callq	_PCIE_BAR_CTRL_OFF
	movq	%rbx, %rdi
	movl	%r15d, %esi
	movl	%eax, %edx
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mvebu_writel                   ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_PCIE_WIN5_CTRL_OFF,4,2         ## @PCIE_WIN5_CTRL_OFF
	.comm	_PCIE_WIN5_BASE_OFF,4,2         ## @PCIE_WIN5_BASE_OFF
	.comm	_PCIE_WIN5_REMAP_OFF,4,2        ## @PCIE_WIN5_REMAP_OFF
	.no_dead_strip	_mvebu_pcie_setup_wins
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvebu_pcie_setup_wins
_mvebu_pcie_setup_wins:                 ; @mvebu_pcie_setup_wins
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
	bl	_mv_mbus_dram_info
	mov	x20, x0
	mov	w0, #1
	bl	_PCIE_BAR_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #1
	bl	_PCIE_BAR_LO_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #1
	bl	_PCIE_BAR_HI_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #2
	bl	_PCIE_BAR_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #2
	bl	_PCIE_BAR_LO_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #2
	bl	_PCIE_BAR_HI_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #0
	bl	_PCIE_WIN04_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #0
	bl	_PCIE_WIN04_BASE_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #0
	bl	_PCIE_WIN04_REMAP_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #1
	bl	_PCIE_WIN04_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #1
	bl	_PCIE_WIN04_BASE_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #1
	bl	_PCIE_WIN04_REMAP_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #2
	bl	_PCIE_WIN04_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #2
	bl	_PCIE_WIN04_BASE_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #2
	bl	_PCIE_WIN04_REMAP_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #3
	bl	_PCIE_WIN04_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #3
	bl	_PCIE_WIN04_BASE_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #3
	bl	_PCIE_WIN04_REMAP_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #4
	bl	_PCIE_WIN04_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #4
	bl	_PCIE_WIN04_BASE_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	mov	w0, #4
	bl	_PCIE_WIN04_REMAP_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
Lloh0:
	adrp	x8, _PCIE_WIN5_CTRL_OFF@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCIE_WIN5_CTRL_OFF@GOTPAGEOFF]
Lloh2:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
Lloh3:
	adrp	x8, _PCIE_WIN5_BASE_OFF@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCIE_WIN5_BASE_OFF@GOTPAGEOFF]
Lloh5:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
Lloh6:
	adrp	x8, _PCIE_WIN5_REMAP_OFF@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCIE_WIN5_REMAP_OFF@GOTPAGEOFF]
Lloh8:
	ldr	w2, [x8]
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	ldr	w8, [x20]
	cmp	w8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	x24, #0
	mov	x22, #0
	mov	w21, #0
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	x8, [x20, #8]
	add	x25, x8, x24
	ldrh	w8, [x25, #2]
	lsl	w23, w8, #16
	mov	x0, x22
	bl	_PCIE_WIN04_BASE_OFF
	mov	x2, x0
	mov	x0, x19
	mov	x1, x23
	bl	_mvebu_writel
	mov	x0, x22
	bl	_PCIE_WIN04_REMAP_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	ldp	w8, w9, [x25, #4]
	sub	w8, w8, #1
	and	w8, w8, #0xffff0000
	ldr	w10, [x20, #4]
	orr	w8, w8, w9, lsl #8
	orr	w8, w8, w10, lsl #4
	orr	w23, w8, #0x1
	mov	x0, x22
	bl	_PCIE_WIN04_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	x1, x23
	bl	_mvebu_writel
	ldr	w8, [x25, #4]
	add	w21, w8, w21
	add	x22, x22, #1
	ldrsw	x8, [x20]
	add	x24, x24, #12
	cmp	x22, x8
	b.lt	LBB0_2
	b	LBB0_4
LBB0_3:
	mov	w21, #0
LBB0_4:
	sub	w8, w21, #1
	tst	w21, w8
	b.eq	LBB0_6
; %bb.5:
	mov	x0, x21
	bl	_fls
	mov	w8, #1
	lsl	w21, w8, w0
LBB0_6:
	ldr	x8, [x20, #8]
	ldr	w20, [x8]
	mov	w0, #1
	bl	_PCIE_BAR_LO_OFF
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	bl	_mvebu_writel
	mov	w0, #1
	bl	_PCIE_BAR_HI_OFF
	mov	x2, x0
	mov	x0, x19
	mov	w1, #0
	bl	_mvebu_writel
	sub	w8, w21, #1
	and	w8, w8, #0xffff0000
	orr	w20, w8, #0x1
	mov	w0, #1
	bl	_PCIE_BAR_CTRL_OFF
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_mvebu_writel
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCIE_WIN5_CTRL_OFF,4,2         ; @PCIE_WIN5_CTRL_OFF
	.comm	_PCIE_WIN5_BASE_OFF,4,2         ; @PCIE_WIN5_BASE_OFF
	.comm	_PCIE_WIN5_REMAP_OFF,4,2        ; @PCIE_WIN5_REMAP_OFF
	.no_dead_strip	_mvebu_pcie_setup_wins
.subsections_via_symbols
