	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function dw_pcie_ep_write_header
_dw_pcie_ep_write_header:               ## @dw_pcie_ep_write_header
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r14
	pushq	%rbx
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	movq	%rdx, %r14
	callq	_epc_get_drvdata
	movq	%rax, %rdi
	callq	_to_dw_pcie_from_ep
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	_dw_pcie_dbi_ro_wr_en
	movq	_PCI_VENDOR_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writew_dbi
	movq	_PCI_DEVICE_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	4(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writew_dbi
	movq	_PCI_REVISION_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	36(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writeb_dbi
	movq	_PCI_CLASS_PROG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	32(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writeb_dbi
	movq	_PCI_CLASS_DEVICE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	12(%r14), %edx
	shll	$8, %edx
	orl	8(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writew_dbi
	movq	_PCI_CACHE_LINE_SIZE@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	28(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writeb_dbi
	movq	_PCI_SUBSYSTEM_VENDOR_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	16(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writew_dbi
	movq	_PCI_SUBSYSTEM_ID@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	20(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writew_dbi
	movq	_PCI_INTERRUPT_PIN@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	24(%r14), %edx
	movq	%rbx, %rdi
	callq	_dw_pcie_writeb_dbi
	movq	%rbx, %rdi
	callq	_dw_pcie_dbi_ro_wr_dis
	xorl	%eax, %eax
	popq	%rbx
	popq	%r14
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_PCI_VENDOR_ID,4,2              ## @PCI_VENDOR_ID
	.comm	_PCI_DEVICE_ID,4,2              ## @PCI_DEVICE_ID
	.comm	_PCI_REVISION_ID,4,2            ## @PCI_REVISION_ID
	.comm	_PCI_CLASS_PROG,4,2             ## @PCI_CLASS_PROG
	.comm	_PCI_CLASS_DEVICE,4,2           ## @PCI_CLASS_DEVICE
	.comm	_PCI_CACHE_LINE_SIZE,4,2        ## @PCI_CACHE_LINE_SIZE
	.comm	_PCI_SUBSYSTEM_VENDOR_ID,4,2    ## @PCI_SUBSYSTEM_VENDOR_ID
	.comm	_PCI_SUBSYSTEM_ID,4,2           ## @PCI_SUBSYSTEM_ID
	.comm	_PCI_INTERRUPT_PIN,4,2          ## @PCI_INTERRUPT_PIN
	.no_dead_strip	_dw_pcie_ep_write_header
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function dw_pcie_ep_write_header
_dw_pcie_ep_write_header:               ; @dw_pcie_ep_write_header
	.cfi_startproc
; %bb.0:
	stp	x20, x19, [sp, #-32]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 32
	stp	x29, x30, [sp, #16]             ; 16-byte Folded Spill
	add	x29, sp, #16
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	mov	x19, x2
	bl	_epc_get_drvdata
	bl	_to_dw_pcie_from_ep
	mov	x20, x0
	bl	_dw_pcie_dbi_ro_wr_en
Lloh0:
	adrp	x8, _PCI_VENDOR_ID@GOTPAGE
Lloh1:
	ldr	x8, [x8, _PCI_VENDOR_ID@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	ldr	w2, [x19]
	mov	x0, x20
	bl	_dw_pcie_writew_dbi
Lloh3:
	adrp	x8, _PCI_DEVICE_ID@GOTPAGE
Lloh4:
	ldr	x8, [x8, _PCI_DEVICE_ID@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	ldr	w2, [x19, #4]
	mov	x0, x20
	bl	_dw_pcie_writew_dbi
Lloh6:
	adrp	x8, _PCI_REVISION_ID@GOTPAGE
Lloh7:
	ldr	x8, [x8, _PCI_REVISION_ID@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	ldr	w2, [x19, #36]
	mov	x0, x20
	bl	_dw_pcie_writeb_dbi
Lloh9:
	adrp	x8, _PCI_CLASS_PROG@GOTPAGE
Lloh10:
	ldr	x8, [x8, _PCI_CLASS_PROG@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	ldr	w2, [x19, #32]
	mov	x0, x20
	bl	_dw_pcie_writeb_dbi
Lloh12:
	adrp	x8, _PCI_CLASS_DEVICE@GOTPAGE
Lloh13:
	ldr	x8, [x8, _PCI_CLASS_DEVICE@GOTPAGEOFF]
Lloh14:
	ldr	w1, [x8]
	ldp	w8, w9, [x19, #8]
	orr	w2, w8, w9, lsl #8
	mov	x0, x20
	bl	_dw_pcie_writew_dbi
Lloh15:
	adrp	x8, _PCI_CACHE_LINE_SIZE@GOTPAGE
Lloh16:
	ldr	x8, [x8, _PCI_CACHE_LINE_SIZE@GOTPAGEOFF]
Lloh17:
	ldr	w1, [x8]
	ldr	w2, [x19, #28]
	mov	x0, x20
	bl	_dw_pcie_writeb_dbi
Lloh18:
	adrp	x8, _PCI_SUBSYSTEM_VENDOR_ID@GOTPAGE
Lloh19:
	ldr	x8, [x8, _PCI_SUBSYSTEM_VENDOR_ID@GOTPAGEOFF]
Lloh20:
	ldr	w1, [x8]
	ldr	w2, [x19, #16]
	mov	x0, x20
	bl	_dw_pcie_writew_dbi
Lloh21:
	adrp	x8, _PCI_SUBSYSTEM_ID@GOTPAGE
Lloh22:
	ldr	x8, [x8, _PCI_SUBSYSTEM_ID@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
	ldr	w2, [x19, #20]
	mov	x0, x20
	bl	_dw_pcie_writew_dbi
Lloh24:
	adrp	x8, _PCI_INTERRUPT_PIN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _PCI_INTERRUPT_PIN@GOTPAGEOFF]
Lloh26:
	ldr	w1, [x8]
	ldr	w2, [x19, #24]
	mov	x0, x20
	bl	_dw_pcie_writeb_dbi
	mov	x0, x20
	bl	_dw_pcie_dbi_ro_wr_dis
	mov	w0, #0
	ldp	x29, x30, [sp, #16]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp], #32             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_PCI_VENDOR_ID,4,2              ; @PCI_VENDOR_ID
	.comm	_PCI_DEVICE_ID,4,2              ; @PCI_DEVICE_ID
	.comm	_PCI_REVISION_ID,4,2            ; @PCI_REVISION_ID
	.comm	_PCI_CLASS_PROG,4,2             ; @PCI_CLASS_PROG
	.comm	_PCI_CLASS_DEVICE,4,2           ; @PCI_CLASS_DEVICE
	.comm	_PCI_CACHE_LINE_SIZE,4,2        ; @PCI_CACHE_LINE_SIZE
	.comm	_PCI_SUBSYSTEM_VENDOR_ID,4,2    ; @PCI_SUBSYSTEM_VENDOR_ID
	.comm	_PCI_SUBSYSTEM_ID,4,2           ; @PCI_SUBSYSTEM_ID
	.comm	_PCI_INTERRUPT_PIN,4,2          ; @PCI_INTERRUPT_PIN
	.no_dead_strip	_dw_pcie_ep_write_header
.subsections_via_symbols
