	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ar9003_hw_init_mode_regs
_ar9003_hw_init_mode_regs:              ## @ar9003_hw_init_mode_regs
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_AR_SREV_9330_11
	testq	%rax, %rax
	je	LBB0_5
## %bb.1:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9331_1p1_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9331_1p1_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9331_1p1_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9331_1p1_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9331_1p1_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9331_1p1_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9331_1p1_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9331_common_rx_gain_1p1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9331_modes_lowest_ob_db_tx_gain_1p1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9331_1p1_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	76(%r12), %rdi
	cmpq	$0, 80(%r12)
	je	LBB0_4
## %bb.2:
	movq	_ar9331_1p1_xtal_25M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jmp	LBB0_14
LBB0_5:
	movq	%r12, %rdi
	callq	_AR_SREV_9330_12
	testq	%rax, %rax
	je	LBB0_9
## %bb.6:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9331_1p2_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9331_1p2_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9331_1p2_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9331_1p2_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9331_1p2_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9331_1p2_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9331_1p2_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9331_common_rx_gain_1p2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9331_modes_lowest_ob_db_tx_gain_1p2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9331_1p2_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	76(%r12), %rdi
	cmpq	$0, 80(%r12)
	je	LBB0_8
## %bb.7:
	movq	_ar9331_1p2_xtal_25M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jmp	LBB0_14
LBB0_4:
	movq	_ar9331_1p1_xtal_40M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jmp	LBB0_14
LBB0_9:
	movq	%r12, %rdi
	callq	_AR_SREV_9340
	testq	%rax, %rax
	je	LBB0_15
## %bb.10:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9340_1p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9340_1p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9340_1p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9340_1p0_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9340_1p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9340_1p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9340_1p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9340_1p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9340Common_wo_xlna_rx_gain_table_1p0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9340Modes_high_ob_db_tx_gain_table_1p0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	8(%r12), %rdi
	movq	_ar9340Modes_fast_clock_1p0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9340_1p0_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ar9340_1p0_baseband_postamble_dfs_channel@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_INIT_INI_ARRAY
	cmpq	$0, 80(%r12)
	je	LBB0_11
LBB0_61:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
LBB0_8:
	movq	_ar9331_1p2_xtal_40M@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	jmp	LBB0_14
LBB0_15:
	movq	%r12, %rdi
	callq	_AR_SREV_9485_11_OR_LATER
	testq	%rax, %rax
	je	LBB0_20
## %bb.16:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9485_1_1_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9485_1_1_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9485_1_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9485_1_1_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9485_1_1_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9485_1_1_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9485_1_1_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9485_1_1_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9485Common_wo_xlna_rx_gain_1_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9485_modes_lowest_ob_db_tx_gain_1_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9485_1_1_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	leaq	16(%r12), %rdi
	testl	%eax, 64(%r12)
	je	LBB0_19
## %bb.17:
	movq	_ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1@GOTPCREL(%rip), %rbx
	jmp	LBB0_18
LBB0_11:
	addq	$76, %r12
	movq	_ar9340_1p0_radio_core_40M@GOTPCREL(%rip), %rax
LBB0_12:
	movl	(%rax), %esi
	jmp	LBB0_13
LBB0_20:
	movq	%r12, %rdi
	callq	_AR_SREV_9462_21
	testq	%rax, %rax
	je	LBB0_26
## %bb.21:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9462_2p1_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9462_2p1_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9462_2p1_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9462_2p1_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9462_2p1_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9462_2p1_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	72(%r12), %rdi
	movq	_ar9462_2p1_radio_postamble_sys2ant@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9462_2p1_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9462_2p1_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9462_2p1_common_rx_gain@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	8(%r12), %rdi
	movq	_ar9462_2p1_modes_fast_clock@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9462_2p1_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	movq	_AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPCREL(%rip), %rbx
	testl	%eax, (%rbx)
	je	LBB0_61
## %bb.22:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_24
## %bb.23:
	leaq	16(%r12), %rdi
	movq	_ar9462_2p1_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	testl	%eax, (%rbx)
	je	LBB0_61
LBB0_24:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_61
## %bb.25:
	addq	$12, %r12
	movq	_ar9462_2p1_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_19:
	movq	_ar9485_1_1_pcie_phy_clkreq_disable_L1@GOTPCREL(%rip), %rbx
LBB0_18:
	movl	(%rbx), %esi
	callq	_INIT_INI_ARRAY
	addq	$12, %r12
	movl	(%rbx), %esi
LBB0_13:
	movq	%r12, %rdi
LBB0_14:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_INIT_INI_ARRAY                 ## TAILCALL
LBB0_26:
	movq	%r12, %rdi
	callq	_AR_SREV_9462_20
	testq	%rax, %rax
	je	LBB0_33
## %bb.27:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9462_2p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9462_2p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9462_2p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9462_2p0_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9462_2p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9462_2p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	72(%r12), %rdi
	movq	_ar9462_2p0_radio_postamble_sys2ant@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9462_2p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9462_2p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9462_2p0_common_rx_gain@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	movq	_AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPCREL(%rip), %rbx
	testl	%eax, (%rbx)
	je	LBB0_32
## %bb.28:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_30
## %bb.29:
	leaq	16(%r12), %rdi
	movq	_ar9462_2p0_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	testl	%eax, (%rbx)
	je	LBB0_32
LBB0_30:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_32
## %bb.31:
	leaq	12(%r12), %rdi
	movq	_ar9462_2p0_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
LBB0_32:
	leaq	8(%r12), %rdi
	movq	_ar9462_2p0_modes_fast_clock@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	addq	$4, %r12
	movq	_ar9462_2p0_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_33:
	movq	%r12, %rdi
	callq	_AR_SREV_9550
	testq	%rax, %rax
	je	LBB0_35
## %bb.34:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar955x_1p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar955x_1p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar955x_1p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar955x_1p0_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar955x_1p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar955x_1p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar955x_1p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar955x_1p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar955x_1p0_common_wo_xlna_rx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	68(%r12), %rdi
	movq	_ar955x_1p0_common_wo_xlna_rx_gain_bounds@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar955x_1p0_modes_xpa_tx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	addq	$8, %r12
	movq	_ar955x_1p0_modes_fast_clock@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_35:
	movq	%r12, %rdi
	callq	_AR_SREV_9531
	testq	%rax, %rax
	je	LBB0_42
## %bb.36:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_qca953x_1p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_qca953x_1p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	%r12, %rdi
	callq	_AR_SREV_9531_20
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	testq	%rax, %rax
	movq	_qca953x_2p0_baseband_core@GOTPCREL(%rip), %rax
	cmoveq	_qca953x_1p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_qca953x_2p0_baseband_postamble@GOTPCREL(%rip), %rbx
	cmoveq	_qca953x_1p0_baseband_postamble@GOTPCREL(%rip), %rbx
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movl	(%rbx), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_qca953x_1p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_qca953x_1p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_qca953x_1p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_qca953x_1p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	%r12, %rdi
	callq	_AR_SREV_9531_20
	leaq	24(%r12), %rdi
	testq	%rax, %rax
	movq	_qca953x_2p0_common_wo_xlna_rx_gain_table@GOTPCREL(%rip), %rax
	cmoveq	_qca953x_1p0_common_wo_xlna_rx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_qca953x_2p0_common_wo_xlna_rx_gain_bounds@GOTPCREL(%rip), %rbx
	cmoveq	_qca953x_1p0_common_wo_xlna_rx_gain_bounds@GOTPCREL(%rip), %rbx
	callq	_INIT_INI_ARRAY
	leaq	68(%r12), %rdi
	movl	(%rbx), %esi
	callq	_INIT_INI_ARRAY
	movq	%r12, %rdi
	callq	_AR_SREV_9531_20
	testq	%rax, %rax
	je	LBB0_38
## %bb.37:
	movq	_qca953x_2p0_modes_no_xpa_tx_gain_table@GOTPCREL(%rip), %rax
	jmp	LBB0_41
LBB0_42:
	movq	%r12, %rdi
	callq	_AR_SREV_9561
	testq	%rax, %rax
	je	LBB0_44
## %bb.43:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_qca956x_1p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_qca956x_1p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_qca956x_1p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_qca956x_1p0_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_qca956x_1p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_qca956x_1p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_qca956x_1p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_qca956x_1p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_qca956x_1p0_common_wo_xlna_rx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	68(%r12), %rdi
	movq	_qca956x_1p0_common_wo_xlna_rx_gain_bounds@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_qca956x_1p0_modes_no_xpa_tx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_qca956x_1p0_baseband_postamble_dfs_channel@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r12, %rdi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_qca956x_1p0_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	addq	$8, %r12
	movq	_qca956x_1p0_modes_fast_clock@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_38:
	movq	%r12, %rdi
	callq	_AR_SREV_9531_11
	testq	%rax, %rax
	jne	LBB0_39
## %bb.40:
	movq	_qca953x_1p0_modes_no_xpa_tx_gain_table@GOTPCREL(%rip), %rax
	jmp	LBB0_41
LBB0_44:
	movq	%r12, %rdi
	callq	_AR_SREV_9580
	testq	%rax, %rax
	je	LBB0_46
## %bb.45:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9580_1p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9580_1p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9580_1p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9580_1p0_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9580_1p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9580_1p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9580_1p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9580_1p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9580_1p0_rx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9580_1p0_low_ob_db_tx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	8(%r12), %rdi
	movq	_ar9580_1p0_modes_fast_clock@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9580_1p0_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ar9580_1p0_baseband_postamble_dfs_channel@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_39:
	movq	_qca953x_1p1_modes_no_xpa_tx_gain_table@GOTPCREL(%rip), %rax
LBB0_41:
	leaq	20(%r12), %rdi
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	addq	$8, %r12
	movq	_qca953x_1p0_modes_fast_clock@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_46:
	movq	%r12, %rdi
	callq	_AR_SREV_9565_11_OR_LATER
	testq	%rax, %rax
	je	LBB0_53
## %bb.47:
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %rbx
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9565_1p1_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9565_1p1_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9565_1p1_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9565_1p1_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%rbx), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9565_1p1_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9565_1p1_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9565_1p1_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9565_1p1_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9565_1p1_Common_rx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9565_1p1_Modes_lowest_ob_db_tx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	movq	_AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPCREL(%rip), %rbx
	testl	%eax, (%rbx)
	je	LBB0_52
## %bb.48:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_50
## %bb.49:
	leaq	16(%r12), %rdi
	movq	_ar9565_1p1_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	testl	%eax, (%rbx)
	je	LBB0_52
LBB0_50:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_52
## %bb.51:
	leaq	12(%r12), %rdi
	movq	_ar9565_1p1_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
LBB0_52:
	leaq	8(%r12), %rdi
	movq	_ar9565_1p1_modes_fast_clock@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	addq	$4, %r12
	movq	_ar9565_1p1_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_53:
	movq	%r12, %rdi
	callq	_AR_SREV_9565
	movq	_ATH_INI_CORE@GOTPCREL(%rip), %r14
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	testq	%rax, %rax
	je	LBB0_60
## %bb.54:
	movq	_ar9565_1p0_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9565_1p0_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9565_1p0_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9565_1p0_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9565_1p0_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9565_1p0_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9565_1p0_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9565_1p0_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9565_1p0_Common_rx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9565_1p0_Modes_lowest_ob_db_tx_gain_table@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	movq	_AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPCREL(%rip), %rbx
	testl	%eax, (%rbx)
	je	LBB0_59
## %bb.55:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_57
## %bb.56:
	leaq	16(%r12), %rdi
	movq	_ar9565_1p0_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movl	64(%r12), %eax
	testl	%eax, (%rbx)
	je	LBB0_59
LBB0_57:
	movq	_AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPCREL(%rip), %rcx
	testl	%eax, (%rcx)
	je	LBB0_59
## %bb.58:
	leaq	12(%r12), %rdi
	movq	_ar9565_1p0_pciephy_clkreq_disable_L1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
LBB0_59:
	leaq	8(%r12), %rdi
	movq	_ar9565_1p0_modes_fast_clock@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	addq	$4, %r12
	movq	_ar9565_1p0_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	jmp	LBB0_12
LBB0_60:
	movq	_ar9300_2p2_mac_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_POST@GOTPCREL(%rip), %r15
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	56(%r12), %rdi
	movq	_ar9300_2p2_mac_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9300_2p2_baseband_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	48(%r12), %rdi
	movq	_ar9300_2p2_baseband_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r14), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9300_2p2_radio_core@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	40(%r12), %rdi
	movq	_ar9300_2p2_radio_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ATH_INI_PRE@GOTPCREL(%rip), %rax
	movq	(%rax), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9300_2p2_soc_preamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	(%r15), %rdi
	shlq	$2, %rdi
	addq	32(%r12), %rdi
	movq	_ar9300_2p2_soc_postamble@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	24(%r12), %rdi
	movq	_ar9300Common_rx_gain_table_2p2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	20(%r12), %rdi
	movq	_ar9300Modes_lowest_ob_db_tx_gain_table_2p2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	16(%r12), %rdi
	movq	_ar9300PciePhy_pll_on_clkreq_disable_L1_2p2@GOTPCREL(%rip), %rbx
	movl	(%rbx), %esi
	callq	_INIT_INI_ARRAY
	leaq	12(%r12), %rdi
	movl	(%rbx), %esi
	callq	_INIT_INI_ARRAY
	leaq	8(%r12), %rdi
	movq	_ar9300Modes_fast_clock_2p2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	leaq	4(%r12), %rdi
	movq	_ar9300_2p2_baseband_core_txfir_coeff_japan_2484@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_INIT_INI_ARRAY
	movq	_ar9300_2p2_baseband_postamble_dfs_channel@GOTPCREL(%rip), %rax
	jmp	LBB0_12
	.cfi_endproc
                                        ## -- End function
	.comm	_ATH_INI_CORE,8,3               ## @ATH_INI_CORE
	.comm	_ar9331_1p1_mac_core,4,2        ## @ar9331_1p1_mac_core
	.comm	_ATH_INI_POST,8,3               ## @ATH_INI_POST
	.comm	_ar9331_1p1_mac_postamble,4,2   ## @ar9331_1p1_mac_postamble
	.comm	_ar9331_1p1_baseband_core,4,2   ## @ar9331_1p1_baseband_core
	.comm	_ar9331_1p1_baseband_postamble,4,2 ## @ar9331_1p1_baseband_postamble
	.comm	_ar9331_1p1_radio_core,4,2      ## @ar9331_1p1_radio_core
	.comm	_ATH_INI_PRE,8,3                ## @ATH_INI_PRE
	.comm	_ar9331_1p1_soc_preamble,4,2    ## @ar9331_1p1_soc_preamble
	.comm	_ar9331_1p1_soc_postamble,4,2   ## @ar9331_1p1_soc_postamble
	.comm	_ar9331_common_rx_gain_1p1,4,2  ## @ar9331_common_rx_gain_1p1
	.comm	_ar9331_modes_lowest_ob_db_tx_gain_1p1,4,2 ## @ar9331_modes_lowest_ob_db_tx_gain_1p1
	.comm	_ar9331_1p1_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9331_1p1_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9331_1p1_xtal_25M,4,2        ## @ar9331_1p1_xtal_25M
	.comm	_ar9331_1p1_xtal_40M,4,2        ## @ar9331_1p1_xtal_40M
	.comm	_ar9331_1p2_mac_core,4,2        ## @ar9331_1p2_mac_core
	.comm	_ar9331_1p2_mac_postamble,4,2   ## @ar9331_1p2_mac_postamble
	.comm	_ar9331_1p2_baseband_core,4,2   ## @ar9331_1p2_baseband_core
	.comm	_ar9331_1p2_baseband_postamble,4,2 ## @ar9331_1p2_baseband_postamble
	.comm	_ar9331_1p2_radio_core,4,2      ## @ar9331_1p2_radio_core
	.comm	_ar9331_1p2_soc_preamble,4,2    ## @ar9331_1p2_soc_preamble
	.comm	_ar9331_1p2_soc_postamble,4,2   ## @ar9331_1p2_soc_postamble
	.comm	_ar9331_common_rx_gain_1p2,4,2  ## @ar9331_common_rx_gain_1p2
	.comm	_ar9331_modes_lowest_ob_db_tx_gain_1p2,4,2 ## @ar9331_modes_lowest_ob_db_tx_gain_1p2
	.comm	_ar9331_1p2_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9331_1p2_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9331_1p2_xtal_25M,4,2        ## @ar9331_1p2_xtal_25M
	.comm	_ar9331_1p2_xtal_40M,4,2        ## @ar9331_1p2_xtal_40M
	.comm	_ar9340_1p0_mac_core,4,2        ## @ar9340_1p0_mac_core
	.comm	_ar9340_1p0_mac_postamble,4,2   ## @ar9340_1p0_mac_postamble
	.comm	_ar9340_1p0_baseband_core,4,2   ## @ar9340_1p0_baseband_core
	.comm	_ar9340_1p0_baseband_postamble,4,2 ## @ar9340_1p0_baseband_postamble
	.comm	_ar9340_1p0_radio_core,4,2      ## @ar9340_1p0_radio_core
	.comm	_ar9340_1p0_radio_postamble,4,2 ## @ar9340_1p0_radio_postamble
	.comm	_ar9340_1p0_soc_preamble,4,2    ## @ar9340_1p0_soc_preamble
	.comm	_ar9340_1p0_soc_postamble,4,2   ## @ar9340_1p0_soc_postamble
	.comm	_ar9340Common_wo_xlna_rx_gain_table_1p0,4,2 ## @ar9340Common_wo_xlna_rx_gain_table_1p0
	.comm	_ar9340Modes_high_ob_db_tx_gain_table_1p0,4,2 ## @ar9340Modes_high_ob_db_tx_gain_table_1p0
	.comm	_ar9340Modes_fast_clock_1p0,4,2 ## @ar9340Modes_fast_clock_1p0
	.comm	_ar9340_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9340_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9340_1p0_baseband_postamble_dfs_channel,4,2 ## @ar9340_1p0_baseband_postamble_dfs_channel
	.comm	_ar9340_1p0_radio_core_40M,4,2  ## @ar9340_1p0_radio_core_40M
	.comm	_ar9485_1_1_mac_core,4,2        ## @ar9485_1_1_mac_core
	.comm	_ar9485_1_1_mac_postamble,4,2   ## @ar9485_1_1_mac_postamble
	.comm	_ar9485_1_1,4,2                 ## @ar9485_1_1
	.comm	_ar9485_1_1_baseband_core,4,2   ## @ar9485_1_1_baseband_core
	.comm	_ar9485_1_1_baseband_postamble,4,2 ## @ar9485_1_1_baseband_postamble
	.comm	_ar9485_1_1_radio_core,4,2      ## @ar9485_1_1_radio_core
	.comm	_ar9485_1_1_radio_postamble,4,2 ## @ar9485_1_1_radio_postamble
	.comm	_ar9485_1_1_soc_preamble,4,2    ## @ar9485_1_1_soc_preamble
	.comm	_ar9485Common_wo_xlna_rx_gain_1_1,4,2 ## @ar9485Common_wo_xlna_rx_gain_1_1
	.comm	_ar9485_modes_lowest_ob_db_tx_gain_1_1,4,2 ## @ar9485_modes_lowest_ob_db_tx_gain_1_1
	.comm	_ar9485_1_1_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9485_1_1_baseband_core_txfir_coeff_japan_2484
	.comm	_AR_PCIE_PLL_PWRSAVE_CONTROL,4,2 ## @AR_PCIE_PLL_PWRSAVE_CONTROL
	.comm	_ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1,4,2 ## @ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1
	.comm	_ar9485_1_1_pcie_phy_clkreq_disable_L1,4,2 ## @ar9485_1_1_pcie_phy_clkreq_disable_L1
	.comm	_ar9462_2p1_mac_core,4,2        ## @ar9462_2p1_mac_core
	.comm	_ar9462_2p1_mac_postamble,4,2   ## @ar9462_2p1_mac_postamble
	.comm	_ar9462_2p1_baseband_core,4,2   ## @ar9462_2p1_baseband_core
	.comm	_ar9462_2p1_baseband_postamble,4,2 ## @ar9462_2p1_baseband_postamble
	.comm	_ar9462_2p1_radio_core,4,2      ## @ar9462_2p1_radio_core
	.comm	_ar9462_2p1_radio_postamble,4,2 ## @ar9462_2p1_radio_postamble
	.comm	_ar9462_2p1_radio_postamble_sys2ant,4,2 ## @ar9462_2p1_radio_postamble_sys2ant
	.comm	_ar9462_2p1_soc_preamble,4,2    ## @ar9462_2p1_soc_preamble
	.comm	_ar9462_2p1_soc_postamble,4,2   ## @ar9462_2p1_soc_postamble
	.comm	_ar9462_2p1_common_rx_gain,4,2  ## @ar9462_2p1_common_rx_gain
	.comm	_ar9462_2p1_modes_fast_clock,4,2 ## @ar9462_2p1_modes_fast_clock
	.comm	_ar9462_2p1_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9462_2p1_baseband_core_txfir_coeff_japan_2484
	.comm	_AR_PCIE_PLL_PWRSAVE_ON_D3,4,2  ## @AR_PCIE_PLL_PWRSAVE_ON_D3
	.comm	_ar9462_2p1_pciephy_clkreq_disable_L1,4,2 ## @ar9462_2p1_pciephy_clkreq_disable_L1
	.comm	_AR_PCIE_PLL_PWRSAVE_ON_D0,4,2  ## @AR_PCIE_PLL_PWRSAVE_ON_D0
	.comm	_ar9462_2p0_mac_core,4,2        ## @ar9462_2p0_mac_core
	.comm	_ar9462_2p0_mac_postamble,4,2   ## @ar9462_2p0_mac_postamble
	.comm	_ar9462_2p0_baseband_core,4,2   ## @ar9462_2p0_baseband_core
	.comm	_ar9462_2p0_baseband_postamble,4,2 ## @ar9462_2p0_baseband_postamble
	.comm	_ar9462_2p0_radio_core,4,2      ## @ar9462_2p0_radio_core
	.comm	_ar9462_2p0_radio_postamble,4,2 ## @ar9462_2p0_radio_postamble
	.comm	_ar9462_2p0_radio_postamble_sys2ant,4,2 ## @ar9462_2p0_radio_postamble_sys2ant
	.comm	_ar9462_2p0_soc_preamble,4,2    ## @ar9462_2p0_soc_preamble
	.comm	_ar9462_2p0_soc_postamble,4,2   ## @ar9462_2p0_soc_postamble
	.comm	_ar9462_2p0_common_rx_gain,4,2  ## @ar9462_2p0_common_rx_gain
	.comm	_ar9462_2p0_pciephy_clkreq_disable_L1,4,2 ## @ar9462_2p0_pciephy_clkreq_disable_L1
	.comm	_ar9462_2p0_modes_fast_clock,4,2 ## @ar9462_2p0_modes_fast_clock
	.comm	_ar9462_2p0_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9462_2p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar955x_1p0_mac_core,4,2        ## @ar955x_1p0_mac_core
	.comm	_ar955x_1p0_mac_postamble,4,2   ## @ar955x_1p0_mac_postamble
	.comm	_ar955x_1p0_baseband_core,4,2   ## @ar955x_1p0_baseband_core
	.comm	_ar955x_1p0_baseband_postamble,4,2 ## @ar955x_1p0_baseband_postamble
	.comm	_ar955x_1p0_radio_core,4,2      ## @ar955x_1p0_radio_core
	.comm	_ar955x_1p0_radio_postamble,4,2 ## @ar955x_1p0_radio_postamble
	.comm	_ar955x_1p0_soc_preamble,4,2    ## @ar955x_1p0_soc_preamble
	.comm	_ar955x_1p0_soc_postamble,4,2   ## @ar955x_1p0_soc_postamble
	.comm	_ar955x_1p0_common_wo_xlna_rx_gain_table,4,2 ## @ar955x_1p0_common_wo_xlna_rx_gain_table
	.comm	_ar955x_1p0_common_wo_xlna_rx_gain_bounds,4,2 ## @ar955x_1p0_common_wo_xlna_rx_gain_bounds
	.comm	_ar955x_1p0_modes_xpa_tx_gain_table,4,2 ## @ar955x_1p0_modes_xpa_tx_gain_table
	.comm	_ar955x_1p0_modes_fast_clock,4,2 ## @ar955x_1p0_modes_fast_clock
	.comm	_qca953x_1p0_mac_core,4,2       ## @qca953x_1p0_mac_core
	.comm	_qca953x_1p0_mac_postamble,4,2  ## @qca953x_1p0_mac_postamble
	.comm	_qca953x_2p0_baseband_core,4,2  ## @qca953x_2p0_baseband_core
	.comm	_qca953x_2p0_baseband_postamble,4,2 ## @qca953x_2p0_baseband_postamble
	.comm	_qca953x_1p0_baseband_core,4,2  ## @qca953x_1p0_baseband_core
	.comm	_qca953x_1p0_baseband_postamble,4,2 ## @qca953x_1p0_baseband_postamble
	.comm	_qca953x_1p0_radio_core,4,2     ## @qca953x_1p0_radio_core
	.comm	_qca953x_1p0_radio_postamble,4,2 ## @qca953x_1p0_radio_postamble
	.comm	_qca953x_1p0_soc_preamble,4,2   ## @qca953x_1p0_soc_preamble
	.comm	_qca953x_1p0_soc_postamble,4,2  ## @qca953x_1p0_soc_postamble
	.comm	_qca953x_2p0_common_wo_xlna_rx_gain_table,4,2 ## @qca953x_2p0_common_wo_xlna_rx_gain_table
	.comm	_qca953x_2p0_common_wo_xlna_rx_gain_bounds,4,2 ## @qca953x_2p0_common_wo_xlna_rx_gain_bounds
	.comm	_qca953x_1p0_common_wo_xlna_rx_gain_table,4,2 ## @qca953x_1p0_common_wo_xlna_rx_gain_table
	.comm	_qca953x_1p0_common_wo_xlna_rx_gain_bounds,4,2 ## @qca953x_1p0_common_wo_xlna_rx_gain_bounds
	.comm	_qca953x_2p0_modes_no_xpa_tx_gain_table,4,2 ## @qca953x_2p0_modes_no_xpa_tx_gain_table
	.comm	_qca953x_1p1_modes_no_xpa_tx_gain_table,4,2 ## @qca953x_1p1_modes_no_xpa_tx_gain_table
	.comm	_qca953x_1p0_modes_no_xpa_tx_gain_table,4,2 ## @qca953x_1p0_modes_no_xpa_tx_gain_table
	.comm	_qca953x_1p0_modes_fast_clock,4,2 ## @qca953x_1p0_modes_fast_clock
	.comm	_qca956x_1p0_mac_core,4,2       ## @qca956x_1p0_mac_core
	.comm	_qca956x_1p0_mac_postamble,4,2  ## @qca956x_1p0_mac_postamble
	.comm	_qca956x_1p0_baseband_core,4,2  ## @qca956x_1p0_baseband_core
	.comm	_qca956x_1p0_baseband_postamble,4,2 ## @qca956x_1p0_baseband_postamble
	.comm	_qca956x_1p0_radio_core,4,2     ## @qca956x_1p0_radio_core
	.comm	_qca956x_1p0_radio_postamble,4,2 ## @qca956x_1p0_radio_postamble
	.comm	_qca956x_1p0_soc_preamble,4,2   ## @qca956x_1p0_soc_preamble
	.comm	_qca956x_1p0_soc_postamble,4,2  ## @qca956x_1p0_soc_postamble
	.comm	_qca956x_1p0_common_wo_xlna_rx_gain_table,4,2 ## @qca956x_1p0_common_wo_xlna_rx_gain_table
	.comm	_qca956x_1p0_common_wo_xlna_rx_gain_bounds,4,2 ## @qca956x_1p0_common_wo_xlna_rx_gain_bounds
	.comm	_qca956x_1p0_modes_no_xpa_tx_gain_table,4,2 ## @qca956x_1p0_modes_no_xpa_tx_gain_table
	.comm	_qca956x_1p0_baseband_postamble_dfs_channel,4,2 ## @qca956x_1p0_baseband_postamble_dfs_channel
	.comm	_qca956x_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ## @qca956x_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_qca956x_1p0_modes_fast_clock,4,2 ## @qca956x_1p0_modes_fast_clock
	.comm	_ar9580_1p0_mac_core,4,2        ## @ar9580_1p0_mac_core
	.comm	_ar9580_1p0_mac_postamble,4,2   ## @ar9580_1p0_mac_postamble
	.comm	_ar9580_1p0_baseband_core,4,2   ## @ar9580_1p0_baseband_core
	.comm	_ar9580_1p0_baseband_postamble,4,2 ## @ar9580_1p0_baseband_postamble
	.comm	_ar9580_1p0_radio_core,4,2      ## @ar9580_1p0_radio_core
	.comm	_ar9580_1p0_radio_postamble,4,2 ## @ar9580_1p0_radio_postamble
	.comm	_ar9580_1p0_soc_preamble,4,2    ## @ar9580_1p0_soc_preamble
	.comm	_ar9580_1p0_soc_postamble,4,2   ## @ar9580_1p0_soc_postamble
	.comm	_ar9580_1p0_rx_gain_table,4,2   ## @ar9580_1p0_rx_gain_table
	.comm	_ar9580_1p0_low_ob_db_tx_gain_table,4,2 ## @ar9580_1p0_low_ob_db_tx_gain_table
	.comm	_ar9580_1p0_modes_fast_clock,4,2 ## @ar9580_1p0_modes_fast_clock
	.comm	_ar9580_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9580_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9580_1p0_baseband_postamble_dfs_channel,4,2 ## @ar9580_1p0_baseband_postamble_dfs_channel
	.comm	_ar9565_1p1_mac_core,4,2        ## @ar9565_1p1_mac_core
	.comm	_ar9565_1p1_mac_postamble,4,2   ## @ar9565_1p1_mac_postamble
	.comm	_ar9565_1p1_baseband_core,4,2   ## @ar9565_1p1_baseband_core
	.comm	_ar9565_1p1_baseband_postamble,4,2 ## @ar9565_1p1_baseband_postamble
	.comm	_ar9565_1p1_radio_core,4,2      ## @ar9565_1p1_radio_core
	.comm	_ar9565_1p1_radio_postamble,4,2 ## @ar9565_1p1_radio_postamble
	.comm	_ar9565_1p1_soc_preamble,4,2    ## @ar9565_1p1_soc_preamble
	.comm	_ar9565_1p1_soc_postamble,4,2   ## @ar9565_1p1_soc_postamble
	.comm	_ar9565_1p1_Common_rx_gain_table,4,2 ## @ar9565_1p1_Common_rx_gain_table
	.comm	_ar9565_1p1_Modes_lowest_ob_db_tx_gain_table,4,2 ## @ar9565_1p1_Modes_lowest_ob_db_tx_gain_table
	.comm	_ar9565_1p1_pciephy_clkreq_disable_L1,4,2 ## @ar9565_1p1_pciephy_clkreq_disable_L1
	.comm	_ar9565_1p1_modes_fast_clock,4,2 ## @ar9565_1p1_modes_fast_clock
	.comm	_ar9565_1p1_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9565_1p1_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9565_1p0_mac_core,4,2        ## @ar9565_1p0_mac_core
	.comm	_ar9565_1p0_mac_postamble,4,2   ## @ar9565_1p0_mac_postamble
	.comm	_ar9565_1p0_baseband_core,4,2   ## @ar9565_1p0_baseband_core
	.comm	_ar9565_1p0_baseband_postamble,4,2 ## @ar9565_1p0_baseband_postamble
	.comm	_ar9565_1p0_radio_core,4,2      ## @ar9565_1p0_radio_core
	.comm	_ar9565_1p0_radio_postamble,4,2 ## @ar9565_1p0_radio_postamble
	.comm	_ar9565_1p0_soc_preamble,4,2    ## @ar9565_1p0_soc_preamble
	.comm	_ar9565_1p0_soc_postamble,4,2   ## @ar9565_1p0_soc_postamble
	.comm	_ar9565_1p0_Common_rx_gain_table,4,2 ## @ar9565_1p0_Common_rx_gain_table
	.comm	_ar9565_1p0_Modes_lowest_ob_db_tx_gain_table,4,2 ## @ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
	.comm	_ar9565_1p0_pciephy_clkreq_disable_L1,4,2 ## @ar9565_1p0_pciephy_clkreq_disable_L1
	.comm	_ar9565_1p0_modes_fast_clock,4,2 ## @ar9565_1p0_modes_fast_clock
	.comm	_ar9565_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9565_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9300_2p2_mac_core,4,2        ## @ar9300_2p2_mac_core
	.comm	_ar9300_2p2_mac_postamble,4,2   ## @ar9300_2p2_mac_postamble
	.comm	_ar9300_2p2_baseband_core,4,2   ## @ar9300_2p2_baseband_core
	.comm	_ar9300_2p2_baseband_postamble,4,2 ## @ar9300_2p2_baseband_postamble
	.comm	_ar9300_2p2_radio_core,4,2      ## @ar9300_2p2_radio_core
	.comm	_ar9300_2p2_radio_postamble,4,2 ## @ar9300_2p2_radio_postamble
	.comm	_ar9300_2p2_soc_preamble,4,2    ## @ar9300_2p2_soc_preamble
	.comm	_ar9300_2p2_soc_postamble,4,2   ## @ar9300_2p2_soc_postamble
	.comm	_ar9300Common_rx_gain_table_2p2,4,2 ## @ar9300Common_rx_gain_table_2p2
	.comm	_ar9300Modes_lowest_ob_db_tx_gain_table_2p2,4,2 ## @ar9300Modes_lowest_ob_db_tx_gain_table_2p2
	.comm	_ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,4,2 ## @ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
	.comm	_ar9300Modes_fast_clock_2p2,4,2 ## @ar9300Modes_fast_clock_2p2
	.comm	_ar9300_2p2_baseband_core_txfir_coeff_japan_2484,4,2 ## @ar9300_2p2_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9300_2p2_baseband_postamble_dfs_channel,4,2 ## @ar9300_2p2_baseband_postamble_dfs_channel
	.no_dead_strip	_ar9003_hw_init_mode_regs
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ar9003_hw_init_mode_regs
_ar9003_hw_init_mode_regs:              ; @ar9003_hw_init_mode_regs
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	bl	_AR_SREV_9330_11
	cbz	x0, LBB0_3
; %bb.1:
Lloh0:
	adrp	x20, _ATH_INI_CORE@GOTPAGE
Lloh1:
	ldr	x20, [x20, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh2:
	adrp	x8, _ar9331_1p1_mac_core@GOTPAGE
Lloh3:
	ldr	x8, [x8, _ar9331_1p1_mac_core@GOTPAGEOFF]
Lloh4:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh5:
	adrp	x21, _ATH_INI_POST@GOTPAGE
Lloh6:
	ldr	x21, [x21, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh7:
	adrp	x8, _ar9331_1p1_mac_postamble@GOTPAGE
Lloh8:
	ldr	x8, [x8, _ar9331_1p1_mac_postamble@GOTPAGEOFF]
Lloh9:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh10:
	adrp	x8, _ar9331_1p1_baseband_core@GOTPAGE
Lloh11:
	ldr	x8, [x8, _ar9331_1p1_baseband_core@GOTPAGEOFF]
Lloh12:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh13:
	adrp	x8, _ar9331_1p1_baseband_postamble@GOTPAGE
Lloh14:
	ldr	x8, [x8, _ar9331_1p1_baseband_postamble@GOTPAGEOFF]
Lloh15:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh16:
	adrp	x8, _ar9331_1p1_radio_core@GOTPAGE
Lloh17:
	ldr	x8, [x8, _ar9331_1p1_radio_core@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh19:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh21:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh22:
	adrp	x8, _ar9331_1p1_soc_preamble@GOTPAGE
Lloh23:
	ldr	x8, [x8, _ar9331_1p1_soc_preamble@GOTPAGEOFF]
Lloh24:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh25:
	adrp	x8, _ar9331_1p1_soc_postamble@GOTPAGE
Lloh26:
	ldr	x8, [x8, _ar9331_1p1_soc_postamble@GOTPAGEOFF]
Lloh27:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh28:
	adrp	x8, _ar9331_common_rx_gain_1p1@GOTPAGE
Lloh29:
	ldr	x8, [x8, _ar9331_common_rx_gain_1p1@GOTPAGEOFF]
Lloh30:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh31:
	adrp	x8, _ar9331_modes_lowest_ob_db_tx_gain_1p1@GOTPAGE
Lloh32:
	ldr	x8, [x8, _ar9331_modes_lowest_ob_db_tx_gain_1p1@GOTPAGEOFF]
Lloh33:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh34:
	adrp	x8, _ar9331_1p1_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh35:
	ldr	x8, [x8, _ar9331_1p1_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #80]
	add	x0, x19, #76
	cbz	x8, LBB0_6
; %bb.2:
Lloh37:
	adrp	x8, _ar9331_1p1_xtal_25M@GOTPAGE
Lloh38:
	ldr	x8, [x8, _ar9331_1p1_xtal_25M@GOTPAGEOFF]
	b	LBB0_15
LBB0_3:
	mov	x0, x19
	bl	_AR_SREV_9330_12
	cbz	x0, LBB0_7
; %bb.4:
Lloh39:
	adrp	x20, _ATH_INI_CORE@GOTPAGE
Lloh40:
	ldr	x20, [x20, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh41:
	adrp	x8, _ar9331_1p2_mac_core@GOTPAGE
Lloh42:
	ldr	x8, [x8, _ar9331_1p2_mac_core@GOTPAGEOFF]
Lloh43:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh44:
	adrp	x21, _ATH_INI_POST@GOTPAGE
Lloh45:
	ldr	x21, [x21, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh46:
	adrp	x8, _ar9331_1p2_mac_postamble@GOTPAGE
Lloh47:
	ldr	x8, [x8, _ar9331_1p2_mac_postamble@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh49:
	adrp	x8, _ar9331_1p2_baseband_core@GOTPAGE
Lloh50:
	ldr	x8, [x8, _ar9331_1p2_baseband_core@GOTPAGEOFF]
Lloh51:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh52:
	adrp	x8, _ar9331_1p2_baseband_postamble@GOTPAGE
Lloh53:
	ldr	x8, [x8, _ar9331_1p2_baseband_postamble@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh55:
	adrp	x8, _ar9331_1p2_radio_core@GOTPAGE
Lloh56:
	ldr	x8, [x8, _ar9331_1p2_radio_core@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh58:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh59:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh60:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh61:
	adrp	x8, _ar9331_1p2_soc_preamble@GOTPAGE
Lloh62:
	ldr	x8, [x8, _ar9331_1p2_soc_preamble@GOTPAGEOFF]
Lloh63:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh64:
	adrp	x8, _ar9331_1p2_soc_postamble@GOTPAGE
Lloh65:
	ldr	x8, [x8, _ar9331_1p2_soc_postamble@GOTPAGEOFF]
Lloh66:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh67:
	adrp	x8, _ar9331_common_rx_gain_1p2@GOTPAGE
Lloh68:
	ldr	x8, [x8, _ar9331_common_rx_gain_1p2@GOTPAGEOFF]
Lloh69:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh70:
	adrp	x8, _ar9331_modes_lowest_ob_db_tx_gain_1p2@GOTPAGE
Lloh71:
	ldr	x8, [x8, _ar9331_modes_lowest_ob_db_tx_gain_1p2@GOTPAGEOFF]
Lloh72:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh73:
	adrp	x8, _ar9331_1p2_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh74:
	ldr	x8, [x8, _ar9331_1p2_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh75:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #80]
	add	x0, x19, #76
	cbz	x8, LBB0_10
; %bb.5:
Lloh76:
	adrp	x8, _ar9331_1p2_xtal_25M@GOTPAGE
Lloh77:
	ldr	x8, [x8, _ar9331_1p2_xtal_25M@GOTPAGEOFF]
	b	LBB0_15
LBB0_6:
Lloh78:
	adrp	x8, _ar9331_1p1_xtal_40M@GOTPAGE
Lloh79:
	ldr	x8, [x8, _ar9331_1p1_xtal_40M@GOTPAGEOFF]
	b	LBB0_15
LBB0_7:
	mov	x0, x19
	bl	_AR_SREV_9340
	cbz	x0, LBB0_11
; %bb.8:
Lloh80:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh81:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh82:
	adrp	x8, _ar9340_1p0_mac_core@GOTPAGE
Lloh83:
	ldr	x8, [x8, _ar9340_1p0_mac_core@GOTPAGEOFF]
Lloh84:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh85:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh86:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh87:
	adrp	x8, _ar9340_1p0_mac_postamble@GOTPAGE
Lloh88:
	ldr	x8, [x8, _ar9340_1p0_mac_postamble@GOTPAGEOFF]
Lloh89:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh90:
	adrp	x8, _ar9340_1p0_baseband_core@GOTPAGE
Lloh91:
	ldr	x8, [x8, _ar9340_1p0_baseband_core@GOTPAGEOFF]
Lloh92:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh93:
	adrp	x8, _ar9340_1p0_baseband_postamble@GOTPAGE
Lloh94:
	ldr	x8, [x8, _ar9340_1p0_baseband_postamble@GOTPAGEOFF]
Lloh95:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh96:
	adrp	x8, _ar9340_1p0_radio_core@GOTPAGE
Lloh97:
	ldr	x8, [x8, _ar9340_1p0_radio_core@GOTPAGEOFF]
Lloh98:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh99:
	adrp	x8, _ar9340_1p0_radio_postamble@GOTPAGE
Lloh100:
	ldr	x8, [x8, _ar9340_1p0_radio_postamble@GOTPAGEOFF]
Lloh101:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh102:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh103:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh104:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh105:
	adrp	x8, _ar9340_1p0_soc_preamble@GOTPAGE
Lloh106:
	ldr	x8, [x8, _ar9340_1p0_soc_preamble@GOTPAGEOFF]
Lloh107:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh108:
	adrp	x8, _ar9340_1p0_soc_postamble@GOTPAGE
Lloh109:
	ldr	x8, [x8, _ar9340_1p0_soc_postamble@GOTPAGEOFF]
Lloh110:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh111:
	adrp	x8, _ar9340Common_wo_xlna_rx_gain_table_1p0@GOTPAGE
Lloh112:
	ldr	x8, [x8, _ar9340Common_wo_xlna_rx_gain_table_1p0@GOTPAGEOFF]
Lloh113:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh114:
	adrp	x8, _ar9340Modes_high_ob_db_tx_gain_table_1p0@GOTPAGE
Lloh115:
	ldr	x8, [x8, _ar9340Modes_high_ob_db_tx_gain_table_1p0@GOTPAGEOFF]
Lloh116:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh117:
	adrp	x8, _ar9340Modes_fast_clock_1p0@GOTPAGE
Lloh118:
	ldr	x8, [x8, _ar9340Modes_fast_clock_1p0@GOTPAGEOFF]
Lloh119:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh120:
	adrp	x8, _ar9340_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh121:
	ldr	x8, [x8, _ar9340_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh122:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh123:
	adrp	x8, _ar9340_1p0_baseband_postamble_dfs_channel@GOTPAGE
Lloh124:
	ldr	x8, [x8, _ar9340_1p0_baseband_postamble_dfs_channel@GOTPAGEOFF]
Lloh125:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #80]
	cbz	x8, LBB0_14
LBB0_9:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
LBB0_10:
Lloh126:
	adrp	x8, _ar9331_1p2_xtal_40M@GOTPAGE
Lloh127:
	ldr	x8, [x8, _ar9331_1p2_xtal_40M@GOTPAGEOFF]
	b	LBB0_15
LBB0_11:
	mov	x0, x19
	bl	_AR_SREV_9485_11_OR_LATER
	cbz	x0, LBB0_17
; %bb.12:
Lloh128:
	adrp	x20, _ATH_INI_CORE@GOTPAGE
Lloh129:
	ldr	x20, [x20, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh130:
	adrp	x8, _ar9485_1_1_mac_core@GOTPAGE
Lloh131:
	ldr	x8, [x8, _ar9485_1_1_mac_core@GOTPAGEOFF]
Lloh132:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh133:
	adrp	x21, _ATH_INI_POST@GOTPAGE
Lloh134:
	ldr	x21, [x21, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh135:
	adrp	x8, _ar9485_1_1_mac_postamble@GOTPAGE
Lloh136:
	ldr	x8, [x8, _ar9485_1_1_mac_postamble@GOTPAGEOFF]
Lloh137:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh138:
	adrp	x22, _ATH_INI_PRE@GOTPAGE
Lloh139:
	ldr	x22, [x22, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x8, [x19, #48]
	ldr	x9, [x22]
	add	x0, x8, x9, lsl #2
Lloh140:
	adrp	x8, _ar9485_1_1@GOTPAGE
Lloh141:
	ldr	x8, [x8, _ar9485_1_1@GOTPAGEOFF]
Lloh142:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh143:
	adrp	x8, _ar9485_1_1_baseband_core@GOTPAGE
Lloh144:
	ldr	x8, [x8, _ar9485_1_1_baseband_core@GOTPAGEOFF]
Lloh145:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh146:
	adrp	x8, _ar9485_1_1_baseband_postamble@GOTPAGE
Lloh147:
	ldr	x8, [x8, _ar9485_1_1_baseband_postamble@GOTPAGEOFF]
Lloh148:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh149:
	adrp	x8, _ar9485_1_1_radio_core@GOTPAGE
Lloh150:
	ldr	x8, [x8, _ar9485_1_1_radio_core@GOTPAGEOFF]
Lloh151:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh152:
	adrp	x8, _ar9485_1_1_radio_postamble@GOTPAGE
Lloh153:
	ldr	x8, [x8, _ar9485_1_1_radio_postamble@GOTPAGEOFF]
Lloh154:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x22]
	add	x0, x8, x9, lsl #2
Lloh155:
	adrp	x8, _ar9485_1_1_soc_preamble@GOTPAGE
Lloh156:
	ldr	x8, [x8, _ar9485_1_1_soc_preamble@GOTPAGEOFF]
Lloh157:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh158:
	adrp	x8, _ar9485Common_wo_xlna_rx_gain_1_1@GOTPAGE
Lloh159:
	ldr	x8, [x8, _ar9485Common_wo_xlna_rx_gain_1_1@GOTPAGEOFF]
Lloh160:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh161:
	adrp	x8, _ar9485_modes_lowest_ob_db_tx_gain_1_1@GOTPAGE
Lloh162:
	ldr	x8, [x8, _ar9485_modes_lowest_ob_db_tx_gain_1_1@GOTPAGEOFF]
Lloh163:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh164:
	adrp	x8, _ar9485_1_1_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh165:
	ldr	x8, [x8, _ar9485_1_1_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh166:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
Lloh167:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGE
Lloh168:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGEOFF]
Lloh169:
	ldr	w9, [x9]
	add	x0, x19, #16
	tst	w9, w8
	b.eq	LBB0_22
; %bb.13:
Lloh170:
	adrp	x20, _ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1@GOTPAGE
Lloh171:
	ldr	x20, [x20, _ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1@GOTPAGEOFF]
	b	LBB0_23
LBB0_14:
	add	x0, x19, #76
Lloh172:
	adrp	x8, _ar9340_1p0_radio_core_40M@GOTPAGE
Lloh173:
	ldr	x8, [x8, _ar9340_1p0_radio_core_40M@GOTPAGEOFF]
LBB0_15:
	ldr	w1, [x8]
LBB0_16:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	b	_INIT_INI_ARRAY
LBB0_17:
	mov	x0, x19
	bl	_AR_SREV_9462_21
	cbz	x0, LBB0_25
; %bb.18:
Lloh174:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh175:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh176:
	adrp	x8, _ar9462_2p1_mac_core@GOTPAGE
Lloh177:
	ldr	x8, [x8, _ar9462_2p1_mac_core@GOTPAGEOFF]
Lloh178:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh179:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh180:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh181:
	adrp	x8, _ar9462_2p1_mac_postamble@GOTPAGE
Lloh182:
	ldr	x8, [x8, _ar9462_2p1_mac_postamble@GOTPAGEOFF]
Lloh183:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh184:
	adrp	x8, _ar9462_2p1_baseband_core@GOTPAGE
Lloh185:
	ldr	x8, [x8, _ar9462_2p1_baseband_core@GOTPAGEOFF]
Lloh186:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh187:
	adrp	x8, _ar9462_2p1_baseband_postamble@GOTPAGE
Lloh188:
	ldr	x8, [x8, _ar9462_2p1_baseband_postamble@GOTPAGEOFF]
Lloh189:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh190:
	adrp	x8, _ar9462_2p1_radio_core@GOTPAGE
Lloh191:
	ldr	x8, [x8, _ar9462_2p1_radio_core@GOTPAGEOFF]
Lloh192:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh193:
	adrp	x8, _ar9462_2p1_radio_postamble@GOTPAGE
Lloh194:
	ldr	x8, [x8, _ar9462_2p1_radio_postamble@GOTPAGEOFF]
Lloh195:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #72
Lloh196:
	adrp	x8, _ar9462_2p1_radio_postamble_sys2ant@GOTPAGE
Lloh197:
	ldr	x8, [x8, _ar9462_2p1_radio_postamble_sys2ant@GOTPAGEOFF]
Lloh198:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh199:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh200:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh201:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh202:
	adrp	x8, _ar9462_2p1_soc_preamble@GOTPAGE
Lloh203:
	ldr	x8, [x8, _ar9462_2p1_soc_preamble@GOTPAGEOFF]
Lloh204:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh205:
	adrp	x8, _ar9462_2p1_soc_postamble@GOTPAGE
Lloh206:
	ldr	x8, [x8, _ar9462_2p1_soc_postamble@GOTPAGEOFF]
Lloh207:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh208:
	adrp	x8, _ar9462_2p1_common_rx_gain@GOTPAGE
Lloh209:
	ldr	x8, [x8, _ar9462_2p1_common_rx_gain@GOTPAGEOFF]
Lloh210:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh211:
	adrp	x8, _ar9462_2p1_modes_fast_clock@GOTPAGE
Lloh212:
	ldr	x8, [x8, _ar9462_2p1_modes_fast_clock@GOTPAGEOFF]
Lloh213:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh214:
	adrp	x8, _ar9462_2p1_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh215:
	ldr	x8, [x8, _ar9462_2p1_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh216:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
Lloh217:
	adrp	x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGE
Lloh218:
	ldr	x21, [x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_9
; %bb.19:
Lloh219:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGE
Lloh220:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGEOFF]
Lloh221:
	ldr	w9, [x9]
Lloh222:
	adrp	x20, _ar9462_2p1_pciephy_clkreq_disable_L1@GOTPAGE
Lloh223:
	ldr	x20, [x20, _ar9462_2p1_pciephy_clkreq_disable_L1@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_21
; %bb.20:
	add	x0, x19, #16
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_9
LBB0_21:
Lloh224:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGE
Lloh225:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGEOFF]
Lloh226:
	ldr	w9, [x9]
	tst	w9, w8
	b.ne	LBB0_24
	b	LBB0_9
LBB0_22:
Lloh227:
	adrp	x20, _ar9485_1_1_pcie_phy_clkreq_disable_L1@GOTPAGE
Lloh228:
	ldr	x20, [x20, _ar9485_1_1_pcie_phy_clkreq_disable_L1@GOTPAGEOFF]
LBB0_23:
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
LBB0_24:
	add	x0, x19, #12
	ldr	w1, [x20]
	b	LBB0_16
LBB0_25:
	mov	x0, x19
	bl	_AR_SREV_9462_20
	cbz	x0, LBB0_32
; %bb.26:
Lloh229:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh230:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh231:
	adrp	x8, _ar9462_2p0_mac_core@GOTPAGE
Lloh232:
	ldr	x8, [x8, _ar9462_2p0_mac_core@GOTPAGEOFF]
Lloh233:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh234:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh235:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh236:
	adrp	x8, _ar9462_2p0_mac_postamble@GOTPAGE
Lloh237:
	ldr	x8, [x8, _ar9462_2p0_mac_postamble@GOTPAGEOFF]
Lloh238:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh239:
	adrp	x8, _ar9462_2p0_baseband_core@GOTPAGE
Lloh240:
	ldr	x8, [x8, _ar9462_2p0_baseband_core@GOTPAGEOFF]
Lloh241:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh242:
	adrp	x8, _ar9462_2p0_baseband_postamble@GOTPAGE
Lloh243:
	ldr	x8, [x8, _ar9462_2p0_baseband_postamble@GOTPAGEOFF]
Lloh244:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh245:
	adrp	x8, _ar9462_2p0_radio_core@GOTPAGE
Lloh246:
	ldr	x8, [x8, _ar9462_2p0_radio_core@GOTPAGEOFF]
Lloh247:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh248:
	adrp	x8, _ar9462_2p0_radio_postamble@GOTPAGE
Lloh249:
	ldr	x8, [x8, _ar9462_2p0_radio_postamble@GOTPAGEOFF]
Lloh250:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #72
Lloh251:
	adrp	x8, _ar9462_2p0_radio_postamble_sys2ant@GOTPAGE
Lloh252:
	ldr	x8, [x8, _ar9462_2p0_radio_postamble_sys2ant@GOTPAGEOFF]
Lloh253:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh254:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh255:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh256:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh257:
	adrp	x8, _ar9462_2p0_soc_preamble@GOTPAGE
Lloh258:
	ldr	x8, [x8, _ar9462_2p0_soc_preamble@GOTPAGEOFF]
Lloh259:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh260:
	adrp	x8, _ar9462_2p0_soc_postamble@GOTPAGE
Lloh261:
	ldr	x8, [x8, _ar9462_2p0_soc_postamble@GOTPAGEOFF]
Lloh262:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh263:
	adrp	x8, _ar9462_2p0_common_rx_gain@GOTPAGE
Lloh264:
	ldr	x8, [x8, _ar9462_2p0_common_rx_gain@GOTPAGEOFF]
Lloh265:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
Lloh266:
	adrp	x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGE
Lloh267:
	ldr	x21, [x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_31
; %bb.27:
Lloh268:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGE
Lloh269:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGEOFF]
Lloh270:
	ldr	w9, [x9]
Lloh271:
	adrp	x20, _ar9462_2p0_pciephy_clkreq_disable_L1@GOTPAGE
Lloh272:
	ldr	x20, [x20, _ar9462_2p0_pciephy_clkreq_disable_L1@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_29
; %bb.28:
	add	x0, x19, #16
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_31
LBB0_29:
Lloh273:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGE
Lloh274:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGEOFF]
Lloh275:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_31
; %bb.30:
	add	x0, x19, #12
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
LBB0_31:
	add	x0, x19, #8
Lloh276:
	adrp	x8, _ar9462_2p0_modes_fast_clock@GOTPAGE
Lloh277:
	ldr	x8, [x8, _ar9462_2p0_modes_fast_clock@GOTPAGEOFF]
Lloh278:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh279:
	adrp	x8, _ar9462_2p0_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh280:
	ldr	x8, [x8, _ar9462_2p0_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
	b	LBB0_15
LBB0_32:
	mov	x0, x19
	bl	_AR_SREV_9550
	cbz	x0, LBB0_34
; %bb.33:
Lloh281:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh282:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh283:
	adrp	x8, _ar955x_1p0_mac_core@GOTPAGE
Lloh284:
	ldr	x8, [x8, _ar955x_1p0_mac_core@GOTPAGEOFF]
Lloh285:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh286:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh287:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh288:
	adrp	x8, _ar955x_1p0_mac_postamble@GOTPAGE
Lloh289:
	ldr	x8, [x8, _ar955x_1p0_mac_postamble@GOTPAGEOFF]
Lloh290:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh291:
	adrp	x8, _ar955x_1p0_baseband_core@GOTPAGE
Lloh292:
	ldr	x8, [x8, _ar955x_1p0_baseband_core@GOTPAGEOFF]
Lloh293:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh294:
	adrp	x8, _ar955x_1p0_baseband_postamble@GOTPAGE
Lloh295:
	ldr	x8, [x8, _ar955x_1p0_baseband_postamble@GOTPAGEOFF]
Lloh296:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh297:
	adrp	x8, _ar955x_1p0_radio_core@GOTPAGE
Lloh298:
	ldr	x8, [x8, _ar955x_1p0_radio_core@GOTPAGEOFF]
Lloh299:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh300:
	adrp	x8, _ar955x_1p0_radio_postamble@GOTPAGE
Lloh301:
	ldr	x8, [x8, _ar955x_1p0_radio_postamble@GOTPAGEOFF]
Lloh302:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh303:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh304:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh305:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh306:
	adrp	x8, _ar955x_1p0_soc_preamble@GOTPAGE
Lloh307:
	ldr	x8, [x8, _ar955x_1p0_soc_preamble@GOTPAGEOFF]
Lloh308:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh309:
	adrp	x8, _ar955x_1p0_soc_postamble@GOTPAGE
Lloh310:
	ldr	x8, [x8, _ar955x_1p0_soc_postamble@GOTPAGEOFF]
Lloh311:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh312:
	adrp	x8, _ar955x_1p0_common_wo_xlna_rx_gain_table@GOTPAGE
Lloh313:
	ldr	x8, [x8, _ar955x_1p0_common_wo_xlna_rx_gain_table@GOTPAGEOFF]
Lloh314:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #68
Lloh315:
	adrp	x8, _ar955x_1p0_common_wo_xlna_rx_gain_bounds@GOTPAGE
Lloh316:
	ldr	x8, [x8, _ar955x_1p0_common_wo_xlna_rx_gain_bounds@GOTPAGEOFF]
Lloh317:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh318:
	adrp	x8, _ar955x_1p0_modes_xpa_tx_gain_table@GOTPAGE
Lloh319:
	ldr	x8, [x8, _ar955x_1p0_modes_xpa_tx_gain_table@GOTPAGEOFF]
Lloh320:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh321:
	adrp	x8, _ar955x_1p0_modes_fast_clock@GOTPAGE
Lloh322:
	ldr	x8, [x8, _ar955x_1p0_modes_fast_clock@GOTPAGEOFF]
	b	LBB0_15
LBB0_34:
	mov	x0, x19
	bl	_AR_SREV_9531
	cbz	x0, LBB0_37
; %bb.35:
Lloh323:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh324:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh325:
	adrp	x8, _qca953x_1p0_mac_core@GOTPAGE
Lloh326:
	ldr	x8, [x8, _qca953x_1p0_mac_core@GOTPAGEOFF]
Lloh327:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh328:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh329:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh330:
	adrp	x8, _qca953x_1p0_mac_postamble@GOTPAGE
Lloh331:
	ldr	x8, [x8, _qca953x_1p0_mac_postamble@GOTPAGEOFF]
Lloh332:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	mov	x0, x19
	bl	_AR_SREV_9531_20
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
Lloh333:
	adrp	x10, _qca953x_1p0_baseband_core@GOTPAGE
Lloh334:
	ldr	x10, [x10, _qca953x_1p0_baseband_core@GOTPAGEOFF]
	add	x8, x8, x9, lsl #2
Lloh335:
	adrp	x9, _qca953x_2p0_baseband_core@GOTPAGE
Lloh336:
	ldr	x9, [x9, _qca953x_2p0_baseband_core@GOTPAGEOFF]
	cmp	x0, #0
	csel	x9, x10, x9, eq
	ldr	w1, [x9]
Lloh337:
	adrp	x9, _qca953x_1p0_baseband_postamble@GOTPAGE
Lloh338:
	ldr	x9, [x9, _qca953x_1p0_baseband_postamble@GOTPAGEOFF]
Lloh339:
	adrp	x10, _qca953x_2p0_baseband_postamble@GOTPAGE
Lloh340:
	ldr	x10, [x10, _qca953x_2p0_baseband_postamble@GOTPAGEOFF]
	csel	x22, x9, x10, eq
	mov	x0, x8
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
	ldr	w1, [x22]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh341:
	adrp	x8, _qca953x_1p0_radio_core@GOTPAGE
Lloh342:
	ldr	x8, [x8, _qca953x_1p0_radio_core@GOTPAGEOFF]
Lloh343:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh344:
	adrp	x8, _qca953x_1p0_radio_postamble@GOTPAGE
Lloh345:
	ldr	x8, [x8, _qca953x_1p0_radio_postamble@GOTPAGEOFF]
Lloh346:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh347:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh348:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh349:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh350:
	adrp	x8, _qca953x_1p0_soc_preamble@GOTPAGE
Lloh351:
	ldr	x8, [x8, _qca953x_1p0_soc_preamble@GOTPAGEOFF]
Lloh352:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh353:
	adrp	x8, _qca953x_1p0_soc_postamble@GOTPAGE
Lloh354:
	ldr	x8, [x8, _qca953x_1p0_soc_postamble@GOTPAGEOFF]
Lloh355:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	mov	x0, x19
	bl	_AR_SREV_9531_20
Lloh356:
	adrp	x9, _qca953x_1p0_common_wo_xlna_rx_gain_table@GOTPAGE
Lloh357:
	ldr	x9, [x9, _qca953x_1p0_common_wo_xlna_rx_gain_table@GOTPAGEOFF]
	add	x8, x19, #24
Lloh358:
	adrp	x10, _qca953x_2p0_common_wo_xlna_rx_gain_table@GOTPAGE
Lloh359:
	ldr	x10, [x10, _qca953x_2p0_common_wo_xlna_rx_gain_table@GOTPAGEOFF]
	cmp	x0, #0
	csel	x9, x9, x10, eq
	ldr	w1, [x9]
Lloh360:
	adrp	x9, _qca953x_1p0_common_wo_xlna_rx_gain_bounds@GOTPAGE
Lloh361:
	ldr	x9, [x9, _qca953x_1p0_common_wo_xlna_rx_gain_bounds@GOTPAGEOFF]
	add	x20, x19, #68
Lloh362:
	adrp	x10, _qca953x_2p0_common_wo_xlna_rx_gain_bounds@GOTPAGE
Lloh363:
	ldr	x10, [x10, _qca953x_2p0_common_wo_xlna_rx_gain_bounds@GOTPAGEOFF]
	csel	x21, x9, x10, eq
	mov	x0, x8
	bl	_INIT_INI_ARRAY
	ldr	w1, [x21]
	mov	x0, x20
	bl	_INIT_INI_ARRAY
	mov	x0, x19
	bl	_AR_SREV_9531_20
	cbz	x0, LBB0_39
; %bb.36:
Lloh364:
	adrp	x8, _qca953x_2p0_modes_no_xpa_tx_gain_table@GOTPAGE
Lloh365:
	ldr	x8, [x8, _qca953x_2p0_modes_no_xpa_tx_gain_table@GOTPAGEOFF]
	b	LBB0_40
LBB0_37:
	mov	x0, x19
	bl	_AR_SREV_9561
	cbz	x0, LBB0_41
; %bb.38:
Lloh366:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh367:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh368:
	adrp	x8, _qca956x_1p0_mac_core@GOTPAGE
Lloh369:
	ldr	x8, [x8, _qca956x_1p0_mac_core@GOTPAGEOFF]
Lloh370:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh371:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh372:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh373:
	adrp	x8, _qca956x_1p0_mac_postamble@GOTPAGE
Lloh374:
	ldr	x8, [x8, _qca956x_1p0_mac_postamble@GOTPAGEOFF]
Lloh375:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh376:
	adrp	x8, _qca956x_1p0_baseband_core@GOTPAGE
Lloh377:
	ldr	x8, [x8, _qca956x_1p0_baseband_core@GOTPAGEOFF]
Lloh378:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh379:
	adrp	x8, _qca956x_1p0_baseband_postamble@GOTPAGE
Lloh380:
	ldr	x8, [x8, _qca956x_1p0_baseband_postamble@GOTPAGEOFF]
Lloh381:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh382:
	adrp	x8, _qca956x_1p0_radio_core@GOTPAGE
Lloh383:
	ldr	x8, [x8, _qca956x_1p0_radio_core@GOTPAGEOFF]
Lloh384:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh385:
	adrp	x8, _qca956x_1p0_radio_postamble@GOTPAGE
Lloh386:
	ldr	x8, [x8, _qca956x_1p0_radio_postamble@GOTPAGEOFF]
Lloh387:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh388:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh389:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh390:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh391:
	adrp	x8, _qca956x_1p0_soc_preamble@GOTPAGE
Lloh392:
	ldr	x8, [x8, _qca956x_1p0_soc_preamble@GOTPAGEOFF]
Lloh393:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh394:
	adrp	x8, _qca956x_1p0_soc_postamble@GOTPAGE
Lloh395:
	ldr	x8, [x8, _qca956x_1p0_soc_postamble@GOTPAGEOFF]
Lloh396:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh397:
	adrp	x8, _qca956x_1p0_common_wo_xlna_rx_gain_table@GOTPAGE
Lloh398:
	ldr	x8, [x8, _qca956x_1p0_common_wo_xlna_rx_gain_table@GOTPAGEOFF]
Lloh399:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #68
Lloh400:
	adrp	x8, _qca956x_1p0_common_wo_xlna_rx_gain_bounds@GOTPAGE
Lloh401:
	ldr	x8, [x8, _qca956x_1p0_common_wo_xlna_rx_gain_bounds@GOTPAGEOFF]
Lloh402:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh403:
	adrp	x8, _qca956x_1p0_modes_no_xpa_tx_gain_table@GOTPAGE
Lloh404:
	ldr	x8, [x8, _qca956x_1p0_modes_no_xpa_tx_gain_table@GOTPAGEOFF]
Lloh405:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh406:
	adrp	x8, _qca956x_1p0_baseband_postamble_dfs_channel@GOTPAGE
Lloh407:
	ldr	x8, [x8, _qca956x_1p0_baseband_postamble_dfs_channel@GOTPAGEOFF]
Lloh408:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh409:
	adrp	x8, _qca956x_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh410:
	ldr	x8, [x8, _qca956x_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh411:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh412:
	adrp	x8, _qca956x_1p0_modes_fast_clock@GOTPAGE
Lloh413:
	ldr	x8, [x8, _qca956x_1p0_modes_fast_clock@GOTPAGEOFF]
	b	LBB0_15
LBB0_39:
	mov	x0, x19
	bl	_AR_SREV_9531_11
Lloh414:
	adrp	x8, _qca953x_1p1_modes_no_xpa_tx_gain_table@GOTPAGE
Lloh415:
	ldr	x8, [x8, _qca953x_1p1_modes_no_xpa_tx_gain_table@GOTPAGEOFF]
Lloh416:
	adrp	x9, _qca953x_1p0_modes_no_xpa_tx_gain_table@GOTPAGE
Lloh417:
	ldr	x9, [x9, _qca953x_1p0_modes_no_xpa_tx_gain_table@GOTPAGEOFF]
	cmp	x0, #0
	csel	x8, x9, x8, eq
LBB0_40:
	add	x0, x19, #20
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh418:
	adrp	x8, _qca953x_1p0_modes_fast_clock@GOTPAGE
Lloh419:
	ldr	x8, [x8, _qca953x_1p0_modes_fast_clock@GOTPAGEOFF]
	b	LBB0_15
LBB0_41:
	mov	x0, x19
	bl	_AR_SREV_9580
	cbz	x0, LBB0_44
; %bb.42:
Lloh420:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh421:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh422:
	adrp	x8, _ar9580_1p0_mac_core@GOTPAGE
Lloh423:
	ldr	x8, [x8, _ar9580_1p0_mac_core@GOTPAGEOFF]
Lloh424:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh425:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh426:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh427:
	adrp	x8, _ar9580_1p0_mac_postamble@GOTPAGE
Lloh428:
	ldr	x8, [x8, _ar9580_1p0_mac_postamble@GOTPAGEOFF]
Lloh429:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh430:
	adrp	x8, _ar9580_1p0_baseband_core@GOTPAGE
Lloh431:
	ldr	x8, [x8, _ar9580_1p0_baseband_core@GOTPAGEOFF]
Lloh432:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh433:
	adrp	x8, _ar9580_1p0_baseband_postamble@GOTPAGE
Lloh434:
	ldr	x8, [x8, _ar9580_1p0_baseband_postamble@GOTPAGEOFF]
Lloh435:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh436:
	adrp	x8, _ar9580_1p0_radio_core@GOTPAGE
Lloh437:
	ldr	x8, [x8, _ar9580_1p0_radio_core@GOTPAGEOFF]
Lloh438:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh439:
	adrp	x8, _ar9580_1p0_radio_postamble@GOTPAGE
Lloh440:
	ldr	x8, [x8, _ar9580_1p0_radio_postamble@GOTPAGEOFF]
Lloh441:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh442:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh443:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh444:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh445:
	adrp	x8, _ar9580_1p0_soc_preamble@GOTPAGE
Lloh446:
	ldr	x8, [x8, _ar9580_1p0_soc_preamble@GOTPAGEOFF]
Lloh447:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh448:
	adrp	x8, _ar9580_1p0_soc_postamble@GOTPAGE
Lloh449:
	ldr	x8, [x8, _ar9580_1p0_soc_postamble@GOTPAGEOFF]
Lloh450:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh451:
	adrp	x8, _ar9580_1p0_rx_gain_table@GOTPAGE
Lloh452:
	ldr	x8, [x8, _ar9580_1p0_rx_gain_table@GOTPAGEOFF]
Lloh453:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh454:
	adrp	x8, _ar9580_1p0_low_ob_db_tx_gain_table@GOTPAGE
Lloh455:
	ldr	x8, [x8, _ar9580_1p0_low_ob_db_tx_gain_table@GOTPAGEOFF]
Lloh456:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh457:
	adrp	x8, _ar9580_1p0_modes_fast_clock@GOTPAGE
Lloh458:
	ldr	x8, [x8, _ar9580_1p0_modes_fast_clock@GOTPAGEOFF]
Lloh459:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh460:
	adrp	x8, _ar9580_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh461:
	ldr	x8, [x8, _ar9580_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh462:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh463:
	adrp	x8, _ar9580_1p0_baseband_postamble_dfs_channel@GOTPAGE
Lloh464:
	ldr	x8, [x8, _ar9580_1p0_baseband_postamble_dfs_channel@GOTPAGEOFF]
LBB0_43:
	ldr	w1, [x8]
	mov	x0, x19
	b	LBB0_16
LBB0_44:
	mov	x0, x19
	bl	_AR_SREV_9565_11_OR_LATER
	cbz	x0, LBB0_51
; %bb.45:
Lloh465:
	adrp	x21, _ATH_INI_CORE@GOTPAGE
Lloh466:
	ldr	x21, [x21, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh467:
	adrp	x8, _ar9565_1p1_mac_core@GOTPAGE
Lloh468:
	ldr	x8, [x8, _ar9565_1p1_mac_core@GOTPAGEOFF]
Lloh469:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh470:
	adrp	x20, _ATH_INI_POST@GOTPAGE
Lloh471:
	ldr	x20, [x20, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh472:
	adrp	x8, _ar9565_1p1_mac_postamble@GOTPAGE
Lloh473:
	ldr	x8, [x8, _ar9565_1p1_mac_postamble@GOTPAGEOFF]
Lloh474:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh475:
	adrp	x8, _ar9565_1p1_baseband_core@GOTPAGE
Lloh476:
	ldr	x8, [x8, _ar9565_1p1_baseband_core@GOTPAGEOFF]
Lloh477:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh478:
	adrp	x8, _ar9565_1p1_baseband_postamble@GOTPAGE
Lloh479:
	ldr	x8, [x8, _ar9565_1p1_baseband_postamble@GOTPAGEOFF]
Lloh480:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh481:
	adrp	x8, _ar9565_1p1_radio_core@GOTPAGE
Lloh482:
	ldr	x8, [x8, _ar9565_1p1_radio_core@GOTPAGEOFF]
Lloh483:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh484:
	adrp	x8, _ar9565_1p1_radio_postamble@GOTPAGE
Lloh485:
	ldr	x8, [x8, _ar9565_1p1_radio_postamble@GOTPAGEOFF]
Lloh486:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh487:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh488:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh489:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh490:
	adrp	x8, _ar9565_1p1_soc_preamble@GOTPAGE
Lloh491:
	ldr	x8, [x8, _ar9565_1p1_soc_preamble@GOTPAGEOFF]
Lloh492:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh493:
	adrp	x8, _ar9565_1p1_soc_postamble@GOTPAGE
Lloh494:
	ldr	x8, [x8, _ar9565_1p1_soc_postamble@GOTPAGEOFF]
Lloh495:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh496:
	adrp	x8, _ar9565_1p1_Common_rx_gain_table@GOTPAGE
Lloh497:
	ldr	x8, [x8, _ar9565_1p1_Common_rx_gain_table@GOTPAGEOFF]
Lloh498:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh499:
	adrp	x8, _ar9565_1p1_Modes_lowest_ob_db_tx_gain_table@GOTPAGE
Lloh500:
	ldr	x8, [x8, _ar9565_1p1_Modes_lowest_ob_db_tx_gain_table@GOTPAGEOFF]
Lloh501:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
Lloh502:
	adrp	x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGE
Lloh503:
	ldr	x21, [x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_50
; %bb.46:
Lloh504:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGE
Lloh505:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGEOFF]
Lloh506:
	ldr	w9, [x9]
Lloh507:
	adrp	x20, _ar9565_1p1_pciephy_clkreq_disable_L1@GOTPAGE
Lloh508:
	ldr	x20, [x20, _ar9565_1p1_pciephy_clkreq_disable_L1@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_48
; %bb.47:
	add	x0, x19, #16
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_50
LBB0_48:
Lloh509:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGE
Lloh510:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGEOFF]
Lloh511:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_50
; %bb.49:
	add	x0, x19, #12
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
LBB0_50:
	add	x0, x19, #8
Lloh512:
	adrp	x8, _ar9565_1p1_modes_fast_clock@GOTPAGE
Lloh513:
	ldr	x8, [x8, _ar9565_1p1_modes_fast_clock@GOTPAGEOFF]
Lloh514:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh515:
	adrp	x8, _ar9565_1p1_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh516:
	ldr	x8, [x8, _ar9565_1p1_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
	b	LBB0_15
LBB0_51:
	mov	x0, x19
	bl	_AR_SREV_9565
	mov	x8, x0
	ldr	x9, [x19, #56]
Lloh517:
	adrp	x20, _ATH_INI_CORE@GOTPAGE
Lloh518:
	ldr	x20, [x20, _ATH_INI_CORE@GOTPAGEOFF]
	ldr	x10, [x20]
	add	x0, x9, x10, lsl #2
	cbz	x8, LBB0_58
; %bb.52:
Lloh519:
	adrp	x8, _ar9565_1p0_mac_core@GOTPAGE
Lloh520:
	ldr	x8, [x8, _ar9565_1p0_mac_core@GOTPAGEOFF]
Lloh521:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh522:
	adrp	x21, _ATH_INI_POST@GOTPAGE
Lloh523:
	ldr	x21, [x21, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh524:
	adrp	x8, _ar9565_1p0_mac_postamble@GOTPAGE
Lloh525:
	ldr	x8, [x8, _ar9565_1p0_mac_postamble@GOTPAGEOFF]
Lloh526:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh527:
	adrp	x8, _ar9565_1p0_baseband_core@GOTPAGE
Lloh528:
	ldr	x8, [x8, _ar9565_1p0_baseband_core@GOTPAGEOFF]
Lloh529:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh530:
	adrp	x8, _ar9565_1p0_baseband_postamble@GOTPAGE
Lloh531:
	ldr	x8, [x8, _ar9565_1p0_baseband_postamble@GOTPAGEOFF]
Lloh532:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh533:
	adrp	x8, _ar9565_1p0_radio_core@GOTPAGE
Lloh534:
	ldr	x8, [x8, _ar9565_1p0_radio_core@GOTPAGEOFF]
Lloh535:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh536:
	adrp	x8, _ar9565_1p0_radio_postamble@GOTPAGE
Lloh537:
	ldr	x8, [x8, _ar9565_1p0_radio_postamble@GOTPAGEOFF]
Lloh538:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh539:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh540:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh541:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh542:
	adrp	x8, _ar9565_1p0_soc_preamble@GOTPAGE
Lloh543:
	ldr	x8, [x8, _ar9565_1p0_soc_preamble@GOTPAGEOFF]
Lloh544:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh545:
	adrp	x8, _ar9565_1p0_soc_postamble@GOTPAGE
Lloh546:
	ldr	x8, [x8, _ar9565_1p0_soc_postamble@GOTPAGEOFF]
Lloh547:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh548:
	adrp	x8, _ar9565_1p0_Common_rx_gain_table@GOTPAGE
Lloh549:
	ldr	x8, [x8, _ar9565_1p0_Common_rx_gain_table@GOTPAGEOFF]
Lloh550:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh551:
	adrp	x8, _ar9565_1p0_Modes_lowest_ob_db_tx_gain_table@GOTPAGE
Lloh552:
	ldr	x8, [x8, _ar9565_1p0_Modes_lowest_ob_db_tx_gain_table@GOTPAGEOFF]
Lloh553:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
Lloh554:
	adrp	x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGE
Lloh555:
	ldr	x21, [x21, _AR_PCIE_PLL_PWRSAVE_CONTROL@GOTPAGEOFF]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_57
; %bb.53:
Lloh556:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGE
Lloh557:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D3@GOTPAGEOFF]
Lloh558:
	ldr	w9, [x9]
Lloh559:
	adrp	x20, _ar9565_1p0_pciephy_clkreq_disable_L1@GOTPAGE
Lloh560:
	ldr	x20, [x20, _ar9565_1p0_pciephy_clkreq_disable_L1@GOTPAGEOFF]
	tst	w9, w8
	b.eq	LBB0_55
; %bb.54:
	add	x0, x19, #16
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
	ldr	w8, [x19, #64]
	ldr	w9, [x21]
	tst	w9, w8
	b.eq	LBB0_57
LBB0_55:
Lloh561:
	adrp	x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGE
Lloh562:
	ldr	x9, [x9, _AR_PCIE_PLL_PWRSAVE_ON_D0@GOTPAGEOFF]
Lloh563:
	ldr	w9, [x9]
	tst	w9, w8
	b.eq	LBB0_57
; %bb.56:
	add	x0, x19, #12
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
LBB0_57:
	add	x0, x19, #8
Lloh564:
	adrp	x8, _ar9565_1p0_modes_fast_clock@GOTPAGE
Lloh565:
	ldr	x8, [x8, _ar9565_1p0_modes_fast_clock@GOTPAGEOFF]
Lloh566:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh567:
	adrp	x8, _ar9565_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh568:
	ldr	x8, [x8, _ar9565_1p0_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
	b	LBB0_15
LBB0_58:
Lloh569:
	adrp	x8, _ar9300_2p2_mac_core@GOTPAGE
Lloh570:
	ldr	x8, [x8, _ar9300_2p2_mac_core@GOTPAGEOFF]
Lloh571:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh572:
	adrp	x21, _ATH_INI_POST@GOTPAGE
Lloh573:
	ldr	x21, [x21, _ATH_INI_POST@GOTPAGEOFF]
	ldr	x8, [x19, #56]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh574:
	adrp	x8, _ar9300_2p2_mac_postamble@GOTPAGE
Lloh575:
	ldr	x8, [x8, _ar9300_2p2_mac_postamble@GOTPAGEOFF]
Lloh576:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh577:
	adrp	x8, _ar9300_2p2_baseband_core@GOTPAGE
Lloh578:
	ldr	x8, [x8, _ar9300_2p2_baseband_core@GOTPAGEOFF]
Lloh579:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #48]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh580:
	adrp	x8, _ar9300_2p2_baseband_postamble@GOTPAGE
Lloh581:
	ldr	x8, [x8, _ar9300_2p2_baseband_postamble@GOTPAGEOFF]
Lloh582:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x20]
	add	x0, x8, x9, lsl #2
Lloh583:
	adrp	x8, _ar9300_2p2_radio_core@GOTPAGE
Lloh584:
	ldr	x8, [x8, _ar9300_2p2_radio_core@GOTPAGEOFF]
Lloh585:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #40]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh586:
	adrp	x8, _ar9300_2p2_radio_postamble@GOTPAGE
Lloh587:
	ldr	x8, [x8, _ar9300_2p2_radio_postamble@GOTPAGEOFF]
Lloh588:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh589:
	adrp	x8, _ATH_INI_PRE@GOTPAGE
Lloh590:
	ldr	x8, [x8, _ATH_INI_PRE@GOTPAGEOFF]
	ldr	x9, [x19, #32]
Lloh591:
	ldr	x8, [x8]
	add	x0, x9, x8, lsl #2
Lloh592:
	adrp	x8, _ar9300_2p2_soc_preamble@GOTPAGE
Lloh593:
	ldr	x8, [x8, _ar9300_2p2_soc_preamble@GOTPAGEOFF]
Lloh594:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	ldr	x8, [x19, #32]
	ldr	x9, [x21]
	add	x0, x8, x9, lsl #2
Lloh595:
	adrp	x8, _ar9300_2p2_soc_postamble@GOTPAGE
Lloh596:
	ldr	x8, [x8, _ar9300_2p2_soc_postamble@GOTPAGEOFF]
Lloh597:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #24
Lloh598:
	adrp	x8, _ar9300Common_rx_gain_table_2p2@GOTPAGE
Lloh599:
	ldr	x8, [x8, _ar9300Common_rx_gain_table_2p2@GOTPAGEOFF]
Lloh600:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #20
Lloh601:
	adrp	x8, _ar9300Modes_lowest_ob_db_tx_gain_table_2p2@GOTPAGE
Lloh602:
	ldr	x8, [x8, _ar9300Modes_lowest_ob_db_tx_gain_table_2p2@GOTPAGEOFF]
Lloh603:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #16
Lloh604:
	adrp	x20, _ar9300PciePhy_pll_on_clkreq_disable_L1_2p2@GOTPAGE
Lloh605:
	ldr	x20, [x20, _ar9300PciePhy_pll_on_clkreq_disable_L1_2p2@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #12
	ldr	w1, [x20]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #8
Lloh606:
	adrp	x8, _ar9300Modes_fast_clock_2p2@GOTPAGE
Lloh607:
	ldr	x8, [x8, _ar9300Modes_fast_clock_2p2@GOTPAGEOFF]
Lloh608:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
	add	x0, x19, #4
Lloh609:
	adrp	x8, _ar9300_2p2_baseband_core_txfir_coeff_japan_2484@GOTPAGE
Lloh610:
	ldr	x8, [x8, _ar9300_2p2_baseband_core_txfir_coeff_japan_2484@GOTPAGEOFF]
Lloh611:
	ldr	w1, [x8]
	bl	_INIT_INI_ARRAY
Lloh612:
	adrp	x8, _ar9300_2p2_baseband_postamble_dfs_channel@GOTPAGE
Lloh613:
	ldr	x8, [x8, _ar9300_2p2_baseband_postamble_dfs_channel@GOTPAGEOFF]
	b	LBB0_43
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh13, Lloh14, Lloh15
	.loh AdrpLdrGotLdr	Lloh10, Lloh11, Lloh12
	.loh AdrpLdrGotLdr	Lloh7, Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh5, Lloh6
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGot	Lloh76, Lloh77
	.loh AdrpLdrGot	Lloh78, Lloh79
	.loh AdrpLdrGotLdr	Lloh123, Lloh124, Lloh125
	.loh AdrpLdrGotLdr	Lloh120, Lloh121, Lloh122
	.loh AdrpLdrGotLdr	Lloh117, Lloh118, Lloh119
	.loh AdrpLdrGotLdr	Lloh114, Lloh115, Lloh116
	.loh AdrpLdrGotLdr	Lloh111, Lloh112, Lloh113
	.loh AdrpLdrGotLdr	Lloh108, Lloh109, Lloh110
	.loh AdrpLdrGotLdr	Lloh105, Lloh106, Lloh107
	.loh AdrpLdrGotLdr	Lloh102, Lloh103, Lloh104
	.loh AdrpLdrGotLdr	Lloh99, Lloh100, Lloh101
	.loh AdrpLdrGotLdr	Lloh96, Lloh97, Lloh98
	.loh AdrpLdrGotLdr	Lloh93, Lloh94, Lloh95
	.loh AdrpLdrGotLdr	Lloh90, Lloh91, Lloh92
	.loh AdrpLdrGotLdr	Lloh87, Lloh88, Lloh89
	.loh AdrpLdrGot	Lloh85, Lloh86
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGot	Lloh80, Lloh81
	.loh AdrpLdrGot	Lloh126, Lloh127
	.loh AdrpLdrGotLdr	Lloh167, Lloh168, Lloh169
	.loh AdrpLdrGotLdr	Lloh164, Lloh165, Lloh166
	.loh AdrpLdrGotLdr	Lloh161, Lloh162, Lloh163
	.loh AdrpLdrGotLdr	Lloh158, Lloh159, Lloh160
	.loh AdrpLdrGotLdr	Lloh155, Lloh156, Lloh157
	.loh AdrpLdrGotLdr	Lloh152, Lloh153, Lloh154
	.loh AdrpLdrGotLdr	Lloh149, Lloh150, Lloh151
	.loh AdrpLdrGotLdr	Lloh146, Lloh147, Lloh148
	.loh AdrpLdrGotLdr	Lloh143, Lloh144, Lloh145
	.loh AdrpLdrGotLdr	Lloh140, Lloh141, Lloh142
	.loh AdrpLdrGot	Lloh138, Lloh139
	.loh AdrpLdrGotLdr	Lloh135, Lloh136, Lloh137
	.loh AdrpLdrGot	Lloh133, Lloh134
	.loh AdrpLdrGotLdr	Lloh130, Lloh131, Lloh132
	.loh AdrpLdrGot	Lloh128, Lloh129
	.loh AdrpLdrGot	Lloh170, Lloh171
	.loh AdrpLdrGot	Lloh172, Lloh173
	.loh AdrpLdrGot	Lloh217, Lloh218
	.loh AdrpLdrGotLdr	Lloh214, Lloh215, Lloh216
	.loh AdrpLdrGotLdr	Lloh211, Lloh212, Lloh213
	.loh AdrpLdrGotLdr	Lloh208, Lloh209, Lloh210
	.loh AdrpLdrGotLdr	Lloh205, Lloh206, Lloh207
	.loh AdrpLdrGotLdr	Lloh202, Lloh203, Lloh204
	.loh AdrpLdrGotLdr	Lloh199, Lloh200, Lloh201
	.loh AdrpLdrGotLdr	Lloh196, Lloh197, Lloh198
	.loh AdrpLdrGotLdr	Lloh193, Lloh194, Lloh195
	.loh AdrpLdrGotLdr	Lloh190, Lloh191, Lloh192
	.loh AdrpLdrGotLdr	Lloh187, Lloh188, Lloh189
	.loh AdrpLdrGotLdr	Lloh184, Lloh185, Lloh186
	.loh AdrpLdrGotLdr	Lloh181, Lloh182, Lloh183
	.loh AdrpLdrGot	Lloh179, Lloh180
	.loh AdrpLdrGotLdr	Lloh176, Lloh177, Lloh178
	.loh AdrpLdrGot	Lloh174, Lloh175
	.loh AdrpLdrGot	Lloh222, Lloh223
	.loh AdrpLdrGotLdr	Lloh219, Lloh220, Lloh221
	.loh AdrpLdrGotLdr	Lloh224, Lloh225, Lloh226
	.loh AdrpLdrGot	Lloh227, Lloh228
	.loh AdrpLdrGot	Lloh266, Lloh267
	.loh AdrpLdrGotLdr	Lloh263, Lloh264, Lloh265
	.loh AdrpLdrGotLdr	Lloh260, Lloh261, Lloh262
	.loh AdrpLdrGotLdr	Lloh257, Lloh258, Lloh259
	.loh AdrpLdrGotLdr	Lloh254, Lloh255, Lloh256
	.loh AdrpLdrGotLdr	Lloh251, Lloh252, Lloh253
	.loh AdrpLdrGotLdr	Lloh248, Lloh249, Lloh250
	.loh AdrpLdrGotLdr	Lloh245, Lloh246, Lloh247
	.loh AdrpLdrGotLdr	Lloh242, Lloh243, Lloh244
	.loh AdrpLdrGotLdr	Lloh239, Lloh240, Lloh241
	.loh AdrpLdrGotLdr	Lloh236, Lloh237, Lloh238
	.loh AdrpLdrGot	Lloh234, Lloh235
	.loh AdrpLdrGotLdr	Lloh231, Lloh232, Lloh233
	.loh AdrpLdrGot	Lloh229, Lloh230
	.loh AdrpLdrGot	Lloh271, Lloh272
	.loh AdrpLdrGotLdr	Lloh268, Lloh269, Lloh270
	.loh AdrpLdrGotLdr	Lloh273, Lloh274, Lloh275
	.loh AdrpLdrGot	Lloh279, Lloh280
	.loh AdrpLdrGotLdr	Lloh276, Lloh277, Lloh278
	.loh AdrpLdrGot	Lloh321, Lloh322
	.loh AdrpLdrGotLdr	Lloh318, Lloh319, Lloh320
	.loh AdrpLdrGotLdr	Lloh315, Lloh316, Lloh317
	.loh AdrpLdrGotLdr	Lloh312, Lloh313, Lloh314
	.loh AdrpLdrGotLdr	Lloh309, Lloh310, Lloh311
	.loh AdrpLdrGotLdr	Lloh306, Lloh307, Lloh308
	.loh AdrpLdrGotLdr	Lloh303, Lloh304, Lloh305
	.loh AdrpLdrGotLdr	Lloh300, Lloh301, Lloh302
	.loh AdrpLdrGotLdr	Lloh297, Lloh298, Lloh299
	.loh AdrpLdrGotLdr	Lloh294, Lloh295, Lloh296
	.loh AdrpLdrGotLdr	Lloh291, Lloh292, Lloh293
	.loh AdrpLdrGotLdr	Lloh288, Lloh289, Lloh290
	.loh AdrpLdrGot	Lloh286, Lloh287
	.loh AdrpLdrGotLdr	Lloh283, Lloh284, Lloh285
	.loh AdrpLdrGot	Lloh281, Lloh282
	.loh AdrpLdrGot	Lloh362, Lloh363
	.loh AdrpLdrGot	Lloh360, Lloh361
	.loh AdrpLdrGot	Lloh358, Lloh359
	.loh AdrpLdrGot	Lloh356, Lloh357
	.loh AdrpLdrGotLdr	Lloh353, Lloh354, Lloh355
	.loh AdrpLdrGotLdr	Lloh350, Lloh351, Lloh352
	.loh AdrpLdrGotLdr	Lloh347, Lloh348, Lloh349
	.loh AdrpLdrGotLdr	Lloh344, Lloh345, Lloh346
	.loh AdrpLdrGotLdr	Lloh341, Lloh342, Lloh343
	.loh AdrpLdrGot	Lloh339, Lloh340
	.loh AdrpLdrGot	Lloh337, Lloh338
	.loh AdrpLdrGot	Lloh335, Lloh336
	.loh AdrpLdrGot	Lloh333, Lloh334
	.loh AdrpLdrGotLdr	Lloh330, Lloh331, Lloh332
	.loh AdrpLdrGot	Lloh328, Lloh329
	.loh AdrpLdrGotLdr	Lloh325, Lloh326, Lloh327
	.loh AdrpLdrGot	Lloh323, Lloh324
	.loh AdrpLdrGot	Lloh364, Lloh365
	.loh AdrpLdrGot	Lloh412, Lloh413
	.loh AdrpLdrGotLdr	Lloh409, Lloh410, Lloh411
	.loh AdrpLdrGotLdr	Lloh406, Lloh407, Lloh408
	.loh AdrpLdrGotLdr	Lloh403, Lloh404, Lloh405
	.loh AdrpLdrGotLdr	Lloh400, Lloh401, Lloh402
	.loh AdrpLdrGotLdr	Lloh397, Lloh398, Lloh399
	.loh AdrpLdrGotLdr	Lloh394, Lloh395, Lloh396
	.loh AdrpLdrGotLdr	Lloh391, Lloh392, Lloh393
	.loh AdrpLdrGotLdr	Lloh388, Lloh389, Lloh390
	.loh AdrpLdrGotLdr	Lloh385, Lloh386, Lloh387
	.loh AdrpLdrGotLdr	Lloh382, Lloh383, Lloh384
	.loh AdrpLdrGotLdr	Lloh379, Lloh380, Lloh381
	.loh AdrpLdrGotLdr	Lloh376, Lloh377, Lloh378
	.loh AdrpLdrGotLdr	Lloh373, Lloh374, Lloh375
	.loh AdrpLdrGot	Lloh371, Lloh372
	.loh AdrpLdrGotLdr	Lloh368, Lloh369, Lloh370
	.loh AdrpLdrGot	Lloh366, Lloh367
	.loh AdrpLdrGot	Lloh416, Lloh417
	.loh AdrpLdrGot	Lloh414, Lloh415
	.loh AdrpLdrGot	Lloh418, Lloh419
	.loh AdrpLdrGot	Lloh463, Lloh464
	.loh AdrpLdrGotLdr	Lloh460, Lloh461, Lloh462
	.loh AdrpLdrGotLdr	Lloh457, Lloh458, Lloh459
	.loh AdrpLdrGotLdr	Lloh454, Lloh455, Lloh456
	.loh AdrpLdrGotLdr	Lloh451, Lloh452, Lloh453
	.loh AdrpLdrGotLdr	Lloh448, Lloh449, Lloh450
	.loh AdrpLdrGotLdr	Lloh445, Lloh446, Lloh447
	.loh AdrpLdrGotLdr	Lloh442, Lloh443, Lloh444
	.loh AdrpLdrGotLdr	Lloh439, Lloh440, Lloh441
	.loh AdrpLdrGotLdr	Lloh436, Lloh437, Lloh438
	.loh AdrpLdrGotLdr	Lloh433, Lloh434, Lloh435
	.loh AdrpLdrGotLdr	Lloh430, Lloh431, Lloh432
	.loh AdrpLdrGotLdr	Lloh427, Lloh428, Lloh429
	.loh AdrpLdrGot	Lloh425, Lloh426
	.loh AdrpLdrGotLdr	Lloh422, Lloh423, Lloh424
	.loh AdrpLdrGot	Lloh420, Lloh421
	.loh AdrpLdrGot	Lloh502, Lloh503
	.loh AdrpLdrGotLdr	Lloh499, Lloh500, Lloh501
	.loh AdrpLdrGotLdr	Lloh496, Lloh497, Lloh498
	.loh AdrpLdrGotLdr	Lloh493, Lloh494, Lloh495
	.loh AdrpLdrGotLdr	Lloh490, Lloh491, Lloh492
	.loh AdrpLdrGotLdr	Lloh487, Lloh488, Lloh489
	.loh AdrpLdrGotLdr	Lloh484, Lloh485, Lloh486
	.loh AdrpLdrGotLdr	Lloh481, Lloh482, Lloh483
	.loh AdrpLdrGotLdr	Lloh478, Lloh479, Lloh480
	.loh AdrpLdrGotLdr	Lloh475, Lloh476, Lloh477
	.loh AdrpLdrGotLdr	Lloh472, Lloh473, Lloh474
	.loh AdrpLdrGot	Lloh470, Lloh471
	.loh AdrpLdrGotLdr	Lloh467, Lloh468, Lloh469
	.loh AdrpLdrGot	Lloh465, Lloh466
	.loh AdrpLdrGot	Lloh507, Lloh508
	.loh AdrpLdrGotLdr	Lloh504, Lloh505, Lloh506
	.loh AdrpLdrGotLdr	Lloh509, Lloh510, Lloh511
	.loh AdrpLdrGot	Lloh515, Lloh516
	.loh AdrpLdrGotLdr	Lloh512, Lloh513, Lloh514
	.loh AdrpLdrGot	Lloh517, Lloh518
	.loh AdrpLdrGot	Lloh554, Lloh555
	.loh AdrpLdrGotLdr	Lloh551, Lloh552, Lloh553
	.loh AdrpLdrGotLdr	Lloh548, Lloh549, Lloh550
	.loh AdrpLdrGotLdr	Lloh545, Lloh546, Lloh547
	.loh AdrpLdrGotLdr	Lloh542, Lloh543, Lloh544
	.loh AdrpLdrGotLdr	Lloh539, Lloh540, Lloh541
	.loh AdrpLdrGotLdr	Lloh536, Lloh537, Lloh538
	.loh AdrpLdrGotLdr	Lloh533, Lloh534, Lloh535
	.loh AdrpLdrGotLdr	Lloh530, Lloh531, Lloh532
	.loh AdrpLdrGotLdr	Lloh527, Lloh528, Lloh529
	.loh AdrpLdrGotLdr	Lloh524, Lloh525, Lloh526
	.loh AdrpLdrGot	Lloh522, Lloh523
	.loh AdrpLdrGotLdr	Lloh519, Lloh520, Lloh521
	.loh AdrpLdrGot	Lloh559, Lloh560
	.loh AdrpLdrGotLdr	Lloh556, Lloh557, Lloh558
	.loh AdrpLdrGotLdr	Lloh561, Lloh562, Lloh563
	.loh AdrpLdrGot	Lloh567, Lloh568
	.loh AdrpLdrGotLdr	Lloh564, Lloh565, Lloh566
	.loh AdrpLdrGot	Lloh612, Lloh613
	.loh AdrpLdrGotLdr	Lloh609, Lloh610, Lloh611
	.loh AdrpLdrGotLdr	Lloh606, Lloh607, Lloh608
	.loh AdrpLdrGot	Lloh604, Lloh605
	.loh AdrpLdrGotLdr	Lloh601, Lloh602, Lloh603
	.loh AdrpLdrGotLdr	Lloh598, Lloh599, Lloh600
	.loh AdrpLdrGotLdr	Lloh595, Lloh596, Lloh597
	.loh AdrpLdrGotLdr	Lloh592, Lloh593, Lloh594
	.loh AdrpLdrGotLdr	Lloh589, Lloh590, Lloh591
	.loh AdrpLdrGotLdr	Lloh586, Lloh587, Lloh588
	.loh AdrpLdrGotLdr	Lloh583, Lloh584, Lloh585
	.loh AdrpLdrGotLdr	Lloh580, Lloh581, Lloh582
	.loh AdrpLdrGotLdr	Lloh577, Lloh578, Lloh579
	.loh AdrpLdrGotLdr	Lloh574, Lloh575, Lloh576
	.loh AdrpLdrGot	Lloh572, Lloh573
	.loh AdrpLdrGotLdr	Lloh569, Lloh570, Lloh571
	.cfi_endproc
                                        ; -- End function
	.comm	_ATH_INI_CORE,8,3               ; @ATH_INI_CORE
	.comm	_ar9331_1p1_mac_core,4,2        ; @ar9331_1p1_mac_core
	.comm	_ATH_INI_POST,8,3               ; @ATH_INI_POST
	.comm	_ar9331_1p1_mac_postamble,4,2   ; @ar9331_1p1_mac_postamble
	.comm	_ar9331_1p1_baseband_core,4,2   ; @ar9331_1p1_baseband_core
	.comm	_ar9331_1p1_baseband_postamble,4,2 ; @ar9331_1p1_baseband_postamble
	.comm	_ar9331_1p1_radio_core,4,2      ; @ar9331_1p1_radio_core
	.comm	_ATH_INI_PRE,8,3                ; @ATH_INI_PRE
	.comm	_ar9331_1p1_soc_preamble,4,2    ; @ar9331_1p1_soc_preamble
	.comm	_ar9331_1p1_soc_postamble,4,2   ; @ar9331_1p1_soc_postamble
	.comm	_ar9331_common_rx_gain_1p1,4,2  ; @ar9331_common_rx_gain_1p1
	.comm	_ar9331_modes_lowest_ob_db_tx_gain_1p1,4,2 ; @ar9331_modes_lowest_ob_db_tx_gain_1p1
	.comm	_ar9331_1p1_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9331_1p1_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9331_1p1_xtal_25M,4,2        ; @ar9331_1p1_xtal_25M
	.comm	_ar9331_1p1_xtal_40M,4,2        ; @ar9331_1p1_xtal_40M
	.comm	_ar9331_1p2_mac_core,4,2        ; @ar9331_1p2_mac_core
	.comm	_ar9331_1p2_mac_postamble,4,2   ; @ar9331_1p2_mac_postamble
	.comm	_ar9331_1p2_baseband_core,4,2   ; @ar9331_1p2_baseband_core
	.comm	_ar9331_1p2_baseband_postamble,4,2 ; @ar9331_1p2_baseband_postamble
	.comm	_ar9331_1p2_radio_core,4,2      ; @ar9331_1p2_radio_core
	.comm	_ar9331_1p2_soc_preamble,4,2    ; @ar9331_1p2_soc_preamble
	.comm	_ar9331_1p2_soc_postamble,4,2   ; @ar9331_1p2_soc_postamble
	.comm	_ar9331_common_rx_gain_1p2,4,2  ; @ar9331_common_rx_gain_1p2
	.comm	_ar9331_modes_lowest_ob_db_tx_gain_1p2,4,2 ; @ar9331_modes_lowest_ob_db_tx_gain_1p2
	.comm	_ar9331_1p2_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9331_1p2_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9331_1p2_xtal_25M,4,2        ; @ar9331_1p2_xtal_25M
	.comm	_ar9331_1p2_xtal_40M,4,2        ; @ar9331_1p2_xtal_40M
	.comm	_ar9340_1p0_mac_core,4,2        ; @ar9340_1p0_mac_core
	.comm	_ar9340_1p0_mac_postamble,4,2   ; @ar9340_1p0_mac_postamble
	.comm	_ar9340_1p0_baseband_core,4,2   ; @ar9340_1p0_baseband_core
	.comm	_ar9340_1p0_baseband_postamble,4,2 ; @ar9340_1p0_baseband_postamble
	.comm	_ar9340_1p0_radio_core,4,2      ; @ar9340_1p0_radio_core
	.comm	_ar9340_1p0_radio_postamble,4,2 ; @ar9340_1p0_radio_postamble
	.comm	_ar9340_1p0_soc_preamble,4,2    ; @ar9340_1p0_soc_preamble
	.comm	_ar9340_1p0_soc_postamble,4,2   ; @ar9340_1p0_soc_postamble
	.comm	_ar9340Common_wo_xlna_rx_gain_table_1p0,4,2 ; @ar9340Common_wo_xlna_rx_gain_table_1p0
	.comm	_ar9340Modes_high_ob_db_tx_gain_table_1p0,4,2 ; @ar9340Modes_high_ob_db_tx_gain_table_1p0
	.comm	_ar9340Modes_fast_clock_1p0,4,2 ; @ar9340Modes_fast_clock_1p0
	.comm	_ar9340_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9340_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9340_1p0_baseband_postamble_dfs_channel,4,2 ; @ar9340_1p0_baseband_postamble_dfs_channel
	.comm	_ar9340_1p0_radio_core_40M,4,2  ; @ar9340_1p0_radio_core_40M
	.comm	_ar9485_1_1_mac_core,4,2        ; @ar9485_1_1_mac_core
	.comm	_ar9485_1_1_mac_postamble,4,2   ; @ar9485_1_1_mac_postamble
	.comm	_ar9485_1_1,4,2                 ; @ar9485_1_1
	.comm	_ar9485_1_1_baseband_core,4,2   ; @ar9485_1_1_baseband_core
	.comm	_ar9485_1_1_baseband_postamble,4,2 ; @ar9485_1_1_baseband_postamble
	.comm	_ar9485_1_1_radio_core,4,2      ; @ar9485_1_1_radio_core
	.comm	_ar9485_1_1_radio_postamble,4,2 ; @ar9485_1_1_radio_postamble
	.comm	_ar9485_1_1_soc_preamble,4,2    ; @ar9485_1_1_soc_preamble
	.comm	_ar9485Common_wo_xlna_rx_gain_1_1,4,2 ; @ar9485Common_wo_xlna_rx_gain_1_1
	.comm	_ar9485_modes_lowest_ob_db_tx_gain_1_1,4,2 ; @ar9485_modes_lowest_ob_db_tx_gain_1_1
	.comm	_ar9485_1_1_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9485_1_1_baseband_core_txfir_coeff_japan_2484
	.comm	_AR_PCIE_PLL_PWRSAVE_CONTROL,4,2 ; @AR_PCIE_PLL_PWRSAVE_CONTROL
	.comm	_ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1,4,2 ; @ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1
	.comm	_ar9485_1_1_pcie_phy_clkreq_disable_L1,4,2 ; @ar9485_1_1_pcie_phy_clkreq_disable_L1
	.comm	_ar9462_2p1_mac_core,4,2        ; @ar9462_2p1_mac_core
	.comm	_ar9462_2p1_mac_postamble,4,2   ; @ar9462_2p1_mac_postamble
	.comm	_ar9462_2p1_baseband_core,4,2   ; @ar9462_2p1_baseband_core
	.comm	_ar9462_2p1_baseband_postamble,4,2 ; @ar9462_2p1_baseband_postamble
	.comm	_ar9462_2p1_radio_core,4,2      ; @ar9462_2p1_radio_core
	.comm	_ar9462_2p1_radio_postamble,4,2 ; @ar9462_2p1_radio_postamble
	.comm	_ar9462_2p1_radio_postamble_sys2ant,4,2 ; @ar9462_2p1_radio_postamble_sys2ant
	.comm	_ar9462_2p1_soc_preamble,4,2    ; @ar9462_2p1_soc_preamble
	.comm	_ar9462_2p1_soc_postamble,4,2   ; @ar9462_2p1_soc_postamble
	.comm	_ar9462_2p1_common_rx_gain,4,2  ; @ar9462_2p1_common_rx_gain
	.comm	_ar9462_2p1_modes_fast_clock,4,2 ; @ar9462_2p1_modes_fast_clock
	.comm	_ar9462_2p1_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9462_2p1_baseband_core_txfir_coeff_japan_2484
	.comm	_AR_PCIE_PLL_PWRSAVE_ON_D3,4,2  ; @AR_PCIE_PLL_PWRSAVE_ON_D3
	.comm	_ar9462_2p1_pciephy_clkreq_disable_L1,4,2 ; @ar9462_2p1_pciephy_clkreq_disable_L1
	.comm	_AR_PCIE_PLL_PWRSAVE_ON_D0,4,2  ; @AR_PCIE_PLL_PWRSAVE_ON_D0
	.comm	_ar9462_2p0_mac_core,4,2        ; @ar9462_2p0_mac_core
	.comm	_ar9462_2p0_mac_postamble,4,2   ; @ar9462_2p0_mac_postamble
	.comm	_ar9462_2p0_baseband_core,4,2   ; @ar9462_2p0_baseband_core
	.comm	_ar9462_2p0_baseband_postamble,4,2 ; @ar9462_2p0_baseband_postamble
	.comm	_ar9462_2p0_radio_core,4,2      ; @ar9462_2p0_radio_core
	.comm	_ar9462_2p0_radio_postamble,4,2 ; @ar9462_2p0_radio_postamble
	.comm	_ar9462_2p0_radio_postamble_sys2ant,4,2 ; @ar9462_2p0_radio_postamble_sys2ant
	.comm	_ar9462_2p0_soc_preamble,4,2    ; @ar9462_2p0_soc_preamble
	.comm	_ar9462_2p0_soc_postamble,4,2   ; @ar9462_2p0_soc_postamble
	.comm	_ar9462_2p0_common_rx_gain,4,2  ; @ar9462_2p0_common_rx_gain
	.comm	_ar9462_2p0_pciephy_clkreq_disable_L1,4,2 ; @ar9462_2p0_pciephy_clkreq_disable_L1
	.comm	_ar9462_2p0_modes_fast_clock,4,2 ; @ar9462_2p0_modes_fast_clock
	.comm	_ar9462_2p0_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9462_2p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar955x_1p0_mac_core,4,2        ; @ar955x_1p0_mac_core
	.comm	_ar955x_1p0_mac_postamble,4,2   ; @ar955x_1p0_mac_postamble
	.comm	_ar955x_1p0_baseband_core,4,2   ; @ar955x_1p0_baseband_core
	.comm	_ar955x_1p0_baseband_postamble,4,2 ; @ar955x_1p0_baseband_postamble
	.comm	_ar955x_1p0_radio_core,4,2      ; @ar955x_1p0_radio_core
	.comm	_ar955x_1p0_radio_postamble,4,2 ; @ar955x_1p0_radio_postamble
	.comm	_ar955x_1p0_soc_preamble,4,2    ; @ar955x_1p0_soc_preamble
	.comm	_ar955x_1p0_soc_postamble,4,2   ; @ar955x_1p0_soc_postamble
	.comm	_ar955x_1p0_common_wo_xlna_rx_gain_table,4,2 ; @ar955x_1p0_common_wo_xlna_rx_gain_table
	.comm	_ar955x_1p0_common_wo_xlna_rx_gain_bounds,4,2 ; @ar955x_1p0_common_wo_xlna_rx_gain_bounds
	.comm	_ar955x_1p0_modes_xpa_tx_gain_table,4,2 ; @ar955x_1p0_modes_xpa_tx_gain_table
	.comm	_ar955x_1p0_modes_fast_clock,4,2 ; @ar955x_1p0_modes_fast_clock
	.comm	_qca953x_1p0_mac_core,4,2       ; @qca953x_1p0_mac_core
	.comm	_qca953x_1p0_mac_postamble,4,2  ; @qca953x_1p0_mac_postamble
	.comm	_qca953x_2p0_baseband_core,4,2  ; @qca953x_2p0_baseband_core
	.comm	_qca953x_2p0_baseband_postamble,4,2 ; @qca953x_2p0_baseband_postamble
	.comm	_qca953x_1p0_baseband_core,4,2  ; @qca953x_1p0_baseband_core
	.comm	_qca953x_1p0_baseband_postamble,4,2 ; @qca953x_1p0_baseband_postamble
	.comm	_qca953x_1p0_radio_core,4,2     ; @qca953x_1p0_radio_core
	.comm	_qca953x_1p0_radio_postamble,4,2 ; @qca953x_1p0_radio_postamble
	.comm	_qca953x_1p0_soc_preamble,4,2   ; @qca953x_1p0_soc_preamble
	.comm	_qca953x_1p0_soc_postamble,4,2  ; @qca953x_1p0_soc_postamble
	.comm	_qca953x_2p0_common_wo_xlna_rx_gain_table,4,2 ; @qca953x_2p0_common_wo_xlna_rx_gain_table
	.comm	_qca953x_2p0_common_wo_xlna_rx_gain_bounds,4,2 ; @qca953x_2p0_common_wo_xlna_rx_gain_bounds
	.comm	_qca953x_1p0_common_wo_xlna_rx_gain_table,4,2 ; @qca953x_1p0_common_wo_xlna_rx_gain_table
	.comm	_qca953x_1p0_common_wo_xlna_rx_gain_bounds,4,2 ; @qca953x_1p0_common_wo_xlna_rx_gain_bounds
	.comm	_qca953x_2p0_modes_no_xpa_tx_gain_table,4,2 ; @qca953x_2p0_modes_no_xpa_tx_gain_table
	.comm	_qca953x_1p1_modes_no_xpa_tx_gain_table,4,2 ; @qca953x_1p1_modes_no_xpa_tx_gain_table
	.comm	_qca953x_1p0_modes_no_xpa_tx_gain_table,4,2 ; @qca953x_1p0_modes_no_xpa_tx_gain_table
	.comm	_qca953x_1p0_modes_fast_clock,4,2 ; @qca953x_1p0_modes_fast_clock
	.comm	_qca956x_1p0_mac_core,4,2       ; @qca956x_1p0_mac_core
	.comm	_qca956x_1p0_mac_postamble,4,2  ; @qca956x_1p0_mac_postamble
	.comm	_qca956x_1p0_baseband_core,4,2  ; @qca956x_1p0_baseband_core
	.comm	_qca956x_1p0_baseband_postamble,4,2 ; @qca956x_1p0_baseband_postamble
	.comm	_qca956x_1p0_radio_core,4,2     ; @qca956x_1p0_radio_core
	.comm	_qca956x_1p0_radio_postamble,4,2 ; @qca956x_1p0_radio_postamble
	.comm	_qca956x_1p0_soc_preamble,4,2   ; @qca956x_1p0_soc_preamble
	.comm	_qca956x_1p0_soc_postamble,4,2  ; @qca956x_1p0_soc_postamble
	.comm	_qca956x_1p0_common_wo_xlna_rx_gain_table,4,2 ; @qca956x_1p0_common_wo_xlna_rx_gain_table
	.comm	_qca956x_1p0_common_wo_xlna_rx_gain_bounds,4,2 ; @qca956x_1p0_common_wo_xlna_rx_gain_bounds
	.comm	_qca956x_1p0_modes_no_xpa_tx_gain_table,4,2 ; @qca956x_1p0_modes_no_xpa_tx_gain_table
	.comm	_qca956x_1p0_baseband_postamble_dfs_channel,4,2 ; @qca956x_1p0_baseband_postamble_dfs_channel
	.comm	_qca956x_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ; @qca956x_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_qca956x_1p0_modes_fast_clock,4,2 ; @qca956x_1p0_modes_fast_clock
	.comm	_ar9580_1p0_mac_core,4,2        ; @ar9580_1p0_mac_core
	.comm	_ar9580_1p0_mac_postamble,4,2   ; @ar9580_1p0_mac_postamble
	.comm	_ar9580_1p0_baseband_core,4,2   ; @ar9580_1p0_baseband_core
	.comm	_ar9580_1p0_baseband_postamble,4,2 ; @ar9580_1p0_baseband_postamble
	.comm	_ar9580_1p0_radio_core,4,2      ; @ar9580_1p0_radio_core
	.comm	_ar9580_1p0_radio_postamble,4,2 ; @ar9580_1p0_radio_postamble
	.comm	_ar9580_1p0_soc_preamble,4,2    ; @ar9580_1p0_soc_preamble
	.comm	_ar9580_1p0_soc_postamble,4,2   ; @ar9580_1p0_soc_postamble
	.comm	_ar9580_1p0_rx_gain_table,4,2   ; @ar9580_1p0_rx_gain_table
	.comm	_ar9580_1p0_low_ob_db_tx_gain_table,4,2 ; @ar9580_1p0_low_ob_db_tx_gain_table
	.comm	_ar9580_1p0_modes_fast_clock,4,2 ; @ar9580_1p0_modes_fast_clock
	.comm	_ar9580_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9580_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9580_1p0_baseband_postamble_dfs_channel,4,2 ; @ar9580_1p0_baseband_postamble_dfs_channel
	.comm	_ar9565_1p1_mac_core,4,2        ; @ar9565_1p1_mac_core
	.comm	_ar9565_1p1_mac_postamble,4,2   ; @ar9565_1p1_mac_postamble
	.comm	_ar9565_1p1_baseband_core,4,2   ; @ar9565_1p1_baseband_core
	.comm	_ar9565_1p1_baseband_postamble,4,2 ; @ar9565_1p1_baseband_postamble
	.comm	_ar9565_1p1_radio_core,4,2      ; @ar9565_1p1_radio_core
	.comm	_ar9565_1p1_radio_postamble,4,2 ; @ar9565_1p1_radio_postamble
	.comm	_ar9565_1p1_soc_preamble,4,2    ; @ar9565_1p1_soc_preamble
	.comm	_ar9565_1p1_soc_postamble,4,2   ; @ar9565_1p1_soc_postamble
	.comm	_ar9565_1p1_Common_rx_gain_table,4,2 ; @ar9565_1p1_Common_rx_gain_table
	.comm	_ar9565_1p1_Modes_lowest_ob_db_tx_gain_table,4,2 ; @ar9565_1p1_Modes_lowest_ob_db_tx_gain_table
	.comm	_ar9565_1p1_pciephy_clkreq_disable_L1,4,2 ; @ar9565_1p1_pciephy_clkreq_disable_L1
	.comm	_ar9565_1p1_modes_fast_clock,4,2 ; @ar9565_1p1_modes_fast_clock
	.comm	_ar9565_1p1_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9565_1p1_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9565_1p0_mac_core,4,2        ; @ar9565_1p0_mac_core
	.comm	_ar9565_1p0_mac_postamble,4,2   ; @ar9565_1p0_mac_postamble
	.comm	_ar9565_1p0_baseband_core,4,2   ; @ar9565_1p0_baseband_core
	.comm	_ar9565_1p0_baseband_postamble,4,2 ; @ar9565_1p0_baseband_postamble
	.comm	_ar9565_1p0_radio_core,4,2      ; @ar9565_1p0_radio_core
	.comm	_ar9565_1p0_radio_postamble,4,2 ; @ar9565_1p0_radio_postamble
	.comm	_ar9565_1p0_soc_preamble,4,2    ; @ar9565_1p0_soc_preamble
	.comm	_ar9565_1p0_soc_postamble,4,2   ; @ar9565_1p0_soc_postamble
	.comm	_ar9565_1p0_Common_rx_gain_table,4,2 ; @ar9565_1p0_Common_rx_gain_table
	.comm	_ar9565_1p0_Modes_lowest_ob_db_tx_gain_table,4,2 ; @ar9565_1p0_Modes_lowest_ob_db_tx_gain_table
	.comm	_ar9565_1p0_pciephy_clkreq_disable_L1,4,2 ; @ar9565_1p0_pciephy_clkreq_disable_L1
	.comm	_ar9565_1p0_modes_fast_clock,4,2 ; @ar9565_1p0_modes_fast_clock
	.comm	_ar9565_1p0_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9565_1p0_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9300_2p2_mac_core,4,2        ; @ar9300_2p2_mac_core
	.comm	_ar9300_2p2_mac_postamble,4,2   ; @ar9300_2p2_mac_postamble
	.comm	_ar9300_2p2_baseband_core,4,2   ; @ar9300_2p2_baseband_core
	.comm	_ar9300_2p2_baseband_postamble,4,2 ; @ar9300_2p2_baseband_postamble
	.comm	_ar9300_2p2_radio_core,4,2      ; @ar9300_2p2_radio_core
	.comm	_ar9300_2p2_radio_postamble,4,2 ; @ar9300_2p2_radio_postamble
	.comm	_ar9300_2p2_soc_preamble,4,2    ; @ar9300_2p2_soc_preamble
	.comm	_ar9300_2p2_soc_postamble,4,2   ; @ar9300_2p2_soc_postamble
	.comm	_ar9300Common_rx_gain_table_2p2,4,2 ; @ar9300Common_rx_gain_table_2p2
	.comm	_ar9300Modes_lowest_ob_db_tx_gain_table_2p2,4,2 ; @ar9300Modes_lowest_ob_db_tx_gain_table_2p2
	.comm	_ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,4,2 ; @ar9300PciePhy_pll_on_clkreq_disable_L1_2p2
	.comm	_ar9300Modes_fast_clock_2p2,4,2 ; @ar9300Modes_fast_clock_2p2
	.comm	_ar9300_2p2_baseband_core_txfir_coeff_japan_2484,4,2 ; @ar9300_2p2_baseband_core_txfir_coeff_japan_2484
	.comm	_ar9300_2p2_baseband_postamble_dfs_channel,4,2 ; @ar9300_2p2_baseband_postamble_dfs_channel
	.no_dead_strip	_ar9003_hw_init_mode_regs
.subsections_via_symbols
