	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function x86_64_map_dwarf_register
_x86_64_map_dwarf_register:             ## @x86_64_map_dwarf_register
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movl	%edi, %esi
	leal	-17(%rsi), %eax
	cmpl	$7, %eax
	ja	LBB0_3
## %bb.1:
	movq	_CV_AMD64_XMM0@GOTPCREL(%rip), %rcx
	jmp	LBB0_2
LBB0_3:
	leal	-25(%rsi), %eax
	cmpl	$7, %eax
	ja	LBB0_5
## %bb.4:
	movq	_CV_AMD64_XMM8@GOTPCREL(%rip), %rcx
	jmp	LBB0_2
LBB0_5:
	leal	-33(%rsi), %eax
	cmpl	$7, %eax
	ja	LBB0_7
## %bb.6:
	movq	_CV_AMD64_ST0@GOTPCREL(%rip), %rcx
LBB0_2:
	addl	(%rcx), %eax
	popq	%rbp
	retq
LBB0_7:
	cmpl	$66, %esi
	ja	LBB0_27
## %bb.8:
	movl	%esi, %eax
	leaq	LJTI0_0(%rip), %rcx
	movslq	(%rcx,%rax,4), %rax
	addq	%rcx, %rax
	jmpq	*%rax
LBB0_9:
	movq	_CV_AMD64_RAX@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_11:
	movq	_CV_AMD64_RDX@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_12:
	movq	_CV_AMD64_RCX@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_13:
	movq	_CV_AMD64_RBX@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_14:
	movq	_CV_AMD64_RSI@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_15:
	movq	_CV_AMD64_RDI@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_16:
	movq	_CV_AMD64_RBP@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_17:
	movq	_CV_AMD64_RSP@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_18:
	movq	_CV_AMD64_R8@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_19:
	movq	_CV_AMD64_R9@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_20:
	movq	_CV_AMD64_R10@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_21:
	movq	_CV_AMD64_R11@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_22:
	movq	_CV_AMD64_R12@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_23:
	movq	_CV_AMD64_R13@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_24:
	movq	_CV_AMD64_R14@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_25:
	movq	_CV_AMD64_R15@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_26:
	movq	_CV_AMD64_RIP@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_27:
	leaq	L_.str(%rip), %rdi
                                        ## kill: def $esi killed $esi killed $rsi
	callq	_FIXME
	xorl	%eax, %eax
	popq	%rbp
	retq
LBB0_28:
	movq	_CV_AMD64_EFLAGS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_29:
	movq	_CV_AMD64_ES@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_30:
	movq	_CV_AMD64_CS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_31:
	movq	_CV_AMD64_SS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_32:
	movq	_CV_AMD64_DS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_33:
	movq	_CV_AMD64_FS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_34:
	movq	_CV_AMD64_GS@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_35:
	movq	_CV_AMD64_TR@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_36:
	movq	_CV_AMD64_LDTR@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_37:
	movq	_CV_AMD64_MXCSR@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_38:
	movq	_CV_AMD64_CTRL@GOTPCREL(%rip), %rax
	jmp	LBB0_10
LBB0_39:
	movq	_CV_AMD64_STAT@GOTPCREL(%rip), %rax
LBB0_10:
	movl	(%rax), %eax
	popq	%rbp
	retq
	.cfi_endproc
	.p2align	2, 0x90
	.data_region jt32
.set L0_0_set_9, LBB0_9-LJTI0_0
.set L0_0_set_11, LBB0_11-LJTI0_0
.set L0_0_set_12, LBB0_12-LJTI0_0
.set L0_0_set_13, LBB0_13-LJTI0_0
.set L0_0_set_14, LBB0_14-LJTI0_0
.set L0_0_set_15, LBB0_15-LJTI0_0
.set L0_0_set_16, LBB0_16-LJTI0_0
.set L0_0_set_17, LBB0_17-LJTI0_0
.set L0_0_set_18, LBB0_18-LJTI0_0
.set L0_0_set_19, LBB0_19-LJTI0_0
.set L0_0_set_20, LBB0_20-LJTI0_0
.set L0_0_set_21, LBB0_21-LJTI0_0
.set L0_0_set_22, LBB0_22-LJTI0_0
.set L0_0_set_23, LBB0_23-LJTI0_0
.set L0_0_set_24, LBB0_24-LJTI0_0
.set L0_0_set_25, LBB0_25-LJTI0_0
.set L0_0_set_26, LBB0_26-LJTI0_0
.set L0_0_set_27, LBB0_27-LJTI0_0
.set L0_0_set_28, LBB0_28-LJTI0_0
.set L0_0_set_29, LBB0_29-LJTI0_0
.set L0_0_set_30, LBB0_30-LJTI0_0
.set L0_0_set_31, LBB0_31-LJTI0_0
.set L0_0_set_32, LBB0_32-LJTI0_0
.set L0_0_set_33, LBB0_33-LJTI0_0
.set L0_0_set_34, LBB0_34-LJTI0_0
.set L0_0_set_35, LBB0_35-LJTI0_0
.set L0_0_set_36, LBB0_36-LJTI0_0
.set L0_0_set_37, LBB0_37-LJTI0_0
.set L0_0_set_38, LBB0_38-LJTI0_0
.set L0_0_set_39, LBB0_39-LJTI0_0
LJTI0_0:
	.long	L0_0_set_9
	.long	L0_0_set_11
	.long	L0_0_set_12
	.long	L0_0_set_13
	.long	L0_0_set_14
	.long	L0_0_set_15
	.long	L0_0_set_16
	.long	L0_0_set_17
	.long	L0_0_set_18
	.long	L0_0_set_19
	.long	L0_0_set_20
	.long	L0_0_set_21
	.long	L0_0_set_22
	.long	L0_0_set_23
	.long	L0_0_set_24
	.long	L0_0_set_25
	.long	L0_0_set_26
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_28
	.long	L0_0_set_29
	.long	L0_0_set_30
	.long	L0_0_set_31
	.long	L0_0_set_32
	.long	L0_0_set_33
	.long	L0_0_set_34
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_27
	.long	L0_0_set_35
	.long	L0_0_set_36
	.long	L0_0_set_37
	.long	L0_0_set_38
	.long	L0_0_set_39
	.end_data_region
                                        ## -- End function
	.comm	_CV_AMD64_XMM0,4,2              ## @CV_AMD64_XMM0
	.comm	_CV_AMD64_XMM8,4,2              ## @CV_AMD64_XMM8
	.comm	_CV_AMD64_ST0,4,2               ## @CV_AMD64_ST0
	.comm	_CV_AMD64_RAX,4,2               ## @CV_AMD64_RAX
	.comm	_CV_AMD64_RDX,4,2               ## @CV_AMD64_RDX
	.comm	_CV_AMD64_RCX,4,2               ## @CV_AMD64_RCX
	.comm	_CV_AMD64_RBX,4,2               ## @CV_AMD64_RBX
	.comm	_CV_AMD64_RSI,4,2               ## @CV_AMD64_RSI
	.comm	_CV_AMD64_RDI,4,2               ## @CV_AMD64_RDI
	.comm	_CV_AMD64_RBP,4,2               ## @CV_AMD64_RBP
	.comm	_CV_AMD64_RSP,4,2               ## @CV_AMD64_RSP
	.comm	_CV_AMD64_R8,4,2                ## @CV_AMD64_R8
	.comm	_CV_AMD64_R9,4,2                ## @CV_AMD64_R9
	.comm	_CV_AMD64_R10,4,2               ## @CV_AMD64_R10
	.comm	_CV_AMD64_R11,4,2               ## @CV_AMD64_R11
	.comm	_CV_AMD64_R12,4,2               ## @CV_AMD64_R12
	.comm	_CV_AMD64_R13,4,2               ## @CV_AMD64_R13
	.comm	_CV_AMD64_R14,4,2               ## @CV_AMD64_R14
	.comm	_CV_AMD64_R15,4,2               ## @CV_AMD64_R15
	.comm	_CV_AMD64_RIP,4,2               ## @CV_AMD64_RIP
	.comm	_CV_AMD64_EFLAGS,4,2            ## @CV_AMD64_EFLAGS
	.comm	_CV_AMD64_ES,4,2                ## @CV_AMD64_ES
	.comm	_CV_AMD64_CS,4,2                ## @CV_AMD64_CS
	.comm	_CV_AMD64_SS,4,2                ## @CV_AMD64_SS
	.comm	_CV_AMD64_DS,4,2                ## @CV_AMD64_DS
	.comm	_CV_AMD64_FS,4,2                ## @CV_AMD64_FS
	.comm	_CV_AMD64_GS,4,2                ## @CV_AMD64_GS
	.comm	_CV_AMD64_TR,4,2                ## @CV_AMD64_TR
	.comm	_CV_AMD64_LDTR,4,2              ## @CV_AMD64_LDTR
	.comm	_CV_AMD64_MXCSR,4,2             ## @CV_AMD64_MXCSR
	.comm	_CV_AMD64_CTRL,4,2              ## @CV_AMD64_CTRL
	.comm	_CV_AMD64_STAT,4,2              ## @CV_AMD64_STAT
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"Don't know how to map register %d\n"

	.no_dead_strip	_x86_64_map_dwarf_register
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function x86_64_map_dwarf_register
_x86_64_map_dwarf_register:             ; @x86_64_map_dwarf_register
	.cfi_startproc
; %bb.0:
	stp	x29, x30, [sp, #-16]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 16
	mov	x29, sp
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	sub	w8, w0, #17
	cmp	w8, #7
	b.hi	LBB0_2
; %bb.1:
Lloh0:
	adrp	x9, _CV_AMD64_XMM0@GOTPAGE
Lloh1:
	ldr	x9, [x9, _CV_AMD64_XMM0@GOTPAGEOFF]
	b	LBB0_6
LBB0_2:
	mov	x1, x0
	sub	w8, w0, #25
	cmp	w8, #7
	b.hi	LBB0_4
; %bb.3:
Lloh2:
	adrp	x9, _CV_AMD64_XMM8@GOTPAGE
Lloh3:
	ldr	x9, [x9, _CV_AMD64_XMM8@GOTPAGEOFF]
	b	LBB0_6
LBB0_4:
	sub	w8, w1, #33
	cmp	w8, #7
	b.hi	LBB0_7
; %bb.5:
Lloh4:
	adrp	x9, _CV_AMD64_ST0@GOTPAGE
Lloh5:
	ldr	x9, [x9, _CV_AMD64_ST0@GOTPAGEOFF]
LBB0_6:
	ldr	w9, [x9]
	add	w0, w8, w9
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
LBB0_7:
	cmp	w1, #66
	b.hi	LBB0_26
; %bb.8:
	mov	w8, w1
Lloh6:
	adrp	x9, lJTI0_0@PAGE
Lloh7:
	add	x9, x9, lJTI0_0@PAGEOFF
	adr	x10, LBB0_9
	ldrb	w11, [x9, x8]
	add	x10, x10, x11, lsl #2
	br	x10
LBB0_9:
Lloh8:
	adrp	x8, _CV_AMD64_RAX@GOTPAGE
Lloh9:
	ldr	x8, [x8, _CV_AMD64_RAX@GOTPAGEOFF]
	b	LBB0_39
LBB0_10:
Lloh10:
	adrp	x8, _CV_AMD64_RDX@GOTPAGE
Lloh11:
	ldr	x8, [x8, _CV_AMD64_RDX@GOTPAGEOFF]
	b	LBB0_39
LBB0_11:
Lloh12:
	adrp	x8, _CV_AMD64_RCX@GOTPAGE
Lloh13:
	ldr	x8, [x8, _CV_AMD64_RCX@GOTPAGEOFF]
	b	LBB0_39
LBB0_12:
Lloh14:
	adrp	x8, _CV_AMD64_RBX@GOTPAGE
Lloh15:
	ldr	x8, [x8, _CV_AMD64_RBX@GOTPAGEOFF]
	b	LBB0_39
LBB0_13:
Lloh16:
	adrp	x8, _CV_AMD64_RSI@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CV_AMD64_RSI@GOTPAGEOFF]
	b	LBB0_39
LBB0_14:
Lloh18:
	adrp	x8, _CV_AMD64_RDI@GOTPAGE
Lloh19:
	ldr	x8, [x8, _CV_AMD64_RDI@GOTPAGEOFF]
	b	LBB0_39
LBB0_15:
Lloh20:
	adrp	x8, _CV_AMD64_RBP@GOTPAGE
Lloh21:
	ldr	x8, [x8, _CV_AMD64_RBP@GOTPAGEOFF]
	b	LBB0_39
LBB0_16:
Lloh22:
	adrp	x8, _CV_AMD64_RSP@GOTPAGE
Lloh23:
	ldr	x8, [x8, _CV_AMD64_RSP@GOTPAGEOFF]
	b	LBB0_39
LBB0_17:
Lloh24:
	adrp	x8, _CV_AMD64_R8@GOTPAGE
Lloh25:
	ldr	x8, [x8, _CV_AMD64_R8@GOTPAGEOFF]
	b	LBB0_39
LBB0_18:
Lloh26:
	adrp	x8, _CV_AMD64_R9@GOTPAGE
Lloh27:
	ldr	x8, [x8, _CV_AMD64_R9@GOTPAGEOFF]
	b	LBB0_39
LBB0_19:
Lloh28:
	adrp	x8, _CV_AMD64_R10@GOTPAGE
Lloh29:
	ldr	x8, [x8, _CV_AMD64_R10@GOTPAGEOFF]
	b	LBB0_39
LBB0_20:
Lloh30:
	adrp	x8, _CV_AMD64_R11@GOTPAGE
Lloh31:
	ldr	x8, [x8, _CV_AMD64_R11@GOTPAGEOFF]
	b	LBB0_39
LBB0_21:
Lloh32:
	adrp	x8, _CV_AMD64_R12@GOTPAGE
Lloh33:
	ldr	x8, [x8, _CV_AMD64_R12@GOTPAGEOFF]
	b	LBB0_39
LBB0_22:
Lloh34:
	adrp	x8, _CV_AMD64_R13@GOTPAGE
Lloh35:
	ldr	x8, [x8, _CV_AMD64_R13@GOTPAGEOFF]
	b	LBB0_39
LBB0_23:
Lloh36:
	adrp	x8, _CV_AMD64_R14@GOTPAGE
Lloh37:
	ldr	x8, [x8, _CV_AMD64_R14@GOTPAGEOFF]
	b	LBB0_39
LBB0_24:
Lloh38:
	adrp	x8, _CV_AMD64_R15@GOTPAGE
Lloh39:
	ldr	x8, [x8, _CV_AMD64_R15@GOTPAGEOFF]
	b	LBB0_39
LBB0_25:
Lloh40:
	adrp	x8, _CV_AMD64_RIP@GOTPAGE
Lloh41:
	ldr	x8, [x8, _CV_AMD64_RIP@GOTPAGEOFF]
	b	LBB0_39
LBB0_26:
Lloh42:
	adrp	x0, l_.str@PAGE
Lloh43:
	add	x0, x0, l_.str@PAGEOFF
	bl	_FIXME
	mov	w0, #0
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
LBB0_27:
Lloh44:
	adrp	x8, _CV_AMD64_EFLAGS@GOTPAGE
Lloh45:
	ldr	x8, [x8, _CV_AMD64_EFLAGS@GOTPAGEOFF]
	b	LBB0_39
LBB0_28:
Lloh46:
	adrp	x8, _CV_AMD64_ES@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CV_AMD64_ES@GOTPAGEOFF]
	b	LBB0_39
LBB0_29:
Lloh48:
	adrp	x8, _CV_AMD64_CS@GOTPAGE
Lloh49:
	ldr	x8, [x8, _CV_AMD64_CS@GOTPAGEOFF]
	b	LBB0_39
LBB0_30:
Lloh50:
	adrp	x8, _CV_AMD64_SS@GOTPAGE
Lloh51:
	ldr	x8, [x8, _CV_AMD64_SS@GOTPAGEOFF]
	b	LBB0_39
LBB0_31:
Lloh52:
	adrp	x8, _CV_AMD64_DS@GOTPAGE
Lloh53:
	ldr	x8, [x8, _CV_AMD64_DS@GOTPAGEOFF]
	b	LBB0_39
LBB0_32:
Lloh54:
	adrp	x8, _CV_AMD64_FS@GOTPAGE
Lloh55:
	ldr	x8, [x8, _CV_AMD64_FS@GOTPAGEOFF]
	b	LBB0_39
LBB0_33:
Lloh56:
	adrp	x8, _CV_AMD64_GS@GOTPAGE
Lloh57:
	ldr	x8, [x8, _CV_AMD64_GS@GOTPAGEOFF]
	b	LBB0_39
LBB0_34:
Lloh58:
	adrp	x8, _CV_AMD64_TR@GOTPAGE
Lloh59:
	ldr	x8, [x8, _CV_AMD64_TR@GOTPAGEOFF]
	b	LBB0_39
LBB0_35:
Lloh60:
	adrp	x8, _CV_AMD64_LDTR@GOTPAGE
Lloh61:
	ldr	x8, [x8, _CV_AMD64_LDTR@GOTPAGEOFF]
	b	LBB0_39
LBB0_36:
Lloh62:
	adrp	x8, _CV_AMD64_MXCSR@GOTPAGE
Lloh63:
	ldr	x8, [x8, _CV_AMD64_MXCSR@GOTPAGEOFF]
	b	LBB0_39
LBB0_37:
Lloh64:
	adrp	x8, _CV_AMD64_CTRL@GOTPAGE
Lloh65:
	ldr	x8, [x8, _CV_AMD64_CTRL@GOTPAGEOFF]
	b	LBB0_39
LBB0_38:
Lloh66:
	adrp	x8, _CV_AMD64_STAT@GOTPAGE
Lloh67:
	ldr	x8, [x8, _CV_AMD64_STAT@GOTPAGEOFF]
LBB0_39:
	ldr	w0, [x8]
	ldp	x29, x30, [sp], #16             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh2, Lloh3
	.loh AdrpLdrGot	Lloh4, Lloh5
	.loh AdrpAdd	Lloh6, Lloh7
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGot	Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh22, Lloh23
	.loh AdrpLdrGot	Lloh24, Lloh25
	.loh AdrpLdrGot	Lloh26, Lloh27
	.loh AdrpLdrGot	Lloh28, Lloh29
	.loh AdrpLdrGot	Lloh30, Lloh31
	.loh AdrpLdrGot	Lloh32, Lloh33
	.loh AdrpLdrGot	Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGot	Lloh40, Lloh41
	.loh AdrpAdd	Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh44, Lloh45
	.loh AdrpLdrGot	Lloh46, Lloh47
	.loh AdrpLdrGot	Lloh48, Lloh49
	.loh AdrpLdrGot	Lloh50, Lloh51
	.loh AdrpLdrGot	Lloh52, Lloh53
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGot	Lloh56, Lloh57
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh60, Lloh61
	.loh AdrpLdrGot	Lloh62, Lloh63
	.loh AdrpLdrGot	Lloh64, Lloh65
	.loh AdrpLdrGot	Lloh66, Lloh67
	.cfi_endproc
	.section	__TEXT,__const
lJTI0_0:
	.byte	(LBB0_9-LBB0_9)>>2
	.byte	(LBB0_10-LBB0_9)>>2
	.byte	(LBB0_11-LBB0_9)>>2
	.byte	(LBB0_12-LBB0_9)>>2
	.byte	(LBB0_13-LBB0_9)>>2
	.byte	(LBB0_14-LBB0_9)>>2
	.byte	(LBB0_15-LBB0_9)>>2
	.byte	(LBB0_16-LBB0_9)>>2
	.byte	(LBB0_17-LBB0_9)>>2
	.byte	(LBB0_18-LBB0_9)>>2
	.byte	(LBB0_19-LBB0_9)>>2
	.byte	(LBB0_20-LBB0_9)>>2
	.byte	(LBB0_21-LBB0_9)>>2
	.byte	(LBB0_22-LBB0_9)>>2
	.byte	(LBB0_23-LBB0_9)>>2
	.byte	(LBB0_24-LBB0_9)>>2
	.byte	(LBB0_25-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_27-LBB0_9)>>2
	.byte	(LBB0_28-LBB0_9)>>2
	.byte	(LBB0_29-LBB0_9)>>2
	.byte	(LBB0_30-LBB0_9)>>2
	.byte	(LBB0_31-LBB0_9)>>2
	.byte	(LBB0_32-LBB0_9)>>2
	.byte	(LBB0_33-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_26-LBB0_9)>>2
	.byte	(LBB0_34-LBB0_9)>>2
	.byte	(LBB0_35-LBB0_9)>>2
	.byte	(LBB0_36-LBB0_9)>>2
	.byte	(LBB0_37-LBB0_9)>>2
	.byte	(LBB0_38-LBB0_9)>>2
                                        ; -- End function
	.comm	_CV_AMD64_XMM0,4,2              ; @CV_AMD64_XMM0
	.comm	_CV_AMD64_XMM8,4,2              ; @CV_AMD64_XMM8
	.comm	_CV_AMD64_ST0,4,2               ; @CV_AMD64_ST0
	.comm	_CV_AMD64_RAX,4,2               ; @CV_AMD64_RAX
	.comm	_CV_AMD64_RDX,4,2               ; @CV_AMD64_RDX
	.comm	_CV_AMD64_RCX,4,2               ; @CV_AMD64_RCX
	.comm	_CV_AMD64_RBX,4,2               ; @CV_AMD64_RBX
	.comm	_CV_AMD64_RSI,4,2               ; @CV_AMD64_RSI
	.comm	_CV_AMD64_RDI,4,2               ; @CV_AMD64_RDI
	.comm	_CV_AMD64_RBP,4,2               ; @CV_AMD64_RBP
	.comm	_CV_AMD64_RSP,4,2               ; @CV_AMD64_RSP
	.comm	_CV_AMD64_R8,4,2                ; @CV_AMD64_R8
	.comm	_CV_AMD64_R9,4,2                ; @CV_AMD64_R9
	.comm	_CV_AMD64_R10,4,2               ; @CV_AMD64_R10
	.comm	_CV_AMD64_R11,4,2               ; @CV_AMD64_R11
	.comm	_CV_AMD64_R12,4,2               ; @CV_AMD64_R12
	.comm	_CV_AMD64_R13,4,2               ; @CV_AMD64_R13
	.comm	_CV_AMD64_R14,4,2               ; @CV_AMD64_R14
	.comm	_CV_AMD64_R15,4,2               ; @CV_AMD64_R15
	.comm	_CV_AMD64_RIP,4,2               ; @CV_AMD64_RIP
	.comm	_CV_AMD64_EFLAGS,4,2            ; @CV_AMD64_EFLAGS
	.comm	_CV_AMD64_ES,4,2                ; @CV_AMD64_ES
	.comm	_CV_AMD64_CS,4,2                ; @CV_AMD64_CS
	.comm	_CV_AMD64_SS,4,2                ; @CV_AMD64_SS
	.comm	_CV_AMD64_DS,4,2                ; @CV_AMD64_DS
	.comm	_CV_AMD64_FS,4,2                ; @CV_AMD64_FS
	.comm	_CV_AMD64_GS,4,2                ; @CV_AMD64_GS
	.comm	_CV_AMD64_TR,4,2                ; @CV_AMD64_TR
	.comm	_CV_AMD64_LDTR,4,2              ; @CV_AMD64_LDTR
	.comm	_CV_AMD64_MXCSR,4,2             ; @CV_AMD64_MXCSR
	.comm	_CV_AMD64_CTRL,4,2              ; @CV_AMD64_CTRL
	.comm	_CV_AMD64_STAT,4,2              ; @CV_AMD64_STAT
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"Don't know how to map register %d\n"

	.no_dead_strip	_x86_64_map_dwarf_register
.subsections_via_symbols
