	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_CLK_enable_timebase            ## -- Begin function CLK_enable_timebase
	.p2align	4, 0x90
_CLK_enable_timebase:                   ## @CLK_enable_timebase
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	_GCLK@GOTPCREL(%rip), %rax
	movq	(%rax), %r15
	movq	_MCLK@GOTPCREL(%rip), %rax
	movq	(%rax), %r13
	movq	_TC4@GOTPCREL(%rip), %rax
	movq	(%rax), %r14
	movq	_TC0@GOTPCREL(%rip), %rax
	movq	(%rax), %rbx
	movq	_EVSYS@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, -48(%rbp)                 ## 8-byte Spill
	movq	_DC_CLK_ENABLE_TIMEBASE_BEGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	movq	_GEN_TC45@GOTPCREL(%rip), %r12
	movq	(%r12), %rdi
	movq	_FREQ_TC45_DEFAULT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_CLK_set_gclk_freq
	xorl	%eax, %eax
	callq	_CLK_init_osc
	movl	$1, 12(%r13)
	movq	(%r12), %rax
	movq	(%r15), %rcx
	movq	_TC4_GCLK_ID@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	movq	$0, 112(%r14)
	cmpq	$0, 80(%r14)
	je	LBB0_3
## %bb.1:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	callq	_DBGC
	cmpq	$0, 80(%r14)
	jne	LBB0_2
LBB0_3:
	movl	$1, 104(%r14)
	cmpq	$0, 72(%r14)
	je	LBB0_6
## %bb.4:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_5:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	callq	_DBGC
	cmpq	$0, 72(%r14)
	jne	LBB0_5
	jmp	LBB0_7
LBB0_6:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
LBB0_7:
	cmpl	$0, 104(%r14)
	jne	LBB0_6
## %bb.8:
	movl	$5, 96(%r14)
	cmpq	$0, 64(%r14)
	je	LBB0_11
## %bb.9:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_10:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	callq	_DBGC
	cmpq	$0, 64(%r14)
	jne	LBB0_10
LBB0_11:
	movq	88(%r14), %rax
	movl	$999, (%rax)                    ## imm = 0x3E7
	cmpq	$0, 56(%r14)
	je	LBB0_14
## %bb.12:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0@GOTPCREL(%rip), %r12
	.p2align	4, 0x90
LBB0_13:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r12), %edi
	callq	_DBGC
	cmpq	$0, 56(%r14)
	jne	LBB0_13
LBB0_14:
	movabsq	$4294967297, %rax               ## imm = 0x100000001
	movq	%rax, 44(%r14)
	movq	_TC4_IRQn@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_NVIC_EnableIRQ
	movl	$1, 40(%r14)
	movq	_DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	movl	$1, 4(%r13)
	movq	_GEN_TC45@GOTPCREL(%rip), %r12
	movq	(%r12), %rax
	movq	(%r15), %rcx
	movq	_TC0_GCLK_ID@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movl	$1, 8(%r13)
	movq	(%r12), %rax
	movq	_TC1_GCLK_ID@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movq	_DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	movq	$0, 16(%rbx)
	cmpq	$0, 32(%rbx)
	je	LBB0_17
## %bb.15:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_16:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_DBGC
	cmpq	$0, 32(%rbx)
	jne	LBB0_16
LBB0_17:
	movl	$1, 8(%rbx)
	cmpq	$0, 24(%rbx)
	je	LBB0_20
## %bb.18:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_19:                                ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	callq	_DBGC
	cmpq	$0, 24(%rbx)
	jne	LBB0_19
	jmp	LBB0_21
LBB0_20:
	movq	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
LBB0_21:
	cmpl	$0, 8(%rbx)
	jne	LBB0_20
## %bb.22:
	movl	$2, 12(%rbx)
	movabsq	$8589934593, %rax               ## imm = 0x200000001
	movq	%rax, (%rbx)
	movq	_DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	movq	_DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	movl	$1, (%r13)
	movq	(%r12), %rax
	movq	(%r15), %rcx
	movq	_EVSYS_GCLK_ID_0@GOTPCREL(%rip), %rdx
	movq	(%rdx), %rdx
	shlq	$4, %rdx
	movq	%rax, 8(%rcx,%rdx)
	movl	$1, (%rcx,%rdx)
	movq	_EVSYS_ID_USER_PORT_EV_0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-48(%rbp), %rdx                 ## 8-byte Reload
	movq	8(%rdx), %rcx
	movl	%eax, 176(%rcx)
	movq	_EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	(%rdx), %rcx
	movl	%eax, 8(%rcx)
	movq	_EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 4(%rcx)
	movq	_EVSYS_ID_GEN_TC4_MCX_0@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%rcx)
	movq	_DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	xorl	%eax, %eax
	callq	_CLK_reset_time
	xorl	%eax, %eax
	callq	_ADC0_clock_init
	movq	_DC_CLK_ENABLE_TIMEBASE_COMPLETE@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_DBGC
	xorl	%eax, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_GCLK,8,3                       ## @GCLK
	.comm	_MCLK,8,3                       ## @MCLK
	.comm	_TC4,8,3                        ## @TC4
	.comm	_TC0,8,3                        ## @TC0
	.comm	_EVSYS,8,3                      ## @EVSYS
	.comm	_DC_CLK_ENABLE_TIMEBASE_BEGIN,4,2 ## @DC_CLK_ENABLE_TIMEBASE_BEGIN
	.comm	_GEN_TC45,8,3                   ## @GEN_TC45
	.comm	_FREQ_TC45_DEFAULT,4,2          ## @FREQ_TC45_DEFAULT
	.comm	_TC4_GCLK_ID,8,3                ## @TC4_GCLK_ID
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0
	.comm	_TC4_IRQn,4,2                   ## @TC4_IRQn
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE
	.comm	_TC0_GCLK_ID,8,3                ## @TC0_GCLK_ID
	.comm	_TC1_GCLK_ID,8,3                ## @TC1_GCLK_ID
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE,4,2 ## @DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE
	.comm	_DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN,4,2 ## @DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN
	.comm	_EVSYS_GCLK_ID_0,8,3            ## @EVSYS_GCLK_ID_0
	.comm	_EVSYS_ID_USER_PORT_EV_0,4,2    ## @EVSYS_ID_USER_PORT_EV_0
	.comm	_EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val,4,2 ## @EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
	.comm	_EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val,4,2 ## @EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
	.comm	_EVSYS_ID_GEN_TC4_MCX_0,4,2     ## @EVSYS_ID_GEN_TC4_MCX_0
	.comm	_DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE,4,2 ## @DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE
	.comm	_DC_CLK_ENABLE_TIMEBASE_COMPLETE,4,2 ## @DC_CLK_ENABLE_TIMEBASE_COMPLETE
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.section	__TEXT,__literal8,8byte_literals
	.p2align	3                               ; -- Begin function CLK_enable_timebase
lCPI0_0:
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.section	__TEXT,__text,regular,pure_instructions
	.globl	_CLK_enable_timebase
	.p2align	2
_CLK_enable_timebase:                   ; @CLK_enable_timebase
	.cfi_startproc
; %bb.0:
	stp	d9, d8, [sp, #-96]!             ; 16-byte Folded Spill
	.cfi_def_cfa_offset 96
	stp	x26, x25, [sp, #16]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #32]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #48]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #64]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #80]             ; 16-byte Folded Spill
	add	x29, sp, #80
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset b8, -88
	.cfi_offset b9, -96
Lloh0:
	adrp	x8, _GCLK@GOTPAGE
Lloh1:
	ldr	x8, [x8, _GCLK@GOTPAGEOFF]
Lloh2:
	ldr	x20, [x8]
Lloh3:
	adrp	x8, _MCLK@GOTPAGE
Lloh4:
	ldr	x8, [x8, _MCLK@GOTPAGEOFF]
Lloh5:
	ldr	x21, [x8]
Lloh6:
	adrp	x8, _TC4@GOTPAGE
Lloh7:
	ldr	x8, [x8, _TC4@GOTPAGEOFF]
Lloh8:
	ldr	x24, [x8]
Lloh9:
	adrp	x8, _TC0@GOTPAGE
Lloh10:
	ldr	x8, [x8, _TC0@GOTPAGEOFF]
Lloh11:
	ldr	x23, [x8]
Lloh12:
	adrp	x8, _EVSYS@GOTPAGE
Lloh13:
	ldr	x8, [x8, _EVSYS@GOTPAGEOFF]
Lloh14:
	ldr	x19, [x8]
Lloh15:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_BEGIN@GOTPAGE
Lloh16:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_BEGIN@GOTPAGEOFF]
Lloh17:
	ldr	w0, [x8]
	bl	_DBGC
Lloh18:
	adrp	x22, _GEN_TC45@GOTPAGE
Lloh19:
	ldr	x22, [x22, _GEN_TC45@GOTPAGEOFF]
	ldr	x0, [x22]
Lloh20:
	adrp	x8, _FREQ_TC45_DEFAULT@GOTPAGE
Lloh21:
	ldr	x8, [x8, _FREQ_TC45_DEFAULT@GOTPAGEOFF]
Lloh22:
	ldr	w1, [x8]
	bl	_CLK_set_gclk_freq
	bl	_CLK_init_osc
	mov	w25, #1
	str	w25, [x21, #12]
	ldr	x8, [x22]
	ldr	x9, [x20]
Lloh23:
	adrp	x10, _TC4_GCLK_ID@GOTPAGE
Lloh24:
	ldr	x10, [x10, _TC4_GCLK_ID@GOTPAGEOFF]
Lloh25:
	ldr	x10, [x10]
	add	x9, x9, x10, lsl #4
	str	x8, [x9, #8]
	str	w25, [x9]
Lloh26:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN@GOTPAGE
Lloh27:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN@GOTPAGEOFF]
Lloh28:
	ldr	w0, [x8]
	bl	_DBGC
	str	xzr, [x24, #112]
	ldr	x8, [x24, #80]
	cbz	x8, LBB0_3
; %bb.1:
Lloh29:
	adrp	x26, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE@GOTPAGE
Lloh30:
	ldr	x26, [x26, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x26]
	bl	_DBGC
	ldr	x8, [x24, #80]
	cbnz	x8, LBB0_2
LBB0_3:
	str	w25, [x24, #104]
	ldr	x8, [x24, #72]
	cbz	x8, LBB0_6
; %bb.4:
Lloh31:
	adrp	x25, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1@GOTPAGE
Lloh32:
	ldr	x25, [x25, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1@GOTPAGEOFF]
LBB0_5:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x25]
	bl	_DBGC
	ldr	x8, [x24, #72]
	cbnz	x8, LBB0_5
	b	LBB0_7
LBB0_6:
Lloh33:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2@GOTPAGE
Lloh34:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2@GOTPAGEOFF]
Lloh35:
	ldr	w0, [x8]
	bl	_DBGC
LBB0_7:
	ldr	w8, [x24, #104]
	cbnz	w8, LBB0_6
; %bb.8:
	mov	w8, #5
	str	w8, [x24, #96]
	ldr	x8, [x24, #64]
	cbz	x8, LBB0_11
; %bb.9:
Lloh36:
	adrp	x25, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB@GOTPAGE
Lloh37:
	ldr	x25, [x25, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB@GOTPAGEOFF]
LBB0_10:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x25]
	bl	_DBGC
	ldr	x8, [x24, #64]
	cbnz	x8, LBB0_10
LBB0_11:
	ldr	x8, [x24, #88]
	mov	w9, #999
	str	w9, [x8]
	ldr	x8, [x24, #56]
	cbz	x8, LBB0_14
; %bb.12:
Lloh38:
	adrp	x25, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0@GOTPAGE
Lloh39:
	ldr	x25, [x25, _DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0@GOTPAGEOFF]
LBB0_13:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x25]
	bl	_DBGC
	ldr	x8, [x24, #56]
	cbnz	x8, LBB0_13
LBB0_14:
	movi.2s	v8, #1
	stur	d8, [x24, #44]
Lloh40:
	adrp	x8, _TC4_IRQn@GOTPAGE
Lloh41:
	ldr	x8, [x8, _TC4_IRQn@GOTPAGEOFF]
Lloh42:
	ldr	w0, [x8]
	bl	_NVIC_EnableIRQ
	mov	w25, #1
	str	w25, [x24, #40]
Lloh43:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE@GOTPAGE
Lloh44:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE@GOTPAGEOFF]
Lloh45:
	ldr	w0, [x8]
	bl	_DBGC
	ldr	x8, [x22]
	ldr	x9, [x20]
Lloh46:
	adrp	x10, _TC0_GCLK_ID@GOTPAGE
Lloh47:
	ldr	x10, [x10, _TC0_GCLK_ID@GOTPAGEOFF]
Lloh48:
	ldr	x10, [x10]
	add	x10, x9, x10, lsl #4
	str	x8, [x10, #8]
	str	w25, [x10]
	stur	d8, [x21, #4]
	ldr	x8, [x22]
Lloh49:
	adrp	x10, _TC1_GCLK_ID@GOTPAGE
Lloh50:
	ldr	x10, [x10, _TC1_GCLK_ID@GOTPAGEOFF]
Lloh51:
	ldr	x10, [x10]
	add	x9, x9, x10, lsl #4
	str	x8, [x9, #8]
	str	w25, [x9]
Lloh52:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN@GOTPAGE
Lloh53:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN@GOTPAGEOFF]
Lloh54:
	ldr	w0, [x8]
	bl	_DBGC
	str	xzr, [x23, #16]
	ldr	x8, [x23, #32]
	cbz	x8, LBB0_17
; %bb.15:
Lloh55:
	adrp	x24, _DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE@GOTPAGE
Lloh56:
	ldr	x24, [x24, _DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE@GOTPAGEOFF]
LBB0_16:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_DBGC
	ldr	x8, [x23, #32]
	cbnz	x8, LBB0_16
LBB0_17:
	str	w25, [x23, #8]
	ldr	x8, [x23, #24]
	cbz	x8, LBB0_20
; %bb.18:
Lloh57:
	adrp	x24, _DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1@GOTPAGE
Lloh58:
	ldr	x24, [x24, _DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1@GOTPAGEOFF]
LBB0_19:                                ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x24]
	bl	_DBGC
	ldr	x8, [x23, #24]
	cbnz	x8, LBB0_19
	b	LBB0_21
LBB0_20:
Lloh59:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2@GOTPAGE
Lloh60:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2@GOTPAGEOFF]
Lloh61:
	ldr	w0, [x8]
	bl	_DBGC
LBB0_21:
	ldr	w8, [x23, #8]
	cbnz	w8, LBB0_20
; %bb.22:
	mov	w8, #2
	str	w8, [x23, #12]
Lloh62:
	adrp	x8, lCPI0_0@PAGE
Lloh63:
	ldr	d0, [x8, lCPI0_0@PAGEOFF]
	str	d0, [x23]
Lloh64:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE@GOTPAGE
Lloh65:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE@GOTPAGEOFF]
Lloh66:
	ldr	w0, [x8]
	bl	_DBGC
Lloh67:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN@GOTPAGE
Lloh68:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN@GOTPAGEOFF]
Lloh69:
	ldr	w0, [x8]
	bl	_DBGC
	mov	w8, #1
	str	w8, [x21]
	ldr	x9, [x22]
	ldr	x10, [x20]
Lloh70:
	adrp	x11, _EVSYS_GCLK_ID_0@GOTPAGE
Lloh71:
	ldr	x11, [x11, _EVSYS_GCLK_ID_0@GOTPAGEOFF]
Lloh72:
	ldr	x11, [x11]
	add	x10, x10, x11, lsl #4
	str	x9, [x10, #8]
	str	w8, [x10]
Lloh73:
	adrp	x8, _EVSYS_ID_USER_PORT_EV_0@GOTPAGE
Lloh74:
	ldr	x8, [x8, _EVSYS_ID_USER_PORT_EV_0@GOTPAGEOFF]
Lloh75:
	ldr	w8, [x8]
	ldp	x10, x9, [x19]
	str	w8, [x9, #176]
Lloh76:
	adrp	x8, _EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val@GOTPAGE
Lloh77:
	ldr	x8, [x8, _EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val@GOTPAGEOFF]
Lloh78:
	ldr	w8, [x8]
	str	w8, [x10, #8]
Lloh79:
	adrp	x8, _EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val@GOTPAGE
Lloh80:
	ldr	x8, [x8, _EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val@GOTPAGEOFF]
Lloh81:
	ldr	w8, [x8]
Lloh82:
	adrp	x9, _EVSYS_ID_GEN_TC4_MCX_0@GOTPAGE
Lloh83:
	ldr	x9, [x9, _EVSYS_ID_GEN_TC4_MCX_0@GOTPAGEOFF]
Lloh84:
	ldr	w9, [x9]
	stp	w9, w8, [x10]
Lloh85:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE@GOTPAGE
Lloh86:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE@GOTPAGEOFF]
Lloh87:
	ldr	w0, [x8]
	bl	_DBGC
	bl	_CLK_reset_time
	bl	_ADC0_clock_init
Lloh88:
	adrp	x8, _DC_CLK_ENABLE_TIMEBASE_COMPLETE@GOTPAGE
Lloh89:
	ldr	x8, [x8, _DC_CLK_ENABLE_TIMEBASE_COMPLETE@GOTPAGEOFF]
Lloh90:
	ldr	w0, [x8]
	bl	_DBGC
	mov	w0, #0
	ldp	x29, x30, [sp, #80]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #64]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #48]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #32]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #16]             ; 16-byte Folded Reload
	ldp	d9, d8, [sp], #96               ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh26, Lloh27, Lloh28
	.loh AdrpLdrGotLdr	Lloh23, Lloh24, Lloh25
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh22
	.loh AdrpLdrGot	Lloh18, Lloh19
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh29, Lloh30
	.loh AdrpLdrGot	Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGot	Lloh36, Lloh37
	.loh AdrpLdrGot	Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGot	Lloh55, Lloh56
	.loh AdrpLdrGot	Lloh57, Lloh58
	.loh AdrpLdrGotLdr	Lloh59, Lloh60, Lloh61
	.loh AdrpLdrGotLdr	Lloh88, Lloh89, Lloh90
	.loh AdrpLdrGotLdr	Lloh85, Lloh86, Lloh87
	.loh AdrpLdrGotLdr	Lloh82, Lloh83, Lloh84
	.loh AdrpLdrGotLdr	Lloh79, Lloh80, Lloh81
	.loh AdrpLdrGotLdr	Lloh76, Lloh77, Lloh78
	.loh AdrpLdrGotLdr	Lloh73, Lloh74, Lloh75
	.loh AdrpLdrGotLdr	Lloh70, Lloh71, Lloh72
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.loh AdrpAdrp	Lloh62, Lloh64
	.loh AdrpLdr	Lloh62, Lloh63
	.cfi_endproc
                                        ; -- End function
	.comm	_GCLK,8,3                       ; @GCLK
	.comm	_MCLK,8,3                       ; @MCLK
	.comm	_TC4,8,3                        ; @TC4
	.comm	_TC0,8,3                        ; @TC0
	.comm	_EVSYS,8,3                      ; @EVSYS
	.comm	_DC_CLK_ENABLE_TIMEBASE_BEGIN,4,2 ; @DC_CLK_ENABLE_TIMEBASE_BEGIN
	.comm	_GEN_TC45,8,3                   ; @GEN_TC45
	.comm	_FREQ_TC45_DEFAULT,4,2          ; @FREQ_TC45_DEFAULT
	.comm	_TC4_GCLK_ID,8,3                ; @TC4_GCLK_ID
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_BEGIN
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_DISABLE
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_1
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_SWRST_2
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CLTRB
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_SYNC_CC0
	.comm	_TC4_IRQn,4,2                   ; @TC4_IRQn
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC4_COMPLETE
	.comm	_TC0_GCLK_ID,8,3                ; @TC0_GCLK_ID
	.comm	_TC1_GCLK_ID,8,3                ; @TC1_GCLK_ID
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC0_BEGIN
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_DISABLE
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_1
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC0_SYNC_SWRST_2
	.comm	_DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE,4,2 ; @DC_CLK_ENABLE_TIMEBASE_TC0_COMPLETE
	.comm	_DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN,4,2 ; @DC_CLK_ENABLE_TIMEBASE_EVSYS_BEGIN
	.comm	_EVSYS_GCLK_ID_0,8,3            ; @EVSYS_GCLK_ID_0
	.comm	_EVSYS_ID_USER_PORT_EV_0,4,2    ; @EVSYS_ID_USER_PORT_EV_0
	.comm	_EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val,4,2 ; @EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val
	.comm	_EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val,4,2 ; @EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val
	.comm	_EVSYS_ID_GEN_TC4_MCX_0,4,2     ; @EVSYS_ID_GEN_TC4_MCX_0
	.comm	_DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE,4,2 ; @DC_CLK_ENABLE_TIMEBASE_EVSYS_COMPLETE
	.comm	_DC_CLK_ENABLE_TIMEBASE_COMPLETE,4,2 ; @DC_CLK_ENABLE_TIMEBASE_COMPLETE
.subsections_via_symbols
