	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mt7530_core_pll_setup
_mt7530_core_pll_setup:                 ## @mt7530_core_pll_setup
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_HWSTRAP@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	callq	_mt753x_reg_read
	movq	_XTAL_FSEL_M@GOTPCREL(%rip), %rcx
	andl	(%rcx), %eax
	movq	_XTAL_FSEL_S@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	cmpl	$128, %eax
	jne	LBB0_2
## %bb.1:
	movq	_TRGMII_GSW_CLK_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	xorl	%edx, %edx
	callq	_mt7530_core_reg_write
	movq	_CORE_GSWPLL_GCR_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GSWPLL_POSTDIV_200M_S@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$2, %r13d
	movl	$2, %eax
	shll	%cl, %eax
	movq	_GSWPLL_FBKDIV_200M_S@GOTPCREL(%rip), %r12
	movb	(%r12), %cl
	movl	$32, %r14d
	movl	$32, %edx
	shll	%cl, %edx
	orl	%eax, %edx
	movq	%rbx, %rdi
	callq	_mt7530_core_reg_write
	movq	_CORE_GSWPLL_GCR_2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GSWPLL_POSTDIV_500M_S@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	movq	_GSWPLL_FBKDIV_500M_S@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$25, %edx
	shll	%cl, %edx
	btsl	%eax, %edx
	movq	%rbx, %rdi
	callq	_mt7530_core_reg_write
	movq	_CORE_GSWPLL_GCR_1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GSWPLL_POSTDIV_200M_S@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	shll	%cl, %r13d
	movb	(%r12), %cl
	shll	%cl, %r14d
	orl	%r13d, %r14d
	movq	_GSWPLL_EN_PRE@GOTPCREL(%rip), %rax
	orl	(%rax), %r14d
	movq	%rbx, %rdi
	movl	%r14d, %edx
	callq	_mt7530_core_reg_write
	movl	$20, %edi
	movl	$40, %esi
	callq	_usleep_range
	movq	_TRGMII_GSW_CLK_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GSWCK_EN@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mt7530_core_reg_write
LBB0_2:
	movl	(%r15), %esi
	movq	%rbx, %rdi
	callq	_mt753x_reg_read
	movq	_CHG_TRAP@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movq	_C_MDIO_BPS_S@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movl	%edx, %ecx
	notl	%ecx
	andl	%eax, %ecx
	orl	%eax, %edx
	cmpq	$0, 16(%rbx)
	cmovnel	%ecx, %edx
	movq	_MHWSTRAP@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%rbx, %rdi
	callq	_mt753x_reg_write
	cmpq	$0, 8(%rbx)
	je	LBB0_5
## %bb.3:
	movq	(%rbx), %rax
	movq	_PHY_INTERFACE_MODE_TRGMII@GOTPCREL(%rip), %rcx
	cmpq	(%rcx), %rax
	jne	LBB0_5
## %bb.4:
	movq	%rbx, %rdi
	callq	_mt7530_trgmii_setting
	jmp	LBB0_6
LBB0_5:
	movq	%rbx, %rdi
	callq	_mt7530_rgmii_setting
LBB0_6:
	movq	_P5RGMIIRXCR@GOTPCREL(%rip), %rax
	movq	_CSR_RGMII_RXC_0DEG_CFG_S@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	movl	$2, %edx
	shll	%cl, %edx
	movl	(%rax), %esi
	movq	_CSR_RGMII_EDGE_ALIGN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%rbx, %rdi
	callq	_mt753x_reg_write
	movq	_P5RGMIITXCR@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_CSR_RGMII_TXC_CFG_S@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$20, %edx
	shll	%cl, %edx
	movq	%rbx, %rdi
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	jmp	_mt753x_reg_write               ## TAILCALL
	.cfi_endproc
                                        ## -- End function
	.comm	_HWSTRAP,4,2                    ## @HWSTRAP
	.comm	_XTAL_FSEL_M,4,2                ## @XTAL_FSEL_M
	.comm	_XTAL_FSEL_S,4,2                ## @XTAL_FSEL_S
	.comm	_TRGMII_GSW_CLK_CG,4,2          ## @TRGMII_GSW_CLK_CG
	.comm	_CORE_GSWPLL_GCR_1,4,2          ## @CORE_GSWPLL_GCR_1
	.comm	_GSWPLL_POSTDIV_200M_S,4,2      ## @GSWPLL_POSTDIV_200M_S
	.comm	_GSWPLL_FBKDIV_200M_S,4,2       ## @GSWPLL_FBKDIV_200M_S
	.comm	_CORE_GSWPLL_GCR_2,4,2          ## @CORE_GSWPLL_GCR_2
	.comm	_GSWPLL_POSTDIV_500M_S,4,2      ## @GSWPLL_POSTDIV_500M_S
	.comm	_GSWPLL_FBKDIV_500M_S,4,2       ## @GSWPLL_FBKDIV_500M_S
	.comm	_GSWPLL_EN_PRE,4,2              ## @GSWPLL_EN_PRE
	.comm	_GSWCK_EN,4,2                   ## @GSWCK_EN
	.comm	_CHG_TRAP,4,2                   ## @CHG_TRAP
	.comm	_C_MDIO_BPS_S,4,2               ## @C_MDIO_BPS_S
	.comm	_MHWSTRAP,4,2                   ## @MHWSTRAP
	.comm	_PHY_INTERFACE_MODE_TRGMII,8,3  ## @PHY_INTERFACE_MODE_TRGMII
	.comm	_P5RGMIIRXCR,4,2                ## @P5RGMIIRXCR
	.comm	_CSR_RGMII_EDGE_ALIGN,4,2       ## @CSR_RGMII_EDGE_ALIGN
	.comm	_CSR_RGMII_RXC_0DEG_CFG_S,4,2   ## @CSR_RGMII_RXC_0DEG_CFG_S
	.comm	_P5RGMIITXCR,4,2                ## @P5RGMIITXCR
	.comm	_CSR_RGMII_TXC_CFG_S,4,2        ## @CSR_RGMII_TXC_CFG_S
	.no_dead_strip	_mt7530_core_pll_setup
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mt7530_core_pll_setup
_mt7530_core_pll_setup:                 ; @mt7530_core_pll_setup
	.cfi_startproc
; %bb.0:
	stp	x26, x25, [sp, #-80]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 80
	stp	x24, x23, [sp, #16]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #32]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #48]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #64]             ; 16-byte Folded Spill
	add	x29, sp, #64
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	mov	x19, x0
Lloh0:
	adrp	x20, _HWSTRAP@GOTPAGE
Lloh1:
	ldr	x20, [x20, _HWSTRAP@GOTPAGEOFF]
	ldr	w1, [x20]
	bl	_mt753x_reg_read
Lloh2:
	adrp	x8, _XTAL_FSEL_M@GOTPAGE
Lloh3:
	ldr	x8, [x8, _XTAL_FSEL_M@GOTPAGEOFF]
Lloh4:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh5:
	adrp	x9, _XTAL_FSEL_S@GOTPAGE
Lloh6:
	ldr	x9, [x9, _XTAL_FSEL_S@GOTPAGEOFF]
Lloh7:
	ldr	w9, [x9]
	asr	w8, w8, w9
	cmp	w8, #128
	b.ne	LBB0_2
; %bb.1:
Lloh8:
	adrp	x21, _TRGMII_GSW_CLK_CG@GOTPAGE
Lloh9:
	ldr	x21, [x21, _TRGMII_GSW_CLK_CG@GOTPAGEOFF]
	ldr	w1, [x21]
	mov	x0, x19
	mov	w2, #0
	bl	_mt7530_core_reg_write
Lloh10:
	adrp	x22, _CORE_GSWPLL_GCR_1@GOTPAGE
Lloh11:
	ldr	x22, [x22, _CORE_GSWPLL_GCR_1@GOTPAGEOFF]
	ldr	w1, [x22]
Lloh12:
	adrp	x23, _GSWPLL_POSTDIV_200M_S@GOTPAGE
Lloh13:
	ldr	x23, [x23, _GSWPLL_POSTDIV_200M_S@GOTPAGEOFF]
	ldr	w8, [x23]
	mov	w24, #2
	lsl	w8, w24, w8
Lloh14:
	adrp	x25, _GSWPLL_FBKDIV_200M_S@GOTPAGE
Lloh15:
	ldr	x25, [x25, _GSWPLL_FBKDIV_200M_S@GOTPAGEOFF]
	ldr	w9, [x25]
	mov	w26, #32
	lsl	w9, w26, w9
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mt7530_core_reg_write
Lloh16:
	adrp	x8, _CORE_GSWPLL_GCR_2@GOTPAGE
Lloh17:
	ldr	x8, [x8, _CORE_GSWPLL_GCR_2@GOTPAGEOFF]
Lloh18:
	ldr	w1, [x8]
Lloh19:
	adrp	x8, _GSWPLL_POSTDIV_500M_S@GOTPAGE
Lloh20:
	ldr	x8, [x8, _GSWPLL_POSTDIV_500M_S@GOTPAGEOFF]
Lloh21:
	ldr	w8, [x8]
	mov	w9, #1
	lsl	w8, w9, w8
Lloh22:
	adrp	x9, _GSWPLL_FBKDIV_500M_S@GOTPAGE
Lloh23:
	ldr	x9, [x9, _GSWPLL_FBKDIV_500M_S@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	mov	w10, #25
	lsl	w9, w10, w9
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mt7530_core_reg_write
	ldr	w1, [x22]
	ldr	w8, [x23]
	lsl	w8, w24, w8
	ldr	w9, [x25]
	lsl	w9, w26, w9
	orr	w8, w9, w8
Lloh25:
	adrp	x9, _GSWPLL_EN_PRE@GOTPAGE
Lloh26:
	ldr	x9, [x9, _GSWPLL_EN_PRE@GOTPAGEOFF]
Lloh27:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_mt7530_core_reg_write
	mov	w0, #20
	mov	w1, #40
	bl	_usleep_range
	ldr	w1, [x21]
Lloh28:
	adrp	x8, _GSWCK_EN@GOTPAGE
Lloh29:
	ldr	x8, [x8, _GSWCK_EN@GOTPAGEOFF]
Lloh30:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_mt7530_core_reg_write
LBB0_2:
	ldr	w1, [x20]
	mov	x0, x19
	bl	_mt753x_reg_read
Lloh31:
	adrp	x8, _CHG_TRAP@GOTPAGE
Lloh32:
	ldr	x8, [x8, _CHG_TRAP@GOTPAGEOFF]
Lloh33:
	ldr	w8, [x8]
	orr	w8, w8, w0
	ldr	x9, [x19, #16]
Lloh34:
	adrp	x10, _C_MDIO_BPS_S@GOTPAGE
Lloh35:
	ldr	x10, [x10, _C_MDIO_BPS_S@GOTPAGEOFF]
Lloh36:
	ldr	w10, [x10]
	bic	w11, w8, w10
	orr	w8, w10, w8
	cmp	x9, #0
	csel	w2, w8, w11, eq
Lloh37:
	adrp	x8, _MHWSTRAP@GOTPAGE
Lloh38:
	ldr	x8, [x8, _MHWSTRAP@GOTPAGEOFF]
Lloh39:
	ldr	w1, [x8]
	mov	x0, x19
	bl	_mt753x_reg_write
	ldr	x8, [x19, #8]
	cbz	x8, LBB0_5
; %bb.3:
	ldr	x8, [x19]
Lloh40:
	adrp	x9, _PHY_INTERFACE_MODE_TRGMII@GOTPAGE
Lloh41:
	ldr	x9, [x9, _PHY_INTERFACE_MODE_TRGMII@GOTPAGEOFF]
Lloh42:
	ldr	x9, [x9]
	cmp	x8, x9
	b.ne	LBB0_5
; %bb.4:
	mov	x0, x19
	bl	_mt7530_trgmii_setting
	b	LBB0_6
LBB0_5:
	mov	x0, x19
	bl	_mt7530_rgmii_setting
LBB0_6:
Lloh43:
	adrp	x8, _P5RGMIIRXCR@GOTPAGE
Lloh44:
	ldr	x8, [x8, _P5RGMIIRXCR@GOTPAGEOFF]
Lloh45:
	ldr	w1, [x8]
Lloh46:
	adrp	x8, _CSR_RGMII_EDGE_ALIGN@GOTPAGE
Lloh47:
	ldr	x8, [x8, _CSR_RGMII_EDGE_ALIGN@GOTPAGEOFF]
Lloh48:
	ldr	w8, [x8]
Lloh49:
	adrp	x9, _CSR_RGMII_RXC_0DEG_CFG_S@GOTPAGE
Lloh50:
	ldr	x9, [x9, _CSR_RGMII_RXC_0DEG_CFG_S@GOTPAGEOFF]
Lloh51:
	ldr	w9, [x9]
	mov	w10, #2
	lsl	w9, w10, w9
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mt753x_reg_write
Lloh52:
	adrp	x8, _P5RGMIITXCR@GOTPAGE
Lloh53:
	ldr	x8, [x8, _P5RGMIITXCR@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
Lloh55:
	adrp	x8, _CSR_RGMII_TXC_CFG_S@GOTPAGE
Lloh56:
	ldr	x8, [x8, _CSR_RGMII_TXC_CFG_S@GOTPAGEOFF]
Lloh57:
	ldr	w8, [x8]
	mov	w9, #20
	lsl	w2, w9, w8
	mov	x0, x19
	ldp	x29, x30, [sp, #64]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #48]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #32]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #16]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp], #80             ; 16-byte Folded Reload
	b	_mt753x_reg_write
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGotLdr	Lloh28, Lloh29, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh27
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGotLdr	Lloh16, Lloh17, Lloh18
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.cfi_endproc
                                        ; -- End function
	.comm	_HWSTRAP,4,2                    ; @HWSTRAP
	.comm	_XTAL_FSEL_M,4,2                ; @XTAL_FSEL_M
	.comm	_XTAL_FSEL_S,4,2                ; @XTAL_FSEL_S
	.comm	_TRGMII_GSW_CLK_CG,4,2          ; @TRGMII_GSW_CLK_CG
	.comm	_CORE_GSWPLL_GCR_1,4,2          ; @CORE_GSWPLL_GCR_1
	.comm	_GSWPLL_POSTDIV_200M_S,4,2      ; @GSWPLL_POSTDIV_200M_S
	.comm	_GSWPLL_FBKDIV_200M_S,4,2       ; @GSWPLL_FBKDIV_200M_S
	.comm	_CORE_GSWPLL_GCR_2,4,2          ; @CORE_GSWPLL_GCR_2
	.comm	_GSWPLL_POSTDIV_500M_S,4,2      ; @GSWPLL_POSTDIV_500M_S
	.comm	_GSWPLL_FBKDIV_500M_S,4,2       ; @GSWPLL_FBKDIV_500M_S
	.comm	_GSWPLL_EN_PRE,4,2              ; @GSWPLL_EN_PRE
	.comm	_GSWCK_EN,4,2                   ; @GSWCK_EN
	.comm	_CHG_TRAP,4,2                   ; @CHG_TRAP
	.comm	_C_MDIO_BPS_S,4,2               ; @C_MDIO_BPS_S
	.comm	_MHWSTRAP,4,2                   ; @MHWSTRAP
	.comm	_PHY_INTERFACE_MODE_TRGMII,8,3  ; @PHY_INTERFACE_MODE_TRGMII
	.comm	_P5RGMIIRXCR,4,2                ; @P5RGMIIRXCR
	.comm	_CSR_RGMII_EDGE_ALIGN,4,2       ; @CSR_RGMII_EDGE_ALIGN
	.comm	_CSR_RGMII_RXC_0DEG_CFG_S,4,2   ; @CSR_RGMII_RXC_0DEG_CFG_S
	.comm	_P5RGMIITXCR,4,2                ; @P5RGMIITXCR
	.comm	_CSR_RGMII_TXC_CFG_S,4,2        ; @CSR_RGMII_TXC_CFG_S
	.no_dead_strip	_mt7530_core_pll_setup
.subsections_via_symbols
