	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mvswitch_config_init
_mvswitch_config_init:                  ## @mvswitch_config_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r12
	callq	_to_mvsw
	movq	24(%r12), %r13
	testq	%r13, %r13
	je	LBB0_1
## %bb.2:
	movq	%rax, %r15
	movl	16(%r13), %esi
	leaq	L_.str(%rip), %rdi
	callq	_printk
	movq	_ADVERTISED_100baseT_Full@GOTPCREL(%rip), %rax
	movq	(%rax), %rax
	movq	%rax, 16(%r12)
	movq	%rax, 8(%r12)
	movq	%r15, 24(%r13)
	movq	_PHY_POLL@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, (%r12)
	movq	_MV_PORTS@GOTPCREL(%rip), %rbx
	cmpl	$0, (%rbx)
	jle	LBB0_8
## %bb.3:
	movq	(%r15), %rax
	xorl	%ecx, %ecx
	movq	_MV_WANPORT@GOTPCREL(%rip), %rdx
	.p2align	4, 0x90
LBB0_4:                                 ## =>This Inner Loop Header: Depth=1
	movl	$1, %esi
	shll	%cl, %esi
	xorl	%edi, %edi
	cmpl	(%rdx), %ecx
	sete	%dil
	orl	%esi, 4(%rax,%rdi,4)
	incl	%ecx
	movl	(%rbx), %esi
	cmpl	%esi, %ecx
	jl	LBB0_4
## %bb.5:
	testl	%esi, %esi
	jle	LBB0_8
## %bb.6:
	xorl	%ebx, %ebx
	movq	_CONTROL@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_7:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%r14), %edi
	movl	%ebx, %esi
	callq	_MV_PORTREG
	movq	%r12, %rdi
	movl	%eax, %esi
	xorl	%edx, %edx
	callq	_w16
	incl	%ebx
	movq	_MV_PORTS@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jl	LBB0_7
LBB0_8:
	movl	$2, %edi
	callq	_msleep
	movq	%r12, %r14
	movq	_ATU_CTRL@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_MV_SWITCHREG
	movq	_MV_ATUCTL_RESET@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_w16
	movl	(%r12), %edi
	callq	_MV_SWITCHREG
	movl	(%rbx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	xorl	%ecx, %ecx
	callq	_mvswitch_wait_mask
	testl	%eax, %eax
	js	LBB0_9
## %bb.10:
	movq	%r13, -56(%rbp)                 ## 8-byte Spill
	movl	(%r12), %edi
	callq	_MV_SWITCHREG
	movl	%eax, %r12d
	movq	_MV_ATUCTL_NO_LEARN@GOTPCREL(%rip), %rax
	movq	_MV_ATUCTL_ATU_1K@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	orl	(%rax), %ebx
	movq	_MV_ATUCTL_AGETIME_MIN@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_MV_ATUCTL_AGETIME
	orl	%eax, %ebx
	movq	%r14, %rdi
	movl	%r12d, %esi
	movl	%ebx, %edx
	callq	_w16
	movq	_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_MV_CPUPORT@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	callq	_MV_PORTREG
	movq	_MV_PORTCTRL_RXTR@GOTPCREL(%rip), %rcx
	movq	_MV_PORTCTRL_TXTR@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	_MV_PORTCTRL_ENABLED@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movq	%r14, -48(%rbp)                 ## 8-byte Spill
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_w16
	movl	$2, %edi
	callq	_msleep
	movq	_MV_PORTS@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	jle	LBB0_18
## %bb.11:
	xorl	%r12d, %r12d
	jmp	LBB0_12
	.p2align	4, 0x90
LBB0_17:                                ##   in Loop: Header=BB0_12 Depth=1
	incl	%r12d
	movq	_MV_PORTS@GOTPCREL(%rip), %rax
	cmpl	(%rax), %r12d
	jge	LBB0_18
LBB0_12:                                ## =>This Loop Header: Depth=1
                                        ##     Child Loop BB0_14 Depth 2
	movq	(%r15), %rdi
	callq	_ARRAY_SIZE
	testl	%eax, %eax
	jle	LBB0_17
## %bb.13:                              ##   in Loop: Header=BB0_12 Depth=1
	movl	$1, %r14d
	movl	%r12d, %ecx
	shll	%cl, %r14d
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
	.p2align	4, 0x90
LBB0_14:                                ##   Parent Loop BB0_12 Depth=1
                                        ## =>  This Inner Loop Header: Depth=2
	movq	(%r15), %rdi
	movl	(%rdi,%rbx,4), %eax
	testl	%r14d, %eax
	cmovnel	%eax, %r13d
	incq	%rbx
	callq	_ARRAY_SIZE
	cltq
	cmpq	%rax, %rbx
	jl	LBB0_14
## %bb.15:                              ##   in Loop: Header=BB0_12 Depth=1
	testl	%r13d, %r13d
	je	LBB0_17
## %bb.16:                              ##   in Loop: Header=BB0_12 Depth=1
	movq	_MV_CPUPORT@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %r13d
	notl	%r14d
	andl	%r13d, %r14d
	movq	_VLANMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_MV_PORTREG
	movl	%eax, %r13d
	movl	%r14d, %edi
	callq	_MV_PORTVLAN_PORTS
	movl	%eax, %ebx
	movl	%r12d, %edi
	callq	_MV_PORTVLAN_ID
	orl	%eax, %ebx
	movq	-48(%rbp), %r14                 ## 8-byte Reload
	movq	%r14, %rdi
	movl	%r13d, %esi
	movl	%ebx, %edx
	callq	_w16
	movq	_CONTROL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movl	%r12d, %esi
	callq	_MV_PORTREG
	movq	_MV_PORTCTRL_ENABLED@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_w16
	jmp	LBB0_17
LBB0_18:
	movq	_VLANMAP@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	movq	_MV_CPUPORT@GOTPCREL(%rip), %r14
	movl	(%r14), %esi
	callq	_MV_PORTREG
	movl	%eax, %ebx
	movl	(%r14), %edi
	callq	_MV_PORTVLAN_ID
	movq	-48(%rbp), %r13                 ## 8-byte Reload
	movq	%r13, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_w16
	movq	_MV_PORTS@GOTPCREL(%rip), %rax
	cmpl	$0, (%rax)
	js	LBB0_21
## %bb.19:
	movl	$-1, %ebx
	movq	_ASSOC@GOTPCREL(%rip), %r14
	.p2align	4, 0x90
LBB0_20:                                ## =>This Inner Loop Header: Depth=1
	incl	%ebx
	movl	(%r14), %edi
	movl	%ebx, %esi
	callq	_MV_PORTREG
	movl	%eax, %r12d
	movl	$1, %edi
	movl	%ebx, %ecx
	shll	%cl, %edi
	callq	_MV_PORTASSOC_PORTS
	movq	%r13, %rdi
	movl	%r12d, %esi
	movl	%eax, %edx
	callq	_w16
	movq	_MV_PORTS@GOTPCREL(%rip), %rax
	cmpl	(%rax), %ebx
	jl	LBB0_20
LBB0_21:
	movq	_CTRL@GOTPCREL(%rip), %rax
	movl	(%rax), %edi
	callq	_MV_SWITCHREG
	movq	_MV_SWITCHCTL_MSIZE@GOTPCREL(%rip), %rcx
	movq	_MV_SWITCHCTL_DROP@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movq	%r13, %rdi
	movl	%eax, %esi
	callq	_w16
	movq	_mvswitch_mangle_rx@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movq	-56(%rbp), %rdx                 ## 8-byte Reload
	movl	%eax, 12(%rdx)
	movq	_mvswitch_mangle_tx@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	movl	%eax, 8(%rdx)
	movl	(%rdx), %eax
	movl	%eax, 8(%r15)
	movq	_NETIF_F_HW_VLAN_CTAG_RX@GOTPCREL(%rip), %rcx
	orl	(%rcx), %eax
	movl	%eax, (%rdx)
	xorl	%ebx, %ebx
	jmp	LBB0_22
LBB0_1:
	movq	_EINVAL@GOTPCREL(%rip), %rax
	xorl	%ebx, %ebx
	subl	(%rax), %ebx
	jmp	LBB0_22
LBB0_9:
	movl	%eax, %ebx
	movl	16(%r13), %esi
	leaq	L_.str.1(%rip), %rdi
	callq	_printk
LBB0_22:
	movl	%ebx, %eax
	addq	$24, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_EINVAL,4,2                     ## @EINVAL
	.section	__TEXT,__cstring,cstring_literals
L_.str:                                 ## @.str
	.asciz	"%s: Marvell 88E6060 PHY driver attached.\n"

	.comm	_ADVERTISED_100baseT_Full,8,3   ## @ADVERTISED_100baseT_Full
	.comm	_PHY_POLL,4,2                   ## @PHY_POLL
	.comm	_MV_PORTS,4,2                   ## @MV_PORTS
	.comm	_MV_WANPORT,4,2                 ## @MV_WANPORT
	.comm	_CONTROL,4,2                    ## @CONTROL
	.comm	_ATU_CTRL,4,2                   ## @ATU_CTRL
	.comm	_MV_ATUCTL_RESET,4,2            ## @MV_ATUCTL_RESET
L_.str.1:                               ## @.str.1
	.asciz	"%s: Timeout waiting for the switch to reset.\n"

	.comm	_MV_ATUCTL_NO_LEARN,4,2         ## @MV_ATUCTL_NO_LEARN
	.comm	_MV_ATUCTL_ATU_1K,4,2           ## @MV_ATUCTL_ATU_1K
	.comm	_MV_ATUCTL_AGETIME_MIN,4,2      ## @MV_ATUCTL_AGETIME_MIN
	.comm	_MV_CPUPORT,4,2                 ## @MV_CPUPORT
	.comm	_MV_PORTCTRL_RXTR,4,2           ## @MV_PORTCTRL_RXTR
	.comm	_MV_PORTCTRL_TXTR,4,2           ## @MV_PORTCTRL_TXTR
	.comm	_MV_PORTCTRL_ENABLED,4,2        ## @MV_PORTCTRL_ENABLED
	.comm	_VLANMAP,4,2                    ## @VLANMAP
	.comm	_ASSOC,4,2                      ## @ASSOC
	.comm	_CTRL,4,2                       ## @CTRL
	.comm	_MV_SWITCHCTL_MSIZE,4,2         ## @MV_SWITCHCTL_MSIZE
	.comm	_MV_SWITCHCTL_DROP,4,2          ## @MV_SWITCHCTL_DROP
	.comm	_mvswitch_mangle_rx,4,2         ## @mvswitch_mangle_rx
	.comm	_mvswitch_mangle_tx,4,2         ## @mvswitch_mangle_tx
	.comm	_NETIF_F_HW_VLAN_CTAG_RX,4,2    ## @NETIF_F_HW_VLAN_CTAG_RX
	.comm	_IFF_NO_IP_ALIGN,4,2            ## @IFF_NO_IP_ALIGN
	.comm	_IFF_PROMISC,4,2                ## @IFF_PROMISC
	.comm	_MV_PORTCTRL_HEADER,4,2         ## @MV_PORTCTRL_HEADER
	.comm	_NETIF_F_HW_VLAN_CTAG_TX,4,2    ## @NETIF_F_HW_VLAN_CTAG_TX
	.no_dead_strip	_mvswitch_config_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mvswitch_config_init
_mvswitch_config_init:                  ; @mvswitch_config_init
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #112
	.cfi_def_cfa_offset 112
	stp	x28, x27, [sp, #16]             ; 16-byte Folded Spill
	stp	x26, x25, [sp, #32]             ; 16-byte Folded Spill
	stp	x24, x23, [sp, #48]             ; 16-byte Folded Spill
	stp	x22, x21, [sp, #64]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #80]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #96]             ; 16-byte Folded Spill
	add	x29, sp, #96
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	.cfi_offset w25, -72
	.cfi_offset w26, -80
	.cfi_offset w27, -88
	.cfi_offset w28, -96
	mov	x20, x0
	bl	_to_mvsw
	ldr	x23, [x20, #24]
	cbz	x23, LBB0_20
; %bb.1:
	mov	x19, x0
	ldr	w1, [x23, #16]
Lloh0:
	adrp	x0, l_.str@PAGE
Lloh1:
	add	x0, x0, l_.str@PAGEOFF
	bl	_printk
Lloh2:
	adrp	x8, _ADVERTISED_100baseT_Full@GOTPAGE
Lloh3:
	ldr	x8, [x8, _ADVERTISED_100baseT_Full@GOTPAGEOFF]
Lloh4:
	ldr	x8, [x8]
	stp	x8, x8, [x20, #8]
	str	x19, [x23, #24]
Lloh5:
	adrp	x8, _PHY_POLL@GOTPAGE
Lloh6:
	ldr	x8, [x8, _PHY_POLL@GOTPAGEOFF]
Lloh7:
	ldr	w8, [x8]
	str	w8, [x20]
Lloh8:
	adrp	x25, _MV_PORTS@GOTPAGE
Lloh9:
	ldr	x25, [x25, _MV_PORTS@GOTPAGEOFF]
	ldr	w8, [x25]
Lloh10:
	adrp	x26, _CONTROL@GOTPAGE
Lloh11:
	ldr	x26, [x26, _CONTROL@GOTPAGEOFF]
	cmp	w8, #1
	b.lt	LBB0_7
; %bb.2:
	mov	w8, #0
	ldr	x9, [x19]
	mov	w10, #1
Lloh12:
	adrp	x11, _MV_WANPORT@GOTPAGE
Lloh13:
	ldr	x11, [x11, _MV_WANPORT@GOTPAGEOFF]
	mov	w12, #4
	mov	w13, #8
LBB0_3:                                 ; =>This Inner Loop Header: Depth=1
	lsl	w14, w10, w8
	ldr	w15, [x11]
	cmp	w8, w15
	csel	x15, x13, x12, eq
	ldr	w16, [x9, x15]
	orr	w14, w16, w14
	str	w14, [x9, x15]
	add	w8, w8, #1
	ldr	w14, [x25]
	cmp	w8, w14
	b.lt	LBB0_3
; %bb.4:
	cmp	w14, #1
	b.lt	LBB0_7
; %bb.5:
	mov	w21, #0
LBB0_6:                                 ; =>This Inner Loop Header: Depth=1
	ldr	w0, [x26]
	mov	x1, x21
	bl	_MV_PORTREG
	mov	x1, x0
	mov	x0, x20
	mov	w2, #0
	bl	_w16
	add	w21, w21, #1
	ldr	w8, [x25]
	cmp	w21, w8
	b.lt	LBB0_6
LBB0_7:
	mov	w0, #2
	bl	_msleep
Lloh14:
	adrp	x22, _ATU_CTRL@GOTPAGE
Lloh15:
	ldr	x22, [x22, _ATU_CTRL@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_MV_SWITCHREG
	mov	x1, x0
Lloh16:
	adrp	x21, _MV_ATUCTL_RESET@GOTPAGE
Lloh17:
	ldr	x21, [x21, _MV_ATUCTL_RESET@GOTPAGEOFF]
	ldr	w2, [x21]
	mov	x0, x20
	bl	_w16
	ldr	w0, [x22]
	bl	_MV_SWITCHREG
	mov	x1, x0
	ldr	w2, [x21]
	mov	x0, x20
	mov	w3, #0
	bl	_mvswitch_wait_mask
	tbnz	w0, #31, LBB0_21
; %bb.8:
	str	x23, [sp, #8]                   ; 8-byte Folded Spill
	ldr	w0, [x22]
	bl	_MV_SWITCHREG
	mov	x21, x0
Lloh18:
	adrp	x8, _MV_ATUCTL_NO_LEARN@GOTPAGE
Lloh19:
	ldr	x8, [x8, _MV_ATUCTL_NO_LEARN@GOTPAGEOFF]
Lloh20:
	adrp	x9, _MV_ATUCTL_ATU_1K@GOTPAGE
Lloh21:
	ldr	x9, [x9, _MV_ATUCTL_ATU_1K@GOTPAGEOFF]
Lloh22:
	ldr	w8, [x8]
Lloh23:
	ldr	w9, [x9]
	orr	w22, w9, w8
Lloh24:
	adrp	x8, _MV_ATUCTL_AGETIME_MIN@GOTPAGE
Lloh25:
	ldr	x8, [x8, _MV_ATUCTL_AGETIME_MIN@GOTPAGEOFF]
Lloh26:
	ldr	w0, [x8]
	bl	_MV_ATUCTL_AGETIME
	orr	w2, w22, w0
	mov	x0, x20
	mov	x1, x21
	bl	_w16
	ldr	w0, [x26]
Lloh27:
	adrp	x8, _MV_CPUPORT@GOTPAGE
Lloh28:
	ldr	x8, [x8, _MV_CPUPORT@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
	bl	_MV_PORTREG
	mov	x1, x0
Lloh30:
	adrp	x8, _MV_PORTCTRL_RXTR@GOTPAGE
Lloh31:
	ldr	x8, [x8, _MV_PORTCTRL_RXTR@GOTPAGEOFF]
Lloh32:
	ldr	w8, [x8]
Lloh33:
	adrp	x9, _MV_PORTCTRL_TXTR@GOTPAGE
Lloh34:
	ldr	x9, [x9, _MV_PORTCTRL_TXTR@GOTPAGEOFF]
Lloh35:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh36:
	adrp	x9, _MV_PORTCTRL_ENABLED@GOTPAGE
Lloh37:
	ldr	x9, [x9, _MV_PORTCTRL_ENABLED@GOTPAGEOFF]
Lloh38:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x20
	bl	_w16
	mov	w0, #2
	bl	_msleep
	ldr	w8, [x25]
Lloh39:
	adrp	x24, _VLANMAP@GOTPAGE
Lloh40:
	ldr	x24, [x24, _VLANMAP@GOTPAGEOFF]
	cmp	w8, #1
	b.lt	LBB0_16
; %bb.9:
	mov	w21, #0
	mov	w28, #1
	b	LBB0_11
LBB0_10:                                ;   in Loop: Header=BB0_11 Depth=1
	add	w21, w21, #1
	ldr	w8, [x25]
	cmp	w21, w8
	b.ge	LBB0_16
LBB0_11:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_13 Depth 2
	ldr	x0, [x19]
	bl	_ARRAY_SIZE
	cmp	w0, #1
	b.lt	LBB0_10
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=1
	mov	x27, #0
	mov	w23, #0
	lsl	w22, w28, w21
LBB0_13:                                ;   Parent Loop BB0_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ldr	x0, [x19]
	ldr	w8, [x0, x27, lsl #2]
	tst	w8, w22
	csel	w23, w23, w8, eq
	add	x27, x27, #1
	bl	_ARRAY_SIZE
	cmp	x27, w0, sxtw
	b.lt	LBB0_13
; %bb.14:                               ;   in Loop: Header=BB0_11 Depth=1
	cbz	w23, LBB0_10
; %bb.15:                               ;   in Loop: Header=BB0_11 Depth=1
Lloh41:
	adrp	x8, _MV_CPUPORT@GOTPAGE
Lloh42:
	ldr	x8, [x8, _MV_CPUPORT@GOTPAGEOFF]
Lloh43:
	ldr	w8, [x8]
	lsl	w8, w28, w8
	orr	w8, w8, w23
	bic	w22, w8, w22
	ldr	w0, [x24]
	mov	x1, x21
	bl	_MV_PORTREG
	mov	x23, x0
	mov	x0, x22
	bl	_MV_PORTVLAN_PORTS
	mov	x22, x0
	mov	x0, x21
	bl	_MV_PORTVLAN_ID
	orr	w2, w0, w22
	mov	x0, x20
	mov	x1, x23
	bl	_w16
	ldr	w0, [x26]
	mov	x1, x21
	bl	_MV_PORTREG
	mov	x1, x0
Lloh44:
	adrp	x8, _MV_PORTCTRL_ENABLED@GOTPAGE
Lloh45:
	ldr	x8, [x8, _MV_PORTCTRL_ENABLED@GOTPAGEOFF]
Lloh46:
	ldr	w2, [x8]
	mov	x0, x20
	bl	_w16
	b	LBB0_10
LBB0_16:
	ldr	w0, [x24]
Lloh47:
	adrp	x22, _MV_CPUPORT@GOTPAGE
Lloh48:
	ldr	x22, [x22, _MV_CPUPORT@GOTPAGEOFF]
	ldr	w1, [x22]
	bl	_MV_PORTREG
	mov	x21, x0
	ldr	w0, [x22]
	bl	_MV_PORTVLAN_ID
	mov	x2, x0
	mov	x0, x20
	mov	x1, x21
	bl	_w16
	ldr	w8, [x25]
	tbnz	w8, #31, LBB0_19
; %bb.17:
	mov	w21, #-1
Lloh49:
	adrp	x23, _ASSOC@GOTPAGE
Lloh50:
	ldr	x23, [x23, _ASSOC@GOTPAGEOFF]
	mov	w24, #1
LBB0_18:                                ; =>This Inner Loop Header: Depth=1
	add	w21, w21, #1
	ldr	w0, [x23]
	mov	x1, x21
	bl	_MV_PORTREG
	mov	x22, x0
	lsl	w0, w24, w21
	bl	_MV_PORTASSOC_PORTS
	mov	x2, x0
	mov	x0, x20
	mov	x1, x22
	bl	_w16
	ldr	w8, [x25]
	cmp	w21, w8
	b.lt	LBB0_18
LBB0_19:
Lloh51:
	adrp	x8, _CTRL@GOTPAGE
Lloh52:
	ldr	x8, [x8, _CTRL@GOTPAGEOFF]
Lloh53:
	ldr	w0, [x8]
	bl	_MV_SWITCHREG
	mov	x1, x0
Lloh54:
	adrp	x8, _MV_SWITCHCTL_MSIZE@GOTPAGE
Lloh55:
	ldr	x8, [x8, _MV_SWITCHCTL_MSIZE@GOTPAGEOFF]
Lloh56:
	ldr	w8, [x8]
Lloh57:
	adrp	x9, _MV_SWITCHCTL_DROP@GOTPAGE
Lloh58:
	ldr	x9, [x9, _MV_SWITCHCTL_DROP@GOTPAGEOFF]
Lloh59:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x20
	bl	_w16
	mov	w21, #0
Lloh60:
	adrp	x8, _mvswitch_mangle_rx@GOTPAGE
Lloh61:
	ldr	x8, [x8, _mvswitch_mangle_rx@GOTPAGEOFF]
Lloh62:
	ldr	w8, [x8]
Lloh63:
	adrp	x9, _mvswitch_mangle_tx@GOTPAGE
Lloh64:
	ldr	x9, [x9, _mvswitch_mangle_tx@GOTPAGEOFF]
Lloh65:
	ldr	w9, [x9]
	ldr	x10, [sp, #8]                   ; 8-byte Folded Reload
	stp	w9, w8, [x10, #8]
	ldr	w8, [x10]
	str	w8, [x19, #8]
Lloh66:
	adrp	x9, _NETIF_F_HW_VLAN_CTAG_RX@GOTPAGE
Lloh67:
	ldr	x9, [x9, _NETIF_F_HW_VLAN_CTAG_RX@GOTPAGEOFF]
Lloh68:
	ldr	w9, [x9]
	orr	w8, w9, w8
	str	w8, [x10]
	b	LBB0_22
LBB0_20:
Lloh69:
	adrp	x8, _EINVAL@GOTPAGE
Lloh70:
	ldr	x8, [x8, _EINVAL@GOTPAGEOFF]
Lloh71:
	ldr	w8, [x8]
	neg	w21, w8
	b	LBB0_22
LBB0_21:
	mov	x21, x0
	ldr	w1, [x23, #16]
Lloh72:
	adrp	x0, l_.str.1@PAGE
Lloh73:
	add	x0, x0, l_.str.1@PAGEOFF
	bl	_printk
LBB0_22:
	mov	x0, x21
	ldp	x29, x30, [sp, #96]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #80]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #64]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp, #48]             ; 16-byte Folded Reload
	ldp	x26, x25, [sp, #32]             ; 16-byte Folded Reload
	ldp	x28, x27, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #112
	ret
	.loh AdrpLdrGot	Lloh10, Lloh11
	.loh AdrpLdrGot	Lloh8, Lloh9
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpAdd	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh39, Lloh40
	.loh AdrpLdrGotLdr	Lloh36, Lloh37, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh35
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh20, Lloh21, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh22
	.loh AdrpLdrGotLdr	Lloh44, Lloh45, Lloh46
	.loh AdrpLdrGotLdr	Lloh41, Lloh42, Lloh43
	.loh AdrpLdrGot	Lloh47, Lloh48
	.loh AdrpLdrGot	Lloh49, Lloh50
	.loh AdrpLdrGotLdr	Lloh66, Lloh67, Lloh68
	.loh AdrpLdrGotLdr	Lloh63, Lloh64, Lloh65
	.loh AdrpLdrGotLdr	Lloh60, Lloh61, Lloh62
	.loh AdrpLdrGotLdr	Lloh57, Lloh58, Lloh59
	.loh AdrpLdrGotLdr	Lloh54, Lloh55, Lloh56
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh69, Lloh70, Lloh71
	.loh AdrpAdd	Lloh72, Lloh73
	.cfi_endproc
                                        ; -- End function
	.comm	_EINVAL,4,2                     ; @EINVAL
	.section	__TEXT,__cstring,cstring_literals
l_.str:                                 ; @.str
	.asciz	"%s: Marvell 88E6060 PHY driver attached.\n"

	.comm	_ADVERTISED_100baseT_Full,8,3   ; @ADVERTISED_100baseT_Full
	.comm	_PHY_POLL,4,2                   ; @PHY_POLL
	.comm	_MV_PORTS,4,2                   ; @MV_PORTS
	.comm	_MV_WANPORT,4,2                 ; @MV_WANPORT
	.comm	_CONTROL,4,2                    ; @CONTROL
	.comm	_ATU_CTRL,4,2                   ; @ATU_CTRL
	.comm	_MV_ATUCTL_RESET,4,2            ; @MV_ATUCTL_RESET
l_.str.1:                               ; @.str.1
	.asciz	"%s: Timeout waiting for the switch to reset.\n"

	.comm	_MV_ATUCTL_NO_LEARN,4,2         ; @MV_ATUCTL_NO_LEARN
	.comm	_MV_ATUCTL_ATU_1K,4,2           ; @MV_ATUCTL_ATU_1K
	.comm	_MV_ATUCTL_AGETIME_MIN,4,2      ; @MV_ATUCTL_AGETIME_MIN
	.comm	_MV_CPUPORT,4,2                 ; @MV_CPUPORT
	.comm	_MV_PORTCTRL_RXTR,4,2           ; @MV_PORTCTRL_RXTR
	.comm	_MV_PORTCTRL_TXTR,4,2           ; @MV_PORTCTRL_TXTR
	.comm	_MV_PORTCTRL_ENABLED,4,2        ; @MV_PORTCTRL_ENABLED
	.comm	_VLANMAP,4,2                    ; @VLANMAP
	.comm	_ASSOC,4,2                      ; @ASSOC
	.comm	_CTRL,4,2                       ; @CTRL
	.comm	_MV_SWITCHCTL_MSIZE,4,2         ; @MV_SWITCHCTL_MSIZE
	.comm	_MV_SWITCHCTL_DROP,4,2          ; @MV_SWITCHCTL_DROP
	.comm	_mvswitch_mangle_rx,4,2         ; @mvswitch_mangle_rx
	.comm	_mvswitch_mangle_tx,4,2         ; @mvswitch_mangle_tx
	.comm	_NETIF_F_HW_VLAN_CTAG_RX,4,2    ; @NETIF_F_HW_VLAN_CTAG_RX
	.comm	_IFF_NO_IP_ALIGN,4,2            ; @IFF_NO_IP_ALIGN
	.comm	_IFF_PROMISC,4,2                ; @IFF_PROMISC
	.comm	_MV_PORTCTRL_HEADER,4,2         ; @MV_PORTCTRL_HEADER
	.comm	_NETIF_F_HW_VLAN_CTAG_TX,4,2    ; @NETIF_F_HW_VLAN_CTAG_TX
	.no_dead_strip	_mvswitch_config_init
.subsections_via_symbols
