	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ar71xx_sys_frequency           ## -- Begin function ar71xx_sys_frequency
	.p2align	4, 0x90
_ar71xx_sys_frequency:                  ## @ar71xx_sys_frequency
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	movq	_AR71XX_PLL_REG_CPU_CONFIG@GOTPCREL(%rip), %rax
	movq	_AR71XX_PLL_BASE@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rdi
	addq	(%rax), %rdi
	callq	_KSEG1ADDR
	movl	%eax, %edi
	callq	_readl
	movl	%eax, %esi
	movq	_AR71XX_PLL_DIV_MASK@GOTPCREL(%rip), %rax
	movl	(%rax), %eax
	andl	%esi, %eax
	movq	_AR71XX_PLL_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %eax
	movq	_AR71XX_CPU_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edi
	andl	%esi, %edi
	movq	_AR71XX_CPU_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %edi
	movq	_AR71XX_DDR_DIV_MASK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %ebx
	andl	%esi, %ebx
	movq	_AR71XX_DDR_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %ebx
	movq	_AR71XX_AHB_DIV_MASK@GOTPCREL(%rip), %rcx
	andl	(%rcx), %esi
	movq	_AR71XX_AHB_DIV_SHIFT@GOTPCREL(%rip), %rcx
	movb	(%rcx), %cl
	sarl	%cl, %esi
	incl	%edi
	imull	$40000000, %eax, %ecx           ## imm = 0x2625A00
	addl	$40000000, %ecx                 ## imm = 0x2625A00
	testq	%r12, %r12
	je	LBB0_2
## %bb.1:
	movl	%ecx, %eax
	cltd
	idivl	%edi
	movl	%eax, (%r12)
LBB0_2:
	testq	%r15, %r15
	je	LBB0_4
## %bb.3:
	incl	%ebx
	movl	%ecx, %eax
	cltd
	idivl	%ebx
	movl	%eax, (%r15)
LBB0_4:
	testq	%r14, %r14
	je	LBB0_6
## %bb.5:
	addl	%esi, %esi
	addl	$2, %esi
	movl	%ecx, %eax
	cltd
	idivl	%edi
	cltd
	idivl	%esi
	movl	%eax, (%r14)
LBB0_6:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_AR71XX_PLL_REG_CPU_CONFIG,8,3  ## @AR71XX_PLL_REG_CPU_CONFIG
	.comm	_AR71XX_PLL_BASE,8,3            ## @AR71XX_PLL_BASE
	.comm	_AR71XX_PLL_DIV_MASK,4,2        ## @AR71XX_PLL_DIV_MASK
	.comm	_AR71XX_PLL_DIV_SHIFT,4,2       ## @AR71XX_PLL_DIV_SHIFT
	.comm	_AR71XX_CPU_DIV_MASK,4,2        ## @AR71XX_CPU_DIV_MASK
	.comm	_AR71XX_CPU_DIV_SHIFT,4,2       ## @AR71XX_CPU_DIV_SHIFT
	.comm	_AR71XX_DDR_DIV_MASK,4,2        ## @AR71XX_DDR_DIV_MASK
	.comm	_AR71XX_DDR_DIV_SHIFT,4,2       ## @AR71XX_DDR_DIV_SHIFT
	.comm	_AR71XX_AHB_DIV_MASK,4,2        ## @AR71XX_AHB_DIV_MASK
	.comm	_AR71XX_AHB_DIV_SHIFT,4,2       ## @AR71XX_AHB_DIV_SHIFT
	.comm	_AR91XX_AHB_DIV_MASK,4,2        ## @AR91XX_AHB_DIV_MASK
	.comm	_AR91XX_AHB_DIV_SHIFT,4,2       ## @AR91XX_AHB_DIV_SHIFT
	.comm	_AR91XX_DDR_DIV_MASK,4,2        ## @AR91XX_DDR_DIV_MASK
	.comm	_AR91XX_DDR_DIV_SHIFT,4,2       ## @AR91XX_DDR_DIV_SHIFT
	.comm	_AR91XX_PLL_DIV_MASK,4,2        ## @AR91XX_PLL_DIV_MASK
	.comm	_AR91XX_PLL_DIV_SHIFT,4,2       ## @AR91XX_PLL_DIV_SHIFT
	.comm	_AR91XX_PLL_REG_CPU_CONFIG,8,3  ## @AR91XX_PLL_REG_CPU_CONFIG
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.globl	_ar71xx_sys_frequency           ; -- Begin function ar71xx_sys_frequency
	.p2align	2
_ar71xx_sys_frequency:                  ; @ar71xx_sys_frequency
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x2
	mov	x20, x1
	mov	x21, x0
Lloh0:
	adrp	x8, _AR71XX_PLL_REG_CPU_CONFIG@GOTPAGE
Lloh1:
	ldr	x8, [x8, _AR71XX_PLL_REG_CPU_CONFIG@GOTPAGEOFF]
Lloh2:
	ldr	x8, [x8]
Lloh3:
	adrp	x9, _AR71XX_PLL_BASE@GOTPAGE
Lloh4:
	ldr	x9, [x9, _AR71XX_PLL_BASE@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	add	x0, x9, x8
	bl	_KSEG1ADDR
	bl	_readl
Lloh6:
	adrp	x8, _AR71XX_PLL_DIV_MASK@GOTPAGE
Lloh7:
	ldr	x8, [x8, _AR71XX_PLL_DIV_MASK@GOTPAGEOFF]
Lloh8:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh9:
	adrp	x9, _AR71XX_PLL_DIV_SHIFT@GOTPAGE
Lloh10:
	ldr	x9, [x9, _AR71XX_PLL_DIV_SHIFT@GOTPAGEOFF]
Lloh11:
	ldr	w9, [x9]
	asr	w10, w8, w9
Lloh12:
	adrp	x8, _AR71XX_CPU_DIV_MASK@GOTPAGE
Lloh13:
	ldr	x8, [x8, _AR71XX_CPU_DIV_MASK@GOTPAGEOFF]
Lloh14:
	ldr	w8, [x8]
	and	w8, w8, w0
Lloh15:
	adrp	x9, _AR71XX_CPU_DIV_SHIFT@GOTPAGE
Lloh16:
	ldr	x9, [x9, _AR71XX_CPU_DIV_SHIFT@GOTPAGEOFF]
Lloh17:
	ldr	w9, [x9]
	asr	w8, w8, w9
	add	w14, w8, #1
Lloh18:
	adrp	x8, _AR71XX_DDR_DIV_MASK@GOTPAGE
Lloh19:
	ldr	x8, [x8, _AR71XX_DDR_DIV_MASK@GOTPAGEOFF]
Lloh20:
	ldr	w11, [x8]
Lloh21:
	adrp	x8, _AR71XX_DDR_DIV_SHIFT@GOTPAGE
Lloh22:
	ldr	x8, [x8, _AR71XX_DDR_DIV_SHIFT@GOTPAGEOFF]
Lloh23:
	ldr	w12, [x8]
Lloh24:
	adrp	x8, _AR71XX_AHB_DIV_MASK@GOTPAGE
Lloh25:
	ldr	x8, [x8, _AR71XX_AHB_DIV_MASK@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _AR71XX_AHB_DIV_SHIFT@GOTPAGE
Lloh28:
	ldr	x9, [x9, _AR71XX_AHB_DIV_SHIFT@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	mov	w13, #23040
	movk	w13, #610, lsl #16
	madd	w13, w10, w13, w13
	sdiv	w10, w13, w14
	cbz	x21, LBB0_2
; %bb.1:
	str	w10, [x21]
LBB0_2:
	cbz	x20, LBB0_4
; %bb.3:
	and	w11, w11, w0
	asr	w11, w11, w12
	add	w11, w11, #1
	sdiv	w11, w13, w11
	str	w11, [x20]
LBB0_4:
	cbz	x19, LBB0_6
; %bb.5:
	and	w8, w8, w0
	asr	w8, w8, w9
	lsl	w8, w8, #1
	add	w8, w8, #2
	sdiv	w8, w10, w8
	str	w8, [x19]
LBB0_6:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_AR71XX_PLL_REG_CPU_CONFIG,8,3  ; @AR71XX_PLL_REG_CPU_CONFIG
	.comm	_AR71XX_PLL_BASE,8,3            ; @AR71XX_PLL_BASE
	.comm	_AR71XX_PLL_DIV_MASK,4,2        ; @AR71XX_PLL_DIV_MASK
	.comm	_AR71XX_PLL_DIV_SHIFT,4,2       ; @AR71XX_PLL_DIV_SHIFT
	.comm	_AR71XX_CPU_DIV_MASK,4,2        ; @AR71XX_CPU_DIV_MASK
	.comm	_AR71XX_CPU_DIV_SHIFT,4,2       ; @AR71XX_CPU_DIV_SHIFT
	.comm	_AR71XX_DDR_DIV_MASK,4,2        ; @AR71XX_DDR_DIV_MASK
	.comm	_AR71XX_DDR_DIV_SHIFT,4,2       ; @AR71XX_DDR_DIV_SHIFT
	.comm	_AR71XX_AHB_DIV_MASK,4,2        ; @AR71XX_AHB_DIV_MASK
	.comm	_AR71XX_AHB_DIV_SHIFT,4,2       ; @AR71XX_AHB_DIV_SHIFT
	.comm	_AR91XX_AHB_DIV_MASK,4,2        ; @AR91XX_AHB_DIV_MASK
	.comm	_AR91XX_AHB_DIV_SHIFT,4,2       ; @AR91XX_AHB_DIV_SHIFT
	.comm	_AR91XX_DDR_DIV_MASK,4,2        ; @AR91XX_DDR_DIV_MASK
	.comm	_AR91XX_DDR_DIV_SHIFT,4,2       ; @AR91XX_DDR_DIV_SHIFT
	.comm	_AR91XX_PLL_DIV_MASK,4,2        ; @AR91XX_PLL_DIV_MASK
	.comm	_AR91XX_PLL_DIV_SHIFT,4,2       ; @AR91XX_PLL_DIV_SHIFT
	.comm	_AR91XX_PLL_REG_CPU_CONFIG,8,3  ; @AR91XX_PLL_REG_CPU_CONFIG
.subsections_via_symbols
