	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function oxnas_pcie_link_up
_oxnas_pcie_link_up:                    ## @oxnas_pcie_link_up
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %rbx
	movq	_jiffies@GOTPCREL(%rip), %r13
	movq	(%r13), %rdi
	movq	_LINK_UP_TIMEOUT_SECONDS@GOTPCREL(%rip), %rax
	movq	_HZ@GOTPCREL(%rip), %rcx
	movq	(%rcx), %r14
	imulq	(%rax), %r14
	addq	%rdi, %r14
	movq	%r14, %rsi
	callq	_time_after
	xorl	%ecx, %ecx
	testl	%eax, %eax
	jne	LBB0_6
## %bb.1:
	leaq	-44(%rbp), %r12
	movq	_PCIE_LINK_UP@GOTPCREL(%rip), %r15
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movl	(%rbx), %esi
	movl	4(%rbx), %edi
	movq	%r12, %rdx
	callq	_regmap_read
	movl	(%r15), %eax
	testl	%eax, -44(%rbp)
	jne	LBB0_3
## %bb.4:                               ##   in Loop: Header=BB0_2 Depth=1
	movq	(%r13), %rdi
	movq	%r14, %rsi
	callq	_time_after
	testl	%eax, %eax
	je	LBB0_2
## %bb.5:
	xorl	%ecx, %ecx
	jmp	LBB0_6
LBB0_3:
	movl	$1, %ecx
LBB0_6:
	movl	%ecx, %eax
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_jiffies,8,3                    ## @jiffies
	.comm	_LINK_UP_TIMEOUT_SECONDS,8,3    ## @LINK_UP_TIMEOUT_SECONDS
	.comm	_HZ,8,3                         ## @HZ
	.comm	_PCIE_LINK_UP,4,2               ## @PCIE_LINK_UP
	.no_dead_strip	_oxnas_pcie_link_up
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function oxnas_pcie_link_up
_oxnas_pcie_link_up:                    ; @oxnas_pcie_link_up
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #64
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
Lloh0:
	adrp	x21, _jiffies@GOTPAGE
Lloh1:
	ldr	x21, [x21, _jiffies@GOTPAGEOFF]
Lloh2:
	adrp	x8, _LINK_UP_TIMEOUT_SECONDS@GOTPAGE
Lloh3:
	ldr	x8, [x8, _LINK_UP_TIMEOUT_SECONDS@GOTPAGEOFF]
	ldr	x0, [x21]
Lloh4:
	ldr	x8, [x8]
Lloh5:
	adrp	x9, _HZ@GOTPAGE
Lloh6:
	ldr	x9, [x9, _HZ@GOTPAGEOFF]
Lloh7:
	ldr	x9, [x9]
	madd	x20, x9, x8, x0
	mov	x1, x20
	bl	_time_after
	cbnz	w0, LBB0_4
; %bb.1:
Lloh8:
	adrp	x22, _PCIE_LINK_UP@GOTPAGE
Lloh9:
	ldr	x22, [x22, _PCIE_LINK_UP@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	ldp	w1, w0, [x19]
	add	x2, sp, #12
	bl	_regmap_read
	ldr	w8, [sp, #12]
	ldr	w9, [x22]
	tst	w9, w8
	b.ne	LBB0_5
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	ldr	x0, [x21]
	mov	x1, x20
	bl	_time_after
	cbz	w0, LBB0_2
LBB0_4:
	mov	w0, #0
	b	LBB0_6
LBB0_5:
	mov	w0, #1
LBB0_6:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	add	sp, sp, #64
	ret
	.loh AdrpLdrGotLdr	Lloh5, Lloh6, Lloh7
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh4
	.loh AdrpLdrGot	Lloh0, Lloh1
	.loh AdrpLdrGot	Lloh8, Lloh9
	.cfi_endproc
                                        ; -- End function
	.comm	_jiffies,8,3                    ; @jiffies
	.comm	_LINK_UP_TIMEOUT_SECONDS,8,3    ; @LINK_UP_TIMEOUT_SECONDS
	.comm	_HZ,8,3                         ; @HZ
	.comm	_PCIE_LINK_UP,4,2               ; @PCIE_LINK_UP
	.no_dead_strip	_oxnas_pcie_link_up
.subsections_via_symbols
