	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ag71xx_hw_init
_ag71xx_hw_init:                        ## @ag71xx_hw_init
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r12
	pushq	%rbx
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_RESET_MODULE_GE0_MAC@GOTPCREL(%rip), %rax
	movq	_RESET_MODULE_GE1_MAC@GOTPCREL(%rip), %rcx
	movq	_RESET_MODULE_GE0_PHY@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	movq	_RESET_MODULE_GE1_PHY@GOTPCREL(%rip), %rsi
	movl	(%rsi), %ebx
	orl	(%rax), %edx
	orl	(%rcx), %ebx
	cmpq	$0, (%rdi)
	cmovel	%edx, %ebx
	movq	_AG71XX_REG_MAC_CFG1@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_MAC_CFG1_SR@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	callq	_ag71xx_sb
	movl	$20, %edi
	callq	_udelay
	movq	_AR91XX_RESET_REG_RESET_MODULE@GOTPCREL(%rip), %r12
	movl	(%r12), %edi
	callq	_ar71xx_reset_rr
	movl	(%r12), %edi
	orl	%ebx, %eax
	movl	%eax, %esi
	callq	_ar71xx_reset_wr
	movl	$100000, %edi                   ## imm = 0x186A0
	callq	_udelay
	movl	(%r12), %edi
	callq	_ar71xx_reset_rr
	movl	(%r12), %edi
	notl	%ebx
	andl	%eax, %ebx
	movl	%ebx, %esi
	callq	_ar71xx_reset_wr
	movl	$100000, %edi                   ## imm = 0x186A0
	callq	_udelay
	movl	(%r15), %esi
	movq	_MAC_CFG1_RXE@GOTPCREL(%rip), %rax
	movq	_MAC_CFG1_TXE@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ag71xx_wr
	movq	_AG71XX_REG_MAC_CFG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MAC_CFG2_PAD_CRC_EN@GOTPCREL(%rip), %rax
	movq	_MAC_CFG2_LEN_CHECK@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ag71xx_sb
	movq	_AG71XX_REG_FIFO_CFG0@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FIFO_CFG0_INIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ag71xx_wr
	movl	24(%r14), %esi
	movq	%r14, %rdi
	callq	_ag71xx_mii_ctrl_set_if
	movq	_AG71XX_REG_MII_CFG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_MII_CFG_CLK_DIV_20@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ag71xx_wr
	movq	_AG71XX_REG_FIFO_CFG4@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FIFO_CFG4_INIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ag71xx_sb
	movq	_AG71XX_REG_FIFO_CFG1@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$268369920, %edx                ## imm = 0xFFF0000
	callq	_ag71xx_wr
	movq	_AG71XX_REG_FIFO_CFG2@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$8191, %edx                     ## imm = 0x1FFF
	callq	_ag71xx_wr
	movq	_AG71XX_REG_FIFO_CFG5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_FIFO_CFG5_INIT@GOTPCREL(%rip), %rax
	movl	(%rax), %edx
	movq	%r14, %rdi
	callq	_ag71xx_wr
	movq	%r14, %rdi
	callq	_ag71xx_dma_reset
	movq	%r14, %rdi
	callq	_ag71xx_rings_init
	movl	%eax, %ecx
	movl	$-1, %eax
	testl	%ecx, %ecx
	jne	LBB0_2
## %bb.1:
	movq	_AG71XX_REG_TX_DESC@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	20(%r14), %edi
	callq	_virt_to_phys
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ag71xx_wr
	movq	_AG71XX_REG_RX_DESC@GOTPCREL(%rip), %rax
	movl	(%rax), %ebx
	movl	16(%r14), %edi
	callq	_virt_to_phys
	movq	%r14, %rdi
	movl	%ebx, %esi
	movl	%eax, %edx
	callq	_ag71xx_wr
	movq	8(%r14), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	callq	_ag71xx_hw_set_macaddr
	xorl	%eax, %eax
LBB0_2:
	popq	%rbx
	popq	%r12
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_RESET_MODULE_GE0_MAC,4,2       ## @RESET_MODULE_GE0_MAC
	.comm	_RESET_MODULE_GE0_PHY,4,2       ## @RESET_MODULE_GE0_PHY
	.comm	_RESET_MODULE_GE1_MAC,4,2       ## @RESET_MODULE_GE1_MAC
	.comm	_RESET_MODULE_GE1_PHY,4,2       ## @RESET_MODULE_GE1_PHY
	.comm	_AG71XX_REG_MAC_CFG1,4,2        ## @AG71XX_REG_MAC_CFG1
	.comm	_MAC_CFG1_SR,4,2                ## @MAC_CFG1_SR
	.comm	_AR91XX_RESET_REG_RESET_MODULE,4,2 ## @AR91XX_RESET_REG_RESET_MODULE
	.comm	_MAC_CFG1_RXE,4,2               ## @MAC_CFG1_RXE
	.comm	_MAC_CFG1_TXE,4,2               ## @MAC_CFG1_TXE
	.comm	_AG71XX_REG_MAC_CFG2,4,2        ## @AG71XX_REG_MAC_CFG2
	.comm	_MAC_CFG2_PAD_CRC_EN,4,2        ## @MAC_CFG2_PAD_CRC_EN
	.comm	_MAC_CFG2_LEN_CHECK,4,2         ## @MAC_CFG2_LEN_CHECK
	.comm	_AG71XX_REG_FIFO_CFG0,4,2       ## @AG71XX_REG_FIFO_CFG0
	.comm	_FIFO_CFG0_INIT,4,2             ## @FIFO_CFG0_INIT
	.comm	_AG71XX_REG_MII_CFG,4,2         ## @AG71XX_REG_MII_CFG
	.comm	_MII_CFG_CLK_DIV_20,4,2         ## @MII_CFG_CLK_DIV_20
	.comm	_AG71XX_REG_FIFO_CFG4,4,2       ## @AG71XX_REG_FIFO_CFG4
	.comm	_FIFO_CFG4_INIT,4,2             ## @FIFO_CFG4_INIT
	.comm	_AG71XX_REG_FIFO_CFG1,4,2       ## @AG71XX_REG_FIFO_CFG1
	.comm	_AG71XX_REG_FIFO_CFG2,4,2       ## @AG71XX_REG_FIFO_CFG2
	.comm	_AG71XX_REG_FIFO_CFG5,4,2       ## @AG71XX_REG_FIFO_CFG5
	.comm	_FIFO_CFG5_INIT,4,2             ## @FIFO_CFG5_INIT
	.comm	_AG71XX_REG_TX_DESC,4,2         ## @AG71XX_REG_TX_DESC
	.comm	_AG71XX_REG_RX_DESC,4,2         ## @AG71XX_REG_RX_DESC
	.no_dead_strip	_ag71xx_hw_init
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ag71xx_hw_init
_ag71xx_hw_init:                        ; @ag71xx_hw_init
	.cfi_startproc
; %bb.0:
	stp	x22, x21, [sp, #-48]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 48
	stp	x20, x19, [sp, #16]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #32]             ; 16-byte Folded Spill
	add	x29, sp, #32
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	mov	x19, x0
	ldr	x8, [x0]
Lloh0:
	adrp	x9, _RESET_MODULE_GE0_MAC@GOTPAGE
Lloh1:
	ldr	x9, [x9, _RESET_MODULE_GE0_MAC@GOTPAGEOFF]
Lloh2:
	adrp	x10, _RESET_MODULE_GE1_MAC@GOTPAGE
Lloh3:
	ldr	x10, [x10, _RESET_MODULE_GE1_MAC@GOTPAGEOFF]
Lloh4:
	ldr	w9, [x9]
Lloh5:
	ldr	w10, [x10]
Lloh6:
	adrp	x11, _RESET_MODULE_GE0_PHY@GOTPAGE
Lloh7:
	ldr	x11, [x11, _RESET_MODULE_GE0_PHY@GOTPAGEOFF]
Lloh8:
	adrp	x12, _RESET_MODULE_GE1_PHY@GOTPAGE
Lloh9:
	ldr	x12, [x12, _RESET_MODULE_GE1_PHY@GOTPAGEOFF]
Lloh10:
	ldr	w11, [x11]
Lloh11:
	ldr	w12, [x12]
	orr	w9, w11, w9
	orr	w10, w12, w10
	cmp	x8, #0
	csel	w20, w9, w10, eq
Lloh12:
	adrp	x21, _AG71XX_REG_MAC_CFG1@GOTPAGE
Lloh13:
	ldr	x21, [x21, _AG71XX_REG_MAC_CFG1@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh14:
	adrp	x8, _MAC_CFG1_SR@GOTPAGE
Lloh15:
	ldr	x8, [x8, _MAC_CFG1_SR@GOTPAGEOFF]
Lloh16:
	ldr	w2, [x8]
	bl	_ag71xx_sb
	mov	w0, #20
	bl	_udelay
Lloh17:
	adrp	x22, _AR91XX_RESET_REG_RESET_MODULE@GOTPAGE
Lloh18:
	ldr	x22, [x22, _AR91XX_RESET_REG_RESET_MODULE@GOTPAGEOFF]
	ldr	w0, [x22]
	bl	_ar71xx_reset_rr
	ldr	w8, [x22]
	orr	w1, w0, w20
	mov	x0, x8
	bl	_ar71xx_reset_wr
	mov	w0, #34464
	movk	w0, #1, lsl #16
	bl	_udelay
	ldr	w0, [x22]
	bl	_ar71xx_reset_rr
	ldr	w8, [x22]
	bic	w1, w0, w20
	mov	x0, x8
	bl	_ar71xx_reset_wr
	mov	w0, #34464
	movk	w0, #1, lsl #16
	bl	_udelay
Lloh19:
	adrp	x8, _MAC_CFG1_RXE@GOTPAGE
Lloh20:
	ldr	x8, [x8, _MAC_CFG1_RXE@GOTPAGEOFF]
	ldr	w1, [x21]
Lloh21:
	ldr	w8, [x8]
Lloh22:
	adrp	x9, _MAC_CFG1_TXE@GOTPAGE
Lloh23:
	ldr	x9, [x9, _MAC_CFG1_TXE@GOTPAGEOFF]
Lloh24:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_ag71xx_wr
Lloh25:
	adrp	x8, _AG71XX_REG_MAC_CFG2@GOTPAGE
Lloh26:
	ldr	x8, [x8, _AG71XX_REG_MAC_CFG2@GOTPAGEOFF]
Lloh27:
	adrp	x9, _MAC_CFG2_PAD_CRC_EN@GOTPAGE
Lloh28:
	ldr	x9, [x9, _MAC_CFG2_PAD_CRC_EN@GOTPAGEOFF]
Lloh29:
	ldr	w1, [x8]
Lloh30:
	ldr	w8, [x9]
Lloh31:
	adrp	x9, _MAC_CFG2_LEN_CHECK@GOTPAGE
Lloh32:
	ldr	x9, [x9, _MAC_CFG2_LEN_CHECK@GOTPAGEOFF]
Lloh33:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_ag71xx_sb
Lloh34:
	adrp	x8, _AG71XX_REG_FIFO_CFG0@GOTPAGE
Lloh35:
	ldr	x8, [x8, _AG71XX_REG_FIFO_CFG0@GOTPAGEOFF]
Lloh36:
	ldr	w1, [x8]
Lloh37:
	adrp	x8, _FIFO_CFG0_INIT@GOTPAGE
Lloh38:
	ldr	x8, [x8, _FIFO_CFG0_INIT@GOTPAGEOFF]
Lloh39:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ag71xx_wr
	ldr	w1, [x19, #24]
	mov	x0, x19
	bl	_ag71xx_mii_ctrl_set_if
Lloh40:
	adrp	x8, _AG71XX_REG_MII_CFG@GOTPAGE
Lloh41:
	ldr	x8, [x8, _AG71XX_REG_MII_CFG@GOTPAGEOFF]
Lloh42:
	ldr	w1, [x8]
Lloh43:
	adrp	x8, _MII_CFG_CLK_DIV_20@GOTPAGE
Lloh44:
	ldr	x8, [x8, _MII_CFG_CLK_DIV_20@GOTPAGEOFF]
Lloh45:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ag71xx_wr
Lloh46:
	adrp	x8, _AG71XX_REG_FIFO_CFG4@GOTPAGE
Lloh47:
	ldr	x8, [x8, _AG71XX_REG_FIFO_CFG4@GOTPAGEOFF]
Lloh48:
	ldr	w1, [x8]
Lloh49:
	adrp	x8, _FIFO_CFG4_INIT@GOTPAGE
Lloh50:
	ldr	x8, [x8, _FIFO_CFG4_INIT@GOTPAGEOFF]
Lloh51:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ag71xx_sb
Lloh52:
	adrp	x8, _AG71XX_REG_FIFO_CFG1@GOTPAGE
Lloh53:
	ldr	x8, [x8, _AG71XX_REG_FIFO_CFG1@GOTPAGEOFF]
Lloh54:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #268369920
	bl	_ag71xx_wr
Lloh55:
	adrp	x8, _AG71XX_REG_FIFO_CFG2@GOTPAGE
Lloh56:
	ldr	x8, [x8, _AG71XX_REG_FIFO_CFG2@GOTPAGEOFF]
Lloh57:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #8191
	bl	_ag71xx_wr
Lloh58:
	adrp	x8, _AG71XX_REG_FIFO_CFG5@GOTPAGE
Lloh59:
	ldr	x8, [x8, _AG71XX_REG_FIFO_CFG5@GOTPAGEOFF]
Lloh60:
	ldr	w1, [x8]
Lloh61:
	adrp	x8, _FIFO_CFG5_INIT@GOTPAGE
Lloh62:
	ldr	x8, [x8, _FIFO_CFG5_INIT@GOTPAGEOFF]
Lloh63:
	ldr	w2, [x8]
	mov	x0, x19
	bl	_ag71xx_wr
	mov	x0, x19
	bl	_ag71xx_dma_reset
	mov	x0, x19
	bl	_ag71xx_rings_init
	cbz	w0, LBB0_2
; %bb.1:
	mov	w0, #-1
	b	LBB0_3
LBB0_2:
Lloh64:
	adrp	x8, _AG71XX_REG_TX_DESC@GOTPAGE
Lloh65:
	ldr	x8, [x8, _AG71XX_REG_TX_DESC@GOTPAGEOFF]
Lloh66:
	ldr	w20, [x8]
	ldr	w0, [x19, #20]
	bl	_virt_to_phys
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
                                        ; kill: def $w2 killed $w2 killed $x2
	bl	_ag71xx_wr
Lloh67:
	adrp	x8, _AG71XX_REG_RX_DESC@GOTPAGE
Lloh68:
	ldr	x8, [x8, _AG71XX_REG_RX_DESC@GOTPAGEOFF]
Lloh69:
	ldr	w20, [x8]
	ldr	w0, [x19, #16]
	bl	_virt_to_phys
	mov	x2, x0
	mov	x0, x19
	mov	x1, x20
                                        ; kill: def $w2 killed $w2 killed $x2
	bl	_ag71xx_wr
	ldr	x8, [x19, #8]
	ldr	w1, [x8]
	mov	x0, x19
	bl	_ag71xx_hw_set_macaddr
	mov	w0, #0
LBB0_3:
	ldp	x29, x30, [sp, #32]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #16]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp], #48             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGotLdr	Lloh61, Lloh62, Lloh63
	.loh AdrpLdrGotLdr	Lloh58, Lloh59, Lloh60
	.loh AdrpLdrGotLdr	Lloh55, Lloh56, Lloh57
	.loh AdrpLdrGotLdr	Lloh52, Lloh53, Lloh54
	.loh AdrpLdrGotLdr	Lloh49, Lloh50, Lloh51
	.loh AdrpLdrGotLdr	Lloh46, Lloh47, Lloh48
	.loh AdrpLdrGotLdr	Lloh43, Lloh44, Lloh45
	.loh AdrpLdrGotLdr	Lloh40, Lloh41, Lloh42
	.loh AdrpLdrGotLdr	Lloh37, Lloh38, Lloh39
	.loh AdrpLdrGotLdr	Lloh34, Lloh35, Lloh36
	.loh AdrpLdrGotLdr	Lloh31, Lloh32, Lloh33
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh30
	.loh AdrpLdrGotLdr	Lloh25, Lloh26, Lloh29
	.loh AdrpLdrGotLdr	Lloh22, Lloh23, Lloh24
	.loh AdrpLdrGotLdr	Lloh19, Lloh20, Lloh21
	.loh AdrpLdrGot	Lloh17, Lloh18
	.loh AdrpLdrGotLdr	Lloh14, Lloh15, Lloh16
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh8, Lloh9, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh10
	.loh AdrpLdrGotLdr	Lloh2, Lloh3, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh4
	.loh AdrpLdrGotLdr	Lloh67, Lloh68, Lloh69
	.loh AdrpLdrGotLdr	Lloh64, Lloh65, Lloh66
	.cfi_endproc
                                        ; -- End function
	.comm	_RESET_MODULE_GE0_MAC,4,2       ; @RESET_MODULE_GE0_MAC
	.comm	_RESET_MODULE_GE0_PHY,4,2       ; @RESET_MODULE_GE0_PHY
	.comm	_RESET_MODULE_GE1_MAC,4,2       ; @RESET_MODULE_GE1_MAC
	.comm	_RESET_MODULE_GE1_PHY,4,2       ; @RESET_MODULE_GE1_PHY
	.comm	_AG71XX_REG_MAC_CFG1,4,2        ; @AG71XX_REG_MAC_CFG1
	.comm	_MAC_CFG1_SR,4,2                ; @MAC_CFG1_SR
	.comm	_AR91XX_RESET_REG_RESET_MODULE,4,2 ; @AR91XX_RESET_REG_RESET_MODULE
	.comm	_MAC_CFG1_RXE,4,2               ; @MAC_CFG1_RXE
	.comm	_MAC_CFG1_TXE,4,2               ; @MAC_CFG1_TXE
	.comm	_AG71XX_REG_MAC_CFG2,4,2        ; @AG71XX_REG_MAC_CFG2
	.comm	_MAC_CFG2_PAD_CRC_EN,4,2        ; @MAC_CFG2_PAD_CRC_EN
	.comm	_MAC_CFG2_LEN_CHECK,4,2         ; @MAC_CFG2_LEN_CHECK
	.comm	_AG71XX_REG_FIFO_CFG0,4,2       ; @AG71XX_REG_FIFO_CFG0
	.comm	_FIFO_CFG0_INIT,4,2             ; @FIFO_CFG0_INIT
	.comm	_AG71XX_REG_MII_CFG,4,2         ; @AG71XX_REG_MII_CFG
	.comm	_MII_CFG_CLK_DIV_20,4,2         ; @MII_CFG_CLK_DIV_20
	.comm	_AG71XX_REG_FIFO_CFG4,4,2       ; @AG71XX_REG_FIFO_CFG4
	.comm	_FIFO_CFG4_INIT,4,2             ; @FIFO_CFG4_INIT
	.comm	_AG71XX_REG_FIFO_CFG1,4,2       ; @AG71XX_REG_FIFO_CFG1
	.comm	_AG71XX_REG_FIFO_CFG2,4,2       ; @AG71XX_REG_FIFO_CFG2
	.comm	_AG71XX_REG_FIFO_CFG5,4,2       ; @AG71XX_REG_FIFO_CFG5
	.comm	_FIFO_CFG5_INIT,4,2             ; @FIFO_CFG5_INIT
	.comm	_AG71XX_REG_TX_DESC,4,2         ; @AG71XX_REG_TX_DESC
	.comm	_AG71XX_REG_RX_DESC,4,2         ; @AG71XX_REG_RX_DESC
	.no_dead_strip	_ag71xx_hw_init
.subsections_via_symbols
