	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function mt7530_trgmii_setting
_mt7530_trgmii_setting:                 ## @mt7530_trgmii_setting
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movq	%rdi, %r14
	movq	_CORE_PLL_GROUP5@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movl	$1920, %edx                     ## imm = 0x780
	callq	_mt7530_core_reg_write
	movl	$1, %edi
	callq	_mdelay
	movq	_CORE_PLL_GROUP6@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	xorl	%edx, %edx
	callq	_mt7530_core_reg_write
	movq	_CORE_PLL_GROUP10@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$135, %edx
	callq	_mt7530_core_reg_write
	movl	$1, %edi
	callq	_mdelay
	movq	_CORE_PLL_GROUP11@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	%r14, %rdi
	movl	$135, %edx
	callq	_mt7530_core_reg_write
	movq	_CORE_PLL_GROUP4@GOTPCREL(%rip), %r15
	movl	(%r15), %esi
	movq	_RG_SYSPLL_DDSFBK_EN@GOTPCREL(%rip), %r12
	movq	_RG_SYSPLL_BIAS_EN@GOTPCREL(%rip), %rbx
	movl	(%rbx), %edx
	orl	(%r12), %edx
	movq	%r14, %rdi
	callq	_mt7530_core_reg_write
	movl	$1, %edi
	callq	_mdelay
	movl	(%rbx), %edx
	orl	(%r12), %edx
	movl	(%r15), %esi
	movq	_RG_SYSPLL_BIAS_LPF_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mt7530_core_reg_write
	movq	_CORE_PLL_GROUP2@GOTPCREL(%rip), %rax
	movq	_RG_SYSPLL_EN_NORMAL@GOTPCREL(%rip), %rcx
	movq	_RG_SYSPLL_VODEN@GOTPCREL(%rip), %rdx
	movl	(%rdx), %edx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_RG_SYSPLL_POSDIV_S@GOTPCREL(%rip), %rax
	movb	(%rax), %al
	btsl	%eax, %edx
	movq	%r14, %rdi
	callq	_mt7530_core_reg_write
	movq	_RG_LCCDS_C_S@GOTPCREL(%rip), %rax
	movb	(%rax), %cl
	movl	$3, %edx
	shll	%cl, %edx
	movq	_CORE_PLL_GROUP7@GOTPCREL(%rip), %rax
	movq	_RG_LCDDS_PWDB@GOTPCREL(%rip), %rcx
	orl	(%rcx), %edx
	movl	(%rax), %esi
	movq	_RG_LCDDS_ISO_EN@GOTPCREL(%rip), %rax
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mt7530_core_reg_write
	movl	$1, %edi
	callq	_mdelay
	movq	_TRGMII_GSW_CLK_CG@GOTPCREL(%rip), %rax
	movl	(%rax), %esi
	movq	_GSWCK_EN@GOTPCREL(%rip), %rax
	movq	_TRGMIICK_EN@GOTPCREL(%rip), %rcx
	movl	(%rcx), %edx
	orl	(%rax), %edx
	movq	%r14, %rdi
	callq	_mt7530_core_reg_write
	movq	_NUM_TRGMII_ODT@GOTPCREL(%rip), %r15
	cmpq	$0, (%r15)
	jle	LBB0_3
## %bb.1:
	xorl	%ebx, %ebx
	movq	_TX_DM_DRVP_S@GOTPCREL(%rip), %r12
	movq	_TX_DM_DRVN_S@GOTPCREL(%rip), %r13
	.p2align	4, 0x90
LBB0_2:                                 ## =>This Inner Loop Header: Depth=1
	movq	%rbx, %rdi
	callq	_TRGMII_TD_ODT
	movzbl	(%r12), %ecx
	movl	$4, %esi
	shll	%cl, %esi
	movzbl	(%r13), %ecx
	movl	$4, %edx
	shll	%cl, %edx
	orl	%esi, %edx
	movq	%r14, %rdi
	movl	%eax, %esi
	callq	_mt753x_reg_write
	incq	%rbx
	cmpq	(%r15), %rbx
	jl	LBB0_2
LBB0_3:
	addq	$8, %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_CORE_PLL_GROUP5,4,2            ## @CORE_PLL_GROUP5
	.comm	_CORE_PLL_GROUP6,4,2            ## @CORE_PLL_GROUP6
	.comm	_CORE_PLL_GROUP10,4,2           ## @CORE_PLL_GROUP10
	.comm	_CORE_PLL_GROUP11,4,2           ## @CORE_PLL_GROUP11
	.comm	_CORE_PLL_GROUP4,4,2            ## @CORE_PLL_GROUP4
	.comm	_RG_SYSPLL_DDSFBK_EN,4,2        ## @RG_SYSPLL_DDSFBK_EN
	.comm	_RG_SYSPLL_BIAS_EN,4,2          ## @RG_SYSPLL_BIAS_EN
	.comm	_RG_SYSPLL_BIAS_LPF_EN,4,2      ## @RG_SYSPLL_BIAS_LPF_EN
	.comm	_CORE_PLL_GROUP2,4,2            ## @CORE_PLL_GROUP2
	.comm	_RG_SYSPLL_EN_NORMAL,4,2        ## @RG_SYSPLL_EN_NORMAL
	.comm	_RG_SYSPLL_VODEN,4,2            ## @RG_SYSPLL_VODEN
	.comm	_RG_SYSPLL_POSDIV_S,4,2         ## @RG_SYSPLL_POSDIV_S
	.comm	_CORE_PLL_GROUP7,4,2            ## @CORE_PLL_GROUP7
	.comm	_RG_LCCDS_C_S,4,2               ## @RG_LCCDS_C_S
	.comm	_RG_LCDDS_PWDB,4,2              ## @RG_LCDDS_PWDB
	.comm	_RG_LCDDS_ISO_EN,4,2            ## @RG_LCDDS_ISO_EN
	.comm	_TRGMII_GSW_CLK_CG,4,2          ## @TRGMII_GSW_CLK_CG
	.comm	_GSWCK_EN,4,2                   ## @GSWCK_EN
	.comm	_TRGMIICK_EN,4,2                ## @TRGMIICK_EN
	.comm	_NUM_TRGMII_ODT,8,3             ## @NUM_TRGMII_ODT
	.comm	_TX_DM_DRVP_S,4,2               ## @TX_DM_DRVP_S
	.comm	_TX_DM_DRVN_S,4,2               ## @TX_DM_DRVN_S
	.no_dead_strip	_mt7530_trgmii_setting
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function mt7530_trgmii_setting
_mt7530_trgmii_setting:                 ; @mt7530_trgmii_setting
	.cfi_startproc
; %bb.0:
	stp	x24, x23, [sp, #-64]!           ; 16-byte Folded Spill
	.cfi_def_cfa_offset 64
	stp	x22, x21, [sp, #16]             ; 16-byte Folded Spill
	stp	x20, x19, [sp, #32]             ; 16-byte Folded Spill
	stp	x29, x30, [sp, #48]             ; 16-byte Folded Spill
	add	x29, sp, #48
	.cfi_def_cfa w29, 16
	.cfi_offset w30, -8
	.cfi_offset w29, -16
	.cfi_offset w19, -24
	.cfi_offset w20, -32
	.cfi_offset w21, -40
	.cfi_offset w22, -48
	.cfi_offset w23, -56
	.cfi_offset w24, -64
	mov	x19, x0
Lloh0:
	adrp	x8, _CORE_PLL_GROUP5@GOTPAGE
Lloh1:
	ldr	x8, [x8, _CORE_PLL_GROUP5@GOTPAGEOFF]
Lloh2:
	ldr	w1, [x8]
	mov	w2, #1920
	bl	_mt7530_core_reg_write
	mov	w20, #1
	mov	w0, #1
	bl	_mdelay
Lloh3:
	adrp	x8, _CORE_PLL_GROUP6@GOTPAGE
Lloh4:
	ldr	x8, [x8, _CORE_PLL_GROUP6@GOTPAGEOFF]
Lloh5:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #0
	bl	_mt7530_core_reg_write
Lloh6:
	adrp	x8, _CORE_PLL_GROUP10@GOTPAGE
Lloh7:
	ldr	x8, [x8, _CORE_PLL_GROUP10@GOTPAGEOFF]
Lloh8:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #135
	bl	_mt7530_core_reg_write
	mov	w0, #1
	bl	_mdelay
Lloh9:
	adrp	x8, _CORE_PLL_GROUP11@GOTPAGE
Lloh10:
	ldr	x8, [x8, _CORE_PLL_GROUP11@GOTPAGEOFF]
Lloh11:
	ldr	w1, [x8]
	mov	x0, x19
	mov	w2, #135
	bl	_mt7530_core_reg_write
Lloh12:
	adrp	x21, _CORE_PLL_GROUP4@GOTPAGE
Lloh13:
	ldr	x21, [x21, _CORE_PLL_GROUP4@GOTPAGEOFF]
Lloh14:
	adrp	x22, _RG_SYSPLL_DDSFBK_EN@GOTPAGE
Lloh15:
	ldr	x22, [x22, _RG_SYSPLL_DDSFBK_EN@GOTPAGEOFF]
	ldr	w1, [x21]
	ldr	w8, [x22]
Lloh16:
	adrp	x23, _RG_SYSPLL_BIAS_EN@GOTPAGE
Lloh17:
	ldr	x23, [x23, _RG_SYSPLL_BIAS_EN@GOTPAGEOFF]
	ldr	w9, [x23]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mt7530_core_reg_write
	mov	w0, #1
	bl	_mdelay
	ldr	w1, [x21]
	ldr	w8, [x22]
	ldr	w9, [x23]
	orr	w8, w9, w8
Lloh18:
	adrp	x9, _RG_SYSPLL_BIAS_LPF_EN@GOTPAGE
Lloh19:
	ldr	x9, [x9, _RG_SYSPLL_BIAS_LPF_EN@GOTPAGEOFF]
Lloh20:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_mt7530_core_reg_write
Lloh21:
	adrp	x8, _CORE_PLL_GROUP2@GOTPAGE
Lloh22:
	ldr	x8, [x8, _CORE_PLL_GROUP2@GOTPAGEOFF]
Lloh23:
	ldr	w1, [x8]
Lloh24:
	adrp	x8, _RG_SYSPLL_EN_NORMAL@GOTPAGE
Lloh25:
	ldr	x8, [x8, _RG_SYSPLL_EN_NORMAL@GOTPAGEOFF]
Lloh26:
	ldr	w8, [x8]
Lloh27:
	adrp	x9, _RG_SYSPLL_VODEN@GOTPAGE
Lloh28:
	ldr	x9, [x9, _RG_SYSPLL_VODEN@GOTPAGEOFF]
Lloh29:
	ldr	w9, [x9]
	orr	w8, w9, w8
Lloh30:
	adrp	x9, _RG_SYSPLL_POSDIV_S@GOTPAGE
Lloh31:
	ldr	x9, [x9, _RG_SYSPLL_POSDIV_S@GOTPAGEOFF]
Lloh32:
	ldr	w9, [x9]
	lsl	w9, w20, w9
	orr	w2, w8, w9
	mov	x0, x19
	bl	_mt7530_core_reg_write
Lloh33:
	adrp	x8, _CORE_PLL_GROUP7@GOTPAGE
Lloh34:
	ldr	x8, [x8, _CORE_PLL_GROUP7@GOTPAGEOFF]
Lloh35:
	adrp	x9, _RG_LCCDS_C_S@GOTPAGE
Lloh36:
	ldr	x9, [x9, _RG_LCCDS_C_S@GOTPAGEOFF]
Lloh37:
	ldr	w1, [x8]
Lloh38:
	ldr	w8, [x9]
	mov	w9, #3
	lsl	w8, w9, w8
Lloh39:
	adrp	x9, _RG_LCDDS_PWDB@GOTPAGE
Lloh40:
	ldr	x9, [x9, _RG_LCDDS_PWDB@GOTPAGEOFF]
Lloh41:
	ldr	w9, [x9]
	orr	w8, w8, w9
Lloh42:
	adrp	x9, _RG_LCDDS_ISO_EN@GOTPAGE
Lloh43:
	ldr	x9, [x9, _RG_LCDDS_ISO_EN@GOTPAGEOFF]
Lloh44:
	ldr	w9, [x9]
	orr	w2, w8, w9
	mov	x0, x19
	bl	_mt7530_core_reg_write
	mov	w0, #1
	bl	_mdelay
Lloh45:
	adrp	x8, _TRGMII_GSW_CLK_CG@GOTPAGE
Lloh46:
	ldr	x8, [x8, _TRGMII_GSW_CLK_CG@GOTPAGEOFF]
Lloh47:
	adrp	x9, _GSWCK_EN@GOTPAGE
Lloh48:
	ldr	x9, [x9, _GSWCK_EN@GOTPAGEOFF]
Lloh49:
	ldr	w1, [x8]
Lloh50:
	ldr	w8, [x9]
Lloh51:
	adrp	x9, _TRGMIICK_EN@GOTPAGE
Lloh52:
	ldr	x9, [x9, _TRGMIICK_EN@GOTPAGEOFF]
Lloh53:
	ldr	w9, [x9]
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mt7530_core_reg_write
Lloh54:
	adrp	x21, _NUM_TRGMII_ODT@GOTPAGE
Lloh55:
	ldr	x21, [x21, _NUM_TRGMII_ODT@GOTPAGEOFF]
	ldr	x8, [x21]
	cmp	x8, #1
	b.lt	LBB0_3
; %bb.1:
	mov	x20, #0
Lloh56:
	adrp	x22, _TX_DM_DRVP_S@GOTPAGE
Lloh57:
	ldr	x22, [x22, _TX_DM_DRVP_S@GOTPAGEOFF]
	mov	w23, #4
Lloh58:
	adrp	x24, _TX_DM_DRVN_S@GOTPAGE
Lloh59:
	ldr	x24, [x24, _TX_DM_DRVN_S@GOTPAGEOFF]
LBB0_2:                                 ; =>This Inner Loop Header: Depth=1
	mov	x0, x20
	bl	_TRGMII_TD_ODT
	mov	x1, x0
	ldr	w8, [x22]
	lsl	w8, w23, w8
	ldr	w9, [x24]
	lsl	w9, w23, w9
	orr	w2, w9, w8
	mov	x0, x19
	bl	_mt753x_reg_write
	add	x20, x20, #1
	ldr	x8, [x21]
	cmp	x20, x8
	b.lt	LBB0_2
LBB0_3:
	ldp	x29, x30, [sp, #48]             ; 16-byte Folded Reload
	ldp	x20, x19, [sp, #32]             ; 16-byte Folded Reload
	ldp	x22, x21, [sp, #16]             ; 16-byte Folded Reload
	ldp	x24, x23, [sp], #64             ; 16-byte Folded Reload
	ret
	.loh AdrpLdrGot	Lloh54, Lloh55
	.loh AdrpLdrGotLdr	Lloh51, Lloh52, Lloh53
	.loh AdrpLdrGotLdr	Lloh47, Lloh48, Lloh50
	.loh AdrpLdrGotLdr	Lloh45, Lloh46, Lloh49
	.loh AdrpLdrGotLdr	Lloh42, Lloh43, Lloh44
	.loh AdrpLdrGotLdr	Lloh39, Lloh40, Lloh41
	.loh AdrpLdrGotLdr	Lloh35, Lloh36, Lloh38
	.loh AdrpLdrGotLdr	Lloh33, Lloh34, Lloh37
	.loh AdrpLdrGotLdr	Lloh30, Lloh31, Lloh32
	.loh AdrpLdrGotLdr	Lloh27, Lloh28, Lloh29
	.loh AdrpLdrGotLdr	Lloh24, Lloh25, Lloh26
	.loh AdrpLdrGotLdr	Lloh21, Lloh22, Lloh23
	.loh AdrpLdrGotLdr	Lloh18, Lloh19, Lloh20
	.loh AdrpLdrGot	Lloh16, Lloh17
	.loh AdrpLdrGot	Lloh14, Lloh15
	.loh AdrpLdrGot	Lloh12, Lloh13
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.loh AdrpLdrGot	Lloh58, Lloh59
	.loh AdrpLdrGot	Lloh56, Lloh57
	.cfi_endproc
                                        ; -- End function
	.comm	_CORE_PLL_GROUP5,4,2            ; @CORE_PLL_GROUP5
	.comm	_CORE_PLL_GROUP6,4,2            ; @CORE_PLL_GROUP6
	.comm	_CORE_PLL_GROUP10,4,2           ; @CORE_PLL_GROUP10
	.comm	_CORE_PLL_GROUP11,4,2           ; @CORE_PLL_GROUP11
	.comm	_CORE_PLL_GROUP4,4,2            ; @CORE_PLL_GROUP4
	.comm	_RG_SYSPLL_DDSFBK_EN,4,2        ; @RG_SYSPLL_DDSFBK_EN
	.comm	_RG_SYSPLL_BIAS_EN,4,2          ; @RG_SYSPLL_BIAS_EN
	.comm	_RG_SYSPLL_BIAS_LPF_EN,4,2      ; @RG_SYSPLL_BIAS_LPF_EN
	.comm	_CORE_PLL_GROUP2,4,2            ; @CORE_PLL_GROUP2
	.comm	_RG_SYSPLL_EN_NORMAL,4,2        ; @RG_SYSPLL_EN_NORMAL
	.comm	_RG_SYSPLL_VODEN,4,2            ; @RG_SYSPLL_VODEN
	.comm	_RG_SYSPLL_POSDIV_S,4,2         ; @RG_SYSPLL_POSDIV_S
	.comm	_CORE_PLL_GROUP7,4,2            ; @CORE_PLL_GROUP7
	.comm	_RG_LCCDS_C_S,4,2               ; @RG_LCCDS_C_S
	.comm	_RG_LCDDS_PWDB,4,2              ; @RG_LCDDS_PWDB
	.comm	_RG_LCDDS_ISO_EN,4,2            ; @RG_LCDDS_ISO_EN
	.comm	_TRGMII_GSW_CLK_CG,4,2          ; @TRGMII_GSW_CLK_CG
	.comm	_GSWCK_EN,4,2                   ; @GSWCK_EN
	.comm	_TRGMIICK_EN,4,2                ; @TRGMIICK_EN
	.comm	_NUM_TRGMII_ODT,8,3             ; @NUM_TRGMII_ODT
	.comm	_TX_DM_DRVP_S,4,2               ; @TX_DM_DRVP_S
	.comm	_TX_DM_DRVN_S,4,2               ; @TX_DM_DRVN_S
	.no_dead_strip	_mt7530_trgmii_setting
.subsections_via_symbols
