	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	4, 0x90                         ## -- Begin function ddr_timing_initialisation
_ddr_timing_initialisation:             ## @ddr_timing_initialisation
	.cfi_startproc
## %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	movl	$0, -4(%rbp)
	movl	(%rdi), %eax
	movl	%eax, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	4(%rdi), %ecx
	shll	$4, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	8(%rdi), %ecx
	shll	$8, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	12(%rdi), %ecx
	shll	$12, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	16(%rdi), %ecx
	shll	$16, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	20(%rdi), %ecx
	shll	$20, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	24(%rdi), %ecx
	shll	$24, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movq	_C_DDR_REG_TIMING0@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, (%rcx)
	movl	28(%rdi), %eax
	movl	%eax, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	32(%rdi), %ecx
	shll	$8, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	36(%rdi), %ecx
	shll	$16, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	40(%rdi), %ecx
	shll	$24, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	44(%rdi), %ecx
	shll	$28, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movq	_C_DDR_REG_TIMING1@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, (%rcx)
	movl	48(%rdi), %eax
	movl	%eax, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	52(%rdi), %ecx
	shll	$4, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	56(%rdi), %ecx
	shll	$8, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	60(%rdi), %ecx
	shll	$16, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	64(%rdi), %ecx
	shll	$21, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movl	68(%rdi), %ecx
	shll	$24, %ecx
	addl	%eax, %ecx
	movl	%ecx, -4(%rbp)
	movl	-4(%rbp), %eax
	movq	_C_DDR_REG_TIMING2@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, (%rcx)
	movl	52(%rdi), %eax
	movl	72(%rdi), %ecx
	shll	$16, %ecx
	movl	76(%rdi), %edx
	shll	$8, %edx
	orl	%ecx, %edx
	shll	$4, %eax
	orl	%edx, %eax
	orl	48(%rdi), %eax
	movl	%eax, -4(%rbp)
	movl	-4(%rbp), %eax
	movq	_C_DDR_REG_PHY_TIMING@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, (%rcx)
	movl	80(%rdi), %eax
	movl	%eax, -4(%rbp)
	movl	-4(%rbp), %eax
	movq	_C_DDR_REG_PHY_WR_RATIO@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, (%rcx)
	movl	84(%rdi), %eax
	movl	%eax, -4(%rbp)
	movl	88(%rdi), %eax
	shll	$8, %eax
	addl	%eax, -4(%rbp)
	movl	-4(%rbp), %eax
	movq	_C_DDR_REG_PHY_RD_RATIO@GOTPCREL(%rip), %rcx
	movq	(%rcx), %rcx
	movl	%eax, (%rcx)
	popq	%rbp
	retq
	.cfi_endproc
                                        ## -- End function
	.comm	_C_DDR_REG_TIMING0,8,3          ## @C_DDR_REG_TIMING0
	.comm	_C_DDR_REG_TIMING1,8,3          ## @C_DDR_REG_TIMING1
	.comm	_C_DDR_REG_TIMING2,8,3          ## @C_DDR_REG_TIMING2
	.comm	_C_DDR_REG_PHY_TIMING,8,3       ## @C_DDR_REG_PHY_TIMING
	.comm	_C_DDR_REG_PHY_WR_RATIO,8,3     ## @C_DDR_REG_PHY_WR_RATIO
	.comm	_C_DDR_REG_PHY_RD_RATIO,8,3     ## @C_DDR_REG_PHY_RD_RATIO
	.no_dead_strip	_ddr_timing_initialisation
.subsections_via_symbols

	.section	__TEXT,__text,regular,pure_instructions
	.build_version macos, 13, 0	sdk_version 13, 3
	.p2align	2                               ; -- Begin function ddr_timing_initialisation
_ddr_timing_initialisation:             ; @ddr_timing_initialisation
	.cfi_startproc
; %bb.0:
	sub	sp, sp, #16
	.cfi_def_cfa_offset 16
	str	wzr, [sp, #12]
	ldp	w8, w9, [x0]
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	add	w8, w8, w9, lsl #4
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #8]
	add	w8, w8, w9, lsl #8
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #12]
	add	w8, w8, w9, lsl #12
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #16]
	add	w8, w8, w9, lsl #16
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #20]
	add	w8, w8, w9, lsl #20
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #24]
	add	w8, w8, w9, lsl #24
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
Lloh0:
	adrp	x9, _C_DDR_REG_TIMING0@GOTPAGE
Lloh1:
	ldr	x9, [x9, _C_DDR_REG_TIMING0@GOTPAGEOFF]
Lloh2:
	ldr	x9, [x9]
	str	w8, [x9]
	ldp	w8, w9, [x0, #28]
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	add	w8, w8, w9, lsl #8
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #36]
	add	w8, w8, w9, lsl #16
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #40]
	add	w8, w8, w9, lsl #24
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #44]
	add	w8, w8, w9, lsl #28
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
Lloh3:
	adrp	x9, _C_DDR_REG_TIMING1@GOTPAGE
Lloh4:
	ldr	x9, [x9, _C_DDR_REG_TIMING1@GOTPAGEOFF]
Lloh5:
	ldr	x9, [x9]
	str	w8, [x9]
	ldp	w8, w9, [x0, #48]
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	add	w8, w8, w9, lsl #4
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #56]
	add	w8, w8, w9, lsl #8
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #60]
	add	w8, w8, w9, lsl #16
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #64]
	add	w8, w8, w9, lsl #21
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
	ldr	w9, [x0, #68]
	add	w8, w8, w9, lsl #24
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
Lloh6:
	adrp	x9, _C_DDR_REG_TIMING2@GOTPAGE
Lloh7:
	ldr	x9, [x9, _C_DDR_REG_TIMING2@GOTPAGEOFF]
Lloh8:
	ldr	x9, [x9]
	str	w8, [x9]
	ldp	w8, w9, [x0, #72]
	lsl	w9, w9, #8
	orr	w8, w9, w8, lsl #16
	ldp	w10, w9, [x0, #48]
	orr	w8, w8, w9, lsl #4
	orr	w8, w8, w10
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
Lloh9:
	adrp	x9, _C_DDR_REG_PHY_TIMING@GOTPAGE
Lloh10:
	ldr	x9, [x9, _C_DDR_REG_PHY_TIMING@GOTPAGEOFF]
Lloh11:
	ldr	x9, [x9]
	str	w8, [x9]
	ldr	w8, [x0, #80]
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
Lloh12:
	adrp	x9, _C_DDR_REG_PHY_WR_RATIO@GOTPAGE
Lloh13:
	ldr	x9, [x9, _C_DDR_REG_PHY_WR_RATIO@GOTPAGEOFF]
Lloh14:
	ldr	x9, [x9]
	str	w8, [x9]
	ldr	w8, [x0, #84]
	str	w8, [sp, #12]
	ldr	w8, [x0, #88]
	ldr	w9, [sp, #12]
	add	w8, w9, w8, lsl #8
	str	w8, [sp, #12]
	ldr	w8, [sp, #12]
Lloh15:
	adrp	x9, _C_DDR_REG_PHY_RD_RATIO@GOTPAGE
Lloh16:
	ldr	x9, [x9, _C_DDR_REG_PHY_RD_RATIO@GOTPAGEOFF]
Lloh17:
	ldr	x9, [x9]
	str	w8, [x9]
	add	sp, sp, #16
	ret
	.loh AdrpLdrGotLdr	Lloh15, Lloh16, Lloh17
	.loh AdrpLdrGotLdr	Lloh12, Lloh13, Lloh14
	.loh AdrpLdrGotLdr	Lloh9, Lloh10, Lloh11
	.loh AdrpLdrGotLdr	Lloh6, Lloh7, Lloh8
	.loh AdrpLdrGotLdr	Lloh3, Lloh4, Lloh5
	.loh AdrpLdrGotLdr	Lloh0, Lloh1, Lloh2
	.cfi_endproc
                                        ; -- End function
	.comm	_C_DDR_REG_TIMING0,8,3          ; @C_DDR_REG_TIMING0
	.comm	_C_DDR_REG_TIMING1,8,3          ; @C_DDR_REG_TIMING1
	.comm	_C_DDR_REG_TIMING2,8,3          ; @C_DDR_REG_TIMING2
	.comm	_C_DDR_REG_PHY_TIMING,8,3       ; @C_DDR_REG_PHY_TIMING
	.comm	_C_DDR_REG_PHY_WR_RATIO,8,3     ; @C_DDR_REG_PHY_WR_RATIO
	.comm	_C_DDR_REG_PHY_RD_RATIO,8,3     ; @C_DDR_REG_PHY_RD_RATIO
	.no_dead_strip	_ddr_timing_initialisation
.subsections_via_symbols
