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Paper text:
luminosity conditions at the lhc pose many unique challenges for potential silicon based track trigger systems .
this is true for both level-1 and level-2 trigger applications . among those data formatting
is one of major challenges , where hits and clusters from many thousands of silicon modules must first be shared and organized into overlapping eta - phi trigger towers due to finite size of the beam s luminous region along the beam axis and the finite curvature of charged particles in the magnetic field .
communication between nodes requires high bandwidth , low latency , and flexible real time data sharing .
the first silicon based track trigger at the lhc will be the atlas fast tracker ( ftk ) at level-2  @xcite .
although atlas ftk is designed for level-1 accept rates up to 100  khz , the data volume per event is quite large since all silicon modules ( more than 86 million channels ) are involved at high luminosity , therefore this is where challenging data formatting issues will be encountered for the first time .
we have been developing data formatting solutions for high luminosity lhc conditions and the atlas ftk data formatter system  @xcite is the first targeted application .
the atlas ftk is organized as a set of parallel processor units within an array of 64 eta - phi trigger towers .
the @xmath0 matrix in figure  [ fig : input_output ] shows the required data sharing in the data formatting stage first among the atlas ftk eta - phi trigger towers . because the existing silicon tracker and front end electronics were not designed for triggering , the data sharing among trigger towers is quite complex , as shown in the matrix .
the data formatter hardware design is dominated by the input and output requirements , and we analyzed the data sharing in early design stage using real beam data with the actual readout cable mapping .
the four red boxes in the matrix represent crate boundaries .
boards within each crate communicate over the backplane .
fiber links are used when boards must communicate across crate boundaries .
our analysis shows that the data sharing between trigger towers is highly dependent upon upstream cabling and detector geometry .
the ideal data formatter hardware platform should be flexible enough to accommodate future expansion and allow for changes in input cabling and module assignments .
one example of such a system is shown in figure  [ fig : tower_connection ] , where each trigger tower is represented by a green ball and lines represent data paths .
matrix shows the required data sharing in atlas ftk data formatter among 64 eta - phi trigger towers .
the four red boxes indicate the assignment of trigger towers to four crates to minimize inter - crate data sharing .
the color scale indicates the number of clusters shared between trigger towers per event evaluated with lhc - atlas data taken in 2012  @xcite.,scaledwidth=45.0% ]
our hardware design process followed a bottom up approach whereby we studied various track trigger architectures .
implementations involving full custom backplanes and discrete cables were considered .
eventually the full mesh advanced telecommunication computing architecture ( atca )  @xcite backplane was found to be a natural fit for the data formatter requirements .
the fabric interface of the full mesh backplane enables high speed point - to - point communication between every slot ( figure  [ fig : fullmesh ] ) , with no switching or blocking .
each line in this diagram represents a channel which consists of up to four bidirectional lanes , which runs at the maximum speed of 40  gb / s .
field programmable gate array ( fpga ) devices , which are abundant in local cells , memory , and high speed serial transceivers , were selected for the core processing element on each data formatter board .
high speed serializer components in the fpga are directly connected to the full mesh backplane fabric interface channels and also to pluggable fiber transceivers located on a rear transition module ( rtm ) .
our first prototype atca board incorporated a pair of fpgas , and thus required a high speed local bus to implement the three types of interconnects described in figure  [ fig : internal_connectity ] .
the full mesh backplane , when coupled with large fpgas rich in high speed serial transceivers , offers a level flexibility previously unattainable in a conventional shared bus architecture . in effect
, the system blurs the distinction between individual fpgas and dramatically increases the processing power and i / o capability .
we designed the first prototype , the pulsar iia , to gain experience using the latest fpgas with their high speed transceivers in an atca form factor .
the pulsar iia consists of a front board and rear transition module ( rtm ) as shown in figure  [ fig : pulsar2a_system_photo ] .
in addition we developed an fmc  @xcite mezzanine card which includes a smaller fpga , four fiber transceivers , and a socket used for asic testing .
a mini - backplane was also developed to facilitate standalone board testing on the bench top .
this section describes the design details of each component .
further design details also can be accessed on our open web site  @xcite .
the pulsar iia front board is designed around a pair of xilinx kintex xc7k325 t fpgas .
the block diagram of the board is shown in figure  [ fig : proto_block ] .
each fpga has 16 high speed serial transceivers ( gtx ) which support data rates up to 10  gb / s .
of these 16 gtx transceivers 9 connect to the fabric interface , 6 connect to the rtm , and the last gtx transceiver is used for the local bus .
each board supports up to four high pin count fmc mezzanine cards , which are connected to the main fpgas using general purpose lvds signal pairs .
the fmc form factor has in recent years become a popular choice with xilinx development boards and many third party developers .
when the pulsar iia board is used as the ftk data formatter four cluster finder input mezzanine cards will be used .
a cortex - m3 microcontroller is used as an intelligent platform management controller ( ipmc ) , which is required on all atca boards .
this microcontroller is responsible for the following :    * implementing the ipmi protocol and communicating with the atca shelf manager board(s ) , coordinating hot swap operations , etc . * running telnet and ftp servers which are accessed via the 100base - t base interface ethernet port . * managing firmware images on a micro sdhc flash card . *
programming the fpgas via jtag and monitoring over an spi bus . * reading various board temperature and voltage sensors . * communicating with the rtm over an i@xmath1c bus .
the pulsar iia rtm conforms to the picmg3.8 standard  @xcite and is considered an intelligent - fru device . a small arm microcontroller on the rtm continuously monitors the status of the 8 qsfp+ and 6 sfp+ pluggable transceivers .
the microcontroller also communicates with the front board ipmc microcontroller and coordinates hot swap sequencing .
each of the pulsar iia fpgas connects to one qsfp+ transceiver and two sfp+ transceivers on the rtm .
the pulsar iia supports up to four fmc mezzanine cards with the high pin count ( hpc ) lvds interface .
mezzanine cards may contain fpgas , pattern recognition asics , fiber optic transceivers , or any other custom hardware .
we developed our fmc test mezzanine card , shown in figure  [ fig : test_mezzanine_photo ] , in order to become familiar with the fmc form factor and to study high speed lvds communication between fpgas .
the test mezzanine card features a xilinx kintex xc7k160 t fpga , 4 sfp+ transceivers , 128 mb ddr3 , and a 144 pin socket used for testing custom asic chips , primarily aimed at testing pattern recognition associative memory devices  @xcite .
the fmc connector supports 3.3v and 12v power .
an i@xmath2c bus and jtag interface are also provided for slow controls and in - system programming .          the mini backplane ( figure  [ fig : mini_backplane ] ) was developed to support stand alone testing of a single pulsar iia board and rtm on the bench top .
power is supplied from a 48vdc bench supply .
the base interface ethernet port is brought out to an rj45 connector which may then be connected to a pc and used for communicating with the ipmc microcontroller .
the mini backplane also loops back each fabric interface port .
this loopback feature has proved to be very useful in testing and characterizing the performance of the gtx serial transceivers outside of the crate .
figure  [ fig : board_level_testing_photo ] shows our bench top test setup , which is used to check basic functionality such power supply operation , ipmc microcontroller communication , fpga programming and gtx loopback tests .
the fpga gtx transceivers are driving data in the test - stand system in the fabric interface channels , the rtm channels and the local bus .
it turns out that the fpgas achieved a bit error rates ( ber ) less than @xmath3 level in long - running loop back tests .
the upper limit of ber is defined to be @xmath4 if there is no single error detected during the test .
table  [ tab : long_hour_test ] summarized the measured upper limit .
.ber upper limit measurement results .
the upper limit depends on the length of the long hour test for each channel . [ cols="<,^,^",options="header " , ]     in addition to the ber test , we performed a receiver margin analysis , or eye scan , using the xilinx ibert tool .
the kintex-7 gtx transceivers have built - in diagnostic features which provide a mechanism to measure and visualize the receiver eye margin after rx equalizer  @xcite .
sweeping the receiver sampling point and vertical offset voltage enables the generation of a ber map or statistical eye diagram , where the color represents @xmath5 .
figure  [ fig : eye_diagram ] shows an example of the measured statistical eye diagram and the open blue region indicates that we can have error free operating points .
the size of eye corresponds to the quality of the high speed serial communication after the rx equalization .
all gtx transceiver channels have been tested and characterized using the ibert tool .
furthermore , the eye scan has been done with a xilinx kintex-7 evaluation kit ( kc705 )  @xcite , which provides a `` golden '' reference for comparison studies .
comparing the pulsar iia eye diagrams against the xilinx reference design helps us learn more about high speed layout techniques , which will be used in the next iteration of the board ( section  [ sec : pulsa2b ] ) .
communication over the lvds lines between the fmc mezzanine and the main fpgas has been tested successfully at 400  mhz single data rate ( sdr ) and 200  mhz double data rate ( ddr ) .
thirty - four lvds pairs running at this speed yield a bandwidth of 13.6  gb / s , which exceeds the atlas ftk requirements for the data formatter board .
a crate - level testing followed the single board - level testing .
we set up an atca shelf with a network switch blade in the hub slot and seven pulsar iia front boards as well as rtms in the node slots , as shown in figure  [ fig : crate_level_testing_photo ] .        in our system test
the ipmc microcontroller communicates with the switch blade over the base interface network .
we first log into the switch and then telnet into each pulsar iia board , where commands are issued to program the fpgas and monitor various board sensors .
the default firmware image is setup to drive data over all gtx transceivers to the fabric , rtm and local bus channels .
the xilinx ibert tool has also been used in the the crate to test the backplane performance .
while our 10 g atca backplane is rated for only 3  gb / s per lane it has proven to work admirably at up to 6.25  gb / s across all slots , as shown in figure  [ fig : eye_scan_atca ] .
leveraging the experience we gained through designing , building and testing the pulsar iia system we are in the final stages of laying out the next generation board , the pulsar iib ( figure  [ fig : pulsariib_block ] and figure  [ fig : pulsariib_photo ] ) .
the new board design replaces the two kintex k325 t devices with a single large virtex-7 fpga .
the gtx transceiver count has increased up to 80 channels , providing a significant bandwidth increase to the rtm , fabric and mezzanine cards .
the power regulator sections of the board have been redesigned to handle the increased power required by the virtex-7 fpga .
the pulsar iib boards will be used for the atlas ftk data formatter system .
we anticipate that the boards will also be used for cms l1 tracking trigger early technical demonstrations  @xcite .
the pulsar iia is our first atca prototype board and works as designed , as demonstrated by our successful stand - alone and crate - level tests . through this prototype development process
we have gained experience using the latest xilinx fpgas and high speed serializers to communicate over the atca full mesh backplane .
furthermore , the pulsar iia boards have successfully interfaced with other atca system components such as commercial switch blades and shelf manager cards .
the pulsar iib boards will be used in the atlas ftk data formatter system starting in 2015 .
the pulsar iib design forms the basic building block of a high performance scalable architecture , which may find applications beyond tracking triggers , and may serve as a starting point for future level-1 silicon - based tracking trigger r&d for cms , where the full mesh backplane is used most effectively for sophisticated time multiplexing data transfer schemes .
our baseline design also works well as a general purpose fpga - based processor board .
the design may prove useful in scalable systems where highly flexible , non - blocking , high bandwidth board to board communication is required .
ted liu et al .
, _ a new concept of vertically integrated pattern recognition associative memory _ , fermilab - conf-11 - 709-e , 2011
. published in proceedings of the 2nd international conference on technology and instrumentation in particle physics ( tipp 2011 ) , physics procedia , volume 37 , 2012 , pages 1973 - 1982        j. olsen , t. liu , y. okumura , _ a full mesh atca - based general purpose data processing board : pulsar ii _ , fermilab - conf-13 - 526-cms - ppd , to be published in proceedings of topical workshop on electronics for particle physics 2013 ( twepp-13 ) in the journal of instrumentation ( jinst ) proceedings section
high luminosity conditions at the lhc pose many unique challenges for potential silicon based track trigger systems . 
 one of the major challenges is data formatting , where hits from thousands of silicon modules must first be shared and organized into overlapping eta - phi trigger towers . 
 communication between nodes requires high bandwidth , low latency , and flexible real time data sharing , for which a full mesh backplane is a natural solution . 
 a custom advanced telecommunications computing architecture data processing board is designed with the goal of creating a scalable architecture abundant in flexible , non - blocking , high bandwidth board to board communication channels while keeping the design as simple as possible . 
 we have performed the first prototype board testing and our first attempt at designing the prototype system has proven to be successful . leveraging the experience we gained through designing , building and testing the prototype board system we are in the final stages of laying out the next generation board , which will be used in the atlas level-2 fast tracker as data formatter , as well as in the cms level-1 tracking trigger r&d for early technical demonstrations .