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Paper text:
the concept of particle flow algorithms ( pfa ) and the beam structure of the planned international linear collider ( ilc ) accelerator put constraints on the data acquisition ( daq ) system which are described in the following .
pfa is a widely accepted approach to improve the energy resolution at the ilc .
particle flow uses the high segmentation of about 1@xmath01 cm ( or smaller ) in the detection layer of a sampling calorimeter to track particles through the calorimeter .
the segmentation results in about 24 million readout pads in the electromagnetic calorimeter ( ecal ) of a planned ilc detector@xcite . because of the large number of readout channels it is necessary to minimise the cost of the electronics .
this is achieved by using standard networking chipsets and protocols .
already at an early stage of the calorimeter prototypes the daq system has been designed for scalability . in the current detector
plans the space for the electronics and cooling inside the calorimeters is very restricted .
the daq system under development is aiming at a generic daq system , which will be applicable for the ecal , analogue hadronic calorimeter ( ahcal ) and digital hadron calorimeter ( dhcal ) prototypes . at the ilc
it is assumed that all data will be collected with no triggers implemented . during a bunch train
, data will be stored on the detector and then read out during the inter - train gap of about 200ms .
the data are taken by the detectors on the detection slabs and digitised by the very front - end on - detector electronics or slabs .
then all output data are delivered to electronics boards at the end of the detector .
data is then sent to a concentrator card which collects data from many detector units before being sent off the detector on gigabit optical fibres to a detector receiver in the counting room .
figure[fig_daqoverview ] gives an overview of the generic daq scheme .
the calorimeter is designed such that vfe chips are embedded in the detector slabs .
the slabs are served from the ends with a detector interface ( dif ) .
the difs transmit the data to the link - data aggregator ( lda ) which is fitted on - detector and serves many difs via standard hdmi links .
the data from the ldas are fed to the off - detector receiver ( odr ) via the gigabit optical cables .
the odr is a dedicated pci - express card which is hosted in a daq pc , being capable of saving the data to central storage .
the detector signals are buffered and digitised by the vfe asics situated on the detector slabs .
the vfe asics depend on the detector used in the prototypes accommodating the different features of each detectors .
the interface between the vfe and the daq system is provided by the dif board which is located at the end of the calorimeter slabs .
the dif board consists of a customised part which translates the signals of the asics into more generic signals which are independent of the detector used for the calorimeter .
the interface has been defined together with three detector groups working on prototypes for the ecal , ahcal and dhcal within the eudet@xcite project and is common to the three different detector types . a generic part of the dif passes the data on and sends configuration on to the vfe electronics .
hdmi@xcite is a home entertainment system standard with small cabling and connectors which are commercially available at low cost .
they are rated at more than 300mb / sec for data . to provide redundancy against link failures ,
a provision is made on the dif to connect to its neighbour . by connecting even and odd difs to different ldas
, the system is protected for the loss of a dif - lda link , or even the failure of an entire lda .      in order to accumulate the data sent from the dif ,
an lda collects the data from several difs and sends it further to the odr .
the number of difs aggregated in the lda depends on the detector type chosen in the detection layer
. the optimal number of difs / lda should take into account the number of available pins on the fpga , the bandwidth per dif and the effective performance - price ratio to maximise bandwidth of the optical link .
the current lda prototype can host up to eight links to the difs with a small upgrade up to ten dif connections .
the lda has banks of hdmi connectors for connections to the difs and a small form - factor pluggable ( sfp ) connector for the optical link off - detector .
the prototype version of the lda is built on a commercial development board with a xilinx spartan3 - 200 fpga .
the two sets of connectors are physically add - on boards : one providing the sfp and serialiser chipset for the optical link , the other hosting eight working hdmi connectors with clock fan - out hardware .
a first prototype of the lda has been produced by the company enterpoint @xcite and has been thoroughly tested .
the lda is situated at the edge of the detector , the odr however is located in the counting room connected to the on - detector daq system by an optical fibre . as well as receiving data from the detector , it sends control and configuration data to the lda for distribution to the difs and finally sends the data off the detector to the event building .
it is realised as a pci - express card and can serve up to four ldas per card , with one pc hosting up to two odrs .
for the proposed daq system currently a xilinxvirtex4 fpga is used , thereby using a commercial fpga board designed by plda@xcite . at present , the data stream which will come from the detector in the eudet test beam is simulated by an internal data generator in the firmware or via an on - board ethernet interface ; this allows for a thorough debugging and optimisation of the system before integration with the detectors .
the user interface to the odr card contains two parts : a customised driver and a client program .
the former is mainly tasked with mapping card memory to the user space and providing direct memory access ( dma ) support .
the latter client retrieves data from the odr card memory and stores it on the local disk .
the performance of the prototype odr has been investigated using an ethernet interface to provide an input data stream which is copied to host memory and is currently higher than 150 mb / s writing to an array of disks
. a higher data rate of up to 700mb / s can be achieved when writing into the host memory .
the number of dmas has been optimised for the performance .
the odr prototype is ready and can be optimised further in the next months .
for the event building a good clock is essential because the events will be built using time stamps .
it is understood that a machine clock will be fed into the odrs and fanned out to the ldas and difs .
the requirements on the clock are a low jitter and a fixed latency between the machine clock and the clock in the difs .
commercial networking hardware is not suited for this task as it is most efficient when it can buffer data and provides no guarantees on delivery times . similarly networking hardware built into modern fpgas suffers from varying latency .
therefore a clock and control ( c&c ) board has been designed with links to eight odrs .
the c&c logic is implemented on a board with 6u format , translating into a board size of 100mm@xmath1160 mm .
the clock and control module must interface with the machine and provide stand - alone signal and clock generation .
the machine clock is expected to run between 50 and 100mhz .
the bunch clock will be derived as a multiple of the machine clock .
it is able to deliver fast asynchronous triggers .
it will also receive a busy signal from the vfe .
the hdmi cables used for the dif to lda link will be reused here for sending control data .
the c&c board has been delivered and has been successfully tested . in parallel the firmware for the c&c board is being developed .
the most important requirement on the daq software for the calorimeters is its scalability . in order to minimise risks and to shorten development time
a well - established software framework will be used .
doocs@xcite was found to be suitable for our daq needs .    to adapt doocs to the requirements of our daq software
the equipment name server ( ens ) has been used to integrate all daq components into one system .
ens provides services for naming resolution and rpc communication . in the naming structure of ens
all the functionalities and properties for each device have to be classified and defined . as seen in fig.[fig_daqoverview ] , the odr is the first hardware layer which can communicate with doocs .
therefore the software for the odr has been the starting point of the daq software development .
the doocs client provides a list of commands and configurable parameter with which the odr devices can be managed .
configuration data and files are used when the system starts and runs .
a prototype for the odr doocs client has already been shown . to steer the whole system with the doocs control software several further developments are in progress .
the daq system for the eudet detector will be a hierarchical daq system which minimises the space needed on the detector and uses commercial components to minimise the cost of the daq system . in order to make the development for
the test system independent of the detector type tested a dif board will make the readout generic .
an lda card will concentrate the data from the dif and send it off to the odr which is located off the detector in a control room .
the task of the odr is to store the data .
all components have in addition the task to send configuration data and control messages to the detector and all other daq components upstream .
at the time of writing each hardware component of the daq system exists and has been tested ; the individual components now need to be integrated into a complete system .
current tests have shown that the daq software is able to integrate the odr into the daq system based on the existing software framework doocs and manage successful communication and control tests .
the goal is to have the whole daq system ready for a test beam in 2009 .
we would like to acknowledge the support of the commission of the european communities under the 6th framework programme `` structuring the european research area '' , contract number rii3 - 026126 .
99 tesla technical design report , part iv , a detector for tesla , t. behnke et al . , 2001 eudet - detector r&d towards the international linear collider , eudet homepage : + http://www.eudet.org/ hdmi- high definition multimedia interface consortium homepage : + http://www.hdmi.org enterpoint , fpga and asic design , homepage : + http://www.enterpoint.co.uk plda homepage : + http://www.plda.com/index.php doocs , distributed object oriented control system homepage : + http://tesla.desy.de/doocs/doocs.html linear collider  .
a data acquisition ( daq ) system is described which will be used for the next generation of prototype calorimeters using particle flow algorithms for the international linear collider ( ilc ) . 
 the design is sufficiently generic and scalable such that it should have numerous applications either for ilc detectors or elsewhere within high energy physics in general . 
 the daq system will be implemented using fpgas and built using off - the - shelf components and networking hardware with programmable fpgas . 
 the software for the daq system is based on an existing framework , doocs , which is a server / client object - oriented system . 
 the design philosophy , current status of the project and its aims are presented in this report .