You are presented with multiple paper abstracts, alongside the associated literature review and chapter titles. Given the provided information, you are going to do a literature review. Please generate a coherent literature review that synthesizes the content, draws connections between different works, highlights major findings, and identifies any gaps in the existing research.

Literature Review Title: Survey of Memory Management Techniques for HPC and Cloud Computing 
Chapter Title:  H. ALLOCATION 
1. Abstract of Cited Paper (BIB001):  This paper discusses the incorporation of dynamic memory management during High-Level-Synthesis (HLS) for effective resource utilization in many-accelerator architectures targeting to FPGA devices. We show that in today’s FPGA devices, the main limiting factor of scaling the number of accelerators is the starvation of the available on-chip memory. For many-accelerator architectures, this leads in severe inefficiencies, i.e. memory-induced resource under-utilization of the rest of the FPGA’s resources. Recognizing that static memory allocation – the de-facto mechanism supported by modern design techniques and synthesis tools – forms the main source of “resource under-utilization” problems, we introduce the DMM-HLS framework that extends conventional HLS with dynamic memory allocation/deallocation mechanisms to be incorporated during many-accelerator synthesis. We integrated the proposed framework with the industrial strength Vivado-HLS tool, and we evaluate its effectiveness with a set of key accelerators from emerging application domains. DMM-HLS delivers significant increase in FPGA’s accelerators density (3.8\(\times \) more accelerators) in exchange for affordable overheads in terms of delay and resource count. 
2. Abstract of Cited Paper (BIB002):  Power management through dynamic core, cache and frequency adaptation is becoming a necessity in today's power-constrained many-core environments. Unfortunately, as core count grows, the complexity of both the adaptation hardware and the power management algorithms increases. In this paper, we propose a two-tier hierarchical power management methodology to exploit per-tile voltage regulators and clustered last-level caches. In addition, we include a novel thread migration layer that (i) analyzes threads running on the tiled many-core processor for shared resource sensitivity in tandem with core, cache and frequency adaptation, and (ii) co-schedules threads per tile with compatible behavior. 
3. Abstract of Cited Paper (BIB003):  In systems with complex many-core cache hierarchy, exploiting data locality can significantly reduce execution time and energy consumption of parallel applications. Locality can be exploited at various hardware and software layers. For instance, by implementing private and shared caches in a multi-level fashion, recent hardware designs are already optimised for locality. However, this would all be useless if the software scheduling does not cast the execution in a manner that promotes locality available in the programs themselves. Since programs for parallel systems consist of tasks executed simultaneously, task scheduling becomes crucial for the performance in multi-level cache architectures. This paper presents a heuristic algorithm for homogeneous multi-core systems called locality-aware task scheduling (LeTS). The LeTS heuristic is a work-conserving algorithm that takes into account both locality and load balancing in order to reduce the execution time of target applications. The working principle of LeTS is based on two distinctive phases, namely; working task group formation phase (WTG-FP) and working task group ordering phase (WTG-OP). The WTG-FP forms groups of tasks in order to capture data reuse across tasks while the WTG-OP determines an optimal order of execution for task groups that minimizes the reuse distance of shared data between tasks. We have performed experiments using randomly generated task graphs by varying three major performance parameters, namely: (1) communication to computation ratio (CCR) between 0.1 and 1.0, (2) application size, i.e., task graphs comprising of 50-, 100-, and 300-tasks per graph, and (3) number of cores with 2-, 4-, 8-, and 16-cores execution scenarios. We have also performed experiments using selected real-world applications. The LeTS heuristic reduces overall execution time of applications by exploiting inter-task data locality. Results show that LeTS outperforms state-of-the-art algorithms in amortizing inter-task communication cost. 
4. Abstract of Cited Paper (BIB004):  Abstract The execution of a workflow application can result in an imbalanced workload among allocated processors, ultimately resulting in a waste of resources and a higher cost to the user. Here, we consider a dynamic resource management system in which processors are reserved not for a job but only to run a task, thus allowing a higher resource usage rate. This paper presents a scheduling algorithm that manages concurrent workflows in a dynamic environment in which jobs are submitted by users at any moment in time, on shared heterogeneous resources, and constrained to a specified budget and deadline for each job. Recent research attempted to propose dynamic strategies for concurrent workflows but only addressed fairness in resource sharing among applications while minimizing the execution time. The Multi-QoS Profit-Aware scheduling algorithm (MQ-PAS) proposed here is able to increase the profit achieved by the provider by considering the budget available for each job to define tasks priorities. We study the scalability of the algorithm with different types of workflows and infrastructures. The experimental results show that our strategy improves provider revenue significantly and obtains comparable successful rates of completed jobs. 
5. Abstract of Cited Paper (BIB005):  Abstract Multiple processors have been incorporated on the autonomous mobile robots in order to assure the higher performance needs of the real time applications. These robots are battery powered systems usually executes periodic real time tasks. The main challenge here is to professionally manage the energy consumption of the system to exploit the battery life time. Whenever a task terminates the implementation prior to its worst-case implementation time then slack has been established in the processor. It is the focal factor for increasing the energy consumption of the system. Numerous methods have proposed to handle the processor slack. Allocation of slack fully for reclamation or procrastination doesn’t provide energy efficient loom. This article presents Energy aware proportionate Slack Management Scheduling (EAPSM) mechanism. It efficiently distributes the slack between sluggish and suspension to maximize the energy economy. It also reduces task migration and frequency switching overheads of the system. Simulation experiments illustrate that proposed algorithm reduces energy consumption of the system comparing with the existing optimal schedulers. 
6. Abstract of Cited Paper (BIB006):  With the increases in complexity and number of nodes in large-scale high performance computing (HPC) systems over time, the probability of applications experiencing runtime failures has increased significantly. Projections indicate that exascale-sized systems are likely to operate with mean time between failures (MTBF) of as little as a few minutes. Several strategies have been proposed in recent years for enabling systems of these extreme sizes to be resilient against failures. This work provides a comparison of four state-of-the-art HPC resilience protocols that are being considered for use in exascale systems. We explore the behavior of each resilience protocol operating under the simulated execution of a diverse set of applications and study the performance degradation that a large-scale system experiences from the overhead associated with each resilience protocol as well as the re-computation needed to recover when a failure occurs. Using the results from these analyses, we examine how resource management on exascale systems can be improved by allowing the system to select the optimal resilience protocol depending upon each application's execution characteristics, as well as providing the system resource manager the ability to make scheduling decisions that are “resilience aware” through the use of more accurate execution time predictions.

Literature Review:
The resource allocation and scheduling techniques can be applied as a part of MM in order to choose a specific memory unit for the task. Recent studies on the shared resource-aware scheduling and task allocation methods for HPC systems have focused on locality- BIB004 , energy- BIB006 , performance- BIB005 , resilience- BIB007 aware usage planning of the processors and accelerators. The power-aware threads co-scheduling approach for the multicore processor presented in BIB003 takes into account an effect of the shared last-level cache on the performance degradation. Recent advances in memory allocation for homogeneous multicore architectures have focused on removing the need for application-specific allocators and on improving scalability and allocation speed BIB001 . The work presented in BIB002 addresses the adoption of dynamic memory management for the design of many-accelerator FPGA-based systems, thus allowing each accelerator to dynamically adapt its allocated memory according to the runtime memory requirements. It supports fully-parallel memory access paths by grouping block RAM (BRAM) modules into unique memory banks, named heaps, each managed by an allocator. The approach proves effective in increasing FPGA density. The current research trend in memory allocation is to perform an online characterisation of the memory access behaviour and performing page migrations to improve the behaviour. Data placement for software-controlled on-chip memory requires more complex design solutions, where the characteristics of FPGA computation, memory access patterns, as well as the architectural properties, need to be explicitly considered. FPGAs come with large on-chip memory resource these days. However, the limited dynamic memory management (DMM) support does not allow application developers to maximise the utilisation of the on-chip memory resources during run time and thus achieve higher performance. CPU-based solutions, such as garbage collection and slab allocation, lead to significant resource overhead if use on FPGA directly. Recent research on DMM support for FPGA deal with reducing high latency of memory allocation. Another challenge in on-chip memory allocation is synthesising dynamic data structures that require either particular implementation of an application-specific memory management scheme or resolving the dynamic memory usage using static allocations.