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Paper text:
* side - channel attacks * ( sca ) have been put forward mainly by paul kocher _
et al . _ in 1996 in @xcite .
this first description of a sca explained how the mere observation of the duration of computations could allow an attacker to retrieve the secret key .
the attack was then improved and extended to other cryptosystems  @xcite .    in 1999
kocher  _ et al .
_ described what they called `` '' @xcite .
this new attack used the power consumption instead to the duration but yielded the same result : the retrieval of the secret key .
the process of this latter attack is relatively simple : a large number of cryptographic operations are monitored and the cipher text stored together with the electric consumption
. then guesses were made of some parts of the secret key , which were confirmed or or not by a statistical processing the data .
other attacks against various cryptosystems were based on this method @xcite .
countermeasures soon appeared to protect systems based on a strong algebraic structure@xcite . at he
protection of opposite symmetric cryptosystems often consisted in introducing some randomization either in the computing process or power consumption to prevent the statistical processing of the acquired data .
however `` counter - countermeasures '' also appeared @xcite .
some other protection schemes were designed @xcite .
an interesting and apparently efficient countermeasure is the wddl  @xcite which duplicates each signal in the circuit so that whatever the value is , one of the lines will toggle .
this countermeasure was enhanced by an improved routing of related signals @xcite , which reduces the differences between the power consumptions of a 1 and a 0.    * asynchronous circuits * , the history of which dates back to 1950 , are nowadays increasingly considered as a viable alternative to classical synchronous designs .
indeed they feature some very useful properties such as flexibility , robustness , high speed and low power .
this article brings another good reason to consider asynchronous designs : a greater resistance against _ side - channel attacks_.    some industrial applications of asynchronous asic and fpga begin to appear both in the academic world  @xcite and in the industry  @xcite .    at the same time
synchronous circuits are suffering from problems arising from the distribution of the clock signal through the ic and the excessive power consumption ( and thus dissipation ! ) .
as an asynchronous circuit has no centralized clock , the problems associated with the clock distribution , clock skew and power consumption do not exist .
in addition this circuits offers advantages like :    * average - time performance , * lower electromagnetic radiation , * better robustness towards variations of the power voltage , * better robustness towards fabrication process variations  @xcite , * better composability and modularity because of the simple handshake interfaces and the local timing  @xcite and * better scrambling of the _ side - channel _ information  @xcite .
asynchronous circuits thus seem to be a viable alternative which would remove these limiting factors  @xcite .
due to these advantages , there has been a resurgence of interest in asynchronous design , especially in the reprogrammable field .
there have been several recent successful design projects such as aspro-216  @xcite , aes crypto - processor  @xcite , many of philips designs targeting low power  @xcite , projects focused on designing an asynchronous fpga from a synchronous one , like montage  @xcite and pga - stc  @xcite or targeting asynchronous application - specific fpgas , locally synchronous , like galsa  @xcite and stacc  @xcite or completely asynchronous like papa  @xcite , and other recent works  @xcite .
pga - stc was developed to implement two - phase bundled - data systems such as micro pipelines , galsa for massively parallel computing architecture , stacc for reconfigurable computation and papa was mainly created and optimized for pipe - lined processes .
* this article * describe the design of the plb of a new asynchronous fpga with security as the main requirement , even at the expense of performance . indeed in the particular case of cryptography performance is second to security even if it can not be ignored .
the fpga must be able to implement various styles of asynchronous protocols and different representations of data so as to enable comparisons between these representations and protocols as for their ability to thwart the side - channel attacks .
section [ asynchronous - representation ] describes the representation of data and the different asynchronous protocols used in the fpga .
we also discuss their suitablity for trusted computing .
section [ 4-phase - protocol ] shows the construction of the plb to implement the 4-phase protocol using both binary and ternary representations of data .
section [ 2-phase - protocol ] shows the necessary additions to the plb to accommodate the 2-phase protocols .
section [ programming - the - fpga ] shows how the fpga is programmed .
finally section [ conclusion ] concludes the article .
as opposed to synchronous data , whose validity is guaranteed by the timing of some global `` clock '' signal , the asynchronous computations are synchronized by the availability of data and , when necessary , by a request / acknowledge handshake signalling .    a formal description of delay insensitive representation of data can be found in  @xcite . in the * * q**uasi-**d**elay * * i**nsensitive ( qdi ) protocols the request is carried by the data itself .
this allows to obtain a reliable design , independent of the routing .
the data are transmitted together with the availability information and thus a logic signal or , shorter a `` * * signal * * '' , must be represented by more than a single electrical signal or , shorter , a `` * * wire * * '' representation on a single wire per signal would be acceptable in some cases but we shall restrict ourselves in the following pages to standard cmos levels : @xmath0and @xmath1 . ] . in this article ,
a wire is able to take one of two values , which we denote * 0 * and * 1 * regardless of their actual electric implementation .    in order to avoid glitches
, a sufficient condition is that _ given a signal @xmath2 represented by @xmath3 wires , the transmission of a new value of @xmath2 must consist in * exactly one * of the @xmath3 wires changing its electrical state_. this means that the number of wires is greater than or equal to the number of the states of @xmath2 . as silicon and routing is a precious resource , the number of wires representing a given signal will thus be equal to the number of possible values of this signal .
the most frequently used kind of signal is the binary signal , which carries a \{*`1'*,*`0 ' * } information .
such a signal is encoded with 2 wires .
this representation is called `` * * dual - rail * * '' or `` 2 ''
. however ternary signals , which carry a \{*`0'*,*`1'*,*`2 ' * } information , can also be thought of .
such a signal is represented by 3 wires and one speaks of `` 3 '' representation .
this representation is more compact than the _ 1-out - of-2 _ as for arithmetic : 6 wires in 2 represent 3 2 signals which can take 8 valid values , compared to two _ 1-out - of-3 _ signals , which can take 9 valid values .
however due to the greater complexity of gates in 3 representation , the binary signals are most of the time preferred .
an asynchronous design may need additional signals , which are specialized to synchronisation .
these signal carry no _ data _ information and can thus be coded on a single wire .
they will be referred to as _ acknowledge_signals .
the inputs of the gates which receive such a signal will be denoted @xmath4and those driving these signals will be called @xmath5 .
there are two main families of qdi asynchronous communication protocols , which differ by the nature of the signalling information : the  protocols and the  protocols .      under a  protocol ,
valid values of a signal are separated by a special value , denoted @xmath6 .
the transmission of a value @xmath7 from an emitter to a receiver proceeds as follows :    [ cols=">,<,^,<",options="header " , ]     [ [ synchronization ] ] synchronization + + + + + + + + + + + + + + +    the synchronization is performed by a device called `` @xmath8-decision - wait '' ( or , shorter : ) .
[ 2phe-1x2 ] depicts the schematic of the .
the works as follows :    1 .   in the initial state ,
the following relations hold : @xmath9 , @xmath10 and @xmath11 , which imply @xmath12 and @xmath13 .
( because @xmath14 , idem for @xmath15 ) ; 2 .
assume @xmath16 toggles and thus becomes equal to @xmath17 , the c - elementtransmits the common value of its inputs to @xmath18 , 3 .
as @xmath18 toggles , @xmath19 toggles too and becomes equal to @xmath20 .
4 .   until @xmath4toggles , we have @xmath21 and @xmath22 : even if one of the inputs toggles , the c - elements will remain stable ; 5 .   when @xmath4toggles , @xmath15 and @xmath23 toggle and the system is back in the initial state .
if one wants to combine the computation stage with the , it can not be done in 2 lut .
it is not because of the complexity of the functions : each of @xmath24 and @xmath25 is a function of 2 feed - backs , 1 @xmath4and at most 3 @xmath26 , at least if one does not want to implement trivial , constant functions .
however , the set of 2 luttogether would need 2 feed - backs , 1 @xmath4and 4 @xmath26 , which is one more than the number of available wires .
thus we must use a full plb .
if we use the full plb , the memory element will provide the necessary c - elementand the lutbecome purely combinatorial .
the inputs will be assigned following eq .
[ edge-2x1-in - eq ] and depicted on fig .
[ 2008-edge - all-2x1dw ] : @xmath27    then the lutare programmed as by eq .
[ edge-2x1-lut - eq ] @xmath28      the  protocolis difficult to implement in a fpga without special hardware added to the plb : it takes two plb to implement a single 2-input gate .
however this protocol has advantages as for security because the instantaneous value of the wires is not significant in itself .
for instance * ` 1'*is represented alternatively by the rising and the falling edge of a given wire . an attacker trying dpa , for instance , would have to exhibit the difference between the average consumption of both edges on wire 1 and the same average on wire 0.
the fpga can be partially programmed : it is divided in square blocks which can be programmed separately from the other .
the programming chain is a set of asynchronous fifo memories .
an elementary stage of these fifo is depicted by fig .
[ 2008-jmm - fifo - pg ] .    at reset time ,
all c - elements are set to zero by a general reset wire .
then the programming bits are fed to the fifo , separated by @xmath6values .
the last stage of each fifo is particular : the _ acknowledge_signal is controlled by an external pin . during the programming of the block ,
acknowledge_signal is held low . this way the programming bits are stacked in the fifo and
the fpga becomes functional .
if a partial reconfiguration is wanted , the chosen blocks are cleared by allowing the _ acknowledge_signal of their last stage to acknowledge the value in the last stage .
then the fifo is activated again until all bits have gone thought it . at this point ,
acknowledge_signal is blocked again and the fifo is ready to receive a new set of configuration bits .    during the configuration of the fpga ,
all outputs of plb are kept at 0 to avoid short - circuits .
the plb are programmed first , while all switchboxes are left in an insulation mode .
then the switchboxes are programmed to connect the newly reconfigured part to be connected to the still working part .
it is the designer s responsibility to ensure that the new part can create no conflict with the existing part .
we have presented the programmable logic block of an asynchronous fpga , which is oriented towards security rather than performance . in particular
we have chosen not to implement one of the advantages of an asynchronous design , which usually allows to compute in average time : the early evaluation .
this choice is deliberate as early evaluation is a security risk  @xcite .
the fpga can accommodate various sizes of data as well as various styles of asynchronous control , thus making it possible for the end user to design mixed styles of logic , depending on the applicative requirements .
incidentally , this fpga is also a valuable prototype that allows to perform comparisons between styles of asynchronous protocols .
a silicon is being manufactured and will be used for intensive testing .
the different resistances of the various protocols against sca will be evaluated .
in particular the strict link under the  protocolbetween the value of a signal @xmath29 and the one of the @xmath30 wire will decide whether this protocol is suitable at all for a secure implementation .
_ side - channel attacks _ are efficient attacks against cryptographic devices . 
 they use only quantities observable from outside , such as the duration and the power consumption .    
 attacks against synchronous devices using electric observations are facilitated by the fact that all transitions occur simultaneously with some global clock signal .    
 asynchronous control remove this synchronization and therefore makes it more difficult for the attacker to insulate _ 
 interesting intervals_. in addition the coding of data in an asynchronous circuit is inherently more difficult to attack .    
 this article describes the programmable logic block of an asynchronous fpga resistant against _ side - channel attacks_. additionally it can implement different styles of asynchronous control and of data representation .