You are presented with multiple paper abstracts, alongside the associated literature review and chapter titles. Given the provided information, you are going to do a literature review. Please generate a coherent literature review that synthesizes the content, draws connections between different works, highlights major findings, and identifies any gaps in the existing research.

Literature Review Title: GaN Power Integration for High Frequency and High Efficiency Power Applications: A Review 
Chapter Title:  A. GATE LENGTH 
1. Abstract of Cited Paper (BIB001):  A three-stage W-band GaN monolithic microwave integrated circuit power amplifier (MMIC PA) is reported. Electron-beam lithography has been employed to define a 100-nm T-shaped gate on the AlGaN/GaN HEMT structure with ultrahigh aluminum content. The MMIC PA offers a peak small signal gain of 16.7 dB in the 90–97 GHz bandwidth. Moreover, it achieves a peak 1.66-W (32.2 dBm) output power at 93 GHz in a continuous-wave mode, with an associated power added efficiency of 21% and an associated power gain of 13.7 dB. Most notably, the peak power density is 3.46 W/mm with a 480- $\mu \text{m}$ wide output stage, which exceeds 3 W/mm in AlGaN/GaN HEMT at W-band for the first time. 
2. Abstract of Cited Paper (BIB002):  A linear high power amplifier (HPA) monolithic microwave integrated circuit (MMIC) is designed with 0.15 $\mu\text{m}$ gallium nitride (GaN) high electron mobility transistor (HEMT) technology on silicon carbide (SiC) substrate. To keep the linear characteristics of the power stage, 2:4:8 staging ratio of $8 \times 50\;\mu\text{m}$ unit transistor is adapted for the 3-stage HPA MMIC. The MMIC delivers $\text{P}_{3\;\mathrm{dB}}$ of 39.5 dBm with a PAE of 35% at 21.5 GHz. Linear output power ( $\text{P}_{L}$ ) meeting IMD3 of −25 dBc is 37.3 dBm with an associated PAE of 29.5%. The MMIC dimensions are 3.4 mm $\times$ 2.5 mm, generating an output power density of 1049 mW/mm2.

Literature Review:
The gate length is the determining factor for operation frequency of GaN HEMTs. Along with the scaling down of critical dimensions in IC industry, the gate length in MMIC platform has been scaled down to sub-micron level. Besides conventional optical lithography, electron-beam lithography (EBL) is used in aggressively scaled technologies. The device performance includes the maximum power-gain cutoff frequency f max which is the maximum frequency at which there is still a power gain. It can be expressed as [55] f where f T is the current-gain cutoff frequency; R i , R s , R g , R ds are respectively the gate-charging, source, gate and output resistance; C gd is the gate-drain capacitance. All the denominator parameters need to be reduced to realize high f max . The down-scaled gate length effectively decreases C gd while shorter source-drain length can bring lower R ds . The parasitic components in contacts and interconnects affect the R s and R g , which can be suppressed in optimized integration schemes. Fig. 7 shows the annual number of reports on MMICs from 2015 to August 2019 in terms of gate length values. Although the data are non-exhaustive, the 0.25 µm gate length MMIC process has been the major choice among the total 130 reviewed reports in scientific research area. The percentage has been over 33.3 % throughout these years. This can be attributed to the acceptable balance between device performance and fabrication cost. Aggressively scaled process, i.e. gate length in tens of nanometers, has been demonstrated by HRL laboratory in 2016 BIB001 . In Fig. 7 , the high proportion of the commercial 0.25 µm processes in cited papers can reflect its popularity, accessibility and maturity in industrial companies and research institutes. for mainstream 3G/4G/5G base station architectures, which should meet requirements of massive antenna arrays in power density and efficiency, and they can surpass the performance of LDMOS technology. The parameters of the MMIC performance mainly include operation frequency, output power and power added efficiency (PAE). Here the performance of GaN MMICs with the state-of-the-art processes is discussed in terms of gate length, which is the critical dimension of fabrication process. Fig. 10 shows the output power of reported PAs from 2015 to August 2019. As can be seen from Fig. 10 , the range of output power of reported PAs with smaller gate length (<0.2 µm) is lower, while 0.25 µm PAs have output power ranging from 1 W to 75 W. Other than the different application background of PAs with various operation frequencies, the difference of output power capability can be related with the structures of HEMTs. GaN HEMTs with smaller gate length typically have smaller source-drain distance in order to obtain high device cut-off frequency. The device breakdown voltage as well as the power handling capability is limited. For example, VOLUME 8, 2020 the GaN HEMTs fabricated by Wolfspeed's 0.25 µm process can operate under drain bias of 28-40 V with breakdown voltage larger than 120 V and power density over 6 W/mm. In comparison, GaN HEMTs using 0.15 µm process can be biased at only 28 V, the breakdown voltage is larger than 84 V and the power density is only 3.75 W/mm. The operation frequency and efficiency of PAs are related with amplifier class. According to the operating mechanism, PAs are divided into conventional PAs (Class A, B AB and C) and switching mode PAs (Class D, E, F and so on). The Class A and AB PAs have relative higher linearity but lower efficiency, typically less than 60 %. The structure of Class AB in conventional PAs is simple and regarded as the trade-off between linearity and efficiency. However, its deterioration of linearity is large when operating at high efficiency. In comparison, switching mode PAs show high efficiency but less linearity than conventional PAs. The theoretical efficiency of Class D, E and F PAs can be 100 % while the typical value is 70 % to 90 %. For applications including wireless communication systems, phased array radars and active imagers, different demands in efficiency and linearity require different optimization of PAs. Fig. 11 shows the operation frequency and PAE of the reported PAs with different device gate length to provide an intuitive understanding of relationship between amplifier performance and device structure. Fig. 11(a) shows that the operation frequency of PAs is obviously increasing with smaller device gate length, and can be up to several hundreds of GHz. Relatively high frequency (>100 GHz) can be achieved through process with gate length < 0.15 um. On the other hand, the PAE generally decreases with smaller gate length. Fig. 11(b) shows the decreasing trend of PAE in terms of frequency of 0.25/0.15/0.1 um processes. In early works on X-band and below, gate length is above 0.5 µm and the device f T is 20-40 GHz. The PAs are working in deep A/B-class and the PAE are relatively higher. With the decrease of gate length and increase of frequency, PAE decreases together with gains. From Fig. 11 , the choice of process for up to hundreds of GHz application can be the 0.1 µm and 0.15 µm process. They are expected to provide both better frequency and PAE at the same time compared with 0.25 µm process. Fig. 12 shows two typical optical images of fabricated PAs. Wu et al. realize a peak output power of 1.66 W with a peak PAE of 35% in a continuous-wave mode at 93 GHz using 0.1 µm process BIB002 . Youn et al. realize a peak output power of 9.03 W with a peak PAE of 35% under CW operation at 21.5 GHz using 0.15 µm process BIB003 .