You are presented with multiple paper abstracts, alongside the associated literature review and chapter titles. Given the provided information, you are going to do a literature review. Please generate a coherent literature review that synthesizes the content, draws connections between different works, highlights major findings, and identifies any gaps in the existing research.

Literature Review Title: DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW 
Chapter Title:  DCO Combined with DAC and VCO 
1. Abstract of Cited Paper (BIB001):  A digital PLL (DPLL) with a time-to-digital converter (TDC) embedded within a digitally controlled oscillator (DCO) has been implemented in 65 nm CMOS occupying an active area of 0.027 mm . The quantization step of the TDC naturally tracks the DCO period over corners, and therefore requires no calibration. By utilizing an interpolation flip flop, the timing resolution provided by DCO is further enhanced. The DPLL achieves fractional-N operation without a multi-modulus feedback divider, thereby avoiding its complexity and quantization noise. To improve the TDC linearity, a mismatch filtering technique that incorporates cross-coupled resistor network is proposed to achieve a DNL less than 0.04 LSB of the TDC quantization level. The prototype consumes 3.2 mW with an operation frequency ranging from 600 to 800 MHz. The measured DPLL output phase noise at 800 MHz frequency (after a divide-by-two) achieves and dBc/Hz at 1 kHz and 1 MHz offset, respectively. 
2. Abstract of Cited Paper (BIB002):  Most electronic systems require a frequency reference, and so, much research has been devoted to the realization of on-chip frequency references in standard CMOS. However, the accuracy of such references is limited by the process spread and temperature drift of on-chip components. By means of trimming and temperature compensation, RC and ring oscillators have achieved inaccuracies in the order of 1% [1–2]. LC oscillators achieve inaccuracies below 0.1%, but dissipate much more power [3]. This paper describes a new approach, which exploits the well-defined thermal diffusivity of IC-grade silicon in order to generate frequencies stable to 0.1% over process and temperature variations. Such thermal diffusivity (TD) frequency references dissipate less power than LC oscillators, are more accurate than RC and ring oscillators and, uniquely, scale well with process. 
3. Abstract of Cited Paper (BIB003):  A digitally controlled oscillator (DCO) that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair used in a classical LC-tank oscillator. The new tuning circuitry does not appreciably affect the intrinsic oscillator phase noise and allows to trim the frequency with a programmable resolution for calibration and multi-standard operation. A prototype integrated in 65 nm CMOS technology exhibits a phase noise of @ 1 MHz drawing 16 mA from a supply of 1.8 V, resulting in a FoM of 183 dBc/Hz. The active area is 700 450. 
4. Abstract of Cited Paper (BIB004):  A highly-digital clock multiplication architecture that achieves excellent jitter and mitigates supply noise is presented. The proposed architecture utilizes a calibration-free digital multiplying delay-locked loop (MDLL) to decouple the tradeoff between time-to-digital converter (TDC) resolution and oscillator phase noise in digital phase-locked loops (PLLs). Both reduction in jitter accumulation down to sub-picosecond levels and improved supply noise rejection over conventional PLL architectures is demonstrated with low power consumption. A digital PLL that employs a 1-bit TDC and a low power regulator that seeks to improve supply noise immunity without increasing loop delay is presented and used to compare with the proposed MDLL. The prototype MDLL and DPLL chips are fabricated in a 0.13 μm CMOS technology and operate from a nominal 1.1 V supply. The proposed MDLL achieves an integrated jitter of 400 fs rms at 1.5 GHz output frequency from a 375 MHz reference clock, while consuming 890 μ W. The worst-case supply noise sensitivity of the MDLL is 20 fspp/mVpp which translates to a jitter degradation of 3.8 ps in the presence of 200 mV supply noise. The proposed clock multipliers occupy active die areas of 0.25 mm2 and 0.2 mm2 for the MDLL and DPLL, respectively. 
5. Abstract of Cited Paper (BIB005):  This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm2 it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.

Literature Review:
Many researchers developed ADPLL that uses a DCO composed of a DAC and VCO depicts in Figure 12 to produce a very high-resolution DAC but utilized big silicon area [34] , BIB005 , BIB006 BIB001 BIB002 BIB003 BIB004 . Therefore, another approach reported a high-speed dithering on the digital filter output fractional part.