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the large hadron collider ( lhc ) at cern , geneva , switzerland , will be upgraded in two phases , resulting in ten times higher luminosity .
the atlas detector is one of the two major experiments at the lhc .
for the first phase of the luminosity upgrade , the plan is to install a new layer of pixel detector inside the present pixel detector to compensate for the expected degradation due to the intense radiation . we have designed three asics for possible applications in the optical links for the new pixel layer .
the prototype asics were fabricated using a 130 nm cmos 8rf process .
the asics contain three circuit blocks  @xcite ; a vcsel driver ( optimized for operation at 640 mb / s and 3.2 gb / s ) , a pin receiver with a clock and data recovery circuit capable of operation at 40 , 160 , or 320 mb / s , and a clock multiplier ( two versions ) designed to operate at 640 mb / s .
the clock multiplier is needed to produce a higher frequency clock to serialize the data for transmission .
all circuitries were designed following test results and guidelines from cern on radiation tolerant design in the 130 nm process used  @xcite .
we have characterized the asics in the lab followed by an irradiation with 24 gev protons at cern .
the results are summarized below .
all asics tested were packaged for the irradiation and therefore we experienced some speed degradation due to the added stray capacitance of the packaging .
the two vcsel driver circuits in the test chip have similar architecture ; one optimized for 640 mb / s with higher drive current and the other for 3.2 gb / s with lower current .
each consists of a 1.5 v lvds receiver circuit , a 1.5 to 2.5 v logic converter circuit , and a 2.5 v vcsel driver circuit .
both vcsel drivers allow for adjustable bias and modulation currents and contain circuitry to reduce switching noise on the power supply lines .
the lvds receiver was designed using the standard thin oxide transistors that operate with a 1.5 v supply .
the use of the of the thin oxide transistors allowed us to not only achieve higher bandwidth over the thick oxide transistors but also produce a circuit that could be used by other members of our community developing chips which operate with a single 1.5 v supply .
we used a 2.5 v supply for the driver circuitry because most commercially available vcsels require bias voltages greater than 2 v to produce suitable output optical power .
the driver portion of the chips were therefore designed using the thick oxide transistors available in the 130 nm process .
previous results from cern have shown that thin oxide transistors designed using conventional layout techniques exhibit radiation tolerance suitable for slhc applications . however , conventionally designed thick oxide transistors are not suitably radiation tolerant .
all of the thick oxide transistors were therefore designed using an enclosed structure .
four prototype asics were packaged and the performance was satisfactory up to 1 gb / s .
the performance at higher speeds could not be sufficiently evaluated due to the packaging parasitics .
these tests also verified the operation of the lvds receiver up to 1 gb / s . during the irradiation ,
each driver asic was connected to a 25  @xmath0 resistor instead of a vcsel to allow testing of the degradation of the chip alone .
the duty cycle of the output signal and the current consumption of the lvds receiver remained constant during the irradiation .
however , we observed significant decrease in the vcsel driver circuit current consumption and the output drive current .
it should be noted that the decrease in the drive current could be compensated by adjusting the control current but this option was not used during the irradiation in order to study the degradation under the same condition .
post - irradiation analysis indicates that there is no other significant degradation and the decreases in the vcsel driver current is now understood
. figure  [ iv ] shows the iv curves of a pmos transistor fabricated in the thick oxide technology before and after irradiation .
the iv characteristic before the irradiation is well reproduced by the simulation .
a shift is observed after the irradiation and is well reproduced by the simulation after including a 175 mv threshold shift .
the threshold shift is significantly smaller in the nmos transistors .
the present current mirror in the driver circuit uses both type of transistors and thus is sensitive to the different threshold shifts .
the plan is to use pmos transistors only in the future design .
the pin receiver / decoder contains a trans - impedance amplifier , limiting amplifier , bi - phase mark ( bpm ) decoder with clock recovery , and lvds drivers to send the decoded data and recovered clock off the asic .
all transistors are fabricated with thin oxide , allowing the asic to run with a 1.5 v power supply .
the clock and data recovery is accomplished using a delay locked loop that contains networks of switchable capacitors in the delay stages allow for the three operating frequencies , 40 , 160 , and 320 mb / s . however , due to insufficient time to optimize the design , the asics operate at somewhat lower speed and require higher threshold currents to achieve a low bit error rate ( ber ) .
other than these two limitations , the performance of the asics is satisfactory , including clock jitter , duty cycle , rise / fall time , and high / low levels of the lvds drivers .    for the irradiation ,
the asics were tested in two different setups of four asics each .
the first setup was purely electrical while the second setup involved a pin diode so that we could decouple the electrical and optical degradations . in both setups ,
the decoded data were transmitted to the control room using 20 m of coax . in the first setup ,
40 mb / s bpm signals were transmitted over 20 m of coax to the asics .
the long cable precluded testing at higher speed . in the second setup , we sent 40 mb / s bpm signal via a fiber to a pin diode coupled to an asic .
for both setups , we observed single event upset during the spill but observed no degradation in the threshold for @xmath11 error / s as a function of dosage .
we also monitored the ber vs. pin current during the irradiation .
the ber decreased with larger pin current and was higher for an asic coupled to a pin diode as expected ( fig .
[ ber ] ) .
the current consumption was constant during the irradiation .
detailed post - irradiation analysis reveals no significant degradation in the overall performance .
the clock multiplier circuits consist of charge pump / ring oscillator phase locked loops ( pll ) with dividers in the feedback loop .
one circuit performs a frequency multiplication of 16 and the other a multiplication by 4 , both yielding a 640 mhz clock .
the multipliers are designed using thin oxide transistors and are powered by a single 1.5 v supply .
the multiplier circuits share a common 50  @xmath0 driver and lvds receiver enabling testing of only one multiplier at a time .
an additional switching network allows the recovered clock from the pin receiver prototype to be routed to either multiplier to allow for testing of how the received signal jitter is coupled to the multiplied clock .
four multipliers were packaged for the irradiation .
all asics functioned well with clock jitter of @xmath2 8 ps ( 0.5% ) . during the irradiation
, we observed that the clocks of two asics lost lock and power cycling was needed to resume operation at 640 mhz .
this problem is not yet understood .
detailed post - irradiation analysis also reveals no significant degradation in the overall performance .
we have designed prototype asics using the 130 nm process to enhance the radiation - hardness .
the submission has been mostly successful .
we irradiated the asics to a dose of 70 mrad and observed no significant degradation except in the vcsel driver .
post - irradiation analysis indicates that there is a significant threshold shift in the pmos transistors fabricated in the thick oxide technology for the operation at 2.5 v to drive the vcsel .
an improved version of the asic will be submitted implementing what we learned from the study .
this work was supported in part by the u.s .
department of energy under contract no .
de - fg-02 - 91er-40690 .
the authors are indebted to m. glaser for his tireless assistance in the use of the t7 irradiation facility at cern .
we have designed three asics for possible applications in the optical links of a new layer of pixel detector in the atlas experiment for the first phase of the lhc luminosity upgrade . 
 the asics include a high - speed driver for the vcsel , a receiver / decoder to decode the signal received at the pin diode to extract the data and clock , and a clock multiplier to produce a higher frequency clock to serialize the data for transmission . 
 these asics were designed using a 130 nm cmos process to enhance the radiation - hardness . 
 we have characterized the fabricated asics and the submission has been mostly successful . 
 we irradiated the asics with 24 gev / c protons at cern to a dosage of 70 mrad . 
 we observed no significant degradation except the driver circuit in the vcsel driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a vcsel . 
 the degradation is due to a large threshold shifts in the pmos transistors used .