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Paper text:
ecc is an approach to public - key cryptography based on the algebraic structure of elliptic curves over finite fields .
the use of elliptic curves in cryptography was suggested independently by neal koblitz@xcite and victor s. miller@xcite in 1985 .
elliptic curve cryptography , in essence , entails using the group of points on an elliptic curve as the underlying number system for public key cryptography .
the primary reason for using elliptic curves as a basis for public key crypto - systems is that elliptic curve based crypto - systems appear to provide better security than traditional crypto - systems for a given key size@xcite , thereby reducing the process overhead .
one can take advantage of this fact to increase security , or ( more often ) to increase performance by reducing the key size while keeping the same security .
designers are now working on designing dedicated hardware accelerator blocks along with the main processor @xcite@xcite@xcite to increase the throughput of the design .
ecc algorithm is used for secured communication in smart cards@xcite and also in gsm security@xcite .
so , high speed , resource constrained environment is required . using a dual - core instead of a dedicated co
- processor enables the user to operate from the application layer without entering the subordinate layers . also , the thread - level parallelism , used by the dual - core ensures higher throughput without increasing the much power , which is an important issue for low - power communication devices like smart cards .
implementations can be made in different platforms namely , fpga or asic or can be done using micro - controllers .
fpgas provides reconfigurability and lesser design time , while asic provides better throughput though the design time is large and expensive .
we propose the design and implementation of elliptic curve cryptography ( ecc ) encryption algorithm by developing suitable single core and dual core design on xilinx virtex 4 ( ml403 ) device .
the system is optimized in terms of execution speed .
we perform a trade - off between throughput , power and resource requirements for our dual core implementation . to the best of our knowledge ,
dual - soft core processor based implementation of ecc in an fpga is not yet available in related literatures and hence it is first of its kind .
the paper is organized as follows : section 2 details the overview of ecc , the encryption and decryption process .
the design and implementation details for single and dual - core processor architectures are described in section 3 .
the experimental results are summarized in section 4 .
conclusion and references are briefed in section 5 .
this section provides some background on elliptic curves and ecc and then the hardness of decrypting the elliptic curve ciphers is also discussed .
the idea of a multi processor system , establishment of communication between the processors using shared memory and the needed data synchronization is also briefed in the later part of this section .
elliptic curves are described by curves , which are similar to cubic equations , used for calculating the circumference of an ellipse . in general , cubic equations for elliptic curves
take the following form known as weierstrass equation@xcite : @xmath0 where _ a _ , _ b_,_c _ , _ d _ , _ e _
, _ p _ are real numbers and _ x _ and _ y _ take on any values in the real numbers . for our purpose , it is sufficient to limit ourselves to equation of the form given in equation[eqn : reduced weierstrass equation ] for appropriate curve parameters of ecc .
@xmath1 figure [ fig : elliptic curve(a ) ] shows an example of elliptic curve .
ecc can be used to encrypt a plain text message _
m _ into cipher text for secured communication .
firstly , the plain text message _
m _ is converted into a set of finite points p@xmath2(_x _ , _ y _ ) , which lie in the elliptic curve e@xmath3(_a _ , _ b _ ) .
a generator point , _ g _
e@xmath3(_a _ , _ b _ ) , is chosen next such that the smallest value of _ n _ for which _ ng _ = _ o _ is a very large prime number .
the elliptic curve e@xmath3(_a _ , _ b _ ) and the generator point _
g _ are then made public .
let there be two parties a and b who wish to communicate using ecc .
each user selects a private key , user a s private key is n@xmath5 , while n@xmath6 is the private key for user b such that n@xmath5 , n@xmath6 < _ _
n__. then they compute their public keys .
the public key of a is p@xmath5 = n@xmath5_g _ , while for b the public key is p@xmath6 = n@xmath6_g_. to send the secret message to b , a encrypts the message point p@xmath2 by choosing a random number _
k _ and computes the cipher text points c@xmath2 using b s public key . the cipher text is given by : @xmath7   \label{ciphertext}\ ] ] on receiving the cipher text ( pair of points ) _ c@xmath2 _ , b multiplies the first pair of points ( _ kg _ ) with his private key _
n@xmath6 _ , and then adds the result to the second point of the cipher text ( _ p@xmath2 + kp@xmath6 _ )
i.e. , @xmath8 = \;\;(p_{m } + kn_{b}g ) - [ n_{b}(kg ) ] = \;\;p_{m } \label{palintext}\ ] ] plain text message point p@xmath2 , corresponds to the message _ m_.
it is to be observed here that only b can remove n@xmath6(_kg _ ) from the second part of the cipher text .
no , third party or intruder can know the message except b. thus , ecc is very secured and can be relied for confidential communication .
+ breaking of ecc is a `` hard problem '' , which requires computing of discreet logarithm @xcite .
a multi processor system consists of two or more processors working concurrently and capable of communicating with each other .
such a design tends to double the throughput , with two processors running independently , but with an extra cost of resource and power . on the other hand ,
a multi core system is one in which more than one processor is build on the same die .
in fpga we have on - chip soft processor cores , which has been utilized in our design to multi core design .
there are some basic conditions required for the execution of a design in a multi core system .
the primary being concurrency in the design i.e. , no data dependency must be present in processes that run in different processors and also the two processors must have some handshaking for synchronization of data .
multi core processors often use a shared memory system or a mailbox system as a interprocessor communication mechanism , that operates very quickly@xcite .      in a multi core environment , mailbox and shared memory @xcite are the two mechanisms , provided by xilinx .
out of these two mechanisms , shared memory is the most common and most intuitive way of passing information between processing subsystems and we have used it in our design .    a shared memory system has the following properties@xcite : + any processor can refer any location in the shared memory directly by some system call .
+ location of data in memory is transparent to the programmer .
data could be distributed across multiple processors , with the help of some proper api , data can be handled at program level .
+ a synchronization is a must for accessing the shared memory segment by some hardware / software protocol between the two processors .
+ shared memory is typically the fastest asynchronous mode of communication , especially when the information to be shared is large .
shared memory gives another approach of `` in - place '' message processing schemes .
shared memory can be built out of on - chip local memory like bram or on external memory like ddr sdram .
the region in which the shared data is stored is known as a critical region in operating system terminology . unless there is some sort of well - defined non - conflicting way in which each processor accesses the shared data , the multi core system can not work properly . a synchronization protocol or construct
is usually required to serialize accesses to the shared resource .
the xps mutex synchronization primitive is used in this work , which is provided by xilinx as a separate ip - core@xcite . when using shared memory as a method of data communication , the pseudo code should look like this to ensure proper synchronization , + _ /
* shared tasks * / _ + _ xmutex_lock ( ) ; _ + _ / * critical region - perform shared memory access * / _ + _ xmutex_unlock ( ) ; _ + by calling the _ xmutex_lock ( ) _ it must be ensured that one processor is accessing the critical region and other processor should not be allowed to access the same until _ xmutex_lock ( ) _ is called by that processor .
this section highlights the key components of our proposed design . at first
, we describe the processor that is used and then we brief the design innovations made to enhance the throughput .
the microblaze embedded processor soft core is a 32-bit reduced instruction set computer ( risc ) optimized for implementation in fpgas@xcite . as a soft - core processor , microblaze
is implemented entirely in the general - purpose memory and logic fabric of xilinx fpgas . the embedded development kit ( edk )
platform from xilinx has been used to build a complete processor system on fpga .      in a single processor architecture ,
the fpga receives the input via the rs-232 port through uart and then the input plaintext message is encrypted using ecc algorithm , which is running in the microblaze processor of the the fpga . after encryption ,
the cipher text is send back to the host pc and is seen in the hyper terminal using serial communication between the board and the pc .
figure [ single ] shows the flow of steps in the design .
processor working at 100mhz clock frequency is used to encrypt 8-bits of message using ecc .
scalar multiplication constitutes the main operation in ecc .
it is seen that the processor takes 19.01 msec to perform the total encryption . the resource utilized i.e. , the number of luts and slices required by the design as well as the power requirements are summarized in the table [ table : resource and power calculation ] .          after evaluating the performance of ecc in single processor architecture by using microblaze soft - core processor ,
another approach is taken to implement it in dual processor architecture by considering the fact discussed in section  [ mps ] for higher throughput and efficiency .
xilinx virtex4 ml403 is taken as a platform for design .
shared memory is used for creating a handshaking between the two processors as described in section  [ shared ] and the synchronization for communication is achieved using the process described in section  [ sync ] .
[ dual ] shows the architecture of dual microblaze design ,        in addition , multiple port memory controller ( ddr_sdram ) and inter - processor communication - xps mutex hardware ip @xcite is also incorporated in the test bed to facilitate the memory sharing and inter processor synchronization and communication .    in the experiment ,
the two processors are equally engaged to execute ecc in parallel fashion and in between the consequent steps , the two processors communicate with each other via shared memory with proper synchronization .
the message to be encrypted is transferred to the fpga from a computer using rs232 serial port communication .
the two multiplications are executed concurrently in two processors and the resulting data is assembled in the shared memory .
the addition operation is then performed by the 1st processor and the resultant cipher text is generated .
the resultant cipher text is send back to the pc using the rs232 interface and is viewed at the hyper terminal of the computer .
[ dual - mb ] shows the mechanism in which the two processors communicate using the shared memory and using mutex locking and unlocking .
it is seen that the encryption engine speeds up by 3.3 times as the proposed architecture takes only 5.72 msec to perform the encryption.the resource estimation , power required and throughput measurements for both the designs are shown in table [ table : throughput calculation ] and table [ table : resource and power calculation ] below . the design improves the throughput of execution , but utilizes more resources due to the dual cores .
it is to be noted here that the throughput of the design can be improved further by enabling the cache memory . but due to the resource constraints of our implementation board the cache memory of the two processors
could not be enabled .
.for an encryption process [ cols="^,^,^,^,^ " , ]     [ table : resource and power calculation ]
this work is an exploration of ecc implementation for fpga based embedded systems .
two specific designs have been addressed , the first one is simpler involving a single microblaze core whereas the other one utilizes two microblaze cores and thus enables multi - threading .
the dual core based implementation gives almost a 3 times increase in the throughput but utilizes almost twice the resource and 30% more power as compared to the single core based implementation .
this clearly shows a trade off between speed , resource utilization and power requirement . in future
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cryptographic algorithms are computationally costly and the challenge is more if we need to execute them in resource constrained embedded systems . field programmable gate arrays ( fpgas ) having programmable logic devices and processing cores , have proven to be highly feasible implementation platforms for embedded systems providing lesser design time and reconfigurability . 
 design parameters like throughput , resource utilization and power requirements are the key issues . 
 the popular elliptic curve cryptography ( ecc ) , which is superior over other public - key crypto - systems like rsa in many ways , such as providing greater security for a smaller key size , is chosen in this work and the possibilities of its implementation in fpga based embedded systems for both single and dual processor core architectures involving task parallelization have been explored . 
 this exploration , which is first of its kind considering the other existing works , is a needed activity for evaluating the best possible architectural environment for ecc implementation on fpga ( virtex4 xc4vfx12 , ff668 , -10 ) based embedded platform .    
 fpga , ecc , single - core , dual - core , microblaze , shared memory