You are presented with multiple paper abstracts, alongside the associated literature review and chapter titles. Given the provided information, you are going to do a literature review. Please generate a coherent literature review that synthesizes the content, draws connections between different works, highlights major findings, and identifies any gaps in the existing research.

Literature Review Title: Advances in Photonic Packet Switching: An Overview 
Chapter Title:  Optical Buffering 
1. Abstract of Cited Paper (BIB001):  An architecture and implementation issues for an almost-all-optical packet switch that does not rely on recirculating loops for storage implementation are presented. The architecture is based on two rearrangeably nonblocking stages interconnected by optical delay lines with different amounts of delay. The probability of loss and the switch latency as a function of link utilization and of the size of the switch are investigated. In general, with proper setting of the number of delay lines, the switch can achieve an arbitrarily low probability of loss. Growability patterns and extension of the design to the dense wavelength-division-multiplexing (WDM) case are also shown. In particular, an extension to the architecture whereby, through the use of WDM, the switch capability can be increased several times, with only minor changes to the switch design is discussed. Additionally, issues involving practical implementation of such a switch are considered. For example, a scheme that allows optical packet synchronization for the synchronously-operated switch is shown. Using this scheme, the switch can be a central component in the design of future all-optical, packet-switched networks. > 
2. Abstract of Cited Paper (BIB002):  The implementation of optical packet-switched networks requires that the problems of resource contention, signalling and local and global synchronization be resolved. A possible optical solution to resource contention is based on the use of switching matrices suitably connected with optical delay lines. Signalling could be dealt with using subcarrier multiplexing of packet headers. Synchronization could take advantage of clock tone multiplexing techniques, digital processing for ultra-fast clock recovery, and new distributed techniques for global packet-slot alignment. To explore the practical feasibility and effectiveness of these key techniques, a consortium was formed among the University of Massachusetts, Stanford University, and GTE Laboratories. The consortium, funded by ARPA, has three main goals: investigating networking issues involved in optical contention resolution (University of Massachusetts), constructing an experimental contention-resolution optical (CRO) device (GTE Laboratories), and building a packet-switched optical network prototype employing a CRO and novel signaling/synchronization techniques (Stanford University). This paper describes the details of the project and provides an overview of the main results obtained so far. 
3. Abstract of Cited Paper (BIB003):  Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic.

Literature Review:
In electronic switches, contention is usually resolved by store-and-forward technique, which means the packets in contention are stored in a queue and sent out one by one. This is possible because of the available random access memory (RAM). In an optical switch we have to take a different approach because there is no ready-to-use random access optical memory. The main difference between electronic RAM and optical buffer is that optical buffers must be implemented with delay-lines, which are fixed length fibers. Once a packet has entered the fiber, it must emerge from the other end after a fixed amount of time; there is no way to retrieve the packet any time earlier (except for recirculation fiber loops, which will be discussed later.) There are various designs of node architecture applying optical buffer and there are different ways to categorizing them. One way is to compare them to the buffering in electronic switches (input, output, shared and recirculating buffering). There is a simpler, more direct way to categorize them: in general the optical buffer can be categorized into single-stage or multi-stage, forward or feedback. (A stage is a single continuous piece of delay-line.) We will not look at multi-stage feedback buffering since it is seldom proposed. The first example, proposed in the European ACTS KEOPS (Keys to Optical Packet Switching), is a broadcast and select space switch using single-stage forward buffering scheme as contention resolution (Fig. 7) . The wavelength converters encode the packet streams entering each input; therefore the packets on each input are distinguished by a separate wavelength. The streams are then combined by a multiplexer and distributed to k groups of delay-lines of different lengths, which give the packets necessary delays to resolve contention. By means of semiconductor optical amplifier (SOA) gates and passive couplers, each output port is able to select the packets with proper delays. At the final stage, the demultiplexer, SOA gates and multiplexer can select one packet from a specific input port. In this architecture there is only one stage of buffer and each delay-line feeds forward to the next part of the switch. Since each packet is broadcast to all delay-lines and every output port, it is possible to offer broadcast operation and packet priorities. The drawback is the use of a great number of components and controls, which considerably increases the cost. For example, it needs n wavelength converters, n×k+n 2 SOA gates and 2n+1 multiplexers / demultiplexers. The second example is the Shared-Memory Optical Packet (SMOP) Switch BIB001 , which belongs to the single-stage feedback category. It is very straightforward to see how the switch works from Fig. 8 . The lengths of the delay-lines could be 1, 2, 3,…, m packet duration. The (n+m)x(n+m) space switch can switch a packet either directly to an output port or to one of the delay-lines, according to how much delay the packet needs. Delay-lines of length greater than one packet duration greatly reduce the number of recirculation loops needed, resulting in the reduced need for amplifiers and, therefore, less noise. This scheme also allows packet priorities since a lower priority packet may be preempted by being sent to another circulation. Since the number of recirculations a packet is to take is unpredictable, some packets could suffer more power loss than others, making optical amplification necessary. This will inevitably introduce additional signal to noise ratio degradation to the recirculating packets. Another case of single-stage feedback optical buffering is the Fiber Loop Memory Switch concept introduced in the research and development in advanced communications in Europe (RACE), asynchronous transfer mode optical switching (ATMOS) project, as shown in Fig. 9 . The buffer is based on a fiber loop delay-line containing multiple wavelength channels. When contention occurs, the input packet is converted to one of the available wavelengths in the loop and kept circulating by activating the corresponding passive fixed filter (i.e., by turning on the related SOA gate). At the input of the loop, half of the power enters the loop, and the other half goes toward the outputs through the passive coupler. When the contention is resolved, the packet is switched to the destination link by the proper tuning of the corresponding output tunable filter. At the same time the passive filter in the loop is turned off to erase the packet in the buffer. It is possible for incoming packets to preempt those that are already waiting; hence this type of switch can implement packet priorities. For multistage feed-forward buffering examples, several node architectures applying cascaded 2x2 switching elements containing optical buffer  have been proposed (Fig. 10) . Each of these switching elements provides buffering of one or more packet duration delays in case of contention. A larger switch fabric can be constructed by cascading a number of these 2x2 elements in, for example, Banyan configuration. There are various designs of optical buffering, such as the staggering switch BIB002 , Switched Fiber DelayLines (SDL) (CORD: Contention Resolution by Delay Lines) BIB003 , Switch with Large Optical Buffers (SLOB) BIB004 , etc. Packet loss rate, network latency, hardware cost, control circuit complexity, packet reordering are among the many important issues to be considered in the design, which depends on the network specification, i.e., network dimension, topology, traffic load and pattern, etc.