You are presented with multiple paper abstracts, alongside the associated literature review and chapter titles. Given the provided information, you are going to do a literature review. Please generate a coherent literature review that synthesizes the content, draws connections between different works, highlights major findings, and identifies any gaps in the existing research.

Literature Review Title: Catastrophic failure and fault-tolerant design of IGBT power electronic converters - an overview 
Chapter Title:  2) Static/ dynamic latch-up. 
1. Abstract of Cited Paper (BIB001):  The semiconductor structure of bipolar transistors can cause failures by second breakdown. Also power MOSFETs and new semiconductor devices like IGBTs with a parasitic npn-structure may be damaged by this mechanism. First generation IGBTs with a parasitic thyristor inside the device are susceptible to the phenomenon of latch-up. Advances in technology improve the device characteristics. Modern IGBTs seem to show no latch-up despite the existing parasitic thyristor in their structure. This paper gives a short discussion of latch-up and second breakdown phenomena. IGBT of different semiconductor generations during latch-up under various conditions were investigated. A test circuit for these measurements is proposed. > 
2. Abstract of Cited Paper (BIB002):  Simulation studies on dynamic avalanche exhibit self-extinguishing current filaments which move across the device. In spite of high current densities, there is no indication for subsequent latching. High power densities will probably result in high local transient temperatures and device failure. The benefit of prolonged channel current during turn-off is obviously due to suppression of current filaments. 
3. Abstract of Cited Paper (BIB003):  A number of experiments show that IGBTs have some non thermal destruction modes, which are similar to secondary breakdown in bipolar transistors. These are destruction just after turn-on, during the turn-off process in short circuit operation and during the turn-off process in an L-load operation. In this paper, the author reproduces the waves of the first and second destructions in isothermal transient simulations. In both cases, increasing the power supply voltage gradually, in a short circuit measurement, the pnp transistors in the IGBT would start to turn on, driven by electrons generated by impact ionization. Although this turn-on process has a positive feedback ability to increase the current, this current flows through a stray inductance (L/sub s/) and causes a voltage drop. So, an IGBT has an ability to sustain some current density at a certain V/sub CE/ originally. However, if there was a local area whose pnp transistor is easier to turn on than the other major part, its current would not cease to increase because the voltage drop due to L/sub s/ was mainly decided by the increasing ratio of the majority current. The local area would inevitably latch up in a very short time. An IGBT has no destruction mechanism which is characterized by a universal constant, such as 200 kW/cm/sup 2/ for npn bipolar transistors. Nevertheless, the destruction limit of IGBTs could be evaluated as the ultimate operating voltage in a quasi-stationary simulation. 
4. Abstract of Cited Paper (BIB004):  This paper will discuss the different principal short circuit failure modes of IGBTs focusing on the new Trench-/Field-Stop-IGBT device concept. Beside the short circuit robustness limitation regarding an over temperature destruction, a new failure mode, the so called short circuit current destruction mode, is described. Necessary design aspects for Trench-/Field-Stop devices resulting in a superior short circuit robustness at least as good as the well established Non Punch Through IGBTs - are derived and proved experimentally by extreme single (e.g. Tj=200/spl deg/C!) and repetitive short circuit pulse tests (e.g. 50.000 times). 
5. Abstract of Cited Paper (BIB005):  A new insulated gate bipolar transistor (IGBT) model developed on a physical basis is presented. The Lumped-Charge method has been revised in order to point out a more general methodology for implementing the model into a circuit form. As an example, a version of the model for the popular PSPICE simulator is presented. The N-channel IGBT structure is described by means of an evolution of the PSPICE level-1 metal oxide semiconductor field effect transistor model. An accurate mobility model has been included to precisely predict the voltage drop in the ON state. Simulation results agree well with the experiments both in static and in switching operations. The comparison between the proposed and the native IGBT PSPICE model shows the better behavior of the former. The reasons for this result have been verified by means of two-dimensional MEDICI simulations. Moreover, the proposed model is able to predict the device behavior also in critical operations like its latchup during a turn-off under short-circuit conditions. 
6. Abstract of Cited Paper (BIB006):  Short-circuit-failure energy of insulated gate bipolar transistors (IGBTs) is generally known to be constant, depending on the thermal capacity of the devices. However, apart from the intrinsic thermal-failure limit, a premature short-circuit failure was observed for 600-V punchthrough (PT) IGBTs at turn-off transition. The observed failure seems irrelevant to the electrical-failure mode as well as the thermal-failure mode, rather, it depends on the dynamic-breakdown voltage of the device. In this paper, with comprehensive investigations into an instant short-circuit failure, it is shown that the observed short-circuit failure of the PT IGBTs results from insufficient avalanche capability, which is initiated by dynamic-avalanche breakdown and can severely degrade the short-circuit ruggedness of the PT IGBTs independent of the duration of the short-circuit event. 
7. Abstract of Cited Paper (BIB007):  A systematic methodology is developed in order to clarify the punch through trench insulated gate bipolar transistor (T-IGBT) failure mechanisms which can occur under extreme operating conditions such as short circuit and clamped inductive switching. By considering a 2D dimensional physically based device simulation, and by analyzing some T-IGBT physical parameters, it is possible to identify if the failure mechanism is due to a breakdown, a latchup or a thermal runaway phenomenon. 
8. Abstract of Cited Paper (BIB008):  Precursor parameters have been identified to enable development of a prognostic approach for insulated gate bipolar transistors (IGBT). The IGBT were subjected to thermal overstress tests using a transistor test board until device latch-up. The collector-emitter current, transistor case temperature, transient and steady state gate voltages, and transient and steady state collector-emitter voltages were monitored in-situ during the test. Pre- and post-aging characterization tests were performed on the IGBT. The aged parts were observed to have shifts in capacitance-voltage (C-V) measurements as a result of trapped charge in the gate oxide. The collector-emitter ON voltage VCE(ON) showed a reduction with aging. The reduction in the VCE(ON) was found to be correlated to die attach degradation, as observed by scanning acoustic microscopy (SAM) analysis. The collector-emitter voltage, and transistor turn-off time were observed to be precursor parameters to latch-up. The monitoring of these precursor parameters will enable the development of a prognostic methodology for IGBT failure. The prognostic methodology will involve trending precursor data, and using physics of failure models for prediction of the remaining useful life of these devices. 
9. Abstract of Cited Paper (BIB009):  In this paper, effects preceding a latch-up fault in insulated gate bipolar transistors (IGBTs) are studied. Primary failure modes associated with IGBT latch-up faults are reviewed. Precursors to latch-up, primarily an increase in turn-off time as a consequence of elevated junction temperature, are examined for an IGBT. The relationship between junction temperature and turn-off time is explained by modeling the parasitic properties of an IGBT. A metric is derived from the model to standardize the relative estimates in junction temperature from measurements of turn-off time. To evaluate the effects preceding latch-up in-situ, seeded fault testing is conducted on a three-phase power inverter using aged transistors induced with a fault located in the die-attach solder layer. Experimental results demonstrated the feasibility of using the proposed metric as a precursor to transistor latch-up.

Literature Review:
Latch-up is a condition where the collector current can no longer be controlled by the gate voltage. With respect to Fig. 3 , latch-up happens when the parasitic NPN transistor is turned on, and works together with the main PNP transistor as thyristor, and then the gate loses control of I C . IGBT latch-up can be divided into two types, static and dynamic latch-up  . Static latch-up happens at high collector currents, which turn on the parasitic NPN transistor by increasing the voltage drop across the parasitic resistance R S . Dynamic latch-up happens during switching transients, usually during turn-off, when the parasitic NPN transistor biased by the displacement current through junction capacitance C cb between the deep P+ region and the N-base region. There are two distinct conditions that may lead to dynamic latch-up BIB001 BIB002 BIB003 BIB004 BIB007 BIB006 . One is when the gate voltage drops very fast and induces excessive displacement current through the gate oxide that flows through the parasitic resistance. The other one is when the off-state collector-emitter voltage is quite high and induces excessive charging currents within the IGBT during the switching transient, which will flow through the parasitic resistance. Both conditions may trigger the parasitic NPN transistor and eventually lead to latch-up. It should be noticed that the collector current leading to dynamic latch-up is lower than that of static latch-up. When latch-up happens, IGBT will be almost inevitably damaged due to the loss of gate control, as confirmed by the 2D finite element simulations BIB010 BIB008 . Therefore, several methods are proposed to predict latch-up, especially based on the collector-emitter on-voltage V CE(on) and turn off time BIB010 BIB009 . It is worth mentioning, though, that latest-generation IGBTs with trench-gate structure and heavily doped P-base region under N-emitter, have been proved to have good latchup immunity BIB005 , and latch-up is not a common failure in the latest devices anymore.