You are presented with multiple paper abstracts, alongside the associated literature review and chapter titles. Given the provided information, you are going to do a literature review. Please generate a coherent literature review that synthesizes the content, draws connections between different works, highlights major findings, and identifies any gaps in the existing research.

Literature Review Title: Multi-Channel Neural Recording Implants: A Review 
Chapter Title:  Neural Recording Architectures 
1. Abstract of Cited Paper (BIB001):  We consider the problem of reconstructing a sparse signal x 0 2 R n from a limited number of linear measurements. Given m randomly selected samples of Ux 0 , where U is an orthonormal matrix, we show that ‘1 minimization recovers x 0 exactly when the number of measurements exceeds m Const ·µ 2 (U) ·S · logn, where S is the number of nonzero components in x 0 , and µ is the largest entry in U properly normalized: µ(U) = p n · maxk,j |Uk,j|. The smaller µ, the fewer samples needed. The result holds for “most” sparse signals x 0 supported on a fixed (but arbitrary) set T. Given T, if the sign of x 0 for each nonzero entry on T and the observed values of Ux 0 are drawn at random, the signal is recovered with overwhelming probability. Moreover, there is a sense in which this is nearly optimal since any method succeeding with the same probability would require just about this many samples. 
2. Abstract of Cited Paper (BIB002):  This article surveys the theory of compressive sampling, also known as compressed sensing or CS, a novel sensing/sampling paradigm that goes against the common wisdom in data acquisition. CS theory asserts that one can recover certain signals and images from far fewer samples or measurements than traditional methods use. To make this possible, CS relies on two principles: sparsity, which pertains to the signals of interest, and incoherence, which pertains to the sensing modality. ::: ::: Our intent in this article is to overview the basic CS theory that emerged in the works [1]–[3], present the key mathematical ideas underlying this theory, and survey a couple of important results in the field. Our goal is to explain CS as plainly as possible, and so our article is mainly of a tutorial nature. One of the charms of this theory is that it draws from various subdisciplines within the applied mathematical sciences, most notably probability theory. In this review, we have decided to highlight this aspect and especially the fact that randomness can — perhaps surprisingly — lead to very effective sensing mechanisms. We will also discuss significant implications, explain why CS is a concrete protocol for sensing and compressing data simultaneously (thus the name), and conclude our tour by reviewing important applications. 
3. Abstract of Cited Paper (BIB003):  An implantable microsystem capable of recording neural activity simultaneously on 64 channels is reported. This system receives power and setup data through an inductive wireless link, and wirelessly transmits the recorded neural information to an external interface. The microsystem is capable of detecting spike occurrences, as well as digitizing the spike waveforms on any channel with 8-bit resolution. Signals are amplified by 60 dB with a programmable bandwidth from < 100 Hz to 10 kHz. The input-referred noise is 8 muVrms. The channel scan rate for spike detection is 62.5 kS/s using a 2-MHz clock. The system dissipates 14.4 mW at 1.8 V, weighs 275 mg, and measures 1.4 cm times 1.55 cm. 
4. Abstract of Cited Paper (BIB004):  We present a multichip structure assembled with a medical-grade stainless-steel microelectrode array intended for neural recordings from multiple channels. The design features a mixed-signal integrated circuit (IC) that handles conditioning, digitization, and time-division multiplexing of neural signals, and a digital IC that provides control, bandwidth reduction, and data communications for telemetry toward a remote host. Bandwidth reduction is achieved through action potential detection and complete capture of waveforms by means of onchip data buffering. The adopted architecture uses high parallelism and low-power building blocks for safety and long-term implantability. Both ICs are fabricated in a CMOS 0.18-mum process and are subsequently mounted on the base of the microelectrode array. The chips are stacked according to a vertical integration approach for better compactness. The presented device integrates 16 channels, and is scalable to hundreds of recording channels. Its performance was validated on a testbench with synthetic neural signals. The proposed interface presents a power consumption of 138 muW per channel, a size of 2.30 mm2, and achieves a bandwidth reduction factor of up to 48 with typical recordings. 
5. Abstract of Cited Paper (BIB005):  We present an inductively powered 32-channel wireless integrated neural recording (WINeR) system-on-a-chip (SoC) to be ultimately used for one or more small freely behaving animals. The inductive powering is intended to relieve the animals from carrying bulky batteries used in other wireless systems, and enables long recording sessions. The WINeR system uses time-division multiplexing along with a novel power scheduling method that reduces the current in unused low-noise amplifiers (LNAs) to cut the total SoC power consumption. In addition, an on-chip high-efficiency active rectifier with optimized coils help improve the overall system power efficiency, which is controlled in a closed loop to supply stable power to the WINeR regardless of the coil displacements. The WINeR SoC has been implemented in a 0.5-μ m standard complementary metal-oxide semiconductor process, measuring 4.9×3.3 mm2 and consuming 5.85 mW at ±1.5 V when 12 out of 32 LNAs are active at any time by power scheduling. Measured input-referred noise for the entire system, including the receiver located at 1.2 m, is 4.95 μVrms in the 1 Hz~10 kHz range when the system is inductively powered with 7-cm separation between aligned coils. 
6. Abstract of Cited Paper (BIB006):  We present the design and implementation of linear-phase delay filters for ultra-low-power signal processing in neural recording implants. We use these filters as low-distortion delay elements along with an automatic biopotential detector to perform integral waveform extraction and efficient power management. The presented delay elements are realized employing continuous-time OTA-C filters featuring 9th-order equiripple transfer functions with constant group delay. Such analog delay enables processing neural waveforms with reduced overhead compared to a digital delay since it does not requires sampling and digitization. It uses an allpass transfer function for achieving wider constant-delay bandwidth than all-pole does. Two filters realizations are compared for implementing the delay element: the Cascaded structure and the Inverse follow-the-leader feedback filter. Their respective strengths and drawbacks are assessed by modeling parasitics and non-idealities of OTAs, and by transistor-level simulations. A budget of 200 nA is used in both filters. Experimental measurements with the chosen filter topology are presented and discussed. 
7. Abstract of Cited Paper (BIB007):  We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 μm CMOS intracranial EEG interface is presented. DC offset of up to ±50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are freely moving ratsshared among 56 channels resulting in 0.018 mm ::: 2 ::: effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 μV ::: rms ::: over the bandwidth of 1 Hz to 1 kHz. The 8.7 mm ::: 2 ::: chip dissipating 1.07 mW has been validated in vivo in online intracranial EEG monitoring in freely moving rats.

Literature Review:
The multi-channel neural recording implants are designed in three main architectures in the literature and are shown in Figure 1 . The most common architecture illustrated in Figure 1a exploits one analog to digital converter (ADC) that is shared among all channels. Each channel has a neural amplifier, and the neural signal of each channel is passed to the ADC through an analog multiplexer. The performance of this multiplexing method, which is also referred to as time division multiplexing (TDM) method in analog domain, becomes limited when the number of channels increase dramatically. In order to improve the neural recording spatial resolution, the number of channels increase. This results in a higher sampling frequency of the ADC and the multiplexer which in turn increases the power consumption of the ADC and the driving buffers. Since analog signals are more prone to distortion due to cross-talk noise in analog multiplexers compared to digital signals, careful design considerations have to be accounted for the design process. An example of this design is presented in BIB004 . The architecture shown in Figure 1b utilizes one ADC for each channel. Due to the low bandwidth of neural signals, the sampling frequency and the power consumption of the ADCs are low. In this architecture, a digital multiplexer is used, unlike the previous architecture, where an analog multiplexer is used. The main advantage of utilizing a digital multiplexer is that the power-consuming buffers and ADC drivers are avoided, and the inter-channel cross-talk noise is eliminated. This is due to the fact that digital signals have high noise margins and are more stable, compared to analog signals against cross-talk and other noises. However, this architecture has higher numbers of ADCs and, consequently, consumes a higher area and power consumption. Therefore, area and power reduction techniques should be applied in the design process. This architecture is shown in BIB005 . In the third architecture, unlike the other two architectures in which there is one ADC for all the channels or one ADC for each channel, one ADC is shared among multiple channels. Figure 1c shows the block diagram of this architecture, where there are m rows and n columns. As shown in this figure, one ADC is assigned to each column with m rows through an analog multiplexer. Since these multiplexers are smaller compared to the first architecture, the design considerations to avoid cross-talk is less challenging. As another advantage of this architecture, since the number of ADCs are dependent on the number of columns (n), choosing an appropriate value for n results in minimum value of the power consumption and the area, especially when the total number of the channels is very high. Therefore, as a solution for the large-scale recordings, the architecture of Figure 1c is the best option. This architecture is presented in BIB008 . In addition to these main architectures, other non-popular architectures are reported in the literature where no ADC is involved. As an example, in BIB006 , the analog signals are converted to time duration using the pulse width modulation (PWM) technique and transmitted to the outside of the body. Increasing the number of channels in order to increase the spatial resolution is desirable, however, it increases the output data rate and the power consumption especially in the transmitter. In order to decrease the data rate, researchers have proposed different methods to compress the data. One of the main methods to compress the data that is utilized in neural extracellular activities is done in the time domain. In this method, only the APs are detected and transferred out of the body. Since the duty cycle of this method is in the range of 2% to 20%, the data can be compressed by a maximum factor of 50 BIB005 BIB007 . This method is applicable in both digital and analog domains. Another compression method that is used in both analog and digital domains is compressive sensing (CS). This method is simple in its implementation and efficient in compression and is suitable for neural signals, especially iEEG. In this method, instead of sending all N samples of the neural signal of each channel, an M linear combination of these samples are sent where M is less than N BIB001 BIB003 BIB002 . The compression blocks can be implemented in analog in points A1 and A2 or can be implemented digitally in points D1 and D2 in various architectures of Figure 1 . In Section 6, we explore the compression methods and their challenges in more detail. In the following sections, we probe the main blocks of these architectures and their challenges.