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Controversial BU Biolab Faces Environmental and Security Review
Reinventing T-Mobile's Security Function
Bioterrorism Alerts: Immune Systems
Three Ways to Keep the Dream Alive
Front and Center: Security at Boston's Infectious Disease Research Lab
When controversy hit, Kevin Tuohey became the public face of a high-profile plan to study deadly diseases in Boston. To succeed, the security director would have to become part diplomat, part great communicator.
By Scott Berinato
CSO |
Kevin Tuohey is the executive director of operations and safety at Boston University Medical Center, a job that includes security responsibilities and, he declares, "anything to do with risk." That includes expected tasks like access control and surveillance, managed from an operations center on the BU Medical Center campus. Through bulletproof glass, the ops center looks across Albany Street at the hospital, where Tuohey takes care of triply redundant utilities that keep critical medical systems online. On one side of the ops center sits security staff. On the other side, separated by a glass wall, sits the safety team. On a campus with a busy hospital and research facilities, safety and public health risks are on par with security risks. A public health risk he deals with is the potential release from research labs of infectious agents such as Francisella tularensis.
One micron long, F. tularensis is a small bacterium. But it can survive months in below-freezing temperatures, and 10 microbes will infect humans with a disease called tularemia. Historically, outbreaks were associated with rodent hunters who got sick from carcasses of their prey, giving tularemia its familiar name: rabbit fever.
The most virulent rabbit fever strain, pneumatic tularemia, is capable of airborne transmission. Antibiotics suppress the fever, but left untreated, it can kill. (Because early symptoms are flulike, some people will try to tough out what feels like a nasty cold.)
Outbreaks occur sporadically across the Northern Hemisphere. One took place on the Massachusetts island Martha's Vineyard in 2000, when landscapers mowed over an infected rabbit and aerosolized the bacteria, giving 15 people the fever, one of whom didn't seek treatment right away. He later died.
The Centers for Disease Control and Prevention classifies pneumatic tularemia as a "Category A" infectious agent&mdash:a potential biological weapon that the government monitors and that universities research to prevent wider epidemics.
At Boston University Medical Center, Dr. Peter Rice was researching a vaccine for tularemia. In May 2004, one researcher in his lab went to the doctor's office with a fever, cough and headache. Two days later, a second researcher from the lab felt similar but more severe symptoms and was hospitalized overnight. Both were diagnosed with the flu, given antibiotics and recovered. In September, a third researcher from the same lab landed in the hospital for several days with more severe flulike symptoms. This time, someone put one and one and one together. For the vaccine research, all three had worked with what was supposed to be a harmless strain of F. tularensis.
By the end of October, scientists determined that the bacteria strains delivered to Rice's lab, thought to be inert, were actually virulent. Over the next two weeks, the medical center's Institutional Biosafety Committee, where Tuohey's manager of emergency planning holds a seat, shuttered Dr. Rice's lab, notified the Massachusetts Department of Public Health, the Boston Public Health Commission and the mayor of Boston, and finally confirmed with blood tests that the researchers had contracted pneumonic tularemia.
It was Nov. 12, 2004, almost six months after the first researcher contracted rabbit fever. The information had been kept confidential because the local health officials and BU Medical Center determined there was no threat to public health. Now the public would find out. And for Tuohey, the timing couldn't have been worse.
That's because the medical center was in the process of getting approval to build a new infectious disease research lab on campus. In 2003, the National Institute of Allergy and Infectious Diseases (NIAID) awarded a $128 million grant to build the lab, which if approved by state and federal environmental agencies, would bring billions in grants and attract top scientists.
But the new facility would also be classified a Biosafety Level 4 lab, one of only seven in the United States. In lab safety terms, level 4 means the biologics handled at that facility have no known vaccine or therapy. No cure. Ebola. Smallpox. Anthrax. (Level 3 biologics can cause disease if inhaled, but there are treatments available. Level 2 agents can cause disease but are not transmitted in a lab. Level 1 is not harmful.)
The live strains of F. tularensis that infected BU Medical Center researchers are Biosafety Level 3 agents. Those who opposed building the biolab seized on the rabbit fever cases as Exhibit A in their grassroots fight to stop the project, evidence that the center was incapable of protecting the surrounding neighborhoods from potentially deadly outbreaks.
A CSO Steps Front and Center
As an operations director, Tuohey initially had a limited role when a public controversy struck his organization's most important project. All he could do was explain the building design, systems and processes that BU Medical Center would use&mdash:most mandated by regulators&mdash:to prevent failures at the new lab. He also could point to his team's operations center, and the redundant systems and all of the new high-end security controls like advanced surveillance and biometrics that would protect the facility.
Tuohey did all that. But soon he did more. Tuohey knew it would fall to him to defend the new lab and quell a chorus of dissent coming from a well-organized alliance of citizens and scientists who categorically opposed the lab. Despite the tularemia episode, Tuohey had to tell them that the security and safety risks associated with this new lab were fringe risks, and manageable. And tell them he did. By the time the news of the three rabbit fever infections reached the public, Tuohey was making himself a public face for BU Medical Center. Ever since the center won the federal grant to build the bioresearch lab, Tuohey had moved beyond his normal focus as strategic security and safety director. He had testified at public hearings, briefed politicians, talked to the media and met regularly with community groups. His role became a community outreach and communications job too.
It's a leadership role more security executives are playing as issues of risk migrate to a central place in our politics and culture. Security leaders will find themselves in Tuohey's position, tackling outward-facing roles, meeting with key constituents, testifying in hearings and speaking to the media.
Hemanshu Nigam, for example, was named CSO at MySpace.com in April partly to assuage parents unsettled by media reports of online predators associated with the site. Nigam's background was in consumer security outreach. And during the recent controversy over a Dubai-based company taking over management of some U.S. ports, analysis that shaped public opinion came from security experts like Stephen E. Flynn, a Council on Foreign Relations fellow, Graham Kee of the Vancouver Port Authority and Dennis Treece of Massport.
At BU Medical Center, the response to the rabbit fever outbreak had the medical center leaning on Tuohey to fulfill this new kind of role. "This will be a huge blow," Tuohey remembers thinking as he anticipated the public's response to the rabbit fever cases. "It will take a lot of time and effort to explain factually. I was prepared for a lot of, See! See! We told you!"
The medical center wanted him right in front of it all. "Early on, we didn't always bring Kevin with us to meetings," says Ellen Berlin, BU Medical Center's director of corporate communications. "But we found the issues that gave people angst were Kevin's issues. And he is a natural. In many ways, Kevin is the face of the project."
The Site of a New Lab
A chain-link fence wrapped with green fabric surrounds the site on Albany Street, between Boston's South End and Roxbury neighborhoods, where the Biosafety Level 4 lab will rise. Tuohey stops at a gap in the fence and, opening his arms to the controversial plot, says, "Here it is."
His tone borders on apology, for the site on this brisk April morning is just an old vacant parking lot. It's an unremarkable urban blot, a typo in the neighborhood sentence.
But the site itself isn't the point. It's the process for picking this place to build a biolab. Biosafety Level 4s are like nuclear power plants. They are rare, most people at least can understand an argument for their existence and necessity, but no one wants them nearby because of their risks.
This site's backyard is Boston's gentrifying South End and, farther down, the Roxbury section. More than 50,000 people work and live within a few square miles, and a million people are within 10 square miles. Some residents live just yards away, across Albany Street, in rows of rejuvenated brownstones. To the site's south is a county jail and a half-built parking garage. The sprawling Boston Flower Exchange cooperative of wholesale florists borders on the east. Beyond that runs the Southeast Expressway, one of the busiest highways in the United States.
Remarkably, the notion that bringing anthrax and other incurable biologics into this bustling, densely populated setting might upset the neighbors initially seemed to escape BU Medical Center officials, who assumed it would rise on their campus, in "BioSquare" with existing research facilities and the hospital nearby. Federal officials "believed like us that these are safe facilities no matter where they are," Tuohey says, recalling the two-year-plus application process, when BU officials were focused much more on the science that would go on inside the facility than they were on the risks the building brought to the neighborhood. "Location is just one of many criteria that go into the application process. If you want the grant you have to meet National Institutes for Health standards on everything, including security and siting." From a security and safety perspective, the Albany Street site has advantages, Tuohey says. "People didn't put together that an infectious disease outbreak response will come here"&mdash:he points toward the hospital&mdash:"no matter where it originates. It's good to be close."
The Plan's Awful Debut
An air of inevitability surrounded the biolab. Besides the federal grant, state and city elected leaders backed the project for the jobs it would bring to Boston. Then came the first community meeting about the facility, held in January 2003 at the hospital and led by one of the lab's champions, a microbiologist named Dr. Mark Klempner. He began explaining, with some enthusiasm, the scientific research that would be done in the new facility and what he hoped that would produce&mdash:vaccines and therapies to combat natural epidemics and used as defenses against bioweapons. (It is illegal under international treaty to do bioweapons research, but not biodefense research.)
But a significant klatch of attendees from surrounding neighborhoods grew restless and irritated listening to Klempner. They wound up challenging him. They accused him of being patronizing and out of touch with their concerns. They demanded to know why they weren't involved earlier in the approval process for such a facility. They asked how Boston University could assume everyone would be OK with a "bioterror" lab in their neighborhood. The international Sars epidemic, having crested six months earlier, was no doubt fresh in their minds, and the anthrax attacks of 2001 probably weren't forgotten either. Questions about a "weapons factory" came up.
Officials for BU Medical Center appeared surprised by the tenor of these responses. They saw the biolab as a boon, producing construction and research jobs, and a dose of national prestige. Instead, according to a Boston Globe story, Klempner was seen as "condescending" and "evasive."
Tuohey's comments about this public relations disaster suggest that he understood the reactions. "They said, basically, Stop talking down to us. We don't care about the science. Make it safe.' We were focused on the potential outcomes from this lab; they were focused on potential risks. It was then I realized our perceived concerns were much, much different than theirs."
BU Medical Center clearly needed a new front man. Enter Tuohey. He was approachable, human. He maintained eye contact without staring. His voice was calm but strong, and he responded to the harshest attacks with polite replies. But most of all, as director of "anything to do with risk," Tuohey could address citizens' most urgent concerns. And so BU Medical Center, and those opposing this big lab project, looked to him to do that.
Tuohey Gets Going
In the 90 days following that initial community gathering, Tuohey held about 100 meetings with citizen groups, politicians and scientists. Meetings usually had a couple dozen attendees. He had a presentation outlining the basic security and safety issues at hand, but for the most part, his job was to listen. After a while, it seemed like every question had been asked, including, Tuohey recalls, if there would be snipers on the roof (no), if the lab was designed to withstand an earthquake (yes) and if the building would be fortress-ugly (no). When he didn't know the answer, he said so. "I said, I'm not going to tell you I'm the smartest guy, but I will research it. I will use all the resources I can to find an answer.'"
Microsoft's very bad year for security: A timeline


When you think of STIHL, you think of old-world care and concern – the handcrafted work of skilled artisans from times past. It is an attitude, a dedication to quality that has made STIHL power tools the most dependable on the market for over 70 years.
Along with STIHL's commitment to achieving the ultimate in product performance and dependability comes a long history of distributing products exclusively through servicing dealers.
Astro Rents can also tell you where and how to use these products. Remember, any power tool, when used improperly, can be dangerous. Protective clothing, including protective glasses, should be worn when operating power tools. Be sure to read and follow the operating instructions in your owner's manual.
Multi Quip-Plate Tampers, Jumpin Jacks, etc.
Target Tile Saws, Road Saws, Diamond Blades, etc.
Whiteman Concrete & Mortar Mixers, etc.


Below is the progress of the new Out of Order CPU micro-architecture based on the new TIP Dynamic Instruction Scheduling Algorithm.
Latest Block Diagrams are shown below. I first began thinking about this design on Mar 2, 2016.
cpu_params_RV.svh localparams determined by RV_params. These should not be changed.
alu_core_RV.sv Logical functions, add, subtract, etc. logic.
arch_reg_dep.sv Architectural Register Dependency logic. The whole reason this project was created was to test this logic which creates a new Dynamic Instruction Scheduling algorithm!
decode_core_RV.sv Decode logic for RV32IMC instructions.
fu.sv Dispatches instructions to appropriate functional unit.
gpr.sv CPU architectural register read/write logic. The commit stage writes to this architectural register set.
kpu_core.sv Top level module of the cpu. Ties all CPU design related modules together.
rs.sv Reservation Stations (not similar to any known RS). This is a circular bin of instruction information, stored in instructions order. This module keeps track of all instructions and whether they are ready to start execution. Instructions can execute out of order by going to the appropriate functional unit and the results come back into the appropriate bin (still in order). This module also determines Load/Store address dependencies and whe Load/Store instrucitons may execute. Dependency control logic is now integrated into this module.
update_ib.sv Update Instruction Bins logic. Data in bins is updated by various modules sending data/ctrl logic to this module.
disasm.sv Used for debugging. It displays RV32IMC instructions in assembly language format in ModelSim simulation waveforms.
April 4, 2019: Load/Store updates/fixes, CSR, interrupts, and memory decoding improvements. Code is starting to run. Currently adding multi-ported L1 D$ so that more than 1 L/S can occur. Initially, any Read Hit will respond for any port. This change involves CPU and L1 D$ logic.
Nov 16, 2018: Working on creating various CSRs and interrupt logic. Also added logic to the L1 Instruction Cache related to the incoming cache line data. Multiple instructions per cache line are predecoded to determine which ones are branches and the type of branch. This extra data is saved in the cache for use by new Fetch logic. Looking at a new branch method for Fetch logic which will affect the RS.sv module.
June 13, 2018: Rework of design to simplify/reduce the amount of logic by creating a new "Reservation Station" While the RS can execute instructions Out of Order, it mantains and commits the instructions In Order. Due to the new algorithm, no register renaming is needed and only architectural registers are needed.
May 27, 2018: Some work on the L1 Data Cache. Written for single port input/output. It appears to be working for a single port design. Next goal is to try to create a multi-port design. Still busy with my contract work which will end by the beginning of July 2018.
Nov 2017 - Present: Most all interns busy with college work and I took a short term contract to do some Clock Domain Crossing, Reset Domain Crossing and Re-convergencve debugging/fixing of a system in Redmond, WA. Hope to be back full time on this project by mid to late Spring.
Aug-Sept 2017: Guiding and helping volunteer interns, under NDA, working on various projects to support the design and debug of the CPU. No one has info or access to the critical sections of code related to the TIP algorithm (dependency_control.sv and ls_dependency_control.sv) due to it not being patented yet.
July 2017: Decided to get some help. Setting up projects for various engineers to work on relate to this CPU.
June 2, 2017: Debugging new logic related to changes in pool.v and ls_process.v Also debugging ROB and COMMIT stages.
May 15, 2017: Debugging instruction flow through the various stages. Fixes to decoding, disassemble, and the dependency control so far.
May 11, 2017: Debugging RISC-V instructions/disassembler. Created a new Load/Store Process diagram. Added a 32x32 integer multiplier and logic to the ALU for various integer multiply instructions.
Apr 27, 2017: Decided to change from using the ARMv7 ISA to the RISC-V ISA for this new microarchitecture. It will be simpler to implement. Working to implement the RV32I for now.
Apr 19, 2017: Worked on new block diagrams and updates to the PPT presentation.
Apr 17, 2017: Worked on writing lsrs.v and corrected other files under ls_process.v so they all now compile without errors. Stilll need to debug L/S Process block (ls_process.v and all under it). I've also been taking a look at the RISC-V. It looks very interesting and would simplify the design (compared to using this ARM ISA I'm currently using). I will most likely target my new architecture to the RISC-V ISA someday.
Apr 13, 2017: Most of ls_queue.v and ls_dependency_control.v are written and ready to start debuging. Code for the Pool of Functional Units was removed from kpu_oooe.v and put in its own module as well as cleaned up a bit. Modified Pool block diagram and created new LS Process block diagram.
Apr 11, 2017: Redesign of Pool of Functioanl Units and L/S instructions process.
Mar 27, 2017: The following diagram for the Pool of Functional Units reflects the architecture needed for an ARMv7 type ISA where the address is not known (i.e. calculated) until inside the Load/Store Functional Unit. Once the L/S address is known, the information from all Load/Store Functional Units are fed into the L/S Dependency Control. This module caluclates address dependencies in a similar way that the Dependency Control module calculates register dependencies. Output data from the L/S Dependency Control module is placed into an available Load/Store Reservation Stations (LSRS). These reservation stations hold the instruction from starting a load or store from/to memory until all dependencies are satisfied, much like the Linked List Reservation Stations do for the architectural registers. Once a Load/Store instruction is released from an LSRS it can then start a Load or Store transfer from/to memory. The instruction then passes on to the ROB and Commit units as do ALU type instructions. Also updates to the KPU design PowerPoint Presentation were made today. It's basically finished.
Mar 23, 2017: I think I've finally determined how I want to do Load/Store logic in this new architecture as well as how to do it for the ARMv7 ISA. The above Pool of Functional Units diagram will get changed soon to show the implementation as it would relate to the ARMv7 ISA. Load/Store address dependencies will get handled in a similar way as the register dependencies. ...stay tuned... Muhammad Moazam is on board now and will start createing testbenches for simulation for a new module I created called ls_cam_cache.v which will be used to hold load/store addresses and tags in a CAM (Content Addressable Memory) type manner.
Mar 20, 2017: Created a simplified block diagram of an example of the Pool of Functional Units. The actual POOL is determined by parameters that can be changed. The number of each type of Functional Unit can be changed.
Mar 10, 2017: Finished the basics of module ls_cam_cache.v. Now it needs debugged before adding the final bit of code it needs. Engineer Muhammad Moazam has volunteered to help do some debugging in exchange for the experience.
Feb 28, 2017: Temporarily sidetracked since the 16th with another project I have to finish up.
Feb 16, 2017: Conversion to System Verilog mostly complete and simulations working again. Separated ROB/COMMIT code and fixed a couple bugs due to both being together in the same module.
Right click on the pic and save or open in a new tab to see the full resolution.
Feb 7, 2017: Nearing completion of writing code for the Load/Store logic. Need to create an L1 cache that will interface to the Load/Store logic.
Jan 29, 2017: Updated the PPTX presentation. Worked on a new Load/Store logic. This will soon be integrated into the last stage of the design.
Jan 16, 2016: Updates/fixes to forwarding logic has greatly improved IPC. For the test being used (186 instructions completed in 47 clocks, hardware ignoring branches & load/store instructions), the IPC is close to 4 for a 4 instruction wide issue. The LLRS queues are only averaging 1 or 2 instructions in them up until where the test has a lot of back to back load/store type instructions. This backup is at least partially due to no forwarding logic for load/store instructions yet. There may be some other instructions doing this too. Anyway, the forwarding logic currently implemented seems to be working much better. More work on the powerpoint presentation about this design.
Jan 10, 2016: To facilitate multiple micro-ops due to a single instruction, the microarchitecture has been changed to the following.
Jan 6, 2016: Spending time determining how to issue multiple micro-ops due to a single CPU instruction.
Jan 5, 2016: Spent time debugging/fixing commit.v logic and related ALU problems.
Jan 4, 2016: Found that I had a parameter that was wrong and some of the LLRS units where not getting data. Fixed it and now IPC = 256 instructions in 73 clocks = IPC of 3.5 for a 4 issue wide CPU. Still appears to be another problem slowing it down, but things are getting better. The simulation test used is a random wide variety of instructions with no Load/Store delay penalty and no branch delay penalty so the IPC should be VERY close to 4 for this 4 issue wide CPU simulation setup. Currently the L/S and branch instructions are decoded and processed up to the Functional Unit related to them, but they are basically discarded until I have time to work on them.
Jan 3, 2016: Register forwarding updates/fixes. Microcode table updates/fixes. However I'm only getting 258 instructions is 111 clocks = IPC of 2.3 for a 4 issue wide CPU. I can see where the problem lies. Just need to figure it out.
Jan 2, 2016: Basically finished with new integer multiplier section of the ALU. Here's a simple block diagram of what was implemented.
Updated Jan4. Right click on the pic and save or open in a new tab to see the full resolution.
Dec 30, 2016: Overhauling the integer multiplier section of the ALU to maximize resources and fix problems. Removed one of the multipiers. Only uses one 16x16 unsigned multiplier and one 32x32 unsigned mutiplier.I may post a block diagram here when finished.
Dec 28, 2016: Added more ARM Media instruction microcode, debugged various microcode. Fixes to transfer logic from LLRS to Functional Units. Added simulation debug code to arm_micro.v to abort sim if a certain invalid type of microcode is used (pulled from table). Found a few instances of this problem and corrected logic.
Dec 26, 2016: Created a Xilinx ISE project and compiled the Verilog modules to see if I had any RTL problems. A few things had to be changed to be synthesizable. Created a new simplified block diagram that is now in my PPT presentation.
Dec 23, 2016: Worked on the load/store functional unit (ls_functional_unit.v) and related logic in the whole system. Still have a chunk of logic related to Load/Store to go into the final Commit stage. Updated microcode table in arm_micro.v related to load/store instructions.
Dec 20, 2016: Worked on microcode table and logic for ARM "Extra load/store" instructions. Continued PPT presentation - 45 slides so far.
Dec 14, 2016: After months of having random booting issue after a poweron, my desktop computer finally died today :(. After trying to figure out the problem, I discovered the Power Supply voltages were all very low! Drove in the afternoon snowstorm to Fry's in Wilsonville, OR to get a new supply and put it in. Its working again and not having the boot issue. Started creating a powerpoint presentation about this new Out of Order Execution microarchitecture.
Dec 13, 2016: Started working on the Load/Store Functional Unit and microcode control logic. Fixed a couple issues with decode.v.
Dec 8, 2016: Added most of the ARM 32 bit Media Instructions to armv7_disasm.v.
Dec 6, 2016: Changed armv7_disasm.v. Changed the disassembler code to use SystemVerilog "string"s instead of a method with regular Verilog. It shortened the code a bit. Spent the day adding new instructions and debugging them. Still need to add Media instructions. Being able to SEE the instruction flow during simulation is a big help.
November 29 - Dec 5, 2016: Microcode table data fixes and improvements to the microcode state machine/instructions. Feedingvarious instructions to armv7_disasm.v and debugging them. I use the results to also check decode.v functionality. This will take a lot of time.
November 27, 2016: Bugs found and fixed. Got first 100 instructions executed in 31 clocks. Still needs more forwarding logic. The following pic shows the instruction flow in the ROB/Commit section using my ARM disassembler in the simulation. Right click on the pic and save or open in a new tab to see the full resolution.
November 24, 2016: Found out why the CPU appeared to be going very slow - no forwarding logic. Added one (of 3 I need to add) level of forwarding from the ALU Functional Units back to the LLRS stage. The commit.v now has a Reorder Buffer and then commit logic before data is written back to the architectural registers. Thus forwarding logic will get added for the ROB and the COMMIT stages once I get other debugging done.
November 20, 2016: Ran into a dependency algorithm problem. May take some time to figure this one out.
November 18, 2016: Anther fix to llrs.v to correct what happens when both a trasfer in and out of the module occur at the same time. Also some minor fixes to commit.v and kpu_oooe.v. Today was the first day that the first instruction made it all the way through the architecture. Unfortunately nothing else did... Debugging is going well.
November 17, 2016: Starting creating br_functional_unit.v so that branches dont get stuck in the llrs.v units while debugging. For now I'll just bring them into the br_functional_unit.v and pass them on to commit.v so they can be retired and not hold up data processing instrucutions I'm currently debugging.
November 16, 2016: more debugging of llrs.v (problems with adding/removing data in linked lists), dependency_control.v and just about to start debugging llrs.v - commit.v interactions.
November 10, 2016: Fixes to llrs.v logic. Looking much better now.
November 9, 2016: Working on DC - LLRS flow/control logic. Snapshot below (open in another tab to see full size) of the Dependency Control unit working on 4 instructions per clock. This can easily be changed to 8 ... 64... by changing 1 parameter. Similar changes to other modules have to be made.
November 7, 2016: Good debugging progress up to DC (Dependency Control). Also updates/fixes to debug_asm.v, which is renamed to armv7_disasm.v. Currently teh parameter determining the number of instructions per clock is set to 4. Most everything is parameterized so it can be easily changed. Things such as IPC, the number of LLRS units, instruction window length, the number of different types of functional units, etc.. This will make it easy to try different CPU design configurations later on.
November 4, 2016: Currently debugging debug_asm.v, fetch.v, etc.. Right click on the pic below and save it so you can see the full hi res pic. This shows the beginning of debugging instructions using the debug_asm.v module in a ModelSim simulation. If anyone is interested in helping debug this module and using it, contact me. You will need ModelSim and a tool such as IAR Workbench to compile code to generate assembly language to compare against ModelSim, and binary code (in hex format) that can be placed in a file that the simulation can read in.
November 2, 2016: Wrote simple testbench top_tb1.v and started the debugging process. Typical bugs like port size mismatches between modules, wire vs. reg usage on port signals, etc... Still more to debug before I can actually get the simulation (waveforms) running so I can debug the logic.
October 31, 2016: Added new ALU control bits to microcode ROM/RAM table and logic, added Multipliers and logic in alu_functional_unit.v, got logic completed for ARM Data Processing instruction flow from Fetch through Issue/Execute ready to begin debugging once I create a testbench.
October 18, 2016: For debugging purposes I am optionally passing the full 32 bit instruction through each stage. I'm creating a Verilog code module that can be used to disassemble the instructions at various locations and display in ModelSim the disassembled instructions as as ASCII string in the waveforms. This will greatly help watching the data flow.
October 13, 2016: Various code mods. Renamed Hazard Control to Dependency Control.
October 9, 2016: Got all but the ROB/commit module (not designed yet) to compile without errors. Next I'll start making testbenches for individual modules and the whole design.
October 5, 2016: It's started raining here in Oregon so I've been inside the last couple of days and made good progress and improvements on the Fetch, Decode&Tag, Hazard/Control, and LLRS sections shown above. I may rename some sections as this is a very different architect for Out of Order type CPUs. One important change to the above diagram is that there are now more LLRS blocks than the number of instructions Fetched per clock (Decodes too). The ROB/Commit section will be able to retire more instructions per clock (if available and can be done) than there will be instructions Fetched per clock. This will help improve IPC as some instructions may have to wait awhile (i.e. Loads, Stores,etc..) in the LLRS blocks before they are ready to be executed.
July 22, 2016: Finished initial design of the LLRS (Linked List Reservation Stations) module (llrs.v) and have most of the Reg. Rename (reg_rename.v) module written that will do register renaming logic for the new ARM OoOE cpu.
Decode & Tag - Instruction decoding and "tag" creation. The tag "magic" happens in LLRS and ROB/commit.
Reg. Rename - The number of physical registers is parameterized and can be changed to get the best performance per application. Currently it's set to 64. reg_rename.v keeps track, using a linked list, to which of the physical registers are the current architectural registers defined by the ISA.
LLRS - a new type of Linked List Reservation Station. The first CPU version will not be superscalar as shown above, but will be designed & parameterized so that it can become a superscalar. There are two linked lists that use a common pool of Reservation Stations. One linked list is "used" pool items and the other linked list is the "unused" pool items. Only 1 clock cycle is needed by the module due to the way the linked lists are maintained. The "used" linked list keeps ready instructions in order from oldest to youngest so that the oldest can be passed on to Issue/Execute first.
ROB/Commit can commit multiple (more than N) ready instructions per clock.
July 8, 2016: Worked more on a module that will be the equivalent of a reservation station for the new ARM OoOE cpu.
June 24, 2016: Slowly starting to work on the new ARM OoOE architect idea I have as time permits. Just completed writing a new module (A linked list type of Reservation Station) I will need to make sure is synthesizable and then simulate it. I finally found a patent (owned by QualComm) that may have some similarity to my design, but it doesn't have features my design method does.
April 2, 2016: Created a disassembler (for a portion of the ISA) to display the assembly language instructions during ModelSim simulations. Also looking at a another OoOE architect idea. However, I now have to do some other work for the next 2 - 3 months before I can continue on this project.
Mar 22, 2016: Just found out during simulation that my new OoOE architecture has a design problem. So back to the drawing board on that idea. Still working on a new architecture based on the ARM7-TDMI ISA.
Mar. 17, 2016: Decided to go with the ARMv7 ISA for this new Out of Order design. Even though my OoOE internals are very different than ARM's, I guess I can't release the CPU with this ISA. I also have some of the basic modules created and they finally, tonight, compile without errors. Currently setting up a test bench and top level to integrate all the current modules and begin debugging. First test will be just to get the basic flow working for all the Data Processing type instructions and see that my new style of logic works. I also setup IAR tools for ARM to generate binary code to use in my Verilog simulations.
Mar. 9, 2016: Modified ISA for both KPU55 and KPU_OoOE. Working on creating KPU_OoOE CPU with Branch Method 3. Modifications to DECODE stage so that it may be easy to change it to use microcode instead of brute force decoding for every instruction. It would also facilitate changing over to a different ISA - such as an ARM Cortex. The microcode method will reduce the amount of logic gates in the DECODE and thus reduce delays in the stage. Might be nice to show this CPU running on an ARM instruction set. Anyone have any suggestions?
Mar. 2, 2016: In researching how these branch methods may apply in OoOE processors, I've gotten sidetracked today with a new algorithm I came up with for OoOE that I believe is easier to implement than Tomasulo's. I've begun creating a new OoOE CPU to see if it's any good.


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Vitality Senior Living
Macomb Daily on Twitter
Macomb County Bicentennial
M-59 reconstruction project
President Barack Obama speaks to members of the media in the Oval Office of the White House in Washington, Monday, June 13, 2016. Obama said there's no clear evidence that the shooter at an Orlando nightclub was directed to conduct his attack or part of a larger plot. Pablo Martinez Monsivais-AP Photo.
Pablo Martinez Monsivais
Column: Needed: A declaration of war
By Cal Thomas Tribune Content Agency
Credit President Obama for finally using the words he has desperately tried to avoid during his presidency. He correctly called the mass shooting in an Orlando gay nightclub Sunday morning, which killed 49 and injured 53, 'an act of terror.' It was, writes The New York Times, the 'deadliest attack on a gay target in the nation's history.'
Discredit to the president for avoiding linking the attack to ISIS and Islamic terrorism, even though the shooter, Omar Mateen, reportedly called 911 during the rampage and 'pledged loyalty to the Islamic State.' Jihadists everywhere quickly celebrated the carnage on the internet and, reports israelnationalnews.com, '...the al-Amaq agency - which functions as ISIS's propaganda and media wing - claimed that 'the attack ... was carried out by an Islamic State fighter.''
The president used the tragedy to make another pitch for stronger gun laws. Does he believe that someone who claims to be on a mission from Allah would not be able to obtain guns and explosives illegally?
Mateen had been on the Federal Bureau of Investigation's radar in 2013 and 2014, but reports The Daily Beast, the FBI 'subsequently closed the case when it produced nothing that appeared to warrant further investigation.' NBC News learned that Mateen traveled twice to Saudi Arabia in 2011 and 2012 'to perform a pilgrimage to Mecca,' according to a spokesman for Saudi Arabia's Ministry of the Interior. Once again, we are reactive rather than proactive.
The pattern following these terrorist attacks is now familiar. First comes extreme caution in which we say very little and refuse even to speculate about what seems obvious, followed, after the fact, as in the Fort Hood shooting, which was dubbed 'workplace violence,' by an attempt to quickly change the subject. Next comes the obligatory news conference in which a quickly produced imam or 'expert,' speaking for the Muslim community, is trotted out to say that the latest incident has nothing to do with Islam, which is a peaceful religion, and that we should all embrace unity.
Omar Mateen's father, Seddique Mateen, initially claimed there was no religious motivation behind the killings, but The Washington Post reported the father 'is an Afghan man who holds strong political views, including support for the Afghan Taliban.'
Muhammad Musri joined law enforcement officers at the news conference in Orlando. He is connected to the Islamic Society of Central Florida, which is connected to the Islamic Society of North America (ISNA), an Islamic umbrella organization that some believe has ties to terrorist groups.
Muhammad Musri's mosque was even used for a fundraiser that collected $55,000 for Hamas. There is also a 2011 video of Musri in which he blames the United States for Sept. 11.
People like Omar Mateen are not so much 'lone wolves' as 'known wolves.' But before law enforcement can legally act, it's often too late.
In wartime, certain liberties have been suspended in order to protect the country. This may be one of those times. Or should we wait until our enemies obtain a weapon of mass destruction?
Congress should declare war on all terrorist groups. Websites that promote ideologies that encourage terrorist acts should be shut down. No more mosques should be built in the U.S. until we gain an upper hand against radical Islamists. It does no good to say most Muslims are peaceful if you have no mechanism in place to act against or even identify those who are not.
On 'American Idol,' Randy Jackson would often say of a contestant that he or she was 'in it to win it.'
We don't appear to be in it, but our enemies are.
Readers may email Cal Thomas at tcaeditors@tribpub.com.
Roseville Denny's abruptly closes
Utica Community Schools teachers overwhelmingly reject final contract offer
Perry Rouse gets 10-15 years for killing friend at July Fourth party in Mount Clemens
De La Salle sued by former wrestler over alleged attack by fellow grappler
Icy roads close schools throughout northern Oakland County and in Macomb County
Police car crashes into truck that ran red light
President Trump to return to Macomb County this week
Sterling Heights man says little at sentencing for killing mother
Trader Todd's Marina brings 'Ogre' actor to Detroit Boat Show
Emagine Macomb and Rochester Hills showing the Super Bowl for free

redpajama_set_name: RedPajamaCommonCrawl


You're going to need to hear this.
While we're at it, the word definitely doesn't have an a in it, and the word grammar doesn't have an e in it. To hear means to listen and here is a place. Their is another word used as a possessive pronoun and there indicates a place the same way here does but can also be used as an adverb.
And if you aren't sure what a possessive pronoun or an adverb are, then take a minute to look it up before posting on the internet. Do it for the children.
Ahhh I feel much better now. Thanks for listening.


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Managing Partner Vitaliy Vodolazkin and Partner Arman Berdalin Included in the 2017-2018 Edition of the The Best Lawyers™ in Kazakhstan
On 16 June 2017, the reputable international legal review publication The Best Lawyers™in Kazakhstan issued its 2017-2018 edition.
Sayat Zholshy & Partners was ranked byThe Best Lawyers™in Kazakhstan for the first time, and the remarkable fact is that two SZP partners leading key areas of law were included in the 2017-2018 edition.
The utmost professional level of Managing Partner Vitaliy Vodolazkin, who leads Litigation & Arbitration and Finance & Securities practices, was acknowledged and recognised by the guide. According to their researchers, Vitaliy is one of the best Kazakhstan experts in dispute resolution proceedings.
The achievements of our Partner Arman Berdalin, the leader of Corporate Law and M&A practices, were also fully appreciated by the guide's analysts. Arman was recommended as one of the best Kazakhstan specialists in antitrust law.
Best Lawyers® is the oldest and most respected peer review publication in the legal profession. Originally, the guide was published only in the United States of America, where the first edition was issued over 30 years ago. In 2006, the publication entered the international area and, at present, it covers over 70 countries around the world, including Kazakhstan.
Best Lawyers® is a peer-review voting process. Each nominee is included in the annual publication on the basis of detailed evaluations of lawyers by an anonymous panel of esteemed lawyers earlier rated by the guide. The panel and research staff review the tallied results and decide on the finalists based on the number of votes in each category. Lawyers do not pay to be nominated or included on the list. Therefore, recognition inBest Lawyersis widely regarded by both clients and legal professionals as a significant honour, conferred on a lawyer by his or her peers.


I had seen Her around on a few blogs and coming up in my news feed on Facebook so when this was suggested as a swap over on Rick O'Shea's book swap page, I jumped at the chance to read it!
Two women; two different worlds.
Emma is a struggling mother who has put everything on hold.
Nina is sophisticated and independent – entirely in control.
When the pair meet, Nina generously draws Emma into her life. But this isn't the first time the women's paths have crossed. Nina remembers Emma and she remembers what Emma did.
But what exactly does Nina want from her?
And how far will she go in pursuit of it?
I hadn't read many reviews of the book (I tend to avoid reviews of books I'm dying to read in case they put me off!!) so I went into it not knowing what to expect!
The book is written in alternate chapters by the main characters Nina and Emma, which I'm guessing is to give both versions of the events that took place, but which only serves to annoy me when I start reading!
Nina seems well put together; an artist, second marriage but happy, teenage daughter, yada yada! Emma is a mother and portrayed as struggling to be seen as anything other than a mother I think! Married, with 2 kids, left a glamorous job and yearns for something more. Both equally annoying in my opinion.
I didn't find this book to be a psychological thriller, in parts where this tag was applied, the actions were little more than petty mind games. Maybe it's that I've read so many psych thrillers that I've become desensitised to the acts themselves but I really didn't find this book chilling in any way.
In relation to how the women know each other, this is alluded to maybe three quarters of the way through the book, and even then it is quite vague so it is hard to discern what it was Emma did to make Nina do the things she's doing. Without spoiling it for you, I will just say I was disappointed with the ending. I looked twice, it was still rubbish.
I gave this book 1* on Goodreads, and even that was too much for it if you ask me! One of those books I wish I didn't read!
Home to books and blastbeats.


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