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TMS320DM357 Inter-Integrated Circuit (I2C)
Texas Instruments | TMS320DM357 Inter-Integrated Circuit (I2C) | User Guides | Texas Instruments TMS320DM357 Inter-Integrated Circuit (I2C) User guides
TMS320DM357 DMSoC Inter-Integrated Circuit
(I2C) Peripheral
Literature Number: SPRUG27
SPRUG27 – November 2008
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Preface ........................................................................................................................................ 6
Introduction......................................................................................................................... 9
Purpose of the Peripheral ................................................................................................ 9
Features .................................................................................................................... 9
Functional Block Diagram .............................................................................................. 10
........................................................................ 10
Peripheral Architecture ....................................................................................................... 11
Bus Structure ............................................................................................................. 11
Clock Generation ........................................................................................................ 12
Clock Synchronization .................................................................................................. 13
Signal Descriptions ...................................................................................................... 13
START and STOP Conditions ......................................................................................... 14
Serial Data Formats ..................................................................................................... 15
Operating Modes ........................................................................................................ 17
NACK Bit Generation ................................................................................................... 18
Arbitration ................................................................................................................. 19
2.10 Reset Considerations ................................................................................................... 20
2.11 Initialization ............................................................................................................... 20
2.12 Interrupt Support ......................................................................................................... 22
2.13 DMA Events Generated by the I2C Peripheral ...................................................................... 23
2.14 Power Management ..................................................................................................... 23
2.15 Emulation Considerations .............................................................................................. 23
Registers ........................................................................................................................... 24
I2C Own Address Register (ICOAR) .................................................................................. 25
I2C Interrupt Mask Register (ICIMR) .................................................................................. 26
I2C Interrupt Status Register (ICSTR) ................................................................................ 27
I2C Clock Divider Registers (ICCLKL and ICCLKH) ................................................................ 30
I2C Data Count Register (ICCNT) ..................................................................................... 32
I2C Data Receive Register (ICDRR) .................................................................................. 33
I2C Slave Address Register (ICSAR) ................................................................................. 34
I2C Data Transmit Register (ICDXR) ................................................................................. 35
I2C Mode Register (ICMDR) ........................................................................................... 36
3.10 I2C Interrupt Vector Register (ICIVR) ................................................................................. 40
3.11 I2C Extended Mode Register (ICEMDR) ............................................................................. 41
3.12 I2C Prescaler Register (ICPSC) ....................................................................................... 42
3.13 I2C Peripheral Identification Register (ICPID1) ...................................................................... 43
3.14 I2C Peripheral Identification Register (ICPID2) ..................................................................... 43
Industry Standard(s) Compliance Statement
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I2C Peripheral Block Diagram ...........................................................................................
Multiple I2C Modules Connected ........................................................................................
Clocking Diagram for the I2C Peripheral ...............................................................................
Synchronization of Two I2C Clock Generators During Arbitration ...................................................
Bit Transfer on the I2C-Bus ...............................................................................................
I2C Peripheral START and STOP Conditions ..........................................................................
I2C Peripheral Data Transfer .............................................................................................
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR) .............................................
I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver (FDF = 0,
XA = 1 in ICMDR) ..........................................................................................................
I2C Peripheral Free Data Format (FDF = 1 in ICMDR) ...............................................................
I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0, XA = 0 in ICMDR) .....
Arbitration Procedure Between Two Master-Transmitters ............................................................
I2C Own Address Register (ICOAR).....................................................................................
I2C Interrupt Mask Register (ICIMR) ....................................................................................
I2C Interrupt Status Register (ICSTR) ...................................................................................
I2C Clock Low-Time Divider Register (ICCLKL) .......................................................................
I2C Clock High-Time Divider Register (ICCLKH) ......................................................................
I2C Data Count Register (ICCNT) .......................................................................................
I2C Data Receive Register (ICDRR).....................................................................................
I2C Slave Address Register (ICSAR) ....................................................................................
I2C Data Transmit Register (ICDXR) ....................................................................................
I2C Mode Register (ICMDR) ..............................................................................................
Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit ......................................
I2C Interrupt Vector Register (ICIVR) ...................................................................................
I2C Extended Mode Register (ICEMDR) ................................................................................
I2C Prescaler Register (ICPSC) ..........................................................................................
I2C Peripheral Identification Register 1 (ICPID1) ......................................................................
Operating Modes of the I2C Peripheral .................................................................................
Ways to Generate a NACK Bit ...........................................................................................
Descriptions of the I2C Interrupt Events ................................................................................
Inter-Integrated Circuit (I2C) Registers ..................................................................................
I2C Own Address Register (ICOAR) Field Descriptions ..............................................................
I2C Interrupt Mask Register (ICIMR) Field Descriptions ..............................................................
I2C Interrupt Status Register (ICSTR) Field Descriptions ............................................................
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions .................................................
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions ................................................
I2C Data Count Register (ICCNT) Field Descriptions .................................................................
I2C Data Receive Register (ICDRR) Field Descriptions ..............................................................
I2C Slave Address Register (ICSAR) Field Descriptions .............................................................
I2C Data Transmit Register (ICDXR) Field Descriptions ..............................................................
I2C Mode Register (ICMDR) Field Descriptions .......................................................................
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ....................................
How the MST and FDF Bits Affect the Role of TRX Bit ...............................................................
I2C Interrupt Vector Register (ICIVR) Field Descriptions .............................................................
I2C Extended Mode Register (ICEMDR) Field Descriptions .........................................................
I2C Prescaler Register (ICPSC) Field Descriptions ...................................................................
I2C Peripheral Identification Register 1 (ICPID1) Field Descriptions ................................................
About This Manual
This document describes the inter-integrated circuit (I2C) peripheral in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The I2C peripheral provides an interface between the DMSoC and other
devices that are compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1
and connected by way of an I2C-bus. The scope of this document assumes that you are familiar with the
I2C-bus specification.
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables.
– Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM357 Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the
search box provided at www.ti.com.
SPRUG06 — TMS320DM357 DMSoC Video Processing Back End (VPBE) User's Guide. Describes
the video processing back end (VPBE) in the TMS320DM357 Digital Media System-on-Chip
(DMSoC) video processing subsystem. Included in the VPBE is the video encoder, on-screen
display, and digital LCD controller.
SPRUG25 — TMS320DM357 DMSoC ARM Subsystem Reference Guide. Describes the ARM
subsystem in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the video processing subsystem,
and a majority of the peripherals and external memories.
SPRUG26 — TMS320DM357 DMSoC Universal Asynchronous Receiver/Transmitter (UART) User's
Guide. This document describes the universal asynchronous receiver/transmitter (UART) peripheral
in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The UART peripheral performs
serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial
conversion on data received from the CPU.
SPRUG27 — TMS320DM357 DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide.
Describes the inter-integrated circuit (I2C) peripheral in the TMS320DM357 Digital Media
devices compliant with the I2C-bus specification and connected by way of an I2C-bus. External
components attached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and
from the DMSoC through the I2C peripheral. This document assumes the reader is familiar with the
SPRUG28 — TMS320DM357 DMSoC 64-Bit Timer User's Guide. Describes the operation of the
software-programmable 64-bit timer in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
Timer 0 and Timer 1 are used as general-purpose (GP) timers and can be programmed in 64-bit
mode, dual 32-bit unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a
watchdog timer. The GP timer modes can be used to generate periodic interrupts or enhanced
direct memory access (EDMA) synchronization events. The watchdog timer mode is used to
provide a recovery mechanism for the device in the event of a fault condition, such as a non-exiting
code loop.
SPRUG29 — TMS320DM357 DMSoC Serial Peripheral Interface (SPI) User's Guide. Describes the
serial peripheral interface (SPI) in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The
SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed
bit-transfer rate. The SPI is normally used for communication between the DMSoC and external
peripherals. Typical applications include an interface to external I/O or peripheral expansion via
devices such as shift registers, display drivers, SPI EPROMs and analog-to-digital converters.
SPRUG30 — TMS320DM357 DMSoC Host Port Interface (HPI) Reference Guide. This document
describes the host port interface in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
The HPI provides a parallel port interface through which an external host processor can directly
access the TMS320DM357 DMSoC processor's resources (configuration and program/data
memories).
SPRUG31 — TMS320DM357 DMSoC General-Purpose Input/Output (GPIO) User's Guide. Describes
the general-purpose input/output (GPIO) peripheral in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The GPIO peripheral provides dedicated general-purpose pins that can
be configured as either inputs or outputs. When configured as an input, you can detect the state of
the input by reading the state of an internal register. When configured as an output, you can write
to an internal register to control the state driven on the output pin.
SPRUG32 — TMS320DM357 DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller
User's Guide. Describes the multimedia card (MMC)/secure digital (SD) card controller in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The MMC/SD card is used in a number of
applications to provide removable data storage. The MMC/SD controller provides an interface to
external MMC and SD cards. The communication between the MMC/SD controller and MMC/SD
card(s) is performed by the MMC/SD protocol.
SPRUG33 — TMS320DM357 DMSoC Asynchronous External Memory Interface (EMIF) User's
Guide. Describes the asynchronous external memory interface (EMIF) in the TMS320DM357
Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to a variety of
external devices.
SPRUG34 — TMS320DM357 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's
Guide. Describes the operation of the enhanced direct memory access (EDMA3) controller in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The EDMA3 controller's primary purpose
is to service user-programmed data transfers between two memory-mapped slave endpoints on the
DMSoC.
SPRUG35 — TMS320DM357 DMSoC Audio Serial Port (ASP) User's Guide. Describes the operation
of the audio serial port (ASP) audio interface in the TMS320DM357 Digital Media System-on-Chip
(DMSoC). The primary audio modes that are supported by the ASP are the AC97 and IIS modes. In
addition to the primary audio modes, the ASP supports general serial port receive and transmit
operation, but is not intended to be used as a high-speed interface.
SPRUG36 — TMS320DM357 DMSoC Ethernet Media Access Controller (EMAC)/Management Data
Input/Output (MDIO) Module User's Guide. Discusses the ethernet media access controller
(EMAC) and physical layer (PHY) device management data input/output (MDIO) module in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The EMAC controls the flow of packet
data from the DMSoC to the PHY. The MDIO module controls PHY configuration and status
SPRUG37 — TMS320DM357 DMSoC Pulse-Width Modulator (PWM) Peripheral User's Guide.
Describes the pulse-width modulator (PWM) peripheral in the TMS320DM357 Digital Media
System-on-Chip (DMSoC).
SPRUG38 — TMS320DM357 DMSoC DDR2 Memory Controller User's Guide. Describes the DDR2
memory controller in the TMS320DM357 Digital Media System-on-Chip (DMSoC). The DDR2
memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM
devices.
SPRUG39 — TMS320DM357 DMSoC Video Processing Front End (VPFE) User's Guide. Describes
the video processing front end (VPFE) in the TMS320DM357 Digital Media System-on-Chip
(DMSoC) video processing subsystem. Included in the VPFE is the preview engine, CCD controller,
resizer, histogram, and hardware 3A (H3A) statistic generator.
SPRUGH2 — TMS320DM357 DMSoC Peripherals Overview Reference Guide. This document provides
an overview of the peripherals in the TMS320DM357 Digital Media System-on-Chip (DMSoC).
SPRUGH3 — TMS320DM357 DMSoC Universal Serial Bus Controller User's Guide. This document
describes the universal serial bus (USB) controller in the TMS320DM357 Digital Media
System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It
provides a mechanism for data transfer between USB devices and also supports host negotiation.
Inter-Integrated Circuit (I2C) Peripheral
This document describes the operation of the inter-integrated circuit (I2C) peripheral in the
TMS320DM357 Digital Media System-on-Chip (DMSoC). The scope of this document assumes that you
are familiar with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1.
Purpose of the Peripheral
The I2C peripheral provides an interface between the DMSoC and other devices that are compliant with
the I2C-bus specification and connected by way of an I2C-bus. External components that are attached to
this two-wire serial bus can transmit and receive data that is up to eight bits wide both to and from the
DMSoC through the I2C peripheral.
The I2C peripheral has the following features:
• Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for byte format transfer
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers mode
– Support for multiple slave-transmitters and master-receivers mode
– Combined master transmit/receive and receive/transmit mode
– I2C data transfer rate of from 10 kbps up to 400 kbps (Philips I2C rate)
• 2 to 7 bit format transfer
• Free data format mode
• One read DMA event and one write DMA event that the DMA can use
• Seven interrupts that the CPU can use
• Peripheral enable/disable capability
Features Not Supported
• High-speed mode
• CBUS-compatibility mode
• The combined format in 10-bit addressing mode (the I2C sends the slave address the second byte
every time it sends the slave address the first byte).
A block diagram of the I2C peripheral is shown in Figure 1. Refer to Section 2 for detailed information
about the architecture of the I2C peripheral.
Figure 1. I2C Peripheral Block Diagram
I2C peripheral
Peripheral data bus
ICXSR
ICDXR
ICRSR
ICDRR
Control/status
Prescaler
I2C INT
to CPU
ICREVT
ICXEVT
Sync events to
EDMA controller
The I2C peripheral is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) specification
version 2.1.
Peripheral Architecture
The I2C peripheral consists of the following primary blocks:
• A serial interface: one data pin (SDA) and one clock pin (SCL)
• Data registers to temporarily hold receive data and transmit data traveling between the SDA pin and
the CPU or the EDMA controller
• Control and status registers
• A peripheral data bus interface to enable the CPU and the EDMA controller to access the I2C
peripheral registers
• A clock synchronizer to synchronize the I2C input clock (from the processor clock generator) and the
clock on the SCL pin, and to synchronize data transfers with masters of different clock speeds
• A prescaler to divide down the input clock that is driven to the I2C peripheral
• A noise filter on each of the two pins, SDA and SCL
• An arbitrator to handle arbitration between the I2C peripheral (when it is a master) and another master
• Interrupt generation logic, so that an interrupt can be sent to the CPU
• EDMA event generation logic, so that activity in the EDMA controller can be synchronized to data
reception and data transmission in the I2C peripheral
Figure 1 shows the four registers used for transmission and reception. The CPU or the EDMA controller
writes data for transmission to ICDXR and reads received data from ICDRR. When the I2C peripheral is
configured as a transmitter, data written to ICDXR is copied to ICXSR and shifted out on the SDA pin one
bit a time. When the I2C peripheral is configured as a receiver, received data is shifted into ICRSR and
then copied to ICDRR.
Bus Structure
Figure 1 shows how the I2C peripheral is connected to the I2C bus. The I2C bus is a multi-master bus
that supports a multi-master mode. This allows more than one device capable of controlling the bus that is
connected to it. A unique address recognizes each I2C device. Each I2C device can operate as either
transmitter or receiver, depending on the function of the device. Devices that are connected to the I2C bus
can be considered a master or slave when performing data transfers, in addition to being a transmitter or
receiver.
A master device is the device that initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Any device that is addressed by this master is
considered a slave during this transfer.
An example of multiple I2C modules that are connected for a two-way transfer from one device to other
devices is shown in Figure 2.
Figure 2. Multiple I2C Modules Connected
TI device
Serial data (SDA)
Serial clock (SCL)
As shown in Figure 3, PLL1 receives a signal from an external clock source and produces an I2C input
clock. A programmable prescaler (IPSC bit in ICPSC) in the I2C module divides down the I2C input clock
to produce a prescaled module clock. The prescaled module clock must be operated within the range of
7 to 12 MHz. The I2C clock dividers divide-down the high (ICCH bit in ICCLKH) and low portions (ICCL bit
in ICCLKL) of the prescaled module clock signal to produce the I2C serial clock, which appears on the
SCL pin when the I2C module is configured to be a master on the I2C bus.
Figure 3. Clocking Diagram for the I2C Peripheral
input clock
PLL1
I2C input clock
Register bits
(ICPSC[IPSC])
I2C module
Prescaled module clock−−MUST be set to 7−12 MHz!
Prescaled module clock frequency +
(ICCLKL[ICCL]),
(ICCLKH[ICCH])
I2C input clock frequency
(IPSC)1)
I2C clock
I2C serial clock on SCL pin
I2C serial clock frequency +
prescaled module clock frequency
(ICCL)d))(ICCH)d)
To I2C bus Where d depends on IPSC value in ICPSC:
IPSC value
2h−FFh
Prescaled Module Clock Frequency Range:
The I2C module must be operated with a prescaled module clock frequency of
7 to 12 MHz. The I2C prescaler register (I2CPSC) must be configured to this
frequency range.
The prescaler (IPSC bit in ICPSC) must only be initialized while the I2C module is in the reset state
(IRS = 0 in ICMDR). The prescaled frequency only takes effect when the IRS bit in ICMDR is changed to
1. Changing the IPSC bit in ICPSC while IRS = 1 in ICMDR has no effect. Likewise, you must configure
the I2C clock dividers (ICCH bit in ICCLKH and ICCL bit in ICCLKL) while the I2C module is still in reset
(IRS = 0 in ICMDR).
Clock Synchronization
Only one master device generates the clock signal (SCL) under normal conditions. However, there are
two or more masters during the arbitration procedure; and, you must synchronize the clock so that you
can compare the data output. Figure 4 illustrates the clock synchronization. The wired-AND property of
SCL means that a device that first generates a low period on SCL (device #1) overrules the other devices.
At this high-to-low transition, the clock generators of the other devices are forced to start their own low
period. The SCL is held low by the device with the longest low period. The other devices that finish their
low periods must wait for SCL to be released before starting their high periods. A synchronized signal on
SCL is obtained, where the slowest device determines the length of the low period and the fastest device
determines the length of the high period.
If a device pulls down the clock line for a longer time, the result is that all clock generators must enter the
wait state. This way, a slave slows down a fast master and the slow device creates enough time to store a
received data word or to prepare a data word that you are going to transmit.
Figure 4. Synchronization of Two I2C Clock Generators During Arbitration
Start HIGH
SCL from
device #1
The I2C peripheral has a serial data pin (SDA) and a serial clock pin (SCL) for data communication, as
shown in Figure 1. These two pins carry information between the DM357 device and other devices that
are connected to the I2C-bus. The SDA and SCL pins both are bi-directional. They each must be
connected to a positive supply voltage using a pull-up resistor. When the bus is free, both pins are high.
The driver of these two pins has an open-drain configuration to perform the required wired-AND function.
See the device-specific data manual for additional timing and electrical specifications for these pins.
Input and Output Voltage Levels
The master device generates one clock pulse for each data bit that is transferred. Due to a variety of
different technology devices that can be connected to the I2C-bus, the levels of logic 0 (low) and logic 1
(high) are not fixed and depend on the associated power supply level. See the device-specific data
manual for more information.
Data Validity
The data on SDA must be stable during the high period of the clock (see Figure 5). The high or low state
of the data line, SDA, can change only when the clock signal on SCL is low.
Figure 5. Bit Transfer on the I2C-Bus
stable data
Change of data
START and STOP Conditions
The I2C peripheral can generate START and STOP conditions when the peripheral is configured to be a
master on the I2C-bus, as shown in Figure 6:
• The START condition is defined as a high-to-low transition on the SDA line while SCL is high. A
master drives this condition to indicate the start of a data transfer.
• The STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. A master
drives this condition to indicate the end of a data transfer.
The I2C-bus is considered busy after a START condition and before a subsequent STOP condition. The
bus busy (BB) bit of ICSTR is 1. The bus is considered free between a STOP condition and the next
START condition. The BB is 0.
The master mode (MST) bit and the START condition (STT) bit in ICMDR must both be 1 for the I2C
peripheral to start a data transfer with a START condition. The STOP condition (STP) bit must be set to 1
for the I2C peripheral to end a data transfer with a STOP condition. A repeated START condition
generates when BB is set to 1 and STT is also set to 1. See Section 3.9 for a description of ICMDR
(including the MST, STT, and STP bits).
Figure 6. I2C Peripheral START and STOP Conditions
condition (S)
condition (P)
Serial Data Formats
Figure 7 shows an example of a data transfer on the I2C-bus. The I2C peripheral supports 1-bit to 8-bit
data values. Figure 7 is shown in an 8-bit data format (BC = 000 in ICMDR). Each bit put on the SDA line
is equivalent to one pulse on the SCL line. The data is always transferred with the most-significant bit
(MSB) first. The number of data values that can be transmitted or received is unrestricted; however, the
transmitters and receivers must agree on the number of data values being transferred.
The I2C peripheral supports the following data formats:
• 7-bit addressing mode
• 10-bit addressing mode
Figure 7. I2C Peripheral Data Transfer
bit from slave
(No-)Acknowledgement
bit from receiver
R/W ACK
Slave address
7-Bit Addressing Format
In the 7-bit addressing format (Figure 8), the first byte after a START condition (S) consists of a 7-bit slave
address followed by a R/W bit. The R/W bit determines the direction of the data.
• R/W = 0: The master writes (transmits) data to the addressed slave.
• R/W = 1: The master reads (receives) data from the slave.
An extra clock cycle dedicated for acknowledgment (ACK) is inserted after the R/W bit. If the slave inserts
the ACK bit, n bits of data from the transmitter (master or slave, depending on the R/W bit) follow it. n is a
number from 1 to 8 that the bit count (BC) bits of ICMDR determine. The receiver inserts an ACK bit after
the data bits have been transferred.
Write a 0 to the expanded address enable (XA) bit of ICMDR to select the 7-bit addressing format.
Figure 8. I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)
R/W
ACK P
n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR.
10-Bit Addressing Format
The 10-bit addressing format (Figure 9) is like the 7-bit addressing format, but the master sends the slave
address in two separate byte transfers. The first byte consists of 11110b, the two MSBs of the 10-bit slave
address, and R/W = 0 (write). The second byte is the remaining 8 bits of the 10-bit slave address. The
slave must send acknowledgment (ACK) after each of the two byte transfers. Once the master has written
the second byte to the slave, the master can either write data or use a repeated START condition to
change the data direction. (For more information about using 10-bit addressing, see the Philips
Semiconductors I2C-bus specification.)
Write 1 to the XA bit of ICMDR to select the 10-bit addressing format.
Figure 9. I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing to Slave-Receiver
(FDF = 0, XA = 1 in ICMDR)
11110AA
A A = 2 MSBs
8 LSBs of slave address
Free Data Format
In the free data format (Figure 10), the first bits after a START condition (S) are a data word. An ACK bit is
inserted after each data word, which can be from 1 to 8 bits, depending on the bit count (BC) bits of
ICMDR. No address or data-direction bit is sent. Therefore, the transmitter and the receiver must both
support the free data format, and the direction of the data must be constant throughout the transfer.
To select the free data format, write 1 to the free data format (FDF) bit of ICMDR.
Figure 10. I2C Peripheral Free Data Format (FDF = 1 in ICMDR)
Using a Repeated START Condition
The repeated START condition can be used with the 7-bit addressing, 10-bit addressing, and free data
formats. The 7-bit addressing format using a repeated START condition (S) is shown in Figure 11. At the
end of each data word, the master can drive another START condition. Using this capability, a master can
transmit/receive any number of data words before driving a STOP condition. The length of a data word
can be from 1 to 8 bits and is selected with the bit count (BC) bits of ICMDR.
Figure 11. I2C Peripheral 7-Bit Addressing Format With Repeated START Condition (FDF = 0,
XA = 0 in ICMDR)
Slave address R/W ACK
The I2C peripheral has four basic operating modes to support data transfers as a master and as a slave.
See Table 1 for the names and descriptions of the modes.
If the I2C peripheral is a master, it begins as a master-transmitter and, typically, transmits an address for a
particular slave. When giving data to the slave, the I2C peripheral must remain a master-transmitter. In
order to receive data from a slave, the I2C peripheral must be changed to the master-receiver mode.
If the I2C peripheral is a slave, it begins as a slave-receiver and, typically, sends acknowledgment when it
recognizes its slave address from a master. If the master will be sending data to the I2C peripheral, the
peripheral must remain a slave-receiver. If the master has requested data from the I2C peripheral, the
peripheral must be changed to the slave-transmitter mode.
Table 1. Operating Modes of the I2C Peripheral
Slave-receiver mode
The I2C peripheral is a slave and receives data from a master. All slave modules begin in this
mode. In this mode, serial data bits received on SDA are shifted in with the clock pulses that are
generated by the master. As a slave, the I2C peripheral does not generate the clock signal, but it
can hold SCL low while the intervention of the processor is required (RSFULL = 1 in ICSTR) after
data has been received.
Slave-transmitter mode
The I2C peripheral is a slave and transmits data to a master. This mode can only be entered from
the slave-receiver mode; the I2C peripheral must first receive a command from the master. When
you are using any of the 7-bit/10-bit addressing formats, the I2C peripheral enters its
slave-transmitter mode if the slave address is the same as its own address (in ICOAR) and the
master has transmitted R/W = 1. As a slave-transmitter, the I2C peripheral then shifts the serial
data out on SDA with the clock pulses that are generated by the master. While a slave, the I2C
peripheral does not generate the clock signal, but it can hold SCL low while the intervention of the
processor is required (XSMT = 0 in ICSTR) after data has been transmitted.
Master-receiver mode
The I2C peripheral is a master and receives data from a slave. This mode can only be entered
from the master-transmitter mode; the I2C peripheral must first transmit a command to the slave.
When you are using any of the 7-bit/10-bit addressing formats, the I2C peripheral enters its
master-receiver mode after transmitting the slave address and R/W = 1. Serial data bits on SDA
are shifted into the I2C peripheral with the clock pulses generated by the I2C peripheral on SCL.
The clock pulses are inhibited and SCL is held low when the intervention of the processor is
required (RSFULL = 1 in ICSTR) after data has been received.
Master-transmitter mode
The I2C peripheral is a master and transmits control information and data to a slave. All master
modules begin in this mode. In this mode, data assembled in any of the 7-bit/10-bit addressing
formats is shifted out on SDA. The bit shifting is synchronized with the clock pulses generated by
the I2C peripheral on SCL. The clock pulses are inhibited and SCL is held low when the
intervention of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted.
NACK Bit Generation
When the I2C peripheral is a receiver (master or slave), it can acknowledge or ignore bits sent by the
transmitter. To ignore any new bits, the I2C peripheral must send a no-acknowledge (NACK) bit during the
acknowledge cycle on the bus. Table 2 summarizes the various ways the I2C peripheral sends a NACK
bit.
Table 2. Ways to Generate a NACK Bit
• Disable data transfers (STT = 0 in ICSTR).
• Allow an overrun condition (RSFULL = 1 in
ICSTR).
• Reset the peripheral (IRS = 0 in ICMDR)
Set the NACKMOD bit of ICMDR before the rising
edge of the last data bit you intend to receive.
Repeat mode
(RM = 1 in ICMDR)
• Generate a STOP condition (STOP = 1 in
ICMDR).
• Reset the peripheral (IRS = 0 in ICMDR).
Nonrepeat mode
• If STP = 1 in ICMDR, allow the internal data
counter to count down to 0 and force a STOP
• If STP = 0, make STP = 1 to generate a
STOP condition.
If two or more master-transmitters simultaneously start a transmission on the same bus, an arbitration
procedure is invoked. The arbitration procedure uses the data presented on the serial data bus (SDA) by
the competing transmitters. Figure 12 illustrates the arbitration procedure between two devices. The first
master-transmitter, which drives SDA high, is overruled by another master-transmitter that drives SDA low.
The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest
binary value. Should two or more devices send identical first bytes, arbitration continues on the
subsequent bytes.
If the I2C peripheral is the losing master, it switches to the slave-receiver mode, sets the arbitration lost
(AL) flag, and generates the arbitration-lost interrupt.
If during a serial transfer the arbitration procedure is still in progress when a repeated START condition or
a STOP condition is transmitted to SDA, the master-transmitters involved must send the repeated START
condition or the STOP condition at the same position in the format frame. Arbitration is not allowed
• A repeated START condition and a data bit
• A STOP condition and a data bit
• A repeated START condition and a STOP condition
Figure 12. Arbitration Procedure Between Two Master-Transmitters
Device #1 lost arbitration
and switches off
2.10 Reset Considerations
The I2C peripheral has two reset sources: software reset and hardware reset.
Software Reset Considerations
To reset the I2C peripheral, write 0 to the I2C reset (IRS) bit in the I2C mode register (ICMDR). All status
bits in the I2C interrupt status register (ICSTR) are forced to their default values, and the I2C peripheral
remains disabled until IRS is changed to 1. The SDA and SCL pins are in the high-impedance state.
If the IRS bit is cleared to 0 during a transfer, this can cause the I2C bus to hang (SDA and
SCL are in the high-impedance state).
Hardware Reset Considerations
When a hardware reset occurs, all the registers of the I2C peripheral are set to their default values and
the I2C peripheral remains disabled until the I2C reset (IRS) bit in the I2C mode register (ICMDR) is
changed to 1.
The IRS bit must be cleared to 0 while you configure/reconfigure the I2C peripheral. Forcing
IRS to 0 can be used to save power and to clear error conditions.
2.11 Initialization
Proper I2C initialization is required prior to starting communication with other I2C device(s). Unless a fully
fledged driver is in place, you need to determine the required I2C configuration needed (for example,
Master Receiver, etc.) and configure the I2C controller with the desired settings. Enabling the I2C clock
should be the first task. Then the I2C controller is placed in reset. You now are ready to configure the I2C
controller. Once configuration is done, you need to enable the I2C controller by releasing the controller
from reset. Prior to starting communication, you need to make sure that all status bits are cleared and no
pending interrupts exist. Once the bus is determined to be available (the bus is not busy), the I2C is ready
to proceed with the desired communication.
Configuring the I2C in Master Receiver Mode and Servicing Receive Data via CPU
The following initialization procedure is for the I2C controller configured in Master Receiver mode. The
CPU is used to move data from the I2C receive register to CPU memory (memory accessible by the
CPU).
1. Enable I2C clock from the Power and Sleep Controller (see the TMS320DM357 DMSoC ARM
Subsystem Reference Guide (SPRUG25).
2. Place I2C in reset (clear IRS = 0 in ICMDR).
3. Configure ICMDR:
• Configure I2C as Master (MST = 1).
• Indicate the I2C configuration to be used; for example, Data Receiver (TRX = 0)
• Indicate 7-bit addressing is to be used (XA = 0).
• Disable repeat mode (RM = 0).
• Disable loopback mode (DLB = 0).
• Disable free data format (FDF = 0).
• Optional: Disable start byte mode if addressing a fully fledged I2C device (STB = 0).
• Set number of bits to transfer to be 8 bits (BC = 0).
4. Configure Slave Address: the I2C device this I2C master would be addressing (ICSAR = 7BIT
ADDRESS).
5. Configure the peripheral clock operation frequency (ICPSC). This value should be selected in such a
way that the frequency is between 7 and 12 MHZ.
6. Configure I2C master clock frequency:
• Configure the low-time divider value (ICCLKL).
• Configure the high-time divider value (ICCLKH).
7. Make sure the interrupt status register (ICSTR) is cleared:
• Read ICSTR and write it back (write 1 to clear) ICSTR = ICSTR
• Read ICIVR until it is zero.
8. Take I2C controller out of reset: enable I2C controller (set IRS bit = 1 in ICMDR).
9. Wait until bus busy bit is cleared (BB = 0 in ICSTR).
10. Generate a START event, followed by Slave Address, etc. (set STT = 1 in ICMDR).
11. Wait until data is received (ICRRDY = 1 in ICSTR).
12. Read data:
• If ICRRDY = 1 in ICSTR, then read ICDRR.
• Perform the previous two steps until receiving one byte short of the entire byte expecting to
receive.
13. Configure the I2C controller not to generate an ACK on the next/final byte reception: set NACKMOD
bit for the I2C to generate a NACK on the last byte received (set NACKMOD = 1 in ICMDR).
14. End transfer/release bus when transfer is done. Generate a STOP event (set STP = 1 in ICMDR).
Configuring the I2C in Slave Receiver and Transmitter Mode
The following initialization procedure is for the I2C controller configured in Slave Receiver and Transmitter
1. Enable I2C clock from PSC Level. Do this so that you will be able to configure the I2C registers.
2. Place I2C in Reset (Clear IRS bit).
• IRS=0
3. Assign the Address (a 7 bit or 10 bit address) that the I2C Controller will be responding to. This is the
Address that the Master is going to broadcast when attempting to start communication with this slave
device; I2C Controller.
• If the I2C is able to respond to 7-bit Addressing: Configure XA=0
• If the I2C is able to respond to 10-bit Addressing: Configure XA=1
• Program ICOAR=Assigned Address(7 or 10 bit Address)
4. Enable the desired interrupt you need to receive by setting the desired interrupt bit field within ICIMR to
enable the particular Interrupt.
AAS=1; Expect an interrupt when Master's Address matches yours (ICOAR programmed value).
ICRRDY=1; Expect a receive interrupt when a byte worth data sent from the master is ready to be
• ICXRDY=1; Expect to receive interrupt when the transmit register is ready to be written with a new
data that is to be sent to the master.
• SCD=1; Expect to receive interrupt when Stop Condition is detected.
5. Configure the I2C Controller Operating frequency; this is not the serial clock frequency. This should be
between 7 and 12 MHz. Program IPSC to generate a 7 to 12MHz operating frequency.
• Prescaled Module Clock Frequency = PLL1 Output Frequency / (IPSC + 1).
6. Configure the I2C Serial Clock Frequency. It is advised to configure this frequency to operate at 400
KHz. This will allow the slave device to be able to attend to all Master speeds. Program ICCH and
ICCL.
• 400 KHz = I2C Operating Frequency (7-12MHz from Step 5) / [(ICCH+5) + (ICCL+5)].
• If ICCL==ICCH ≥ 400 KHz = Prescaled Module Clock Frequency / [2×ICCH+10]
7. Configure the Mode Register.
• MST=0; Configure the I2C Controller to operate as SLAVE.
• FDF=0; Free Data Format is disabled.
• BC=0; Set data width to 8 bytes.
• DLB=0; Disable Loopback Mode.
• STB=0; I2C Controller can detect Start condition via H/W.
• RM=1, STP=0, STT=1. See Table 16. (No Activity case).
• Configure remaining bits other than IRS to 0.
8. Release I2C from Reset
• IRS=1; Make sure you do not over write your previous configurations.
9. Make sure Interrupt Status Register is cleared.
• ICSTR=ICSTR; Clear Interrupt fields that require writing '1' requirements.
• While (ICIVR != 0) Read ICIVR; Read until it is cleared to Zero.
10. Instruct I2C Controller to detect START Condition and Its Own Address.
• STT=1; Make sure you do not over write your previous configurations.
MASTER desires to perform a write transfer.
11. If Master requests a Write, i.e, I2C needs to receive data, perform the following.
• Wait for Receive Interrupt to be received, i.e, ICRRDY=1.
• Read Data
12. Perform Step 11 until one of the two happens:
• Master generates a STOP Condition (SCD=1) or
• I2C Slave desires to end receive transfer.
If the latter, then the I2C needs to Not Acknowledge the last byte to be received from the Master.
After reading the byte prior from the last byte set NACKMOD bit so that the I2C automatically
NACKs the following received data byte, which is the last data byte.
• NACKMOD=1; set this field on the 2nd data prior from the last.
Master desires to perform a read transfer.
13. If Master requests a Read, i.e, I2C needs to transmit data, perform the following.
• Write Data.
• Wait for Transmit Interrupt to be received, i.e, ICXRDY=1.
14. Perform step 13 until a STOP condition is detected, i.e. (SCD=1).
2.12 Interrupt Support
The I2C peripheral is capable of interrupting the ARM CPU. The CPU can determine which I2C events
caused the interrupt by reading the I2C interrupt vector register (ICIVR). ICIVR contains a binary-coded
interrupt vector type to indicate which interrupt has occurred. Reading ICIVR clears the interrupt flag; if
other interrupts are pending, a new interrupt is generated. If there is more than one pending interrupt flag,
reading ICIVR clears the highest-priority interrupt flag.
Interrupt Events and Requests
The I2C peripheral can generate the interrupts described in Table 3. Each interrupt has a flag bit in the
I2C interrupt status register (ICSTR) and a mask bit in the interrupt mask register (ICIMR). When one of
the specified events occurs, its flag bit is set. If the corresponding mask bit is 0, the interrupt request is
blocked; if the mask bit is 1, the request is forwarded to the CPU as an I2C interrupt.
Table 3. Descriptions of the I2C Interrupt Events
I2C Interrupt
Initiating Event
Arbitration-lost interrupt (AL)
Generated when the I2C arbitration procedure is lost or illegal START/STOP conditions
occur
No-acknowledge interrupt (NACK)
Generated when the master I2C does not receive any acknowledge from the receiver
Registers-ready-for-access interrupt
(ARDY)
Generated by the I2C when the previously programmed address, data and command have
been performed and the status bits have been updated. This interrupt is used to let the
controlling processor know that the I2C registers are ready to be accessed.
Receive interrupt/status (ICRINT
and ICRRDY)
Generated when the received data in the receive-shift register (ICRSR) has been copied into
the ICDRR. The ICRRDY bit can also be polled by the CPU to read the received data in the
ICDRR.
Transmit interrupt/status (ICXINT
and ICXRDY)
Generated when the transmitted data has been copied from ICDXR to the transmit-shift
register (ICXSR) and shifted out on the SDA pin. This bit can also polled by the CPU to write
the next transmitted data into the ICDXR.
Stop-Condition-Detection interrupt
(SCD)
Generated when a STOP condition has been detected
Address-as-Slave interrupt (AAS)
Generated when the I2C has recognized its own slave address or an address of all (8)
zeros.
Interrupt Multiplexing
The I2C interrupt to the ARM CPU are not multiplexed with any other interrupt source.
2.13 DMA Events Generated by the I2C Peripheral
For the EDMA controller to handle transmit and receive data, the I2C peripheral generates the following
two EDMA events. Activity in EDMA channels can be synchronized to these events.
• Receive event (ICREVT): When receive data has been copied from the receive shift register (ICRSR)
to the data receive register (ICDRR), the I2C peripheral sends an REVT signal to the EDMA controller.
In response, the EDMA controller can read the data from ICDRR.
• Transmit event (ICXEVT): When transmit data has been copied from the data transmit register
(ICDXR) to the transmit shift register (ICXSR), the I2C peripheral sends an XEVT signal to the EDMA
controller. In response, the EDMA controller can write the next transmit data value to ICDXR.
2.14 Power Management
The I2C peripheral can be placed in reduced-power modes to conserve power during periods of low
activity. The power management of the I2C peripheral is controlled by the processor Power and Sleep
Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on
the device. For detailed information on power management procedures using the PSC, see the
TMS320DM357 DMSoC ARM Subsystem Reference Guide (SPRUG25).
2.15 Emulation Considerations
The response of the I2C events to emulation suspend events (such as halts and breakpoints) is controlled
by the FREE bit in the I2C mode register (ICMDR). The I2C peripheral either stops exchanging data
(FREE = 0) or continues to run (FREE = 1) when an emulation suspend event occurs. How the I2C
peripheral terminates data transactions is affected by whether the I2C peripheral is acting as a master or a
slave. For more information, see the description of the FREE bit in ICMDR (see Section 3.9).
Table 4 lists the memory-mapped registers for the inter-integrated circuit (I2C) peripheral. See the
device-specific data manual for the memory address of these registers. All other register offset addresses
not listed in Table 4 should be considered as reserved locations and the register contents should not be
modified.
Table 4. Inter-Integrated Circuit (I2C) Registers
ICOAR
I2C Own Address Register
Section 3.1
ICIMR
I2C Interrupt Mask Register
ICSTR
I2C Interrupt Status Register
ICCLKL
I2C Clock Low-Time Divider Register
ICCLKH
I2C Clock High-Time Divider Register
ICCNT
I2C Data Count Register
I2C Data Receive Register
ICSAR
I2C Slave Address Register
I2C Data Transmit Register
ICMDR
I2C Mode Register
ICIVR
I2C Interrupt Vector Register
ICEMDR
I2C Extended Mode Register
ICPSC
I2C Prescaler Register
ICPID1
I2C Peripheral Identification Register 1
I2C Own Address Register (ICOAR)
The I2C own address register (ICOAR) is used to specify its own slave address, which distinguishes it
from other slaves connected to the I2C-bus. If the 7-bit addressing mode is selected (XA = 0 in ICMDR),
only bits 6-0 are used; bits 9-7 are ignored.
The I2C own address register (ICOAR) is shown in Figure 13 and described in Table 5.
Figure 13. I2C Own Address Register (ICOAR)
OADDR
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5. I2C Own Address Register (ICOAR) Field Descriptions
These reserved bit locations are always read as zeros. A value written to this field has no effect.
0-3FFh Own slave address. Provides the slave address of the I2C.
In 7-bit addressing mode (XA = 0 in ICMDR): bits 6-0 provide the 7-bit slave address of the I2C. Bits 9-7
are ignored.
In 10-bit addressing mode (XA = 1 in ICMDR): bits 9-0 provide the 10-bit slave address of the I2C.
I2C Interrupt Mask Register (ICIMR)
The I2C interrupt mask register (ICIMR) is used to individually enable or disable I2C interrupt requests.
The I2C interrupt mask register (ICIMR) is shown in Figure 14 and described Table 6.
Figure 14. I2C Interrupt Mask Register (ICIMR)
ICXRDY
ICRRDY
Table 6. I2C Interrupt Mask Register (ICIMR) Field Descriptions
Address-as-slave interrupt enable bit.
Interrupt request is disabled.
Interrupt request is enabled.
Stop condition detected interrupt enable bit.
Transmit-data-ready interrupt enable bit.
Receive-data-ready interrupt enable bit.
Register-access-ready interrupt enable bit.
No-acknowledgment interrupt enable bit.
Arbitration-lost interrupt enable bit
I2C Interrupt Status Register (ICSTR)
The I2C interrupt status register (ICSTR) is used to determine which interrupt has occurred and to read
status information.
The I2C interrupt status register (ICSTR) is shown in Figure 15 and described in Table 7.
Figure 15. I2C Interrupt Status Register (ICSTR)
SDIR
NACKSNT
RSFULL
R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions
Slave direction bit. In digital-loopback mode (DLB), the SDIR bit is cleared to 0.
I2C is acting as a master-transmitter/receiver or a slave-receiver. SDIR is cleared by one of the
• A STOP or a START condition.
• SDIR is manually cleared. To clear this bit, write a 1 to it.
I2C is acting as a slave-transmitter.
No-acknowledgment sent bit. NACKSNT bit is used when the I2C is in the receiver mode. One instance
in which NACKSNT is affected is when the NACK mode is used (see the description for NACKMOD in
Section 3.9).
NACK is not sent. NACKSNT is cleared by one of the following events:
• It is manually cleared. To clear this bit, write a 1 to it.
• The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset).
NACK is sent. A no-acknowledge bit was sent during the acknowledge cycle on the I2C-bus.
Bus busy bit. BB bit indicates whether the I2C-bus is busy or is free for another data transfer. In the
master mode, BB is controlled by the software.
Bus is free. BB is cleared by one of the following events:
• The I2C receives or transmits a STOP bit (bus free).
• BB is manually cleared. To clear this bit, write a 1 to it.
Bus is busy. When the STT bit in ICMDR is set to 1, a restart condition is generated. BB is set by one of
the following events:
• The I2C has received or transmitted a START bit on the bus.
• SCL is in a low state and the IRS bit in ICMDR is 0.
Table 7. I2C Interrupt Status Register (ICSTR) Field Descriptions (continued)
Receive shift register full bit. RSFULL indicates an overrun condition during reception. Overrun occurs
when the receive shift register (ICRSR) is full with new data but the previous data has not been read
from the data receive register (ICDRR). The new data will not be copied to ICDRR until the previous
data is read. As new bits arrive from the SDA pin, they overwrite the bits in ICRSR.
No overrun is detected. RSFULL is cleared by one of the following events:
• ICDRR is read.
Overrun is detected.
Transmit shift register empty bit. XSMT indicates that the transmitter has experienced underflow.
Underflow occurs when the transmit shift register (ICXSR) is empty but the data transmit register
(ICDXR) has not been loaded since the last ICDXR-to-ICXSR transfer. The next ICDXR-to-ICXSR
transfer will not occur until new data is in ICDXR. If new data is not transferred in time, the previous
data may be re-transmitted on the SDA pin.
Underflow is detected.
No underflow is detected. XSMT is set by one of the following events:
• Data is written to ICDXR.
Addressed-as-slave bit.
The AAS bit has been cleared by a repeated START condition or by a STOP condition.
AAS is set by one of the following events:
• I2C has recognized its own slave address or an address of all zeros (general call).
• The first data word has been received in the free data format (FDF = 1 in ICMDR).
Address 0 bit.
AD0 has been cleared by a START or STOP condition.
An address of all zeros (general call) is detected.
Stop condition detected bit. SCD indicates when a STOP condition has been detected on the I2C bus.
The STOP condition could be generated by the I2C or by another I2C device connected to the bus.
No STOP condition has been detected. SCD is cleared by one of the following events:
• By reading the INTCODE bits in ICIVR as 110b.
• SCD is manually cleared. To clear this bit, write a 1 to it.
A STOP condition has been detected.
Transmit-data-ready interrupt flag bit. ICXRDY indicates that the data transmit register (ICDXR) is ready
to accept new data because the previous data has been copied from ICDXR to the transmit shift
register (ICXSR). The CPU can poll ICXRDY or use the XRDY interrupt request.
ICDXR is not ready. ICXRDY is cleared by one of the following events:
• ICXRDY is manually cleared. To clear this bit, write a 1 to it.
ICDXR is ready. Data has been copied from ICDXR to ICXSR. ICXRDY is forced to 1 when the I2C is
reset.
Receive-data-ready interrupt flag bit. ICRRDY indicates that the data receive register (ICDRR) is ready
to be read because data has been copied from the receive shift register (ICRSR) to ICDRR. The CPU
can poll ICRRDY or use the RRDY interrupt request.
ICDRR is not ready. ICRRDY is cleared by one of the following events:
• ICRRDY is manually cleared. To clear this bit, write a 1 to it.
ICDRR is ready. Data has been copied from ICRSR to ICDRR.
Register-access-ready interrupt flag bit (only applicable when the I2C is in the master mode). ARDY
indicates that the I2C registers are ready to be accessed because the previously programmed address,
data, and command values have been used. The CPU can poll ARDY or use the ARDY interrupt
request.
The registers are not ready to be accessed. ARDY is cleared by one of the following events:
• The I2C starts using the current register contents.
• ARDY is manually cleared. To clear this bit, write a 1 to it.
The registers are ready to be accessed.
• In the nonrepeat mode (RM = 0 in ICMDR): If STP = 0 in ICMDR, ARDY is set when the internal data
counter counts down to 0. If STP = 1, ARDY is not affected (instead, the I2C generates a STOP
condition when the counter reaches 0).
• In the repeat mode (RM = 1): ARDY is set at the end of each data word transmitted from ICDXR.
No-acknowledgment interrupt flag bit. NACK applies when the I2C is a transmitter (master or slave).
NACK indicates whether the I2C has detected an acknowledge bit (ACK) or a no-acknowledge bit
(NACK) from the receiver. The CPU can poll NACK or use the NACK interrupt request.
ACK received/NACK is not received. NACK is cleared by one of the following events:
• An acknowledge bit (ACK) has been sent by the receiver.
• NACK is manually cleared. To clear this bit, write a 1 to it.
• The CPU reads the interrupt source register (ICISR) when the register contains the code for a NACK
interrupt.
NACK bit is received. The hardware detects that a no-acknowledge (NACK) bit has been received.
Note: While the I2C performs a general call transfer, NACK is 1, even if one or more slaves send
acknowledgment.
Arbitration-lost interrupt flag bit (only applicable when the I2C is a master-transmitter). AL primarily
indicates when the I2C has lost an arbitration contest with another master-transmitter. The CPU can poll
AL or use the AL interrupt request.
Arbitration is not lost. AL is cleared by one of the following events:
• AL is manually cleared. To clear this bit, write a 1 to it.
• The CPU reads the interrupt source register (ICISR) when the register contains the code for an AL
Arbitration is lost. AL is set by one of the following events:
• The I2C senses that it has lost an arbitration with two or more competing transmitters that started a
transmission almost simultaneously.
• The I2C attempts to start a transfer while the BB (bus busy) bit is set to 1.
When AL is set to 1, the MST and STP bits of ICMDR are cleared, and the I2C becomes a
slave-receiver.
I2C Clock Divider Registers (ICCLKL and ICCLKH)
When the I2C is a master, the prescaled module clock is divided down for use as the I2C serial clock on
the SCL pin. The shape of the I2C serial clock depends on two divide-down values, ICCL and ICCH. For
detailed information on how these values are programmed, see Section 2.2.
I2C Clock Low-Time Divider Register (ICCLKL)
For each I2C serial clock cycle, ICCL determines the amount of time the signal is low. ICCLKL must be
configured while the I2C is still in reset (IRS = 0 in ICMDR).
The I2C clock low-time divider register (ICCLKL) is shown in Figure 16 and described in Table 8.
Figure 16. I2C Clock Low-Time Divider Register (ICCLKL)
ICCL
Table 8. I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions
0-FFFFh
Clock low-time divide-down value of 1-65536. The period of the module clock is multiplied by
(ICCL + d) to produce the low-time duration of the I2C serial on the SCL pin.
I2C Clock High-Time Divider Register (ICCLKH)
For each I2C serial clock cycle, ICCH determines the amount of time the signal is high. ICCLKH must be
The I2C clock high-time divider register (ICCLKH) is shown in Figure 17 and described in Table 9.
Figure 17. I2C Clock High-Time Divider Register (ICCLKH)
ICCH
Table 9. I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions
Clock high-time divide-down value of 1-65536. The period of the module clock is multiplied by
(ICCH + d) to produce the high-time duration of the I2C serial on the SCL pin.
I2C Data Count Register (ICCNT)
The I2C data count register (ICCNT) is used to indicate how many data words to transfer when the I2C is
configured as a master-transmitter (MST = 1 and TRX = 1 in ICMDR) and the repeat mode is off (RM = 0
in ICMDR). In the repeat mode (RM = 1), ICCNT is not used.
The value written to ICCNT is copied to an internal data counter. The internal data counter is decremented
by 1 for each data word transferred (ICCNT remains unchanged). If a STOP condition is requested
(STP = 1 in ICMDR), the I2C terminates the transfer with a STOP condition when the countdown is
complete (that is, when the last data word has been transferred).
The data count register (ICCNT) is shown in Figure 18 and described in Table 10.
Figure 18. I2C Data Count Register (ICCNT)
Table 10. I2C Data Count Register (ICCNT) Field Descriptions
1h-FFFFh
Data count value. When RM = 0 in ICMDR, ICDC indicates the number of data words to transfer in
the nonrepeat mode. When RM = 1 in ICMDR, the value in ICCNT is a don't care. If STP = 1 in
ICMDR, a STOP condition is generated when the internal data counter counts down to 0.
The start value loaded to the internal data counter is 65536.
The start value loaded to internal data counter is 1-65535.
I2C Data Receive Register (ICDRR)
The I2C data receive register (ICDRR) is used to read the receive data. The ICDRR can receive a data
value of up to 8 bits; data values with fewer than 8 bits are right-aligned in the D bits and the remaining D
bits are undefined. The number of data bits is selected by the bit count bits (BC) of ICMDR. The I2C
receive shift register (ICRSR) shifts in the received data from the SDA pin. Once data is complete, the I2C
copies the contents of ICRSR into ICDRR. The CPU and the EDMA controller cannot access ICRSR.
The I2C data receive register (ICDRR) is shown in Figure 19 and described in Table 11.
Figure 19. I2C Data Receive Register (ICDRR)
LEGEND: R = Read only; -n = value after reset
Table 11. I2C Data Receive Register (ICDRR) Field Descriptions
0-FFh
Receive data.
I2C Slave Address Register (ICSAR)
The I2C slave address register (ICSAR) contains a 7-bit or 10-bit slave address. When the I2C is not
using the free data format (FDF = 0 in ICMDR), it uses this address to initiate data transfers with a slave
or slaves. When the address is nonzero, the address is for a particular slave. When the address is 0, the
address is a general call to all slaves. If the 7-bit addressing mode is selected (XA = 0 in ICMDR), only
bits 6-0 of ICSAR are used; bits 9-7 are ignored. The I2C slave address register (ICSAR) is shown in
Figure 20 and described in Table 12.
Figure 20. I2C Slave Address Register (ICSAR)
SADDR
R/W-3FFh
Table 12. I2C Slave Address Register (ICSAR) Field Descriptions
0-3FFh
Slave address. Provides the slave address of the I2C.
In 7-bit addressing mode (XA = 0 in ICMDR): bits 6-0 provide the 7-bit slave address that the I2C
transmits when it is in the master-transmitter mode. Bits 9-7 are ignored.
In 10-bit addressing mode (XA = 1 in ICMDR): Bits 9-0 provide the 10-bit slave address that the
I2C transmits when it is in the master-transmitter mode.
I2C Data Transmit Register (ICDXR)
The CPU or EDMA writes transmit data to the I2C data transmit register (ICDXR). The ICDXR can accept
a data value of up to 8 bits. When writing a data value with fewer than 8 bits, the written data must be
right-aligned in the D bits. The number of data bits is selected by the bit count bits (BC) of ICMDR. Once
data is written to ICDXR, the I2C copies the contents of ICDXR into the I2C transmit shift register
(ICXSR). The ICXSR shifts out the transmit data from the SDA pin. The CPU and the EDMA controller
cannot access ICXSR.
The I2C data transmit register (ICDXR) is shown in Figure 21 and described in Table 13.
Figure 21. I2C Data Transmit Register (ICDXR)
Table 13. I2C Data Transmit Register (ICDXR) Field Descriptions
Transmit data.
I2C Mode Register (ICMDR)
The I2C mode register (ICMDR) contains the control bits of the I2C.
The I2C mode register (ICMDR) is shown in shown in Figure 22 and described in Table 14.
Figure 22. I2C Mode Register (ICMDR)
NACKMOD
Table 14. I2C Mode Register (ICMDR) Field Descriptions
No-acknowledge (NACK) mode bit (only applicable when the I2C is a receiver).
In slave-receiver mode: The I2C sends an acknowledge (ACK) bit to the transmitter during the each
acknowledge cycle on the bus. The I2C only sends a no-acknowledge (NACK) bit if you set the
NACKMOD bit.
In master-receiver mode: The I2C sends an ACK bit during each acknowledge cycle until the internal
data counter counts down to 0. When the counter reaches 0, the I2C sends a NACK bit to the
transmitter. To have a NACK bit sent earlier, you must set the NACKMOD bit.
In either slave-receiver or master-receiver mode: The I2C sends a NACK bit to the transmitter during
the next acknowledge cycle on the bus. Once the NACK bit has been sent, NACKMOD is cleared.
To send a NACK bit in the next acknowledge cycle, you must set NACKMOD before the rising edge of
the last data bit.
This emulation mode bit is used to determine the state of the I2C when a breakpoint is encountered in
the high-level language debugger.
When I2C is master: If SCL is low when the breakpoint occurs, the I2C stops immediately and keeps
driving SCL low, whether the I2C is the transmitter or the receiver. If SCL is high, the I2C waits until
SCL becomes low and then stops.
When I2C is slave: A breakpoint forces the I2C to stop when the current transmission/reception is
The I2C runs free; that is, it continues to operate when a breakpoint occurs.
START condition bit (only applicable when the I2C is a master). The RM, STT, and STP bits determine
when the I2C starts and stops data transmissions (see Table 15). Note that the STT and STP bits can
be used to terminate the repeat mode.
In master mode, STT is automatically cleared after the START condition has been generated.
In slave mode, if STT is 0, the I2C does not monitor the bus for commands from a master. As a result,
the I2C performs no data transfers.
In master mode, setting STT to 1 causes the I2C to generate a START condition on the I2C-bus.
In slave mode, if STT is 1, the I2C monitors the bus and transmits/receives data in response to
commands from a master.
Table 14. I2C Mode Register (ICMDR) Field Descriptions (continued)
STOP condition bit (only applicable when the I2C is a master). The RM, STT, and STP bits determine
STP is automatically cleared after the STOP condition has been generated.
STP has been set to generate a STOP condition when the internal data counter of the I2C counts down
to 0.
Master mode bit. MST determines whether the I2C is in the slave mode or the master mode. MST is
automatically changed from 1 to 0 when the I2C master generates a STOP condition. See Table 16.
Slave mode. The I2C is a slave and receives the serial clock from the master.
Master mode. The I2C is a master and generates the serial clock on the SCL pin.
Transmitter mode bit. When relevant, TRX selects whether the I2C is in the transmitter mode or the
receiver mode. Table 16 summarizes when TRX is used and when it is a don't care.
Receiver mode. The I2C is a receiver and receives data on the SDA pin.
Transmitter mode. The I2C is a transmitter and transmits data on the SDA pin.
Expanded address enable bit.
7-bit addressing mode (normal address mode). The I2C transmits 7-bit slave addresses (from bits 6-0 of
ICSAR), and its own slave address has 7 bits (bits 6-0 of ICOAR).
10-bit addressing mode (expanded address mode). The I2C transmits 10-bit slave addresses (from bits
9-0 of ICSAR), and its own slave address has 10 bits (bits 9-0 of ICOAR).
Repeat mode bit (only applicable when the I2C is a master-transmitter). The RM, STT, and STP bits
determine when the I2C starts and stops data transmissions (see Table 15). If the I2C is configured in
slave mode, the RM bit is don't care.
Nonrepeat mode. The value in the data count register (ICCNT) determines how many data words are
received/transmitted by the I2C.
Repeat mode. Data words are continuously received/transmitted by the I2C until the STP bit is manually
set to 1, regardless of the value in ICCNT.
Digital loopback mode bit (only applicable when the I2C is a master-transmitter). This bit disables or
enables the digital loopback mode of the I2C. The effects of this bit are shown in Figure 23. Note that
DLB mode in the free data format mode (DLB = 1 and FDF = 1) is not supported.
Digital loopback mode is disabled.
Digital loopback mode is enabled. In this mode, the MST bit must be set to 1 and data transmitted out
of ICDXR is received in ICDRR after n clock cycles by an internal path, where:
n = ((I2C input clock frequency/prescaled module clock frequency) נ8)
The transmit clock is also the receive clock. The address transmitted on the SDA pin is the address in
ICOAR.
I2C reset bit. Note that if IRS is reset during a transfer, it can cause the I2C bus to hang (SDA and SCL
are in a high-impedance state).
The I2C is in reset/disabled. When this bit is cleared to 0, all status bits (in ICSTR) are set to their
The I2C is enabled.
START byte mode bit (only applicable when the I2C is a master). As described in version 2.1 of the
Philips I2C-bus specification, the START byte can be used to help a slave that needs extra time to
detect a START condition. When the I2C is a slave, the I2C ignores a START byte from a master,
regardless of the value of the STB bit.
The I2C is not in the START byte mode.
The I2C is in the START byte mode. When you set the START condition bit (STT), the I2C begins the
transfer with more than just a START condition. Specifically, it generates:
START byte (0000 0001b)
dummy acknowledge clock pulse
repeated START condition
The I2C sends the slave address that is in ICSAR.
Free data format mode bit. Note that DLB mode in the free data format mode (DLB = 1 and FDF = 1) is
not supported. See Table 16.
Free data format mode is disabled. Transfers use the 7-/10-bit addressing format selected by the XA bit.
Free data format mode is enabled.
Bit count bits. BC defines the number of bits (1 to 8) in the next data word that is to be received or
transmitted by the I2C. The number of bits selected with BC must match the data size of the other
device. Note that when BC = 0, a data word has 8 bits.
If the bit count is less than 8, receive data is right aligned in the D bits of ICDRR and the remaining D
bits are undefined. Also, transmit data written to ICDXR must be right aligned.
8 bits per data word
1 bit per data word
Table 15. Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits
ICMDR Bit
Bus Activity (1) Description
STOP condition
S-A-D..(n)..D
START condition, slave address, n data words (n = value in ICCNT)
S-A-D..(n)..D-P START condition, slave address, n data words, STOP condition (n = value in ICCNT)
S-A-D-D-D..
Repeat mode transfer: START condition, slave address, continuous data transfers
until STOP condition or next START condition
Reserved bit combination (No activity
A = Address; D = Data word; P = STOP condition; S = START condition
Table 16. How the MST and FDF Bits Affect the Role of TRX Bit
I2C State
In slave mode but not free data format TRX is a don't care. Depending on the command from the master, the I2C
responds as a receiver or a transmitter.
Function of TRX Bit
In slave mode and free data format
The free data format mode requires that the transmitter and receiver be
fixed. TRX identifies the role of the I2C:
TRX = 0: The I2C is a receiver.
TRX = 1: The I2C is a transmitter.
In master mode but not free data
format mode
TRX identifies the role of the I2C:
In master mode and free data format
Figure 23. Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
To internal I2C logic
SCL_IN
From internal I2C logic
SCL_OUT
To ARM CPU or EDMA
From ARM CPU or EDMA
Address/data
3.10 I2C Interrupt Vector Register (ICIVR)
The I2C interrupt vector register (ICIVR) is used by the CPU to determine which event generated the I2C
interrupt. Reading ICIVR clears the interrupt flag; if other interrupts are pending, a new interrupt is
generated. If there are more than one interrupt flag, reading ICIVR clears the highest priority interrupt flag.
Note that you must read (clear) ICIVR before doing another start; otherwise, ICIVR could contain an
incorrect (old interrupt flags) value.
The I2C interrupt vector register (ICIVR) is shown in Figure 24 and described in Table 17.
Figure 24. I2C Interrupt Vector Register (ICIVR)
INTCODE
LEGEND: R= Read only; -n = value after reset
Table 17. I2C Interrupt Vector Register (ICIVR) Field Descriptions
Interrupt code bits. The binary code in INTCODE indicates which event generated an I2C interrupt.
No-acknowledgment interrupt (NACK)
Register-access-ready interrupt (ARDY)
Receive-data-ready interrupt (ICRRDY)
Transmit-data-ready interrupt (ICXRDY)
Stop condition detected interrupt (SCD)
3.11 I2C Extended Mode Register (ICEMDR)
The I2C extended mode register (ICEMDR) is used to indicate which condition generates a transmit data
ready interrupt.
The I2C extended mode register (ICEMDR) is shown in Figure 25 and described in Table 18.
Figure 25. I2C Extended Mode Register (ICEMDR)
LEGEND: R/W = Read/Write; R= Read only; -n = value after reset
Table 18. I2C Extended Mode Register (ICEMDR) Field Descriptions
Backward compatibility mode bit. Determines which condition generates a transmit data ready interrupt.
The BCM bit only has an effect when the I2C is operating as a slave-transmitter.
The transmit data ready interrupt is generated when the master requests more data by sending an
acknowledge signal after the transmission of the last data.
The transmit data ready interrupt is generated when the data in ICDXR is copied to ICXSR.
3.12 I2C Prescaler Register (ICPSC)
The I2C prescaler register (ICPSC) is used for dividing down the I2C input clock to obtain the desired
prescaled module clock for the operation of the I2C.
The IPSC bits must be initialized while the I2C is in reset (IRS = 0 in ICMDR). The prescaled frequency
takes effect only when the IRS bit is changed to 1. Changing the IPSC value while IRS = 1 has no effect.
The I2C prescaler register (ICPSC) is shown in Figure 26 and described in Table 19.
Figure 26. I2C Prescaler Register (ICPSC)
Table 19. I2C Prescaler Register (ICPSC) Field Descriptions
I2C prescaler divide-down value. IPSC determines how much the I2C input clock is divided to create the
I2C prescaled module clock:
I2C clock frequency = I2C input clock frequency/(IPSC + 1)
Note: IPSC must be initialized while the I2C is in reset (IRS = 0 in ICMDR).
3.13 I2C Peripheral Identification Register (ICPID1)
The I2C peripheral identification registers (ICPID1) contain identification data (class, revision, and type) for
the peripheral.
The I2C peripheral identification register (ICPID1) is shown in Figure 27 and described in Table 20.
Figure 27. I2C Peripheral Identification Register 1 (ICPID1)
R-01h
Table 20. I2C Peripheral Identification Register 1 (ICPID1) Field Descriptions
Identifies class of peripheral.
Identifies revision of peripheral.
Current revision of peripheral.
Identifies type of peripheral.
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So it's been almost a year ago that my husband and I started our second renovation on our house. I think we started the first steps in our demolition somewhere around March. I took pictures of every little step obsessively, first of all, because it's kind of our thing now…we tear things up and then we make them pretty…or at least that is the goal.
Secondly, I wanted to share this journey with all those of you who have supported the sisters of lifefullandfrugal.com and maybe inspire those of you who are also renovating home, self, faith or life. I believe we are ALL in the midst of some form of renovation at any given point. May we have eyes to see and ears to hear the Kingdom at work in all those areas under construction!
Be sure to check out the before pictures in my first blog post on our renovation called My Anthropomorphic House.
I will definitely have a follow-up video with the finished results soon, so STAY TUNED!!!!


text:
Hotel ROI
London's Shoreditch neighborhood braces for hotel development
Oct 13, 2014 10:26am
Shoreditch, an emerging and stylish neighborhood in the East End of London, is set for a hotel building boom, reports the Londonist. Seven new hotels are slated to open in the area in the next two years, in addition to the already-opened Ace Hotel (pictured). The number of new hotel rooms for the area totals more than 1,500.
The new properties include offerings from Nobu Hospitality Group and the Gansevoort Hotel Group. These are joined by new additions from chains CitizenM and Z Hotels.
Some hotels, like the Nobu property, have already begun work, demolishing the previous buildings.
Hotel Optimization Part 3 | January 27, 2021
With 2020 behind us and widespread vaccine distribution on the horizon, the second half of the new year is looking up, but for Q1 (and most likely well into Q2) we're very much still in the thick of what has undeniably been the lowest point of the pandemic. What can you be doing now to power through and set yourself up for a prosperous 2021 and beyond? Join us at Part 3 of Hotel Optimization – A Virtual Event on January 27 from 10am – 1:05pm ET for expert panels focused on getting you back to profitability.
Local campaigners, however, have concerns over the influx of development, the Londonist writes. The concern is turning Shoreditch into a transient site.
The site quoted Rachel Munro-Peebles, co-chair of the Shoreditch Community Association, who said, "We have so many due to be built in the area, we wonder whether the council has forgotten about the people who live and work here, families, young couples… the extreme transient growth, along with the tsunami of licensed premises, may lose what we have to come to love so much."
Shoreditch currently has about 700 hotel rooms from existing properties, such as the Hoxton, Holiday Inn Express and Premier Inn.
Print/Digital

redpajama_set_name: RedPajamaCommonCrawl


The Asian Pacific American Network of Oregon (APANO) was founded in 1996, and serves as one of Oregon's leading advocates for Asian and Pacific Islander communities, especially recent immigrant and refugee populations. APANO is headquartered in Portland's Jade District, a Neighborhood Prosperity Initiative (NPI) area designated by the City of Portland in 2011. The Jade District has now been adopted by APANO, which focuses on community development work in the neighborhood around Southeast 82nd Avenue and Division Street. Three Portland neighborhoods make up the Jade District: South Tabor, Montavilla, and Powellhurst-Gilbert, with the Lents and Foster-Powell neighborhoods directly adjacent. According to APANO, the Jade District is one of the most diverse neighborhoods in the Oregon, with a large population of people of color and recent immigrants. APANO's programming focuses on four core pillars: community organizing, policy advocacy and civic engagement, leadership development, and cultural work. Cultural work is what we highlight in this story, looking at APANO's creative placemaking work which began in 2015.
The Jade-Midway Placemaking Projects are community engagement projects that cultivate community building and consciousness raising among residents that make up the Jade and Midway Districts. APANO's manager of cultural work programming, Candace Kita, says that their projects are designed to create opportunities where community members and artists can work with local organizations and small businesses to develop a series of temporary performances, exhibitions, and installations, focusing on placemaking, social justice, economic development, and community collaboration. The goal of APANO's placemaking efforts is to challenge displacement and gentrification in the rapidly changing neighborhoods around 82nd Avenue that APANO serves.
To view more videos of APANO's placemaking projects and cultural work, CLICK HERE.
Between 2015-2017, twenty-three (23) creative placemaking projects have been funded, spanning 12 neighborhoods in North, Northeast, and Southeast Portland. The projects range from interactive workshops to theatrical productions.
The Jade-Midway Placemaking Projects aim to support artists, cultural workers, and community members who lead grassroots creative projects focused on issues of transportation, anti-displacement, and other issues specific to the two districts. The projects incorporate a range of creative mediums, including music, film, poetry, visual art, and multimedia. The selected grantees participate in the Resident Artist Collaborative, a program of 4-6 workshop sessions to build an interconnected cohort of skilled cultural workers who serve as important partners in the work for social justice. Below are some highlights from three placemaking grantees.
Jennifer Phung and Tommy Larracas's Youth Photo Essay Project and Exhibition captured young people of color experiences, challenges, and their changing environments in the Jade and Midway Districts. Over the course of several months, youth from the Youth Environmental Justice Alliance (YEJA) explored and documented what it's like growing up in Portland and living in East Portland communities and captured their families' experiences of displacement and resilience. This project culminated in an "Eastside 'Just Us' Stories Photo Exhibition" which featured multimedia story-telling and creative performances by youth. Candace Kita says that this project challenges the notions people have of Portland and of young people of color. She says that the artists' work flips the dominant narrative and empower young people of color, and creates a safe space for the APANO community to celebrate their diverse identities.
Sabina Haque's Our City, Our Voice creative place-keeping project addressed the east/west disparities in Portland, highlighting that over 40 percent of Portland's children are growing up east of 82nd Avenue, in the heart of the Jade District. Haque says that 82nd Avenue is a street which historically has been a line of physical and psychological division between inner and outer east-side Portland, despite being the actual geographical center of the city. She says that this part of the city is the most diverse, underserved, and rapidly growing section of Portland. Madison High School (MHS), situated on that line, draws students who reside along and east of NE 82nd Avenue.
Haque partnered with a MHS history teacher and his twenty students to explore the historical record of how annexation, city policy, and investments in East Portland have affected the community. During eight weeks of mini workshops, students led their own round-table discussions on six major issues that impact them: direct representation at city hall, affordable housing, jobs in their neighborhood, paved roads and a more equitable city for all Portland residents. The youth created their own documents, writing, art and oral histories culminating in 400 printed zines, 100 silkscreened posters, multiple 10-foot murals, and a 100-foot text banner that asked the question: How will we as a city find a more inclusive voice and a sustainable future? This creative place-keeping project not only shed light on invisible and lost histories but gave a voice to the needs and aspirations of this vibrant neighborhood.
Hampton Rodriguez's Division Street Playing Cards project is an artistic study of the entire course of Division Street in Portland, Oregon, presenting its transportation, the human characters who make it what it is, and its businesses, street cafes, and major intersections. Through 200 or more initial sketches, with some developed as study drawings, Rodriguez created a deck of 52 fine art playing cards, each bearing a full-color illustration taken from his artistic investigation of Division Street. The project produced 50 decks of playable full-color cards. With local collaborators, exhibitions of the playing cards were held, featuring larger format prints of the card illustrations and some initial drawings and sketches, with the aim to stimulate the public and catalyze the creation of further urban art by communities along the Division Street corridor.
Images, clockwise from top right: (1-2) Sabina Haque's Annexation and Assimilartion: East 82nd Avenue project, (3-4) Jennifer Phung and Tommy Larracas' Youth Photo Essay project, (5-7) Sabina Haque's Our City, Our Voice project, (8-10) Hampton Rodriguez's Division Street Playing Cards.
The Jade District is uniquely situated along SE 82nd Avenue and is at the intersection of three rapidly gentrifying neighborhoods: Montavilla, South Tabor, and Powellhurst Gilbert. APANO staff also understand the complexity involved with their community development efforts and gentrification. As they work to make the neighborhood more livable for their community, APANO staff say that they acknowledge amenities make the Jade District more desirable for private developers, investors, and a wealthier, whiter demographic, but that doesn't end the conversation. APANO staff fight for investments and policies that improve the neighborhood in a way that supports current residents and businesses. The Jade District believes that the most vulnerable residents deserve the same public investments and resources as the rest of the city.
APANO's work will continue to address socioeconomic and environmental disparities within the Jade District. In the near future, they anticipate more parks, a bus rapid transit line, and safer streets, all of which they believe will drive up property values. This coupled with a current lack of public affordable housing in the Jade District, and desirable real estate markets makes addressing gentrification and displacement an uphill battle for the organization. There are no magic bullets in solving gentrification and displacement, however, the Jade District has developed an anti-displacement tool kit which outlines policies and practices they support and contribute to in an effort to mitigate the effects of gentrification.
The creative placemaking program highlights the organization's continued commitment to robust community engagement in all public investments with a focus on building community capacity. APANO staff say that they believe all public investments must have the support of the community. Community engagement should not be one-off exercises, but must build the community capacity to meaningfully engage in the public decision-making process over the long term.
Candace Kita says that by elevating members' stories and connecting them to issues, APANO is advancing a long-term cultural strategy to impact beliefs, actions and policies. Cultural work programming does this by centering the voices of those most impacted and silenced, resisting and shifting harmful narratives and ideas, and moving beyond defensive strategies to envisioning alternatives. APANO believes that telling their stories, speaking truths, imagining alternatives and shifting social narratives matters as a strategy for cultural change. Kita says that this strategy has captured the interest and excitement of APANO members. She and other APANO staff are working to create a vibrant space where artists and communities are shifting perceptions and re-envisioning an equitable world through the tool of creative expression.
Special thanks to APANO's Cultural Work Manager Candace Kita, for providing content and graciously sharing her work with us.


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Album Review, VCReporter
"Whiskey And Waves" Review by Chris Jay, VCReporter
"There's the power-pop factor present on tracks like "The Only Thing" and "Ain't Complaining" that are reminiscent of The Lemonheads, yet alternative country in the vein of The Jayhawks reigns supreme on "Scared of You" and "107 Songs." On the other hand, "More Than I Wanted" and "Falling Graces" are flat-out movie montage stoner rock."
"The recording, engineered by Earle Mankey (The Runaways, Concrete Blonde) is surprisingly lo-fi, which works well for the overall vibe, and there's even a guest appearance from everybody's favorite local renaissance man, Neal Casal. While post-power-pop-alt-country-desert-stoner-rock (PPPACDSR as fans like to call it) is a relatively young genre, Whiskey & Waves is its Sgt. Pepper."
— Chris Jay


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