In the break between semesters at Florence I've been busy sculpting and painting. Heres a few things I've been doing. The painting is currently in a exhibition of members' work over at the Liver Sketching Club in Liverpool.


text:
NPD: Octopath Traveler leads continued Switch success in July
Nintendo published half of July's top 10 best selling software titles
Wednesday 22nd August 2018
The NPD Group
Nintendo has shown a strong 2018 so far, and in July it showed no signs of slowing down. Not only did the company dominate software charts, but the Nintendo Switch returned to the top of hardware units and dollar sales for the first time since December.
According to the report by The NPD Group for July of 2018, overall spending on gaming hardware, software, accessories, and game cards was up 14% year-over-year, with hardware and game card growth helping account for weaker software sales. Year to date spending continued to rise across all categories, with a 17% year-over-year increase lead by accessories and game cards.
Though the NES Classic was unable to retain its title from last month as the top hardware seller in units, Nintendo still took the spot with the Nintendo Switch, which also dominated in dollar sales. Though the Switch has topped hardware charts a total of seven months since its launch in March of last year, this is the first time it's led since December.
That's not to say other hardware didn't do well. The NES Classic and SNES Classic continued to help drive hardware growth alongside the Switch and Xbox One, bringing total monthly spending up 19% year-over-year and year-to-date spending up 21% year-over-year.
Accessory and game card spending continued to see monthly record highs, rising 49% year-over-year and breaking the record for highest spending in the month of July.
Finally, software spending was down 12% year-over-year for July, though year-to-date spending was up 5%. The Nintendo Switch drove a good chunk of sales, with exclusives Octopath Traveler, Mario Kart 8, The Legend of Zelda: Breath of the Wild, Super Mario Odyssey, and Mario Tennis Aces all showing up in the top 10 titles for the month. So far for 2018, the Switch is the only console showing year-over-year dollar sales growth, up nearly 70% (that's not including digital sales). Year-to-date game sales have more than doubled year-over-year as well.
Top 10 selling games (physical and digital) for July 2018
Crash Bandicoot: N. Sane Trilogy
Call of Duty: Modern Warfare was the best-selling game of the year in the US
But Nintendo thrived in hardware and software sales at the end of its competitors' console generations
NPD: Growth of mobile gamers slows while revenue continues rising
Research firm finds number of US and Canada mobile users playing games was up just 2% last year, but revenues jumped 24% to more than $11.82 billion
Latest comments (1)
AbdulBasit Saliu Mechanic, Flowmotion Entertainment IncA year ago
GTA V is an unprecedented game and a phenomenal.

redpajama_set_name: RedPajamaCommonCrawl


Time requirements: 1 or 2 Class periods (and homework).
Materials needed: Students instructions (printed), old magazines, Bristol board, pencil crayons, felt pens, crayons, glue, scissors.
The world of the Cretaceous period was very different from the one we see today. In this activity, you will recreate the prehistoric world by making a collage.
Materials: Old magazines, Bristol board, construction paper, pencil crayons, felt pens, crayons, glue, scissors.
1. Gather magazine or hand-drawn pictures of plants, animals and other shapes that illustrate a Cretaceous environment. Try to use pictures that illustrate the environment in which the creatures of the Cretaceous would have lived. Create a collage that shows how the Cretaceous might have looked if you were there to see it. You can base your world on the information that you have found in the "Evolution in the Cretaceous" Learning Collection. You might also want to look at the "Uncrating the Cretaceous" and "Creatures of the Cretaceous" Learning Collections.
2. You may want to look at other resources such as books, magazines and what you may have seen on T.V. for more ideas.
How is today's environment different from the palaeoenvironment that you just created?
What things are still the same?


text:
Simultaneous built-in self-testing of multiple identical blocks of integrated circuitry
n identical integrated circuit blocks are simultaneously tested for defects. Each block contains m scan chains. The ith scan chains in each block are identical (i=1, 2, . . . , m). During an ith clock cycle, an ith test vector is simultaneously applied to each block's ith scan chain. The resultant n output signals are compared. If all n outputs are equal the ith scan chain is designated defect-free for all n blocks; otherwise, the ith scan chain is designated defective for one or more blocks. After sequentially repeating the test vector application, output comparison and designation process for i=1, 2, . . . , m the n blocks are designated defect-free if all m scan chains have been designated defect-free for all n blocks; otherwise, if one or more scan chains have been designated defective for one or more blocks, the n blocks are designated defective.
Arabi, Karim (Burnaby, CA)
ARABI KARIM
G01R31/3185; (IPC1-7): G01R31/28
20070027933 Resilient system partition for personal internet communicator February, 2007 Lavin et al.
20020147945 Automated analysis of interface timing measurements October, 2002 Fox et al.
20040141389 Solid state storage device and data storage method July, 2004 Banks et al.
20020170000 Test and on-board programming station November, 2002 Gorodetsky et al.
20060224913 Token with relatively moving components and separator assembly thereof October, 2006 Abe
20020083374 Identification module for a passive component of a system June, 2002 Hinds et al.
20040117540 User-space resource management June, 2004 Hahn et al.
20100083056 PROGNOSTIC DIAGNOSTIC CAPABILITY TRACKING SYSTEM April, 2010 Spier et al.
20040025083 Generating test code for software February, 2004 Nanja et al.
20090319831 Automation Network, Remote Access Server for an Automation Network and a Method for Transmitting Operating Data Between an Automation System and a Remote Computer December, 2009 Kruchinin et al.
20090292953 MODIFYING CONNECTION RECORDS November, 2009 Barghouthi et al.
CHAUDRY, MUJTABA M
OYEN, WIGGS, GREEN & MUTALA LLP (480 - THE STATION 601 WEST CORDOVA STREET, VANCOUVER, BC, V6B 1G1, CA)
1. A method of testing for defects in n identical blocks of circuitry on an integrated circuit device, each one of said blocks containing m logic gate scan chains, each ith one of said scan chains in each one of said blocks being identical, where i=1, 2, . . . , m, said method comprising: (a) during an ith clock cycle, simultaneously applying an ith test vector to said ith ones of said scan chains in each one of said blocks; (b) during said ith clock cycle, simultaneously comparing n output signals produced by said ith ones of said scan chains in each one of said blocks; (c) if said comparison reveals that all of said n output signals are equal, designating said ith ones of said scan chains defect-free for all of said n blocks; (d) if said comparison reveals that all of said n output signals are not equal, designating said ith ones of said scan chains defective for one or more of said n blocks; (e) sequentially repeating said applying, said comparing and said designating for each value of i=1, 2, . . . , m; (f) if all in of said scan chains are designated defect-free for all of said n blocks, designating said n identical blocks of circuitry defect-free; and, (g) if one or more of said scan chains are designated defective for one or more of said n blocks, designating said n identical blocks of circuitry defective.
2. A method as defined in claim 1, wherein said test vectors are random bit patterns.
3. A method as defined in claim 1, further comprising, during said ith clock cycle, generating said ith test vector as a random bit pattern.
4. A method as defined in claim 1, further comprising, during said ith clock cycle, generating said ith test vector as a pre-defined non-random bit pattern.
5. A method as defined in claim 4, wherein said pre-defined non-random bit pattern further comprises an alternating pattern of logic "0's" and logic "1's".
6. A method as defined in claim 1, further comprising masking all but a selected one of said n output signals to thereby select for defect testing only that one of said blocks which produces said selected one of said n output signals.
7. Apparatus for testing for defects in n identical blocks of circuitry on an integrated circuit device, each one of said blocks containing m logic gate scan chains, each ith one of said scan chains in each one of said blocks being identical, where i=1, 2, . . . , m, said apparatus comprising: (a) a test vector generator connected to an input of said each ith one of said scan chains in each one of said blocks to simultaneously apply an ith test vector to said each ith one of said scan chains in each one of said blocks during an ith clock cycle; (b) a comparator connected to an output of said each ith one of said scan chains in each one of said blocks to simultaneously compare n output signals produced by said ith ones of said scan chains in each one of said blocks during said ith clock cycle, said comparator producing: (i) a pass output signal designating said ith ones of said scan chains defect-free for all of said n blocks if all of said n output signals are equal; and, (ii) a fail output signal designating said ith ones of said scan chains defective for one or more of said n blocks if all of said n output signals are not equal.
8. Apparatus as defined in claim 7, said test vector generator further comprising m test vector outputs, each ith one of said test vector outputs connected to an input of said each ith one of said scan chains in each one of said blocks.
9. Apparatus as defined in claim 7, said comparator further comprising m n-input sub-comparators, each ith one of said sub-comparators having a jth input connected to an output of a one of said jth scan chains in each one of said blocks, where j=1, 2, . . . , n.
10. Apparatus as defined in claim 9, further comprising an m-input AND gate each ith one of said AND gate inputs connected to an output of an ith one of said sub-comparators.
11. Apparatus as defined in claim 7, said test vector generator further comprising a linear feedback shift register.
12. Apparatus as defined in claim 11, said linear feedback shift register further comprising m D-type flip-flops, m reconfigurable connection lines and m−1 reconfigurable exclusive-OR gates, each jth one of said connection lines having an input connected to a Q output of a jth one of said flip-flops, where j=1, 2, . . ., m, each kth one of said exclusive-OR gates having a first input connected to an output of a kth one of said connection lines and a second input connected to an output of a k+1th one of said exclusive-OR gates, where k=1, 2, . . . , m−2, an m−1th one of said exclusive-OR gates having a first input connected to an output of an m−1th one of said connection lines and a second input connected to an output of an mth one of said connection lines.
13. Apparatus as defined in claim 12, said linear feedback shift register further comprising m 2-input multiplexors, each jth one of said 2-input multiplexors excepting a j=1 one of said 2-input multiplexors having: (a) an output connected to a D input of a jth one of said flip-flops; (b) a first input connected to a {overscore (Q)} output of said jth one of said flip-flops; (c) a second input connected to a Q output of a j−1th one of said flip-flops; said j=1 one of said 2-input multiplexors having: (d) an output connected to a D input of said j=1 one of said 2-input multiplexors; (e) a first input connected to a {overscore (Q)} output of said j=1 one of said 2-input multiplexors; and, (f) a second input connected to an output of a k=1 one of said exclusive-OR gates; each one of said 2-input multiplexors having an output selectably connectible to either one of said first or said second inputs of said one of said 2-input multiplexors.
14. Apparatus as defined in claim 9, each one of said sub-comparators further comprising: (a) an n-input NOR gate, each jth one of said NOR gate inputs connected to an output of a jth one of said ith scan chains in each one of said blocks; (b) an n-input AND gate, each jth one of said AND gate inputs connected to an output of a jth one of said ith scan chains in each one of said blocks; and, (c) a 2-input OR gate having a first input connected to an output of said NOR gate and a second output connected to an output of said AND gate.
15. Apparatus as defined in claim 14, each one of said sub-comparators further comprising: (a) first and second D-type flip-flops, said first flip-flop having a D input connected to an output of said OR gate, said second flip-flop having a D input connected to a Q output of said first flip-flop; (b) a 2-input exclusive-OR gate having a first input connected to a Q output of said first flip-flop and a second input connected to a Q output of said second flip-flop; and, (c) a 2-input multiplexor having a first input connected to said output of said OR gate, a second input connected to an output of said exclusive-OR gate and an output selectably connectible to either one of said first or said second inputs of said 2-input multiplexor.
16. Apparatus as defined in claim 7, further comprising a controller for producing n block select signals, each jth one of said block select signals coupled to a jth one of said blocks, where j=1, 2, . . . , n, wherein all of said output signals produced by all of said scan chains in said jth one of said blocks are masked if said jth one of said block select signals has a first logic value and all of said output signals produced by all of said scan chains in said jth one of said blocks are not masked if said jth one of said block select signals has a second logic value opposite to said first logic value.
17. Apparatus as defined in claim 16, said controller further comprising, for each ith one of said scan chains in each jth one of said blocks, an ijth 2-input AND gate having a first input connected to said output of said ith one of said scan chains in said jth one of said blocks, and having a second input connected to said jth one of said block select signals.
[0001] This invention provides a technique for simultaneous built-in self-testing of multiple blocks of identical circuitry on an integrated circuit chip.
[0002] Production testing of integrated circuit devices to verify their correct operation is becoming a complex problem, due to the increasing number of logic gates which must be tested on each device. The number of test pattern vectors which must be applied to a modern multi-million gate device in order to screen out defective devices can exceed the capability of currently available external automatic test equipment (ATE). Unacceptably long duration, expensive testing time is consumed in applying the required large number of test vectors to such devices, thereby decreasing production capacity and adversely affecting the time required to bring such devices to market.
[0003] One prior art approach to the problem has been to fabricate built-in self-test (BIST) circuitry on each device. Such circuitry can be dedicated to specific blocks of circuitry and actuated to test all blocks simultaneously with little or no intervention by ATE. However, BIST circuitry can be difficult to implement without violating the design rules applicable to the device itself and in a manner that achieves the required test coverage, and may adversely affect the time required to bring such devices to market. Another disadvantage is that prior art BIST circuitry can consume significant integrated circuit silicon area, thereby increasing manufacturing costs and decreasing manufacturing yields.
[0004] Integrated circuits commonly contain multiple blocks of identical circuitry. Examples include multi-link or multiple channel communication and networking devices in which the same communications link is replicated inside the device to achieve better integration. This invention provides a BIST technique which facilitates rapid, efficient simultaneous testing of such multiple identical blocks. The technique produces a signature which remains constant, irrespective of the circuit under test. The technique can be used either in conjunction with ATE or on a stand-alone basis to test multiple blocks of identical circuitry on the same integrated circuit chip. The testing time and the number of test patterns required to test multiple blocks is only marginally higher than is required to test a single block.
SUMMARY OF INVENTION
[0005] The invention provides a method of testing for defects in n identical blocks of circuitry on an integrated circuit device. Each block contains m logic gate scan chains. The ith scan chains in each block are identical, where i=1, 2, . . . , m (i.e. the 1st scan chain in block 1 is identical to the 1st scan chain in each of blocks 2, . . . , n; the 2nd scan chain in block 1 is identical to the 2nd scan chain in each of blocks 2, . . . , n; etc.). During an ith clock cycle, an ith test vector is simultaneously applied to each block's ith scan chain, and the n output signals produced by those scan chains are simultaneously compared to one another. If all n output signals are equal to one another then the ith scan chain is designated defect-free for all n blocks; otherwise, the ith scan chain is designated defective for one or more of the n blocks. After sequential repetition of the above-described test vector application, output comparison and designation process for each value of i=1, 2, . . . , m the n identical blocks of circuitry are designated defect-free if all m scan chains have been designated defect-free for all of the n blocks; otherwise, if one or more scan chains have been designated defective for one or more of the n blocks, then the n identical blocks of circuitry are designated defective.
[0006] The invention also provides an apparatus for testing for defects in n identical blocks of circuitry on an integrated circuit device. Each block again contains m logic gate scan chains. The ith scan chains in each block are identical, where i=1, 2, . . . , m. A test vector generator is connected to the input of each ith scan chain in each block to simultaneously apply an ith test vector to each ith scan chain in each block during an ith clock cycle. A comparator is connected to the output of each ith scan chain in each block to simultaneously compare the n output signals produced by those scan chains during the ith clock cycle. The comparator produces a "pass" output signal designating the ith scan chain defect-free for all n blocks if all n output signals are equal to one another, or produces a "fail" output signal designating the ith scan chain defective for one or more of the n blocks if all n output signals are not equal to one another. The test vector generator may be configured to produce m test vector outputs, with each ith test vector output connected to an input of each ith scan chain in each block. The comparator can be configured as m n-input sub-comparators, with each ith sub-comparator having a jth input connected to an output of a jth one of the ith scan chains in each block, where j=1, 2, . . . , n.
[0007] Each sub-comparator includes an n-input NOR gate with each jth NOR gate input connected to the output of a jth one of the ith scan chains in each block; an n-input AND gate with each jth AND gate input connected to the output of a jth one of the ith scan chains in each block; and, a 2-input OR gate having a first input connected to the NOR gate's output and a second output connected to the AND gate's output. Each sub-comparator can further include first and second D-type flip-flops, with the first flip-flop's D input connected to the OR gate's output and the second flip-flop's D input connected to the first flip-flop's Q output; a 2-input exclusive-OR gate having a first input connected to the first flip-flop's Q output and a second input connected the second flipflop's Q output; and, a 2-input multiplexor having a first input connected to the OR gate's output, a second input connected to the exclusive-OR gate's output, and an output selectably connectible to either one of the 2-input multiplexor's first or second inputs.
[0008] An m-input AND gate is provided, with each ith AND gate input connected to an output of an ith one of the sub-comparators. The AND gate's output constitutes a single pass/fail indication for all of the ith scan chains in each block simultaneously.
[0009] The test vector generator can be a linear feedback shift register having m D-type flip-flops, m reconfigurable connection lines and m−1 exclusive-OR ("XOR") gates. Each jth connection line has an input connected between a Q output of a jth one of the flip-flops, where j=1, 2, . . . , m. Each kth XOR gate has a first input connected to an output of a kth one of the connection lines, and a second input connected to an output of a k+1th one of the XOR gates, where k=1, 2, . . . , m−2. The m−1th XOR gate's first and second inputs are respectively connected to the outputs of the m−1th and mth connection lines.
[0010] The linear feedback shift register may also have m 2-input multiplexors. Each jth 2-input multiplexor (excepting the j=1 2-input multiplexor) has an output connected to the D input of the jth flip-flop, a first input connected to the {overscore (Q)} output of the jth flip-flop, and a second input connected to the Q output of the j−1th flip-flop. The j=1 2-input multiplexor has an output connected to the D input of the j=1 2-input multiplexor, a first input connected to the {overscore (Q)} output of the j=1 2-input multiplexor, and a second input connected to an output of the k=1 XOR gate. The output of each 2-input multiplexor is selectably connectible to either one of that multiplexor's first or second inputs.
[0011] FIG. 1 is a block diagram schematically depicting n identical circuit blocks configured for testing in accordance with the invention.
[0012] FIG. 2 provides further details of the FIG. 1 block and comparator circuitry.
[0013] FIG. 3 is a logic circuit diagram of a linear feedback shift register (LFSR) for generating test and flush vectors in accordance with the invention.
[0014] FIG. 4 is a logic circuit diagram of a preferred sub-comparator.
[0015] Throughout the following description, specific details are set forth in order to provide a more thorough understanding of the invention. However, the invention may be practiced without these particulars. In other instances, well known elements have not been shown or described in detail to avoid unnecessarily obscuring the invention. Accordingly, the specification and drawings are to be regarded in an illustrative, rather than a restrictive, sense.
[0016] FIGS. 1 and 2 depict multiple identical blocks 1, 2, . . . , n of identical circuitry to be tested in accordance with the invention. Each one of blocks 1, 2, . . . , n is configured to contain multiple scan chains 1, 2, . . . , m of interconnected logic gates, such that the first scan chain in block 1 is identical to the first scan chain in each of blocks 2, . . . , n; the second scan chain in block 1 is identical to the second scan chain in each of blocks 2, . . . , n; and so on through to the mth scan chain in block 1 which is identical to the mth scan chain in each of blocks 2, . . . , n.
[0017] More particularly, as seen in FIG. 2, block 1 contains, between input SI11 and output SO11, a first scan chain comprising a plurality of series-connected logic gates S11A, S11B, S11C, . . . ; block 2 contains, between input SI21 and output SO21, an identical first scan chain comprising a plurality of identical series-connected logic gates S21A, S21B, S21C, . . . ; and, block n contains, between input SIn1 and output SOn1, another identical first scan chain comprising a plurality of series-connected logic gates Sn1A, Sn1B, Sn1C, . . . . Similarly, block 1 contains, between input SI12 and output SO12, a second scan chain comprising a plurality of series-connected logic gates S12A, S12B, S12C, . . . ; block 2 contains, between input SI22 and output SO22, an identical second scan chain comprising a plurality of identical series-connected logic gates S22A, S22B, S22C, . . . ; and, block n contains, between input SIn2 and output SOn2, another identical second scan chain comprising a plurality of series-connected logic gates Sn2A, Sn2B, Sn2C, . . . . The foregoing structure is repeated for each scan chain in each block, culminating in the final (mth) scan chain, such that block 1 contains, between input SI1m and output SO1m, an mth scan chain comprising a plurality of series-connected logic gates S1mA, S1mB, S1mC, . . . ; block 2 contains, between input SI2m and output SO2m, an identical mth scan chain comprising a plurality of identical series-connected logic gates S2mA, S2mB, S2mC, . . . ; and, block n contains, between input SInm and output SOnm, another identical mth scan chain comprising a plurality of series-connected logic gates SnmA, SnmB, SnmC, . . . .
[0018] A single, on-chip, source of test vectors, such as linear feedback shift register (LFSR) 10 (FIG. 1) drives each block such that a first test vector is simultaneously applied to each one of the first scan chains in each one of blocks 1, 2, . . . , n; a second test vector is then simultaneously applied to each one of the second scan chains in each one of blocks 1, 2, . . . , n; and so on such that, finally, an mth test vector is simultaneously applied to each one of the mth scan chains in each one of blocks 1, 2, . . . , n. This is accomplished by tying the inputs SI11 , SI21, . . . , SIn1 of each one of the first scan chains together to provide a single input SI1 (FIG. 2) to which LFSR 10 applies the first test vector; tying the inputs SI12, SI22, . . . , SIn2 of each one of the second scan chains together to provide a single input SI2 to which LFSR 10 applies the second test vector; and so on culminating in tying together of the inputs SI1m, SI2m, . . . , SInm of each one of the mth scan chains to provide a single input SIm to which LFSR 10 applies the mth test vector.
[0019] The output signals produced by each one of blocks 1, 2, . . . , n are input to a comparator 12 as shown in FIG. 2. As seen in FIG. 2, comparator 12 consists of m identical n-input sub-comparators 14, 16, . . . , 18. The outputs SO11, SO21, . . . , SOn1 of each one of the first scan chains are respectively connected to the inputs of first sub-comparator 14, which simultaneously compares the output signals produced by each one of the first scan chains and produces a "pass" (i.e. logic "1") output signal at first sub-comparator 14's output SO1 if the output signals produced by each one of the first scan chains are all identical to one another. Otherwise, if the output signals produced by each one of the first scan chains are not all identical to one another, a "fail" (i.e. logic "0") output signal is produced at first sub-comparator 14's output SO1. The outputs SO12, SO22, . . . , SOn2 of each one of the second scan chains are respectively connected to the inputs of second sub-comparator 16, which simultaneously compares the output signals produced by each one of the second scan chains and produces a "pass" output signal at second sub-comparator 16's output SO2 if the output signals produced by each one of the second scan chains are all identical to one another. Otherwise, if the output signals produced by each one of the second scan chains are not all identical to one another, a "fail" output signal is produced at second sub-comparator 16's output SO2. The foregoing is repeated for each group of corresponding scan chains, culminating in connection of the outputs SO1m, SO2m, . . . , SOnm of each one of the mth scan chains to the respective inputs of the mth sub-comparator 18, which simultaneously compares the output signals produced by each one of the mth scan chains and produces a "pass" output signal at mth sub-comparator 18's output SOm if the output signals produced by each one of the mth scan chains are all identical to one another. Otherwise, if the output signals produced by each one of the mth scan chains are not all identical to one another, a "fail" output signal is produced at mth sub-comparator 18's output SOm. Comparator 12 also includes an m-input AND gate 20. The outputs SO, SO2, . . . , SOm of each one the m sub-comparators 14, 16, . . . , 18 are respectively connected to the inputs of AND gate 20. Accordingly, if each one of the m sub-comparators produces a "pass" output signal then AND gate 20 also produces a "pass" output signal at its output; whereas, if any one or more of the m sub-comparators produces a "fail" output signal then AND gate 20 also produces a "fail" output signal at its output.
[0020] Since the first scan chains in each one of blocks 1, 2, . . . , n are assumed to be identical, the above-described simultaneous application of the first test vector to each of the first scan chains should result in simultaneous production of identical signals at the first scan chain outputs SO11, SO21, . . . , SOn1, which should in turn (i.e. in the absence of defects in the logic gates comprising each one of the first scan chains) result in production of a "pass" output signal by sub-comparator 14, thereby indicating an absence of defects in the logic gates comprising each one of the first scan chains. Similarly, since the second scan chains in each one of blocks 1, 2, . . . , n are assumed to be identical, the above-described simultaneous application of the second test vector to each of the second scan chains should (i.e. in the absence of defects in the logic gates comprising each one of the second scan chains) result in simultaneous production of identical signals at the second scan chain outputs SO12, SO22, . . . , SOn2, which should in turn result in production of a "pass" output signal by sub-comparator 16 thereby indicating an absence of defects in the logic gates comprising each one of the second scan chains; and so on throughout and including the mth scan chains, such that production of a "pass" output signal by sub-comparator 18 indicates an absence of defects in the logic gates comprising each one of the mth scan chains. Accordingly, production of a "pass" output signal by AND gate 20 is indicative of an absence of defects in the logic gates comprising all of blocks 1, 2, . . . , n. However, a defect in any one of the logic gates comprising any one of scan chains 1, 2, . . . , m which disrupts the defective gate's operation so as to result in production of a "fail" output signal by any one of the m sub-comparators will in turn result in production of a "fail" output signal by AND gate 20, thereby indicating the presence of a logic gate defect somewhere within one of blocks 1, 2, . . . , n.
[0021] As shown in FIG. 1, control logic 22 can be provided to selectively apply "block select" control signals BSb1, BSb2, . . . , BSbn to blocks 1, 2, . . . , n respectively in order to enable or disable selected blocks. This can be accomplished as shown in FIG. 2 by providing a first 2-input AND gate G11, G21, . . . , Gn1 at the output of each one of the respective first scan chains; providing a second 2-input AND gate G12, G22, . . . , Gn2 at the output of each one of the respective second scan chains; and so on, culminating in provision of an mth 2-input AND gate G1m, G2m, . . . , Gnm at the output of each one of the respective mth scan chains. The output of the final logic gate S11k1 in block 1's first scan chain is connected to one of the inputs of AND gate G11; and, the other input of AND gate G11 is connected to an output of control logic 22 at which control signal BSb1 is produced. The BSb1 output of control logic 22 is also connected to one of the inputs of each one of block 1's AND gates G12, . . . , G1m; with the other inputs of each one of AND gates G12, . . . , G1m being connected to the final logic gates S12k2, . . . , S1mkm in each of block 1's second through mth scan chains respectively. Similarly, in the case of block 2, the BSb2 output of control logic 22 is connected to one of the inputs of each one of block 2's AND gates G21, G22, . . . , G2m; with the other inputs of each one of AND gates G21, G22, . . . , G2m being connected to the final logic gates S21k1, S22k2, . . . , S2mkm in each of block 2's first through mth scan chains respectively. The foregoing is repeated for each block, culminating, in the case of block n, with the BSbn output of control logic 22 connected to one of the inputs of each one of block n's AND gates Gn1, Gn2, . . . , Gnm; with the other inputs of each one of AND gates Gn1, Gn2, . . . , Gnm being connected to the final logic gates Sn1k1, Sn2k2, . . . , Snmkm in each of block n's first through mth scan chains respectively. (The subscripts k1, k2, . . . , km respectively correspond to the number of logic gates in each of the first through mth scan chains.)
[0022] By applying a logic "1" BSb1 control signal to block 1, control logic 22 selectively enables all of block 1's first through mth scan chains, such that the signals produced at block 1's outputs SO11, SO12, . . . , SO1m are respectively representative of the results of applying the first through mth test vectors to block 1's inputs SI11, SI12, . . . , SI1m. Conversely, by applying a logic "0" BSb1 control signal to block 1, control logic 22 selectively disables all of block 1's first through mth scan chains, masking the output signals produced at each one of block 1's outputs SO11, SO12, . . . , SO1m such that they have no effect on sub-comparators 14, 16, . . . , 18. Similarly, by applying a logic "1" BSb2 control signal to block 2, control logic 22 selectively enables all of block 2's first through mth scan chains, such that the signals produced at block 2's outputs SO21, SO22, . . . , SO2m are respectively representative of the results of applying the first through mth test vectors to block 2's inputs SI21, SI22, . . . , SI2m; or, by applying a logic "0" BSb2 control signal to block 2, control logic 22 selectively disables all of block 2's first through mth scan chains, masking the output signals produced at each one of block 2's outputs SO21, SO22, . . . , SO2m such that they have no effect on sub-comparators 14, 16, . . . , 18. The same control capability is available for each one of blocks 1, 2, . . . , n such that by applying a logic "1" BSbn control signal to block n, control logic 22 selectively enables all of block n's first through mth scan chains, such that the signals produced at block n's outputs SOn1, SOn2, . . . , SOnm are respectively representative of the results of applying the first through mth test vectors to block n's inputs SIn1, SIn2, . . . , SInm; or, by applying a logic "0" BSbn control signal to block n, control logic 22 selectively disables all of block n's first through mth scan chains, masking the output signals produced at each one of block n's outputs SOn1, SOn2, . . . , SOnm such that they have no effect on sub-comparators 14, 16, . . . , 18.
[0023] It is accordingly possible to individually test any selected one of blocks 1, 2, . . . , n by applying a logic "1" control signal to that one block in order to enable it, and by applying logic "0" control signals to all of the other blocks in order to disable them by masking their output signals such that they have no effect on sub-comparators 14, 16, . . . , 18, and by employing a predefined set of first through mth test vectors such that the block being tested produces a predefined (hence recognizable) set of output signals in the absence of defects in that block. Alternatively, by simultaneously applying logic "1" BSb1, BSb2, . . . , BSbn control signals to each one of blocks 1, 2, . . . , n control logic 22 facilitates simultaneous testing of all of blocks 1, 2, . . . , n by passing through each scan chain's terminating AND gate to sub-comparators 14, 16, . . . , 18 the results of applying the first through mth test vectors to the corresponding first through mth scan chains in each of blocks 1, 2, . . . , n.
[0024] It is preferable to initially test comparator 12 and its connections to blocks 1, 2, . . . , n to verify correct operation thereof, before commencing testing of blocks 1, 2, . . . , n for defects. This is achieved by sequentially individually selecting each block (i.e. by applying a logic "1" control signal to each block in turn, while simultaneously applying logic "0" control signals to all of the other blocks, as explained above); and, while each block is selected, applying a predefined set of non-random bit pattern "flush" vectors to the input of each one of the selected block's first through mth scan chains in order to test the integrity of each scan chain, including the connections between the logic gates comprising the respective scan chains (together with each scan chain's terminating 2-input AND gate), the connections between the scan chains' outputs and the sub-comparators' inputs, and the sub-comparators themselves. The preferred flush vector comprises an alternating pattern of logic "0's" and logic "1's" (i.e. 01010101 . . . ). Appropriate scan enable signals are applied to each scan chain while the flush vectors are input to the scan chains, to operate each scan chain in shift mode during the above-described initial comparator and connection test phase. When operating in shift mode, each scan chain passes the applied input signal through the scan chain's logic gates without alteration. Accordingly, in the absence of defects, and after k clock cycles, where k is the number of logic gates in the lengthiest scan chain in the block being tested (i.e. k is the largest integer in the set {k1, k2, . . . , km}) the output signals produced by each scan chain in that block should be simultaneously identical to the input signal (i.e. 01010101 . . . ). Furthermore, if each scan chain successfully produces simultaneously identical output signals (i.e. 01010101 . . . ) after k clock cycles, and if comparator 12 (consisting of m sub-comparators 14, 16, . . . , 18 plus AND gate 20) is free of defects, then a "pass" signal is continuously produced at the output of AND gate 20, thereby confirming defect free operation of comparator 12, the scan chains and their respective interconnections as described above. Production of a "fail" signal at the output of AND gate 20 indicates the presence of at least one defect in comparator 12, the scan chains, or their respective interconnections as described above.
[0025] If the above-described initial comparator and connection test phase is successfully passed, then defect testing of blocks 1, 2, . . . , n can proceed. This is accomplished by simultaneously selecting all of blocks 1, 2, . . . , n (i.e. by causing control logic 22 to simultaneously apply logic "1 " BSb1, BSb2, . . . , BSbn control signals to each of blocks 1, 2, . . . , n); and, simultaneously applying the first test vector to each one of the first scan chains in each block, simultaneously applying the second test vector to each one of the second scan chains in each block, and so on including simultaneously applying the mth test vector to each one of the mth scan chains in each block.
[0026] The test vectors are random patterns produced by LFSR 10, as hereinafter explained. Because a single (i.e. "first") test vector is simultaneously applied to all of the first scan chains, and because the first scan chains are identical to one another, an absence of defects throughout all of the first scan chains results in simultaneous production of identical output signals at the SO11, SO21, . . . , SOn1 outputs of each of the first scan chains, thus continuously producing a "pass" signal at the SO1 output of sub-comparator 14, and thereby simultaneously confirming defect free operation of all of the first scan chains. Similarly, because a single (i.e. "second") test vector is simultaneously applied to all of the second scan chains, and because the second scan chains are identical to one another, an absence of defects throughout all of the second scan chains results in simultaneous production of identical output signals at the SO12, SO22, . . . , SOn2 outputs of each of the second scan chains, thus continuously producing a "pass" signal at the SO2 output of sub-comparator 16, and thereby simultaneously confirming defect free operation of all of the second scan chains. Operation is the same for all remaining scan chains, throughout and including the mth scan chain: because a single (i.e. "mth") test vector is simultaneously applied to all of the mth scan chains, and because the mth scan chains are identical to one another, an absence of defects throughout all of the mth scan chains results in simultaneous production of identical output signals at the SOm, SO2m, . . . , SOnm outputs of each of the mth scan chains, thus continuously producing a "pass" signal at the SOm output of sub-comparator 18, and thereby simultaneously confirming defect free operation of all of the mth scan chains. An absence of defects throughout all of scan chains 1, 2, . . . , m in all of blocks 1, 2, . . . , n thus results in simultaneous input of m "pass" signals to AND gate 20, which in turn continuously produces a "pass" output signal, thereby simultaneously confirming defect free operation of all of blocks 1, 2, . . . , n.
[0027] Construction and operation of LFSR 10 is now described with reference to FIG. 3. LFSR 10 incorporates a series of m flip-flops FF1, FF2, . . . , FFm where m is the number of scan chains in each of blocks 1, 2, . . . , n as previously explained. The outputs of m 2-input multiplexors are respectively connected to the flip-flops' D inputs (i.e. the output of first multiplexor 24 is connected to the D input of FF1, the output of second multiplexor 26 is connected to the D input of FF2, and so on culminating in connection of the output of mth multiplexor 28 to the D input of FFm). FF1's Q output is connected to the "1" input of multiplexor 26; and, FF1's {overscore (Q)} output is fed back to the "0" input of FF1's input multiplexor 24. Application of a logic "0" signal to multiplexor 24's select ("S") terminal causes multiplexor 24 to output the signal applied to multiplexor 24's "0" input; and, application of a logic "1" signal to multiplexor 24's select ("S") terminal causes multiplexor 24 to output the signal applied to multiplexor 24's "1" input. FF2's Q output is connected to the "1" input of an input multiplexor (not shown) connected to the D input of a third flip-flop (not shown); and, FF2's {overscore (Q)} output is fed back to the "0" input of FF2's input multiplexor 26. Application of a logic "0" signal to multiplexor 26's select ("S") terminal causes multiplexor 26 to output the signal applied to multiplexor 26's "0" input; and, application of a logic "1" signal to multiplexor 26's select ("S") terminal causes multiplexor 26 to output the signal applied to multiplexor 26's "1" input. This structure is repeated, culminating with connection of the Q output of the m−1st flip-flop (not shown) to the "1" input of FFm's input multiplexor 28 and with FFm's {overscore (Q)} output being fed back to the "0" input of FFm's input multiplexor 28. Application of a logic "0" signal to multiplexor 28's select ("S") terminal causes multiplexor 28 to output the signal applied to multiplexor 28's "0" input; and, application of a logic "1" signal to multiplexor 28's select ("S") terminal causes multiplexor 28 to output the signal applied to multiplexor 28's "1" input. A common clock signal "Clk" is applied to each of flip-flops FF1, FF2, . . . , FFm, as shown. Simultaneous application of logic "0" signals to the select terminals of all m multiplexors causes LFSR 10 to produce the aforementioned flush vector. Simultaneous application of logic "1" signals to the select terminals of all m multiplexors causes LFSR 10 to produce a random test vector.
[0028] The Q outputs of each of flip-flops FF1, FF2, . . . , FFm−1, FFm are tapped and fed back through a chain of reconfigurable connection lines 30, 32, . . . , 34, 36 and reconfigurable exclusive-OR ("XOR") gates 38, 40, . . . , 42 to the "1" input of multiplexor 24. This can be accomplished in well known fashion by meamns of suitable computer programming. The connection line coefficients C1, C2, . . . , Cm have binary values (i.e. either "0" or "1"). If a particular connection line coefficient has the value "0" then the corresponding connection line does not exist, nor does the associated XOR gate exist. For example, if connection line 30's coefficient C1=0 then neither connection line 30 nor its associated XOR gate 38 exists. If a particular connection line coefficient has the value "1" then the corresponding connection line exists, as does the associated XOR gate. For example, if connection line 30's coefficient C1=1 then connection line 30 exists, as does XOR gate 38. To simplify matters, the following discussion assumes that all of the connection lines and XOR gates shown or implicit in FIG. 3 do in fact exist.
[0029] Consider the case in which logic "1" signals are applied to the select terminals of all m multiplexors to cause LFSR 10 to produce random test vectors. FFm's Q output is tapped and applied to reconfigurable connection line 36. The Q output of the m−1st flip-flop (i.e. FFm−1 not shown) is tapped and applied to reconfigurable connection line 34. XOR gate 42 exclusive-ORs the outputs of FFm and FFm−1 and feeds the result back to to an immediately downstream (i.e. to the left, as viewed in FIG. 3) XOR gate (not shown) which exclusive-ORs XOR gate 42's output result with a component derived from an m−2nd flip-flop (not shown). Ultimately, XOR gate 40 exclusive-ORs the immediately upstream (i.e. to the right, as viewed in FIG. 3) feedback result with a component derived from FF2; and, XOR gate 38 exclusive-ORs gate 40's output with a component derived from FF1.
[0030] Now consider the case in which logic "0" signals are applied to the select terminals of all m multiplexors to cause LFSR 10 to produce the aforementioned flush vector. Feedback of each flip-flop's {overscore (Q)} output to the "0" input of the same flip-flop's input multiplexor results in production at each flip-flop's Q output, during the next clock cycle, of the logic inverse of the signal at the flip-flop's {overscore (Q)} output. Thus, if FF1's {overscore (Q)} output is "1" during the current clock cycle then FF1's Q output is "0" during the current clock cycle, FF1's Q output is "1" and FF1's {overscore (Q)} output is "0" during the next clock cycle, etc. Accordingly, an alternating pattern of logic "0's" and logic "1's" (i.e. 01010101 . . . ) is produced at each flip-flop's Q output.
[0031] Overall, when configured to produce random test vectors, LFSR 10 generates a random pattern described by the polynomial:
P(x)=1+C1x+C2x2+ . . . +Cm−1xm−1+Cmxm
[0032] For further details of the construction and operation of suitable LFSRs, see: Michael John and Sebastian Smith, "Application-Specific Integrated Circuits", Addison Wesley Longman, Inc., 1997, pp. 771-773; or, Clive Maxfield, "The Ouroboros of the Digital Consciousness: Linear-Feedback-Shift Registers", EDN Jan. 4, 1996, Cahners Business Information division of Reed Elsevier, Inc.
[0033] FIG. 4 depicts the preferred embodiment of each of sub-comparators 14, 16, . . . , 18. As previously explained, if n identical blocks are being tested, each sub-comparator receives, in parallel, n scan chain output signals from scan chain outputs SO1i, SO2i, . . . , SOni respectively, where i=1, 2, . . . , m indicates which one of the 1st, 2nd . . . , or mth groups of scan chains is processed by the particular sub-comparator. The n scan chain output signals are input, in parallel, to n-input NOR gate 44 and to n-input AND gate 46. The outputs of NOR gate 44 and AND gate 46 are in turn connected to the respective inputs of 2-input OR gate 48. If the n scan chain output signals are simultaneously identical to one another, then OR gate 48 produces a logic "1" (i.e. "pass") output signal; otherwise, OR gate 48 produces a logic "0" (i.e. "fail") output signal. Operation in the defect testing mode is accomplished by applying a logic "1" signal to multiplexor 56's select ("S") terminal, such that OR gate 48's output signal appears at the output of multiplexor 56 as the sub-comparator's output signal.
[0034] Operation in the initial comparator and connection test phase is accomplished by applying a logic "0" signal to multiplexor 56's select terminal, such that the sub-comparator's output signal reflects processing of OR gate 48's output signal through flip-flops 50, 52 and exclusive-OR ("XOR") gate 54. More particularly, OR gate 48's output signal is applied to the D input of flip-flop 50. As previously explained, a flush vector alternating pattern of logic "0's" and logic "1's" (i.e. 01010101 . . . ) is input to the scan chains, which operate in shift mode to pass the flush vector without alteration such that, in the absence of scan chain defects, the output signals produced by each scan chain are simultaneously identical to the flush vector input signal (i.e. 01010101 . . . ). In the absence of scan chain defects, OR gate 48's output signal will also be identical to the flush vector input signal (i.e. 01010101 . . . ). The Q output of flip-flop 50 is connected to the D input of flip-flop 52 and to one of the inputs of XOR gate 54. The Q output of flip-flop 52 is connected to the other input of XOR gate 54. Consequently, if the flush vector input signal (i.e. 01010101 . . . ) is applied to the D input of flip-flop 50 (i.e. in the absence of scan chain defects) then XOR gate 54 continuously produces a logic "1" (i.e. "pass") output signal, which appears at the output of multiplexor 56 as the sub-comparator's output signal.
[0035] It can thus be understood that the invention enables rapid, parallel testing of multiple blocks of identical circuitry on an integrated circuit chip. The required number of test vectors is reduced, by simultaneously applying a single 1st test vector to each one of the first scan chains in each one of blocks 1, 2, . . . , n; then simultaneously applying a single 2nd test vector to each one of the second scan chains in each one of blocks 1, 2, . . . , n; and so on, until a single mth test vector is finally simultaneously applied to each one of the mth scan chains in each one of blocks 1, 2, . . . , n. Thus, the invention requires no more test vectors than would be required to test a single block (plus the flush vector used to test the scan chains and comparator). More complex prior art techniques involving multiple-input shift registers, signature compaction, etc. are not required. A relatively simple linear feedback shift register (i.e. LFSR 10) serves as an on-chip pattern generator and is configurable to produce all of the test and flush vectors required for defect testing in accordance with the invention (i.e. LFSR 10 can produce either random test vectors, or a deterministic flush vector).
[0036] The invention does not require the circuit under test to produce a unique "signature" output for the circuit to "pass"; rather, continuous production of a logic "1" (i.e. "pass") output by AND gate 20 simultaneously confirms defect free operation of all of blocks 1, 2, . . . , n. A further important advantage is the invention's ability to produce a pass/fail indication during each clock cycle. For example, if, during a 1st clock cycle, a 1st test vector is simultaneously applied to each one of the 1st scan chains in each one of blocks 1, 2, . . . , n then AND gate 20 outputs either a logic "1" indicating defect free operation of all of those 1st scan chains, or a logic "0" indicating defective operation of at least one of those 1st scan chains; then, during a 2nd clock cycle, a 2nd test vector is simultaneously applied to each one of the 2nd scan chains in each one of blocks 1, 2, . . . , n causing AND gate 20 to output either a logic "1" indicating defect free operation of all of those 2nd scan chains, or a logic "0" indicating defective operation of at least one of those 2nd scan chains; etc.
[0037] Further advantages of the invention include the ability to individually test any selected block for defects; the ability to pre-test the scan chains and comparator circuitry for defects; and, the fact that identical pass/fail test results are produced irrespective of whether the invention operates in defect testing mode or in the initial comparator and connection test mode.
[0038] As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof. For example, instead of using m discrete sub-comparators 14, 16, . . . , 18 as described above, one could alternatively use a comparator-multiplexor-detector structure. The comparator can be configured to compare the results from different blocks, with one multiplexor being used to bypass the comparator for operation in the initial comparator and connection test phase, and a second multiplexor being used for operation in defect testing mode to couple the scan chain output signals of a selected block to the comparator. A flush pattern detector (two flip-flops and an XOR gate) can be coupled to the second multiplexor's output detector. As another example, any one of a variety of prior art linear feedback shift register (LFSR) structures capable of producing flush and random test vectors as described herein can be used. Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.
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text:
Wisdom in Wound Care Webinar Series: Venous Leg Ulcers
Feb 16, 2022, 12:00pm - 12:45pm
Venous leg ulcer
The Wisdom in Wound Care Webinar Series offers 11 monthly, 45-minute webinars hosted by RNAO and facilitated by wound care experts in Ontario. The webinar series will cover best practices in relation to acute and chronic wound prevention, assessment and treatment.
The mission of the webinar series is to reduce the physiological, psychological and the fiscal burden of wounds throughout Ontario by building clinical expertise using best practices related to wound care.
By the end of the webinar series, attendees will be able to explain:
the appropriate best practices as they pertain to varying wound care issues; and
how they can influence optimal person-centered outcomes.
Recordings of previous sessions are available to watch.
The webinar series will cover a variety of topics including:
Date/Time Topic
May 26, 2021, 12 – 12:45 p.m. ET COVID-19 related pressure injuries
June 16, 2021, 12 – 12:45 p.m. ET Wound bed preparation
July 28, 2021, 12 – 12:45 p.m. ET Wound bed assessment
Aug. 25, 2021, 12 – 12:45 p.m. ET Skin Tears
Sept. 29, 2021, 12 – 12:45 p.m. ET Incontience Associated Dermatits and Skin Frailty
Oct. 13, 2021, 12 – 12:45 p.m. ET Nutrition and wound management
Nov. 24, 2021, 12 – 12:45 p.m. ET Pressure Injury Assessment
Jan. 19, 2022, 12 – 12:45 p.m. ET Pressure Injury Management in acute care
Feb. 16, 2022, 12 – 12:45 p.m. ET Venous Leg Ulcers
March 30, 2022, 12 – 12:45 p.m. ET Wound Dressings
April 27, 2022, 12 – 12:45 p.m. ET Diabetic Foot Ulcers
Fee to attend all 11 sessions:
Non-member price: $173.13 + $22.51 = $195.64
Member Price: $138.50 + $18.00 = $156.51
Fee to attend per session:
Non-members: $17.50 + HST = $19.76
Members: $15.00 + HST = $16.95


Davina Merry is an artist from the Highlands of Scotland, not far from Beauly. She has written short stories for her own pleasure all her life, but this novel set in the period from 1920 to 1980 is set to change all that.
This is a story of The Tarnoch family of Merlinstone House, and the comings and goings over three generations.
198 pages hardback. 16 x 24 cm.


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As a driver, it's only natural for you to prioritize safety when it comes to choosing your next vehicle. Aluminum is a lightweight metal, so it will reduce the weight of your vehicle. This can help to make your vehicle easier to handle on the road by providing you with better braking and steering. Aluminum also absorbs shock better than steel, so it will help to protect you from harm in the event of an accident.
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text:
Meet the Labrador retriever searching for survivors in Mexico City
By Yaron Steinbuch
September 22, 2017 | 1:49pm | Updated September 22, 2017 | 3:24pm
Frida, a rescue dog working to save people from the devastation of an earthquake in Mexico City. Twitter
There is indeed a Frida in Mexico City, but she is not a girl trapped under a flattened school – but rather a furry, four-legged, national hero.
Frida, a member of the Mexican navy, is a 7-year-old Labrador retriever who has detected 52 people – a dozen alive – in various natural disasters, the LA Times reported.
Frida, a rescue dog in Mexico City.Twitter
After a magnitude 8.1 earthquake struck the country two weeks ago, Frida located the body of a police officer in Juchitan.
Her handlers hope Frida – who is named after Mexican painter Frida Kahlo — will sniff out survivors from the Tuesday temblor that killed 273 people.
Fourteen other pooches have also been deployed to search for people in Mexico City — but none have as many Twitter followers as Frida.
A tweet about her by the Mexican navy garnered more than 4,000 retweets and nearly 7,000 likes, with people hailing her as a hero and offering to send her more boots to keep her paws safe.
"She should rest a little. She has worked a lot. God take care of you, your work is not easy," one fan tweeted.
"Frida for president," another declared.
And yet another admirer said: "Now you know why they say that dogs are man's best friend."
Some people caught up in the adulation thought that all 52 people Frida has detected were alive, or that she had detected all of them in Mexico City, the paper reported.
On Tuesday, Frida was dispatched to the flattened Enrique Rebsamen school, where emergency workers found 11 children alive. But 25 people, including 19 children, were found dead.
The nation was transfixed Thursday on TV images from the site as rescuers tried desperately to reach a 12-year-old girl dubbed "Frida Sofia."
But reports about the girl — who was believed to have wiggled her fingers and then contacted rescuers by phone — turned out to be false.
Dog handler Israel Arauz Salinas said Frida needed a nap and a drink of electrolytes-infused water during the exhausting search with the help of her two Belgian Malinois partners — Evil and Echo.
Filed under dogs , mexico , mexico city earthquake , natural disasters , rescues
Rand Paul 'won't be bribed or bullied' into backing new he...


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The House approved the bill 110-4. It now goes to Gov. Pat McCrory for his signature.
A national charter advocacy group, the National Association of Charter School Authorizers, wrote House leaders opposing the bill, saying it would leave the state board with little authority to close low-performing schools.
Lee Teague, executive director of the N.C. Public Charter School Association defended the bill in a letter to legislators. With the changes, charter schools and traditional public schools will be judged by the same standard, he wrote.


text:
Q: Arduino code for servo motor I have a servo motor and I want it to spin a certain amount of degrees when I press a button.
Currently the servos spins as long as I keep the button pushed. I also need to keep the button pushed for about half a second till the servo moves or the control LED lights up.
I want the servo to perform a spin of x degrees or x milliseconds when I push it, no matter how long you keep the button pushed, it should perform just that movement.
This is the code I have now:
#include <Servo.h>
Servo myServo;

int LED = 13;
int BUTTON = 4;

void setup()
{
  pinMode(LED, OUTPUT);
  pinMode(BUTTON, INPUT);
  myServo.attach(9);
}

void loop()
{
  if(digitalRead(BUTTON)==HIGH)
   {
    digitalWrite(LED, HIGH);
    myServo.writeMicroseconds(1700);  // Counter clockwise
      delay(200);
   }

  else
  {  myServo.writeMicroseconds(1500);  // Stop
     delay(200);
     digitalWrite(LED, LOW);
  }
}

A: Use a flag that you set when the button is read as pressed for the first time, and unset it when no button press is read.
To check that the button has been pressed for a while, make a second call to the read function after some milliseconds and if it still is pressed, go on. There are more elegant solutions to this but they require use of interrupts.
...
int ButtonPressed = 0;
...
void loop()
{
    // Button pressed?
    if (digitalRead(BUTTON)==HIGH)
    {
        // Try again in a while
        delay_ms(500);
        // Still pressed?
        if (digitalRead(BUTTON)==HIGH)
        {
            // Has button been pressed previously?
            if ((ButtonPressed & (1<<BUTTON)) == 0)
            {
                // Yes
                ButtonPressed |= (1<<BUTTON);
                ...
            }
        }
    }

    else
    {
        // Button has been released
        ButtonPressed &= ^(1<<BUTTON);
        ...
    }
}

redpajama_set_name: RedPajamaStackExchange


Last month, Daniel Pipes made the case for Western support for the Assad regime in Syria. He based this on the idea of sustaining a stalemate between the tyrannical regime of Bashar Assad on the one hand and the Islamist insurgency forces on the other -- neither of whom are paragons of Western democratic values.
Evil forces pose less danger to us when they make war on each other. This (1) keeps them focused locally and it (2) prevents either one from emerging victorious (and thereby posing a yet-greater danger). Western powers should guide enemies to stalemate by helping whichever side is losing, so as to prolong their conflict.
His examples of past implementations of such a strategy are the Nazi invasion of Russia and the Iraq-Iran war.
Now there appears to be an additional aspect to maintaining the stalemate in Syria.
quagmire. How do you say quicksand in Arabic?
According to an organization monitoring the conflict, some 141 Hezbollah fighters were killed in the last month alone, 79 of them in the last 10 days, during the battle for the strategic stronghold of Qusayr, near the Lebanese border. In other words: Hezbollah lost more than one percent of its operational combat power within a month due to its support of Assad - quite a significant number of casualties for a relatively small guerrilla movement.
Nasrallah is facing unprecedented inner criticism in Lebanon due to his intervention in Syria. This week Britain and France promoted an initiative to have the European Union declare Hezbollah a terrorist organization - a move that could profit Israel, since it might limit Hezbollah's operations abroad.
Muslim history is filled with battles among Muslim forces from the early beginnings of Islam, so the fighting among Muslim armies is not surprising. In this case though, it may be coming at an opportune time for the West as the Arab Spring reveals itself as a resurgence of dangerous Islamist extremism.
Similarly, Israel finds that Hezbollah -- Iran's key terrorist tool -- is not only increasingly occupied in Syria, but finding itself weakened in the process.
Daniel Pipes may well be onto something.
Technorati Tag: Israel and Syria and Hezbollah.


text:
Renata Marta Walczak (ur. 18 czerwca 1963 w Płocku) – doktor habilitowana inżynier nauk rolniczych, profesor nadzwyczajna Politechniki Warszawskiej.

Życiorys
Renata Walczak pochodzi z Płocka, gdzie uczęszczała do Liceum Ogólnokształcącego im. Marszałka Stanisława Małachowskiego. Ukończyła studia w zakresie inżynieria środowiska na Wydziale Budownictwa i Maszyn Rolniczych Politechniki Warszawskiej. W 1987 rozpoczęła pracę na macierzystej uczelni na stanowisku asystentki, od 1995 na stanowisku adiunktki. W tym też roku doktoryzowała się w dziedzinie nauk technicznych na podstawie rozprawy Metoda oceny efektywności energetycznej recyrkulacji w procesie suszenia zielonek w suszarce bębnowej (promotor – Leszek Powierża). W 2008 habilitowała się w Instytucie Budownictwa, Mechanizacji i Elektryfikacji Rolnictwa w dziedzinie nauk rolniczych o specjalności inżynieria rolnicza na podstawie pracy Metoda oceny efektywności energetycznej suszarek rolniczych. Od 2014 jest profesor nadzwyczajną Politechniki Warszawskiej. Pełniła szereg funkcji na PW, m.in.: pełnomocniczka Prorektora Politechniki Warszawskiej ds. Międzynarodowych Programów Edukacyjnych (1995–2012), dyrektorka Kolegium Nauk Ekonomicznych i Społecznych Politechniki Warszawskiej (2012–2016), prorektor płockiej filii PW (2020–2024) oraz Dziekan Wydziału Budownictwa, Mechaniki i Petrochemii.

W 2003 uzyskała w Ministerstwie Skarbu Państwa uprawnienia do zasiadania w radach nadzorczych spółek Skarbu Państwa. Prowadziła zajęcia w VIA University College w Horsens w Danii. W latach 2007–2009 odbyła praktykę przemysłową w Dziale Diagnostyki Maszyn PKN Orlen.

Kilkukrotnie wyróżniana nagrodami Rektora PW. Otrzymała srebrny Medal za Długoletnią Służbę (2013) oraz Medal Komisji Edukacji Narodowej.

Publikacje książkowe

 Wybrane metody planowania i kontroli realizacji projektu, Radom: ITE, 2013.
 Podstawy zarządzania projektami. Metody i przykłady, Warszawa: Difin, 2014, .
 Sukces projektu, Warszawa: CeDeWu, 2019, .

Przypisy

Absolwenci Politechniki Warszawskiej
Ludzie urodzeni w Płocku
Odznaczeni Medalem Komisji Edukacji Narodowej
Odznaczeni Srebrnym Medalem za Długoletnią Służbę (III Rzeczpospolita)
Polscy inżynierowie środowiska
Prorektorzy uczelni w Polsce

Urodzeni w 1963
Wykładowcy Politechniki Warszawskiej

redpajama_set_name: RedPajamaWikipedia


text:
Mussuranas (Clelia) sind eine Gattung der Nattern. Am besten beschrieben ist hierbei die Art Clelia clelia.
Obwohl Mussuranas mittelgroße bis große Schlangen sind, werden sie in der Natur selten gefunden. Auch in Sammlungen ist die Gattung kaum vertreten.

Systematik
Folgende sieben Arten dieser Gattung sind bekannt:
 Mussurana (Clelia clelia (, 1803))
 Clelia equatoriana (, 1924)
 Underwoods Mussurana (Clelia errabunda , 1993)
 Clelia hussami ,  & , 2003
 Clelia langeri  & , 2005
 Clelia plumbea (, 1820)
 Clelia scytalina (, 1867)

Die folgenden drei, früher zu Clelia gerechneten Arten, wurden mittlerweile in eine eigene Gattung Mussurana ausgegliedert:
 Mussurana bicolor (, 1904)
 Mussurana montana (,  & , 1997)
 Mussurana quimi (,  & , 1997)

Clelia gehört zum Tribus Pseudoboini innerhalb der Unterfamilie Dipsadinae. In diesem ergibt sich nach Vidal et al. folgende Systematik:

Dementsprechend wurden die Arten, die näher mit Drepanoides verwandt sind, in die Gattung Mussurana verschoben. Die Schwesterngattung von Clelia ist Boiruna.

Merkmale
Juvenile Mussuranas haben ein weißes Halsband, sind meist rötlich mit schwarzen Streifen. Sie färben sich um, sobald sie erwachsen werden; die meisten Arten sind dann dunkel gefärbt. Sie erreichen eine Kopf-Rumpf-Länge von 57 bis 280 Zentimetern, wobei Clelia plumbea die größte Art ist. Weibchen werden generell größer als Männchen. Paarungszeit ist vermutlich ganzjährig, ob dies auch für die in den kühleren Lebensräumen vorkommenden Arten wie C. rustica gilt, ist unbekannt. Clelia sind ovipar, also eierlegend. Die Anzahl der Eier hängt von der Größe des Weibchens ab, Gelegegrößen zwischen 4 und 30 Eiern wurden beobachtet.

Verbreitung
Die Schlangen der Gattung Clelia kommen hauptsächlich in Südamerika vor. Clelia clelia hat das größte Verbreitungsgebiet, das im Norden bis Mexiko und im Süden bis Uruguay reicht. Clelia errabunda ist auf der Antilleninsel St. Lucia endemisch und wahrscheinlich ausgestorben.

Weblinks

 Clelia-Arten bei der IUCN

Einzelnachweise

Dipsadinae (Unterfamilie)


text:
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The United States of America is an exceptional country, the first in the world founded on an idea – that of individual liberty. We fought a revolution to win independence from England to form a republic in which the people directly elect their representatives. "We the People" established the Constitution of the United States to…
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The Office of the Attorney General is not only able to fight back, but I believe it has a moral obligation to defend the rights of citizens who choose to peacefully observe their faith traditions. The Founders knew citizens must be allowed to believe and practice their faith without fear of persecution from their government,…
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As threats from violent drug cartels creep across our borders, it's a stark reminder that securing our borders is not very high on our federal government's list of priorities. As Attorney General, I am making it a top priority to work with the Department of Public Safety, local law enforcement officials, and the executive cabinet…
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Safeguarding the integrity of our elections is a primary function of state government and is one of my top priorities as Attorney General. In 2011, I co-sponsored Senate Bill 14 which requires a person to show photo identification when voting. The bill passed the Texas House with 68% of the vote and bi-partisan support. To…
Ensuring State Sovereignty
"The powers not delegated to the United States by the Constitution, nor prohibited by it to the States, are reserved to the States respectively, or to the people." - 10th Amendment to the U.S. Constitution During the Obama Administration, Washington had a bullseye on Texas, and we boldly held the line against the out-of-control federal…
Standing with Law Enforcement
The Office of the Attorney General serves as a major support agency for Texas prosecutors and local law enforcement. Whether through police officer training and reports initiatives at schools or litigation in the courtroom, the Attorney General plays an important role in keeping Texans safe. Human trafficking and sexual assault crimes are violations of individual…
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Texas' job creators are being attacked in a very real way. Employers are put at risk from the job-killing regulations of the EPA, mountains of regulations, health care fines, and more. Increasingly, business owners are making more and more of their hiring decisions based on potential government regulation. This is wrong. Government should encourage –…
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The Attorney General plays a lead role in protecting taxpayers through investigating waste, fraud, and abuse, by reviewing and approving local bond packages, and through reviewing large state contracts. As a legislator I had a record of scrutinizing state budgets, creating transparency for state and local funds, and opposing tax increases. As Attorney General, I…
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The left's only goal is power...at any cost. They won't stop until our God-given rights are stripped away. Their attempt to use the courts to expand vote by mail (VBM) is a perfect example. My office has investigated hundreds of VBM fraud cases over the years, even as state law restricted the practice to only… continue reading
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text:
Mobility in America
MaaS Defined
From Concept to Clarity
A Definition
Mobility as a Service (MaaS) will manifest differently depending on many factors. MaaS America offers a definition of MaaS and understands that while it is not the only one, we favor a set of priorities and paths that reflect the American experience. This means MaaS will manifest differently here than in other regions of the world. MaaS America offers a definition as a intellectual foundation for those newly introduced to the concept. The premise of MaaS is a simple one:
MaaS is "The delivery, through an integrated digital platform and across all available modes of transport, of seamless, infinitely adaptable, personal mobility services."
An Ecosytem
The simple definition of an ecosystem (Wikipedia) is "a large community of living organisms (plants, animals and microbes) in a particular area. The living and physical components are linked together through nutrient cycles and energy flows. Ecosystems are of any size, but usually they are in particular places.
Mobility as a Service (MaaS) is also an Ecosystem: a large community of specific and distinct Actors and Stakeholders in the public and private sectors coordinating to provide mobility services to the public. Like the biological variety, MaaS ecosystem components are linked together - through data and communications technologies. Also like nature, MaaS ecosystems are built on a framework, off of which may 'hang' any combination of service providers and business models that combine to create a sustainable suite of integrated services, and this looks something like the picture below:
Levels of MaaS
Making it Relatable
The Waterfall Approach
An effective way to advocate for a concept or idea is to make it relatable. A way to do that is to present it in a context your audience can recognize. For technical people, MaaS comprises not one, but several steps in a process akin to waterfall project management, a sequential, linear process of project management: 1) that consists of several discrete phases; 2) where no phase begins until the prior phase is complete, and; 3) where each phase's completion is terminal—you cannot to return to a previous phase. For the less technical among us, MaaS is more understandable and tenable if you liken it to the levels of a waterfall. Do that, and you can present MaaS as already happening in communities now, as you will see in MaaS America's 'Levels of MaaS' section:
Level | Description | Explanation
Level Zero
Description: This is the base level. Relatable with today.
Explanation: There are account-based systems in place, individual modes of transportation already have a digitized interface and the traveler has information available online for each.
Description: There is a one-to-one integration between some private services.
Explanation: Duets of services start to develop joint offerings (e.g. tolling+car park; car+ferry, and; car park'n ride + bus services).
Level Two
Description: Integrated payment and ticketing across modes of limited public and private modes of transportation services.
Explanation: In this level, greater integration occurs but this time between a private operator and a public transport mode of operation. Integration shows promise but other transit modes are skeptical and continue to stay aloof.
Level Three
Description: Unified interface for single account used in multiple modes of transport services.
Explanation: Instead of having multiple channels, interface is unified across modes, providers, and services that the traveler finds necessary for trips provided by a single meta-operator through a traveler account.
Level Four
Description: All modes are integrated, private and public, including routing, ticketing, and payment.
Explanation: Open data and standards are defined and commonly used by all transportation providers and MaaS meta-operators to provide services for Travelers.
Level Five
Description: Active artificial intelligent choices are taken based on travels preferences and near real time data for ad-hoc changes to a journey.
Explanation: Based on traveler specific behavior and profiling, minimal (to no) intervention is needed by the traveler for an end-to-end journey based on the traveler's preferences, past travel history, and filters.
Level Six
Description: MaaS connects beyond mobility, interfacing with IoT's, smart building, and smart cities.
Explanation: As MaaS evolves, so do other systems involved in the traveller's day, such as smart work spaces, smart-homes, smart-cities, and general services (e.g. food, groceries, entertainment, sport, culture) to provide convenient and seamless interface with the Traveler's ecosystem.
© 2021 MaaS America


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— ABOUT MIDTOWN
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ABOUT MIDTOWN
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Porsche® and Mercedes®
Rich History Midtown Auto Repair
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Porsche is known today as one of the best sports car brands in the market. When you think Porsche you think fast, luxury, sport, and much more. But what's behind the flashy speed-racer brand is a rich history full of interesting facts and secrets. Let's take a look at what came before Porsche as we know it today.
The late Ferdinand Porsche was an Austrian automotive engineer that had an affinity for technology and was especially intrigued by electricity. Did you know that he engineered the world's first hybrid electric vehicle in 1899? Porsche built the Semper Vivus for Joseph Lohner and Company, based in Vienna. The Semper Vivus was also the first car with brakes on all four wheels.
Later, in 1923 he continued his successful engineering track as technical manager and executive board member at Stuttgart-based Daimler-Motoren-Gesellschaft Company. His role in this position was to oversee the construction of the Mercedes compressor car. In 1939 Porsche designed the Mercedes-Benz type 80 to be the fastest car on Earth at the time. The car's projected top speed of 470mph would have broken the world land speed record. However, it never made an attempt due to the project being overtaken by the outbreak of World War 2.
Finally, in 1931 Ferdinand and his son Ferdinand Anton Ernst Porsche founded their own firm – Porsche. 1934 was when they collaborated to develop the first designs of the Volkswagen car. Passing away in 1951 the business was left in the hands of his son. Since then, the company has become a world powerhouse for producing sports cars.
Though there are endless stories that can be told about the brand, these are some of the most memorable facts and secrets that make up the rich history behind Porsche.
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Par terre
Mariella Ottosson
As part of the video work "Par Terre", Mariella Ottosson will be filming two young wrestlers, performing a variety of exercises, especially focusing on the grips and techniques applied to sense the others movement, and to dominate ultimately the others body. The artist and the wrestlers will work out together a "set" or choreography, but also improvising and taking into account the wrestling "characters" by working with their expressions and roles towards the viewer.
The project includes research on the term "Parterre" which is found in both wrestling, theatre, and gardening design. Somehow seeming to relate to modes of organizing something chaotic. "On the ground" has also been used to define a specific social group within the late 1700's French theatre, where "the parterre" was used to name a group of standing spectators, often interfering with performances by screaming, fighting or throwing things towards the stage. It has later been argued that this was a form of social and political resistance towards the monarchy and upper classes.
Mariella Ottosson's work has, in the past years, been dealing a lot with body language and how it can be seen and studied as a manifestation of social, political and cultural realities. Previous projects have focused on the body's relation to digital devices as well as code – treating, amongst other things, the gestures relating to touch-screen interfaces, coding- systems for emotional expression and virtual museums available through Google street view.
Although Mariella's new project, "Par Terre", is not directly connected to these themes of technology, it does to a great extent treat the choreographed body, notions of spectator ship and questions of intimacy. In this work she wishes to elaborate on a sort of "organized, or choreographed violence", while also focusing on the intimacy that such physical contact (as found in wrestling or the theatre crowd), automatically brings about. One section of this project, includes filming the wrestlers Alexander Bica (20) and Armando Molin (17), and looking closely on a variety of grips and symbols found within the wrestling technique.
Participating and filming at their training, the artist finds out that rather than winning over with strength a great part of wrestling is about reading the opponents body and to mimic the others movement, while simultaneously weighing and challenging their balance-point and position.
Mariella Ottosson, Armando Molin (wrestler), Alexander Bica (wrestler), Maja Qvarnström (assistant), Aya Urhammer (assistant)


As if tensions between the West and Russia weren't high enough at the moment, the USA and the UK have essentially accused the Kremlin of laying the groundwork for future cyber attacks.
In a first-of-its-kind move, the UK and USA have issued a joint warning to government departments, businesses and citizens about potential Russian cyber intrusions.
"Since 2015, the U.S. Government received information from multiple sources—including private and public sector cybersecurity research organisations and allies—that cyber actors are exploiting large numbers of enterprise-class and SOHO/residential routers and switches worldwide," the warning reads.
While both governments have known for years about Russian attempts to gain access to their networks, the joint warning is the first time either power has publicly alerted people to it on a mass scale.
According to a report on the Guardian, the move may have resulted from frustration with Russia over cyber intrusions and possibly its meddling in elections both in the USA and in Europe.