text:
The departure of Dominic Cummings
Dominic Cummings is a genius at politics but was a failure in government about policy.
And this is because politics and policy are fundamentally different.
For example, politics can be linear while (good) policy will tend to be complex.
The approach of Cummings to the 2016 referendum and the 2019 general election was to be focused and unfussed about niceties and conventions and indeed the truth.
'Take Back Control'
'Get Brexit Done'
And so on, and many other statements, including those written on the side of a bus.
There are many things that one can and should object to in this electoral ruthlessness but it worked – twice.
Policy, on the other hand, is not (easily) amenable to such rush jobs.
Cummings believes, wrongly, that grand projects were easy, as long as you approached them with the right attitude.
On his blog, for example, he wrote about "the history of the classified programme to build ICBMs and the way in which George Mueller turned the failing NASA bureaucracy into an organisation that could put man on the moon. The heart of the paper is about the principles behind effective management of complex projects. These principles are relevant to Government, politics, and campaigns." (Emphasis in original.)
He also published a series of posts on "the unrecognised simplicities of effective action", including this 31 page paper.
Such stuff must have been interesting and exciting to write.
But the examples he used were not transferrable, even if those examples were accurately understood to begin with.
And when faced with two immense policy challenges in government: the departure of United Kingdom from the European Union and the coronavirus pandemic, the heady precedents of the Manhattan Project and putting men on the moon turned out not to be that useful.
Successful policy making is hard and it can rarely (if ever) be done just by making strident demands from the centre and upsetting (in both senses of the word) all those on who you depend to implement policy.
And, as Cummings has said many times, the current planning and public procurement regimes may be cumbersome and problematic – but disregarding them so as to make decisions and award contracts with no safeguards against abuse is no solution to those problems.
The news yesterday is that Cummings has left government, though it is not clear the extent to which he will carry on 'working from home'.
He had everything a policy blogger could have ever have wanted credibility (after those two electoral victories), a place in the centre, direct access to the prime minister, and a large majority.
He even had immense policy challenges in Brexit and Covid to which he could apply and show off his policy prowess.
But it did not work out, and his substantive policy achievements were such that they could fit in a cardboard box.
23 thoughts on "The departure of Dominic Cummings"
"Origin of Genius" has argued that most world changing geniuses had the rare ability of multiple types of skills.
That is, thinking up a huge new theory is very different from tediously writing it up, referencing it, and doing the experiments to prove it.
Hence, Darwin was unique in his ability of doing both. and so others.
Real success in politics + actual policy necessitate having both skills at once (think Lee Kuan Yew from Singapore)
Thanks for your always interesting analyses
Liz A says:
Having, in the past, read 'chapters' of his blog, I've always been struck by his innate shallowness. I mention this because his talent appears to lie in throwing up sand in such a way that people of influence don't subject him to a proper examination.
That may be where his cleverness was rooted. One attribute that he clearly lacks, however, is wisdom.
At serious times, wisdom is greatly needed and at present there seems to be a serious deficit of it in No. 10. Perhaps Mr. Johnson has had a damascene moment and will finally address that.
Lorelei Hunt says:
I hope so too. Wisdom is not a quality that can be easily measured – like IQ. And often comes with experience. So, not highly valued at the moment inside No 10 I suspect.
Guy Driech says:
DC is screensmart, but not that experienced (he had to lock himself away for 2 yrs to "learn how the world works"). Is his thrall indicative of the paucity of outside influence(s) to govt?
Their only obvious sources of inspiration are Oxford PPE grads and journalists. (Journalists?!). They do need to get out more if they want to avoid serial displays of cultural disconnect. Perhaps you should not be able to serve in govt. For longer than you have held a tax paying job.
Running a country needs more than politics and policy, however much of a genius you are. It needs insight and sympathy into what you're running, namely the people who live in that country; you need the human touch. Cummings often appeared almost to hate us.
Paul A Wright says:
Reading his 31 page paper it is interesting to see how much Cummings failed on his own terms. Few of the things he said were essential were actually applied when he had power – he often practised the opposite of what he preached.
He also doesn't seem to grasp the difference between a project and the ongoing process of running a country (which is not just a series of projects)
Robert Campbell says:
Cummings is an autodidact, self-taught about complexity and the principles behind effective management of change projects. The two imprortant problems with this are:
1) He doesn't have a "skeleton" or "framework" onto which to put his ideas, to see how they fit, how they might not work with other theories etc. For this you need a teacher.
2) He has very probably used a pseudo-scientific process. That is, he has started from the outcome, the conclusions, and sought out material that confirms his viewpoint; he hasn't started from the facts, and looked for conclusions. It's verification rather than falsification.
Mr. Anthony Tamburro says:
The extent of misunderstanding in his blogs and, to use the term generously, his policy papers was as breathtaking as it was profound. He is perhaps one of the best exponents of the genre of literate, intellectually limited, and incoherent writing that has infected so many areas of intellectual and public life.
He is gone and will be neither missed nor remembered.
The larger question is whether this imbroglio will damage the PM. I suspect that he is now severely, perhaps even fatally damaged. I think a failure to agree an EU deal or another national lockdown will be sufficient to end the current PM's tenure. I also think it is not unlikely that the current PM will simply walk away, perhaps assisted by an offer of a job, NATO secretary or some such, which would allow him to return to his career as a comment writer.
God help us were he to be offered the post of NATO secretary
David Pringle says:
It's extraordinary that the man who blogged about how Government got big projects wrong was at peak influence when Government got really important really big projects really wrong.
Let's just take Test and Trace.
Properly understanding something like the Manattan Project would have been an excellent primer in how to set up and run Test and Trace, for instance. (And let's be honest. T and T is 10x-100x less complex than the Manhattan Project.)
But of course, without any scientific, technical or management expertise, Cummings didn't really understand what was needed. Remember, he'd just 'studied' it and 'read' about it.
Who is the General Groves of Test and Trace? Dido Harding? And who is the Oppenheimer? Tony Hancock? (Sorry, I meant Matthew John David Hancock.) Etc etc etc. Freezing out genuine expertise was one of many issues that helped doom this year's T and T. (Just read Deenan Pillay and others on the issue.)
I suspect books will be written about what could have been if the UK Government had treated T and T like the Manhattan Project.
Fred Harrison says:
A correct analysis.
I think most people could agree on the objectives behind Cummings' meddling: Make government nimble and more responsive; simplify the decision-making, consultative and procurement processes; reform the command-and-control system.
Cummings was smart enough to see all that, but not smart enough to design a working model of government likely to achieve any of the needed improvements. He also failed to anticipate the problem of incompetence: What he had in mind I think was based on an assumption of intelligent decision making. But what if the decision makers are as stupid as a large number of relevant cabinet members, including the PM, have proved to be?
Example: procurement. Everyone knows the govt procurement system is overly complex and includes huge obstacles for new entrants. The result is a pool of incumbent suppliers who are apt to invest more in the procurement process itself (form filling, lobbying, etc.) than in innovation. The obvious example is defence spending, but can be seen right across government, including in the health service. Cummings tried to short-circuit the system. As a consequence, hundreds of millions in Covid-related service and supply contracts have gone to Tory cronies and others who happen "to know someone who knows someone" — exactly what a procurement system is meant to avoid.
John Turner says:
Cummings has an aversion to concepts like stakeholder analysis.
Heaven forfend that you might determine to seek out who is affected by a project, good and/or bad, and address any concerns to avoid problems in the future.
I don't think Cummings has a problem with a command and control system, if he's the one in command.
David Britten says:
I'm not that convinced about Cummings' brilliance as a political operator; his successes seem to me to owe as much to luck as to judgement. The referendum result was an achievement, but it's not unreasonable to suggest that, law-breaking aside, it required a somewhat lacklustre and complacent approach from Cameron, the impacts of austerity and the refugee crisis (and Farage) and, above all, Corbyn's disastrous non-leadership of the party that in other hands could have been such an effective vehicle for the Remain cause. It's also doubtful that Johnson would have got anything like the 80 majority, or perhaps even won the election at all, without Corbyn's help.
Mike Cohen says:
As an instance of Cummings "thought", he told us in a review that "Superforecasting" could "save trillions of pounds and millions of lives". Not even Philip Tetlock, who wrote the book, has made such claims. Comment is superfluous, and probably not printable.
I think people underestimate how hard it is to achieve good results in government. We seem to only ask what politicians want to do but don't worry if they have skills to achieve them.
David Brooks wrote in 2016 about how Hillary Clinton was boring and uninspiring on the campaign trail but excellent at working in government. (The exact opposite of Cummings' skills)
https://www.nytimes.com/2016/11/04/opinion/the-banality-of-change.html?rref=collection%252Fcolumn%252Fdavid-brooks&action=click&contentCollection=opinion&region=stream&module=stream_unit&version=latest&contentPlacement=39&pgtype=collection&referer=
This is an excellent summary – this quote says it all for me 'In the real world, the process of driving change is usually boring, remorseless and detail oriented….'
Neither DC nor Johnson have the necessary skill set to effective real change.
Peter Coghlan says:
I agree, spot on. Programme, project & change management is relentless & tedious hard work and they all require a basic framework within which to function effectively.
DC somehow managed to get the attention of people like Gove by pointing out glaringly obvious flaws in the system of government without actually understanding the mechanics, methodology, workload or patience required to understand or begin to address them; so instead set about dismantling them in the vague hope something or someone would appear as if by magic, to reassemble them. The self-proclaimed genius and 'superforecaster' also made the fundamental mistake of alienating the very people he'd need to achieve anything.
His vacuous slogan of "Take Back Control" is likely to be his only success by creating an epitaph for the Tory party he has previously claimed to loathe.
DC, like many others, expends lots of energy and lots of words in defining and redefining the problem. But never really suggests a well developed solution, rather an approach to a solution. There's a naivety in much of this – an assumption that the case for change is overwhelming if we are to avoid future catastrophy. As if such massive problems can simply be overcome by changing how we manage the development of solutions.
The application of more rational, scientific methods of management to delivery of public sector goals is far from new. The novelty here is in the scale on which he is thinking. But this is where I find a gap in his rationale, for the larger the problem, the more difficult it is to define the goals. Putting a man on the moon is one thing. Achieving world peace is quite another.
In his earlier blog, talking about Berkshire Hathaway, the founders describe the importance of temperament rather than intelligence per se. This human element is what is missing for me in much of what he writes. From the micro level human disruption of organisations to the macro level of democratic decision making. His current (limited) experience might lead him to think that the system can be relatively easily manipulated but a longer political career might show otherwise. Timing is everything and you need to be around at the wrong time as well as the right time to find that out.
There seems to be an inherent contradiction in his approach – in spite of his avowed commitment to a more rigorous, scientific approaches, he has attached himself to conviction politicians like Gove and Johnson. Their policy aims are rarely back by evidence, lack hard goal and outcomes. This would quickly be revealed if they were subject to scientific management principals.
This suggests to me that DC is a victim of the very flaw at the heart of his thinking – his desire to succeed and to gain the power necessary to test his theories leads him to attach himself to those drawn emotionally to the case he makes. Sadly not the people committed to the hard work and rigorous thinking necessary to test them in practice.
Owen Roberts says:
Hi. A short one. Thank your stars that's over – praying it is. The simple difference in my eyes is between how a voter expects to be treated, and what treatment an employed worker knows he/she has to put up with. Not the same, as hopefully all will agree. NASA – inspired approaches fine when all around depend on you, but not going to satisfy the multiple demands on Govt – eg show you're not wasting our money.
Bogdan C says:
My Eastern European upbringing and experiences may have something to do with it, but I'm failing to understand why you and most of the UK media (special mention for the vomit inducing BBC movie) are presenting an unscrupulous educated crook as some sort of political mastermind. If this British Otto Von Jizzmark (©M. Hyde) is a genius because he played a role in Brexit and the 2019 GE, how about the opportunistic charlatan who became POTUS? Do you think Trump is a political genius as well?
I understand it's much more difficult to admit to being a moron than to pretend the conman was a genius, and even more so when we're talking about an entire nation (so proud of its 'specialness') but unless some very uncomfortable truths are acknowledged the charlatans will thrive and the con will go on and on.
Cummings is not a genius thief who managed to steal 4000 tonnes of gold from Fort Knox, he's an opportunistic scumbag who nicked your stereo and shat on the driver seat because you couldn't be bothered to lock your car.
Well said, agreed!
Ouch! But yes.
Our problem is with the driver who took us to the party – he thinks that boring stuff like having to lock the car is an infringement of our liberty.
Cummings was successful at persuading people to try his simple solutions to complex problems.
Unfortunately the simple solutions didn't work, they just made it worse.
So here we all are, like a cat in a bag, waiting to drown, as this time Brexit's coming down.
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text:
Tron (TRX) joins forces with first decentralized hybrid exchange JOYSO
Ali Qamar
The world's first decentralized hybrid exchange JOYSO has now incorporated Tron network leading to a decentralized blockchain setting that is more maintainable.
Undoubtedly, it is good news as far as the world of digital currency is concerned. Tron is going to collaborate with JOYSON to bring about a more maintainable decentralized hybrid exchange in the market.
JOYSO has been ranked 11th in the development of decentralized Hybrid exchange hence there is some great hope for Tron (TRX). The news brings some anticipation for the Tron users as it recently has been seen dropping consistently in its price index during 2018.
The collaboration will bring about a set up for entirely all decentralized applications also known as (dApps) on Tron platform for increasing the sustainability of the blockchain in the market.
#TRON partners with @joyso_io, building a sustainable decentralized blockchain environment. #TRX $TRX https://t.co/BrbKnzP27t
— Justin Sun (@justinsuntron) October 31, 2018
JOYSO is founded by Tom Soong who is a hybrid decentralized exchange system for digital currency having the benefit of reducing the risk involved in the hacking of the system.
The system also offers the most cost-effective platform to its users. The platform was recently launched in May 2018. To enable one understands how it works JOYSO gives on Chain payments and off Chain matching for trade exchanges at the snap of the hand.
Besides maintaining the decentralized trade exchange platform, it also has a plus in the implementation of the enhancement of technology in blockchain engineering to meet the expectations of the clients hence more effective and efficient system.
That is due to the implementation of a suitable architecture that significantly decreases gas fee in the process of trade. Additionally, apart from enabling the free listing of any ERC20 tokens, it is also more secure and allows the users to have their accounts with no registration providing anonymity while enabling them trade in the market. These benefits of new Tron partner altogether, in turn, give users a 50% discount in the processing fee and creation of value in the digital currency environment.
Earlier on JOYSON implemented and accomplished the eagerly awaited NAS- JOYSON which is a decentralized exchange platform on the Nebulus chain line. With the recent partnership with Tron (TRX), JOYSON will be implementing the system under off chain matching and on chain payment where the users of the system will have the opportunity to exchange the tokens directly using their digital wallets.
On the other hand, Tron blockchain system has given its users the perfect platform for token issuers creating affordability to the clients and user-friendly operation. This implementation will, in turn, attract more users to the Tron market and will enhance its drifting decline in the token demand. JASON CTO Will Hsieh says,
"With all the technological capability and the known name for being the best in this sector, JOYSON can enable a simple, safe and efficient solution for the trade of crypto on a variety of blockchain hence creating a more maintainable infrastructure"
Also, just yesterday, Tron elected another Super Representative after more than 90 million votes in favor of new SR. The cryptocurrency has also been talked about more than anyone else on social media, even Bitcoin.
With many significant developments in the market, we are yet to see Tron rejoicing over the hard work done by its members to make the partnership happen and be implemented. This significant move could make the Tron token ecosystem value to increase substantially even though alongside other cryptocurrencies TRX holds a known continuous pattern of decrease in price since the beginning of the year.
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Image courtesy of Rawpixel/Pixabay
Related Topics:blockchainTronTron (TRX)
Ripple CEO Brad Garlinghouse unfolds the future plans of the company
Coincheck Brings Back Account Openings, Purchases, and Deposits For Selected Coins
Cryptocurrency traders have enjoyed a Bitcoin moon shot during the past few months. Those gains have created a much more enjoyable environment for crypto bulls. Whether it's a temporary or permanent increase remains to be seen but hitting the 10,000 level has put everyone in a better mood. Unfortunately, altcoins have not had experienced the same type of gains and are lagging significantly behind Bitcoin.
I've written articles in the past year that there is at least a decent chance that many altcoins won't survive the current environment. The ones that do will do so because they created a platform that has real world usage. After spending countless hours researching many of the existing altcoins, I've yet to see a company that is more promising than Encrypgen (DNA).
Encrypgen Background Information
Encrypgen is a genomic blockchain network that provides customers and partners with best-in-class, next generation, blockchain security for protecting, sharing and re-marketing genomic data. This creates a fair marketplace for a person's DNA that can be stored privately and sold (if a person wishes to do that). A person's DNA can also be shared privately and securely with their physician for their personalized care.
Typically, people can send their DNA off to a lab to find out who they are and where they come from. As fun as that might sound, there is a significant security problem…
Altcoins24 hours ago
Trade7 days ago

redpajama_set_name: RedPajamaCommonCrawl


text:
Джагго () или Лухо () — уезд Гардзе-Тибетского автономного округа провинции Сычуань (КНР). Правление уезда размещается в посёлке Синьду.

История
Уезд был образован в 1914 году.

В 1939 году была создана провинция Сикан и уезд вошёл в её состав.

В апреле 1950 года в составе провинции Сикан был образован Специальный район Кандин (康定专区), и уезд вошёл в его состав; в декабре 1950 года Специальный район Кандин был переименован в Тибетский автономный район провинции Сикан (西康省藏族自治区). В 1955 году провинция Сикан была расформирована, и район был передан в состав провинции Сычуань; так как в провинции Сычуань уже имелся Тибетский автономный район, то бывший Тибетский автономный район провинции Сикан сменил название на Гардзе-Тибетский автономный округ.

Административное деление
Уезд делится на 2 посёлка и 14 волостей.

Ссылки

Уезды Гардзе-Тибетского автономного округа

redpajama_set_name: RedPajamaWikipedia


http://vimeo.com/15978113 My buddy just released a cool collaborative drawing tool that's worth looking at. Think of it as Your World of Text for images. It's called The Grid and the best of the drawings are posted here on Posterous. There is some seriously creative work; it is mostly 8-bit video game themed for obvious reasons, but it is cool nonetheless.
225 South 6th Street is....pink?


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Registers a script which instantiates a dictionary of translations.
$scriptName The name of the script which will be registered and which will be a property of the global JS object x2.
$namespace The name of the JS object which will contain the translations dictionary. For nested namespaces, each namespace should be separated by a '.' character.
Used by actions to return JSON encoded array containing error status and error message. Used for testing purposes only.
Used by actions to return JSON encoded array containing error status and error message.
Used by actions to return JSON encoded array containing success status and success message.
Calls printError or printSuccess depending on the value of $success.
$limit If set, only the top $limit items on the call stack will get printed. debug_backtrace does have an optional limit argument, but it wasn't introduced until php 5.4.0.


What's in the future for FG RMC ruleset?
Script error when NPC tokens already on, or added to, a map.
How do you handle '"weapon" and "missile" attacks in the Combat Tracker?
Rolemaster Creature XML format for skills?


text:
package com.qingbo.ginkgo.ygb.cms;

import org.junit.Test;
import org.junit.runner.RunWith;
import org.springframework.test.context.ContextConfiguration;
import org.springframework.test.context.junit4.SpringJUnit4ClassRunner;

@RunWith(SpringJUnit4ClassRunner.class)
@ContextConfiguration(locations = { "classpath:consumer.xml" })
public class Consumer {
	@Test
	public void tongji() {
		System.out.println(toString());
	}
}

redpajama_set_name: RedPajamaGithub


text:
<?php

/**
 * ImportInvoice
 *
 * This class has been auto-generated by the Doctrine ORM Framework
 *
 * @package    siwapp
 * @subpackage model
 * @author     Your name here
 * @version    SVN: $Id: Builder.php 7490 2010-03-29 19:53:27Z jwage $
 */
class ImportInvoice extends PluginImportInvoice
{
}


Disclosed herein is a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command: and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle, to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.
1. An apparatus comprising: a memory cell array including a plurality of groups of memory cells defined independently by a plurality of first addresses, respectively; a first control circuit configured to generate a plurality of first refresh signals one after another at first intervals responsive to a self-refresh command and produce a plurality of second addresses one after another at the first intervals responsive to the first refresh signals, respectively; and a second control circuit configured to be reset responsive to the self-refresh command and provide a control signal when the second control circuit detects that the plurality of second addresses has covered all of the plurality of first addresses since the second control circuit was reset: wherein the first control circuit is further configured to change lengths of the first intervals responsive to the control signal.
2. The apparatus of claim 1, wherein the second control circuit includes a counter circuit configured to count a number of the plurality of first refresh signals which have been received at the counter circuit, reset the number responsive to the self-refresh command and provide the control signal. hen the number exceeds a total number of the plurality of first addresses.
3. The apparatus of claim 2, wherein the first control circuit includes an additional counter circuit configured to count the number of the plurality of first refresh signals which have been received at the additional counter circuit and not to be reset irrespective of the self-refresh command.
4. The apparatus of claim 1, wherein the first control circuit includes an oscillator circuit configured to output a plurality of second refresh signals at additional intervals one after another responsive to the self-refresh command and be changed in driving capability responsive to the control signal so that lengths of the additional intervals are changed, the plurality of first refresh signals being produced based on the plurality of second refresh signals.
5. The apparatus of claim 4, wherein the first control circuit further includes a frequency divider circuit configured to provide a plurality of third refresh signals produced by dividing the plurality of second refresh signals and select the plurality of second refresh signals or the plurality of third refresh signals as the first refresh signals based on a temperature signal.
6. The apparatus of claim 1, wherein the first control circuit includes a counter circuit configured to count a number of the plurality of first refresh signals to produce the plurality of second addresses, each of the second addresses comprising a plurality of address bits; and wherein the second control circuit includes a determination circuit configured to receive one of the plurality of address bits of each of the second addresses and determine that the plurality of second addresses has covered all of the plurality of first addresses since the second control circuit was reset when one of the plurality of address bits changes in logic level multiple times.
7. The apparatus of claim 6, wherein the determination circuit is further configured to receive a most significant bit of each of the second addresses and determine that the plurality of second addresses has covered all of the plurality of first addresses since the second control circuit was reset when the most significant bit charges twice.
8. The apparatus of claim 6, wherein the first control circuit includes an oscillator circuit configured to output a plurality of second refresh signals one after another responsive to the self-refresh command and be changed in driving capability responsive to the control signal, the plurality of first refresh signals being produced based on the plurality of second refresh signals.
9. The apparatus of claim 8, wherein the first control circuit further includes a frequency divider circuit configured to provide a plurality of third refresh signals produced by dividing the plurality of second refresh signals and select the plurality of second refresh signals or the plurality of third refresh signals as the first refresh signals based on a temperature signal.
10. An apparatus comprising: a first control circuit configured to produce a refresh address, the first control circuit being further configured to be brought into a self-refresh mode responsive to a self-refresh command to update the refresh address intermittently until the self-refresh mode exits; a memory cell array including a plurality of groups of memory cells, the plurality of groups of memory cells being configured to be refreshed in sequence responsive to the first control circuit updating the refresh address intermittently; and a second control circuit configured to produce a control signal indicating that the first control circuit has updated the refresh address until all of the plurality of groups of memory cells is refreshed; wherein the first control circuit is further configured to update the refresh address at first intervals until the control signal is produced from the second control circuit and at second intervals after the control signal has been produced from the second control circuit, the first intervals being different from the second intervals; and wherein the second control circuit comprises a plurality of latch circuits provided independently of the first control circuit, the plurality of latch circuits being configured to produce the control signal indicating that the first control circuit has updated the refresh address until all of the plurality of groups of memory cells is refreshed.
11. The apparatus of claim 10, wherein the plurality of latch circuits are coupled in cascade to form a counter circuit, the counter circuit being configured to update a count value thereof each time the first control circuit updates the refresh address.
12. The apparatus of claim 11, wherein the first control circuit includes an oscillator circuit configured to output a first refresh signal intermittently at the first intervals until the control signal is produced from the second control circuit and at third intervals after the control signal has been produced, the third intervals being different from the first intervals.
13. The apparatus of claim 12, wherein the oscillator circuit is further configured to change a driving capability thereof responsive to the control signal.
14. The apparatus of claim 12, wherein the first control circuit further includes: a frequency divider circuit configured to provide a second refresh signal produced by dividing the first refresh signal and output the first refresh signal when a temperature signal takes a first value; and a refresh counter configured to update the refresh address intermittently responsive the first refresh signal outputted by the frequency divider circuit when the temperature signal takes the first value such that the second intervals become equal to the third intervals.
15. The apparatus of claim 14, wherein the frequency divider circuit is further configured to output the second refresh signal when the temperature signal takes a second value different from the first value; and the refresh counter is further configured to update the refresh address intermittently responsive to the second refresh signal outputted by the frequency divider circuit when the temperature signal takes the second value such that the second intervals become equal to multiple times as long intervals as the third intervals.
16. The apparatus of claim 10, wherein the refresh address comprises a plurality of bits, and the plurality of latch circuits include at least two latch circuits each configured to receive data of a most significant bit of the plurality of bits to produce the control signal.
17. The apparatus of claim 16, wherein one of the two latch circuits is configured to activate an output node thereof when the most significant bit changes from a first logic level to a second logic level, an other of the two latch circuits is configured to activate an output node thereof when the most significant bit changes from the second logic level to the first logic level, and the control signal is produced when both output nodes of the two latch circuits have been activated.
18. The apparatus of claim 16, wherein the first control circuit includes an oscillator circuit configured to output a first refresh signal intermittently at the first intervals until the control signal is produced from the second control circuit and at third intervals after the control signal has been produced, the third intervals being different from the first intervals.
19. The apparatus of claim 18, wherein the oscillator circuit is further configured to change a driving capability thereof responsive to the control signal.
20. The apparatus of claim 18, wherein the first control circuit further includes: a frequency divider circuit configured to provide a second refresh signal produced by dividing the first refresh signal, output the first refresh signal when a temperature signal takes a first value and output the second refresh signal When the temperature signal takes a second value; and a refresh counter configured to update the refresh address intermittently responsive the first refresh signal outputted by the frequency divider circuit when the temperature signal takes the first value such that the second intervals become equal to the third intervals and update the refresh address intermittently responsive to the second refresh signal outputted by the frequency divider when the temperature signal takes the second value such that the second intervals become equal to multiple times as long intervals as the third intervals.
 This application is a continuation of U.S. patent application Ser. No. 14/4417,287, filed Jul. 30, 2014, which claims the filing benefit of JP Application No. 2013-159058, filed Jul. 31, 2013. These applications are incorporated by reference herein in their entirety and for all purposes.
 Embodiments of the present invention relate to a semiconductor device, and more particularly relates to a semiconductor device including a plurality of memory cells in which a refresh operation is necessary to retain information.
 In a volatile memory device of a charge retention type represented by a DRAM (Dynamic Random Access Memory), it is necessary to cyclically execute, a refresh operation as recharging in order to retain data of memory cells. The cycle of executing the refresh operation is decided based on a period in which the memory cells can retain data (hereinafter referred to as "a data retention period").
 In recent years, in view of reducing power consumption of the semiconductor device, it is desired that the cycle of executing, a refresh operation is extended as long, as possible, For example, Japanese Patent Application Laid-open No. H7-296582 focuses on a relationship between a temperature and a data retention period and discloses a semiconductor device that changes the cycle of executing a refresh operation according to values indicated by a temperature sensor.
 The present invention realizes reduction of power consumption without losing data of memory cells in controlling a refresh operation cycle.
 In one embodiment, there is provided a semiconductor device that includes: a memory cell array including a plurality of memory groups each having a plurality of memory cells, the memory groups being selected by mutually different addresses; a first control circuit periodically executing a refresh operation on the memory groups in response to a first refresh command; and a second control circuit setting a cycle of executing the refresh operation by the first control circuit. The second control circuit sets the cycle to a first cycle until executing the refresh operation to all the memory groups after receiving the first refresh command, and the second control circuit sets the cycle to a second cycle that is longer than the first cycle after executing the refresh operation to all the memory groups.
 In another embodiment, there is provided a semiconductor device that includes: a memory cell array including a plurality of memory cells in which a refresh operation is necessary to retain information; and a refresh control circuit periodically executing the refresh operation on the memory cells in response to a refresh command. The refresh control circuit executes the refresh operation at a first cycle until a first predetermined period elapsed after the refresh command is issued, and the refresh control circuit executes the refresh operation at a second cycle that is longer than the first cycle after the first predetermined period elapsed.
 According to the embodiments of the present invention, it is possible to reduce power consumption without losing data of memory cells.
 FIG. 9 is a circuit diagram indicative of an embodiment of a determination circuit shown FIG. 8.
 The following descriptions are contents provided by the studies of the present inventors.
 In semiconductor devices, of recent years, reduction of power consumption has been strongly demanded as well as high speed of operations, and securing of an operation margin for achieving the both aspects, which are originally in a trade-off relationship, has been much difficult. In this connection, if a write operation is focused, the following two points need to be taken into consideration.
 (1) In order to reduce power consumption, a voltage for writing is stepped down, and thus the amount of charges to be applied to memory cells is decreased.
 (2) in order to realize high speed operations, a write period is shortened, and thus the amount of charges to be applied to memory cells is decreased.
 The (1) and (2) mentioned above are causes for shortening a refresh cycle. The "refresh cycle" is a period required for refreshing all the memory cells, and it is specified by corresponding standards to be equal to or longer than 64 msec, for example. In this example, a case where the signal amount of the memory cells becomes smallest is a case where, at the time of a write operation, on memory cells in which data at a high level (or a low level) is stored, data of a low level (or a high level) which is a reversed one of the high level (or the low level), is overwritten.
 In this example, if the charge amount in the above case is designated as Qmin, an actual refresh cycle needs to be set on an assumption that the charge amount of the respective memory cells is Qmin. However, in a refresh operation, because the charge amount of the respective memory cells is reproduced to a sufficient extent, a charge amount (Qref) of the memory cells after the refresh operation is set to be Qref>Qmin.
 This is because a time for rewriting the same data on the memory cells at the time of the refresh operation is longer than a time for overwriting reversed data on the memory cells in the write operation, and more charges can be supplied to the memory cells at the time of the refresh operation. Therefore, the refresh cycle of memory cells on which a refresh operation has been executed once does not need to be a cycle on an assumption that the charge amount is Qmin, and the refresh cycle can be longer than that of the case of Qmin.
 Focusing on this point, in the semiconductor device according to the present embodiment, reduction of power consumption is realized by setting refresh cycles of the second and following cycles to be longer than that of the first cycle.
 Preferred embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.
 Referring now to FIG. 1, the semiconductor device 10 according to an embodiment of the present invention is a DDR3 (Double Data Rate 3) DRAM integrated in a single semiconductor chip. The semiconductor device 10 is mounted on an external substrate 2 that is a memory module substrate, a mother board or the like. The external substrate 2 employs an external resistor Re that is connected to a calibration terminal ZQ of the semiconductor device 10. The external resistor Re is a reference impedance of the calibration circuit 38. In the present embodiment, a ground potential VSS is supplied to the external resistor Re.
 As shown in FIG. 1, the semiconductor device 10 includes a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL a plurality of bit lines BL, and a plurality of memory cells MC arranged at their intersections. The selection of the word line WL is performed by a TOW decoder 12 and the selection of the bit line BL is performed by a column decoder 13.
 The semiconductor device 10 employs a plurality of external terminals that include command address terminals 21, a reset terminal 22, clock terminals 23, data terminals 24, power supply terminals 25 and 26, and the calibration terminal ZQ.
 The command address terminals 21 are supplied with an address signal ADD and a command signal COM from outside. The address signal ADD supplied to the command address terminals 21 is transferred via a command address input circuit 31 to an address latch circuit 32 that latches the address signal ADD. The address signal IADD latched in the address latch circuit 32 is supplied to the row decoder 12, the column decoder 13, or a mode register 14. The mode register 14 is a circuit in which parameters indicating an operation mode of the semiconductor device 10 are set.
 The command signal COM input to the command terminals 21 is input to a command decode circuit 33 via the command address input circuit 31. The command decode circuit 33 decodes the command signal COM to generate various internal commands that include an active signal IACT, a column signal ICOL, refresh signals REF and SREF, a mode register set signal MRS, and a calibration signal ZQC.
 The active signal IACT is activated when the command signal COM indicates a row access (an active command). When the active signal IACT is activated, the address signal IADD latched in the address latch circuit 32 is supplied to the row decoder 12. The word line WL designated by this address signal IADD is selected accordingly.
 The column signal ICOL is activated when the command signal COM indicates a column access (a read command or a write command). When the column signal ICOL is activated, the address signal IADD latched in the address latch circuit 32 is supplied to the column decoder 13. In this manner, the bit line BL designated by this address signal IADD is selected accordingly.
 Accordingly, when the active command and the read command are issued and a row address and a column address are supplied in synchronism with these commands, read data is read from a memory cell MC designated by these row address and column address. Read data DQ is output to outside from the data terminals 24 via a read/write amplifier 15 and an input/output circuit 16.
 Meanwhile, when the active command and the write command are issued, a row address and a column address are supplied in synchronism with these commands, and then write data DQ is supplied to the data terminals 24, the write data DQ is supplied via the input/output circuit 16 and the read/write amplifier 15 to the memory cell array 11 and written in the memory cell MC designated by these row address and column address.
 The refresh signal SREF is activated when the command signal COM indicates a first refresh command. Although not limited thereto, a self refresh entry command can be used as the first refresh command. When the refresh signal SREF is activated, the semiconductor device 10 enters into a refresh mode and periodic refresh operation is performed automatically. When the semiconductor device 10 enters into the refresh mode, the semiconductor device 10 becomes a low consumption current state, and it becomes impossible to perform a row access and a column access to the semiconductor device 10. In order to return to a normal operation mode from the refresh mode, it is necessary to input a refresh exit command to the semiconductor device 10 via the command address terminal 21 from outside. When the refresh exit command is issued, the refresh signal SREF becomes a non-active state, and the semiconductor device 10 returns to the normal operation mode.
 The refresh signal REF is activated when the command signal COM indicates a second refresh command. Although not limited thereto, an auto refresh command can be used as the second refresh command.
 Both of the refresh signals SREF and REF are supplied to a refresh control circuit 40. The refresh control circuit 40 controls the row decoder 12 to activate a predetermined word WL included in the memory cell array 11, thereby executes a refresh operation. Besides the refresh signals SREF and REF, a temperature signal TEMP that is output from a temperature sensor 39 are supplied to the refresh control circuit 40. The details of the refreshment control circuit 40 are described later.
 The mode register set signal MRS is activated when the command signal COM indicates a mode register set command. Accordingly, when the mode register set command is issued and a mode signal is supplied from the command address terminals 21 in synchronism with this command, a set value of the mode register 14 can be overwritten.
 Turning to the explanation of the external terminals included in the semiconductor device 10, a reset signal RESET is input to the reset terminal 22. When the reset signal RESET is activated, the semiconductor device 10 performs an initialization operation.
 The clock terminals 23 is supplied with external clock signals CK and /CK, respectively. These external clock signals CK and /CK are complementary to each other and then supplied to a clock input circuit 34. The clock input circuit 34 receives the external clock signals CK and /CK to generate an internal clock signal PCLK. The internal clock signal PCLK is supplied to an internal clock generation circuit 35 and thus a phase controlled internal clock signal LCLK is generated. Although not limited thereto, a DLL circuit can be used as the internal clock generation circuit 35. The internal clock signal LCLK is supplied to the input/output circuit 16 and is used as a timing signal for determining an output timing of the read data DQ. The internal clock signal PCLK is also supplied to a timing generator 36 and thus various internal clock signals ICLK are generated. The various internal clock signals ICLK generated by the timing generator 36 are supplied to circuit blocks such as the address latch circuit 32 and the command decode circuit 33 and define operation timings of these circuit blocks.
 The power supply terminals 25 arc supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to an internal voltage generating circuit 37. The internal power supply generating circuit 37 generates various internal potentials VPP, VOD, VARY, VPERI, and the like and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is mainly used in the row decoder 12, the internal potentials VOD and VARY are mainly used in sense amplifiers included in the memory cell array 11, and the internal potential VPERI is used in many other circuit blocks. The reference potential ZQVREF is used in the calibration circuit 38.
 The power supply terminals 26 are supplied with power supply potentials VDDQ and. VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 16. The power supply potentials VDDQ and VSSQ are the same potentials as the power supply potentials VDD and VSS that are supplied to the power supply terminals 25, respectively. However, the dedicated power supply potentials VDDQ and VSSQ are used for the input/output circuit 16 so that power supply noise generated by the input/output circuit 16 does not propagate to the other circuit blocks.
 The calibration terminal ZQ is connected to the calibration circuit 38. The calibration circuit 38 performs a calibration operation with reference to an impedance of an external resistance Re and the reference potential ZQVREF, when activated by the calibration signal ZQC. An impedance code ZQCODE obtained by the calibration operation is supplied to the input/output circuit 16, and thus an impedance of an output buffer (not shown) included in the input/output circuit 16 is specified.
 Turning to FIG. 2, the refresh control circuit 40 includes a refresh counter circuit 41 that generates a row address RAT<12:0> of the word line WK that is a refresh target. In this example, the row address RAT<12:0> represents a 13-bit signal formed of RAT<0> to RAT<12>. The row address RAT<12:0> is supplied to the row decoder 12 shown in FIG. 1. In the present invention, a plurality of memory cells MC refreshed by a predetermined row address RAT<12:0> are sometimes referred to as "memory group".
 The count value of the refresh counter circuit 41, that is, the row address RAT<12:0>, is updated (incremented or decremented) in response to a refresh execution signal MCREFT. The refresh execution signal MCREFT is activated every time the refresh signal REF or a refresh signal SCLK2 is activated. Specifically explaining this operation, the refresh signal REF or SCLK2 is supplied to an OR gate circuit 42, and an output signal therefrom is one-shot pulsed by a one-shot pulse (OSP) generation circuit 43. The one-shot pulsed output signal is latched by a latch circuit 44 and used as the refresh execution signal MCREFT. The refresh execution signal MCREFT is supplied to the row decoder 12 shown in FIG. 1, and fed back to the latch circuit 44 via a delay circuit 45. With this operation, the refresh execution signal MCREFT is activated and then returns to a deactivated state after a predetermined time period.
 With this configuration, when the refresh signal REF or STLK2 is activated, a refresh operation is executed with the activation of the refresh execution signal MCREFT, and the row address RAT<12:0> indicated by the refresh counter circuit 41 is updated. As shown in FIG. 3, the refresh counter circuit 41 is a binary counter of a 13-bit configuration formed by cascade connected latch circuits L0 to L12, and outputs of the respective latch circuits L0 to L12 are used as the respective bits RAT<0> to RAT<12> of the row address RAT<12:0>.
 Accordingly, when the refresh signal REF or SCLK2 is activated 8192 (=213) times, the count value of the refresh counter circuit 41 completes one cycle and then all the memory cells MC included in the memory cell array II are refreshed.
 As described above, the refresh signal REF is a signal that is activated when the command signal COM indicates a second refresh command. Therefore, when the second refresh command is issued 8192 times, the count value of the refresh counter circuit 41 completes one cycle, and all the memory cells MC included in the memory cell array 11 are refreshed.
 Meanwhile, the refresh signal SCLK2 is a signal that is generated by an oscillator circuit 46 and a frequency divider circuit 47 in response to the activation of the refresh signal SREF. Specifically, when the refresh signal SREF is activated, automatic and cyclic generation of a refresh signal SCLK1 by the oscillator circuit 46 is started, and the generated refresh signal SCLK1 is supplied to the frequency divider circuit 47. The frequency divider circuit 47 generates the refresh signal SCLK2 by dividing the refresh signal SCLK1 based on the temperature signal TEMP. The generation of the refresh signal SCLK1 by the oscillator circuit 46 is continued until a refresh exit command is issued from outside. Circuit configurations of the oscillator circuit 46 and the frequency divider circuit 47 are described later.
 As shown in FIG. 2, the refresh signal SREF is also supplied to reset nodes of a counter circuit 48 and a latch circuit 49. These reset nodes are low active, and thus in a normal mode, the counter circuit 48 and the latch circuit 49 are always in a reset state. When the refresh signal SREF is activated at a high level, the reset state of the counter circuit 48 and the latch circuit 49 is canceled.
 Turning to FIG. 4, the counter circuit 48 is a binary counter of a 14-bit configuration formed by cascade connected latch circuits L0 to L13, where a count value is updated (incremented or decremented) based on the refresh execution signal MCREFT. An output of the uppermost latch circuit L13 is used as a detection signal SRAT<13>. Accordingly, when the refresh execution signal MCREFT is activated 8192 times after the reset state of the counter circuit 48 is cancelled, the detection signal SRAT<13> is changed to a high level. Because the refresh execution signal MCREFT is also used for updating of the count value of the refresh counter circuit 41, the tact that the detection signal SRAT<13> is activated means that the count value of the refresh counter circuit 41 has just completed one cycle in a state where the refresh signal SREF is at a high level.
 Turning to FIG. 2, the detection signal SRAT<13> is supplied to the latch circuit 49. The latch circuit 49 is a so-called SR (Set-Reset) latch circuit. When the detection signal SRAT<13> is activated, the latch circuit 49 is set, and then the set state is maintained until the refresh signal SREF is deactivated. A switching signal SRATLAT output from the latch circuit 49 is supplied to the oscillator circuit 46.
 Turning to FIG. 5, the oscillator circuit 46 has a configuration in which a plurality of inverter circuits INV1 to INVn are cyclically connected to each other. The value n is an odd number. Therefore, when the oscillator circuit 46 is activated, the logical level of the refresh signal SCLK1 as the output signal of the oscillator circuit 46 is changed cyclically.
 Each of the inverter circuits INV1 to INVn includes a P-channel MOS transistor P10 and an N-channel MOS transistor N10 that are connected in series, P-channel MOS transistors P11 and P12 that are connected to a source of the transistor P10, and N-channel MOS transistors N11 and N12 that are connected to a source of the transistor N10. The transistors P11 and P12 are connected in parallel to each other, and an inversion signal of the refresh signal SREF and the switching signal SRATLAT are input to respective gate electrodes of the transistors P11 and P12. Further, the transistors N11 and N12 are connected in parallel to each other, and the refresh signal SREF and an inversion signal of the switching signal SRATLAT are input to respective gate electrodes of the transistors N11 and N12.
 With this configuration, when the refresh signal SREF is activated at a high level, an oscillator operation is started and the logical level of the refresh signal SCLK1 is cyclically changed. At this time, when the switching signal SRATLAT is in a deactivated state (at a low level), not only the transistors P11 and N11 but also the transistors P12 and N12 are turned on, and thus the driving capability of the inverter circuits INV1 to INVn becomes large. As a result, the cycle of changing the refresh signal SCLK1 becomes short. On the other hand, when the switching signal SRATLAT is in an activated state (at a high level), while the transistors P11 and N11 are turned on, the transistors P12 and N12 are turned off, and thus the driving capability of the inverter circuits INV1 to INVn becomes small. As a result, in this case, the cycle of changing the refresh signal SCLK1 becomes long.
 It is not necessary that the driving capability of all the inverter circuits INV1 to INVn can be changed, and it is permissible that the driving capability of only a part of the inverter circuits INV1 to INVn can be changed.
 The refresh signal SCLK1 generated as described above is supplied to the frequency divider circuit 47.
 Turning to FIG. 6, the frequency divider circuit 47 includes two JK flip-flop circuits JK1 and JK2, a selection circuit SEL, and a one-shot pulse generation circuit OSP2 that makes an output signal from the selection circuit SEL one-shot pulsed. The JK flip-flop circuits JK1 and JK2 are cascade connected to each other, and both input nodes J and K of the first-stage JK flip-flop circuit JK1 are fixed to a high level. With this configuration, because the JK flip-flop circuit JK1 executes a toggle operation based on the refresh signal SCLK1, a refresh signal SCLK1-2 as an output signal of the JK flip-flop circuit JK1 has a waveform Of dividing the refresh signal SCLK1 into two parts. Further, a refresh signal SCLK1-4 output from the next-stage JK flip-flop circuit JK2 has a waveform of dividing the refresh signal SCLK1 into four parts.
 The refresh signals SCLK1, SCLK1-2, and SCLK1-4 are supplied to the selection circuit SEL. The selection circuit SEL selects any one of the refresh signals SCLK1, SCLK1-2, and SCLK1-4 based on the temperature signal TEMP. Specifically, the refresh signal SCLK1 is selected when the temperature signal TEMP indicates a temperature that can obtain a normal refresh characteristic, the refresh signal SCLK1-2 is selected when the temperature signal TEMP indicates a temperature that can obtain a refresh characteristic which is better than a normal refresh characteristic, and the refresh signal SCLK1-4 is selected when the temperature signal TEMP indicates a temperature that can obtain a refresh characteristic which is much better than a normal refresh characteristic. With this configuration, the output signal of the selection circuit SEL is changed at a cycle corresponding to an actual refresh characteristic (that is, a data retention period of the memory cells MC).
 The output signal of the selection circuit SEL is supplied to the one-shot pulse generation circuit OSP2, and is output as a one-shot pulsed refresh signal SCLK2. The one-shot pulsed refresh signal SCLK2 is supplied to the OR gate circuit 42 shown in FIG. 2. Therefore, when the refresh signal SCLK2 is activated, a refresh operation similar to that of a case where the refresh signal REF is activated is executed.
 Operations of the semiconductor device 10 according to the present embodiment are explained next as focusing on a refresh operation.
 Turning to FIG. 7, a first refresh command is issued at a time t1. In response to the first refresh command, the refresh signal SREF is activated at a high level at the time t1 and the semiconductor device 10 enters a refresh mode. Thereafter, a refresh exit command is issued at a time t3, and the refresh signal SREF is deactivated at a low level. With this process, the semiconductor device 10 returns to a normal mode.
 Before the time t1, because, the semiconductor device 10 is operated at a normal mode, a read command or a write command is issued from a control device (not shown) when necessary, and the semiconductor device 10 executes a read operation or a write operation in response to the issued command. Further, in the normal mode, a second refresh command is issued regularly from the control device. When the second refresh command is issued, the refresh signal REF is activated. When the refresh signal REF is activated, as explained with reference to FIG. 2, a refresh operation is executed on the row address RAT<12:0> that is indicated by the refresh counter circuit 41.
 The second refresh command is issued in a frequency during which all the memory cells MC are refreshed in one refresh cycle (such as 64 msec). In the present embodiment, because the row address RAT<12:0> has a 13-bit configuration, the second refresh command is issued 8192 (=213) times in one refresh cycle. Therefore, as one refresh cycle is assumed to be 64 msec, an average issuing frequency of the second refresh command becomes 7.8 .mu.sec. While an example in which the second refresh command is issued at every 7.8 .mu.sec is shown in FIG. 7, it suffices that the issuing frequency of the second refresh command is 7.8 .mu.sec on average, and the second refresh command does not need to be issued exactly at every 7.8 .mu.sec.
 When the first refresh command is issued at the time t1, the refresh signal SREF is activated at a high level, and the semiconductor device 10 enters a refresh mode. When the semiconductor device 10 enters a refresh mode, the oscillator circuit 46 shown in FIG. 2 is activated, and automatic and cyclic generation of the refresh signal SCLK1 is started, Further, in a period before the time t1, the counter circuit 48 and the latch circuit 49 are kept in a reset state, and the reset state is cancelled at the time t1. Accordingly, the count value of the counter circuit 48 before the time t1 is 0 (zero), and the switching signal SRATLAT before the time t1 is in a low-level state.
 When the switching signal SRATLAT is at a low level, as explained above with reference to FIG. 5, the cycle of changing the refresh signal SCLK1 becomes short. Tlherefore, the refresh execution signal MCREFT is activated in a predetermined short cycle (first cycle), and a regular refresh operation is executed automatically. In this example, the selection circuit SEL included in the frequency divider circuit 47 selects the refresh signal SCLK1, and thus the cycle in which the refresh signal SCLK2 is activated matches the cycle in which the refresh signal SCLK1 is activated.
 In the example shown in FIG. 7, the first cycle is 7.8 .mu.sec and the first cycle matches an average issuing frequency of the second refresh command. This is because, in a state where the semiconductor device 10 has just entered a refresh mode, there are memory cells with a charge amount of Qmin, and thus the refresh execution signal MCREFT needs to be activated in a short cycle (first cycle) on an assumption that the charge amount of the respective memory cells is Qmin.
 Thereafter, incrementing or decrementing of the refresh counter circuit 41 and the counter circuit 48 is progressed by regular activation of the refresh, execution signal MCREFT. In the example shown in FIG. 7, the refresh execution signal MCREFT is activated 8192 times during a period between the time t1 and a time t2. That is, at the time t2, the value of the row address RAT<12:0> as the count value of the refresh counter circuit 41 completes one cycle, and the value returns to n, which is a value just before the semiconductor device 10 enters a refresh mode. At this time, the count value of the counter circuit 48 indicates 8192.
 When the count value of the counter circuit 48 changes from 8191 to 8192, the detection signal SRAT<13> is changed to a high level, and in response to this change, the switching signal SRATLAT is also activated at a high level.
 When the switching signal SRATLAT is changed to a high level, as explained with reference to FIG. 5, the activation cycle of the refresh signal SCLK1 is extended. Therefore, the refresh execution signal MCREFT is activated in a predetermined long cycle (second cycle), and a regular refresh operation is executed automatically. In the example shown in FIG. 7, the second cycle is 15.6 .mu.sec, and it is twice the first cycle. With this configuration, the execution frequency of the refresh operation is decreased to one and thus current consumption of the semiconductor device 10 is further reduced.
 Such control is possible because, when the count value of the refresh counter circuit 41 completes one cycle, the charge amount of all the memory cells becomes Qref. As explained above, because Qref is larger than Qmin, after the time t2, a state where the data retention period of all the memory cells MC is longer than that of in a normal mode is guaranteed. In this example, the data retention period of all the memory cells MC is equal to or more than 128 msec. Therefore, as the refresh execution signal MCREFT is activated at every 15.6 .mu.sec, it is possible to activate the refresh execution signal MCREFT 8192 times during the period of 128 msec, that is, it is possible to refresh all the memory cells MC during the period of 128 msec.
 Subsequently, the refresh execution signal MCREFT is activated at every 15.6 .mu.sec, and the count value of the counter circuit 48 is updated in response to the activation; however, because the SR latch circuit 49 is kept in a set state, the switching signal SRATLAT is maintained at a high level regardless of the change of the detection signal SRAT<13>.
 Thereafter, when a refresh exit command is issued at the time t3, the refresh signal SREF becomes a low level, and the semiconductor device 10 returns from a refresh mode to a normal mode. After returning to a normal mode, operations identical to those before the time t1 are executed.
 As explained above, in the present embodiment, after the semiconductor device 10 enters a refresh mode, when all the memory cells MC are refreshed, the generation cycle of the refresh execution signal MCREFT is elongated. With this configuration, current consumption of the semiconductor device 10 can be further reduced while properly maintaining data of the memory cells MC. Further, by using the refresh control circuit 40 shown in FIG. 2. when the count value of the refresh counter circuit 41 has just completed one cycle, the generation cycle of the refresh execution signal MCREFT is switched from the first cycle to the second cycle, so that effective reduction of current consumption can be made.
 Turning to FIG. 8, the refresh control circuit 40 is different from the refresh control circuit 40 shown in FIG. 2 in that a latch circuit 50 and a determination circuit 51 are provided in place of the counter circuit 48 and the latch circuit 49. Because other elements of the refresh control circuit 40 shown in F1G. 8 are identical to those of the refresh control circuit 40 shown in FIG. 2, like reference numerals are denoted to like elements and redundant explanations thereof will be omitted.
 The latch circuit 50 is a circuit that latches thee upper-most bit RAT<12> among the bits of the row address RAT<12:0> output from the refresh counter circuit 41, and the latch circuit 50 is maintained in a reset state during a period where the refresh signal SREF is at a low level. A latch signal RATLAT<12> output from the latch circuit 50 is supplied to the determination circuit 51. When the determination circuit 51 detects a change of the latch signal RATLAT<12> with a predetermined pattern, the determination circuit 51 activates the switching signal SRATLAT at a high level. The determination circuit 51 is also maintained in a reset state during a period where the refresh signal SREF is at a low level. Therefore, when, the latch signal RATLAT<12> changes with a predetermined pattern after the refresh signal SREF is changed to a high level, the switching signal SRATLAT becomes a high level.
 Turning to FIG. 9, the determination circuit 51 includes two flip-flop circuits FF1 and FF2, and output signals FF1out and FF2out from these flip-flop circuits are supplied to an AND gate circuit G. Each of the flip-flop circuits FF1 and FF2 includes a data node D, a complimentary clock node C, and a low-active reset node RB. The refresh signal SREF is input to the data node D and the reset node RB, and the latch signal RATLAT<12> and an inversion signal thereof are input to the clock node C.
 As shown in FIG. 9, the logic of the latch signal RATLAT<12> input to the clock node C is inverted between the flip-flop circuits FF1 and FF2. Therefore, when the latch signal RATLAT<12> is changed from a high level to a low level, the level of the refresh signal SREF is latched to the flip-flop circuit FF1, whereas when the latch signal RATLAT<12> is changed from a low level to a high level, the level of the refresh signal SREF is latched to the flip-flop circuit FF2. When the refresh signal SREF is at a deactivated level (a low level), the flip-flop circuits FF1 and FF2 are reset.
 With this configuration, under a condition that the refresh signal SREF is activated at a high level, when the latch signal RATLAT<12> is inverted twice, both of the output signals FF1out and FF2out become a high level, and the switching signal SRATLAT output from the AND gate circuit G is activated at a high level.
 That is, after activation of the refresh signal SREF at a high level, when the level of the latch signal RATLAT<12> is changed as H.fwdarw.L.fwdarw.H or L.fwdarw.H.fwdarw.PL, the switching signal SRATLAT becomes a high level. The latch signal RATLAT<12> is changed with such patterns only after the count value of the refresh counter circuit 41 completes one cycle. Therefore, as the switching signal SRATLAT is changed to a high level by using the change of the latch signal RATLAT<12> as a trigger, after refreshing all the memory cells MC in a refresh mode, it becomes possible to elongate the generation cycle of the refresh execution signal MCREFT. Furthermore, because the circuit configuration of the refresh control circuit 40 shown in FIG. 8 is simpler than that of the refresh control circuit 40 shown in FIG. 2, the occupation area of the refresh control circuit 40 on a chip can be decreased.
 In the above embodiment, a case where the present invention is applied to a DRAM has been explained as an example; however, application targets of the present invention are not limited thereto, and the present invention can be applied to any type of semiconductor devices including a plurality of memory cells that require information storage by a refresh operation.
 Furthermore, in the above embodiment, the generation cycle of the refresh execution signal MCREFT is elongated when all the memory cells MC are refreshed in a refresh mode; however, this feature is not necessarily essential. Therefore, it is permissible that the generation cycle of the refresh execution signal MCREFT is elongated when the majority of all the memory cells MC (such as 90% of the memory cells MC) are refreshed in a refresh mode. This is because the rest of the majority of the memory cells (such as 10% of the memory cells MC) that are not refreshed yet will be also refreshed soon after the elongation of the generation cycle.
 Further, in the above embodiment, the activation cycle of the refresh signal SCLK2 is switched by changing the frequency division ratio of the refresh signal SCLK1 based on the temperature signal TEMP; however, in the present invention, control of refresh cycles based on temperature information is not essential. Therefore, it is permissible to omit the frequency divider circuit 47 and to input the refresh signal SCLK1 directly to the OR gate circuit 42.


Creative release is one of the most important things you can do for yourself and your sanity.
Even if you don't think you're 'creative' there are heaps of things you can do to express that inner Picasso of yours. Just putting something different in the kids lunch boxes can give you that feeling of dabbling in some great experiment where you're dying to see their reactions.
Even dancing like an idiot in the living room to Abba or even Justin Beiber (insert singer or band of choice here) is enough to release the creative energy and get your juices flowing.
Instead of just putting your kid's drawings on the fridge, put yours up there too even if they look the same! Tell your inner art critic to go on a long holiday and just draw or paint like no-one's going to judge it.
Everyone is creative in some way, it could be finding a unique solution to a problem of not enough space in the house, planting a veggie garden with the kids, throwing paint at a 6 x 4 canvas or cranking up Florence and the Machine while doing your own version of a Seafood Laksa.
If you're feeling uninspired or don't know how to get in touch with your creative side, go on a what author of The Artists Way, Julia Cameron, calls 'An Artists Date' where you set aside some serious ME time and go and visit an art gallery, see a movie, walk on the beach, go to a concert or whatever floats your boat, but make a commitment to do it. So give the mother in law a call and get her to baby sit, while you go on an artist date with yourself.
You are just as important as everyone else so allow yourself to express yourself in whatever way you can. A life of just going through same routine is soul destroying and your inner creative beast will sit in the corner of your heart feeling unloved and unwanted.
So let him out and give him a cuddle.


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Inkjets Enter Industrial Markets: What it Means for Screen Printers
Screen Printing Screen Printing September 2003 Issue
In the world of wide-format graphics, 2003 is something of a landmark year. It marks the tenth anniversary of when digital printing, mainly in the guise of 200-dpi electrostatic and 300-dpi inkjet printers, first seriously entered the wide-format graphics market as a short-run production technique. Originally, by using high-cost specialty media with inappropriate inks and toners printed by plotters never designed for graphics applications, repro houses, photolabs, newly emerging graphics-service bureaus, and other digital-print providers were able to create and serve a new market, as well as existing display-graphics sectors.
While wide-format photography quickly felt the impact of digital printing, there was no immediate fallout for the traditional, commercial wide-format reproduction methods of screen and offset printing. The printing world essentially divided itself into two extreme camps. The first consisted of fundamentalist screen and offset supporters who ridiculed "this digital stuff" as slow, expensive, and incapable of achieving traditional requirements for print quality at realistic price points. On the other side were the digital evangelists who claimed that screen printing and other traditional processes would be annihilated by digital printing. We at Web Consulting believed neither of these extreme views, and therefore found ourselves somewhat damned by both groups, having to preach opposing gospels to different manufacturers and user groups to achieve some balanced perspective.
Now, ten years later, the reality is that digital printing–particularly with inkjet technology–has grown massively. Nonetheless, even today it accounts for little more than 15% of the total wide-format graphics production globally. Digital imaging hasn't destroyed the screen-printing industry, although it has siphoned off some growth that screen printing would otherwise have been likely to capture, and it created certain new graphics business opportunities.
Two years ago, inkjet technology once again started to nibble at the edges of graphic screen printing. And with the recent rapid emergence of systems with less media dependence, such as flatbed UV and low-cost solvent-based inkjet printers, digital printing shows signs of biting off yet more market share.
One of the most significant consequences of digital-printing technology has been its effect on the mentality of graphics screen printers themselves, who no longer treat growth in market demand with an automatic response to invest in new screen-printing equipment. They might invest in screen, digital, or offset, depending on their application requirements. The name of the new game in town is "flexible production."
When a primary new technology is invented and developed, it may take many years to find its way into robust commercial products and applications. If, for a moment, we think about revolutionary technologies such as lasers, microprocessors, electrophotography, and liquid crystal displays, they all took around 30 years to achieve maturity. The concept of inkjet printing was first described by the UK's Lord Kelvin in the 1860s, and the German scientist Hertz developed some inkjet breakthroughs in the 1930s. But we owe much of current wide-format inkjet development to the boom in new thermal- and piezo-printhead technologies first developed in the late 1980s for office printers. It is fair to assume that inkjet printing still has a long way to go and that its success will not be confined to the home and office sector, wide-format graphics, and marking and coding in the packaging industry.
In the overall market for wide-format graphics, inkjet has already become the number four technology by volume of prints, following screen printing, offset lithography, and computer-aided signmaking. Inkjet is the number two generator of profits for graphics-industry manufacturers and distributors. At Web Consulting, we predict that inkjet will eventually rank first by value and second by volume.
This vision of the wide-format market is old news to the many "traditional" suppliers to the screen-printing, offset, and photographic sectors, who have already started to cross into digital technology. These suppliers, now actively supporting inkjet technology, include such companies as Sericol, NazDar, SunJet (Coates/Sun Chemical), Jetrion (Flint), Heidelberg, Ilford, Kodak, Fujifilm, and many others and join the ranks of the early digital innovators, such as HP, EnCad, 3M, and Rastergraphics (now Oc
Related Topics:ArticlesDigital PrintingSeptember 2003
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Indigo Eagle Sanctuary is an incredible place to experience the abundance of nature, including waterfalls, a rushing creek, fishing, and camping. If you are looking to be immersed in beauty and adventure, then you have found the right place.
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Welcome to this next summary of insights and links to independent reports, key statistics, infographics and analyst recommendations from what we believe to be the most reputable sources globally.
"App building in the next 5 years will change with a bigger reliance on APIs and BaaS to speed up both developments and reduce complexity."
The key to success for any business looking to leverage IoT is not in the connected devices themselves.
33% of IT decision makers identified small mobile-first SIs as their ideal managed mobility solutions partner.
Only 17% of the 'Best-in-Class' prefer an on premise solution.


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Tour: Borjomi, Akhaltsikhe, Khertvisi, Vardzia, Rabati fortress
Travel Company WALKER
Tour highlights:
Khertvisi
Rabati fortress
In the south of Georgia you will find the provinces of Samtsche – Djavakheti – a land of forested mountains and steep river valleys, gushing rivers and clear lakes.
Transfer to Borjomi. The Balneological health resort Borjomi is situated in the south-east of Georgia in the Agura river gorge at the height of 800m above sea level. This is a picturesque place with large-leaved and coniferous forests surrounded with majestic the Caucasian mountains. The resort gained its special reputation owing to mineral sources. The Borjomi mineral waters were mentioned for the first time as early as in the XV century. The main Borjomi source is situated in Borjomi Central Park where everybody who wishes can have it.
Akhaltsikhe (old name Lomisa) is cozy situated on the both banks of a small river Potskhovi, at 1,000 meters above sea level. During a tour of this ancient city we will be able to visit Rabati Fortress. Rarely any fortress can boast of such an unusual history. Rabati – is a town in the city. The complex has many historic castles, towers, churches, and mosques cells. Halls deserve special attention which architectural performance demonstrates the great skill of the ancient masters and delicate artistic taste of the Georgian people. Impressions of the tour will remain in your memory forever, because everything in this place is imbued with the ancient majesty and rich history. In the lower part of the fortress is situated tourist information center, a restaurant, café, gift shops, all these create additional convenience for visitors.
Khertvisi fortress is situated on a high rocky hill in a narrow gorge at the confluence of the Kura and Paravani. Ancient Chronicle Leonti Mroveli wrote that Khertvisi originated during ancient times. One of the legends says that the first fortifications were destroyed during the attack of Alexander the Great. Due to the strategic importance, the fortress was constantly updated and strengthened, but, despite this, the unity of the ensemble is not broken. This is not only a first-class military installation, but also a magnificent landmark. In the center of the citadel stands 20-meter tower, also two secret passages leading to the river survived in the fortress The legendary cave city of Vardzia is a rare historical monument, built at the turn of XII-XIII centuries. At an altitude of 1300 meters above sea level in a steep tuff rock, masters have recreated a monastery complex.
Vardzia delves into the rock half a kilometer and rises up thirteen tiers, which are connected to each other with complex system of tunnels. Total number of caves was originally 3000, but after a strong earthquake in 1283 large part was destroyed. Now there are about 600. There are preserved a large reception hall, living quarters for the nobility and the common people, the book depository, wineries, water and spring water baths. The Church of the Dormition is the central spiritual and monumental focus of the site. On the same north wall are ancient portraits of the royal founders, King Giorgi III and his daughter Queen Tamar.
Rabati fortress is situated in the center of Akhaltsikhe, at a distance of 207 km from Tbilisi on the left bank of the river Potskhovi. The old part of the town so-called Rabati is situated on the rocky inn. Ensemble comprises: Sargis Jakeli castle of 14th c., Fortress Church (late Middle Ages), Palace 18th century and the Church of Saint Marine (1865) with built-in relief works.
Ivane Javakhishvili Samtskhe-Javakheti History Museum in 1972 moved to two buildings at the Rabati territory in Akhaltsikhe and it was named after Ivane Javakhishvili. Today, the Museum houses the significant part of the region's cultural heritage. Totally it preserves over 25,000 objects. They include manuscripts and old printed books (parchments dating to the 11th, 12th, 15th, and 17th cc.), photos, archaeological, numismatic, and ethnographic collections, etc. The Museum's textile collection (rugs and carpets of the verge of 19th-20th cc.) as well as collection of ancient inscriptions cut on stone are of high importance. Since December 2004 Ivane Javakhishvili Samtskhe-Javakheti History Museum is a part of the Georgian National Museum. Apart from two main buildings that display permanent exhibitions – the Castle that surrounds it, Administrative building, Mosque built in 1752, Ruins of a medresa (Islamic school) – belong to the Museum. Total size of the Museums open air territory is 27.500 square meter. From this territory 3.978 square meters is occupied by buildings, 23.522 square meters is a yard inside the citadel.
T R A V E L C O M P A N Y
"W A L K E R"
Georgia, Tbilisi
WhatsApp/Viber: +995 551 211355
Facebook: http://FB.com/Travel.Agency.Walker.Ge
E-Mail: georgianwalkers@gmail.com
Web-Site: www.walker.ge
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Once you have a worklist filtered the way you want it, you can export data in CSV (comma-separated), JSON, or XML formats. You also aren't limited to the fields displayed by the worklist; you can choose any fields, including those from related records.
Similarly, you can also import records on most worklists in CSV format. You'll be given the opportunity to map columns in your import file to record fields.


Summer Family XPERIENCE is a unique VBS-like experience designed for the whole family. There is something for all ages…Babies thru 5th grade kids. Parents attend the Parent Camp portion of the evening because we know that every parent wants to be a better one! You'll get to know other parents who have kids in the same phase and discover transformative ways you can win at parenting.


What Disk Imaging Software do you primarily use to backup and restore?
Discussion in 'polls' started by markymoo, Aug 15, 2008.
Poll closed Sep 14, 2008.
What is consistently your first choice of disk imaging software to backup and restore your system?
Also what be interesting to include how often you backup? I backup my system every single day. I wipe and restore on average every 2 months for a spring clean. I haven't had to restore before then as the system is very stable and error free due to good maintenance. The exception being for testing purposes.
Meant to add 'Other' and 'Dont Backup' so if an MOD see's this, please add thanks. If not listed just reply what you use. Can't edit the full names and it's stuck as multiple choice oh well .
I dont test that much software/malware any more as I used to so I only restore maybe once every other week or so nowadays.
True Image for doing hard drive upgrades for clients, don't use it a home though. Once in a while (like..maybe a couple of times a year) I'll backup my important stuff to another hard drive...but main system just keeps running 'n running til my next big hardware upgrade, in which case she gets rebuilt fresh.
I use Image For Windows/Dos at least once a week to backup to an external drive.
i use paragon drive backup 9.
i backup once a day at 5pm.
I've used Paragon Drive Backup a long time but since mothballed it for DriveSnapshot which is still not showed a single glitch or issue since turning to it some time ago. Plus it's "LITE" and fast and you can easily BROWSE it's contents after imaging in a virtual partition as well as change files/folders at will. I forego the auto-incremental feature w/hash and instead simply manually reimage again directly over the image to update it, a breeze to do.
It's tiny without all the bells and whistles and simply does the job 100% perfectly for me each and every time without issue or confusion that others make for their customers sometimes.
I can't see ever changing to any other again because it's a sure bet none of them are as small as DS while performing exceptionally excellent restores, all completely intact without the massive bloat others load into your machine just to image and restore.
For me a surprisingly real exceptional imaging application worth every penny that is not failed me a single time. I call that super-reliability.
Others can argue, and for good reason, that other imaging apps can perform features DS doesn't offer, but the bottom line is DS images perfect, and restores everything completely intact time & time again without fail without all the extra bloat of loading numerous files which not only consume valuable space but raise chances of issues or problems. DS does none of that and is why i'm a very pleased customer of this tiny imaging app.
I don't see any need to jump ship for a long long time if ever from it. It's "LITE", for me anyway images and restores with a rating so far of 100%, and is very fast. Plus it's a breeze to BROWSE it's contents afterwards or even change files/folders in it, but mostly i forego the auto-incremental route for manual overwrites when i want to update my image. Less files to deal with and just reimages right over the existing image with absolutely no problems at all.
I....Plus it's "LITE" and fast and you can easily BROWSE it's contents after imaging in a virtual partition as well as change files/folders at will. I forego the auto-incremental feature w/hash and instead simply manually reimage again directly over the image to update it, a breeze to do.
Long a tima no see! Anyway, as you know I use paragon and tend to agree it is "complex" Mind you it has saved me many times from my own stupidity!
On DS when you say it can reimage right over to update that loses the famous Grandfather, Father, son rule doesn't it?
What about restoring your OS partition? I doubt you mean if can overright that as it is "in use"?
I think i'm reading too much into your post!
Yeah, you're probably reading too much into it. PARAGON is a class standing imaging app without a doubt and is saved my bacon many times over, but DS to me is almost stupidly simple in comparison but without the additional features, and in my case some of the other features don't even match up with DS, in speed, reliability, which can be argued because PARAGON is never failed me either.
In fact, the only difference i could raise is that DS allows to BROWSE it's image much faster if thats any comparison worth mentioning.
DS is nearly if not completely PORTABLE too, another bonus, and since i really don't rely on daily increments for keeping images up-to-date, i use DS on-the-fly to overwrite it's previous image whenever the need arises.
Plus, it's a breeze to work with and is yet to fail either way for me, imaging or restores. PARAGON does the same, and i wouldn't part with it since it also comes with a CD Rescue Disc, one item sorely missing in DS, but made up for thanks to markymoo.
I used Ghost for years then switched to ATI on some machines - (home and server editions.) For this last year I use ShadowProtect for home and server now being supported by some software I use. I have another of their (StorageCraft) products so I knew about them but also from hearing from others that use the software.
Daily online backups with Mozy Pro. Monthly images with SP.
I use Shadowprotect for imaging exclusively. I don't image as frequently as I do update FDISR archives.
Acronis though fd-isr actually does most of my backups, I tend to only use disc image when fd-isr fails.
I backup when I feel the need to. Sometimes daily if I test software or change my OS-partition. But usually not so often. Sometimes weeks between each backup. I backup to both external and internal hdd.
BING is also a great partition tool. My best purchase.
I use Acronis True Image 10 for system backups (whole OS partitions with or with-out data) about once a week for important OS partitions (these are put on a separate Hard Drive).
I mostly back up my data on CD'S/ DVD'S . For these I use native Windows for CD'S and Nero for DVD'S.
I find that for data it is much faster/easier and inter-computer friendly using regular non-image backups. This way I do not have to have my data tied down by TI10 and I can use the data on any Windows NT OS machine.
Ditto for me. I use BING NG much the same way. It has never failed to restore an image.
Acronis. Quick and effective. Also a good compression.
Paragon Hard Disk Manager for me.Never failed on xp or vista.
SP,hard to beat(first and last defence !) then good ol FDISR for comfort sake.
Acronis TrueImage. Very user-friendly (in my opinion).
Hmmm...not to degrade ATI,but userfriendly........,look over their support forums.


Road maintenance to repair cracking concrete is scheduled to occur next week in the Sparta Road/Commerce Drive roundabout. The work will take place on Tuesday and Wednesday, Dec. 4-5, weather permitting.
The work will be done by Smith Contracting, of Austin.
The roundabout will remain open in all directions during this road work. However, traffic will be diverted, as-needed, to the mountable curb and red concrete area. Mobile home transport vehicles should consider alternate routes. Other large vehicles, such as semi-trailer trucks, freight vehicles, school buses, trash trucks and fire engines, should be able to traverse the mountable curb with ease.
This work may cause some delays in travel time along Sparta and Commerce, so please plan accordingly. As always, patience during the maintenance work is appreciated.


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Padmarajan (23 May 1945 – 24 January 1991) was an Indian author, screenwriter, and film director. His stories deal with deceit, murder, romance, mystery, passion, jealousy, libertinism, anarchism, individualism, and the life of peripheral elements of society.  Some of them are considered as among the best in Malayalam literature.

Padmarajan was noted for his fine and detailed screenwriting and expressive direction style. The follow list details all of his known written and directorial published works.

Novels

Short stories

Films

Bibliographies by writer


Join us for our public launch of TURF: A Mini-Golf Project as we tee-off with a night of play. Free rounds of mini-golf, cash bar, and the public unveiling of nine miniature projects by our architecture teams! TURF: A Mini-Golf Project explores the meaning of terrain and territory in Los Angeles through the architecture of mini-golf. The mini-golf course becomes a playful trope of the city of Los Angeles, articulated through artificial terrains, winding territories, and fantastical architecture.
M&A Catalogue Launch for Building Something (Beyond) Beautiful.