text:
'We are looking into the future with optimism'
rusembassy.in
The ambassador of Russia Alexander Kadakin
The ambassador of Russia, Alexander Kadakin's interview to Vickram Bahl on the situation around the Roerich Museum in Naggar.
Recently, many articles have appeared about the controversies around the International Roerich Memorial Trust (IRMT) in Naggar. As a person closely associated with the Trust for many years, how can you comment on that?
First, I should give the background as to how Russia got so intimately involved with the Naggar Trust. I got acquainted with the last Roerichs – Svetoslav and Devika, way back in 1971, when I was interpreting at a dinner between the couple and the then Soviet ambassador, Nikolai Pegov. Since that period a very close friendship had evolved between the elderly couple and me. Whenever they came to Moscow, we would spend days and days together, the same happening in Delhi when they stayed at Imperial Hotel on the way to Kullu.
I was a young diplomat, just an attaché at that time. They were childless, and after my parents died, they considered me like their son. When they grew older and weaker and moved to Ashoka Hotel in Bangalore, Svetoslav and Devika would phone me every week, and I was flying down south on a weekend to meet them, as they felt very lonesome.
In 1989, I was appointed Minister-Counsellor, DCM, of the Embassy. Svetoslav understood that something had to be done about Kullu because it was a dilapidated and forgotten estate as they stopped visiting it for the last fifteen years of their lives. Once he invited me to Bangalore and I saw a document on the table which he presented to me. It was the general power of attorney. It was late 1991. In that power of attorney he instructed me to start the International Roerich Memorial Trust. He also gave me the powers to take charge of all movable and immovable properties in his Kullu Valley estate.
Naturally, it was a very important event, but quite unusual for a diplomat to get such a thing. We started the Trust immediately. I did it in 1992 under the direct instructions from Svetoslav. At that time the State authorities were never involved. He invited an elderly German lady, Sister Ursula Eichstaedt, who was their old friend, as the supervisor of the estate. We started visiting that place every month. There were dozens of working expeditions from the embassy. Once I gave Rs 50 thousand to Sister Ursula from my own pocket to tidy up the cherry garden and apple orchards. No government money was given. We bought her refrigerators, our engineers were repairing wires, etc.
Ursula was there running the Trust until her death in May 2004. Dr Alena Adamkova, a noted Indologist, a Ph. D. in sciences and a very talented young lady, was already there. During the first ten years of the Trust's existence either State or Central government was nowhere to be seen on the horizon. Everything was done solely on donations from Russian sponsors, Russian companies working in India, from our own pockets. Ursula did not have enough money to buy food. We were bringing her food and gave her money to live. Wives of our diplomats were sweeping and washing the floors in the house, tidying up the gardens, doing menial work to bring the estate to life. And it has resurrected!
It was only after 2000 that the Government of India came into picture. It was former Prime Minister, Mr A.B.Vajpayee. He was the first who actually understood the importance of the place. He visited Naggar several times and said that "a Russian rishi was lying there". He gave a big donation to the Trust, which has not been used until now, due to all bureaucratic trickery by the state bureaucrats, etc.
That is how in 2009 I became, as second-time ambassador, the ex-officio Vice-President. Plus I am a life trustee as the founder. These are the 'avatars' I hold in the IRMT.
For me, it is a very personal thing, because nothing was there. All people who visited that place, remember that. Russia and Russians have invested so much heart, so much soul and so many funds into making the Trust a real gem.
As far as I know, some officials in the Himachal Pradesh Government claim that according to the Indian law there should be no foreigners in the Board of Trustees. Does it mean that Russians will be forced to stop their involvement in the Naggar museum activities?
We were told by the most experienced jurists and advocates in Delhi that of course foreigners can be members of the Trust. If we have been members of the Trust for the last twenty years, why all of a sudden we cannot be members? If you proceed from the British law, the Trust Act of 1882 or something like that, which is still in force, these are the relics of India's colonial past. You cannot today live according to those rules in an independent and democratic India.
As regards the Bangalore Trust, you remember, there was a twenty year old litigation around Tataguni estate in Bangalore. We do not want to be members of that Trust and we are happy that the litigation is finally over and the Government of Karnataka can do something. Of course, as I repeatedly stated, we should participate in the work of that Trust, but not as members. There is much difference between the two Trusts. First of all, the Tataguni Roerich estate belonged to Svetoslav and Devika Rani. Svetoslav was an Indian citizen, like Devika Rani. That is why we do not claim any role of trustees there. We shall be helping. Our Consul General from Chennai will be visiting. I am visiting regularly. We shall be happy if it prospers, that is all we want.
But as regards the Kullu Trust, it is different. First of all, the Trust was started on the power of attorney granted to me personally by Svetoslav. Secondly, that estate is intimately connected with the elder Roerichs while the Bangalore estate has no such connection. Svetoslav and Devika bought it after the death of Nicholas. So the Himachal story is absolutely different.
There is much talk in the media about problems in functioning of the Roerich Memorial in Naggar. Is it true and what, in your opinion, hinders normal activities?
How can a Trust function normally, if before March 2011 not a single Board of Trustees meeting had been held for six years? We voiced our concern in numerous letters sent to the Chief Minister as the President of IRMT. Poor Dr Adamkova! She has been struggling through the last ten years to get things done in spite of all these odds. It was only after our strongest insistence that the last Board of Trustees meeting was called. How can a Trust function normally when a DC, with all our respect to the local authorities, becomes the final decision-making authority?
How can a Trust function normally if a sink is broken in the estate? In such case the curator, a Doctor of Science, has to go to the DC and beg him to give money for its repair? First of all it does not befit such reputed scientist, but still she was doing it. If the lavatory is broken, then the water and other things will be leaking out. Instead of immediately fixing the problem, a three-member committee must be set up and decide! It is sheer nonsense.
How can a Trust function normally, if, again, we want to publish a book by Roerich for a big function and the Trust has the money including the donations received from Mr Vajpayee, but instead of publishing, the scientific curator has to wait for three to five months to get the sanction of the DC. Is it normal that a Doctor of Sciences is begging for a sanction from a DC?
I do not think it is the clash of personalities or lack of coordination because in the long run things were done. There is another aspect. The Trust is not a government body! If a book has to be published for an anniversary, it has to be published. A scientific curator should not beg of a district authority to obtain sanction for a Roerich book. Unfortunately, some of the bureaucrats cannot even spell the name "Roerich" correctly…
Dr Alena Adamkova, Russian Curator of the museum, is accused of financial violations. It is claimed that she has opened a special bank account without permission and, allegedly, is into double accounting. Are these claims justified?
All accusations about "double accounting" are absolute rubbish. I did request Alena Adamkova to open a special personal account as I got angry and sick after the last Board of Trustees meeting. We wanted to reprint a book with Nicholas Roerich letters. We had enough money, but again, a sanction from the DC was required to use that money. I wanted to teach them a lesson. I asked Alena to open a special personal account, of course, traceable by the police and all other authorities, on which I sent my personal money, from my salary. The book was printed on time, within a month, and presented at the function. Is it a crime for an Ambassador and Vice-President of the Trust to send his own money to his compatriot (not an Indian!) for the noble purpose of publishing a book? I openly stated this at the Board of Trustees meeting in March 2011.
There is another question: what kind of accusations can be floated when it is none of the Curator's realm of duties to deal with money or accounting. The State government had been failing to appoint an accountant for the Trust for the last five years! And now the Curator is accused of wrong doing. Funny, indeed, with evident double standards involved.
How is it possible to settle tensions around the IRMT and lay ground for creative work?
On the whole I want to underline that our mood is optimistic. Yet problems have not been sorted out. There will be a commission coming from Moscow. There will be a Russian and an Indian curator. That is good to have two curators. But the Trust has to be liberated from the chains of district authorities, and a DC should not be the final decision-making authority or a treasurer. The Trust cannot work in such way. Again, it is not a government body, it is a trust. If the Trust President or the Vice-President gives a sanction to publish a book, then this book must immediately go to the printing press without any district deputy commissioner. He has nothing to do with scientific aspects. This has to be fixed on paper.
Secondly, we have been insisting and Russia will strongly request in the future, too that the Central Government should be directly involved. We even went to the extent of saying that the Central Government should take the Trust under its wings. Of course, the State Government will be there, as the estate is situated in Himachal Pradesh. We have the highest respect for the State Government and Chief Minister Prof. Dhumal who has done much. The role of Shanta Kumar was also very important. The invaluable contribution was made by former Chief Minister, my friend Virbhadra-ji. It was during Mr Vajpayee's premiership. The flowering of the Trust took place particularly in those years. So we insist that the Central Government should be very much in the picture and in decision-taking process.
How Indians would react if Mahatma Gandhi Museum in South Africa were run by a village panchayat? How Russians would react if Leo Tolstoy's Memorial Estate in Yasnaya Polyana were run at a district level? These are not even national, but international monuments. The Kullu Valley Naggar of the Roerichs does not belong only to Himachal Pradesh, not even to India or Russia. It has world cultural heritage importance, especially for the Russians. It has exceptional civilizational and cultural value. This fact must be kept in mind by any government in Himachal Pradesh and the Government in New Delhi.
I would not agree that there is a stalemate. In the past few weeks there have been hopeful and positive signs. We are expecting now a number of specialists coming from Moscow, a new Russian curator will arrive, he is also a famous Indologist, a scientist of high stature and a Roerich man. Engineers will also come as the house needs immediate repairs. Also we get some good signs from the Himachal government, from the Chief Minister, from the new Chief Secretary. The previous Chief Secretary, outwardly a cultured and elegant person, was requesting Delhi to expel all Russians from the Trust! She did not reply to any of my more than a dozen letters. How can you expel Russians from the Roerich Trust? It is pure nonsense. Is not it schizophrenic to propose such a thing?
The Roerich phenomenon in the world culture is not limited only by the Roerich Pact on protecting monuments which later became a UNESCO convention. India is the signatory to this convention. That is why the Central Government cannot leave the Trust at the mercy of a DC.
Now, large-scale plans are being undertaken in the Kullu Valley to build a Roerich art school. We have sanctioned it and agreed to help. Money given by the previous government is there. But nothing is moving forward. The Trust has decided not to invite any favoured or public work divisions, because the latters put four bricks, grab all the money and leave everything unfinished. When we invited a private company, we immediately achieved tangible success there. There should be no diktat on the Trust as regards the choice of constructors or repairers.
Will Russia assist in the activities of the Roerichs' memorial complex in Naggar, with attracting sponsors being one of the aspects? What are your plans for the near future?
It is good when donations come. If a Russian company sends 100 thousand US dollars to the Trust account, it is good. That is how we were working those ten years. Apart from A.B.Vajpayee, the Central Government has not invested a single rupee in the Trust. The way the Naggar museum looks now, it is all due to sponsors, friends from many countries and from the Embassy.
I think this matter will remain within the focus of our official contacts with the Indian Government for all times to come. As a matter of fact, the situation in Kullu was discussed with External Affairs Minister S.M.Krishna at his Moscow meeting with Russian Foreign Minister Sergey Lavrov last November. This matter was also raised at the recent bilateral consultations as well as during the last visit of Prime Minister Manmohan Singh to Moscow in 2011. Insofar we have not received any official reply from the Indian government.
We are looking into the future with optimism. We have the 20th anniversary of the Trust this July. Though the Trust was registered in 1993, it was officially started in July 1992. We have plans with the Himachal government to have grand celebrations with a children's dancing company flown in specially for this occasion from Russia. When the transfer of powers takes place in the Naggar museum, we hope that we shall start work again. But... all the negative things I mentioned above should be rectified, for they are the obstacles for smooth sailing forward.
nicholas roerich RIR


A super cute pawprint charm, sculpted to fit your pet's own pawprint perfectly. Hand made to order and deep engraved with your pet's own print, each charm is totally unique, and would be a wonderful gift for any pet lover. A short personalised message can be engraved on the back.
~ approx (h) 16mm (w) varies by print (d) 2mm.
Anything else we need to know about your order? For instance, a need-by date, preferred gold colour, or if you want your prints darkening on a silver charm?


Did you ever buy or sell someting on openbazaar?
is #DelistBSV ethical and sets a good president for self regulation?
What crypto debit card(s) are you using?
Do you make a significant portion of your income on the Internet?
Which videogame platforms do you play?
when did you take part in the memo?
Which of these two Bitcoin blockchains would you consider indicative of a larger economic system?
Some guy comes along with a wheelbarrow and demands that you affirm him as Satoshi.
Do you bend the knee?


Cheap parking at fullerton. 8 parking at fullerton airport are available in the latitude 33.8703645 & longitude -117.92421230000002 for long term and short term provided at the best rates. Our prices are cheap and our lots are secure. Use our discount coupons to get even a better deal!


text:
Q: How to filter mongo db documents using timespan with respect to Epoch time? I have a document format as follows in MongoDB. The UpdatedOn is Epoch time. Is there a way I can filter the documents in my collection so that I get only the docs updated within the past hour?
{
    "_id" : ObjectId("5c29f3123d8cf714fd9cdb87"),
    "Machine" : "machine1",
    "Pools" : [
        "Pool1",
        "Pool2"
    ],
    "UpdatedOn": 1546330204
}

A: You need to calculate the Epoch time on a client side, try in JS / Mongo shell:
db.col.find({ UpdatedOn: { $gt: new Date().valueOf() - 1000 * 60 * 60 } })

valueOf returns the number of millisecond since midnight January 1, 1970 UTC

redpajama_set_name: RedPajamaStackExchange


text:
TVO Original "Coppers" takes an "unflinching look" at the lives of retired officers
TVO is presenting the world broadcast and online premiere of TVO Original Coppers on TVO and tvo.org on Monday, March 30, at 9 p.m.
Made by award-winning documentary filmmaker Alan Zweig, (There is a House Here), Coppers offers an "unflinching, harrowing, and compassionate" look at the careers of retired police officers.
"In a profession marked by adrenaline and chaos, but also by suicide and marital breakdown, no one leaves the job unscathed," TVO states. "Using his trademark probing interview style, Zweig turns his lens towards the fabled 'blue wall', shedding light on what it really means to serve and protect."
"Perhaps the most striking feature of Coppers is how deftly Zweig gets his subjects to open up about deeply affecting topics; whether it's extreme stress, racism, sexism, or guilt, this film leaves no stone unturned," says John Ferri, TVO's vice-president of current affairs and documentaries.
"I made Coppers as a follow up to A Hard Name about a group of middle-aged ex-convicts," says filmmaker Alan Zweig. "It occurred to me that audiences might be more empathetic to ex-cops than to ex-cons."
Coppers will be available to stream across Canada on tvo.org and will rebroadcast on TVO April 1 and 4 at 9 p.m. EST.
Doctors at B.C. hospital question why police eavesdrop on suspects in ER
ISCPP Symposium returns to Canada after 30-year hiatus
Police: Nothing questionable about body camera video
Police search for driver after crash hurts two officers in Burnaby, B.C.
Woman in Newfoundland arrested for refusing to self-isolate after talking to police
McDonald's employee charged after faking COVID-19, forcing restaurant to close

redpajama_set_name: RedPajamaCommonCrawl


GMC Envoy XUV. They're bigger than regular Envoys. They don't seem all that much more practical than a regular Envoy... if you needed more space in 2004 just step up to an Envoy XL orTahoe/Suburban for a little more money.
These didn't sell well and at least for me, I see one... maybe once every 6 months.
Somewhat unrelated... I really like the Seq's power rear window.


CommonSENSE is a participatory design toolkit which aims to support communities, neighbors, flat mates, researchers and hobbyists, to creatively explore the potential of their own living space and actively engage them in its design and re-arrangement. Through a sensor kit gathering real time space occupancy data and an online design engine where users access and act upon these data to produce or evaluate design solutions, the platform enables users to document and share their habits and desires, visualize design ideas and test them in physical space. CommonSENSE envisions an alternative definition of "environment intelligence" where embedded systems and information technology turn users into active participants in the design of their living environment. This paper presents the implementation details of this participatory platform prototype in the case of the Athenian typical apartment block (polykatoikia) and discusses its spatial and theoretical implications from three different perspectives: as a participatory design engine prototype, an "urban intelligence" tool and an open source development toolkit.


text:
Aglaoschema inca is a species of beetle in the family Cerambycidae. It was described by Napp in 2007.

References

Aglaoschema
Beetles described in 2007

redpajama_set_name: RedPajamaWikipedia


text:
Coenonympha albomarginata är en fjärilsart som beskrevs av Tutt 1909. Coenonympha albomarginata ingår i släktet Coenonympha och familjen praktfjärilar. Inga underarter finns listade i Catalogue of Life.

Källor

Praktfjärilar
albomarginata


How would society run without computers? Keeping in mind that most every electronic device uses a computer one way or another, the world would be set much further back. The advancement of microprocessing and OS's allowed a general increase in jobs and speed in development of ideas and designs. Computers have advanced the way people build and design things, store information, and communicate with each other. Microprocessors have shaped how computing developed through the years.
The microprocessor originated back in 1971 with the Intel 4004. It was a 4 bit BCD (Binary-Coded Decimal) oriented microprocessor. It helped advance the computer industry in ways such as giving other manufacturers a baseline to work off of and some competition in the field of microprocessors. The 4004 really was the start of microprocessing in the computer industry. This card only ran at 740 kHz which really shows the advancements that have been made up until today's processors with 4 GHz and higher clock speeds.
Communication has changed vastly over the course of approx. 50 years of computer development. The phone was the origin of the technology used for communication over the internet. Phone lines were used for dialup connections which allowed users to communicate over the phone lines. This presented a problem though; When a person in the house would use the phone, the internet would not function properly, rendering dialup inefficient. The most recent form of connection is Ethernet. Ethernet allows Gigabit speeds and uninterrupted connection.
This technology has allowed global near-instant sharing of data and information. The world trade system is reliant on the internet and therefore has been a huge focus by manufacturers worldwide. The ability to store information anywhere you want and it at any time and place is priceless. That is what is called the "cloud". Servers around the globe host services that allow users and companies to store information and retrieve it at any time. This technology was recently made available to almost all platforms but the concept has been around for a while.
The capability to store files for retrieval anywhere has accelerated how data is managed. The consumer didn't actually have much to work with that was computer-related up until 1983 with the Apple Lisa. This computer was the first computer to have a GUI and, despite being aimed toward business customers, was a huge step in the direction of the computer monitor in use today. The amount of pixels in monitors since the Apple Lisa has greatly increased allowing much higher resolutions to be displayed since its creation.
The baseline for Microsoft operating systems today originated in 1981 with MS-DOS. It is a text based command prompt primarily used by IT and manufacturers to manage and change different configurations and setups in the computer. The creation of this operating system allowed computers based on microprocessor the time to advance along with the operating system technologies. The improvement of this technology came along with Windows 1. 0, released in 1985.
This OS provided the beginning of Microsoft's Windows line that has finally lit up to Windows 8 ironically having near identical icon to Windows 1. 0 and 2. 0. Online stores have become a very popular way of purchasing items and getting them shipped to our home within a few days. These stores are made possible by servers hosting the site and the complex network of routers and switches that lead from a home router all the way to a server. This immediately posed the issue of security. How can one be sure that their credit card information will be secure on the Internet?
A new Internet protocol was created called Hypertext Transfer Protocol Secure which basically layered HTTP on top of SSL/TLS protocol. Most websites that allow purchasing of goods show HTTPS usage in the URL bar. Searching for jobs has become much easier through companies hosting websites and allowing users to apply for jobs remotely. This has greatly sped up the employment process and is also allowed for the company to communicate and/or provide feedback on the application to the applicant much faster and easier.
Organization of documents as much cleaner with the automation of the application process which has allowed employers to narrow down applicants to what they are really looking for before they even step in the office. Unfortunately, this has dehumanized applying for a job and made it harder for people to interact with others upon meeting. The ability for defense networks and companies to use satellites for communication and GPS position tracking has greatly increased the speed at which they can gather information and apply it to their job.
Satellites have also been a huge help to the commencement of the Internet by allowing international communication and trade. The computer has greatly impacted society in more ways than one; advancing communication over large networks, proving how we store data, and organizing and accelerating processes that were normally done on paper. The world will be forever reliant on computers to operate and communicate as well as run most things that work off of electricity.


So much, where to begin?
People getting a real choice about music, venue, and buddies (with Gig Buddies).
People learning to be DJ's and then entertaining other people (Kiss My Disco).
Getting commissioners to raise the bar on expectations about Staying up Late (or choice.
Campaigning; people putting on events for themselves, creating artwork for posters and websites, producing t-shirts and other materials, then selling products at events, enabling confidence building and handling money.
Talks to professionals, work in primary school (raising awareness), anti hate crime work, writing a song, or should I say rewriting a song and getting original artists to endorse; and the ultimate in inclusion Glastonbury, Liberty Festival, New York, mainstream cinema and the Beeb through work of Heavy Load.


text:
<?php

namespace Da\StatBundle\DependencyInjection;

use Symfony\Component\Config\Definition\Builder\TreeBuilder;
use Symfony\Component\Config\Definition\ConfigurationInterface;
use Symfony\Component\Config\Definition\Builder\ArrayNodeDefinition;

/**
 * This is the class that validates and merges configuration from your app/config files.
 *
 * @author Thomas Prelot <thomas.prelot@gmail.com>
 */
class Configuration implements ConfigurationInterface
{
    /**
     * {@inheritDoc}
     */
    public function getConfigTreeBuilder()
    {
        $treeBuilder = new TreeBuilder();
        $rootNode = $treeBuilder->root('da_stat');

        $this->addStatSection($rootNode);
        $this->addAssembliesSection($rootNode);
        $this->addMenuSection($rootNode);

        return $treeBuilder;
    }

    /**
     * stat:
     *     {stat_name}:
     *         roles:
     *             _default: [{role_name1}, {role_name2}]
     *             {client_name}: [{role_name1}]
     *         aggregator: {aggregator_service_id}
     *         renderer: {renderer_service_id}
     *         filter: {filter_service_id}
     */
    private function addStatSection(ArrayNodeDefinition $rootNode)
    {
        $rootNode
            ->children()
                ->arrayNode('stat')
                    ->useAttributeAsKey('dumb')
                    ->defaultValue(array())
                        ->prototype('array')
                            ->children()
                                ->scalarNode('aggregator')
                                    ->isRequired(true)
                                ->end()
                                ->scalarNode('renderer')
                                    ->isRequired(true)
                                ->end()
                                ->scalarNode('filter')->end()
                                ->arrayNode('roles')
                                    ->defaultValue(array())
                                    ->prototype('scalar')->end()
                                ->end()
                                ->arrayNode('labels')
                                    ->isRequired(true)
                                    ->children()
                                        ->scalarNode('title')
                                            ->isRequired(true)
                                        ->end()
                                        ->scalarNode('xAxis')->end()
                                        ->scalarNode('yAxis')->end()
                                        ->scalarNode('legend')->end()
                                    ->end()
                                ->end()
                            ->end()
                        ->end()
                    ->end()
                ->end()
            ->end()
        ;
    }

    /**
     * assemblies:
     *     {stat_name}: [{stat_name1}, {stat_name2}]
     */
    private function addAssembliesSection(ArrayNodeDefinition $rootNode)
    {
        $rootNode
            ->children()
                ->arrayNode('assemblies')
                    ->useAttributeAsKey('dumb')
                    ->defaultValue(array())
                        ->prototype('array')
                            ->prototype('scalar')->end()
                        ->end()
                    ->end()
                ->end()
            ->end()
        ;
    }

    /**
     * menu:
     *     items:
     *         {menu_name}:
     *             stat: {stat_name}
     *             category: stat
     */
    private function addMenuSection(ArrayNodeDefinition $rootNode)
    {
        $rootNode
            ->children()
                ->arrayNode('menu')
                    ->addDefaultsIfNotSet()
                    ->children()
                        ->arrayNode('items')
                            ->defaultValue(array())
                            ->useAttributeAsKey('dumb')
                            ->prototype('array')
                                ->children()
                                    ->scalarNode('stat')
                                        ->isRequired(true)
                                    ->end()
                                    ->scalarNode('category')
                                        ->isRequired(true)
                                    ->end()
                                ->end()
                            ->end()
                        ->end()
                    ->end()
                ->end()
            ->end()
        ;
    }
}

redpajama_set_name: RedPajamaGithub


A Berkeley resident received an unwelcome surprise when his postal worker reportedly threw a package at his front door and proceeded to enter his residence and make criminal threats, according to a Nixle alert released by Berkeley Police Department on Tuesday afternoon.
A postal worker who discarded about 100 election guides in a Berkeley recycling bin ahead of the 2016 elections pled guilty in January to obstruction of mail.
North Berkeley resident Mimi Mugler was in her living room at 1:30 a.m. when she heard some noise on her porch and opened the door to see her mailman standing there.
Due to ongoing litigation with the city of Berkeley regarding its sale, the U.S. Postal Service removed the Downtown Berkeley post office from its commercial listings of buildings for sale earlier this month.
Local developer Hudson McDonald failed to reach an agreement regarding the sale of the Downtown Berkeley post office last week, after months of negotiations and prolonged community protest. Despite termination of the sale and recent police intervention, some protesters remain outside the building on Milvia Street and Allston Way after more than a month of occupation.
The United States Postal Service and the city of Berkeley are in the process of potentially selling the Berkeley Post Office, located on 2000 Allston Way.


From the looks of it, Royal Enfield had a little something to prove before the international launch of its 650 twins. It's a known fact that Royal Enfields are never associated with speed, rather they're popular for relaxed cruising and retro looks. But that's all likely to change with the launch of the 650 twins.


text:
Your home for New Zealand music
Looking For Alaska: Fall Into You
New Zealand folk-pop duo Looking for Alaska have returned with the new single "Fall Into You."
Looking For Alaska released their sophomore self-titled debut album in 2016 which spent 12 weeks on the NZ album charts and was nominated for "Best Debut Album" at the 2017 NZ Taite music awards. "Fall Into You" is the first single from their upcoming album "Light and Shadow" which is set to be released later in the year.
"Fall Into You" is a fun indie-pop song. Aaron Gott and Amy Maynard have delivered a new single that captures the essence of what makes Looking For Alaska such an interesting project. "Fall Into You" builds upon the sound that the band established in their first album. Looking For Alaska incorporates elements of folk, pop, country and indie music to create a moody, heartfelt track that will please both fans and newcomers.
Looking for Alaska is an ambitious project. The duo is not afraid to use an extended range of instruments to create their signature sound. Fiddle virtuoso Pascal Roggen (NZ's Albi & The Wolves, UKs Shez Raja) makes a special appearance on the track and it works masterfully well. The blending of instruments gives "Fall Into You" a very unique sound.
Amy Maynard gives a fantastic vocal performance on this track. Maynard has a very angelic voice that lends itself well to the genre. "Fall Into You" is a heartfelt song about longing for someone and the emotion and range of Maynard's vocal performance on the track make "Fall Into You" an exceptional first single for the forthcoming album.
You can listen to "Fall Into You" here;
by Craig Westenberg
Raiza Biza: Around The Way
Valleyside Boys: 3 Pack
Elleio: Play Pretend
FABLE: A Place Called Home
Dharmarat: WUTA
We aim to showcase the next generation of New Zealand's talent.
With a range of features and interviews with some of the scenes rising stars, Something Different is your go to for all things music, art and lifestyle.
Featured Release – Emma Dilemma 'New Attraction'
Processed with VSCO with kp6 preset
A Conversation With Sofia Machray
Park Rd: Control
Oh Sweet Nothings: Shinbone


This year was my first year to participate in National Novel Writing Month, and I won! The goal is to write 50,000 words in thirty days. I reached the 50k word goal today, but my novel isn't done. I'm close to the end but still have a couple thousand more words to write before I can type… Read More NaNoWriMo WIN!


This newer built, Tuscan inspired, south of Ventura Blvd home has 5 bedrooms, 4.5 bathrooms in almost 5,000 sq ft, on over a 1/3 acre flat, private, and gated lot. Wood and stone flooring, granite counters, crown and base moldings, stainless steel appliances, plantation shutters, 3 fireplaces, a rotunda entry hall, iron railings, several balconies, antiqued stone accents and a barrel tile roof are just some of the details. Other features are a formal living and dining room, downstairs office, family room with an eating area adjoining the center-island kitchen, master bedroom with soaring ceilings & views, 2 large walk-in closets, a sitting area and a luxurious bathroom with a double-sided fireplace. The park-like grounds feature numerous fruit trees and rose bushes, a perimeter of tall ficus hedges as well as a gorgeous swimming pool and spa.


text:
Public Key Infrastructure EXPLAINED
by Cog Editor | Sep 19, 2018 | Cogito ergo sum
In the real world…
In the real world, physical documents, hand-written signatures, sealed envelopes, photo identifications and established relationships are measures against fraud.
Public Key Infrastructure (PKI) translates the trust conventions in the real world and makes them work online.
PKI has many uses, but its primary use is providing data integrity through encrypting information. Encrypting information makes it unreadable to everyone except those authorised to see it.
Here is everything that plays a part in PKI:
A certificate authority that issues and verifies digital certificates
A registration authority that acts as the verifier for the certificate authority before a digital certificate is issued to a requestor
One or more directories where the certificates or public keys are held
A certificate management system
Authentication ensures users are who they claim they are, which enables resource access control decisions to be made. PKI provides identification and authentication through digital signatures.
A challenge is created
The challenge is signed by the holder of the private key the digital certificate
The registration authority verifies the digital certificate
The registration authority now knows that the holder of the key is the entity named in the certificate
The holder the public key can view the digital certificate
Confidentiality encodes information in to a format which is incomprehensible to attackers.
When a public key in a digital certificate is used to encrypt information, only the holder of public key can decrypt the information.
Data integrity ensures that information cannot be changed without detection.
When the recipient of digitally signed information can verify the signature on the information, then the recipient knows the content has not changed since it was signed.
Non-repudiation
Non-repudiation prevents users from denying involvement an electronic transaction.
When information has been digitally signed, only the entity named in the digital certificate has access to the private key used to sign the information, and can therefore be assumed to some level of assurance to have been the entity that generated the information.
Here are the key areas where PKI assists organisations:
Encryption and authentication for internal and external web pages (e.g. Internet banking)
Logical access control by provide logon using strong authentication (e.g. smart card logon)
Allowing single sign on to resources
Authentication to different environments (e.g. Windows to Unix)
External access to corporate network services
Messaging solutions (e.g. email) for encryption and message integrity
Document signing of forms and formal correspondence
Transaction Signing of critical services such as Databases and of financial transactions
Resource Communications validation and/or encryption between devices
Encrypted File System
Remote secure administration of ICT assets
Remote access for mobile devices
Timestamp Services
Physical Access to facilities and equipment
PKI is important as it provides the building blocks to allow security solutions to be realised – it is not the end solution, but it is essential in enabling other solutions to create a tangible outcome.


text:
package com.mxixm.fastboot.weixin.test;

import com.mxixm.fastboot.weixin.annotation.*;
import com.mxixm.fastboot.weixin.module.event.WxEvent;
import com.mxixm.fastboot.weixin.module.menu.WxMenu;
import com.mxixm.fastboot.weixin.module.message.WxMessage;
import com.mxixm.fastboot.weixin.module.message.WxMessageBody;
import com.mxixm.fastboot.weixin.module.user.WxUser;
import com.mxixm.fastboot.weixin.module.web.WxRequest;
import com.mxixm.fastboot.weixin.module.web.WxRequestBody;
import com.mxixm.fastboot.weixin.module.web.session.WxSession;
import org.apache.commons.logging.Log;
import org.apache.commons.logging.LogFactory;
import org.springframework.boot.SpringApplication;

/**
 * 微信菜单接口
 *
 */
//@WxController
//@WxApplication(menuAutoCreate = false)
public class WxButtonMappingTest {
	private final Log log = LogFactory.getLog(this.getClass());

    public static void main(String[] args) throws Exception {
        SpringApplication.run(WxButtonMappingTest.class, args);
    }

    @WxButtonMapping(names = "*消息")
    public void left(WxMenu.Button button) {
        System.out.println(button);
    }

}


Thank you SO much! We can't put into words how over the moon we are with how the wedding day went. Every element was just as we imagined and more! And South Farm looked so stunning! Me, Steve and all of our guests were so very happy. There's not a single photo where me and Steve don't have the biggest grins! Compliments also to the Chefs! The vegan food was divine and everyone loved it!


The history of glassmaking stretches back thousands of years. During the second half of the 20th century, this craft was expanded to include a new field – studio glass. This resulted in new works comparable to contemporary painting and sculpting. The former Czechoslovakia soon became a major player in studio glass production, boasting such globally recognised names as Stanislav Libenský and Jaroslava Brychtová; Miluše and René Roubíček; Václav Cigler; Vladimír Kopecký; Jiří Harcuba; and František Vízner.
The Portheimka Summer Palace features works from a number of noted glass artists. Such works are presented in a manner designed to reflect the location's historic baroque atmosphere. Individual rooms evoke past glories, when the Palace was used to lift spirits, entertain, and enthral. The rooms carry specific names: Chapel, Banquet Hall, Marble Hall, Landscape, Study and Theatre. In addition to its permanent glass art exhibition, the Portheimka Museum also offers a rich and engaging programme of short-term exhibitions as well as events geared towards education, enlightenment and cultivated entertainment.


Exclusive as well as public business supply a variety of different training courses. It can be hard to discover training courses that appropriate for your requirements. This is especially true of training courses that have numerous degrees, methods and certifications. Whatever kind of course you choose, you wish to ensure it has the finest quality education. To assist you narrow down your training choices we have a few pointers.
You will certainly need to identify what type of training you require. Are you changing occupations, upgrading your knowledge for your company, etc? The right training will assist you raise your knowledge, abilities, and also associates in an organisation environment. Every profession has adjustments in the workplace. Brand-new devices can be added or a brand-new software program system that needs training. To find the ideal training courses you have to know what you seek. There are training evaluation tools to aid you find the type of courses you require. They will certainly aid you evaluate your existing abilities, quantify your skills, determine what you require to alter professions or move on, examine your sources, and then help you prepare for the ideal training courses.
There is a full series of training courses offered. Specialist and also individual training exist to aid improve your work skills. IT abilities are most preferred in training programs because the market continues to advancement. IT programs are additionally essential for a variety of other industries due to the fact that a qualification on Microsoft Office or various other software application can boost a career.
We pointed out that there are different levels to the training programs offered. Introductory programs provide a basic structure for what you require to learn. Frequently these training programs are brief in duration. As you move up in the level of course you will certainly be able to earn qualifications or credit rating. A higher degree course offers an extra extensive view of the information. You additionally want to think about whether a training course will certainly supply hands on training.
Hands- on training permits you to work with the program, devices, or various other aspects of the training course information differently. For example, a Microsoft Workplace course provides training using the software application along with a book. Locating the appropriate training program can additionally be based on exactly how you learn. Hands- on training might be much better than reading a book for some individuals.
After considering your strengths and weak points you need to consider where you intend to take the training course. A public organization that supplies online training programs might function around your active routine. Nonetheless, you still want to ensure any type of training course you take provides accreditation or debt. There are a variety of internet sites offering training in certain topics, however not every one of these web sites are recognized. As a matter of fact a few of the training websites have actually produced their very own CD up for sale, but do not have the expertise you require in a training program.Learn more about Customers service skills training here.


(PRESS RELEASE) -- BetterBetting Foundation, a software systems enabler for sports betting on the blockchain, today launched its pre-Initial Coin Offering (ICO) sale ahead of its ICO in December. The token sale introduces investors to BETR, the betting cryptocurrency that will lay the foundations of the first truly decentralized peer-to-peer sports betting marketplace on the internet. Supported and advised by a number of industry veterans, BetterBetting will introduce a revolutionary twist on the betting exchange model, completely eradicating the middle man from the equation.
All bets will be stored on the blockchain, providing full transparency and provable fairness on all transactions, thereby eliminating all human or business activity between the two betting parties.
Ultimately, the software and standards that comprise the system will be open source and free for anyone to copy and use, paving the way for BETR to become the exclusive cryptocurrency of some of the world's leading gaming operators.
BetterBetting is seeking a minimum $2 million and maximum $30 million raise from December's ICO. These funds will be used for the development and release of the BetterBetting protocol, the development and open-sourcing of dapps and node software, and marketing to key stakeholders and consumers as well as legal and administrative costs.
Core to the BetterBetting system is software that implements a distributed directory of sporting events and markets, while placing bets as contracts onto the blockchain. This software is called the Better Betting Node (BBN). It acts as a distributed mirror for directories, facilitating a standard repository for sporting information that can be added to by any agent on the network and queried in order to present user-friendly client interfaces to punters.
That means not only is it easier than traditional methods to find any specific bet, but it also makes it possible for bets to be standardized and pooled together.
A tiered bonus system will be built in to incentivise early investment in the ICO. Thereafter, tokens will be issued at ICO value, which is set at the closest Ethereum price to 10 cents per token.
"With Better Betting, we are excited to bring a new paradigm to the world of sports betting," said Adriaan Brink, CEO & Founder, Better Betting Foundation. "By combining the power of blockchain with our experience and knowledge of the sports betting industry, we are introducing a new betting currency that understands the underlying structure of a sports bet, ensuring fair and robust betting opportunities between two parties, who do not have any relationship with one another.
"Working with major industry players, this decentralized liquidity marketplace for sports betting can be used in many different ways and provides automated programmatic interfaces so that existing sportsbooks can link into the system. Working with, rather than against, major industry players with a zero margin model, we seek to provide the railway tracks for sports betting in the future."


1993-06-17 Assigned to DIGITAL EQUIPMENT CORPORATION reassignment DIGITAL EQUIPMENT CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SAGER, DAVID J., ADLER, MICHAEL C., EMER, JOEL S., LOWNEY, GEOFFREY, MCKEEN, FRANCIS X., NIX, ROBERT P.
A compiler groups instructions into sets. The sets of instructions are related by data and control dependencies which are unresolvable by the compiler. Sets of instructions having unresolved dependencies are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition is detected and the set of instructions is re-executed in a real state of the computer system to resolve the exception condition.
This invention relates generally to executing instructions in a computer system, and more particularly to a method and apparatus for speculatively executing instructions.
Conventional digital computers process instructions of a program in accordance with fetch and execute cycles in which instructions are fetched from memory and executed by the processor. Each fetch or execute cycle may include a number of intermediate steps. For example, the processing of an instruction manipulating data may require the fetching of additional operands from memory, and the storing of data generated as a result of the execution of the instruction. Or, the processing of an instruction manipulating the control flow of the program may examine the value of the operands and alter the program flow accordingly.
In conventional low speed computers, the fetch and execute cycle are performed for one instruction at the time. That is, the fetch for the next instruction does not occur until the previous instruction has been completely processed. The hardware that is used during the fetching steps remains idle until it is needed for the next instruction.
However, the speed at which computers can process instructions and data has increased much faster than the speed at which memory can supply the instructions and data to the computer. This memory latency can be hidden by processing multiple instructions concurrently. For example, the next instruction is fetched from memory prior to storing the result of the previous instruction. This is a simple form of instruction level parallelism or pipelining.
Also, the size of computer chips has increased faster than the speed of the logic circuits on the chip. Therefore, a further performance advantage can be gained by using the larger available space on the silicon to process multiple instructions in parallel.
The total throughput of the computer can be further increased by pre-processing or accelerating the execution of certain instructions, particularly instructions which require a large number of cycles, or which may be subject to long latencies. For example, a load instruction may attempt to read data which are not stored in a local fast memory such as a cache. In this case a subsequent instruction operating on the data can not be executed until the data are read, possibly from a virtual memory device. It would be an advantage to move such instructions up in the execution sequence so that the data become available earlier.
Pre-processing of instructions is sometimes known as speculative execution. Speculative execution is also known as the condition where all of the dependencies, control and data, for the instruction are not resolvable at the time the instruction is generated.
Various techniques are known for providing speculative execution of instructions. For example, speculative execution is sometimes engineered at run-time by dynamically processing instructions out of their original order. Other techniques, reorder the execution sequence of the instructions of a program at the time that a source program is compiled into a run-time program or object code. Some techniques require the use of complex hardware not readily adaptable to simple processors such as RISC computers.
A serious problem with the known techniques of speculative execution is the correct detection and management of exception conditions that occur. Exception conditions are signals used to indicate unexpected conditions, for example, the processing of the instruction could not be completed, or the result generated requires further attention, due to, for example, address faults, arithmetic inconsistencies, and the like.
An exception condition that occurred for a speculative instruction which should not have been executed must be ignored. On the other hand, an exception condition for a speculative instruction that was supposed to be executed must be signaled. Most known techniques execute instructions speculatively with the understanding that the instructions will not generate exception conditions. Enforcing these restrictions generally constrain the degree of parallelism possible. Should an exception condition occur anyway, known techniques generally abort processing altogether.
Recovery from an excepting speculative instruction should be possible. This is particularly true for instructions which are executed speculatively in a loop. For example, an instruction which is moved up in a loop may be rendered superfluous by the control flow during the last iteration of the loop. Therefore, an exception condition for that instruction, can generally be ignored.
Furthermore, known techniques of speculative processing of instructions generally do not permit the execution of instructions which may have data dependencies, that is, instructions which consume data before the validity of the data can be determined.
Therefore, there is a need for a mechanism which allows for the speculative execution of instructions without undue restrictions, especially when exception conditions are encountered.
There is provided a mechanism for executing instructions speculatively in a computer system. The mechanism includes a compiler for generating instructions to be executed in the computer system. The compiler groups instructions into sets of instructions related to each other by dependencies which can not be resolved until the instructions are actually executed. Unresolvable dependencies can be data and control dependencies. A set of instructions has data dependencies if the validity of the data used by the set of instructions can not be resolved by the compiler. If the execution flow of the set can not be resolved, the set has control dependencies. Sets of related instructions are called threads.
The sets of instructions are executed in a speculative state of the computer system under the assumption that an exception condition will not occur. If the set of instructions is successfully executed, data generated or manipulated by the set can be incorporated into a real state of the computer system. However, if an exception condition does occur while executing a set of instructions in the speculative state, that exception condition must be detected so that the execution of the set can be repeated in the real state to resolve the exception condition.
Therefore, a mechanism is provided to detect any exception conditions which occur while executing the set in the speculative state. The mechanism provides for marking data with an exception flag if the data is used by an instruction which is subject to an exception condition. The exception flag is propagated to any data derived from data already marked. In addition, the data are marked with a memory address of the first instruction of the set. Thus, simply by examining the markings associated with the data, an exception can be detected, and the set of instructions can be re-executed.
In an exemplary embodiment, data manipulated by the set are stored in general purpose data registers. Associated with each data register is a state register for storing the exception flag and the memory location of the set using the data stored in the corresponding data register.
Also disclosed is a scheme for detecting improper reordering of the instructions of a set by the compiler. A content addressable memory stores the memory address of data read from a main memory of the computer system. This address is compared, in the content addressable memory, with the memory address of data to be subsequently written to the main memory. An exception signal is generated if the read and write addresses are identical. The exception signal can be used to re-executed the instructions of the set in the correct sequence.
FIGS. 12 is block diagram of a procedure for speculative instruction execution.
FIG. 1 is a top level block diagram of a digital computer system 10 for speculatively executing multiple instructions. The digital computer system 10 includes a main memory 20 for storing instructions and data processed by at least one central processing unit (CPU) 30. The CPU 30 communicates with the main memory via bus 21. It should be understood that additional CPUs could be used in the computer system 10 by sharing main memory 20 via bus 21.
As shown in FIG. 1, the CPU 30 includes at least three functional units: a memory access unit 40, an instruction unit 50, and an execution unit 60. These units are sometimes referred to as the MBOX, IBOX, and EBOX, respectively.
The memory access unit or MBOX 40 typically includes a high-speed cache memory storing a copy of a small portion of the information stored in the main memory 20. The cache is employed to increase processing speed by reducing access time to main memory 20 when fetching data and instructions. The MBOX also usually includes a translation buffer, in the form of, for example, a high speed associative memory, to perform virtual to physical address translation during memory accesses.
The instruction unit or IBOX 50 includes a generally conventional program counter (PC). The PC is maintained so that instructions are fetched from main memory 20, via the MBOX 40 and bus 21, in the proper run-time sequence. For example, branch instructions can cause instruction to be fetched in an order different from the stored order. The PC preferably also uses virtual memory addresses rather than physical memory addresses.
The EBOX 60 includes, for example, hard wired logic circuits to perform the operations of the instruction. The invention can also be used with processors of the type which use microcode to process the instruction. Result data generated during the execution of an instruction are subsequently passed back through the MBOX 40 to main memory 20.
The EBOX 60 also includes a generally conventional register bank or register file (RF) having a plurality of general purpose registers (GPRs), generally indicated by reference numeral 61. The RF 61 is for storing data processed by the instructions during their execution. For example, the CPU 30 may have 64 integer registers and 64 floating point registers.
Typically, during the execution of instructions, data are read from main memory 20 into one or more of the GPRs by, for example load instructions. Operations on the data, such as additions, multiplications, and the like, are generally performed on the data stored in the GPRs, since the GPRs can be accessed more quickly than main memory 20. Result data generated during the execution of an instruction are subsequently retrieved from the GPRs, and written back in main memory 20 by, for example, store instructions.
The instructions stored for processing by the computer system 10 are generated by a software program, for example a compiler 23. The compiler 23 translates source code to object code. The compiler 23 is a software program stored in main memory 20 during execution. In the preferred embodiment of the invention, the compiler 23 reorders the sequence of instructions in order to increase total system throughput.
This reordering of the instructions results in the speculative execution of instructions before their use, benefit, or exceptions conditions are known. The compiler can move instructions up in execution order, for example, before branch instructions which may render the moved instructions unneeded. Also load instructions can be ordered ahead of the instructions which store the data.
In order to correctly manage data which may be subject to exception conditions, the compiler, during code generation, assigns registers idempodently. Idempotent register assignment means that the compiler does not change the set of registers which is used for temporary data storage during a particular instruction sequence. That is, during allocation of registers among the various instructions manipulating data in registers, a register is not recycled for storing different data until a point is reached in the execution flow where it is known that the exception condition is resolved.
The techniques described herein are intended to handle the speculative execution of instructions which have been reordered by the compiler 23. The techniques allow for the detection of exception conditions, and the re-execution of the instructions subject to the exception conditions.
Therefore, according to the preferred embodiment, and as is shown in FIG. 2, the digital computer system 10 can assume a real state 1 and a speculative state 2. The real state 1 is the state where all dependencies at a predetermined program counter address have been resolved. The speculative state 2 is the state where the dependencies have not been resolved. Real instructions are executed in the real state, and speculative instructions are executed in the speculative state. The correct program state is enforced at the time that any speculative result data generated from the speculative execution of instructions are deemed ready for incorporation into the real state 1. Note, that the transition 3 from the speculative to the real state coincides with the point at which the compiler 23 can recycle register numbers, now that any dependencies of the data in the registers have been resolved.
The execution flow of a program processed by the computer system 10 comprises both real and speculative instruction execution. The real execution of instructions generating data in the real state 1, and the speculative execution of instructions generating data in the speculative state 2.
Furthermore, speculative execution, according to the embodiments of the invention, comprises two types of executions: data speculative and control speculative.
Execution is defined as data speculative if the validity of the data used during the execution of the instruction is not known at the time of execution of the instruction. In other words, an instruction is data speculative if there are unresolved data dependencies.
FIGS. 3 and 4 show an example of an instruction sequence having data dependencies, before and after re-ordering. In FIG. 3, a STORE 31 is followed by a LOAD 33, and an OP1 34. It is presumed that the OP1 34 requires the data read by the LOAD 33.
As shown in FIG. 4, it would be an advantage to accelerate the execution of the LOAD 33 to increase throughput, since it known that instructions which read data from memory may have relatively long latencies. In other words, by moving the LOAD 33 up in the execution sequence, the execution cycles of the LOAD 33 used to fetch the data substantially overlap, or are executed in parallel with subsequent instructions. However, if the LOAD 33 is moved ahead of the STORE 31, as shown in FIG. 4, the STORE 31 may write the data needed by the LOAD 33. This is an example of data dependency. However, if the memory addresses of the STORE 31 and the LOAD 33 are computed dynamically, it can only be determined at run time if the LOAD 33 is in fact dependent on data supplied by the STORE 31. In other words, in this case, it is not possible for the compiler 23 to resolve the dependencies. In fact, it is not known whether there is a memory address conflict until after the instructions have been executed. For this reason the sequence of instructions shown in FIGS. 4 has data dependencies.
Execution is defined as control speculative if it is not known at the time of generating instruction whether the instruction should have been executed. This is, the control flow of the instructions is unresolvable.
FIGS. 5 and 6 show an example of an instruction sequence executed repetitively in a loop having control dependencies, before and after reordering. In the example, it is presumed that there are N iterations of the loop, expressed as i=1 to N, and x(i) means the data stored at a location corresponding to x(i).
In FIG. 5, an LOAD x(i) 51 is followed by an OP1 x(i) 52, a TST x(i) 53, and a BRANCH 54. During the first iteration, the load is for x(1), the second iteration x(2), and so forth. It is presumed that the OP1 x(i) 52 requires the data read by the LOAD x(i). Therefore, during each iteration of the loop, the OP1 x(i) 52 can not be executed until the LOAD 51 has completed.
It would be an advantage to accelerate the execution of the LOAD. By accelerating the LOAD, the latency associated with the LOAD can be hidden to increases throughput. Therefore, as shown in FIG. 6, the first iteration through the loop, LOAD x(1) 61, is handled outside the loop. The first instruction of the loop is now primed to fetch the data for the next iteration of the loop, LOAD x(i) 62. This instruction is followed by the OP1 x(i-1) 63 which during the first iteration operates on data associated with x(1), and during subsequent iterations operates on data loaded during the previous iteration, e.g., x(i-1).
In other words, while the loop is processing data loaded during the previous iteration, the data for the next iteration is fetched on the speculation that there will be a next iteration of the loop. This will be true for all but the last iterations of the loop. By overlapping the fetch for the next iteration with the processing of the previous fetch, the latency associated with the load instruction is effectively hidden.
However, under certain conditions, as determined by the control flow of the loop is changed, rendering the execution of the LOAD x(i) 62 superfluous. For this reason the sequence of instructions shown has control dependencies.
According to the embodiments of the invention, instructions generating data in the speculative state 2 are instructions that have been executed under the assumption that the result data generated during their execution will, at some point in the future, be incorporated into the real state 1. However, result data generated by the speculative execution of instructions are not incorporated into the real state 1, until pending data and control dependencies are resolved.
Any exception conditions encountered when generating data in the real state 1 are serviced immediately. Exception conditions encountered for data generated in the speculative state 2 are held pending until the results are incorporated into the real state 1.
A thread is defined as a set of instructions related by control or data dependencies. The thread begins with the execution of the first instruction in the set of related instructions. The thread ends when the last instruction of the set is executed and the result data generated during the execution of the thread are incorporated into the real state 1.
FIG. 7 shows sets of related instructions, threads 71-74 which are executed substantially in parallel in CPU 30. In each of the thread 71-74, as an example, the instructions executed in the real state 1 are diagonally hatched, and generally indicated by reference numeral 75. Instructions which are executed in the speculative state 2 include threads 81, 82, and 83. The threads 71-74 are generated by the compiler 23 in a manner to maximize the number of instructions that are processed in parallel by the CPU 30.
FIG. 8 shows the organization of an instruction 100 stored in main memory 20 as executable object code produced by the compiler 23, according to an exemplary embodiment of the invention. It should be understood that the CPU 30 can fetch, at any one time, a plurality of instructions 100, for example, four. Each one of the fetched instructions 100 is to be executed substantially in parallel. Each field of each instruction 100 includes one or more bits of data, which will now be described in greater detail.
The instruction 100 includes an opcode field 101 for storing an opcode. The opcode is used to specify the specific operation that should be executed by the EBOX 60. In an exemplary embodiment, the opcode field 101 is six bits. It should be apparent that the opcode field 101 can have a different number of bits, depending on the number and types of opcodes stored therein.
The instruction 100 also includes an operand field 102 for storing one or more operands. The operands are used to specify addresses of data to be loaded and stored during the execution of the instruction. The addresses may reference, by way of example, main memory 20 or the GPRs of the RF 61.
The operand field can include, for example, two source operands, and one destination operand. The exact structure of the operand field 102 is of course dependent on the opcode field 101. It is to be understood that the invention can also be used with computers systems using different types of instruction organizations.
In order to manage the speculative execution of instructions in a thread, the instruction 100 further includes two fields for facilitating the speculative execution of instructions. The two fields are an identification field (IF) 105, and a speculative state field (SSF) 106. The IF 105 and the SSF 106, like the opcode field 101 and the operand field 102, are generated by the compiler 23 when the source code is translated to object code.
The IF 105 includes, for example, two bits to allow the concurrent identification of up to four separate sets of related instructions. Furthermore, when the IF 105 is combined with the program counter of the first instruction of a thread, a unique identification number is generated. This identification number is used to uniquely identify the related instructions of a thread.
The SSF 106 is used to indicate transitions between the real and speculative states 1 and 2, and whether an instruction should be executed in the real or speculative state. In other words, the SSF 106 tells the CPU 30 how to process the instruction with respect to the real and speculative states 1 and 2.
Starting a thread enables the propagation of exception reporting inside the confines of the speculative state 2 in which the thread is executing, until the end of the thread is detected. When the end of the thread is detected, propagated exception conditions are resolved and the result data generated by the thread are incorporated into the real state 1.
The SSF field 106 includes: a start bit (SB) 111, an end bit (EB) 112, and an exception bit (XB) 113. The SB 111 is set to a logical "1" for the first instruction of a thread, otherwise the SB 111 is set to a logical "0". The SB 111 is used to signal the start of execution in the speculative state 2 and enables the propagation of exception signaling.
Furthermore, the SB 111 also causes the current value of the PC to be stored in a register.
The EB 112 is set to a logical "1" for the last instruction in a thread, otherwise the EB 112 is set to a logical "0". The EB 112 is used to signal the end of a thread, and enables the resolution of any exception conditions accumulated during the execution of the thread.
During the transition 3 from the speculative state 2 to the real state 1, as shown in FIG. 2, at the end of a thread, exception conditions are resolved, and speculative result data generated by the instructions of the thread are incorporated into the real state 1.
The XB 113 is set to a logical "1" for instructions which are to be executed in the real state 1, otherwise the XB 113 is set to a logical "0". Any exception conditions encountered for instructions which have the XB 113 set to "1" are signaled and resolved immediately.
For instructions which have the XB 113 set to a logical "0," that is, for instructions executing in the speculative state 2, exception conditions are held pending until the last instruction in the thread has been executed, and the speculative result data are joined with the real state 1.
In addition to the register file 61, the EBOX 60, of FIG. 1, also includes a speculative state register file (SSRF) 62. The SSRF 62 is used to propagate speculative information from source GPRs to destination GPRs during the execution of speculative instructions. The SSRF 62 is also used during the reprocessing of a thread to permit recovery from an exception condition. The technique of reprocessing a thread for exception condition resolution is called "replay."
The SSRF 62 includes one speculative state register SSR for each GPR of the RF 61. That is, there is a one to one correspondence between the GPRs of the RF 61 and the SSRs of the SSRF 62. As will be explained in greater detail with reference to FIGS. 10 and 11, addressing the RF 61 by a GPR number or address yields the data stored in the register, and addressing the SSRF 62 by the GPR number yields the speculative state associated with the GPR.
As shown in FIG. 9, the speculative state of a GPR as stored in each corresponding SSR 201 comprises a register exception flag (RXF) 205, a register identification field (RIF) 206, and a register PC field (RPCF) 207.
The RXF 205 is a one bit exception flag to hold, signal, and propagate the exception state of the corresponding GPR during the execution of the instructions of a thread. If the RXF 205 set to logical "1" the data stored in the corresponding GPR of the RF 61 are subject to an exception condition, otherwise, if the RXF 205 is set to a logical "0" the corresponding GPR data are not subject to an exception condition.
The RIF 206 is two bits. The RIF 206 is used to identify the thread which caused data to be stored in a GPR which are subject to an exception condition. When a thread is started, the IF 105 of the first instruction of the thread is stored in the RIF 206 of the SSR. During the execution of subsequent instructions of the thread the RIF 206 is propagated from source registers to destination registers.
Also, when an exception condition is encountered, the starting PC of the thread is stored in the RPCF 207 of the corresponding SSR 201. The starting PC is the memory address of the first instruction of the thread. The RPCF is used as the initial PC, if the thread is being replayed to resolve any held exceptions.
Subsequently, if a GPR, which has the RXF 205 of the corresponding SSR set to a logical "1", is used as a source GPR for generating data for a destination GPR, the speculative state of the source GPR, as stored in the corresponding SSR is propagated to the SSR corresponding to the destination GPR.
Turning now to FIG. 10, there is shown a "live/dead" circuit for use in an exemplary embodiment of the invention, for use during the speculative execution of instructions having dependencies. The propagation of speculative state information from GPR to GPR during speculative execution is enabled by the live/dead circuit (LDC) 300, as is shown in FIG. 10. The LDC 300 is also used during replay when exception conditions are resolved to enable the incorporation of speculative data into the real state 1 of the computer system.
The LDC 300 includes first and second latches 301 and 302. The input 351 to the first latch 301 is the register address or number of the first source operand, for example, GPR1. The second latch 302 receives as input 352 the address or number of the second source operand, GPR2.
The outputs of both latches 301,302 are used to address the RF 61 and the SSRF 62, respectively. Addressing the RF 61 by the GPR1 and GPR2 addresses yields the GPR1 and GPR2 data 353, 354 to be used by the first and second source operands, respectively.
Likewise, addressing the SSRF 62 yields the GPR1 and GPR2 speculative states 355-356 as stored in the SSRs corresponding to GPR1 and GPR2, including the exception states RXF1 and RXF2 357-358 stored in the RXF 105 of each of the SSRs. The RXF1 and RXF2 are held separately in latches 311 and 312, respectively.
A latch 313 receives as its input a signal DXF 359 which indicates if an exception condition occurred during the execution of the instruction. In other words, the DXF signal indicates that there is an exception condition with respect to the destination operand as a result of executing the instruction.
The outputs 361-363 of the three latches 311,312, and 313 are connected to a three input OR gate 320. The output of the OR gate 320, carrying an EXCEPTION signal 364, is connected to a latch 314. The output from latch 314, a signal PROPAGATE 365, is used to propagate the speculative state, SSR 201, from the source operands of the instruction to the destination operand of the instruction.
The LDC 300 further includes a two input OR gate 330. The first input of OR gate 330 is connected to the output of OR gate 320 carrying the EXCEPTION signal 364. The second input of OR gate 330 receives a signal REPLAY on line 366 indicating whether exception recovery or replay is taking place. That is, the second input to OR gate 330 will be a logical "1" if the instructions of the excepting thread are being replayed, otherwise, if replay is not taking place, the second input will be a logical "0".
The output of the OR gate 330, a signal STORE ENABLE 367, enables the use of data stored in registers during replay. In other words, the output signal STORE ENABLE 367 indicates whether the data in the register were generated by the thread currently being replayed, and are therefore "live". If the data were not generated by the instructions of the thread being replayed, the data are "dead". If the data are dead, they are not used during replay. Otherwise, if the data are live, the instruction needs to be re-executed, and exception conditions encountered are resolved immediately.
Now turning to FIG. 11, there is shown a circuit for enforcing the execution order of selected instructions, according to an exemplary embodiment of the invention. FIG. 11 shows a load instruction passes store circuit (LIPSC) 400. The LIPSC 400 is used to verify the correct order of memory to register loads, and register to memory stores. That is, the LIPSC 400 provides for the recovery of reordered load/store pairs sharing the same memory address. Such reordering is generally not available in known systems, causing fatal program execution errors.
The operation of the LIPSC 400 will be described in conjunction with a sequence of instructions, as shown in Table 1. Note that the instruction sequence shown in Table 1 also shows the idempotent assignment of registers by the compiler 23. That is, the registers allocated to the sequence are not reassigned for other data use during the sequence. That is, each register only has one use during the sequence.
The first instruction (LD) in the thread, i.e., an instruction with the SB 111 set to a logical "1", is a load register from memory instruction. Because SB 111 is set to logical "1" there is a transition from the real state 1 to the speculative state 2. The LD instruction loads general purpose register (r0, or GPR0) from memory location A.
The next instruction (ST) stores data from a register (r7, or GPR7) at memory location B. Note, that the load instruction is out of order. If memory location A is the same as memory location B.
Then, a multiply instruction (MUL) is executed which uses the data loaded into the register by the load instruction of the thread. And the last instruction of the thread, indicated by the EB 113 set to a logical "1", uses the result of the multiply operation in an add operation (ADD).
For data speculative operations, when the store instruction is executed, a determination is made if a preceding load was reordered out of sequence. If so, replay is initiated at the end of the thread to avoid a fatal program error due to the use of invalid data.
The LIPSC circuit 400 allows loads to be moved ahead of stores, as shown in Table 1, to increase the degree of parallelism. Further, the LIPSC 400 circuit allows non-fatal recovery, even if the reordered load/store pair use the same memory address.
The LIPSC 400 includes a first content addressable memory (CAM1) 401. CAMs are well known in the art of computer systems. A CAM, as its name implies, is a memory that can be accessed not only by its address, but also by its contents. That is, the CAM not only includes locations storing data, but also includes a digital comparator which compares, in parallel, the contents of all of the locations of the CAM for a particular data or "content" pattern. If there is a match at any CAM locations, the CAM generates an output signal indicating the occurrence of the match between the "input" contents, and the "stored" contents, for each of the locations where there is a match.
The CAM1 contains, for example, one location corresponding to each of the general purpose registers of the system 10.
Generally, the CAM has two modes (write and read) in which they can operate. In a first mode (write), an input address is specified to store data at a CAM location corresponding to the input address. In a second mode (read), the CAM is addressable by its contents. That is, the input to the CAM is the "contents" for which the CAM is to search all of its locations for a match. In the read mode, the output of the CAM are signals indicating that the contents stored at one or more locations in the CAM match the input "contents".
During a write operation, the CAM1 stores the memory address used by speculatively executed "load" instructions. Load instructions, in general, are instructions which load a register with data from main memory 20. That is, the input address to the CAM1 corresponds to a register address, and the data stored in the CAM1 are the memory address used by the "load" instruction.
During "store" operations, the CAM1 checks whether a speculatively "load" was executed. That is, the load instruction uses the same memory address as a subsequently executed "store" instruction. In other words, if the memory address used by a store instruction was previously written to the CAM1 401, data dependency may exists.
For example, with reference to the instruction sequence above, the CAM 401 stores memory address A after the "LD" instruction has been executed. During the execution of the "ST" instruction, the CAM1 401 is checked to see if memory address B is equal to a previously written memory address A.
The outputs of the CAM1 401, carrying MATCH 410 signals, are connected to a latch 402. It should be understood that the latch 402 has one bit for every location of the CAM1 401. In other words, there is one bit, and one MATCH signal 411 for each general purpose register. If there are any matches in the CAM 1, the corresponding bits in the latch 402 are set to a logical "1" to indicate that LD/ST instruction pairs share the same memory address.
In order to provide a signal which indicate address load/store address matches, the set of outputs of the latch 402, ADDRESS MATCH 411, are connected to a first input of two input AND gates 403. For clarity, only a single gate is shown in the drawings. It should be understood that there is one AND gate 403 for each of the bits of the latch 402. The outputs of the AND gates 403 indicate address matches on load and store instructions.
Should there be address matches, it is also necessary to determine if the load is speculative and related to the store instruction. This determination is facilitated by a second conventional content addressable memory CAM2 404. There is a one to one correspondence between locations of the CAM2 and general purpose registers of the RF 61 and the SSRs 201 of the SSRF 62.
Each location of the CAM2 stores the RIF 206 and the RPCF 207 of the corresponding general purpose register as provided by outputs 416 of the SSRF 62 when the CAM2 is accessed in the write mode during the execution of "load" instructions. In the read mode, at the end of a thread, the CAM2 404 is checked to see if any of the registers used for load and store instructions share the same RIF 206 and RPCF 207. The combination of the RIF and RPCF being the unique identification of a thread. Matches in the CAM2 are indicated as output signals PC MATCH 412. The PC MATCH signals 412 are a second set of inputs to AND gates 403.
If there is a match in both CAM1 (ADDRESS MATCH 411) and CAM2 (PC MATCH 412) the load instruction uses the same memory address as the store instruction. In this case, DATA SPECULATIVE REPLAY SIGNAL 413 is generated by AND gates 403 to signal the requirement for a thread replay.
The outputs of the AND gates 403, DATA SPECULATIVE REPLAY 413, are connected to two input OR gates 405. The other input of the OR gates 405 is a CONTROL SPECULATIVE REPLAY signal 414. The CONTROL SPECULATIVE REPLAY signal is generated from the EXCEPTION signal 364, as determined by the LDC 300.
In either case, the output of the OR gate 405 is a signal REPLAY TRAP 417, which is used to start the reprocessing of the instructions of the thread. The PC at which to start the replay is supplied by the RPCF 207 of any of the registers which have an exception associated with it.
With the foregoing in mind, the speculative execution of instructions will now be further described with reference to the procedure shown in FIG. 12.
In step 500 the next instruction to be executed is fetched from main memory 20, via the MBOX 40, at a location indicated by the PC. In step 510, the SSF 106 of the instruction is examined to determine if the instruction should be executed in the real state 1, or the speculative state 2. If the instruction is to be executed in the real state 1, then continue with step 600, otherwise, if the instruction is to be executed in the speculative state 2, continue with step 520.
The instruction is executed in step 600. In step 620, determine if there is an exception condition as a result of the execution of the instruction in step 600. If there is an exception condition, proceed with step 630 and cause an exception trap to process the exception condition. Otherwise, if there is no exception condition, write the result data in step 900 and continue processing by fetching the next instruction in step 500.
If the instruction is to executed in the speculative state, in step 520 make a determination if the thread is being replayed. If this is a replay situation continue with step 530. Otherwise, if this is not a replay situation, continue with step 700.
In step 700, execute the instruction. In step 710 propagate the speculative state (RIF 206 and RPCF 207) in accordance with the live/dead circuit 300. In step 720, determine if an exception condition occurred. An exception being either a pre-existing exception (RXF) in one of the source operands, or an exception associated with the destination operand as determined by the DXF signal of the LDC 300.
If there is an exception, set the RXF 205 of the destination to a logical "1". Otherwise, propagate the RXF 205. In either case, after step 730 or step 740, write the result in step 900, and continue by fetching the next instruction in step 500.
If this is a replay situation, in step 530, check if the source register is live or dead as determined by the live/dead circuit 300. If the data are dead fetch the next instruction in step 500. Otherwise, execute the instruction in step 800. In step 820, determine if an exception condition occurred. If an exception occurred, generate a trap in step 830. If there was no exception, write the result in step 900 and continue by fetching the next instruction in step 500.
It is not intended that the present invention be limited to the specific embodiment disclosed in the above description and the associated drawings. Numerous modifications and adaptations of the invention will be apparent to those skilled in the art. Thus, it is intended by the following claims to cover all such modifications and adaptations falling within the scope of the invention.
means, responsive to detecting said exception condition, for repeating execution of the plurality of instructions of said particular set in a real state of the computer system to process said exception condition.
2. The computer system as in claim 1 wherein said plurality of instructions include a branch instruction followed in the normal execution order by a load instruction, and wherein said means for reordering further comprising means for moving said load instruction before said branch instruction, and wherein said load instruction and said branch instruction are related by said control dependencies if an execution flow of said load instruction of said particular set is unresolvable.
3. The computer system as in claim 2 wherein said means for executing includes a first content addressable memory for storing said first memory address of data read by said load instruction, said first content addressable memory generating a first signal if said store instruction subsequently attempts to write data to said memory address.
4. The computer system as in claim 3 wherein said means for executing includes a second content addressable memory for storing a second memory address of a first instruction of said particular set including said load instruction, said second content addressable memory generating a second signal if said store instruction is included in said particular set, said first signal and said second signal in combination for repeating execution of said set of instructions.
5. The computer system as in claim 1 wherein said plurality of instructions include a store instruction followed in the normal execution order by a load instruction, and wherein said means for reordering further comprising means for moving said load instruction before said store instruction, and wherein said load instruction and said store instruction are related by said data dependencies if a validity of data used by said load instruction of said particular set is unresolvable, and wherein said plurality of instructions include a branch instruction followed in the normal execution order by a load instruction, and wherein said means for reordering further comprising means for moving said load instruction before said branch instruction, and wherein said load instruction and said branch instruction are related by said control dependencies if an execution flow of said load instruction of said particular set is unresolvable.
6. The computer system as in claim 1 wherein said means for grouping includes a compiler for marking a first instruction of said particular set, said first instruction to activate said means for executing in said speculative state.
7. The computer system as in claim 1 wherein said means for grouping includes a compiler for marking a last instruction of said particular set, said last instruction to activate said means for determining.
8. The computer system as in claim 1 wherein said means for grouping includes a compiler for marking a particular instruction of said particular set, said particular instruction to be executed only in said real state.
9. The computer system as in claim 1 wherein said means for grouping includes a compiler for marking each instruction of said particular set with an identification, said identification for associating each instruction with said particular set during execution, said plurality of sets executed substantially in parallel.
10. The computer system as in claim 1 wherein said means for grouping includes a compiler for permanently assigning registers to the plurality of instructions of said particular set until the plurality of instructions have been executed.
11. The computer system as in claim 1 wherein said means for executing includes means for storing said speculative data, and means for storing an associated state of said speculative data.
12. The computer system as in claim 11 wherein said associated state includes an identification for associating said speculative data with said particular set.
13. The computer system as in claim 12 wherein said identification includes a memory address of a first instruction of said set.
14. The computer system as in claim 11 wherein said means for executing includes means for marking said associated state with an exception flag if said set is subject to said exception condition.
15. The computer system as in claim 14 wherein said exception condition is propagated as said exception flag with said speculative data when said particular set is executed in said speculative state, and said exception condition is processed when said particular set is executed in said real state.
16. The computer system as in claim 11 wherein said means for storing said speculative data includes a set of data registers.
17. The computer system as in claim 16 wherein said means for storing an associated state is a set of state registers, there being a one to one correspondence between the data registers of said set of data registers and the state registers of said set of state registers.
repeating, in response to determining that said particular set is subject to said exception condition, execution of the plurality of instructions of said particular set in a real state of the computer system, to process said exception condition.
19. The method as in claim 18 further including the steps of marking a first instruction, a last instruction, and a particular instruction of said set, said first instruction to activate said executing in said speculative state, said last instruction to activate said determining, and said particular instruction executing only in said real state of the computer system.
20. The method as in claim 18 further including the step of storing a memory address of a first instruction of said particular set, said memory address stored with said speculative data generated by said particular set, said memory address stored when said particular set is subject to said exception condition.
21. The method as in claim 18 further including the step of holding said exception condition when said particular set is executing in said speculative state, and processing said exception condition when said particular set is executing in said real state.
"A VLIW Architecture for a Trace Scheduling Compiler", Robert P. Colwell et al., Association for Computer Machinery, ACM 0-89791-238-1/87/1000-0180, pp. 180-192.
"Efficient Superscalar Performance Through Boosting", Michael D. Smith et al., ASPLOS V-Oct. 1992/MA, USA, 1992 ACM 0-89791-535-6/92/0010/0248, pp. 248-259.
"Sentinel Scheduling for VLIW and Superscalar Processors", Scott A. Mahlke et al., ASPLOS V-Oct. 1992/MA, USA 1992 ACM 0-89791-535-6/92/0010/0238, pp. 238-247.
"Software Support for Speculative Loads", Anne Rogers et al., ASPLOS V-Oct. 1992/MA, USA, 1992 ACM 0-89791-535-6/92/0010/0038, pp. 38-50.


text:
Charlie King
Author Musings
Satire Scribes
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This month, London Works' 'Temp of the Month' award goes to Kerry McKenna, newly appointed Client Services Manager at international law firm CMS.
Kerry was London Works' first temporary placement at CMS, starting her role in late August to cover the regular Client Services Manager who has many years' experience at the company. Her manager Danny Postill has been delighted with her performance, telling London Works that Kerry "settled in extremely quickly and now effectively leads a team of nine in a highly prestigious environment at our new building, Cannon Place". The whole team are thrilled to have her on board, as her approach and attitude have enabled her to fit in with ease and continue to ensure excellent service is provided to all clients, guests and staff.
CMS has been a great partner and supporter of London Works for over a year, and we are glad that their first temporary placement with us has been such a success. Kerry has taken on the role with such gusto and aplomb that CMS have since offered her a permanent contract, and she looks forward to continuing to provide her welcoming and professional service for the company.