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Justia Patents Electrical Pulse Counters, Pulse Dividers, Or Shift Registers: Circuits And Systems Patents Particular Transfer Means (e.g., Master-slave) Patents Including Logic Circuit Patents (Class 377/116)
Including Logic Circuit Patents (Class 377/116)
Field-effect device (e.g., jfet, igfet, mnos) (Class 377/117)
NVFF monotonic counter and method of implementing same
Patent number: 10419004
Abstract: A monotonic counter includes a plurality of stages respectively corresponding to a plurality of counting bits of the monotonic counter. At least one of the plurality of stages is a non-volatile flip-flop (NVFF) counter that includes a plurality of NVFFs, each NVFF including a pair of non-volatile memory cells.
Type: Grant
Filed: April 21, 2017
Date of Patent: September 17, 2019
Assignee: Windbond Electronics Corporation
Inventors: Seow Fong Lim, Chi-Shun Lin
Counter, counting method, ad converter, solid-state imaging device, and electronic device
Patent number: 9871986
Abstract: A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit.
Date of Patent: January 16, 2018
Assignee: SONY CORPORATION
Inventor: Yasuaki Hisamatsu
Method and apparatus for determining status element total with sequentially coupled counting status circuits
Abstract: Counting status circuits are electrically coupled to corresponding status elements. The status elements selectably store a bit status of a bit line coupled to a memory array. The bit status can indicate one of at least pass and fail. The counting status circuits are electrically coupled to each other in a sequential order. Control logic causes processing of the counting status circuits in the sequential order to determine a total of the memory elements that store the bit status. The total number of memory elements that store the bit status indicate the number of error bits or non-error bits, which can help determine whether there are too many errors to be fixed by error correction codes.
Filed: October 16, 2013
Assignee: MACRONIX INTERNATIONAL CO., LTD.
Inventors: Yih-Shan Yang, Shou-Nan Hung, Chun-Hsiung Hung, Yao-Jen Kuo, Meng-Fan Chang
Modulo-m binary counter
Abstract: An input value, where the input value is an amount which the current value of the counter is to be increased is received. The current value of the modulo binary counter and an offset value of the modulo binary counter are increased by the input value. Whether the current value of the counter is greater than or equal to the modulus value of the binary counter is determined. The current value of the counter is replaced with an updated offset value of the counter, where the updated offset value is the offset value of the counter increased by the input value. The updated offset value of the counter is returned.
Filed: January 30, 2015
Assignee: International Business Machines Corporation
Inventors: Steven R. Carlough, Adam B. Collura
Low power digital self-gated binary counter
Abstract: An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower-order counter sub-module. The control logic includes a clock-gating integrated cell arranged to clock gate at least one higher-order counter sub-module dependent on a logical combination of outputs of the lower-order counter sub-module and to provide a multi-cycle path for resolution of a logical combination of outputs of any subsequent cascaded counter sub-modules. The control logic does not include any intervening memory device between the lower-order counter sub-module and the clock-gating integrated cell for use in determining a later control logic output.
Filed: December 12, 2014
Date of Patent: September 6, 2016
Assignee: FREESCALE SEMICONDUCTOR, INC.
Inventors: Naman Gupta, Amol Agarwal, Gaurav Goyal
Filed: May 22, 2013
Date of Patent: May 26, 2015
COUNTER CIRCUIT AND IMAGE SENSOR INCLUDING THE SAME
Publication number: 20150124926
Abstract: An integrated circuit counter includes a cascaded chain of bit counters, which are collectively configured to count a number of first edges of a counter input signal received at an input thereof and output the count as a counter output signal. The cascaded chain includes at least two bit counters, which are: (i) configured to support both counter and buffer modes of operation, and (ii) responsive to respective bypass control bit signals having values that specify whether a corresponding one of the at least two bit counters is disposed in the counter or buffer mode of operation.
Type: Application
Filed: November 3, 2014
Publication date: May 7, 2015
Inventors: Won-Ho Choi, Jin-Woo Kim, Hyeok-Jong Lee
Multiple data rate counter, data converter including the same, and image sensor including the same
Abstract: A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.
Date of Patent: March 10, 2015
Assignee: Samsung Electronics Co., Ltd.
Inventors: Kyung-Min Kim, Kyoung-Min Koh, Yoon-Seok Han
Counter circuit and protection circuit
Abstract: A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode.
Filed: November 24, 2009
Date of Patent: July 30, 2013
Assignee: Mitsumi Electric Co., Ltd.
Inventor: Takashi Takeda
Double data rate (DDR) counter, analog-to-digital converter (ADC) using the same, CMOS image sensor using the same and methods in DDR counter, ADC and CMOS image sensor
Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.
Filed: December 7, 2009
Inventors: Yong Lim, Kyoung-Min Koh, Kyung-Min Kim
Device for counting oscillations of an oscillating temporal signal
Abstract: A device for counting oscillations of an oscillating temporal signal. The device comprises means for counting all the alternate crossings of a positive threshold value and of a negative threshold value by a monitored time signal.
Filed: June 15, 2009
Date of Patent: June 19, 2012
Assignee: Airbus Operations SAS
Inventors: Philippe Goupil, Pascal Traverse
Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The first stage includes a first clock input and is edge-triggered on one of the rising and falling edges of a signal applied at the first clock input. The counter includes at least one second stage for generating another bit of the value in the counter. The second stage includes a second clock input and is edge-triggered on the other of the rising and falling edges of a signal applied at the second clock input.
Date of Patent: August 2, 2011
Counter array and image sensor including the same
Abstract: A counter array and an image sensor including the same may be provided. The counter array may include a controller and a plurality of counter units. The controller may output an operation control signal and a direction indication signal. The counter units hold previous output values or may perform a counting operation in response to the operation control signal and may perform an up-count operation or a down-count operation in response to the direction indication signal when performing the counting operation.
Inventors: Kyoung Min Koh, Kyung-Min Kim, Yong Lim
Reconfigurable address generation circuit for image processing, and reconfigurable LSI comprising the same
Abstract: A reconfigurable address generation circuit for image processing is configured to an arbitrary state based on configuration data generates a read address for reading out image data of pixel units having a plurality of rows and columns from a memory which stores image data. As the configuration data, there are set a X, Y count end value of the read out pixel unit, a width value of the image in the memory, and edge information for clip processing. The address generation circuit has X counter; Y counter; an X, Y clip processing circuits which convert the count value of the X, Y counter according to the left, right top and bottom edge information; and an address calcuration circuit which generates the reading out address, based on the count values from the X and Y clip processing circuits and the width value.
Filed: February 3, 2006
Date of Patent: April 7, 2009
Assignee: Fujitsu Microelectronics Limited
Inventor: Tetsuo Kawano
On-chip storage of hardware events for debugging
Abstract: An integrated circuit (IC) die includes a plurality of edge counters. Each edge counter is provided to detect at least one change in signal level at a respective location on the IC die. The IC die is in communication with a memory and also includes an event recording circuit on the IC die provided to store states of the counters in the memory.
Inventors: Pat Brouillette, Jason G. Sandri
High speed binary counter
Abstract: A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.
Date of Patent: December 5, 2006
Inventor: James M. Lewis
High-speed synchronous counters with reduced logic complexity
Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.
Date of Patent: February 21, 2006
Assignee: Xilinx, Inc.
Inventor: Ahmed Younis
Date of Patent: November 1, 2005
State machine, counter and related method for gating redundant triggering clocks according to initial state
Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.
Date of Patent: August 30, 2005
Assignee: VIA Technologies Inc.
Inventors: Yung-Huei Chen, Shan-Ting Hong
Monotonic up-counter in an integrated circuit
Abstract: An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1?(n+2) irreversible counting cells distributed in at least n groups of 2p?1 counting cells, where p designates the group rank, and at least n?1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.
Date of Patent: April 19, 2005
Assignee: STMicroelectronics S.A.
Inventors: Luc Wuidart, Claude Anguille
Programmable counter with half-integral steps
Abstract: This invention provides a circuit and a method for programmable counters. It consists of a circuit and a method for unique programmable counters that provide half-integral as well as integral steps, such as 1.5, 2, 2.5, 3, 3.5, 4. This circuit and method are the first implementations of providing programmable counting with half-integral steps. The circuit and method of this invention can be extended via the cascading of toggle flip flops at the front end of the circuit of this invention. This provides the ability to enhance the speed of normal integral step counting applications. In addition, the cascading of the multiple copies of the circuit of this invention provides the ability to provide other fractional programmable counters. A key advantage of this invention is that the method of this invention is general enough to use any other type of counter sub-component beside the binary counter sub-component of this invention.
Filed: March 31, 2003
Date of Patent: January 4, 2005
Assignee: Agency for Science, Technology and Research
Inventors: Chun Geik Tan, Uday Dasgupta
Counter having improved counting speed
Abstract: A counter having enhanced counting speed is provided. The counter includes first through N-th output signal generators. The first output signal generator responds to a clock signal and outputs a first output signal in which a low level and a high level are repeated once per cycle of the clock signal. The second output signal generator responds to the clock signal and the first output signal and outputs a second output signal in which a low level and a high level are repeated every two cycles of the clock signal. The third output signal generator responds to the clock signal and the second output signal and outputs a third output signal in which a low level and a high level are repeated every four cycles of the clock signal. The N-th output signal generator responds to the clock signal and the N−1th output signal and outputs an N-th output signal in which a low level and a high level are repeated every 2N−1 (where N is a natural number greater than 1) cycles of the clock signal.
Inventor: Ki-Mo Joo
Counter circuit for detecting erroneous operation and recovering to normal operation by itself
Abstract: A counter circuit includes a plurality of flip flop circuits (FF circuits) sequentially connected for receiving a common clock signal, and two-input logic gates each having an input connected to an output of a corresponding FF circuit and the other input connected to an output of a common FF circuit, and of which output signal is supplied to an FF circuit positioned at the post stage of the corresponding FF circuit. A booby trap is realized by the two-input logic gates. The value input to each of the FF circuits is determined by logical operation of at most two logical values, so that the counter circuit can be adapted to the increasing frequency of a clock signal CLK. Thus, the counter circuit with the booby trap, capable of performing high-speed operation can be provided.
Assignee: Mitsubishi Denki Kabushiki Kaisha
Inventor: Masahiko Ishiwaki
Multiple-output counters for analog-to-digital and digital-to-analog conversion
Abstract: A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.
Inventor: Charles Douglas Murphy
Abstract: A synchronous counter includes at least three or more flip-flops having a chain structure, and at least two or more 2-input EXOR gates interposed in the chain structure. The number of stages of gates interposed between the output of one among the flip-flops and the input of another is one stage of a 2-input EXOR gate even in a critical path thereby shortening the critical path.
Filed: January 9, 2001
Inventors: Masami Nakajima, Hiroyuki Kondo
Fully programmable multimodulus prescaler
Abstract: The present invention is a method and system for a fully programmable modulus pre-scaler. In one embodiment, the pre-scaler is a cascade of fully programmable divide-by-⅔ sections. A fully programmable divide-by-⅔ section includes a state machine and a control circuit. The state machine generates a modulus control output synchronously with a clock signal in response to a modulus control input and a programming signal. The state machine has a plurality of states corresponding to a ⅔ divider. The control circuit is coupled to the state machine to generate the programming signal to the state machine in response to a programming word for a frequency divider.
Filed: June 7, 2001
Date of Patent: December 31, 2002
Assignee: Maxim Integrated Products, Inc.
Inventors: Konstantin Kouznetsov, Daniel Linebarger
Extended length counter chains in FPGA logic
Abstract: A synchronous counter, the inventive counter is synchronized to a clock, e.g., a master clock of an FPGA, and includes a first counter that increments in response to the master clock, a resynchronizer that receives counter bits from the first counter and, when appropriate, generates an increment signal, and a second counter, clocked by the master clock, that increments in response to the increment signal. In a preferred embodiment, the resynchronizer is an n bit AND gate (where the first counter is an n-bit counter) that ANDs at least selected ones of the counter bits and a latch, e.g., a flip-flop, that latches the output of the AND gate. Thus, small counter chains are linked together using flip-flops clocked at the master clock rate, i.e., the same rate as the counter chains, to form a counter chain of any length that will function at the master clock rate.
Filed: October 8, 2001
Date of Patent: October 22, 2002
Assignee: Raytheon Company
Inventor: Michael K. Carpenter
Low power counters
Abstract: A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks include memory devices consuming a minimum of power when they are disabled and activated only when the value of the respective data output connection has to be changed.
Assignee: Telefonaktiebolaget LM Ericsson (publ)
Inventor: Mattias Hansson
Counter circuit
Abstract: Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).
Filed: September 2, 1998
Inventors: Toru Nakura, Kimio Ueda
Fast synchronous counter
Abstract: A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synchronization circuit and each includes circuitry for receiving a pulse train clock signal, synchronously counting said clock signal and outputting an output bit signal corresponding to said counters' stage bit position. The bit counting stages are arranged in two groups, a reset group and a counting group, such that the output bit signal of said flip-flop circuit of the reset group synchronizes data propagation between each bit counting stage of the counting group.
Assignee: STMicroelectronics, Inc.
Inventor: William C. Rogers
Address counter test mode for memory device
Abstract: A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit. The logic circuit may be configured to generate one or more control signals in response to one or more control inputs. The counter circuit may be configured to generate a first counter output and a second counter output in response to (i) the control outputs and (ii) one or more inputs. The counter may comprise a first portion configured to generate the first counter output and a second portion configured to generate the second counter output.
Assignee: Cypress Semiconductor Corp.
Inventors: George M. Ansel, David R. Lindley, Jeffrey W. Gossett, Junfei Fan, Andrew L. Hawkins, Michael D. Carlson
High-speed binary synchronous counter
Abstract: An integrated circuit includes an n-bit counter having a plurality of k subcounters where both n and k are integers. At least one of the subcounters includes a switchable device adapted to receive a carry-out signal from an adjacent subcounter as a first input, a test carry signal as a second input, and a control input, the switchable device being capable of providing one of its inputs as an output, the control input capable of controlling selection of the output which is a carry signal. The subcounter also includes an n/k-bit counter, the n/k-bit counter receiving the carry signal and providing n/k output bits, and logic for combining the n/k-bits output from the n/k bit counter with the carry-out signal from an adjacent subcounter to provide an output that is a carry-out signal from the subcounter. The logic introducing a single gate delay between the carry-out signal from the adjacent subcounter and the carry-out signal from the subcounter.
Filed: July 30, 1997
Assignee: Lucent Technolgies Inc.
Inventors: Ravi Kumar Kolagotla, Santosh K. Misra, Jiancheng Mo, Hosahalli R. Srinivas
Low power programmable ripple counter
Abstract: A ripple counter becomes programmable by use of intervening circuitry selectively inhibiting state transitions according to an initial programming step. The illustrated embodiment of a programmable ripple counter includes a forward chain of count registers operating generally in the fashion of a ripple counter, but selectively inhibited by an intervening control signal originating from a reverse chain of control registers. By selectively controlling the number of state transitions inhibited and by selectively controlling the number of registers participating in the counting operation, a low power general purpose programmable ripple counter results.
Assignee: Seiko Communications Systems Inc.
Inventor: Jeffrey R. Owen
Low power scannable counter
Abstract: A low power scannable asynchronous counter which is fully testable and which consumes low power in a functional mode consists of counter cells cascaded through NOR gate circuits to which clock signals are applied for each of the stages or cells. Each of the stages or cells comprises a flip-flop and a multiplexer which together operate as a toggle flip-flop only when all of the previous flip-flops are set. The result is that the flip-flop clock is forced high preventing any transition of the flip-flop internal clock tree for all stages or cells where the output is low. Thus, no power consumption of such stages takes place during functional operation. In the scan test mode, the counter operates as a shift register and it is fully testable.
Assignee: VLSI Technology, Inc.
Inventors: Jerome Bombal, Laurent Souef
High-speed binary synchronous counter with precomputation of carry-independent terms
Abstract: An N-bit binary synchronous counter includes K counter stages, with each stage including N/K flip-flops or other suitable storage elements. A given one of the counter stages receives a carry-in signal generated by another counter stage or by a carry logic circuit. The given counter stage includes a selection circuit for selecting one of two precomputed values for application to an input of a storage element in that stage based on a value of the carry-in signal. The selection circuit may include a two-input multiplexer for each of the N/K storage elements of the given counter stage. The jth multiplexer includes a first input coupled to an output of the jth storage element, and a second input coupled to an output of a logic circuit. The logic circuit generates a logic function based on the output of the jth storage element and other lower significant storage elements in the stage.
Assignee: Lucent Technologies Inc.
High-speed synchronous counter circuitry
Abstract: Digital counter register stages are constructed as two-to-one mux registers, each employing a multiplexer stage having first, second, and third inputs and an output connected to the switching signal input of a D-type flip-flop, whose Q output comprises a first input to the multiplexer stage. An inverter buffer is associated with each register stage and has an input connected to the output of said D-type flip-flop and an output connected to the second input of the multiplexer stage and fed forward to a NOR gate associated with each subsequent register stage. The output of the NOR gate comprises the third input to the multiplexer stage of the associated register stage.
Assignee: Hughes Electronics
Inventors: Gregson D. Chinn, Dwight N. Oda
High-speed counter circuit
Abstract: A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit responsive to an output signal from at least one higher-order bit counter of the at least two bit counters, for transferring the clock signal from the input line to a lower-order bit counter of the at least two bit counters, and a delay circuit for delaying the clock signal from the input line by a propagation delay time of the at least one clock synchronizing circuit and applying the delayed clock signal to a highest-order bit counter of the at least two bit counters. According to the present invention, the high-speed counter circuit can minimize a delay time from the application of the clock signal to the generation of the count value to enhance the operation speed.
Date of Patent: October 6, 1998
Assignee: Hyundai Electronics Industries Co., Ltd.
Inventor: Jong Hoon Oh
High-speed predecoding address counter circuit
Abstract: A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at le
Inventor: Kee Woo Park
Fast programmable divider
Abstract: This invention relates to a programmable frequency divider that includes a plurality of flip-flops that are clocked at a frequency to be divided. The plurality of flip-flops is operatively arranged to allow the connection in a ring of a predetermined number of them, selected according to a desired frequency division ratio. In one embodiment, the smallest selectable ring includes at least two successive flip-flops that are initialized to a first state, immediately followed by at least two successive flip-flops that are initialized to the opposite state.
Assignee: SGS-Thomson Microelectronics S.A.
Inventor: Osvaldo Colavin
Counter circuit having load function
Abstract: A counter circuit having a load function which is able to speedily yet stably perform counting operations no matter what kind of value has been loaded. The counter circuit having a load function performs counting operations in synchronization with an input clock signal and is able to count from an arbitrary value upon receiving a count initiation value in synchronization with a load signal. The principal composing elements are: at least three counter circuits 1-1.about.
Filed: September 19, 1995
Date of Patent: February 4, 1997
Assignee: Ando Electric Co., Ltd.
Inventor: Keiji Negi
Binary counter with sped-up ripple carry
Abstract: A binary counter or binary-coded-arithmetic counter uses local look-ahead to speed up ripple carry propagation. A succession of counter stages therein can be identified by respective consecutive ordinal numbers assigned in accordance with the order of carry propagation. Each counter stage receives a respective carry input and supplies a respective output signal, and each counter stage identified by even number supplies a respective complemented output signal. Each counter stage identified by odd number has a respective carry generation circuit for supplying a respective carry output signal which includes a NAND gate responsive to carry input to that counter stage and responsive to output signal from that counter stage, carry input for the next counter stage being supplied in response to the NAND gate response.
Inventor: Si-Yeol Lee
Abstract: A synchronous counter comprises one D flip-flop circuit for performing divide-by-2 frequency division of a clock signal CK, JK flip-flop circuits for, when input signals have HIGH levels (logical value 1), inverting the levels of the output signals in synchronization with the clock signal CK, logic circuits for inputting control signals to the JK flip-flop circuits, lower-stage signal assembling circuits for grouping the output signals from the JK flip-flop circuits into two-signal-unit groups to produce logical product signals of the signals in these two,signal-unit groups, and upper-stage signal assembling circuits for further handling the output signals from the lower-stage signal assembling circuits, thereby firstly simultaneously satisfying an increase in speed of the counting operation as well as simplification of the wiring pattern and reduction in the circuit area and secondly realizing further increase in the counting operation.
Assignee: Nippondenso Co., Ltd.
Inventors: Mitsuaki Kondo, Takamoto Watanabe
Abstract: A frequency divider, constituted by N divide-by-two binaries, comprises logic circuits that enable the generation of a signal of the end of the frequency division by means of the change in state of the most significant bit generated by the Nth order divide-by-two binary. A binary code C representing a decimal integer value V is applied to the divider circuit. The frequency divider comprises circuits that enable the performance of a variable order division (V+1, V, . . . V-p, where p is a whole number greater than or equal to 1 and smaller than N-1) for one and the same binary code C.
Date of Patent: November 21, 1995
Assignee: Thomson-CSF Semiconducteurs Specifiques
Inventor: Richard Ferrant
Data coincidence detecting circuit
Abstract: A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.
Inventors: Sung-il Cho, Ki-ho Shin
Synchronous counter circuit having a plurality of cascade-connected counters
Abstract: A synchronous counter circuit comprises first and second counting circuits and a latch circuit. Each of the first and second counting circuits includes a clock terminal for receiving a clock signal, an enable terminal for receiving an enable signal, a counter coupled to the clock terminal for counting pulses of the clock signal, a carry signal generating circuit coupled to the counter for generating a carry signal in response to a finish of the counting of the counter, and a ripple carry signal generating circuit coupled to the clock terminal and the carry signal generating circuit for generating a ripple carry signal in response to the clock signal and the carry signal.
Assignee: Oki Electric Industry Co., Ltd.
Inventor: Harumi Kawano
Counter circuit with or gates interconnecting stages to provide alternate testing of odd and even stages during test mode
Abstract: A counter circuit includes a plurality of one-bit counters connected in series. The counter circuit includes first and second input terminals which are supplied with a predetermined signal, respectively, in an operational test mode. The counter circuit further includes a unit for alternately supplying a carry signal to a carry signal input of each one-bit counter in series when the predetermined signals are applied thereto. The unit may be composed of a plurality of OR circuits. Each OR circuit is provided with one input connected to the carry signal output of a one-bit counter at the preceding stage of the series, the other input connected to either the first input terminal or the second input terminal, and an output connected to the one-bit counter at the next stage.
Assignee: Sharp Kabushiki Kaisha
Inventor: Yoshinori Hashimoto
Function adjustable signal processing device
Abstract: A signal processing device is provided with a plurality of signal processing circuits which are integrated on a monolithic semiconductor chip and which execute a plurality of predetermined signal processing stages. Signal input terminals are connected with predetermined one of the signal processing circuits for receiving input signals necessary for the plurality of signal processing stages. A first signal output circuit outputs the final signal processing result while a second signal output circuit outputs the intermediate processing results obtained from the signal processing circuits other than a signal processing circuit which performs the final stage signal processing. A plurality of selection circuits are respectively located on each of signal transfer paths for transferring the intermediate signal processing result to a succeeding signal processing circuit.
Filed: April 9, 1992
Assignee: Hitachi, Ltd.
Inventors: Nobukazu Doi, Tohru Setoyama
Timer input control circuit and counter control circuit
Abstract: A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal and system clock and the logical multiplication between the signal and counter write signal to the direct reset input of a transparent latch 7 and for realizing read-on-the-fly or write-on-the-fly operation even if timer input does not synchronize with the system clock.
Inventors: Shohei Moriwaki, Shinichi Hirose
Counter for an image pickup system
Abstract: The horizontal synchronous signal and the vertical synchronous signal included in a composite synchronous signal which is output from one TV camera are separated from the composite synchronous signal. A plurality of TV cameras are controlled on the basis of the horizontal synchronous signal and the vertical synchronous signal so as to produce synchronized video signals from the plurality of TV cameras. These synchronized video signals are easy to compound. In the blanking period of the vertical synchronous signal, the rise period of the synchronous signal is 1/2 of the period of the vertical synchronous signal. Pulses are eliminated alternately in the blanking period by a half killer circuit including a counter and a decoder and having a simple structure, thereby generating a horizontal synchronous signal appropriate for driving the TV cameras.
Date of Patent: July 6, 1993
Assignee: Sanyo Electric Co., Ltd.
Inventor: Yoshihito Higashitsutsumi


HTC seems to have ditched cheap phones as it has launched a mid-ranger Android device yet again. Yes, that's right! The company's latest mobile is One A9. Many people are desperately waiting for the Taiwanese tech giant to launch its alternative to Moto G3, K3 Note, etc but HTC seems to be in no mood to do so.
Samsung is struggling in India and China but it has not yet given up. It is still launching Android as well as Tizen OS based budget phones for the Indian masses. A week ago, the company claimed that Tizen is the 2nd most used mobile operating systems in India after Android. HTC should learn from Samsung.
Anyways, HTC has announced that latest Android OS update will be available for the A9 within 15 days from the day Google launches it.
HTC One A9 uses Snapdragon 617 64 bit processor which delivers slightly better 4G LTE performance than the 615 chipset. If you go through this official SoC comparison page on Qualcomm's website, you'll notice that the 617 chip supports global mode LTE connections and cat 7 technology that promises download speeds of up to 300 MBPS. It is compatible with screens having 1920 x 1080 pixel resolution. Snapdragon 616 supports 2K displays.
Anyways, the SoC of One A9 is paired with Adreno 405 chip and it has 64 bits architecture for superior performance.
HTC One A9 features Android Marshmallow OS (version 6.0). It supports playback of 1080p videos at 60 FPS.
It includes 3G RAM. It is the first mid-range phone from HTC to feature 2+ gigabyte system memory. This Android 6 phone has Amoled FHD 5 inch display. Its screen is covered with Gorilla glass 4 protection.
Battery backup offered by A9 seems to be ordinary because the task to power the octa-core processor and 3GB RAM is assigned to a 2150 mAh capacity battery.
The cameras are powerful too. As seen in many other HTC phones within 25000 range, One A9 features a pair of 13 MP back and 2+ MP front sensors to handle user's photography/selfie craze.
The back sensor is coupled with a dual LED 2 tone flash system. It includes support for optical image stabilization, PDAF, raw imaging, etc. The front side of A9 boasts 4 ultra pixel FHD sensor.
Along with Marshmallow OS, HTC has installed its own UI system in this handset.
HTC One A9 is incorporated with 6 sensors (including fingerprint module). It is light weight phone with 7.3 mm thickness. If you're in the US, you can this phone in an unlocked condition on HTC's online shop for 400 dollars i.e around 24000 Rupees. Supported carriers are AT & T, T-mobile, and sprint.
HTC One A9 will retail in India for the same price tag. It is likely to be sold via Amazon, Flipkart or Snapdeal.


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A Long Time Coming: Roots of the Milwaukee Uprising
from the Milwaukee Branch of Solidarity
The outpouring of grief and anger following the August 13 police killing during a traffic stop of Sylville Smith, a 23 year old Black man who became the latest victim of police related violence in the city of Milwaukee, can only be understood against the backdrop of systematic police violence, oppression, discrimination, and poverty. Milwaukee is the most segregated city in the country and the worst place for Black people as seen in virtually every social index from unemployment rates, multiple educational measures, and official poverty levels to rates of infant mortality and mass incarceration.
National news outlets widely reported the burning of several businesses in the Sherman Park neighborhood in Milwaukee's mostly Black North side where Sylville was killed. Less publicized were the peaceful marches led by the Coalition for Justice, Milwaukee's local organization in the Movement for Black Lives, founded by members of the family of Dontre Hamilton, an unarmed Black man shot fourteen times on April 30, 2014 by a Milwaukee police officer who was never charged for the killing.
The Family of Sylville Smith gathered in the area he was shot and killed. Photo © AP
Friction between law enforcement and the community members has been enormous and growing for decades here. "It's been a long time coming" was a feeling expressed by many protestors and neighborhood residents as the protests erupted. True to form, Governor Walker and reactionary law-and-order Milwaukee county Sheriff David Clarke responded to the uprising by mobilizing the National Guard, ramping up the tensions that led to a second night of confrontations between protestors and police.
The police and National Guard behaved as an occupying force. A closed Walmart was turned into an improvised detainment center and the parking area around the Midtowne Mall used as a staging area for police. A stream of MRAPs, BearCats, Humvees, and other police vehicles crept through the city throughout the uprising. An orange construction fence was quickly erected around Sherman Park and the sidewalk surrounding it, making it impossible for local residents, particularly the disabled, to safely move about. A curfew targeting adolescents was enforced.
Milwaukee's leading public officials deflected all criticism and instead blamed the victim and much of the community itself for the violence. Much was made of the fact that Sylville was armed, although there was no claim he had used or threatened to use his gun. This points to the hypocrisy of the local big business press, because Sylville had a Concealed Carry Permit to possess the gun, a "right" that pro-gun lobby enthusiasts like Walker and Clarke hold extremely dear.
Even before Sylville's funeral Walker responded to the pressure generated by the protests and the national news reports about the desperate conditions in the city, rushing in with a plan to devote $4.5 million dollars to job training programs in the neighborhoods where the uprising took place. This is barely a drop in the bucket of what is needed to truly address the unemployment and other social issues facing the people of the north side.
Wrong Directions
For its part the Milwaukee City Common Council called for more police, longer sentences, boot camps for juveniles, and other repressive measures. Sheriff Clarke demanded funding for four hundred more cops. These plans go in exactly the wrong direction. They will do nothing to address the needs of the city's Black and other people of color.
In fact, the calls for harsher police measures against a community that has suffered police violence, daily racial profiling, and astronomical levels of incarceration would markedly worsen life for Black Milwaukeeans. The Common Council Plan is silent regarding measures to address the desperate conditions facing working people of color in the city.
A protestor holds a sign saying, "For black people there is no justice in Milwaukee Wisconsin."
The unemployment rate for Black people in Milwaukee is fifty percent. Black children in Wisconsin are six times more likely than white children to live in poverty–the highest disparity ratio in the country. Milwaukee's crumbling public school system, in desperate need of more funding, works particularly poorly for Black students. The state of Wisconsin as a whole has the country's largest achievement gap between Black and white students, and ranks last in reading comprehension tests among Black fourth-graders.
Walker and the Republican dominated state legislature, along with the Milwaukee City Council and Democratic Mayor Tom Barrett clearly have other priorities than solving these problems. Since Mayor Barrett took office in 2004, expenditures on police has risen by 54%. The Wisconsin state budget now allots more funding for incarceration than it does for higher education. Wisconsin also uses a higher rate than the national average of private prisons, which have a well-documented record of being even more abusive than state and city owned jails and prisons.
In Wisconsin one in eight Black men have been incarcerated, while white males are incarcerated at a rate of one in eighty-one. In the 53206 Zip Code alone, which represents much of Milwaukee's impoverished Black north side, a full 62 percent of all men have spent time in an adult correctional facility by age 34.
The Need for Independent Politics
Police violence against Black men, underfunded schools, lack of job opportunities, and mass incarceration are various fronts in a war that Democratic and Republican politicians in service to the 1% are waging against working people in general and Black and Brown people in particular. The killing of Sylville Smith and the protests in response are the latest skirmishes in that war.
While the response of state and local Democratic and Republican politicians to the uprising has been greater doses of the same policies that make life miserable for people of color and working people in general, Green party Presidential candidate Jill Stein calls for a Green New Deal that would guarantee work at livable wages for all, the end of mass incarceration and institutional racism, and Medicare for all.
Supporting independent candidates with such a program, along with the peaceful protests that the Coalition for Justice continues to organize, are the best ways to confront racist police violence and to begin to solve the problems exposed by the Milwaukee Uprising.
SofiaDarn says:
Thank you for the article ! Friction between law enforcement and the community members is a real problem, we must live together in peace and respect…
laser-puissant.xyz

redpajama_set_name: RedPajamaCommonCrawl


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Breaking • Deptford • Dover • Kent • LONDON
Two men have been given life sentences for the murder of a well-known drill rapper who was stabbed to death in Deptford in December 2019
Elijah Morgan, 20 of no fixed address and Jedaiah Param, 21 of Norwood High Street, West Norwood, were found guilty on Friday, 12 March following a trial at the Old Bailey.
They were both sentenced at the same court on Monday, 19 April to a minimum of 28 years in jail.
The court heard Morgan and Param were part of a gang of four young men armed with knives who chased and then fatally stabbed 20-year-old Crosslon Davis in an alleyway in Deptford.
Analysis of mobile phone records showed that Crosslon arrived at Deptford Creek with a friend in the early hours of 6 December 2019.
Cell site data of mobile phones belonging to Morgan and Param showed they had arrived in the same area slightly earlier.
The pair were identified by homicide detectives from the Met's Specialist Crime Command through CCTV from a minicab that was called to pick them up at the scene.
The violent attack started after Morgan and Param got into the minicab and Crosslon attacked Morgan with a mallet.
The minicab drove away from the scene a short distance before the driver was told to stop and Morgan and Param got out and started chasing Crosslon.
CCTV footage from Ha'penny Hatch showed that Crosslon was pursued by the pair, as well as two other unidentified males, who were all armed with knives or machetes.
All four of them stabbed Crosslon, who collapsed to the ground. Crosslon's friend had tried to place himself between him and the attackers, but he was overpowered.
A number of local residents provided statements describing how they had seen the group running after Crosslon.
Police and paramedics were called to the scene. Despite their efforts, Crosslon died a short time later due to the loss of blood from at least nine stab wounds, including one that penetrated his lung and heart.
Crosslon's friend called 999 and initially stayed with him until the emergency services arrived. However, he gave a false name to officers at the scene and declined to give a witness statement, or help with the police investigation in any way.
Morgan was identified after a police officer recognised him from the minicab CCTV footage. He was arrested at an address in Birmingham on 2 January.
Param, who was also identified via the minicab CCTV, was arrested at Dover Eastern Docks after he was found hiding underneath a coat in the back of a car as it went through passport control.
Both men declined to comment in police interviews and subsequently pleaded not guilty to murder.
Morgan's defence during the trial was that he was wrongly identified.
Detective Chief Inspector Richard Vandenbergh, the lead investigator, said: "This was a savage and merciless attack. Crosslon was clearly running way from his attackers, who set upon him armed with large knives.
"The number of stab wounds sustained by Crosslon demonstrates the murderous intent of the four people who hunted him down.
"I think it is right that Elijah Morgan and Jedaiah Param have received lengthy jail sentences for their part in the attack. I am also pleased that we have some justice for Crosslon's family, who have conducted themselves with the greatest of dignity throughout the court process
"We know there are still two other people who took part in this attack, who have not yet been identified, and we are still determined to find them. I urge anyone who knows where they are to contact police immediately."
In her victim impact statement, Crosslon's mother Vivienne said: "My life was all about Crosslon. He was reason for leaving my house, the reason I cook every day, he is the first thing on my mind when I wake and the last thing on my mind at night. We had lots of laughs through good and bad and he was also my friend.
"We still can't believe this is happening. Crosslon's life was tragically cut short, and I am still numb and paralysed, plagued by grief and pain. They have ripped out my heart. We are haunted by what happened to Cross.
"Crosslon was easy to love, so polite and always respectful. He was popular amongst his friends, fun compassionate and loyal. He will be greatly missed by them all as they also continue to grieve their loss."
Burglar sentenced to 18 months in prison as part of Operation Crooked
Following a Warwickshire Police investigation, an 18-year-old man has been sentenced to prison for drugs offences in Leamington


text:
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redpajama_set_name: RedPajamaGithub


Does Mouthwash Kill Good Bacteria?
Many conventional mouthwashes hurt your oral flora and can actually make your breath worse.
Bad breath is a sign that your mouths oral microbiome is off balance. And when your oral microbiome is off balance, there's a good chance your gut microbiome is also off balance because they directly influence one another. There are many causes of bad breath, but a common one begins in your gut, or "gut breath" as I like to call it.
Many people think the best way to combat bad breath and improve oral hygiene is through using strong, sanitizing mouthwashes. They opt for powerful, astringent mouthwashes that zap their mouth's bacteria hoping it will leave them with fresh, minty breath.
But that's not how your mouth works.
Your mouth is actually a fine balance of microbes working together with your gut microbes and immune system to keep you healthy.
Imagine your mouth as a pleasant little coral reef with different corals, anemones, and other critters. These make up an ecosystem and each critter needs the other creatures to live and thrive. Even a little competition among species is fine because it keeps everything in balance. This comparison may seem like a silly metaphor, but it's far more accurate than viewing your mouth as simply teeth, gums, and a tongue. Your mouth is much more than that.
Symbiotic relationships abound in your mouth's "ecosystem" and collectively this is known as your oral microbiome. Your mouth contains about 500 to 1,000 different types of bacteria, enzymes that aid in digestion, proteins which provide nutrients for the helpful bacteria, and more.
To keep your mouth healthy, which keeps your body healthy, you need to think of your mouth as a living thing. So, when you see mouthwashes that claims to "kill 99% of germs" run far, far away.
If you're struggling with your oral health, don't reach for Crest, Colgate or Listerine mouthwash – instead, look to improve your microbiome balance in your mouth and gut.
The oral and gut microbiome require a delicate balancing act of the right bacteria to ensure your immune system stays strong and you stay healthy. In fact, bad breath is a symptom of a system that's out of balance.
The health of your mouth reflects the health of the rest of your body. The bacteria that causes bad breath is usually produced by gram negative bacteria which reproduces readily in an anaerobic environment or when there' a lack of oxygen.
These anaerobic bacteria like to burrow into your gums, which breaks down tissue and causes your gums to bleed. Anaerobic bacteria need iron to thrive and fortunately for them, blood contains a lot of iron.
This becomes a vicious cycle and can eventually lead to tooth loss.
Preventing bad bacteria from overgrowing while supporting the helpful bacteria, is how you maintain a healthy oral microbiome and prevent bad breath. So, if you choose a strong, conventional mouthwash you're not just killing the harmful bacteria in your mouth, you're killing the good guys too.
The problem mouthwash ingredients is that we don't really know what they do to our oral microbiome. In fact, it's likely that someone desperately trying to eliminate bad breath may make matters worse when they opt for a mouthwash.
There are a number of common ingredients that throw the mouth's microbiome off balance, leaving you with worse breath, that may cause gut imbalance.
Here are some of the most common ingredients in mouthwash you should stay away from and why.
Alcohol – Alcohol is antimicrobial and doesn't distinguish between the good and bad bacteria. Meaning an alcohol-based mouthwash just kills off your microbiome diversity and can even make your breath worse.
Hydrogen peroxide – Hydrogen peroxide is a cleaning product that's ended up in a lot of mouthwash. Similar to alcohol, it kills off both good and bad bacteria and leads to microbiome imbalance. Hydrogen peroxide can also kill the cells inside your teeth and should be avoided.
Chlorhexidine – A third, broad-spectrum antimicrobial chemical that's commonly found in mouthwash. In addition to its unknown impact on your microbiome, it has other negative side effects – it stains teeth, increases calculus formation, and alters taste perception.
These are the most common AND most harmful ingredients in mouthwashes. How have we gone so far off track creating helpful mouthwash? In order to improve you overall microbiome health, you should consider any mouthwash containing any of these ingredients. There are ways to work on improving your microbiome health instead.
Improves bad breath – There have been numerous studies which reveal how probiotics can improve bad breath. One study found that L. salivarius improved bad breath in as little as two weeks.
Prevents plaque build up – A study found that encouraging the growth of beneficial oral bacteria, A12, helped prevent plaque buildup caused by S. mutans. This study revealed how beneficial bacteria is needed to keep plaque-causing bacteria in check.
Reduces gingivitis – Researchers have found that probiotic L. reuteri was effective in reducing gingivitis and bleeding gums.
Decreases gum disease inflammation – Probiotics are known for their anti-inflammatory effects and the mouth is no exception. A study found that the probiotic L. brevis was effective in reducing inflammation in the mouth caused by gum disease.
Only once you address your oral and gut health in its entirety can you permanently rid yourself of chronic bad breath and improve your dental health completely. Probiotics are a great step in the right direction, it's even better if you can add important nutrients as well.
Coconut Pulling – Coconut pulling is an ancient technique used to gently and effectively clean the mouth. This Rare Body coconut pulling blend also contains sea salt with a high mineral content which can help remineralize your teeth. You can read more about coconut pulling here.
Oral Essentials – This mouthwash contains sea salt, aloe vera, and holy basil oil, all of which are gentle on the oral microbiome and teeth.
Homemade Mouthwash – You can make a very simple homemade mouthwash by mixing a ½ tablespoon of baking soda with water and adding a pinch of sea salt. These ingredients will help with remineralization in addition to freshening your breath.
If you struggle with persistent bad breath, you should make an appointment with your dentist. There's a series of tests they can perform and steps you can take to identify the root cause of your issue.
Also, check out my article on the 14 ways to naturally freshen your breath. It's packed with nutrition advice that will freshen your breath from the inside out.
Do you experience bad breath? Share your experience with mouthwash in the comments.
Thanks for your excellent observations and advice.
I'd like to know if oral probiotics can affect the gut biome, (for better or worse) after long-term use. I would assume that they wouldn't get past the stomach, but I just don't know.
I love the meaning of the article. I've always wondered about mouth flora since we know about gut flora and the relationship between it and our immune system. However, I unbiasedly want to point out there are are a lot of errors that make it somewhat confusing and almost informal to the reader. I hate seeing this because it can cause one to feel like an article has lost credibility.
Your comparisons and examples were spot on though. Thank you for this informative article!


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Filter Sector - All Finance Healthcare Hospitality Industrial Legal Multifamily Net Lease Office Retail Seniors Housing Student Housing
Filter Market - All Illinois Indiana Iowa Kansas Kentucky Michigan Minnesota Missouri Nebraska Ohio N Dakota S Dakota Tennessee Wisconsin
Exact phrase Any word All words Any word or synonyms
More than 200 results for "spaces real estate"
Multifamily N Illinois
Five winter don'ts for multifamily property managers
January 16, 2020 | Jack Devedjian
From frigid temperatures and piles of snow to burst pipes and icy sidewalks, danger can lurk around every corner of a Chicago apartment property during winter. But, with some advance planning and a focus on prevention, property managers can get through the winter season without incident.
CRE O Indiana
Krieg DeVault's Adams: Plenty of good happening in Indy ... and its suburbs
January 16, 2020 | Dan Rafter
David Adams knows the Indianapolis market. He's a partner with the Real Estate and Environmental and Commercial Real Estate Lending practice groups at the Indianapolis office of law firm Krieg DeVault. In this role, he represents banks, lending institutions, developers, landlords and tenants.
The state of the Chicago market in 2020
January 15, 2020 | Matt Baker
Every year for the last 18 years, REjournals has hosted its annual kickoff conference, the Chicago Commercial Real Estate Forecast. It's a massive event—the largest of its kind—but there's always one must-see panel: The State of the Market.
Finance Midwest
Draper & Kramer closes more than $100 million for three Midwest portfolios
Draper and Kramer, Incorporated's Commercial Finance Group closed more than $100 million in loans for three commercial real estate portfolios comprising about 3.7 million square feet in assets throughout the Midwest. The loans included the refinance of an eight-building industrial portfolio in the greater Milwaukee area; an acquisition loan…
Industrial N Illinois
The Cook County conundrum
A paradox of the local industrial market is that taxes and politics have made investors leery about acquiring assets in Cook County. At the same time, however, users absolutely need to be there because there's no greater concentration in the Midwest of both consumers and good labor.
Office i Ohio
Alterra purchases 86,000-square-foot office building in Columbus
Brad Kitchen, president of Alterra Real Estate Advisors, has purchased the five-story, 86,524-square-foot office building occupied by M/I Homes' corporate office at 3 Easton Oval in the Easton Town Center mixed-use development in Columbus, Ohio.
Retail N Illinois
JLL closes sale of Westlake Plaza retail center in Wilmette
JLL closed the sale of Westlake Plaza, a 42,018-square-foot, neighborhood shopping center in Chicago's affluent Northshore community of Wilmette, Illinois. JLL represented the seller, Chicago-based Newport Capital Partners. A private real estate fund advised by Crow Holdings Capital purchased the asset. Terms of the transaction were not disclosed.
CRE c Nebraska
Three questions with ... NorthMarq's John Reed
There's something about Omaha. This market remains one of the steadiest in the Midwest, with brokers closing a solid number of big deals each year and new companies flocking to the city's downtown core and surrounding neighborhoods. What's behind Omaha's success? That's what we asked John Reed, senior vice president and managing director of…
Boeing, Sara Lee and toy soldiers: Gloor, Nieman draw crowd at Forecast event
For the record, both Andy Gloor and Drew Nieman are fans of the Chicago Cubs. But they both think the White Sox will be the next Chicago baseball team to make it to the World Series. They both also think Mitch Trubisky should be shipped far away from the Chicago Bears and that Chicago's best pizza is thin crust, not deep dish.
Office N Illinois
German American Chamber of Commerce relocating to 150 N. Michigan
The German American Chamber of Commerce of the Midwest (GACC Midwest) will relocate to 150 N. Michigan Avenue in August 2020. GACC Midwest signed an 11-year lease with CBRE Global Investors for the space in late 2019.
110 North Wacker partners with award-winning chefs, iconic steakhouse group
The Howard Hughes Corporation and Riverside Investment and Development have inked a deal that will see José Andrés' ThinkFoodGroup, together with Chicago's own Gibsons Restaurant Group, take 17,200 square feet at 110 North Wacker Drive. The group will operate a fine dining restaurant, an elevated cocktail bar experience and provide catering…
Retail O Indiana
Marcus & Millichap sells 112,000-square-foot shopping center in Indianapolis
A private real estate company based out of Fishers, Indiana, paid $3.425 million for Georgetown Plaza, a 112,000-square-foot community shopping center in Indianapolis. The Klink Group of Marcus & Millichap was retained as exclusive advisor to market the property on behalf of the seller, an Indiana limited partnership. The Klink Group also s…
Starting 2020 with a bang: ORIX building a commercial finance giant
January 9, 2020 | Dan Rafter
ORIX Corporation USA kicked off the new year with a big commercial real estate deal, completing in early January its acquisition of New York City-based Hunt Real Estate Capital.
Industrial X Missouri
Colliers sells Permian Plastics building near St. Louis
Commercial real estate services firm Colliers International Group recently completed three transactions in the St. Louis market.
Industrial Midwest
Online returns could take $41B bite out of holiday earnings as reverse logistics redoubles
December 31, 2019 | Matt Baker
Brick-and-mortar stores have an average 8 percent return rate on previously purchased goods. But that's nothing compared with the 15 to 30 percent returns that online retailers will see on holiday shopping.
CRE Q Kentucky
Three questions with ... NAI Isaac's Al Isaac
December 31, 2019 | Dan Rafter
As president of Lexington, Kentucky-based NAI Isaac, Al Isaac understands just how strong the commercial real estate market is in his market today. But what's behind that strength? Midwest Real Estate News asked Isaac three big questions about Lexington's CRE market. Here's what he had to say:
Legal N Illinois
Forecast 2020: Real Estate Law
With past experience in the offices of the Illinois Attorney General and in Chicago's Corporation Counsel, Jack George has helped to mold Chicago. Now a partner with Akerman, he is still shaping the city, though in more concrete terms, bringing zoning and legal consideration to numerous blockbuster developments.
Sturges closes more than $100 million of CRE deals in Northeast Indiana in 2019
Sturges Property Group's commercial real estate brokers have brought more than $100 Million in sales and leases to the Northeast Indiana region in the year 2019. This includes the full value of office, industrial, retail, land and investment sales and leases for the year.
Office Q Kentucky
JLL's Doug Owen: Clients aren't transactions. They're partners
Doug Owen, senior vice president with the Louisville office of JLL, earlier this year won the Broker of the Year Award, in the office brokerage category, from the Kentucky Commercial Real Estate Alliance. Owen is no stranger to this honor. He won the same award in 2012, 2013 and 2017.
BMO Tower officially breaks ground in Chicago
Goettsch Partners celebrated the groundbreaking today for Union Station Tower, also known as BMO Tower, a new 50-story office building in Chicago. Goettsch is serving as the architect for the project, developed by Riverside Investment & Development and Convexity Properties and anchored by Montreal-based BMO Financial Group.
REjournals Newsletter
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World's deepest pool for diving opens in Dubai
10:08, Sunday, 18 July, 2021
The world's deepest swimming pool for underwater diving has opened in Dubai, where people can descend 60 metres (197 ft) to a sunken city-themed landscape and play arcade games.
The pool, which holds the equivalent of six Olympic swimming pools, has been verified by Guinness World Records as the world's deepest swimming pool for diving. Deep Dive Dubai says it is 15 metres deeper than any other.The facility, shaped like an oyster in reference to the UAE's pearl diving heritage, is also the region's largest underwater film studio, the company said.
Visitors can practice scuba diving - with a tank of air - and freediving - where divers simply hold their breath.


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Marion Lüttge, née Graefe le  à Leipzig en Saxe, est une athlète allemande qui dans les années 1960 faisait partie pour la République démocratique allemande des meilleures lanceuses du javelot.

Biographie
Marion Graefe était chimiste avant de se consacrer au sport. En 1963, elle s'est mariée avec le lanceur de marteau Friedrich Lüttge, le frère de la lanceuse de poids Johanna Lüttge.

Elle a été championne de RDA du lancer du javelot en 1962, 1963 et 1966. Elle a établi aussi trois records nationaux, le dernier le avec une meilleure performance personnelle de 59.70 m lors des qualifications des championnats d'Europe de Budapest.

Palmarès

Championnats d'Europe d'athlétisme
 Championnats d'Europe d'athlétisme de 1962 à Belgrade ()
  au lancer du javelot
 Championnats d'Europe d'athlétisme de 1966 à Budapest ()
  Médaille d'or au lancer du javelot
 Championnats d'Europe d'athlétisme de 1969 à Athènes ()
  au lancer du javelot

Liens externes

Sources

Lanceuse de javelot allemande
Athlète est-allemande
Naissance en novembre 1941
Championne d'Europe d'athlétisme
Naissance à Leipzig
Naissance dans le Troisième Reich

redpajama_set_name: RedPajamaWikipedia


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Premium Home Chevron icon It indicates an expandable section or menu, or sometimes previous / next navigation options. News
The Fed says it could speed up rate hikes because of Trump's tax cuts
Akin Oyedele
Federal Reserve Chair Janet Yellen speaks during a news conference following the Federal Open Market Committee meeting in Washington, Wednesday, Dec. 13, 2017
This story is available exclusively to Business Insider subscribers. Become an Insider and start reading now.
The Federal Reserve debated the impact of tax reform on the economy and on how it sets interest rates, minutes of the December meeting showed.
Most Fed officials favor gradual rate increases. However, some noted that the economy could be about to get a boost from tax cuts, which would necessitate faster rate hikes.
The Fed expects to raise rates three times in 2018.
Tax reform could move the Federal Reserve to raise interest rates faster than it anticipates, minutes of the Fed's December meeting showed.
The central bank's minutes showed that most officials were in favor of continuing to raise borrowing costs slowly. But as the Tax Cuts and Jobs Act moved closer to becoming law, they debated its impact on future rate decisions and on economic growth.
There are "several risks" that could necessitate quicker rate hikes including faster growth, "perhaps owing to fiscal stimulus [tax reform] or accommodative financial market conditions," the minutes said.
Fed officials forecast that gross domestic product in 2018 would be at a median of 2.5%, short of the projections of up to 3% that Trump administration officials have made. But most Fed members raised their expectations for growth because of tax reform, the minutes said.
Lower taxes means Americans will extra cash to spend, which would be good for the economy. Just how much more they decide to spend is still uncertain for the Fed. On the corporate side, business owners who were surveyed said some companies would use the extra cash to expand their businesses, but most would likely use it to pay down debt or buy back their stock.
In December, the Fed raised its benchmark federal funds rate by 25 basis points to a range of 1.25% to 1.50%, as had been widely expected. The Fed hinged its decision on the US economy's better-than-expected growth and strong job creation. It expects to raise rates three times this year.
Persistently weak inflation would be one reason to slow down the pace of rate hikes, the minutes showed.
Some members of the Federal Open Market Committee have attributed weak inflation to technological changes, and the fact that the low unemployment rate is not generating the kind of demand and price increases it theoretically should.
But some officials including the Chicago Fed's Charles Evans and the Minneapolis Fed's Neel Kashkari voted against raising interest rates partly because inflation remains short of their 2% target.
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Call for Nominations: Royal Society Africa Prize 2019
African researchers
Grants for Africans
Grants for Scholars
Opportunities for Africans
Opportunity for African scholars
Royal Society Africa Prize
Royal Society Award 2019
Royal Society Pfizer Award
Royal Society Pfizer Award 2019
Royal Society Pfizer Award 2019African researchers
The call for nominations is now open for the Royal Society Africa Prize. The Royal Society Africa Prize (formerly known as the Royal Society Pfizer Award) is to recognise research scientists based in Africa who are making an outstanding innovative contribution to the biological sciences, including basic medical science, which contributes significantly to capacity building in Africa.
The winner will receive
a bronze medal,
£11,000 grant towards the research project and
a gift of £1,000
The Prize is intended for researchers at an early stage of their research career (usually having received their PhD within the last 10-15 years) with the potential to build a research project to follow on from the prize.
The research must be based in Africa.
Nominations can be made by senior academics and members of the national academies of science.
The project and nominee should be linked with an African centre of excellence, which would normally be a University, or equivalent research centre.
Nominations close on Monday 28 January 2019 at 3pm.
Visit the official site for more information
READ ALSO L'ORÉAL-UNESCO International Women Awards 2022(€100,000 prize)


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Bred from a cross of Wagyu and Aberdeen Angus cattle, the meat has a delicious rich beef flavour and a fine marbling of fat throughout.
Bred from a cross of Wagyu and Aberdeen Angus cattle, the meat has a delicious rich beef flavour and a fine marbling of fat throughout that results in succulent tender and richly flavoured beef..
Please note that this product is supplied frozen.


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text:
Believe in Me ! est le sixième album studio de Charles Aznavour et le premier chanté en anglais. Il est sorti en 1958 chez Ducretet-Thomson.

Liste des chansons

Notes et références

Album de Charles Aznavour


text:
Roy Nelson vs. Gabriel Gonzaga Set for Reshuffled Main Card at UFC 146
By Matt Erickson
Updated Apr 24, 2012 at 10:00am
Gabriel Gonzaga (UFC)
TUF 10 winner meets former heavyweight title challenger May 26
The UFC 146 shuffle continues, and Roy Nelson will now face Gabriel Gonzaga on the all-heavyweight main card.
UFC 146 is set for May 26 at the MGM Grand Garden Arena in Las Vegas. The main event was scheduled to be a heavyweight title fight between champion Junior dos Santos and Alistair Overeem. But on Friday, UFC president Dana White pulled Overeem from the fight, anticipating him not being licensed by the Nevada State Athletic Commission at a hearing today. White announced Frank Mir as the new title challenger, moving him out of a top contenders fight with Cain Velasquez in the co-main event on the card.
That left Velasquez in need of a new opponent, and Antonio "Bigfoot" Silva was moved up from his fight with Nelson for that spot. And that, of course, left Nelson in need of a new opponent – so Nelson was moved up from a fight against Shane Del Rosario that was also booked for the main card.
Nelson (16-7, 3-3 UFC) has had a rough go of it since starting his UFC career 2-0, including a knockout win over Brendan Schaub to win Season 10 of "The Ultimate Fighter." After a second straight Knockout of the Night bonus for a 39-second stoppage of Stefan Struve in March 2010, Nelson has lost three of his last four fights.
At UFC 143 in February, Nelson lost a Fight of the Night unanimous decision to Fabricio Werdum that left him battered and bloodied – but unable to be finished. That erased the knockout win he had over Mirko "Cro Cop" Filipovic at UFC 137 last October that had him back in the win column after back-to-back losses to dos Santos and Mir.
Gonzaga (13-6, 8-5 UFC) returned to the UFC in January at UFC 142 in his native Brazil and picked up a first-round submission victory over Ednaldo Oliveira, a highly touted and then-unbeaten training partner of dos Santos. Gonzaga, who started his UFC career 4-0, including a legendary head-kick knockout of Cro Cop, challenged Randy Couture for the heavyweight title at UFC 74, losing by third-round TKO. Since that loss, it was an up-and-down stretch for "Napao." He went 3-4 in the UFC with wins over middle-of-the-pack fighters, none of which currently are with the promotion, and losses to Werdum, Shane Carwin, dos Santos and Schaub. The latter two wound up costing him his UFC job. But after a win outside the promotion, the Massachusetts-based Gonzaga was brought back to the UFC with a new deal and a fight in his home country for the first time since 2004.
The genesis of the UFC 146 main card switches is from Overeem running afoul of the Nevada State Athletic Commission earlier this month when it was revealed a pre-fight drug test he took tested positive for elevated testosterone-to-epitestosterone levels. Overeem on Friday was removed from the card by White, who previously had said that regardless of what might happen for an opponent for dos Santos, the Velasquez vs. Mir fight would remain on the card. Overeem was scheduled to appear in front of the NSAC on Tuesday and is expected to request a continuance in his case. In a statement released yesterday, Overeem said his elevated T/E ratio was due to a doctor-prescribed anti-inflammatory medication. His tested levels were in excess of 10:1, according to the NSAC, and have been reported to be 14:1. The NSAC's maximum standard is 6:1. Other state commissions have a standard of 4:1. The average male has a T/E ratio of 1:1.
Along with the all-heavyweight main card, UFC 146 features a featherweight fight between TUF 14 winner Diego Brandao and Darren Elkins; a middleweight bout between Jason "Mayhem" Miller and C.B. Dollaway; a welterweight bout between Dan Hardy and Duane Ludwig; lightweight fights between Paul Sass and Jacob Volkmann and Edson Barboza and Evan Dunham; and former WEC featherweight champ Mike Brown vs. Daniel Pineda.
Published Apr 24, 2012 at 10:00am
Alistair Overeem, Antonio Silva, Cain Velasquez, Dana White, Frank Mir, Gabriel Gonzaga, Junior Dos Santos, MMA, MMA News, Roy Nelson, UFC
Original Roy Nelson opponent Antonio Silva was moved up to face Cain Velasquez with Velasquez opponent Frank Mir moved up to meet Junior dos Santos. Nelson now meets Gabriel Gonzaga on the main card of UFC 146.


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A flying buttress of a book, continuing the hefty Kingsbridge saga historical novelist Follett began with Pillars of the Earth (1989) and World Without End (2007).
It's all a bit overwrought for what is, after all, a boy-loves-girl, boy-swashbuckles-to-win-girl yarn, but it's competently done. Follett's fans will know what to expect—and they won't be disappointed.