text:
\section{Introduction}\label{sec:introduction}
With the globalization of the semiconductor supply chain and the growth of the semiconductor market value, counterfeit integrated circuits (ICs) have become an established threat to the semiconductor community \cite{CounterfeitIC:UGuin, ChesDom, Counterfeit:CNET, Counterfeit:Micron, CSST_Rahman}. Counterfeit electronic parts and the risks associated with them have been increasing rapidly, which is reflected in the recent news \cite{CounterfeitIC:UGuin, ChesDom, Counterfeit:CNET, Counterfeit:Micron}. Many commercially available memory chips are fabricated worldwide in untrusted facilities and, therefore, a counterfeit memory chip/module can easily enter into the supply chain in different formats: recycled, re-marked, tampered, out-of-spec, forged-documented, defective, cloned, overproduced etc. \cite{CounterfeitIC:UGuin,ujjwalnew,ChesDom, foundaryIdentification:Wendt,ML:Ahmadi,forensic:Helinski}. Recent studies show that the global market share of counterfeit IC is worth $\$169$ billion, and $\sim 17 \%$ of which is contributed by memory chips \cite{ujjwalnew,ChesDom}.

The inclusion of counterfeit components in an electronic system can endanger personal and national privacy, sabotage critical infrastructure, and damage the viability of entire business sectors because of their sub-standard quality, poor performance, and a shorter life-span \cite{CounterfeitIC:UGuin,foundaryIdentification:Wendt,ML:Ahmadi,forensic:Helinski, ujjwalnew}. A counterfeit chip can fail any time after being deployed in the system, or they can be exploited to leak sensitive information or to allow remote access and endanger the integrity, confidentiality, and safety of a system by performing invasive or non-invasive fault-injection attacks \cite{rowhammer_PUF, rowhammer_DDR4}. Furthermore, recent experimental studies suggest that some DRAM modules are more vulnerable to rowhammer attack, a method of changing the restricted memory contents by repeated access to their adjacent rows \cite{rowhammer_DDR4}, because of their poor resiliency against noise, interference, etc.

A single solution to detect or prevent counterfeiting is unrealistic because of the diversity of counterfeit types, sources, and refinement techniques \cite{CounterfeitIC:UGuin,foundaryIdentification:Wendt,ML:Ahmadi,forensic:Helinski}. Several discrete countermeasures have been proposed by the industry and academic researchers, which can be categorized into two major types: (i) electrical-based testing and (ii) physical-inspection based testing \cite{CounterfeitIC:UGuin,ChesDom, ujjwalnew, foundaryIdentification:Wendt,ML:Ahmadi,forensic:Helinski}. Some solutions are applicable to chips that are already in the market, and some solutions are integrated with the original chips for future tracking or metering \cite{CounterfeitIC:UGuin,ChesDom, ujjwalnew, foundaryIdentification:Wendt,ML:Ahmadi,forensic:Helinski}. Most of the solutions are ineffective for memory chips because they might require expensive equipment, expensive testing set-up, maintenance of an expensive database, and exhaustive enrollment process \cite{ChesDom,ujjwalnew, SCARE}. Besides, most physical-inspection based solutions are invasive and therefore, not applicable for mass-volume detection \cite{ChesDom}. For mass-volume verification and low-cost testing, electrical-based testing is required that is non-invasive \cite{ujjwalnew}. However, a non-invasive solution for counterfeit DRAM identification is extremely difficult because they may remain functional at the time of purchase and pass standard product qualification tests. Also, most existing solutions focus on a single counterfeit type (e.g., detecting recycled chips) \cite{CounterfeitIC:UGuin, ChesDom, SCARE}. Furthermore, current extensive regulations require a series of expensive testing methodologies \cite{ujjwalnew, ChesDom}. Therefore, a proper solution is required to identify counterfeit memory chips before deploying them in mission-, safety-, and security-critical systems.

In this paper, we propose a machine-learning-based technique to identify the origin of a DRAM manufacturer along with DRAM specification (i.e., density, grade, etc., see Sec. \ref{sec:ProbDef} for details) by exploiting DRAM latency (the required time to move charge from one location to another location in DRAM \cite{DRAMlatency:Chang,DRAMLatencyPUF:Kim, latencyTalukder,latencyTalukderTRNG}) variations to detect and prevent major counterfeit types. The major contributions of this paper include:
\begin{itemize}
\item We propose a framework to identify the origin of the DRAM manufacturer by exploiting the facts that the architectural, layout, and manufacturing process variations are reflected in latency variations. The framework is also capable of verifying specification of individual DRAM module.
\item We extract the most appropriate features from the latency-based erroneous patterns in DRAM modules to amplify the variations among manufacturers and specifications.
\item We propose a machine learning approach to determine the origin of the DRAM manufacturer based on the extracted features. The same method also separates DRAM modules of different specifications that are from the same manufacturer.
\item We validate our proposed framework with off-the-shelf memory modules (commercial grade) from three major manufacturers- Micron, Samsung, and SK Hynix \cite{DRAMmarketShare}.
\item We validate the robustness of our proposed technique against temperature and voltage variations.
\end{itemize}
The rest of the paper is organized as follows. In Section \ref{sec:background-motivation}, we present the background of DRAM architecture, read/write operation, low-latency induced errors. We also present a set of motivations for our proposed framework in Section \ref{sec:background-motivation}. We highlight our major objectives and necessary assumptions in Section \ref{sec:ProbDef}. We propose the manufacturer identification framework in Section \ref{sec:method}. The experimental results are presented and discussed in Section \ref{sec:result}. We highlight the major limitations and the scopes of our proposed work in Section \ref{sec:futureWork}. We conclude our article in Section \ref{sec:conclusion}.

\section{Background and Motivations}\label{sec:background-motivation}
\subsection{DRAM Architecture and Latency Variations}\label{subsec:DRAMarchitecture}
A DRAM system can have one module or several modules depending on the memory requirement. A DRAM module is divided into one or multiple ranks \cite{DRAMlatency:Chang, DDR3:JEDEC, DRAM:Lui}. Each rank consists of several DRAM chips; and together, they provide a wide data-bus (usually 64 bits). The DRAM memory structure is analogous to a 2-D memory cell array. For simplicity, we can consider that each bit of the 64-bit word comes from 64 individual cell arrays. The rows of the DRAM are known as wordline (or page). The columns are known as bitline, and the chip density determines the total number of rows. The bitlines are connected to the row-buffer, a series of sense-amplifiers. Several DRAM cells are connected to a wordline. A DRAM cell consists of two components- an access transistor and a capacitor to hold the charge. The access transistor connects the capacitor with a bitline and is controlled by the wordline. The state of charge in the capacitor determines the memory content (i.e., `1' or `0'). Depending on the memory architecture, DRAM memory cells can be categorized into \textit{true-cell} and \textit{anti-cell} \cite{DRAM:Lui}. A \textit{true-cell} stores logic `1' with a fully charged capacitor and `0' with an empty capacitor. On the other hand, an \textit{anti-cell} stores `0' with a fully charged capacitor and `1' with an empty state. However, the stored charge in the capacitor leaks away, which leads to an incorrect reading after a certain amount of time. So, to ensure the integrity, the content of a DRAM cell needs to be refreshed periodically before the memory contents flip. This time interval is known as the \textit{Retention} time, which is 32 or 64 milliseconds (ms) \cite{DDR3:JEDEC}. A failure to refresh before the retention time can alter the memory content.

To write/access the cell content, the column (or bitline) voltage need to be initiated at a specific reference voltage ($V_{ref} = \frac{V_{DD}}{2}$).
\begin{figure}[ht!]
\centering
\captionsetup{justification=centering, margin= 0.5cm}
\includegraphics[width=0.48\textwidth]{timing2.pdf}
\caption{DRAM timing at reading cycle \cite{DRAMlatency:Chang}.}
\vspace{-3mm}
\label{fig:timing}
\end{figure}
Fig. \ref{fig:timing} presents a simplified version of DRAM read operation. A read operation starts with an ACTIVATE (ACT) command executed by the memory controller. $t_{RCD}$ is called the \textit{Activation} latency which is required to activate (turn `ON') the access transistor properly. The activated access transistor creates a conducting path between the storage capacitor and the bitline. The charge stored in the capacitor perturbs the bitline voltage. The sense-amplifier senses the perturbed voltage and amplifies it to an appropriate binary value. At this moment, the memory controller applies the READ command to read the data and fetch it to the data bus. The minimum time latency between the READ command and the first data bit to appear in data-bus is called \textit{Column Access Strobe} latency or \textit{CAS} latency ($t_{CL}$). DRAM's read operation is a destructive process. Therefore, the charge on the DRAM storage capacitor needs to be restored after each successful reading. The time required to activate an access transistor and to restore the charge on the corresponding storage capacitor is known as the \textit{Row Active} latency or \textit{Restoration} latency ($t_{RAS}$). At the end of the restoration process, the memory controller again applies the \textit{PRE} command to re-initiate all the bitlines for the next read/write operation. The \textit{PRE} command precharges all bitlines to $V_{ref}$. The time required to precharge all bitlines properly is called \textit{Precharge} Time ($t_{RP}$). The \textit{PRE} command also deactivates all previously activated access transistor. The $t_{RAS}+t_{RP}$ is the total time required to read a DRAM row properly; this total time is called \textit{Row Cycle} Time ($t_{RC}$).

Usually, the DRAM manufacturer specifies a set of timing parameters for reliable read and write operation \cite{DDR3:JEDEC}. At the reduced timing latency below the standard value, we experience unreliable read and write operations, which is different from one module to another \cite{DDR3:JEDEC, DRAMlatency:Chang, DRAMLatencyPUF:Kim}. In our proposed method, we capture the architectural, layout and manufacturing process variations by exploiting the errors originated at the reduced \textit{Activation} latency ($t_{RCD}$).

\subsection{Counterfeit, Existing Work, and Motivations}\label{subsubsec:Motivations}
The modern horizontal semiconductor supply chains involve several parties to reduce the fabrication cost and time to market \cite{CounterfeitIC:UGuin, ChesDom, ujjwalnew, supplyVLSI:Lui, PVal:Basak}. In this model, a chip is designed in one place while fabricated in a different place. Because of traveling IPs in different formats and involvement of untrusted parties, the modern semiconductor supply chain suffers from counterfeiting (such as hardware trojan or malicious change in third-party IP or chip layout, cloning IPs/ICs, remarking, etc.) \cite{CounterfeitIC:UGuin, PVal:Basak, CSST_Rahman,trojannima}. Fig. \ref{fig:Piracy} shows the IC/DRAM design flow for authentic-chip and pirated-chip production cycle. The untrusted party (the third-party IP developer, the foundry, the assembly, the distributor, etc.) can perform counterfeiting at different phases of the manufacturing process. An untrusted party can send out overproduced, and out-of-spec/defective ICs/DRAM chips to the market. The untrusted party also can clone the original chip by stealing IPs or by reverse-engineering (from a post-fabricated product) to avoid research and development (R\&D) costs. Recycled ICs also can be added to the supply chain at different stages (e.g., in the foundry or the assembly). Below, we summarize (but not limited to) the motivations of our proposed work.

\begin{figure}[ht!]
\centering
\captionsetup{justification=centering, margin= 0.5cm}
\includegraphics[width=0.45\textwidth]{Piracy2.pdf}
\caption{(a) Authentic-chip production cycle vs. (b) counterfeit-chip production cycle \cite{PVal:Basak}.}
\vspace{-3mm}
\label{fig:Piracy}
\end{figure}

\hspace{13pt}\textbf{i) Existing countermeasures and their limitations:} In 2015, the Department of Defense imposed several rules to stop entering counterfeit components in the defense supply chain \cite{ujjwalnew}. These rules create more accountability and require proper testing standards along with maintaining a database if the electronic components are acquired from the untrusted party. Researchers, industries, and several organizations have developed several test plans or standards that require a series of testing methods. Visual inspection, X-ray imaging, scanning electron microscopy (SEM), energy disruptive spectroscopy, terahertz spectroscopy, etc., are the most common physical inspection-based techniques that are used to detect counterfeit chips \cite{CounterfeitIC:UGuin, foundaryIdentification:Wendt, ML:Ahmadi, forensic:Helinski}. Some imaging techniques capture the internal features of a sample and might be very effective to identify certain counterfeit types. However, these physical inspection-based techniques usually require expensive tool, long test time for sample collection and imaging, subject matter experts \cite{CounterfeitIC:UGuin}. Curve trace testing (CTT), parameter testing, burn-in testing, aging-based analysis, etc. are the most common electrical test methods that can be used to identify counterfeit components \cite{onChipSensor:Zhang, onChipSensor:He}. Existing burn-in and aging analysis-based techniques partially destructive because months to years of the device are consumed from the accelerated aging. The parameter testing is useful but requires expensive test setup and complex test programs. On the other hand, the CTT (electrical testing to capture damaged packages, broken or damaged wires, cracked die, etc.) is only useful for detecting recycled ICs \cite{ChesDom,ujjwalnew}.

Researchers also have proposed pre-fabrication techniques to prevent counterfeiting such as hardware metering (\bcite{CounterfeitIC:UGuin, hwmeter:Alkabani}), secure split test (SST) (\bcite{CSST_Rahman}), placing on-chip sensors (\bcite{onChipSensor:Zhang, onChipSensor:He, ChesDom, CDIR:Zhang}), electronic chip ID (\bcite{CounterfeitIC:UGuin}), DNA marking (\bcite{DNA:Hayward}), RFID-based tracking (\bcite{RFID}), blockchain-based traceability (\bcite{Kundu}), PUF-based techniques (\bcite{rowhammer_PUF, DPUF:Sutar, DRAMLatencyPUF:Kim, DPUF:Tehranipoor, Xiong:DPUF, Hashemian:DPUF}), etc. Hardware metering and SST are used to provide post-fabrication control but require hardware changes and complex supply chain management. Besides, each of the chips needs to go through the unlocking process, which is tedious and adds extra steps in the supply chain. On the other hand, on-chip sensors are used to monitor the device degradation but need some additional sensors and monitoring units. ECID tags each chip with a unique ID by adding some non-programmable memory (such as OTP or ROM). The ECID-based solution is susceptible to tampering. In DNA marking technique, a mixed plant DNA is used to create a new DNA sequence \cite{DNA:Hayward}. Later, this sequence is applied with the ink to mark the chip package. However, this technique suffers from a complex authentication scheme. For the PUF-based technique, the unique ID generated from each chip can be used to identify authentic chip. However, the PUF-based techniques require an extensive database for registration purposes. The registration and authentication procedures are exhaustive as well. The DRAM memory itself can be used as a PUF, but the uniqueness of PUF can make the solution very challenging. Moreover, most of the existing solutions address a single counterfeit type.

Our proposed machine-learning based technique has some advantages compared to other possible manufacturer identification techniques:
\begin{itemize}
    \item In the proposed machine-learning based technique, we store minimal information (a few statistical parameters) to attest and detect a large group of memory modules/chips. On the other hand, for example, in PUF-based technique, we need to create a golden/reference dataset by accumulating all challenge-response pairs for an individual memory module/chip.
    \item Our proposed technique does not need any exhaustive registration processes. Analyzing a small number of samples from a large group of modules is sufficient enough to reveal the detail statistical information of that group.
    \item Furthermore, the machine-learning based technique can serve some particular purpose; for example, the user might want to test the authenticity of the purchased device without knowing any details of chip design. In such a case, the user does not need to have exclusive access to any sensitive information (e.g., the challenge-response database of PUF-based scheme).
    \item This technique does not require any hardware modification unlike many existing techniques such as: hardware metering, SST, on-chip sensor-based authentication, ECID, etc. \cite{CounterfeitIC:UGuin}.
    \item The proposed solution is invasive and less expensive compared to some other techniques.
\end{itemize}

\textbf{ii) Importance of attesting the DRAM origin}: Attesting the origin of the foundry or the manufacturer is a critical need to (a) enforce the license agreement, (b) ensure and track the quality of the chip, (c) rank the manufacturer based on the quality and durability of their products, (d) protect the intellectual property, (e) ensure accountability, and (f) stop the spread of counterfeit memory chips worldwide. Counterfeiters usually hide the origin of the foundry, fake the quality of the original memory modules/chips, and infringe on the rights of the original manufacturer \cite{Counterfeit:CNET, Counterfeit:Micron, foundaryIdentification:Wendt, ML:Ahmadi, forensic:Helinski, CSST_Rahman}. On the other hand, verification of individual DRAM module's specification can detect certain counterfeit types such as upgrading a DRAM module through remarking or forged documentation.

The existing techniques on attesting of the foundry rely on simulation or test data from fabrication and packaging facilities \cite{foundaryIdentification:Wendt, ML:Ahmadi}. Unfortunately, in most cases, the testing data are not made publicly available and, therefore, a party that does not have access to those test data cannot make the classifier and (or) cannot verify the ratified foundry. In contrast, in our proposed technique, the DRAM chips can be authenticated based on trained classifier provided by the manufacturer or a trusted third party. In the proposed technique, the verifier does not require any prior knowledge of the manufacturing process. The classifier input, a set of features, can be easily evaluated in any low-cost embedded or FPGA-based system.

\textbf{iii) Vulnerability of counterfeit memory chips:} A counterfeit memory module can be more vulnerable to attacks because of their less resiliency against noise. For example, recent studies demonstrate that some DRAM modules possess inferior quality than others, which are more susceptible to rowhammer attack \cite{rowhammer_DDR4}. Our experimental results also suggest that a recycled DRAM chip is $\sim8\%$ more vulnerable to rowhammer attack.

\textbf{iv) Modification of serial presence detect (SPD) information:} DRAM manufacturers provide the information of all DRAM timing parameters in a small read-only memory (ROM) which is integrated with the DRAM module \cite{JEDEC:SPD}. It has been demonstrated that a counterfeiter can modify this information (aka SPD information) to make a DRAM authentic or superior \cite{SPD:zak}. These DRAM chips can pass the initial test but can cause critical failure of the system during runtime under some operating conditions that are considered safe \cite{reducedVoltage:chang}.

\section{Objectives and Assumptions} \label{sec:ProbDef}
The objective of this work is to identify the DRAM origin (i.e., the origin of the manufacturer and the specification of individual DRAM) reliably by capturing all variabilities. The major variations to attest and identify the origin of the manufacturer include:
\begin{itemize}
    \item \textbf{Architectural variations:} Manufacturers usually optimize the DRAM architecture in various ways to support the specifications and product cost \cite{DRAMArch:Jacob, LatVar:Lee}. For example, manufacturers shrink the die size to reduce the cost per cell, which can cause the DRAM more susceptible to noise, more vulnerable, and less robust. The minimum required latency parameters vary from one architecture to another. Therefore, for a given reduced timing latency, DRAMs from different manufacturers create a different amount of errors \cite{DRAMlatency:Chang,DRAMLatencyPUF:Kim, LatVar:Lee}.
    \item \textbf{Layout variations:} Chip layout variation from one manufacturer to another may originate from several sources such as chip area, floorplanning, placement, and routing, etc. \cite{LatVar:Lee, layoutVar:clein}. This layout variation may affect different electrical characteristics such as RC path delay, power utilization ($I^2R$ loss), noise margin, etc., which can be reflected in the DRAM latency parameters \cite{DRAMlatency:Chang,DRAMLatencyPUF:Kim}.
    \item{\textbf{Process variations:} The intrinsic process variation can be either random or systematic \cite{processVar:Cao, processVar:kuhn}. The random process variation can be considered as noise and varied among the chips fabricated on a single silicon wafer. On the other hand, the systematic process variation depends on the quality of the fabrication plant and also related to the microstructural locality and pattern. The process variation can lead to different error patterns at a given reduced latency parameter and can reveal the information about the fabrication plant and the microstructure.}
\end{itemize}

Our proposed technique of identifying the memory manufacturer is based on the following assumptions.
\begin{itemize}
    \item \textbf{Assumption on memory class}: A manufacturer ships memory module with a part number on it, which contains the manufacturer information and chip specification, such as density, speed grade, package, temperature range, bus width, die generation, etc. \cite{hynix:partnmbr}. In addition to part-number, a manufacturer also provides additional module specification on the module label \cite{hynix:Tchspprt}, such as JEDEC PCB layout version \cite{DesignFile:JEDEC}, SPD version \cite{JEDEC:SPD}, manufacturing country, manufacturing lot number, etc. Timing parameters of the DRAM module are specified into SPD data \cite{JEDEC:SPD}. In this work, two DRAM modules are considered as two different classes, if one of the following information is mismatched: i) manufacturer, ii) part number, and iii) PCB layout version/SPD data. A change in one specification can lead to different GDSIIs (related to the die generation, and specification), packaging, PCB layouts, or SPD data. Note that a manufacturer may send a single GDSII file to different fabrication plants. We assume that fabrication plants with the same GDSII follow similar design rules to minimize the effect of systematic process variations.

    \hspace{1.5em} In this article, `sample', `positive sample', and `negative sample' mean memory module under test, memory module that originally belong to the target class, and memory modules that originally do not belong to the classifier target class (i.e., belong to the outlier region), respectively.

 \item \textbf{Assumption on data training, and verification}: We extract different features to capture the architectural, layout, and process variation. These features are trained to learn a statistical model. In our proposed scheme, the manufacturer or a trusted party is responsible for training the statistical model and releasing it for public use. We also assume that, while training the statistical model for a particular memory class, manufacturers do not have any statistical information from other memory classes (i.e., from negative class). However, in practice, the manufacturer may collect a few random samples from other classes. Training statistical model with some negative examples might be beneficial, but it is almost impossible to collect all samples from all negative classes because of the diversity of memory chips/modules and several manufacturers. We also assume that the chips/modules that are used for the enrollment in the proposed technique are authentic. The regular consumers should able to verify their purchased DRAM class by only using the statistical model. We also assume that consumers do not have any knowledge on memory architecture and manufacturing process.
\end{itemize}

\section{Proposed Method} \label{sec:method}
To extract all possible variabilities, we reduce the DRAM timing latency and obtain the signatures (i.e., the error pattern or fail bit count) that reflect the architectural, layout, and process variations. Below, we present a framework to identify the DRAM class that involves several steps.

\textbf{Step 1: Data acquisition.} The experimental results show that the latency-induced error pattern depends on the data written into the memory, the amount of latency reduction, and the DRAM module \cite{PARBOR:Khan}. To capture the maximum variations among the memory classes, we write four different sets of data to the memory module: (i) Data set 1: solid data pattern (all 1's), (ii) Data set 2: inverse solid data pattern (all 0's), (iii) Data set 3: column stripe data pattern (101010$\cdots$), (iv) Data set 4: inverse column stripe data pattern (010101$\cdots$). Then, each data set is read back from the DRAM module at the reduced \textit{Activation} time ($t_{RCD}$) to capture module dependent erroneous outputs.

\textbf{Step 2: Feature selection.} It is crucial to select the optimum number of features since the performance of classifiers is sensitive to the choice of the features and features' attributes such as correlation, noise, and other factors. In this step, we will select the key features that can effectively capture architectural, layout, and process variations observed in DRAM since they directly impact the accuracy, computation time, and storage (of golden data) of our proposed technology. The classification models are created based on a total of 26 features collected from the four sets of data. Features are extracted from the whole data that is read out from one page. A single bank from 1GB memory module contains 16k+ pages per bank (eight banks per module), and for the case of a 2GB memory module, each bank includes 32k+ pages. Each memory page contains 1,024 words and each word contains 64-bits of data. The data collected (at reduced $t_{RCD}$) from each memory pages are then rearranged into a 1,024$\times$64 (denoted as $d_R$ of size $w\times b$, where, $w=$ number of words in a page, $b=$ number of bits in each word) binary array. Moreover, for each page, we create another array, $d_F$ (same size of $d_R$) which tracks the location of flipped bits. Note that, the $d_F(i,j)=1$, if $d_R(i,j)$ is flipped with respect to the actual data that is written to the DRAM otherwise, it will be 0. The following features have been chosen from each page to identify the DRAM origin (i.e., the origin of the manufacturer and the specification of individual DRAM).\\
\textbf{\textit{Feature 1 ($\Psi_1$)}:} The total number of flips, also known as failed bit count (FBC), is used to capture the data dependency, process variation, and layout variation of the DRAM chips. The silicon results show that the FBC counts change from one DRAM module to another module.\\
\textbf{\textit{Feature 2 ($\Psi_2$)}:} The subset of FBC bits that are flipped to logic 1.\\
\textbf{\textit{Feature 3 ($\Psi_3$)}:} The compression ratio ($r$) depends on the distribution of ones and zeros in a string (i.e., randomness). The compression ratio is defined as Eq. \ref{eqn:compRatio}.
\begin{equation} \label{eqn:compRatio}
r = \frac{S_{u}}{S_{c}}
\end{equation}

Where $S_{u}$ and $S_{c}$ are the sizes of the uncompressed and compressed data respectively.

Our preliminary experimental results show that the compression ratio of $d_R$ varies from one manufacturer to another. We compress data using standard ZLIB library \cite{ZLIB:Deutsch} and then compared the data size with the original data. The ZLIB library is optimized for the minimal computational overhead while compressing the data.

\textbf{\textit{Feature 4 ($\Psi_4$)}:} The whole block of $d_F$ is divided into a set of smaller blocks (each block is $64\times1$ of size and denoted by $B_w$). The standard deviation on the FBCs in these $B_w$s are considered as a feature. This feature captures the spatial locality of FBC along the dimension $w$. The higher value of standard deviation represents a greater spatial locality.\\
\textbf{\textit{Feature 5 ($\Psi_5$)}:} The block $d_F$ is divided into a smaller block, $B_b$ (of size $1\times8$) and then FBC is counted on each of the smaller blocks. Then we choose the standard deviation of those FBCs as the feature $\Psi_5$. The spatial locality along the dimension $b$ is captured with this feature $\Psi_5$.\\
\textbf{\textit{Feature 6 ($\Psi_6$)}:} Like $\Psi_4$, we calculate the standard deviation of FBCs on 64 blocks (of size $1024\times1$). This feature captures the fact that some cells of each 64-bit words are more error-prone than others.\\
\textbf{\textit{Feature 7 ($\Psi_7$)}:} Like $\Psi_5$, we calculate the standard deviation of FBCs on 1024 blocks (of size $1\times64$). This feature explores the fact that some bitlines are more error-prone than others.

All features except the $\Psi_2$ is extracted from all four data sets. The feature $\Psi_2$ is only extracted from the dataset 3 and dataset 4 (see Step 1). Choosing block-size for $\Psi_4$ through $\Psi_7$ is correlated to the DRAM organization. For example, we choose a block size of $1\times8$ ($B_b$) for $\Psi_5$ to capture the variations among the chips in a DRAM module. Our tested DRAM modules consist of four or eight chips, and each chip shares $1,024\times16$ or $1,024\times8$ blocks. We use block ($B_b$) height of 8 to extract average variations among the chips to ensure consistency among classes.

\textbf{Step 3: Machine-learning algorithms for detecting the DRAM origin.}
After extracting the most suitable feature, we develop a machine-learning based technique to identify counterfeit DRAM modules. In our proposed technique, we use one-class classifier. Although one-class classifier is a more complex statistical problem, recent works demonstrated that it is more advantageous compared to other machine learning based techniques while detecting counterfeit ICs \cite{ML1:Huang, ML2:Sinanoglu, ML:Ahmadi, ML4:Huang}. On the other hand, in the traditional binary-class classifier, if the statistical diversity is enormous in the negative samples, the classifier might provide poor decision boundary due to the small negative train data \cite{SVDD:Chang, VDD:Tax}. In such a scenario, it will be very expensive or even impossible to collect data from the negative class covering the wide statistical diversity. This situation is particularly true for counterfeit IC detection as counterfeit ICs can be introduced from a wide variety of sources (see Sec. \ref{subsubsec:Motivations}). On the contrary, the one-class classifier \cite{SVDD:Chang, VDD:Tax, occSVM:Scholkoph, disOCC:Castillo, OCC:Taxonomy} is trained by only positive class samples. In our proposed method, we use Support Vector Data Description (SVDD) \cite{SVDD:Chang, VDD:Tax} to detect the outliers of a specific class. SVDD creates a spherical decision boundary in feature-space around the train dataset of a given class. For a given training data $x_{i} \in \mathcal{R}^n, i= 1, 2, 3, ..., l$, Tax et al. \cite{VDD:Tax} solved the following optimization problem given by Eq. \ref{eqn:svdd1}.

\begin{equation} \label{eqn:svdd1}
\begin{aligned}
& \min_{R,\bm{a},\xi} R^2 + \mathcal{C} \sum_{i=1}^{l} \xi_{i} \\
& \text{subject to, } \left \| \varphi(\bm{x})- \bm{a} \right \|^{2} \leq R^2 + \xi_{i}, i = 1, 2, 3, ..., l \\
&\hspace{1.7cm} \xi_{i} \geq 0, i = 1, 2, 3, ..., l
\end{aligned}
\end{equation}

Here, $\xi_{i}$ is a slack variable and $\varphi(\bm{x})$ is the mapping function from the lower dimension to a higher dimension. $R$ and $\bm{a}$ are the radius and center of the encircling boundary, and $\mathcal{C}$ is the regularization parameter. A smaller value of $\mathcal{C}$ causes more training samples to be treated as an outlier. A sample will be considered as an outlier if $\left \| \varphi(\bm{x})- \bm{a} \right \|^{2} > R^2$.
However, Eq. \ref{eqn:svdd1} can be efficiently solved by the Eq. \ref{eqn:svdd2}.

\begin{equation} \label{eqn:svdd2}
\begin{aligned}
& \max_{\alpha} \sum_{i} \alpha_{i}\mathcal{K}_{i,i} - \sum_{i,j} \alpha_{i}\alpha_{j}\mathcal{K}_{i,j} \\
& \text{where, } \sum_{i=1}^{l}\alpha_{i} = 1
\end{aligned}
\end{equation}

Here, $\mathcal{K}$ is the kernel function (i.e., $\mathcal{K}_{i,j} = \langle\varphi(x_{i})^{T}\cdot\varphi(x_{j})\rangle$). In our case, we have chosen the radial basis kernel function (Eq. \ref{eqn:radbas}) \cite{radbas:Scholkopf}. The radial basis function is useful when the data are not linearly separable.

\begin{equation} \label{eqn:radbas}
\mathcal{K}_{i,j} = exp(-\gamma\left \| x_{i} - x_{j} \right \|^2), \gamma > 0
\end{equation}

In Eq. \ref{eqn:radbas} $\gamma$ is a free parameter. A larger value of $\gamma$ enables the classifier to capture more complex attributes of the training data. On the other hand, the classifier model might suffer from overfitting problem if the value of $\gamma$ is too large. However, the $\mathcal{C}$ and $\gamma$ can be optimized more efficiently by introducing artificial outliers and applying k-fold cross-validation \cite{outlier:tax}. Moreover, the classifier accuracy can be increased by introducing some real negative examples during training \cite{VDD:Tax}.

\textbf{Step 4: Constructing a framework to detect DRAM manufacturer.} Fig. \ref{fig:protocol} presents the proposed framework to identify the DRAM origin (i.e., the origin of the manufacturer and the specification of individual DRAM). In the proposed framework, we assume that the manufacturer or a trusted party provides the classifier model to the consumer and also defines a threshold for \textit{Positive Page Rate} ($PPR$). The \textit{positive page rate} ($PPR$) is defined as follows-

\begin{equation} \label{eqn:FPR}
\textit{PPR} = \frac{\textit{No. of pages that are classified as `positive'}}{\textit{No. of test pages from the memory module}}
\end{equation}

In Fig. \ref{fig:protocol}, the steps, shown in the blue region, are performed by the OEM (Original Equipment Manufacturer), and the steps shown in the green region are performed at the consumer end. All other steps (covered by the orange region) can be processed in either consumers' system or manufacturers' system. Initially, the OEM or a trusted party trains a classifier based on all page data that are captured from one or multiple DRAM samples of the target class. The OEM or trusted party should also specify the number of memory pages that need to be tested from a memory module to prove its authenticity. Then, based on the sample statistics, the OEM should choose a threshold ($\lambda_{PPR}$) to decide whether a DRAM is manufactured by them or not. If the $PPR$ from the test module is higher than the threshold, then the memory module should be considered as authentic. The selection of the threshold value $\lambda_{PPR}$ and the number of test pages ($n$) depend on the quality of the classifier and the manufacturing process. Higher process variations might cause a large statistical diversity on the manufactured memory modules and may increase the chance of miss-classification. Besides, a larger process variation may lead to a higher statistical variation among the memory pages from the same DRAM module. In such a case, we might need more randomly sampled memory pages (i.e., a larger value of $n$) to capture all architectural and manufacturing process variations of a DRAM module. The choice of $\lambda_{PPR}$ mostly depends on the quality of classifier. Fig. \ref{fig:lamda_overlap} shows that the distribution of $PPR$ from positive samples and negative samples have an overlapping region. In such case, it is not possible to select a $\lambda_{PPR}$ that creates a clear boundary between the positive samples and the negative samples. On the other hand, if the distribution of the $PPR$ is mutually exclusive (Fig. \ref{fig:lamda_nonoverlap}), selecting a $\lambda_{PPR}$ within the interval [$PPR_{neg,max}$, $PPR_{pos,min}$] will separate positive and negative samples. Therefore, the ideal goal should be, maximizing the separation between $PPR_{neg,max}$ and $PPR_{pos,min}$ for a suitable value of $\lambda_{PPR}$ during classification. As it is difficult/impossible to collect the negative class data that covers the whole distribution (discussed in Step 3), the $\lambda_{PPR}$ should be defined with the highest possible value (i.e., $\lambda_{PPR,op} = PPR_{pos,min}$). In our proposed scheme, the OEM should train a classifier $C_m$, corresponding to a specific memory class and make the classifier parameter public. Then, the user should choose random $n$ test pages from the memory module that is under test. The general information given with the classifier $C_m$ should enable the user to extract features form those selected pages. Then, for each of those $n$ test pages, the OEM/user should test the extracted features using the classifier $C_m$. If the $PPR$ (calculated from Eq. \ref{eqn:FPR}) is higher than the threshold $\lambda_{PPR}$, the memory module should be marked as authentic. Otherwise, it should be identified as a counterfeit one.

\begin{figure}[ht!]
\vspace{-3mm}
\centering
\captionsetup{justification=centering, margin= 0cm}
\includegraphics[width=0.35 \textwidth]{protocol2.pdf}
\caption{The proposed framework that is used to prove the authenticity of the origin of the DRAM manufacturer along with specification.}
\vspace{-3mm}
\label{fig:protocol}
\end{figure}

\begin{figure}[ht!]
\centering
\captionsetup{justification=centering, margin= 0cm}
\begin{subfigure}[t!]{0.38 \textwidth}
\includegraphics[width=\textwidth]{lamda_overlap.pdf}
\caption{}
\label{fig:lamda_overlap}
\end{subfigure}
~
\begin{subfigure}[t!]{0.43 \textwidth}
\includegraphics[width=\textwidth]{lamda_nonoverlap.pdf}
\caption{}
\vspace{-2mm}
\label{fig:lamda_nonoverlap}
\end{subfigure}
\caption{Selecting $\lambda$ for case- (a) when the distribution of $PPR_{neg}$ and $PPR_{pos}$ are overlapped, (b) when the distribution of $PPR_{neg}$ and $PPR_{pos}$ are mutually exclusive. }
\vspace{-3mm}
\label{fig:lamda}
\end{figure}

\section{Results and Analysis} \label{sec:result}
In our experiment, we have collected data from 25 commercial off-the-shelf single rank DDR3 SODIMMs (small outline dual in-line memory module) from 3 major DRAM manufacturers (see Table 1) \cite{DRAMmarketShare}. We have tagged the memory class based on the part number, the Garber version (reference PCB layout version \cite{DesignFile:JEDEC}), and the SPD \cite{JEDEC:SPD} data (see Table 1). Among the first six classes, we found at least one mismatch in their SPD data (detailed of SPD data is not presented in this article). On the other hand, the last two classes only differed by their PCB layout version and SPD version. From each memory module, we have collected data from all memory banks (each DRAM module contains eight banks). The testing platform has been implemented using a Xilinx Virtex ML605 evaluation board with SoftMC \cite{SoftMC:Hasan}. Data have been written and fetched from the DRAM memory module with two 32-byte data bursts. For all memory modules, we have observed error patterns below $7.5ns$ of \textit{Activation} time (the recommended \textit{Activation} time is in between $10ns$ to $15ns$ \cite{DDR3:JEDEC}). In this work, we have conducted our experiment with a $5ns$ of \textit{Activation} time which should be achievable by most of the system. In order to quantify the robustness of our proposed technique, we have evaluated our proposed method in four different operating condition- i) nominal voltage ($1.5$v) and room temperature ($\ang{25}$C) (NVRT), ii) high voltage and room temperature (HVRT), iii) low voltage and room temperature (LVRT), and iv) nominal voltage and high temperature (NVHT). For HVRT and LVRT, we have changed the input voltage ($V_{DD}$) by $\pm{1}$\% as most of the memory controllers limit the voltage ripple within $\pm{1}$\% \cite{TI:MemPower}. For NVHT, we have changed the operating temperature by $+\ang{15}$C from the room temperature.

\begin{table}[ht!]
\setlength{\tabcolsep}{0.5em}
\centering
\begin{tabular}{|c|c|c|c|c|c|}
\hline
\rule{0pt}{2ex} Manufacturer & \begin{tabular}[c]{@{}c@{}}Part\\ Name \footnotemark[2]\end{tabular} & \begin{tabular}[c]{@{}c@{}}Country\\ Origin\end{tabular} & Quantity & \begin{tabular}[c]{@{}c@{}}SPD-Garber\\ Version\end{tabular} & \begin{tabular}[c]{@{}c@{}}Class\\ tag\end{tabular} \\ \hline
\rule{0pt}{2ex} \multirow{3}{*}{Micron} & M1 & China & 2 & 10-C1 & 1 \\ \cline{2-6}
\rule{0pt}{2ex} & \multirow{2}{*}{M2} & Singapore & 3 & \multirow{2}{*}{10-B1} & \multirow{2}{*}{2} \\ \cline{3-4}
\rule{0pt}{2ex} &  & China & 4 &  &  \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{Samsung} & S1 & China & 1 & 10-B1 & 3 \\ \cline{2-6}
\rule{0pt}{2ex} & S2 & China & 1 & 11-B2 & 4 \\ \cline{2-6}
\rule{0pt}{2ex} & \multirow{2}{*}{S3} & China & 4 & \multirow{2}{*}{11-B2} & \multirow{2}{*}{5} \\ \cline{3-4}
\rule{0pt}{2ex} &  & Philippines & 3 &  &  \\ \hline
\rule{0pt}{2ex} \multirow{3}{*}{SK Hynix} & \multirow{3}{*}{H1} & Korea & 5 & 10-B1 & 6 \\ \cline{3-6}
\rule{0pt}{2ex} &  & China & 1 & \multirow{2}{*}{11-B2} & \multirow{2}{*}{7} \\ \cline{3-4}
\rule{0pt}{2ex} &  & Korea & 1 & & \\ \hline
\end{tabular}
\caption{Memory modules used in the data set.}
\vspace{-5mm}
\label{tab:dataInfo}
\end{table}
\footnotetext[2]{\textit{\textbf{M1:} MT4JSF12864HZ-1G4D1, \textbf{M2:}  MT8JSF12864HZ-1G4F1, \textbf{S1:} M471B2873EH1-CF8, \textbf{S2:} M471B2873GB0-CH9, \textbf{S3:} M471B5773DH0-CH9, \textbf{H1:} HMT325S6BFR8C-H9;\\\textbf{M1, M2, S2:} 1GB 1333MT/s, \textbf{S1:} 1GB 1066MT/s, \textbf{S3, H1:} 2GB 1333MT/s}}

Fig. \ref{fig:patterenDistribution} presents the spatial locality of failed bits in a randomly chosen page form each memory class at NVRT operating condition. From the scatter plot, we observe that the error pattern is different for different classes. Note that, the PCB layout version only differs class 6 and class 7 and the subtle difference is difficult to understand from the figure (Fig. \ref{fig:pageEachClass}). In Fig. \ref{fig:pageSameMemory}, we have presented the spatial locality of failed bits on two random pages from the same memory module of the same class. Although there is some similarity in their texture, the pattern is not consistent. The features extracted from these samples (as discussed in Sec. \ref{sec:method}) are still capable of separating these classes.

\begin{figure*}[ht]
\centering
\captionsetup{justification=centering, margin= 0cm}
\begin{subfigure}[t!]{0.5\textwidth}
\includegraphics[width=\textwidth]{pageAllClasslass.pdf}
\caption{}
\vspace{-1mm}
\label{fig:pageEachClass}
\end{subfigure}
~
\begin{subfigure}[t!]{0.18\textwidth}
\includegraphics[width=\textwidth]{randomPageSameModule2.pdf}
\caption{}
\vspace{-1mm}
\label{fig:pageSameMemory}
\end{subfigure}
\caption{(a) Spatial locality of failed bits from a randomly chosen page from each class, \\(b) Spatial locality of randomly chosen two pages from same memory modules.}
\label{fig:patterenDistribution}
\end{figure*}

From each memory page, we have extracted a total of 26 features as described in Sec. \ref{sec:method}. We have applied these 26 features directly to train and test the classifier. However, we have used the Linear Discriminant Analysis (LDA), a linear transformation \cite{LDA:Cunningham}, to provide the best visualization of the class separability. The LDA projects the data into a lower dimension feature-space by keeping the maximum separability among the classes. In the LDA, the lower dimension and the higher dimension features are linearly dependent. The data distribution in lower dimension feature-space is presented in Fig. \ref{fig:visualizing}. In this figure, we have only considered the most significant 5 dimensions ($\Phi_{1}, \Phi_{2}, \Phi_{3}, \Phi_{4},$ and $\Phi_{5}$) in the new feature-space that provides the maximum separability (explained variance). From the figure, we observe that each of the class forms a cluster in the feature space, which enables the separation of manufacturers.

\begin{figure*}[ht!]
\centering
\captionsetup{justification=centering, margin= 0.5cm}
\includegraphics[width=0.84\textwidth]{Visualize_8000page2.pdf}
\caption{Visualizing data in feature-space.}
\vspace{-3mm}
\label{fig:visualizing}
\end{figure*}

To demonstrate our proposed method, we trained one-class SVDD classifier (as discussed in Sec. \ref{sec:method}) for each class where we assume that the manufacturer does not have any prior knowledge of the memory modules from other class (See Sec. \ref{sec:ProbDef}). The classifier was only trained at NVRT operating condition, and the same classifier was used to test the data from other operating conditions. Training one class classifier is a more complex statistical problem compared to the multi-class problem. We used LIBSVM library to implement the one class classifier \cite{libsvm:chang}. For each class, we selected only one module to train the classifier (using 26 features from all pages collected at NVRT condition) and then tested all the pages from the rest of the 24 modules with the trained classifier with all operating conditions.

To validate our algorithm, we have chosen all possible combinations of training and testing data sets. In Table \ref{tab:result}, we have presented the result from the one-class classifier. The third, fourth, and fifth columns of the table represent the mean, the standard deviation, and the minimum $PPR$ from the positive samples for each classifier ($PPR$ is calculated from each test module). The sixth, seventh, and eighth columns of the table represent the mean, the standard deviation, and the maximum $PPR$ from the negative samples. For the ideal case, the $PPR_{pos}$ and $PPR_{neg}$ should be 100\% and 0\% respectively. The standard deviation for both cases should be 0\%. A larger gap between the $PPR_{pos}$ and $PPR_{neg}$ provides us the flexibility of choosing appropriate values of $\lambda_{PPR}$ and $n$ for identifying the origin of the manufacturers along with specification with high confidence (Sec. \ref{sec:method}).
Our silicon results provide a satisfactory difference between the $PPR_{pos}$ and $PPR_{neg}$, which can be further improved by learning statistical model with more positive samples and/or introducing negative samples. Table \ref{tab:result} also presents that a small change in voltage and temperature has a very insignificant effect on classifier performance. This is expected because a small change in voltage or temperature has a negligible effect on \textit{Activation} time. \cite{DRAMLatencyPUF:Kim, DRAMlatency:Chang, reducedVoltage:chang, runtimePerformanceDRAM:Chandrasekar}.

\begin{table}[ht!]
\captionsetup{justification=centering, margin= 0cm}
\setlength\tabcolsep{7pt}
\begin{tabular}{|c|c|c|c|c|c|c|c|}
\hline
\rule{0pt}{2ex} \rotatebox[origin=c]{90}{Class Tag} & \rotatebox[origin=c]{90}{\begin{tabular}[c]{@{}c@{}}Operating\\ Condition\end{tabular}} & \rotatebox[origin=c]{90}{$PPR_{pos, \mu}$} & \rotatebox[origin=c]{90}{$PPR_{pos, \sigma}$} & \rotatebox[origin=c]{90}{$PPR_{pos, min}$} & \rotatebox[origin=c]{90}{$PPR_{neg, \mu}$} & \rotatebox[origin=c]{90}{$PPR_{neg, \sigma}$} & \rotatebox[origin=c]{90}{$PPR_{neg, max}$} \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{1} & NVRT & 0.00 & 0.00 & 0.00 & 0.04 & 0.26 & 1.77 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & 0.00 & 0.00 & 0.00 & 0.03 & 0.20 & 1.37 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & 0.00 & 0.00 & 0.00 & 0.03 & 0.22 & 1.51 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & 0.00 & 0.00 & 0.00 & 0.05 & 0.31 & 2.08 \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{2} & NVRT & 99.07 & 1.16 & 95.40 & 0.00 & 0.02 & 0.17 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & 98.04 & 3.54 & 87.60 & 0.00 & 0.01 & 0.10 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & 99.09 & 0.98 & 96.49 & 0.00 & 0.02 & 0.19 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & 99.33 & 0.58 & 97.53 & 0.00 & 0.01 & 0.07 \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{3*} & NVRT & $-$ & $-$ & $-$ & 0.00 & 0.01 & 0.06 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & $-$ & $-$ & $-$ & 0.00 & 0.01 & 0.06 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & $-$ & $-$ & $-$ & 0.00 & 0.01 & 0.05 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & $-$ & $-$ & $-$ & 0.00 & 0.01 & 0.07 \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{4*} & NVRT & $-$ & $-$ & $-$ & 0.00 & 0.00 & 0.00 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & $-$ & $-$ & $-$ & 0.00 & 0.00 & 0.00 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & $-$ & $-$ & $-$ & 0.00 & 0.00 & 0.00 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & $-$ & $-$ & $-$ & 0.00 & 0.00 & 0.00 \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{5} & NVRT & 84.19 & 6.92 & 59.79 & 0.38 & 1.02 & 6.8 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & 84.74 & 7.16 & 59.31 & 0.41 & 1.10 & 7.19 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & 84.19 & 6.06 & 60.92 & 0.40 & 1.02 & 6.7 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & 82.56 & 7.63 & 57.00 & 0.38 & 1.03 & 6.96 \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{6} & NVRT & 90.29 & 9.31 & 69.58 & 1.58 & 4.16 & 25.91 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & 90.35 & 9.39 & 68.98 & 1.54 & 4.14 & 25.78 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & 81.98 & 9.49 & 69.74 & 1.69 & 4.52 & 28.65 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & 90.32 & 9.31 & 69.17 & 1.52 & 3.80 & 23.64 \\ \hline
\rule{0pt}{2ex} \multirow{4}{*}{7} & NVRT & 73.81 & 10.46 & 66.41 & 1.56 & 4.73 & 21.72 \\ \cline{2-8}
\rule{0pt}{2ex} & HVRT & 74.22 & 9.36 & 68.11 & 1.61 & 4.91 & 22.98 \\ \cline{2-8}
\rule{0pt}{2ex} & LVRT & 71.55 & 14.67 & 61.18 & 1.56 & 4.75 & 21.19 \\ \cline{2-8}
\rule{0pt}{2ex} & NVHT & 76.01 & 6.53 & 71.39 & 1.53 & 4.72 & 22.15 \\ \hline
\end{tabular}
\vspace{1ex}
\rule{0pt}{2ex} {\raggedright *For class 3 and class 4, we have only one sample which is used to train the statistical model. There is no positive test sample left for these two classes.}
\caption{Results from the one-class classifier.}
\vspace{-6mm}
\label{tab:result}
\end{table}

\textbf{A suspicious DRAM module:} \label{subsec:suspiciousModule}
From the results shown in Table 3, for class 1, we observe that the $PPR_{pos}$ is 0\% (the ideal $PPR_{pos}$ is 100\%). Note that we have two samples available for this class: one is used for training, and another one is for testing. Therefore, we suspect that one of them is counterfeit. Fig. \ref{fig:M1_justify_page2} presents the spatial locality of failed bits from 2 random pages from those two samples. The results show that they have distinct FBC properties. Furthermore, the dissimilarities found in visual inspection (Fig. \ref{fig:M1_justify2}) suggests that one of them might be counterfeit (i.e., from a fake manufacturer). The layout difference between these two modules suggests that the reference layout version should be different for these two modules. However, the reference layout version is described as `C1' on both modules' label. From the SPD data, we have found that the reference raw card (i.e., layout) version is specified as `C' (which represents- `C0', `C1', `C2' etc.) for both modules. For further investigation, we have checked the layout provided by the JEDEC \cite{DesignFile:JEDEC} and found that the second module layout version is `C2' instead of `C1' (as shown in Fig. \ref{fig:M1_justify2}). Therefore, we conclude that the second module is either from the fake manufacturer or mislabeled (with layout version `C1').

\begin{figure*}[ht]
\centering
\captionsetup{justification=centering, margin= 0cm}
\begin{subfigure}[t]{0.245\textwidth}
\includegraphics[width=\textwidth]{M1_justify_page2.pdf}
\caption{}
\label{fig:M1_justify_page2}
\end{subfigure}
~
\begin{subfigure}[t]{0.50\textwidth}
\includegraphics[width=\textwidth]{M1_justify2.pdf}
\caption{}
\label{fig:M1_justify2}
\end{subfigure}
\caption{(a) Spatial locality of erroneous bits of 2 random pages of each sample from Class 1, \\ (b) Visual appearance of each sample from Class 1 (Module 2 is suspicious).}
\vspace{-3mm}
\label{fig:M1_justify}
\end{figure*}

\section{Limitations and Future Work} \label{sec:futureWork}

Our proposed method can be used to detect various counterfeit types. However, the proposed work cannot identify overproduction from the same foundry \cite{CSST_Rahman}. In the future, we will extend our technique for other volatile and non-volatile memory chips (e.g., flash memory, SRAM, etc. \cite{SRAM_rahman, flash_rahman}). Selecting a robust set of features to improve the accuracy might be another direction of our current research. In such a case, we might need to use more than one entropy source to capture a better variance among classes. In this article, we have only used data error obtained at the reduced activation latency.

Since our current work only exploits the learning ability of a one-class classifier, we will explore additional machine learning techniques, such as ensemble learning and classifier fusion, for improved generalization across a broader set of manufacturers in future work. We will also explore additional features and filtering, wrapper, and embedded feature analysis techniques to better understand the impact of each feature on identifying a DRAM manufacturer.

\section{Conclusion} \label{sec:conclusion}
In this paper, we proposed a simple non-invasive and low-cost scheme for identifying the origin of a DRAM manufacturer and verifying individual DRAM's specification. The proposed method exploits the DRAM latency variations to capture the architectural, layout, and process variations. At first, we chose the most appropriate features from the DRAM signature, and then we used a one-class classifier to verify the memory class without knowing the information from other classes (i.e., other manufacturers).

\section*{Acknowledgment}
This work was supported by the National Science Foundation under Grant Number CNS-1850241. We would like to thank UAH for filing patent, UAH reference: UAH-P-18038.

redpajama_set_name: RedPajamaArXiv


text:
Infield flop rules
Roger Ebert March 23, 2006
Michael Keaton has a gun in "Game 6."
Michael Keaton is a talker. His strength as an actor is in roles that position him on the scale between literate and glib; even in the wonderful lost film "Touch and Go" (1986), where he played a pro hockey player, he spoke like one who had a novel in him. In "Game 6," he plays a playwright and talks like one, taking pleasure in choosing specific words to evoke exactly what he means. He is also a Boston Red Sox fan, and when the opening night of his new play coincides with the sixth game in the 1986 World Series, he has a lot to talk about: "I've been carrying this franchise on my back since I was 6 years old."
The original screenplay is by the novelist Don DeLillo, and it involves subjects (or obsessions?) he used in his novels Underworld (1997) and Cosmopolis (2003). From the first comes expertise on baseball, pitched somewhere between torch songs and Greek tragedy. From the second comes the Manhattan gridlock and the undercurrent of danger and violence in the streets. The playwright, named Nicky Rogan, abandons a cab after an exploding steam pipe sprays asbestos into the air, and retreats into a bar where he finds an old friend and fellow playwright, Elliot Litvak (Griffin Dunne). Because it is Nicky's opening night, they talk about a critic they both hate; Elliot believes this man destroyed his life, and indeed seems to be entering madness.
This is DeLillo's first produced screenplay, but he has written for the stage, and perhaps his portrait of Steven Schwimmer (Robert Downey Jr.), the detested critic, is drawn from life. I can think of a candidate. Schwimmer has written such lethal reviews of plays that he lives in hiding, is forced to attend opening nights in disguise, and goes to the theater fully armed. Elliott speaks of him in wonder: "I opened a one-act play at 4 a.m. in the Fulton Fish Market. In the rain. For an audience of fish-handlers. Schwimmer was there."
In addition to his fears about opening night and his premonition that the Red Sox will once again destroy his dreams, Nicky is facing personal problems. While one of his cabs was stuck in traffic, he saw his daughter Laurel (Ari Graynor) in another one; visits between cars stuck in traffic are also an Underworld theme. She informs him her mother is divorcing him: "She says daddy's demons are so intense, he doesn't even know when he's lying." There is consolation in an affair he's having with an investor in his play (Bebe Neuwirth), but not much.
Writers find strange connections in their days and lives; they generate wormholes that connect people. How else to explain that one of the taxi drivers "used to be head of neurosurgery in the USSR," and the star of his new play (Harris Yulin) can't remember his dialogue because he has, the director says, "a parasite living in his brain." Yulin's character has a painful rehearsal where he fails again and again to remember the line that has just been repeated to him.
This material could be pitched at various levels. You can imagine it being incorporated into a sequel to "The Producers," or being transformed into quasi-O'Neill. Keaton, DeLillo and director Michael Hoffman make it into a celebration of spoken language; we're reminded that Hoffman directed "Restoration" (1995) and the 1999 "Midsummer Night's Dream." After the Sundance opening of "Game 6," I wrote: "DeLillo's dialogue allows for a complexity and richness of speech that is refreshing compared to the subject-verb-object recitation in many movies." Such dialogue requires an actor who sounds like he understands what he is saying, and Keaton goes one better and convinces us he is generating it. Life for him is a play, he is the actor, his speech is the dialogue, and he deepens and dramatizes his experience by the way he talks about it. Certainly what he says about the Red Sox has a weary grandeur.
Robert Downey Jr., whose troubles of a few years ago were well documented, has come back with a vengeance; his career is ascendent, and since "Game 6" was finished in 2005, he has made 10 other movies, ranging from "Good Night, and Good Luck" to "The Shaggy Dog," and that's some range. Here he makes the critic Schwimmer into a study in affectation, a little Buddhist, a little loony, a little paranoid, a little fearless. Griffin Dunne, who also produced the movie with his filmmaking partner Amy Robinson, plays the disintegrating playwright Elliot as a man halfway between barroom philosopher and dumpster-diver. And for Nicky, everything comes down to which is more important: Success for his play, or the Red Sox winning Game 6? Talk about backing yourself into a lose-lose situation.
Sports Film
Tomris Laffly
Small Axe: Education
Godmothered
Nick Allen
Game 6 (2006)
Rated R for some language and sexuality
Michael Keaton as Nicky Rogan
Robert Downey Jr. as Steven Schwimmer
Griffin Dunne as Elliot Litvak
Ari Graynor as Laurel Rogan
Catherine O'Hara as Lillian Rogan
Bebe Neuwirth as Joanna Bourne
Shalom Harlow as Paisley Porter
Roger Rees as Jack Haskins

redpajama_set_name: RedPajamaCommonCrawl


text:
Home / News / Crime & Justice
Montana man brings down Ten Commandments monument with chain and a pickup truck, arrested
Anthony Weimer was booked into jail and charged with a felony criminal mischief following the incident that took place in Kalispell
By Ishani Ghose
Updated On : 22:15 PST, Jun 28, 2020
Anthony Weimer (Flathead County Sheriff's Office)
KALISPELL, MONTANA: Montana Police have arrested a man who they believe pulled down a courthouse Ten Commandments monument using a chain and a pickup truck.
According to reports, the accused, Anthony Weimer, was booked into jail and charged with a felony criminal mischief following the incident that took place in Kalispell, KHQ revealed. The authorities shared that they had responded to callers who reported seeing a man wandering around the grounds of the Flathead County Courthouse. The callers saw the accused attach a chain to a pickup truck before taking down the monument, NY Post reports. The police were able to locate the truck and find the suspect and arrest him. The authorities said they do not know what provoked the act.
As reported by the Associated Press back in 2011, the Kalispell City Council had been asked to take possession of the monument in addition to six others, which included some historical texts from the Bill of Rights and Declaration of Independence. The monuments formed a 'cornerstone of law' display. The council declined, fearing a lawsuit on First Amendment separation of church and state grounds. It is also reported that the Fraternal Order of the Eagles had handed the Ten Commandments statue over to the Flathead County in 1950. It was then placed outside the courthouse. The group then took possession of the monument again in 2011 when the monuments had become the target of a legal challenge. The monument was eventually moved to the southwest corner during a courthouse renovation.
Recently, POTUS Donald Trump signed an executive order on June 26 to protect federal monuments after several incidents involved vandalism of statues. Trump took to Twitter to say, "I just had the privilege of signing a very strong Executive Order protecting American Monuments, Memorials, and Statues — and combatting recent Criminal Violence. Long prison terms for these lawless acts against our Great Country!"
The order that was signed by Trump reinforces the already existing federal law that criminalizes the destruction of federal monuments. The Veteran's Memorials Preservation and Recognition Act of 2003 looks to impose a fine and 10 years in prison on anyone who vandalizes a monument. According to the order, "Individuals and organizations have the right to peacefully advocate for either the removal or the construction of any monument. But no individual or group has the right to damage, deface, or remove any monument by use of force." The order also threatens to withhold federal funding from state and law enforcement agencies who "fail to protect monuments, memorials and statues".
We had earlier shared that Trump took to Twitter on June 23 to announce that anyone who vandalizes public statues could face 10 years in jail. "I have authorized the Federal Government to arrest anyone who vandalizes or destroys any monument, statue or other such Federal property in the US with up to 10 years in prison, per the Veteran's Memorial Preservation Act, or such other laws that may be pertinent." He added, "This action is taken immediately, but may also be used retroactively for destruction or vandalism already caused. There will be no exceptions!"
If you have a news scoop or an interesting story for us, please reach out at (323) 421-7514


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Home / Headline News / Gang of Youths unveil new single "in the wake of your leave"
Photo by: Ed Cooke
Gang of Youths unveil new single "in the wake of your leave"
John Hutchings 2 weeks ago	Headline News, News, Single Leave a comment
Gang of Youths ended 2021 with a bang, returning to late night TV with their performance of "the angel of 8th ave." on The Late Show with Stephen Colbert as well as a run of sold out shows overseas. Now the band again pick up the pace for a huge year ahead by sharing their new single "in the wake of your leave." The track is the latest to build momentum ahead of the release of their highly anticipated new album angel in realtime. on February 25th.
Collectively, angel in realtime. charts the waves of emotions that flooded over frontman Dave Le'aupepe following the loss of his father. Overwhelmed, Le'aupepe uses songwriting as an eloquent and poignant outlet for his grief. "in the wake of your leave" converts sorrow into a song that burns with life-affirming, passion – from its exuberant rush to its bright, colossal melodies and its addictive, radio-friendly hook. And in one of the band's most striking hallmarks, it still shimmers with a remarkable attention to detail: the elegiac backing harmonies of the Auckland Gospel Choir; the percussion provided by a collective of drummers from the Cook Islands.
Of the song, Dave Le'aupepe says, "I wanted to reflect on how I became dependent on grief for solace and inspiration. The cycle from numbness to acceptance to yearning plays a role in my approach to grieving my dad's death. As a result, most of the time, I feel a bit futile as a person."
The album's conceptual themes are amplified by Gang of Youths' ever more ambitious musical approach. Their influences range from American minimalism and contemporary classical, to drawing upon the legacy of Britain's alternative/indie scenes, such as drum 'n' bass to the most transcendent moments of Britpop. It's equally rooted in Le'aupepe's Polynesian heritage, featuring samples from David Fanshawe's recordings of indigenous music from the Polynesian islands and the wider South Pacific, as well as contributions from a cast of talented Pasifika and Māori vocalists and instrumentalists.
angel in realtime. is available to pre-order here. Formats include digital, double white vinyl and CD, while HMV and select independent stores offer a special edition of the vinyl which feature an alternate cover. Gang of Youths recently filmed live versions of album track "the man himself" as well as fan favorite "Magnolia" from the band's 2015 debut album, The Positions. Gang of Youths recently announced a North American tour in April and May ahead of summer festival season.
About John Hutchings
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Marian Goodman Gallery is delighted to present the first exhibition in our New York space of the work of Indian artist Amar Kanwar.
The artist will present two multi-channel installations, The Torn First Pages, 2004-2008 and The Lightning Testimonies, 2007, both of which will have their New York premiere in this exhibition.
Born in 1964 in New Delhi where he lives and works, Kanwar has distinguished himself through films and multi-media works which explore the politics of power, violence, sexuality, and justice. His multi-layered installations originate in narratives often drawn from zones of conflict and are characterized by a distinctly poetic approach to the social and political. In retracing history through images, ritual objects, literature, poetry and song, Kanwar creates lyrical, meditative film essays that do not aim to represent trauma or political situations as much as to find ways through them. Kanwar's work looks deeply into the causes and effects and how they are translated into everyday life and cultural forms.
"Imagine the formal presentation of poetry as evidence in a future war crimes tribunal. Imagine nineteen sheets of paper floating forever in the wind…"
-- Amar Kanwar, on "The Torn First Pages"
The Torn First Pages (2004-2008), a 19-channel film installation in three parts that will be on view in the North Gallery, is presented in honor of the Burmese bookshop owner Ko Than Htay who was imprisoned for 'tearing out the first page' of all books and journals he sold and which contained ideological slogans from the Burmese military dictatorship. The Torn First Pages is also an ode to the thousands engaged in the struggle for democracy in Burma, following the paths of Burmese activism in exile. The films directly, elliptically and metaphorically encounter resistance and the struggle for a democratic socity, contemporary forms of non violence, political exile, memory, and dislocation.
The Torn First Pages, jointly commissioned by TBA21, Vienna and Public Press, New Delhi, was previously exhibited in its completed form at Haus der Kunst, Munich, in the exhibition A Question of Evidence at TBA 21, Vienna and as a work in progress at the Stedelijk Museum, Amsterdam (in 2008). This is its first presentation in the U.S.
The 8-channel video installation The Lightning Testimonies (2007) will be presented in the South Gallery and reflects upon a history of conflict in the Indian subcontinent through experiences of sexual violence. "The Lightning Testimonies" creates an experience that emerges from a constellation of eight synchronized choreographed projections with sound tracks that lead to disparate narratives that then converge into a single projection. As the stories unfold, women from different times and regions come forward. The multiple projections speak to them directly, in an effort to understand how such violence is resisted, remembered and recorded by individuals and communities.
In this exploration, multiple stories are revealed, sometimes in people, images and memories, and at other times in objects from nature and everyday life that stand as silent but surviving witnesses. Submerged narratives appear, disappear and are then reborn in other permutations at another time. Using a range of visual vocabularies, The Lightning Testimonies transports us beyond the realm of suffering into a space of quiet contemplation, where resilience creates the potential for transformation. The work premiered at Documenta 12, Kassel (2007) and was seen in Reflexions on Contemporary India, Casa Encendida, Madrid (2008) and Indian Highways, Serpentine, London and Astrup Fernley, Oslo (in 2008-2009). This is its first presentation in New York. Lightning Testimonies was made with the support of the Ford Foundation, New Delhi; Documenta 12, Kassel, Germany; and Thyssen-Bornemisza Art Contemporary, Vienna.
Amar Kanwar is the recipient of the 1st Edward Munch Award for Contemporary Art, Norway (2005); an Honorary Doctorate in Fine Arts, Maine College of Art, Portland, ME; the MacArthur Fellowship in India, the Golden Gate Award, San Francisco International Film Festival.
Projects in 2010 include new Artists Cinema commission which will be launched at a special preview evening at Tate Modern on April 16th, 2010; a group exhibition Being Singular Plural: Moving Images from India, upcoming at the Deutsche Guggenheim Berlin in June; HEART Herning Museum of Contemporary Art, Herning, Denmark; Signs of Life, Kunstmuseum Luzern, Switzerland. His work is included in the current Contemplating the Void: Interventions in the Museum, Guggenheim Museum, New York.
Solo exhibitions of Kanwar's work have been seen recently at: Film Huis den Haag, The Hague, Netherlands (2009); Haus der Kunst, Munich; Stedelijk, Amsterdam and Hertogenbosch, The Netherlands; Galerie Marian Goodman, Paris (all 2008); Whitechapel Art Gallery, London (2007);Apeejay Media Gallery, New Delhi (2007); National Museum of Art, Architecture and Design, Olso (2006); Fotogalleriet, Oslo (2005); The Renaissance Society, Chicago (2004); and Tensta Konsthall, Stockholm (2003).
A selection of group exhibitions include Significant and Insignificant Events, Museum of Modern Art, Istanbul (2009); What a Wonderful World , Goteborg International Bieannial for Contemporary Art, Goteborg City Museum (2009); Indian Highway, Serpentine Gallery, London and Astrup Fernley Museum, Oslo (2008-2009); Thyssen Bornemisza Art Contemporary, 2008; The Greenroom: Reconsidering the Documentary and Contemporary Art (Part 1), The Hessel Museum and Centre for Curatorial Studies, Bard College, NY (2008); Documenta 11 and 12, Kassel, Germany (2002 and 2007); Zones of Contact, Museum for Contemporary Art, Biennale of Sydney (2006), Australia; and Image War: Contesting Images of Political Conflict, Whitney Museum of Art, NY (2006).
Please join us at the opening reception on Tuesday, March 16th, from 6 – 8 pm.


In this verse, Jesus points out the problem. He explains that there are so many people living without hope, and so few who are willing to share the gospel with them. Often, we get too caught up in the chaos of our busy schedules, and forget our true mission – to share the good news of Jesus Christ with those who are hurting and without hope. Take some time today to pray that God will break our hearts over those who are lost and give us an overwhelming desire to see them come to know Jesus as their personal Lord and Savior.
WHEN LIFE IS HARD…COUNT YOUR BLESSINGS!
The telephone rang. "Hello," I answered. My daughter–in-law Leigh was on the other end of the call. "Nana, are you busy?" She always asks that question when she calls. Of course, I rarely answer her with the truth … I'm always busy. But, not too busy to talk to my girls. Girls. It took 25 years before a girl joined this testosterone, male dominated family of ours; 31 years to have a female born into it—our first granddaughter, Natalie.
Because of mission trips, writing deadlines and ministry business, I hadn't been able to spend much time with the grandchildren for a couple of months. Lonely for them, I was afraid they were feeling like second fiddle—neglected for The Cause. That concern always brings conviction to my heart—that I'd let ministry duties get out of balance.
Mothers and Grandmothers do that sometimes. We get busy with Important Stuff. Good Stuff. Jobs, church work, ministry, volunteer causes, hobbies, walk-a-thons—whatever. Before you know it, we're over-committed. And tired. And cranky. And forgetful. And if we don't stop the process, our family relationships will suffer.
Family. After our relationship with God, it's our first priority. It's our most important blessing. God meant family to be the foundation of our lives on earth, not a sideline thought. He created family to be the foundation—the glue of society. When we cease to put Him and Them first, our whole lives get out of whack.
So, I listened closely to Leigh to see if my suspicions were correct. Was I going to get an invitation to lay down my responsibilities in ministry to serve my family and fellowship with my precious grandsons, Asher and Mason? Ah, but wait! Serving our family and fellowshipping with them IS ministry! Our most important one!
"Yes! Now, what will we do those days?" I thought.
Join us tomorrow as the planning, and the joy … begins!


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Venue: Richmond Park
O'Malley, Bermingham (Greene h/t), Desmond (Browne h/t), Rooney, Hannigan (Gannon h/t); Forrester (Langley h/t), Brennan (Bayly), Bolger (Chambers h/t), Verdon (Morris h/t), Byrne (Markey h/t); McGrath (Gudje h/t).
O'Brien; Tattum, Oliver, Plummer, Smith-Brown, Kongolo, Intima, Glendon, Faupala, Celina, Nemane
Referee: Rob Harvey
St Patrick's Athletic 3 - Manchester City EDS 2
The Manchester City Elite Development Squad will travel to Dublin this Wednesday, July 29th to take on St Patrick's Athletic.
Team manager Patrick Vieira, a veteran of Man City, Internazionale, Juventus and Arsenal, brings his charges to Richmond Park to take on the Super Saints, managed by Liam Buckley who has his own impressive European pedigree, having played in Belgium, Spain and Switzerland during an illustrious career.
Everyone through the turnstiles on the night will be entered into a raffle to win a signed Manchester City jersey and one lucky person will be going home with a sky blue shirt bearing the signatures of some potential starts of the future.
The last Premier League side to have faced the Saints in Richmond Park were a Chelsea XI in 2009 that featured the likes of Fabio Borini, while a Tottenham Hotspur side with Gareth Bale, Dimitar Berbatov and Robbie Keane amongst their ranks were visitors to Inchicore in 2007.
Two days after the Man City friendly St Pats take on Galway United in the SSE Airtricity Premier Division.
The Saints have enjoyed six straight wins in the league and, following the disappointment of their UEFA Europa League exit, are keen to continue their impressive domestic form in order to finish in the top three to qualify for European football again next year.
"The friendly against Man City will be the perfect opportunity to prepare for the league match against Galway, and hopefully we can entice a few people down to Richmond Park who have never been before" said Liam Buckley.
"Patrick Vieira has assembled an exciting squad of players but we have our own stars of the future here too, so I'm really looking forward to what should be a great occasion".


Home » Blog » I Promise . . .
I can't begin to explain how many times I've made promises I couldn't keep. At one point in my life, promises were so frequent that I knew before I finished my oaths that I wouldn't succeed in keeping them. It's awkward to have a friend, loved one, fellow christian shun you because you've failed them. Again. You're embarrassed when you come face-to-face with those you've made promises to. Your eyes meet for a moment, but the pain and anger behind their eyes linger long after you part.
You find it hard to sleep at night. You kick the dog, yell at the children, burn your dinner, leave work assignments incomplete, irritate your spouse. All because of your guilt. It eats away at you. Apologies burn the edges of your lips, but you can't find the courage to expose your wrong. How many times will you trick yourself into believing there's no way people you've wronged will remember what you had promised to do? But deep in your gut you know they remember. You can see it in their eyes. You can feel it as they come ever nearer to you.
God made a promise to Abraham. The promise didn't depend on Israel's faithfulness. God made an oath and kept it. When things got way out of hand, God punished Israel and made them wander in the desert for 40 years. Later, when they continued to disobey him, he had other nations enslave them. He constantly reminded them that he is the Lord God (Deuteronomy 4:32-40) and that they should keep his commandments. But not once did he ever say he'd renege on his promise. They would inherit the land just as he promised even if it was a generation or two later.
Too often you and I can't see past our next 24 hours before we're bombarded with the what ifs of this life. We stack one task after another onto our plate and refuse to use our common sense to say "no" when we can't do any more. What if the musician doesn't show up for the school play? Ever thought about going a capella? The kids know the words to the song. They've sung it a thousand times.
Some of us are just—can I be blunt here?—lazy. We hide behind our hurt and refuse to do anything for anyone. We've been wronged. And we can't get over it. Someone somewhere made a promise and didn't keep it.
Others use godly ministries as a springboard to success—to build our resumes so we can prove worthy. Our interchange with one another is driven by this self-inflicted pressure. This pressure determines our way of speech, our out-of-character friendliness, our dismissive behavior toward those of lesser stature. We want to look important; to out-do the next fellow; to be known as the one people seek for advice, leadership, love, and benevolence.
The god in your life has become an earthly tabernacle of greed; a self-serving ministry.
To get rid of this stigmatism that you've created for yourself, you continue to take on more and more work that you can't possibly fulfill.
I would suggest you delegate the work to others, but even that becomes part of your power-hungry struggle to feel important. Bossing others around is the perfect fuel for your self-serving ministry, don't you think?
It's time for you to stand still and recall each and every infraction made against your brother. You might ask: "Won't this overwhelm me?" Of course it will. But you'll also begin to experience some of the pain others feel over your inability to keep your word.
Trust is the most sacred thing among men. Long ago, to seal a transaction, all two men had to do was shake hands. Try doing that today?
People trust and respect those who keep their word. People will give their last meal, last coat to those who keep their word.
A promise is all Jesus had before he made the ultimate sacrifice. Jesus relinquished ALL control and trusted God to raise him from the dead. And God kept his promise. After being enslaved for many years, the prophets reminded Israel what they must do to gain God's favor. Without hesitation, they knew God would keep his word. How did they know? They remembered how God gave birth to a nation out of a nation (Deuteronomy 4) and brought them to a land flowing with milk and honey. They remembered the ten plagues; the pillar of cloud by day and fire by night. They remembered . . .
And we hold on to these promises whether we remain in this life or not.
When a man and woman marry, they made a promise to stay together until death separates them. When either party breaks this vow, there is a brokenness beyond words that forever hovers over them. And so it is with those with whom you've made promises.
Tell me again how many promises you have broken?
When you promise to buy your child a uniform, save money for her college education, take him to a baseball game, or attend her school function, you are exposing who you really are. If you keep your word, you gain favor and respect from your child. If you don't, the trust is broken. Perhaps forever. Before long, not only can't your child depend on you, your employer can't depend on you either. Neither can your spouse, your family, or your neighbors.
Then the walls of your self-serving ministry collapse. You are left wondering who is to blame.
If only I hadn't made all those promises . . .
I promise to never make another promise again.
But didn't you just break the very promise you vowed not to make.
If you'll stand still for a moment and go through all the broken promises, how do you think you'll feel? Can you possibly feel any worse than the person with whom you made the promise? No. But you can come close. No one feels good after going back on his word. Though it's unfortunate, everybody loses. No one is left untouched.
The person to whom the promise was made is angry.
Those that witness the guilt and hurt lose trust.
Children learn to look at this despicable sin as normal.
Always be in prayer, about everything.
If you've been overwhelmed with too many commitments, ask God for relief. The moment someone comes up to you, or calls you on the phone and says they've given someone else the job, don't become bitter or angry because you wanted the job for yourself. Know that it's an answer to your prayer and glorify God all the more.
By dcomeaux in Blog, Religion on January 7, 2015 .


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Jama Zehi Kuh Dim (, also Romanized as Jamā Zehī Kūh Dīm; also known as Faqīr Moḩammad Bāzār) is a village in Polan Rural District, Polan District, Chabahar County, Sistan and Baluchestan Province, Iran. At the 2006 census, its population was 239, in 39 families.

References

Populated places in Chabahar County

redpajama_set_name: RedPajamaWikipedia


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Home » Celebs, Aiming for Runway Riches
Celebs, Aiming for Runway Riches
By Rosana|2022-01-11T19:20:12+00:00October 14th, 2014|Events|
Veteran style scribe Teri Agins has covered the business and the buzz of the fashion world for more than two decades at the Wall Street Journal, where she pens the popular Ask Teri column. Known for her incisive commentary on everything from couture trends to marketing mishaps, she just wrote a new book, "Hijacking the Runway: How Celebrities are Stealing the Spotlight from Fashion Designers" ($28, Gotham Books).
It catwalks through the trend toward actors and singers morphing into fashion entrepreneurs, delving into the good (the Olsen twins superlative, simple garments for The Row), the bad (Lindsay Lohan as a brand ambassador for Ungaro) and the just plain bizarre (there are dozens of Paris Hilton accessories shops in the Middle East and South America). We chatted with her about the star-studded read just before she appears in DC October 20 to chat about it with Washington Post fashion reporter Robin Givhan at Mazza Gallerie
Why did celebrities get so interested in fashion?
Blame it in on the internet! It created all these new media channels that needed to be filled with information. It made celebrities get bigger and bigger, and they started to say, 'Hey, I can be a designer too! I'm an arbiter of taste, and I have an army of social media followers.'
Isn't a lot of it about money, too?
Yes — the bigger issue is that famous people are trying to find ways to monetize their fame. They've been robbed of money by reality shows, and there are no more $20 million paydays in movies. So if you are somebody famous, you want to get paid for your fame.
Some celebs just dabble in fashion, but what about the ones who really become known for it, like the Olsen twins or Victoria Beckham? What are they doing differently from say, Lindsay Lohan or Justin Beiber with his cologne?
The difference is they are doing it full time — it's not just something on the side. Fashion is a full time job. And with The Row, the Olsen girls really found white space. They knew there was a critical mass of affluent women who wanted really cool basics — the perfect leather leggings, a perfect T-shirt.
What happens if celebrities do an endorsement or a deal, and it doesn't turn out well? You talk about a collaboration between the Kardashian sisters and Sears that ended up being pretty dismal.
Well, I don't think it hurt their brand. And the last time I checked they were doing another collection for kids with Babies R Us (Kardashian Kids ). So yes, the product was kind of shabby at Sears, but the Kardashians brought in eyeballs to look at Sears like never before. None of those girls would've walked into Sears unless it was to buy a grill or washing machine. So that did work. It got people in the door.
The book also talks about how traditional designers — Michael Kors, Tom Ford — have realized they, too, have to be celebrities to sell their clothes. Why is that key?
I think Michael Kors is a great example — he was an immediate impact on his business after joining "Project Runway." He went on it hoping to make some noise, and he suddenly had a young group of adoring fans. Now most of these designers are savvy — they know they have to have a celebrity factor in their wheelhouse. It's about getting people to care about them and see them as a person.
You talk a lot in the book about how we're a dress-down nation now. How has that changed fashion?
Dress down nation happened when dress codes went away in the late 1990s. It meant people were spending less money on clothing, because casual wear doesn't go out of style quickly, and it isn't expensive. And the fashion industry had to figure out how to keep people buying. So they created expensive handbags and zeroed in on shoes. And in turn, you know see celebrities like Sarah Jessica Parker with their own accessories lines.
To hear more from Teri Agins next Monday, purchase tickets for her Washington, DC event online .
Post by DC Style Factory stylist, Jenn Barger. Jenn has 13 years' experience working as a fashion journalist in the nation's capitol. Her DC Style Factory clients include professional Washingtonians looking to add unusual, funky pieces to their classic DC wardrobes. She specializes in vintage shopping and is an expert in combining pieces with history with new, modern looks. Email dcstylefactory@gmail.com to work with Jenn.


Public transport in London usually works well, and paying is a breeze with an Oyster card or Contactless. However, you might end up paying hundreds of pounds in error… but there's a way to get those back.
Generally speaking, I love public transport services in London. Sure, they're often over-crowded, the heat in the summer is awful, and the constant weekend engineering works are annoying. But even when you consider all the issues and problems – it still WORKS. You get from point A to point B, and you can always find a way around when things go wrong.
And if that's not enough – you might be paying WAY MORE than you should, because of erroneous "incomplete journeys". In fact, many, many people are – in the first half of 2018, there were reportedly £28.8million in incomplete journey charges.
Sadly, I was part of that number. When I learned how to check for incomplete journeys, I found out my household gets them almost EVERY WEEK. Even on a modest estimate of twice a month, that's a potential loss of almost £200 that I'm being mistakenly charged for.
Incomplete Journey Charges – What Are They?
How Can I Get Refunded For Incomplete Journeys?
When you travel on the Tube, DLR, London Overground, TfL Rail, National Rail or the Thames Clippers River Bus, you need to TAP IN with your Oyster or bank Contactless card at the start of your journey, and then TAP OUT at your last stop (On a bus, you only tap IN).
However, if you fail to tap in, OR tap out – for whatever reason – the automatic systems don't know how to calculate the cost of your journey. So they charge you the Maximum Charge (£8.00 in Zones 1-9) for that journey, which is often not the correct charge.
For example, let's say you travel from Bank Tube Station to the Sheperd's Bush tube station. It's just one tube line (Central), and should cost £2.90 during peak times and £2.40 off-peak.
So you TAP IN at Bank, but then – Oh No! – the gate at Sheperd's Bush is broken and you can't TAP OUT. The tube workers let you out, but you haven't tapped your Oyster (or Contactless).
Now, Transport for London's (TfL) computers know where your journey began (Bank) but they have no idea where your journey ended (Sheperd's Bush). So as far as they're concerned, you might have travelled to Upminster and should have paid £5.10. Or maybe you spent the whole day travelling back and forth without tapping out… Anything can happen!
So what do the computers do? They charge you the maximum amount – which is the Pay as You Go daily transport cap, which currently stands at £8.00.
And the same thing happens if you don't TAP IN – so let's say the card reader was broken at Bank. You tap OUT in Sheperd's Bush, so the computers know where your journey ended – but again, they don't know where it began. So it's £8 again, and you just lost £5.1.
But wait, you might say – if the card reader is broken, I'll see that, right? And I'll know to ask for my money back, right? Well – not necessarily. In many cases, you might not tap in or out correctly – and not even be aware of it, because everything seemed fine.
Plus, there's always the possibility of you simply forgetting to tap in or out. Many stations (especially train stations) do not have gates – they have stand-alone card readers, and you need to remember to tap them before you leave (or enter) the station.
Open an account and register your Oyster card and your Contactless card (if you use it for travelling) on TfL's website.
Do note that when you register a new card, you'll have to give details about your last journey with that card (within the past 8 weeks), for security reasons. So if you haven't used your card yet – do it, and register on the next day.
Once you have a TfL account, you can view your public transport journey history (both on your Oyster and Contactless, if you use both), and make sure there are no errors.
I check that website at least once a week. For me (or more accurately, for my husband, who travels more) there are errors there at least once or twice a month – and sometimes more often than that.
Automatic Refund: In some cases, the automatic systems recognise the error (mostly when you forgot/couldn't touch out), and it will be shown prominently on the first screen. When that's the case, you can then ask for a refund directly via the website.
You will be asked to supply details about the missing information – where was it that you left (or entered) the station, and why didn't (or couldn't) tap out – you forgot, the card readers were broken, etc'.
Then, if the details are correct, you will get the refund back automatically, by tapping your Oyster on a valid card reader within a couple of days.
You can use the automatic refund up to three times a month and within 8 weeks of the journey.
Manual Refund – Unfortunately, the automatic systems often fail to recognise the erroneous charges, so it'll be up to you to check.
Go into "View Journey History" within your account, and you will be able to see your public transport history for up to eight weeks back.
The easiest way to find errors, is when you know how much you were SUPPOSED to be charged. For example, if your daily commute is always £8 (the daily cap), then simply look for days when it was higher.
Otherwise, simply look for strange-looking journeys – places where it says "No Tap Out", "Not Tap In", missing stations (that you know you've been at), etc'.
Once you find the errors, make a note of them (the exact date, and the stations involved) – and now it's time to call TfL.
TfL's customer service number is 0343 222 1234 (8am – 8pm daily).
When you call, you'll be asked to give our your Oyster number (or Contactless), and the details of the wrongful charges and incomplete journeys.
Assuming everything is correct, they will offer to refund the money – either back into your Oyster card (but you will need to tap a card reader within two days), or deposited into your bank account.
A quick survey among my friends revealed that almost none of them check their Oyster charges regularly. (It's a bit easier with Contactless – when the charges are too high, you'll spot them the next day on your bank account. However… many people have no idea how much they're SUPPOSED to pay – or simply don't monitor their bank accounts closely enough).
If that's you – please go NOW and register your card, then start checking your journey history. You'll be surprised at how much money you might be losing.
Bonus Tip: TfL's website can also be used to ask for refunds on late trains and tube disruptions. I'll write another post about that in the near future.


Enjoy a quiet, quaint, but quick run. Designed with input from competitive runners, our course zips you through North Taylor with multiple changes in scenery on a flat route. We start and finish in Bull Branch Park, but you'll also experience a bit of our countryside and Taylor living.
No matter your experience, we encourage all skill levels to participate. Strollers, teams & costumes are welcome!


Patient Mark Howell went to his doctor in November, concerned that his throat was swollen. It was a blow to learn the cause was cancer. Ghabach said Howell was initially reluctant to begin treatment. But he was able to convince Howell, an energetic movie actor from Fort Worth, that chemotherapy wouldn't be anywhere near as tough as he feared. The results have been excellent, according to Ghabach. On Wednesday, Howell had what may be his last chemotherapy treatment. He'll come back in a few days for an examination to determine if his rapidly-shrinking tumor has been defeated.


What do you normally do during your lunchtime? A quick bite with friends? Watching YouTube videos at your desk? They're perfectly fine options. But what if you could be part of creating a new, original art production instead?
That's the idea of Open Rehearsals, a new series at ArtisTree that launches in July.
Two productions are part of the Open Rehearsals series in July and August: Emoto, a collaboration between Hong Kong-based group The Nonsensemakers and CITA / International Centre for Theatre Arts; and iCoDaCo, an international contemporary dance collective.
What about the food, you ask? Butler Luxury Caterers will be preparing special lunchboxes for each rehearsal, which you can pick up at the beginning of the session and enjoy while you watch.
Food is great, but the rarity of such open rehearsals is a draw in itself. As Ngai notes, at the Open Rehearsals – and at ArtisTree – "Anything can happen." And you, the audience, are a critical part in making them happen.


Who are not interested in phone display for them this Screenless Smartphone for kids is perfect. It's fully water resistant with the 4G LTE network. Wi-Fi is available to communicate with your Kids. It includes a magnetic charging cable. Screenless Smartphone for kids is a perfect gadget for your kids.


Presidential candidate Rick Perry and Mitt Romney hold heated exchange over employment at presidential candidate debate.
Mr Perry, the Texas governor and new front-runner for the Republican presidential nomination, wasted little time in attacking his main rival, former Massachusetts governor Mr Romney, at the Ronald Reagan presidential library.
Their battle, which largely overshadowed the six other candidates, highlights how the Republican campaign is increasingly a two-horse race.
Buoyed by support from activists in the conservative Tea Party movement, Mr Perry has pushed Mr Romney to second place in opinion polls since entering the race less than a month ago.
They attacked each other over who had the better economic record – a central issue in the campaign as US struggles with 9.1 per cent unemployment.
Mr Romney also said at the debate that if he were elected president, he would not keep Ben Bernanke as chairman of the Federal Reserve arguing that quantitative easing programme had not worked.
The Federal Reserve has used two rounds of quantitative easing – increasing the money supply by buying up securities to help boost the economy.
The event was the first in a series of debates in the next six weeks likely to help define the Republican race.


Back at home, a few weeks ago, the weather was very threatening. Imposing dark clouds in the sky with the brightness of the city at dawn was perfect. Wonderful.
I'm so grateful my camera allows me to grab some nice capture in very low light conditions. Grain is there but I think it brings a more dramatic asset to the situation.


Glamourous and just exotic enough to make you feel like you're strolling around the Polynesian Islands! Or, if you happen to have an upcoming vacation in the works, this look is definitely vacay-ready. Either way, a flowing goddess-like dress with gold accents is always a winning combination in my book!