A semiconductor device that includes a clock generator which generates a clock signal; a booster which boosts a supply voltage by using the clock signal to output the boosted voltage; a potential detector which detects an output potential of the booster to output a frequency changing signal depending on the output potential; and a frequency changer which is interposed between the clock generator and the booster to change the frequency of the clock signal from the clock generator to the booster on the basis of the frequency changing signal.
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2003-429147, filed on Dec. 25, 2003, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor device and a driving method of a semiconductor device.
Such a semiconductor memory device as a NAND type flash memory or the like requires a voltage which is higher than a power source voltage and is constant in order to write, erase or read data. For this reason, a semiconductor device is provided with a booster circuit which boosts a power source and a regulator circuit which holds an output voltage of the booster circuit in a constant voltage.
FIG. 18 shows one example of a boosted potential generating portion in a conventional semiconductor memory device 10. A clock generating circuit 11 outputs a clock signal Φ, and a booster circuit 12 boosts a power source voltage by the clock signal Φ and a reversed signal (hereinafter, called "Φb") of the clock signal Φ having phases reversed to each other.
A regulator circuit 13 is provided with resistors R1, R2, a differential amplifier AMP1, an inverter In1, and AND gates G1, G2. In a potential detecting circuit 14, the resistors R1 and R2 potential-divides an output potential Vout of the booster circuit 12 to produce a monitor potential MON, and the differential amplifier AMP1 compares the monitor potential MON with a reference potential Vref. The differential amplifier AMP1 outputs "H (High)" level, when the monitor potential MON is larger than the reference potential Vref, while it outputs "L (Low)" level, when the monitor potential MON is smaller than the reference potential Vref. An output signal from the differential amplifier AMP1 is inverted by the inverter In1, and it is inputted into one of input terminals of the AND gates G1 and G2 as a flag signal FLG. Further, the other input terminals of the AND gates G1 and G2 are respectively inputted with clock signals Φ and Φb.
When the output potential Vout is relatively low and the monitor potential MON is smaller than the reference potential Vref, the flag signal FLG is H level. Therefore, the AND gates G1 and G2 allow the clock signals Φ and Φb to pass through the booster circuit 12, so that the booster circuit 12 boosts the power source voltage. On the other hand, when the output potential Vout is relatively high and the monitor potential MON exceeds the reference potential Vref, the flag signal FLG becomes L level. Accordingly, the AND gates G1 and G2 interrupt the clock signals Φ and Φb, so that the booster circuit 12 stop its boosting operation.
Thus, the regulator circuit 13 holds the monitor potential MON in almost the reference potential Vref by allowing passing-through of the clock signals Φ and Φb or by interrupting them. Since the monitor potential MON depends on the output potential Vout, the regular circuit 13 holds the output potential Vout in about a certain constant potential. Thereby, by setting the values of the reference potential Vref and the resistors R1 and R2 properly, the regulator circuit 13 can hold the output potential in almost a predetermined expected potential value.
The above technique is described in JP-A2003-242790 (hereinafter, called Patent Literature 1), U.S. Pat. No. 6,294,950 (hereinafter, called Patent Literature 2) and JP-A08-190789 (hereinafter, called Patent Literature 3).
Now, in order to boost the output potential Vout up to a predetermined expected potential value in a short time, it is necessary to elevate a boosting ability of the booster circuit 12. When the boosting ability of the booster circuit 12 is elevated, as shown in FIG. 19, there occurs such a problem that overshoot and ripple become large. The overshoot means such a phenomenon that a potential transiently exceeds a expected potential value at a time of boosting. The ripple means such a phenomenon that, when an output potential Vout after being boosted is held in an expected potential value, the output potential Vout oscillates at an expected potential value. These phenomena occur due to RC delay from detection of the output Vout to feedback of a flag signal FLG to AND gates G1 and G2.
These problems become significant when the values of the resistors R1 and R2 are made large in order to reduce a value of a current flowing in the resistors R1 and R2, which acts a load current on the booster circuit 12. This is because, when the values of the resistors R1 and R2 are made large, the RC time constant in the potential detecting circuit 14 becomes large so that response of the potential detecting circuit 14 is delayed.
In the Patent Literature 1 and the Patent Literature 2, a semiconductor device which compares a voltage obtained by voltage-dividing an output voltage of a booster circuit with a reference voltage to change a frequency of a clock generating circuit. However, in such a flash memory as an NAND type flash memory, clock signals are ordinarily supplied to a plurality of booster circuits by one clock generating circuit. Thereby, there arises a problem that, when the frequency of the clock generating circuit itself is changed, the frequencies of all the clock signals supplied to the plurality of booster circuits change. On the other hand, when clock generating circuits are provided so as to correspond to each of the plurality of booster circuits, there occur such a problem that the size of the semiconductor memory device is made large and such a problem that the amplitude or the frequency of the clock signal is fluctuated.
A semiconductor device according to an embodiment of the present invention comprises a clock generating circuit which generates a clock signal; a booster circuit which boosts a supply voltage by using the clock signal to output the boosted voltage; a potential detecting circuit which detects an output potential of the booster circuit to output a frequency changing signal depending on the output potential; and a frequency changing circuit which is interposed between the clock generating circuit and the booster circuit to change the frequency of the clock signal from the clock generating circuit to the booster circuit on the basis of the frequency changing signal.
detecting an output potential of the booster circuit at the potential detecting circuit; generating a frequency changing signal depending on the output potential at the potential detecting circuit; changing a frequency of the clock signal from clock generating circuit to the booster circuit on the basis of the frequency changing signal.
FIG. 19 is a graph of an output potential Vout in the boosted potential generating section of a conventional semiconductor device.
Embodiments of the present invention will be explained below with reference to the drawings. However, these embodiments do not limit the present invention. The semiconductor devices according to these embodiments is each provided between a clock generating circuit and a booster circuit with a frequency changing circuit for changing the frequency of a clock signal. Thereby, even if a boosting ability of the booster circuit is improved, overshoot and ripple of an output voltage can be reduced.
FIG. 1 is a block diagram of a boosted potential generating section of a semiconductor device 100 according to a first embodiment of the present invention. The semiconductor device 100 is provided with a clock generating circuit 111, booster circuits 112 and regulator circuits 113. Thus, a plurality of the booster circuits 112 are provided to correspond to one clock generating circuit 111. The regulator circuit 113 is provided between each booster circuit 112 and the clock generating circuit 111 so as to correspond to each booster circuit 112. The clock generating circuit 111 may be constituted of an oscillator such as, for example, a ring oscillator. The booster circuit 112 may be a charge pump of Dickson type such as, for example, shown in FIG. 5.
The clock generating circuit 111 generates a clock signal. The booster circuit 112 boosts a supply voltage using the clock signal and further outputs the boosted supply voltage. The regulator circuit 113 detects an output potential Vout of the booster circuit 112 to perform switching between passing-through and interruption of the clock signal from the clock generating circuit 111 through the booster circuit 112 on the basis of the detected output signal Vout and adjust the frequency of the clock signal. Thereby, the regulator circuit 113 holds the output potential Vout in a desired expected voltage value.
The plurality of booster circuits 112 are provided for each clock generating circuit 111. As a representative one of such semiconductor devices, there is a NAND type flash memory. In the NAND type flash memory, an output voltage Vout is used for writing data in a memory cell, erasing the same or reading data from the memory cell.
FIG. 2 is a circuit diagram showing the clock generating circuit 111, and respective ones of the booster circuits 112 and the regular circuits 113. A portion defined with a broken line in FIG. 1 corresponds to a portion shown in FIG. 2. The regulator circuit 113 includes resistors R10, R20 and R30, differential amplifiers AMP10 and AMP20, a frequency changing circuit 120, AND gates G10 and G20, and inverters In10 and In20.
The resistors R10, R20 and R30 are connected in series between an output of the booster circuit 112 and a ground GND. The resistors R10, R20 and R30 may be fixed resistors or variable resistors. The resistors R10, R20 and R30 potential-divide the output voltage Vout to produce a monitor potential MON1 from a node N1 between the resistor R10 and the resistor R20 and a monitor potential MON2 from a node N2 between the resistor R20 and R30, respectively. Since the monitor potentials MON1 and MON2 changes in proportion to the output potential Vout, the output potential Vout can be monitored.
In order to reduce a current IR flowing in the resistors R1, R2 and R3, it is preferable that the sum of resistance values of the resistors R1, R2 and R3 is made larger. This is because that the current IR acts as a load current for blocking a boosting operation of the booster circuit 112. However, the resistance values of the resistors R1, R2 and R3 are large, a RC time constant of the potential detecting circuit 114 becomes large, so that response of the potential detecting circuit 114 is delayed.
One inputs of the differential amplifiers AMP10 and AMP20 are respectively connected to nodes N1 and N2, while the other inputs thereof are both connected to a reference potential Vref. The differential amplifier AMP10 compares the monitor potential MON1 with the reference potential Vref to outputs a flag signal FLG1 on the basis of the comparison result. In details, when the monitor potential MON1 is lower than the reference potential Vref, the differential amplifier AMP10 makes the flag signal FLG1 L (Low), and when the monitor potential MON1 exceeds the reference potential Vref, the differential amplifier AMP10 makes the flag signal FLG1H (High).
The differential amplifier AMP20 compares the monitor potential MON2 with the reference potential Vref to output a signal on the basis of the comparison result. Since an output of the differential amplifier AMP20 is connected with the inverter In10, a flag signal FLG2 is a signal obtained by reversing an output signal of the differential amplifier AMP20. In details, when the monitor potential MON2 is lower than the reference potential Vref, the differential amplifier AMP20 outputs Low and the flag signal FLG 2 becomes High. When the monitor potential MON2 exceeds the reference potential Vref, the differential amplifier AMP20 outputs High and the flag signal FLG2 becomes Low.
The frequency changing circuit 120 is connected between the clock generating circuit 111 and the booster circuit 112. The frequency changing circuit 120 is inputted with a clock input signal CLKIN from the clock generating circuit 111 and is inputted with the flag signal FLG1 from the differential amplifier AMP10 as a frequency changing signal CLKCHG. The frequency changing circuit 120 changes the frequency of the clock input signal CLKIN on the basis of the frequency changing signal CLKCHG. For example, when the frequency changing signal CLKCHG is inactive (Low), namely, the flag signal FLG1 is low, the frequency changing circuit 120 outputs the clock input signal CLKIN as a clock output signal CLKOUT without changing the frequency "w" of the clock input signal CLKIN. When the frequency changing signal CLKCHG is active (High), namely, the flag signal FLG1 is high, the frequency changing circuit 120 lowers the frequency w of the clock input signal CLKIN to w/2 and outputs this signal as the clock output signal CLKOUT.
The AND gates G10 and G20 is connected between the frequency changing circuit 120 and the booster circuit 112. One input terminal of the AND gate G10 is inputted with the flag signal FLG2 as an enabling signal CLKENB, and the other input terminal of thereof is inputted with the clock output signal CLKOUT. Thereby, when the enabling signal CLKENB is active (High), namely, the flag signal FLG2 is high, the AND gate G10 allows passing-through of the clock output signal CLKOUT as a clock signal Φ. When the enabling signal CLKENB is inactive (Low), namely, the flag signal FLG2 is low, the AND gate G10 interrupts the clock output signal CLKOUT. One input of the AND gate G20 is inputted with the flag signal FLG2 as an enabling signal CLKENB and the other input thereof is inputted with a reversed signal of the clock output signal CLKOUT. Thereby, when the enabling signal CLKENB is active (High), the AND gate G20 allows passing-through of the reversed signal of the clock output signal CLKOUT as a clock signal Φbar. When the enabling signal CLKENB is inactive (Low), the AND gate G10 interrupts the reversed signal of the clock output signal CLKOUT.
The monitor potential MON2 is lower than the monitor potential MON1 by the magnitude corresponding to interposition of the resistor R20. Thereby, for example, when the output potential Vout increases from zero, the monitor potential MON1 first exceeds the reference potential Vref and then the monitor potential MON2 exceeds the reference potential Vref. Therefore, from a state (state 1) that the flag signal FLG1 is Low and the flag signal FRG2 is High, the flag signal FLG1 is changed to High (state 2) and the flag signal FRG2 is further changed to Low (state 3).
At a time of the state 1, the frequency changing signal CLKCHG is inactive and the enabling signal CLKENB is active. Therefore, the frequency changing circuit 120 outputs the clock input signal CLKIN with the frequency "w" as the clock output signal CLKOUT, and the AND gates G10 and G20 output the clock output signals CLKOUT as clock signals Φ and Φbar.
At a time of the state 2, both the frequency changing signal CLKCHG and the enabling signal CLKENB are active. Therefore, the frequency changing circuit 120 outputs a clock signal 2*CLK obtained by reducing the frequency w of the clock input signal CLKIN to w/2 as the clock output signal CLKOUT, and the AND gates G10 and G20 output the clock signal 2*CLK as the clock signals Φ and Φbar.
At a time of the state 3, the frequency changing signal CLKCHG is active and the enabling signal CLKENB becomes inactive. Therefore, the frequency changing circuit 120 outputs the clock signal 2*CLK, but the AND gates G10 and G20 interrupt the clock signal 2*CLK.
On the other hand, when the output potential Vout falls below High (H) potential, the monitor potential MON2 first lowers below the reference potential Vref, and the monitor potential MON1 lowers below the reference potential Vref. Therefore, from a state (the state 3) that the flag signal FLG1 is High and the flag signal FRG2 is Low, the flag signal FLG2 first changes to High (the state 2) and further the flag signal FLG1 becomes Low (the state 1).
FIG. 3 is a circuit diagram showing a specific example of the frequency changing circuit 120. The frequency changing circuit 120 is provided with a frequency-dividing circuit 130 which divides the frequency w of the clock input signal CLKIN into w/2 to output this frequency-divided signal as the clock signal 2*CLK. The frequency-dividing circuit 130 includes transfer gates T1 to T4, as shown in FIG. 3. The frequency w of clock input signal CLKIN can be frequency-divided into w/2 by alternate switching between the transfer gates T1 and T4 and the transfer gates T2 and T3. The transfer gates T1 to T4 are, for example, respectively constituted by parallel connections of N-type MOS transistors and P-type MOS transistors.
The frequency changing circuit 120 is further provided with NAND gates G30, G40 and G50. The NAND gate G30 is inputted with the reversed signal of the frequency changing signal CLKCHG and the clock input signal CLKIN. The NAND gate G40 is inputted with the frequency changing signal CLKCHG and the clock signal 2*CLK from the frequency-dividing circuit 130. The NAND gate G50 is inputted with outputs of the NAND gates G30 and G40.
Therefore, when the frequency changing signal CLKCHG is inactive (Low), the clock output signal CLKOUT becomes the clock input signal CLKIN with the frequency w. On the other hand, when the frequency changing signal CLKCHG is active (High), the clock output signal CLKOUT becomes the clock signal 2*CLK obtained by frequency-dividing the frequency w of the clock input signal CLKIN into w/2.
FIG. 4 is a timing chart showing a relationship between the frequency changing signal CLKCHG and the clock output signal CLKOUT. When the frequency changing signal CLKCHG is Low (time points t0 to t1), the clock output signal CLKOUT is the clock input signal CLKIN. When the frequency changing signal CLKCHG becomes High (time points t1 to t2), the clock output signal CLKOUT becomes the clock signal 2*CLK. Further, the frequency changing signal CLKCHG returns to Low (time point t2 and thereafter), the clock output signal CLKOUT returns to the clock input signal CLKIN.
FIG. 5 is a circuit diagram showing a specific example of the booster circuit 112. FIG. 6 is a timing chart showing signal levels of clock signals Φ and Φbar. The booster circuit 112 is inputted with a supply potential Vin, and it boosts the supply potential Vin by the clock signals Φ and Φbar whose phases are reversed to each other, as shown in FIG. 6. The booster circuit 112 outputs the boosted supply potential Vin as an output potential Vout.
FIG. 7 is a graph showing an output potential Vout of this embodiment. FIG. 8 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ. In this connection, since the clock input signal CLKIN and the clock signal 2*CLK are respective signals with fixed frequencies of w and w/2, as illustrated in FIG. 4, they will be omitted in FIG. 8.
The output potential Vout when the monitor potential MON1 is equal to the reference potential Vref is defined as an expected potential value 1, and the output potential Vout when the monitor potential MON2 is equal to the reference potential Vref is defined as an expected potential value 2. As described with reference to FIG. 2, when the output potential Vout is raised, since the monitor potential MON1 exceeds the reference potential Vref prior to the monitor potential MON2, the expected potential value 2 becomes a potential higher than the expected potential value 1.
With reference to FIG. 7 and FIG. 8, operation and advantage of the semiconductor device 100 shown in FIG. 2 will be explained. In this connection, this embodiment serves so as to hold the output potential Vout in the expected potential value 2.
First, when the booster circuit 112 starts boosting operation, the output potential Vout rises from zero (time points t10 to t11). At this time, since both the monitor potential MON1 and the monitor potential MON2 are smaller than the reference potential Vref, the frequency changing signal CLKCHG (flag signal FLG1) is Low and the enabling signal CLKENB (flag signal FLG2) is active (High). Therefore, the frequency changing circuit 120 outputs the clock input signal CLKIN as the clock output signal CLKOUT without changing the frequency w of the clock input signal CLKIN. Further, the AND gates G10 and G20 output the clock output signals CLKOUT as the clock signals Φ and Φbar. Thereby, the booster circuit 112 can boost a supply voltage (not shown) in a short time.
Next, when the output potential Vout exceeds the expected potential value 1 (time point t11), the monitor potential MON1 exceeds the reference potential Vref and the monitor potential MON2 remains smaller than the reference potential Vref. Therefore, the frequency changing signal CLKCHG becomes active (High) and the enabling signal CLKENB holds its active (High) state. Thereby, the frequency changing circuit 120 frequency-divides the frequency w of the clock input signal CLKIN to w/2 to output the same as the clock output signal CLKOUT. The AND gates G10 and G20 output the clock output signals CLKOUT with the frequency w/2 as the clock signal Φ or Φbar. Accordingly, the boosting ability of the booster circuit 112 is reduced to ½ to the clock signals Φ and Φbar with the frequency w.
Next, when the output potential Vout exceeds the expected potential value 2 (time point t12), the monitor potential MON2 exceeds the reference potential Vref. Therefore, the enabling signal CLKENB becomes inactive (Low). Thereby, the AND gates G10 and G20 interrupt the clock output signals CLKOUT. Thereby, the clock signals Φ and Φbar become low. That is, the boosting operation of the booster circuit 112 stops and the output potential Vout gradually lowers due to the current IR. In this connection, after the output potential (voltage) Vout exceeds the expected potential value 2, it is delayed, so that the enabling signal CLKENB is changed. This is because the potential detecting circuit 114 has a RC time constant, and the RC delay of the potential detecting circuit 114 causes overshoot or ripple.
Further, when the output potential Vout lowers below the expected potential value 2 (time point t13), the monitor potential MON2 decreases below the reference potential Vref. Thereby, the enabling potential CLKENB becomes active (High). At this time, the frequency changing signal CLKCHG holds its active (High) state. Therefore, the frequency changing circuit 120 outputs the clock signal CLKOUT with the frequency w/2 CLKOUT, and the AND gates G10 and G20 output the clock signals CLKOUT with the frequency w/2 CLKOUT as the clock signal Φ or Φbar. Accordingly, the booster circuit 112 restarts the boosting operation. However, since the frequency of the clock signal Φ or Φbar is w/2, the boosting ability of the booster circuit is about one half to the boosting ability obtained by the clock signal Φ or Φbar with the frequency w. Incidentally, since the current IR is very small, a lowering speed of the output potential Vout is slow. Thereby, the undershoot ordinarily becomes smaller than the overshoot. Accordingly, the output potential Vout does not lower below the expected potential value 1 and it is held in the expected potential value 2.
Thereafter, when the output potential Vout exceeds the expected potential value 2 (time t14), the same operation as that at the time point t12 is conducted in this embodiment. The operations of the semiconductor device 100 at the time points t13 and t14 are repeated at time points t15 and t16 and time points t17 and t18. Thereby, the semiconductor device 100 serves so as to hold the output potential Vout in the expected potential value 2.
When the output of the booster circuit 112 is connected with a new load (not shown), there occurs a possibility that the output potential Vout lowers rapidly. In such a case, since the output potential Vout lowers below the expected potential value 1, the booster circuit 112 is driven by the clock signals Φ and Φbar with the frequency w like the case at the time points t10 to t11. Thereby, the booster circuit 112 can boost the output voltage (potential) Vout in a short time by a High boosting ability thereof.
According to this embodiment, since the booster circuit 112 is driven by the clock signals Φ and Φbar with the frequency "w" in an initial stage of the boosting operation, the boosting speed of the output potential Vout is fast. On the other hand, when the output potential Vout is boosted up to approximately the expected potential value 2, the frequencies of the clock signals Φ and Φbar are frequency-divided to w/2. Thereby, since the boosting ability of the booster circuit 112 lowers, the overshoot can be suppressed to a smaller value as compared with the conventional case.
Further, when the output potential Vout is held in an expected potential value 2, booster circuits 112 repeats the boosting operation and stopping operation of the boosting operation by the clock signals Φ and Φbar frequency-divided to w/2.
In this embodiment, because the regulator circuit 113 changes the frequency of the clock signal for each of the booster circuits 112, the regulator circuit 113 are respectively provided so as to correspond to the plurality of booster circuits 112 (refer to FIG. 1). Thereby, the plurality of booster circuits 112 can be driven by using clock signals from the same or one clock generating circuit 111.
In this embodiment, the frequency changing circuit 120 must be provided for each of the booster circuits 112. However, the frequency changing circuit 120 can be realized with a simple frequency-dividing circuit, such as shown in FIG. 3. Further, the frequency changing circuit 120 only frequency-divides the clock signal. Therefore, fluctuation of the amplitude or frequency of the clock signal due to process variations or the like can be relatively small without making the size of the semiconductor memory device significantly large.
On the other hand, according to a conventional semiconductor device described in Patent Literature 2 and the like, a clock generating circuit must be provided for each booster circuit in order to change the frequency of the clock signal. Since the clock generating circuit is complicated as compared with the frequency changing circuit 120 according to this embodiment, provision of the clock generating circuit for each booster circuit makes the size of the semiconductor device large. Further, there is a case that the clock generating circuit is provided with a circuit which trims a clock frequency using a fuse or the like in order to suppress fluctuation of the clock frequency. In this case, when the clock generating circuit is provided for each booster circuit, the semiconductor memory device becomes complicated and its size becomes large.
In this embodiment, the frequency changing circuit 120 frequency-divides the frequency of the clock input signal CLKIN to ½. However, the frequency changing circuit 120 shown in FIG. 3 is only one specific example, and the frequency changing circuit 120 may divide the frequency of the clock input signal CLKIN to n/m of the frequency. Incidentally, n and m are natural numbers, where n<m.
In order to adjust the expected potential value 1 and the expected potential value 2, the values of the resistors R10, R20 and R30 may be changed. Thereby, the expected potential value 1 or the expected potential value 2 can be fitted to a required specification of the semiconductor memory device. The expected potential value 1 may be lower than the expected potential value 2, and it is not limited to a specific value. However, in order to reduce overshoot or ripple while holding a high boosting ability, it is preferable that the expected potential value 1 is set such that the output potential Vout does not become lower than the expected potential value 1, and it is preferable that the expected potential value 1 approximates to the expected potential value 2, when holding the output potential Vout in approximately the expected potential value 2.
A block diagram of a boosting section of a semiconductor device 200 according to a second embodiment is similar to that in FIG. 1. In this embodiment, a regulator circuit 213 is provided in place of the regulator circuit 113.
FIG. 9 is a circuit diagram showing a clock generating circuit 111, one of booster circuits 112 and one of regulator circuit 213.
The regulator circuit 213 includes resistor s R10, R20, R30 and R40, differential amplifiers AMP10, AMP20 and AMP30, a frequency changing circuit 220, a latch circuit 215, and inverters In10, In20, In30 and In40.
The resistors R10, R20, R30 and R40 are connected in series between an output of the booster circuit 112 and the ground GND. The resistors R10, R20, R30 and R40 may be either fixed resistors or variable resistors. The resistors R10, R20, R30 and R40 potential-divides the output potential Vout to produce a monitor potential MON1 from a node N1 between the resistor R10 and the resistor R20, a monitor potential MON2 from a node N2 between the resistors R20 and the resistor R30, and a monitor potential MON3 from a node N3 between the resistor R30 and the resistor R40, respectively. Since the monitor potentials MON1, MON2 and MON3 change in proportion to the output potential Vout, the output potential Vout can be monitored.
One inputs of the differential amplifiers AMP10, AMP20 and AMP30 are respectively connected to the nodes N1, N2 and N3, and the other inputs thereof are connected to the reference potential Vref. Outputs of the differential amplifiers AMP10, AMP20 and AMP30 are respectively connected with the inverters In10, In20 and In30.
The differential amplifiers AMP10, AMP20 and AMP30 respectively compare the monitor potentials MON1, MON2 and MON3 with the reference potential Vref to output signals based upon the comparison results. The inverters In10, In20 and In30 reverse respective outputs of the differential amplifiers AMP10, AMP20 and AMP30 and output these reversed outputs as flag signals FLG1, FLG2 and FLG2.
In details, when the monitor potentials MON1, MON2 and MON3 are lower than the reference potential Vref, the flag signals FLG1, FLG2 and FLG3 become High, respectively. When the monitor potentials MON1, MON2 and MON3 exceed the reference potential Vref, the flag signals FLG1, FLG2 and FLG3 become Low, respectively.
The flag signals FLG1 and FLG2 are supplied to the latch circuit 215. The latch circuit 215 outputs a frequency changing signal CLKCHG on the basis of the flag signals FLG1 and FLG2. In this embodiment, when the flag signals FLG1 and FLG2 are changed to low, the frequency changing signal CLKCHG is latched to an active (High) state. When both the flag signals FLG1 and FLG2 are changed to Low, the frequency changing signal CLKCHG is latched to an inactive (Low) state. When only one of the flag signals FLG1 and FLG2 is changed, the state of the frequency changing signal CLKCHG does not change.
The flag signal FLG3 is supplied to the frequency changing circuit 220 as an enabling signal CLKENB.
The frequency changing circuit 220 is connected between the clock generating circuit 111 and the booster circuit 112. The frequency changing circuit 220 is inputted with a clock input signal CLKIN, a frequency changing signal CLKCHG and an enabling signal CLKENB. The frequency changing circuit 220 changes the frequency of the clock input signal CLKIN on the basis of the frequency changing signal CLKCHG. Further, the frequency changing signal 220 allows passing-through of the clock input signal CLKIN or interrupts the clock input signal CLKIN on the basis of the enabling signal CLKENB.
An operation of the frequency changing circuit 220 to the flag signals FLG1, FLG2 and FLG3 will be explained. When the output potential Vout is boosted from a low potential, the monitor potentials MON1, MON2 and MON3 exceed the reference potential Vref in the order of the monitor potentials MON1, MON2 and MON3. Therefore, the flag signals FLG1, FLG2 and FLG3 sequentially change from respective High, High and High states (state 10) to Low, High and High states (state 11), Low, Low and High states (state 12), and Low, Low and Low states (state 13).
During the state 10, the frequency changing signal CLKCHG is inactive (Low) and the enabling signal CLKENB becomes active (High). At this time, the frequency changing circuit 220 outputs the clock input signal CLKIN as the clock output signal CLKOUT without changing the frequency w of outputs the clock input signal CLKIN.
During the state 11, since the frequency changing circuit 220 and the latch circuit 215 do not change, the state 11 is similar to the state 10.
During the state 12, the latch circuit 215 latches the frequency changing signal CLKCHG in an active (High) and the enabling signal CLKENB holds its active (High) state. At this time, the frequency changing circuit 220 changes the clock input signal CLKIN to a clock signal 4*CLK with a frequency of w/4 to output the same as a clock output signal CLKOUT.
During the state 13, the frequency switching signal CLKCHG is active (High) and the enabling signal CLKENB becomes inactive (Low). At this time, the frequency switching circuit 220 interrupts the clock input signal CLKIN and the clock signal 4*CLK.
In case that the output potential Vout falls below a high potential, the monitor potentials MON3, MON2 and MON1 lower below the reference potential Vref in this order. Therefore, the flag signals FLG1, FLG2 and FLG3 transit from the state 13 to the state 12, the state 11 and the state 10. In this connection, when both the flag signals FLG1 and FLG2 change, namely, the state transit from the state 11 to the state 10, the latch circuit 215 changes the frequency changing signal CLKCHG.
FIG. 10 is a circuit diagram showing a specific example of the frequency changing circuit 220. The frequency changing circuit 220 is provided with frequency-dividing circuits 231 and 232. The frequency-dividing circuit 231 frequency-divides the frequency w of the clock input signal CLKIN to w/2 to output the same as a clock signal 2*CLK. The frequency-dividing circuit 232 frequency-divides the frequency w/2 of the clock signal 2*CLK to w/4 to output the same as a clock signal 4*CLK.
The frequency-dividing circuit 231 includes transfer gates T1 to T4. The frequency w of the clock input signal CLKIN can be frequency-divided to ½ by switching the transfer gates T1, T4 and the transfer gates T2, T3 alternately. The frequency-dividing circuit 232 includes transfer gates T5 to T8. The frequency of the clock signal 2*CLK can be further frequency-divided to ½ thereof by alternately switching the transfer gates T5, T8 and the transfer gates T6, T7. The transfer gates T5, T8 are respectively constituted by parallel connections of N-type MOS transistors and P-type MOS transistors.
The frequency changing circuit 220 is further provided with an AND gate G60, and NAND gates G70, G80 and G90. The AND gate G60 is inputted with a clock input signal CLKIN and an enabling signal CLKENB. The NAND gate G70 is inputted with an output of the NAND gate G60 and a reversed signal of a frequency changing signal CLKCHG. The NAND gate G80 is inputted with the frequency changing signal CLKCHG and a clock signal 4*CLK from the frequency-dividing circuit 232. The NAND gate G90 is inputted with outputs of the NAND gates G70 and G80.
The AND gate G60 allows passing-through of a clock input signal CLKIN, when the enabling signal CLKENB is active (High), while it interrupts the clock input signal CLKIN, when the enabling signal CLKENB is inactive (Low). Incidentally, in this embodiment, the AND gate G60 is included in the frequency changing circuit 220 as a gate circuit for allowing a clock input signal CLKIN to pass through or interrupts the same.
Further, when the frequency changing signal CLKCHG is active (High), the clock output signal CLKOUT becomes a clock signal 4*CLK. On the other hand, when the frequency changing signal CLKCHG is inactive (Low), the clock output signal CLKOUT becomes an output signal of the AND gate G60.
FIG. 11 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB and a clock output signal CLKOUT. When the enabling signal CLKENB is High and the frequency changing signal CLKCHG is Low (time points t0 to t1), the frequency changing circuit 220 outputs the clock input signal CLKIN as a clock output signal CLKOUT. When both the enabling signal CLKENB and the frequency changing signal CLKCHG are High (time points t1 to t2), the frequency changing circuit 220 outputs the clock signal 4*CLK as the clock output signal CLKOUT. When the enabling signal CLKENB becomes Low (time points t2 to t3), the frequency changing circuit 220 interrupts the clock input signal CLKIN and the clock signal 4*CLK. Operations of the frequency changing circuit 220 during time points t3 to t4 and time points t5 to t6 are similar to the operation of the frequency changing circuit 220 during the time points t1 to t2. Operations of the frequency changing circuit 220 during time points t4 to t5 and during time point t6 to time point subsequent thereto are similar to the operations of the frequency changing circuit 220 during the time points t2 to t3 and during the time points t0 to t1.
FIG. 12 is a graph showing an output potential Vout of this embodiment. FIG. 13 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and clock signal Φ. Incidentally, since the clock input signal CLKIN and the clock signal 4*CLK are a signal with a fixed frequency of w and a signal with a fixed frequency of w/4, they will be omitted in FIG. 13.
An output potential Vout obtained when the monitor potential MON1 is equal to the reference potential is defined as an expected potential value 1, an output potential Vout obtained when the monitor potential MON2 is equal to the reference potential is defined as an expected potential value 2, and an output potential Vout obtained when the monitor potential MON3 is equal to the reference potential is defined as an expected potential value 3. As explained with reference to FIG. 9, when the output potential Vout is boosted, the monitor potentials MON1, MON2 and MON3 exceed the reference potential Vref in this order, so that the potential of the expected potential value 3 is the highest and the expected potential values lower in the order of the expected potential values 2 and the expected potential value 1.
With reference to FIG. 12 and FIG. 13, an operation and an advantage of the semiconductor device 200 shown in FIG. 9 will be explained. Incidentally, this embodiment serves to hold the output potential Vout in the expected potential value 3. When the booster circuit 112 first starts an boosting operation, the output potential Vout rise from zero (during time points t20 to t21). At this time, the monitor potentials MON1 to MON3 are lower than the reference potential Vref. Alternatively, only the monitor potential MON1 exceeds the reference potential Vref. Therefore, all the flag signals FLG1 to FLG3 become High or only the flag signal FLG1 becomes Low. At this time, the frequency changing signal is inactive (Low) and the enabling signal CLKENB is active (High). Therefore, frequency changing circuit 220 outputs the clock input signal CLKIN as the clock output signal CLKOUT without changing the frequency w of the clock input signal CLKIN. The clock output signal CLKOUT and a reversed signal thereof become clock signals Φ and Φbar. Thereby, the booster circuit 112 can boost the output voltage Vout in a short time with its high boosting ability.
Next, when the output potential Vout exceeds the expected potential value 2 (time point t21), the monitor potentials MON1 and MON2 exceed the reference potential Vref, while the monitor potential MON3 remains lower than the reference potential Vref. Therefore, the frequency changing signal CLKCHG is latched in an active (High) state and the enabling signal CLKENB holds its active (High) state. Therefore, the frequency changing circuit 220 outputs the clock signal 4*CLK with the frequency w/4 as the clock output signal CLKOUT. The clock signal 4*CLK and its reversed signal become clock signals Φ and Φbar. Therefore, the boosting ability of the booster circuit 112 lowers to ¼ to the clock signals Φ and Φbar with the frequency w.
Next, when the output potential Vout exceeds the expected potential value 3 (time point t22), the monitor potential MON3 exceeds the reference potential Vref. Therefore, the enabling signal CLKENB becomes inactive (Low). Therefore, the frequency changing circuit 220 interrupts the clock output signal CLKOUT. Thereby, the clock signals Φ and Φbar become Low. That is, the boosting operation of the booster circuit 112 stops and the output voltage Vout gradually lowers due to a current IR.
When the output potential Vout lowers below the expected potential value 3 (time point t23), the monitor potential MON3 lowers below the reference potential Vref. Therefore, the enabling signal CLKENB becomes active (High). At this time, the frequency changing signal CLKCHG is latched in an active (High) state by the latch circuit 215. Therefore, the frequency changing circuit 120 outputs the clock signal 4*CLK with the frequency w/4 as a clock signal Φ or Φbar. Thus, the booster circuit 112 restarts its boosting operation. However, since the frequency of the clock signal Φ or Φbar is w/4, the boosting ability is about ¼ to the clock signal Φ or Φbar with the frequency w. In this connection, since the current IR is very small, a lowering speed of the output potential Vout is slow. Thereby, undershoot becomes smaller than overshoot. Accordingly, the output potential Vout does not lower below the expected potential value 1 and it can be held in the expected potential value 3.
Therefore, when the output potential Vout exceeds the expected potential value 3 (time point t24), the semiconductor device 200 performs the same operation as the operation at the time point t22. An operation of the semiconductor device 200 during the time points t25 to t26 is the same at the operation of the semiconductor device 200 during the time points t23 to t24.
Further, when an output of the booster circuit 112 is connected with a new load (time point t27), such a possibility may occur that the output voltage Vout lowers urgently. In such a case, since the output voltage Vout lowers below the expected value voltage (potential) 1, the latch circuit 215 is reset, and the booster circuit 112 is driven by the clock signal Φ or Φbar with the frequency w like the case during time points t20 to t21. Thereby, the booster circuit 112 can boost the output voltage Vout in a short time. An operation of the semiconductor device 200 during the time points t28 to t29 is the same as the operation of the semiconductor device during the time points t21 to t22.
This embodiment has an advantage or merit similar to the first embodiment. Further, this embodiment has the latch circuit 215, where three expected potential values have been set. Thereby, the output potential Vout can be boosted with a high boosting ability until the output potential Vout is boosted up to the expected potential value 2 approximating to the expected potential value 3. On the other hand, even if the output potential Vout lowers below the expected potential value 2, the frequencies of the clock signals Φ and Φbar are held in the frequency w/4 by operation of the latch circuit 215. Unless the output potential Vout lowers below the expected potential value 1 lower than the expected potential value 2, the frequencies do not return back to the frequency w. That is, it is made possible to boost the output potential Vout with a high boosting ability just before the expected potential value 3 by causing the expected potential value 2 to approach to the expected potential value 3 sufficiently. In addition thereto, when the output potential Vout is held at the expected potential value 3, the frequencies of the clock signals Φ and Φbar with the frequency w/4 are w/4 and they are not reset to w, so that the output potential Vout is not boosted with an excessive boosting ability. As a result, this embodiment can boosts the output potential Vout in an initial stage of boosting very quickly, and a ripple may be made small.
In this embodiment, the frequency changing circuit 220 frequency-divides the frequency w of the clock input signal CLKIN to ¼. However, the frequency changing circuit 220 shown in FIG. 10 is merely one specific example, and the frequency changing circuit 220 may frequency-divide the clock input signal CLKIN to n/m. Incidentally n and m are natural numbers, where n<m.
In order to adjust the expected potential value 1, the expected potential value 2 and the expected potential value 3, values of the resistors R10, R20, R30 and R40 may be changed. Thereby, the values of the expected potential value 1, the expected potential value 2 and the expected potential value 3 can be fitted to their specifications. The expected potential value 2 is not limited to a specific value as long as it is equal to or less than the expected value 3. In this connection, it is preferable that the expected potential value 2 further approximates to the expected potential value 3 for holding a fast boosting speed. Further, the expected potential value 1 is not limited to a specific value as long as it is equal to or less than the expected potential value 2. In this connection, it is preferable that, when the output potential Vout is held in a value approximating to the expected potential value 3, the output potential Vout is set such that it does not lower below the expected potential value 1 for preventing the output potential Vout from being boosted with an excessive boosting ability.
A block diagram of a boosting section of a semiconductor device 300 according to a third embodiment is similar to that in FIG. 1. Incidentally, in this embodiment, a regulator circuit 313 is provided in place of the regulator circuit 313.
FIG. 14 is a circuit diagram of a clock generating circuit 111, one of booster circuits 112 and one of regulator circuits 313. The regulator circuit 313 is different from the regulator circuit 113 in that the former is provided with one differential amplifier and it includes a latch circuit 315.
Resistors R10 and R20 is connected in series between an output of the booting circuit 112 and the ground GND. The resistors R10 and R20 potential-divide an output potential Vout to produce a monitor potential MON1 from a node N1 between the resistor R10 and the resistor R20. Since the monitor potential MON1 changes in proportion to the output potential Vout, the output potential Vout can be monitored.
One input of a differential amplifier AMP10 is connected to the node N1, and the other input thereof is connected to the reference potential Vref. An output of the differential amplifier AMP10 is connected with an inverter In10.
The differential amplifier AMP10 compares the monitor potential MON1 and the reference potential Vref to each other to output a signal on the basis of the comparison result. The inverter In10 reverses an output of the differential amplifier AMP10 to output the same as a flag signal FLG1.
In details, when the monitor potential MON1 is lower than the reference potential Vref, the flag signal FLG1 becomes High. When the monitor potential MON1 exceeds the reference potential Vref, the flag signal FLG1 becomes Low.
The flag signal FLG1 is supplied to the latch circuit 315, and AND gates G10 and G20. The latch circuit 315 outputs a frequency changing signal CLKCHG on the basis of the flag signal FLG1. In this embodiment, after the flag signal FLF1 has been once changed to Low, the frequency changing signal CLKCHG is always latched in a active (High) state. Thereafter, even if the flag signal FLG1 is changed to High, the state of the frequency changing signal CLKCHG does not change.
Operations of the frequency changing circuit 120 and the AND gates G10 and G20 to the flag signal FLG1 will be explained. When the flag signal FLG1 is High, the enabling signal CLKENB is active (High) and the frequency changing signal CLKCHG is inactive (Low). Therefore, the frequency changing circuit 120 outputs a clock output signal CLKOUT with a frequency w, and the AND gates G10 and G20 cause the clock output signal CLKOUT and its reversed signal to pass through as clock signals Φ and Φbar.
When the flag signal FLG1 becomes Low, the enabling signal CLKENB becomes inactive (Low) and the latch circuit 315 latches the frequency changing signal CLKCHG in an active (High) state. Thereby, the frequency changing circuit 120 outputs a clock output signal CLKOUT with a frequency of w/2, and the AND gates G10 and G20 interrupt the clock output signals CLKOUT.
When the flag signal FLG1 becomes High again, the enabling signal CLKENB becomes active (High), but the frequency changing signal CLKCHG is held at an active (High) state by the latch circuit 315. Thereby, the frequency changing circuit 120 outputs the clock output signal CLKOUT with the frequency of w/2, and the AND gates G10 and G20 allows the clock output signal CLKOUT and its reversed signal to pass as the clock signals Φ and Φbar, respectively.
FIG. 15 is a graph showing an output potential Vout in this embodiment. FIG. 16 is a timing chart showing a relationship among a frequency changing signal CLKCHG, an enabling signal CLKENB, a clock output signal CLKOUT and a clock signal Φ. The output potential Vout obtained when the monitor potential MON1 is equal to the reference potential is defined as an expected potential value 1. The semiconductor device 300 serves to hold the output potential Vout in the expected potential value 1.
With reference to FIG. 15 and FIG. 16, an operation and an advantage of the semiconductor device 300 will be explained. First, when the booster circuit 112 starts a boosting operation, the output potential Vout is boosted (time points t30 to t31). At this time, the monitor potential MON1 is smaller than the reference potential Vref, so that the frequency changing signal CLKCHG is inactive (Low) and the enabling signal CLKENG is active (High). Therefore, the frequency changing circuit 120 outputs the clock input signal CLKIN as a clock output signal CLKOUT without changing the frequency w of the clock input signal CLKIN. Further, the AND gates G10 and G20 output the clock output signals CLKOUT as the clock signal Φ or Φbar. Thereby, the booster circuit 112 can boost a supply voltage in a short time.
Next, when the output potential Vout exceeds the expected potential value 1 (time point t31), the monitor potential MON1 exceeds the reference potential Vref. Therefore, the latch circuit 315 latches the frequency changing signal CLKCHG in an active (High) state and the enabling signal CLKENB becomes inactive (Low). Thereby, the frequency changing circuit 120 frequency-divides the frequency of the clock input signal CLKIN to w/2, but the AND gates G10 and G20 interrupt the clock output signals CLKOUT with the frequency w/2. Accordingly, the booster circuit 112 stops its boosting operation and the output potential Vout gradually lowers due to a current IR.
Next, when the output potential Vout lowers below the expected potential value 1 (time point t33), the monitor potential MON1 lowers below the reference potential Vref. Thereby, the enabling signal CLKENB becomes active (High). At this time, the frequency changing signal CLKCHG is held in an active (High) state by the latch circuit 315. Thereby, the frequency changing circuit 120 outputs the clock output signal CLKOUT with the frequency w/2, and the AND gates G10 and G20 outputs the clock output signals CLKOUT with the frequency w/2 as the clock signal Φ or Φbar. Accordingly, the booster circuit 112 restarts its boosting operation. However, since the frequency of the clock signal Φ or Φbar is w/2, its boosting ability is about one half to the boosting ability by the clock signal Φ or Φbar.
Thereafter, when the output potential Vout exceeds the expected potential value 1 (time point t34), this embodiment performs the same operation as at the time point t32. The operations of the semiconductor device 300 at the time points of t33 and t34 are repeated at the time points t35, t36 and time points t37, t38. Thereby, the semiconductor device 300 serves to hold the output potential Vout in the expected potential value 1.
This embodiment has an advantage or merit similar to the first embodiment. However, when the output of the booster circuit 112 is connected with a new load, there may occurs a possibility that the output potential Vout lowers rapidly. In such a case, since the frequency changing signal CLKCHG is remained in an active (High) state by the latch circuit 315, the booster circuit 112 performs a boosting operation by the clock signal Φ or Φbar with the frequency w/2. Therefore, a time elapsed until the output potential Vout returns back to the expected potential value 1 becomes longer than a time elapsed in the case that boosting is performed by the clock signal Φ or Φbar. Accordingly, this embodiment is unsuitable for a case that, after the output potential Vout has reached the expected potential value 1, the output of the booster circuit 112 is connected with a new load. However, since the circuit configuration of the semiconductor device 300 is simpler than the circuit configuration of the semiconductor device 100, the size of the apparatus can be further reduced.
FIG. 17 is a block diagram of a semiconductor device 400 according to an embodiment of the present invention. The semiconductor device 400 may be, for example, a NAND type EEPROM or a NAND type flash memory.
A bit line control circuit 2 for performing writing/reading of data in the memory cell array 1 as the memory means is provided. The bit line control circuit 2 are connected to a data input buffer 6 and receives an output of a column decoder 3 receiving an address signal from an address buffer 4 as an input. Further, a row decoder 5 is provided for controlling a control gate and a selection gate to the memory cell array 1, and a substrate potential control circuit 7 for controlling a potential of a p-type substrate (or a p-type well) on which the memory cell array 1 is formed is provided.
Further, the semiconductor device 400 is provided with a clock generating circuit 111, a regulator circuit and a booster circuit 112. The regulator circuit may be either one of the regulator circuits 113, 213 and 313 in the first to third embodiments. The booster circuit 112 supplies an output voltage Vout to the bit line control circuit 2, the row decoder 5 and the substrate potential control circuit 7 at reading/writing/erasing times of the memory cell array 1. The booster circuit 112 can supply a stable output potential Vout with reduced overshoot or ripple by the regulator circuit 113.
wherein the semiconductor device further comprises a gate circuit which is interposed between the frequency changer and the booster to cause the clock signal to pass to the booster from the frequency changer or to interrupt the clock signal on the basis of the enabling signal.
the gate circuit interrupts the clock signal from the frequency changer to the booster in a case that the enable signal is inactive.
the gate circuit passes the clock signal from the frequency changer to the booster in a case that the enable signal is active.
each frequency changer changes the frequency of the clock signal fed from the clock generator to the booster corresponding to each frequency changer on the basis of the frequency changing signal supplied from the potential detector corresponding to each frequency changer.
wherein the semiconductor device further comprises a gate circuit which passes or interrupts the clock signal from the clock generator to the booster on the basis of the enabling signal.
the gate circuit is embedded in the frequency changer.
a gate circuit which is interposed between the frequency changer and the booster to cause the clock signal to pass to the booster from the frequency changer or to interrupt the clock signal on the basis of the comparison result signal.
the gate circuit interrupts the clock signal from the frequency changer to the booster when the comparison result signal is active.
the gate circuit passes the clock signal from the frequency changer to booster when the comparison result signal is inactive.
the frequency changer gets back the lowered frequency of the clock signal to the original frequency, when the first potential falls below the reference potential again.
the latch-resets the frequency changing signal, and the frequency changer gets back the lowered frequency of the clock signal to the original frequency, when the first, the second, and the third potentials fall below the reference potential again.
the latch maintains the frequency changing signal, and the frequency changer does not change a state of the decreased frequency of the clock signal, and the gate circuit passes the clock signal to the booster when the first potential falls below the reference potential again.
U.S. Appl. No. 10/019,294, filed Dec. 23, 2004, Fukuda.


Plenty of small paddocks with plenty of space.
Cooling down after following the ride.
Hey ho! A new paddock!
Gelding pretending to be a stallion.
Ahhh! Something that is pleasing to the eye.
Cooling down in the little lake.
At Stockyard Creek Pioneer Homestead you may bring your horses and dogs or arrangements can be made, should guests wish, to hire horses and guides.
You and your animals are in a wondrous, fresh and invigorating environment – in the bush, up in the mountains and around valleys with creeks and rivers with the smell of peppermint in the air.
Care needs to be taken so that weeds are not inadvertently brought into the Valley. It is useful to 'empty out' horses before travelling and wash down hooves which may contain seeds. Weed eradication programs are ongoing on the property each year, so you help is highly regarded.
Animals must be within the care of the owner at all times and kangaroos can be aggressive towards dogs. Groups bringing horses or dogs are reminded that the owners are totally responsible for their care and feed.
All animals have to stay outside the Old Homestead, sorry, because other guests may be allergic to them.


[M/S's 1 & 9] are the  Primary [What-if] Model Segments in the easy-to-learn-and-use FastBooks Solution Self-Employed and Home-Based Business Accounting Model.
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text:
TMF cancels plan to list all downloads in its hit parade
Filed under: Music by Branko Collin @ 2:09 pm
TV music channel TMF (The Music Factory, owned by MTV) recently announced plans to include all downloads in the computation of its new hit parade called Superchart, both from legal and illegal sources. This week the station cancelled those plans, according to NRC (Dutch). Counting paid downloads in hit parades is a relatively new phenomenon. Two years ago, in April 2006, Gnarls Barkeley were the first act to top a major (UK) hit parade on the strength of downloads.
NRC lists no reason why TMF would change the format of their chart at the last minute, other than that the station considers downloading from an illegal source to be "wrong". NVPI, Dutch representatives of the record industry, applaud TMF's decision. "You are sending a fatal message if you count all downloads for your hit parades," Wouter Rutten said. "It would be as if the music industry had accepted downloads from an illegal source." Oh my.
(Why the unwieldy "downloads from an illegal source"? Because the Netherlands, like Canada and a few other countries, allow copies for private use. The phrase "illegal downloads", recently gaining popularity in the Netherlands, may be snappier but is also incorrect.)
Via Dagelinks (Dutch).
Tags: downloading, hit parades, record companies, TMF

redpajama_set_name: RedPajamaCommonCrawl


1. The Award is named as "Prof. Manubhai M. Shah Memorial Award for Excellence in Commerce & Business Management" (MMSMA).
2. The Award is to be given each year for outstanding contributions to the discipline & profession of Commerce & Business Management.
The Award shall comprise cash prize of Rs. 2,00,000/- (Rupees two lacs) [together with a certificate and trophy], to be awarded each year for outstanding research, fundamental or applied, of creative nature in the field of Commerce & Business Management.
1. Any citizen of India engaged in research in any field of Commerce & Business Management up to the age of Sixty (60) years as reckoned on 31st December of the year preceding the year of the Prize. Overseas Citizens of India (OCI) &/or Persons of Indian Origin (PIO) working in India (or in collaboration with Indian citizen/s if residing outside India) are also eligible.
2. The person(s), in the opinion of ICA, should have made conspicuously important and outstanding contributions to human knowledge and progress in the discipline & profession of Commerce & Business Management.


"One Fire" pre-orders and music are coming very soon!
In the meantime, Combichrist have added even more dates to their "One Fire World Tour", now visiting the UK and Europe! The North American portion of the tour begins April 8 in San Diego, CA, and will tour for two months, concluding on June 2 in Indianapolis, IN. Then, not even a month later, Combichrist will continue their international onslaught in the UK and Europe, starting in Dessel, BE on June 21. They will tour for nearly another two months, wrapping up on August 14 in Zebbug, MT.
See below for all tour dates. Tickets are available via individual venues. North American meet and greet upgrades are available here.


We are excited to offer this 2019 Honda Civic Coupe. Stylish and fuel efficient. It's the perfect vehicle for keeping your fuel costs down and your driving enjoying up. The look is unmistakably Honda, the smooth contours and cutting-edge technology of this Honda Civic Coupe Sport will definitely turn heads. The Honda Civic Coupe Sport will provide you with everything you have always wanted in a car -- Quality, Reliability, and Character. You could keep looking, but why? You've found the perfect vehicle right here. We look forward to seeing you soon! Please call us for more information.
Excludes Civic Type RSpecial APR offer valid on new and unregistered 2019 Civic Coupe Models from April 19, 2019 through April 30, 2019, to well qualified buyers on approved credit by Honda Financial Services through participating dealers. Must take new retail delivery on vehicle from dealer stock by April 30, 2019. Not all buyers will qualify. Higher rates apply for buyers with lower credit ratings. No-down-payment financing may be available for well-qualified buyers. Actual down payment may vary. Example for 2019 Civic: 0.9% for 48 months financing at $21.22 a month for every $1,000.00 financed. Dealers set actual prices. See your Honda dealer for details.
*$405/month financing for 60 months with $0 due at signing. No security deposit. Excludes, tax, titles, acquisition fee, and dealer fees. On approved credit. See dealer for more details.


text:
TONIGHT: FLORIDA STATE AT N.C. STATE
WHEN/WHERE: 8, Entertainment and Sports Arena, Raleigh, N.C.
TV/RADIO: Ch. 32; WDAE-AM 620.
RECORDS: Florida State _ 8-10, 3-4. North Carolina State _ 14-4, 4-3.
COACHES: Florida State _ Steve Robinson (39-41, third season; 85-59 overall). North Carolina State _ Herb Sendek (67-48, fourth season; 130-74 overall).
KEY PLAYERS: Florida State _ Ron Hale, G/F, 6-9 Sr. (17.4 ppg, 5.4 rpg); Damous Anderson, F, 6-7 Sr. (14.4 ppg, 4.3 rpg); Delvon Arrington, PG, 5-11 Jr. (8.6 ppg, 6.8 apg, 4.6 rpg). North Carolina State _ Anthony Grundy, G, 6-2 So. (13.4 ppg, 5.0 rpg); Damon Thornton, F, 6-8 Jr. (10.5 ppg, 7.5 rpg); Damien Wilkins, F, 6-6 Fr. (9.7 ppg, 6.7 rpg).
NOTES: After back-to-back ACC losses (Virginia and Maryland), the Seminoles hit the midpoint of the league season tonight. Although they have lost four of their past five overall, they are 2-2 in league road games. Hale, the former Largo High star, has been at his best on the road. He's averaged 22.8 points on 55.9 percent in four league road games. But the Wolfpack is 13-0 at home, the longest home winning streak since 1988-89. FSU continues to live _ or die _ from the perimeter; it leads the ACC in three-point shooting, 37.3 percent. The Wolfpack allows 61.4 points (first in the league) on 40.1 percent shooting. FSU leads the series 14-11; 12-7 since joining the league in 1991-92.
_ Compiled by Brian Landman
Up next:Gore's N.H. win shows he has no time to lose


4th Grade - "Meet the Writer" Phil Bildner author of "A Whole New Ball game" will visit our 4th grade students Tuesday and 4th grade parents are invited to attend as well.
1st Session at 9:50 am for 4-416 and part of 4-417. 2nd Session at 10:35 am for 4-418 and part of 4-417. If your child is in 4-417 and you would like to attend please contact me to see which session your child will be in.


Human Immunodeficiency Virus (HIV-1) afflicts nearly 38 million individuals worldwide (Joseph et al., 2013; "WHO | HIV/AIDS," 2016). Despite the reduction in disease mortality due to increased use of antiretroviral medication, HIV-1 associated neurocognitive disorder (HAND) affects approximately 50% of HIV infected individuals (Antinori et al., 2007; Castellon, Hinkin, Wood, & Yarema, 1998; Castelo, Sherman, Courtney, Melrose, & Stern, 2006; Cysique & Brew, 2009; Heaton et al., 2011, 2015). The brain itself is particularly sensitive to HIV-1 related viral proteins and viral infection (Masliah, DeTeresa, Mallory, & Hansen, 2000), thus, it is vital to empirically examine potentially effective therapeutics which may be capable of improving cognition in HIV-1 patients. In the contemporary literature, cognitive deficiencies encompassed by HAND include deficits in: attention/information processing, language, abstraction-executive function, complex perceptual motor skills, memory (short-term and working memory), learning and recall, simple motor skills and sensory perceptual abilities, as defined by the most recent HIV-1 nosology (Antinori et al., 2007).
Therapeutics capable of improving neurocognitive dysfunction in the HIV-1 brain has yet to be established; therefore, the current study examined a potential therapeutic theoretically capable of improving HAND related cognitive dysfunction: physical activity. Physical activity has been shown to be the strongest environmental factor capable of promoting the genesis of new neurons in the subgranular zone of the hippocampal dentate gyrus (Fuss et al., 2014; Ji et al., 2014; Klein et al., 2016; M.-H. Lee et al., 2013; Naylor et al., 2008; van Praag, Christie, Sejnowski, & Gage, 1999; van Praag, Kempermann, & Gage, 1999; van Praag et al., 2002; van Praag, Shubert, Zhao, & Gage, 2005; Vivar & van Praag, 2013). Furthermore, when examining the relationship between physical activity and HIV-1 associated cognitive decline, there appears to be an association between acute physical activity and cognitive function in human HIV-1+ patients (Dufour et al., 2013, 2018), evidence which suggests physical activity may be capable of preserving/promoting cognitive function in the HIV-1 brain. The current study determined whether promoting neurogenesis through physical activity can act as a neuroprotective/neurorestorative therapeutic agent capable of attenuating the progression of HIV-1 cognitive pathology. Upon completion of the current study, the role of chronic HIV-1 viral protein expression on dentate gyrus neurogenesis in the HIV-1 transgenic (Tg) rat brain was empirically established. The current results provide evidence that HIV-1 viral proteins do inhibit neurogenesis (as determined by doublecortin immunolableling), and that wheel running did not significantly increase neurogenesis. However, wheel running significantly increased dendritic spine length, volume and head diameter, as well as dendritic length. These results suggest that physical activity may be an effective therapeutic for improving HIV-1-dependent neurological synaptodendritic damage due to the expression of HIV-1 viral proteins.


text:
School mourns popular teacher
Staff, pupils and parents at a Coventry primary school are coming to terms with the sudden death of its popular deputy head teacher.
Tracy Henderson had been at Howes Primary school, in Palermo Avenue, Cheylesmore, for two years.
Miss Henderson, who lived in Coventry, died suddenly aged just 37. It is not known what caused her death.
Head teacher Pauline Davies said: "Staff, children, governors and parents are all deeply shocked and upset at the sudden death of their deputy head teacher Tracy Henderson.
"Tracy played a major part in the life of the school and will be sadly missed by everyone who had the privilege to work with her.
"Currently the school team is working to support both each other and the children through this very difficult time.
"Obviously the school will be looking at holding a service of celebration to recognise the part Tracy played in the life of the school."
Members of Coventry City Council's educational psychology team are at the school advising teachers on how to help children deal with the shock.
Plans are being made for a new smaller school building to replace the existing ageing facilities.
Mrs Davies said staff were now thinking of a way to create a permanent memorial to Miss Henderson in the new school building.


Every company today is looking to recruit and retain excellent talents. But in most organizations, a chunk of newly recruited employees themselves resign or are terminated by the company. According to a study by Aberdeen Group, within the company, 86 percent of the workers prefer to stay or leave the company within the first six months of their service, and 69 percent more likely to stick to the company for at least three years.
The employee terminations or resignations will slow down the overall performance of the company and increase the expenses due to the rehiring process. But the recent digitalization of the workforce in companies has completely disrupted the status of the human resource management. Onboarding programs have created an interactive learning experience that increases information sharing over a period of time.
Today, employees do not want to work in a situation where they just receive their salary and have a place to work; they want to involve more with the work and within the organization. For this purpose, popular companies like Deloitte, Pepsi, and PwC have implemented gamification techniques for staying ahead of their competition. Gamification deals with taking elements from games to create an interactive employee experience. Generally, video gamers are considered as unproductive and lazy with no future goal—the opposite of what companies want to use it for.
A productive gamification process contains several features like progress tracking, frequent feedback, linking goals with development, achievements and rewards, and perfect timings on the delivery of information to avoid information overload. The most effective benefit that companies can get is to keep their employees motivated and satisfied while they also learn new concepts, and this will result in productive goal achievements.
A gamified approach ensures a greater employee retention rate as it giving a sense of independence, and they are also assisted while performing various tasks. The new generation of employees actually wishes to be a part of the organization's journey. They need to believe that they are contributing to the business and playing a vital role in the organization's success. Many of the companies are resistant to implement gamification due to lack of knowledge about the productivity and capability of the technology. However, those enterprises that understand its potential are those that will win over the marketplace.


text:
Part 1, Chapter 1 Part 1, Chapter 2 Part 1, Chapter 3 Part 1, Chapter 4 Part 1, Chapter 5 Part 1, Chapter 6 Part 1, Chapter 7 Part 1, Chapter 8 Part 1, Chapter 9 Part 1, Chapter 10 Part 1, Chapter 11 Part 1, Chapter 12 Part 1, Chapter 13 Part 1, Chapter 14 Part 1, Chapter 15 Part 1, Chapter 16 Part 1, Chapter 17 Part 2, Chapter 1 Part 2, Chapter 2 Part 2, Chapter 3 Part 2, Chapter 4 Part 2, Chapter 5 Part 2, Chapter 6 Part 2, Chapter 7 Part 2, Chapter 8 Part 2, Chapter 9 Part 2, Chapter 10 Part 2, Chapter 11 Part 2, Chapter 12 Part 2, Chapter 13 Part 2, Chapter 14 Part 2, Chapter 15 Part 2, Chapter 16 Part 2, Chapter 17 Part 3, Chapter 1 Part 3, Chapter 2 Part 3, Chapter 3 Part 3, Chapter 4 Part 3, Chapter 5 Part 3, Chapter 6 Part 3, Chapter 7 Part 3, Chapter 8 Part 3, Chapter 9 Part 3, Chapter 10 Part 3, Chapter 11 Part 3, Chapter 12
All Themes Guilt, Responsibility, and the Holocaust Secrets, Indifference, and Emotional Distance Generational and Parent-Child Conflict Reading and Illiteracy The Image as Memory and the Gaze
All Characters Michael Berg Hanna Schmitz (Frau Shmitz) Michael's Father The Jewish Woman / The Daughter The Prison Warden The Driver The Judge Gertrud Michael's mother Michael's older brother
All Symbols Building on Bahnhofstrasse Cassette Tapes The Tea Tin
Instant downloads of all 1010 LitChart PDFs (including The Reader).
Part 1, Chapter 1
Part 1, Chapter 10
Guilt, Responsibility, and the Holocaust
Secrets, Indifference, and Emotional Distance
Generational and Parent-Child Conflict
Reading and Illiteracy
The Image as Memory and the Gaze
Hanna Schmitz (Frau Shmitz)
Michael's Father
The Jewish Woman / The Daughter
The Prison Warden
Michael's mother
Michael's older brother
Building on Bahnhofstrasse
The Tea Tin
The Reader Part 2, Chapter 17 Summary & Analysis
LitCharts assigns a color and icon to each theme in The Reader, which you can use to track the themes throughout the work.
While the other defendants receive terms in jails, Hanna is sentenced to life. The courtroom is full and loud the day the verdict is to be announced. When the defendants appear, a hush falls over the crowd as they whisper to each other, "Look!"
The crowd in the court voyeuristically watches the verdict, making a spectacle of the defendants' fates.
Hanna is dressed in a black suit with a white shirt, which makes it look as if she is a uniform. Though Michael had never seen the SS uniform for women, he and the other spectators strongly associate Hanna's clothes with the SS. Outraged, the spectators whisper to each other and soon begin shouting out at her. While the verdict is announced, Michael stares at Hanna, who "looked straight ahead and through everything" with "a proud, wounded, lost, and infinitely tired look."
The crowd takes voyeuristic pleasure in condemning Hanna, who does not seem to understand the impression that her appearance gives to the court. Despite the crowd's jeering, Hanna tries to maintain the professional demeanor that she had upheld as a Nazi prison guard and that hindered her defense. It's suggested that her "infinitely tired" look comes from the years spent guarding her secret.
Lee, Sophia. "The Reader Part 2, Chapter 17." LitCharts. LitCharts LLC, 9 Mar 2017. Web. 14 Jul 2019.
Lee, Sophia. "The Reader Part 2, Chapter 17." LitCharts LLC, March 9, 2017. Retrieved July 14, 2019. https://www.litcharts.com/lit/the-reader/part-2-chapter-17.


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text:
Microfluidic chip device identifies bacteria types
By Bridget Borgobello
Microfluidic chip device ident...
A team of biomedical engineers at Taiwan's National Cheng Kung University has created a new on-chip method to identify bacteria
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A team of biomedical engineers at Taiwan's National Cheng Kung University has created a new "on-chip" method to identify bacteria. By creating microchannels between two roughened glass slides containing gold electrodes, the researchers are able to sort and concentrate bacteria. A form of spectroscopy is then applied to identify them, providing a portable device that can be used for tasks like food monitoring and blood-screening.
The team, led by Hsien-Chang Chang, a professor at the Institute of Biomedical Engineering and the Institute of Nanotechnology and Microsystems Engineering.
A tiny electric field is applied to the specially designed microfluidic chip to separate the bacteria (a phenomenon known as dielectrophoresis). A roughened metal shelter in front of the trapping electrode enhances the collection process.
The identification technique relies on "surface enhanced Raman spectroscopy". Raman spectroscopy. In layman terms, when electrically stimulated, the different components on the surface of a bacteria strand attach themselves to the gold electrodes, creating different wavelength peaks which then form a spectral signature.
This spectral signature or "fingerprint" can then be used to identify different strands or families of bacteria. "In the future, different species of fungi could also be sorted based on their different electrical or physical properties by optimizing conditions such as the flow rate, applied voltage, and frequency," continued Chang. "This portable device could be used for preliminary screening for the pathogenic targets in bacteria-infected blood, urethral irritation, and of raw milk and for food monitoring."
The report on Professor Chang's new microfluidic chip was published in the American Institute of Physics' (AIP) journal Biomicrofluidics.
ScienceMEMSBacteriaChipMicrofluidicMicrochipResearch
Bridget Borgobello
Bridget is an experienced architecture, travel and design writer who has been contributing to New Atlas since 2010. Based between Melbourne and Rome, she and has a keen eye for innovative design, green technology and space saving solutions. Bridget is fluent in Italian and enjoys covering major events in Italy, including the Milan Design Week and Venice Biennale.


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text:
Posted inEnvironment, Featured, News
Edison says it may have sparked Woolsey Fire
Southern California Edison says it's likely its equipment caused a wildfire last year that killed three people and destroyed more than 1,600 homes and other buildings.
The Woolsey Fire in November burned from north of Los Angeles south through Malibu to the sea.
In its quarterly earnings report released Tuesday, Southern California Edison said that Ventura County Fire Department investigators determined the company's equipment sparked the blaze.
Southern California Edison says that unless there's other evidence, the utility "believes that it is likely" its equipment was responsible. Last year, the company told the state Public Utilities Commission only that its equipment might have caused a power outage before the blaze started.
The utility is facing lawsuits from relatives of fire victims blaming it for the blaze.
Electrical equipment has been linked to several of California's recent devastating fires.
Branch caused Getty Fire
Officials say a tree branch striking a power line ignited a wildfire that destroyed a dozen homes in a star-studded area of Los Angeles this week.
The Department of Water and Power said Tuesday that strong winds drove the branch into the line, causing it to arc and spark the fire.
The fire that ignited on a hillside near the J. Paul Getty Museum drove celebrities like LeBron James and Arnold Schwarzenegger from their homes.
The blaze is only smoldering but about 10,000 people remained under evacuation orders as firefighters warned that hot, gusty Santa Ana winds were expected to return Tuesday night.
Meanwhile, Southern California Edison announced Tuesday that it believes its equipment caused the Woolsey fire last year north of Los Angeles that killed three people and destroyed more than 1,600 homes and other buildings.
California utility faces $550M in penalties for 5 wildfires
17 people impacted by the Woolsey fire sue Southern California Edison
LOS ANGELES – Los Angeles County sues utility over fall wildfire damage
Tagged: Getty fire, Public Utilities Commission, southern california edison, Ventura County Fire Department, woolsey fire


text:
Jasper Cho talks about Song Joong-ki and Song Hye-kyo on Radio Star
Jasper Cho talked about Song Hye-kyo and Song Joong-ki.
He appeared in the MBC TV show "Radio Star" and talked about the drama he worked on with Song Hye-kyo and Song Joong-ki.
Jasper Cho starred in "Descendants of the Sun" which also made the Song-Song couple possible. Jasper Cho took on the role of Daniel and spoke in fluent English.
The MC's asked if he knew about Song Joong-ki and Song Hye-kyo then but he said, "I didn't know. Kim Gu-ra said he wasn't that close to them and he agreed. However, he did say something about work dinner.
He said he overheard the director saying, "Be sincere and give it a try". Song Joong-ki replied, "I already am".
Source : biz.heraldcorp.com/vi...
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(태양의 후예 - 2016)
[Spoiler] "Ruler: Master of the Mask" L's mask comes off and falls to the ground
"L"'s mask fell off and he fell, too. On the latest episode of the MBC drama "Ruler: Master of th,...More
[Spoiler] "Queen for 7 Days" Lee Dong-gun goes crazy, rips off Go Bo-gyeol's clothes
Yeon San-gun's (Lee Dong-gun) madness exploded and he ripped off Go Bo-gyeol's clothes. On the la,...More
[Spoiler] "Suspicious Partner" Nam Ji-hyun and Ji Chang-wook kiss
Ji Chang-wook and Nam Ji-hyun reunited with a kiss and Dong Ha turned out to be an attacker in a g,...More


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text:
Recovery is on as house prices rise in Longford
Jessica Thompson
jessica.thompson@longfordleader.ie
House prices continue to rise in Longford
The new year is certainly off to a good start in Longford, with local auctioneers feeling optimistic about the county's recovery.
The optimism comes as a result of a daft.ie housing report, published yesterday morning (Tuesday), that states housing prices have risen by almost 20% in the county since the same time last year - that's the highest increase in the country by a long shot.
"Things are definitely on the up, there's no question about it," local auctioneer, Fintan McGill told the Longford Leader yesterday morning, pointing out that Sherry Fitzgerald McGill have just acquired some high end Longford homes worth €400,000 - something that would have been unheard of this time last year.
Furthermore, Mr McGill is convinced it's time for more development in the area, and that Longford's ease of access to Dublin is something that should be used to the county's advantage.
"I think there's definitely an opening for building to start again in Longford.
"There are eight or nine trains to Dublin daily and while the N4 extension won't come for another couple of years, we're in a great location for people going to Dublin."
In fact, he added, with such high housing prices in the capital, Longford is a prime location for buyers.
"It would be great if we could get an express train between Longford and Dublin," he said.
"Prices in Dublin are mad. I don't know how anyone could save up for a home while paying rent in Dublin."
Another Longford auctioneer, Padraic Davis, agrees that there's a definite recovery on, but it's a slow one because, despite the 19.5% increase in housing prices, Longford prices are still the second lowest in the country.
"It's good to see that there's a bit of recovery happening," said Mr Davis.
"We're definitely heading in the right direction but there's still a long way to go and I don't think developers will come in and start building here yet with these low prices.
"But prices will continue to go forward and we'll start to see more of a recovery and, in the next two to three years, I think developers will start to build in Longford again."
The average house price in Longford is now €129,000. That's 53% above its lowest point.
Housing prices nationally rose by more than €20,000 on average during 2017, according to the latest House Price Report released by property website, Daft.ie.
With prices stable in the final quarter of the year, this means that the average price was almost €241,000. That's 9.2% higher than a year ago.
For the full housing report and an analysis by Trinity College Dublin economist, Ronan Lyons, see:
House prices rise by 19% in Longford - average house price is now €129,000


This is not your normal archery podcast... Professional archer and industry insider Greg Poole discuss all things archery and more! Including Tuning, hunting, industry news and tournament results along with anything else interesting that comes up. Greg's experience and perspective will make for some interesting conversations as he approaches the industry very differently.
BJM's Greg Poole is joined by Braden Gellenthien and Danny McCarthy to talk about the NEW Mathews TRX 38. Braden & Danny discuss the Top Hat system, Arrow rest location, Stabilization and their preferred tuning methods.


text:
Illinois Moves Toward a Budget but Warns It Will Likely Miss Deadline
Looming threat of seeing its debt downgraded to junk status
Quint Forgey
Updated June 30, 2017 8:10 pm ET
Illinois officials took promising steps toward resolving a two-year standoff over a budget, but alerted rating firms that they will likely miss a deadline of midnight Friday that could trigger a downgrade to junk status.
The state's House of Representatives voted Friday in support of a Democratic spending plan introduced by Rep. Greg Harris, one that is largely viewed as a compromise. But how to fund it is still being hashed out in the legislature.


text:
app.controller('angelCafeReservationListCtrl', function ($scope, AngelReservation, toastr) {
  var vm = this;
  AngelReservation.all().then(function (d) {
    vm.reservations = d.data
  })

  vm.add = function () {
    var data = { user_Id: 'user01', product_type: 'angelTalk', payment_method: 'credit_card' }
    AngelReservation.add(data).then(function (d) {
      console.log(d)
    }, function (err) {
      console.log(err)
    })
  }

  vm.update = function (extend, extendValue) {
    console.log('update', extend, extendValue)
    // toastr.warning('일정을 삭제했습니다.');
    console.log((vm.selected));
    var selected = Object.keys(vm.selected);
    // console.log(JSON.stringify(vm.selected));
    // var an_obj = { 100: 'a', 2: 'b', 7: 'c' };
    // console.log(Object.keys(an_obj)); // console: ['2', '7', '100']

    for (var i = 0; i < selected.length; i++) {
      console.log(selected[i])
      for (var j = 0; j < vm.reservations.length; j++) {
        if (vm.reservations[j].reservation_id === selected[i]) {
          if (extend === 'day') {
            console.log(vm.reservations[j].service_end)
            var service_end = moment(vm.reservations[j].service_end).add(extendValue, 'd').format()
            // console.log(service_end, vm.reservations[j].reservation_id)
            vm.reservations[j].extend_day.push({extend:'day', date:new Date(), extend_value: extendValue})
            var data = {
              reservation_id: vm.reservations[j].reservation_id,
              service_end: service_end,
              extend_day: vm.reservations[j].extend_day,
            }

            console.log(data);

            AngelReservation.update(data).then(function (d) {
              console.log(d)
              toastr.success('작업을 저장했습니다.');
            }, function (err) {
              console.log(err)
            })

          } else {
            var service
          }
        }
      }
    }

  }

  vm.getExtendDay = function(extendDays) {
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    for (var i=0; i < extendDays.length; i++) {
      days = days + extendDays[i].extend_value;
    }
    return days === 0 ? '-' : days
  }

  vm.getRemainingDay = function(item) {
    var days = moment(item.service_end).subtract(item.service_end, 'd').format('d')
    var end = moment(item.service_end)
    var start = moment(item.service_start)
    var now = moment(new Date()).subtract(1, 'd')
    var days = end.diff(start, 'days')
    var remaining = end.diff(now, 'days')
    var result = remaining + '/' + days
    if (item.product_type === 'ring') result = '-'
    return result
  }

})

redpajama_set_name: RedPajamaGithub