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You are here: Home / News Well / Second suitor cedes the field early to Zimmer | Medtech Wall Street news for the week of September 15, 2014
Second suitor cedes the field early to Zimmer | Medtech Wall Street news for the week of September 15, 2014
September 18, 2014 By MassDevice Leave a Comment
Second suitor ceded early to Zimmer in chase for Biomet
September 12, 2014 by Brad Perriello
In the early days of Zimmer's courtship of Biomet, a 2nd suitor emerged who eventually ceded the field to concentrate on "internal projects," according to a regulatory filing.
And Biomet played hard-to-get, pursuing plans for an IPO until very late in the game and holding out for a higher valuation from Zimmer, according to the filing, which offers a detailed look at exactly how the deal went down. Read more
Kimberly-Clark readies Halyard Health medical device spinout
With the spinout of Kimberly-Clark's former K-C Health Care medical device division slated for Nov. 1, MassDevice.com sat down with Chris Lowery, the Kimberly-Clark executive who's in line to become the COO of the new company, Halyard Health.
Alpharetta, Ga.-based Halyard, which threw off $1.6 billion in sales last year as K-C Health Care, does about 30% of its business in medical devices and the rest in surgical and infection-prevention products. Lowery, who's vice president of sales and marketing for K-C Health Care until the spinout goes live, told us that Halyard is well-positioned to take advantage of the new healthcare landscape's focus on cost reduction and outcomes. Read more
InVivo's stock drops as ex-CEO dumps shares
September 11, 2014 by Arezu Sarvestani
As if InVivo Therapeutics wasn't having a tough enough time already, the company's stock is under even more pressure as former CEO Frank Reynolds has been liquidating his position over the last few weeks.
NVIV shares were down about 6% today to trade at 64¢ apiece as of about 1:55 p.m. EST. The stock has dropped more than 40% over the last 3 months and is down nearly 70% since the start of 2014. Read more
Mevion Medical files for $69M IPO
Mevion Medical registered for a $69 million initial public offering as it gears up to commercialize its proton therapy system.
The Littleton, Mass.-based company has sold 1 of its Mevion S250 radiation therapy devices to date, according to a regulatory filing. That sale, to the Siteman Cancer Center at Barnes-Jewish Hospital in St. Louis, brought in $7.6 million in revenues for Mevion during the 2nd quarter, according to the filing. Read more
ReWalk Robotics prices IPO at $36M, below range
ReWalk Robotics priced its initial public offering below its forecast range, at $12 per share, grossing some $36.0 million for its exo-skeleton suit.
ReWalk, formerly known as Argo Medical Technologies, initially forecast a range of $14 – $16 per share for the 3.4-million-share IPO. That would have raised $47.6 million to $54.4 million; instead, at $12 apiece for 3 million shares, the offering brought in $36 million, according to a regulatory filing. Read more
Filed Under: News Well, Wall Street Beat Tagged With: Avanos Medical (formerly Halyard Health), Biomet, InVivo Therapeutics, Kimberly-Clark Worldwide Inc., Mevion Medical Systems, ReWalk Robotics, Zimmer Biomet
Major Texas health system will use CHF Solutions' Aquadex FlexFlow system
Johnson & Johnson planning a robotic surgery reveal in May
Bayer and Exscientia partner to bring AI to drug discovery
Outgoing Medtronic CEO Ishrak to chair Intel's board
FDA clears Verily Study Watch for additional capabilities
Teleflex wins FDA clearance for Wattson temporary pacing guidewire
Abbott Q4 sales beat The Street
Invo Bioscience signs Indian distribution deal
CardioFocus names new CEO
TransEnterix scores another leasing agreement for Senhance robot
Johnson & Johnson misses the mark on Q4 revenue
Onkos Surgical partners with Integrum for OPRA Implant System
Miach names new VP of manufacturing
Vyaire Medical appoints new CEO
Robocath performs first robotic coronary angioplasties in Germany
BREAKING: Medtronic wins FDA approval for Micra AV
Ra Medical Systems wins FDA's OK to study new uses for Dabra system
From Medical Design & Outsourcing
Heraeus Medical Components and Myant partner on electrical sensing for textiles
Heraeus Medical Components (St. Paul, Minn.) and Toronto-based Myant have entered a partnership enabling Myant to use Heraeus' Tectitoat for electrical sensing applications in textiles, the companies announced today. Tecticoat is a conductive polymer-based coating that can be applied to textiles to control electrical conductivity, electromagnetic shielding and electrostatic dissipation, making it suitable for integration… […]
Cook Medical's peripheral artery set debuts in U.S.
Cook Medical recently announced the U.S. launch of its TriForce peripheral crossing set to support vascular obstruction procedures. The TriForce set is designed to be percutaneously introduced into blood vessels to support a wire guide while performing a peripheral intervention, according to the Bloomington, Ind.-based company. This device is also intended for injection of radiopaque… […]
Bayer (ETR:BAYN) announced that it is entering into a collaboration agreement with artificial intelligence drug discovery company Exscientia to identify and optimize novel lead structures for potential drug candidates in treating cardiovascular and oncological diseases. The agreement, announced earlier this month, is slated to see the companies work together on early research projects combining Exscientia's proprietary… […]
GHO Capital acquires Ardena
European specialist investor Global Healthcare Opportunities, also called GHO Capital Partners, recently announced that it has acquired Ardena — a specialist contract development and manufacturing organization focused on early phase drug development. Financial terms of the deal, announced Jan. 9, were not disclosed. Get the full story on sister site Drug Discovery and Development. The […]
Albright Silicone launches 3D printed tooling for silicone molding
Albright Silicone (Leominster, Mass.) recently announced that it has added 3D printed tooling for LSR molding, touting the relative low coast and rapid turnaround the process offers for prototyping. "This capability of 3D printing and molding LSR is a helpful solution to customers' problems when trying to develop and prove a concept before investing in… […]
Medtronic (NYSE:MDT) has won FDA approval for its Micra AV — greatly expanding the number of people who could potentially benefit from leadless pacemaker technology. The medical device giant plans to start offering the Micra AV in a limited number of implanting centers in the coming weeks, with a full launch expected in the spring. FDA… […]
FDA reclassifies some medical image analyzers
The FDA today imposed stricter regulations on certain radiological medical image analyzers, reclassifying them from Class III to Class II. Affected products include computer-assisted detection (CADe) devices for breast cancer mammography, breast-lesion ultrasound, and lung-nodule and dental-caries radiography, the agency said. It defines these devices as those intended to identify, mark, highlight, or in any… […]
Medline Industries temporarily halts EtO sterilization at Illinois plant
This article has been updated with a comment from Medela. Medline Industries has temporarily closed its Waukegan, Ill., medical device sterilization operation to install nearly $10 million in emissions upgrades. The privately owned company uses the carcinogenic gas ethylene oxide (EtO) to sterilize its own and other companies' devices at the plant. Medline did not… […]
Mojo Vision developing 'smart' contact lens
Mojo Vision is working with the FDA to develop a smart contact lens to help people with low vision. The lens overlays real-time contrast and lighting enhancements with zoom functionality and recently won FDA breakthrough device designation. "Receiving the Breakthrough Device Designation is a significant step in our research and development process. We look forward to… […]
FDA to EPA: Leave us out of your ethylene oxide rule
This article has been updated with comments from the FDA. The FDA has asked the Environmental Protection Agency to leave the FDA out of its proposal for stricter regulation of ethylene oxide (EtO) emissions, and the EPA complied. In an interagency comment on the EPA's proposed rule governing commercial EtO users — which includes medical… […]
Clippart debuts stepper-controlled flow valve
Clippard recently launched a new stepper-controlled proportional valve for precision flow control. The Eclipse valve uses the industry's most robust and powerful miniature linear actuator, according to Cincinnati-based Clippard. The patent-pending Eclipse is designed for liquid and gas delivery, medical, analytical and industrial automation requiring ultra-fine resolution and repeatability. The design also allows for custom… […]


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Евге́ний Оле́гович Боля́кин () — казахстанский и российский профессиональный хоккеист, защитник. Игрок клуба «Номад», выступающего в чемпионате Казахстана.

Биография
Евгений Олегович Болякин родился 30 апреля 1990 года в городе Караганде Карагандинской области Казахской ССР, ныне Республика Казахстан. Сын Олега Владимировича Болякина — хоккейного тренера.

Е. О. Болякин — воспитанник карагандинского хоккея.

Окончил Университет имени Лесгафта.

Играл в чемпионате Казахстана и нескольких лигах чемпионата России.

В КХЛ провел 22 игры.

В 52 играх, проведенных в МХЛ, забил 3 шайбы и сделал 15 передач.

В 64 играх, проведенных в ВХЛ, забил 3 шайбы и сделал 7 передач.

В 2 играх, проведенных в высшей хоккейной лиге за «Сарыарку», сделал результативную передачу.

В 113 играх, проведенных в 1 лиге чемпионата России, забил 3 шайбы и сделал 18 результативных передач.

В чемпионате Казахстана провел 30 игр, забил 1 шайбу и сделал 5 голевых передач.

Играл в молодёжных сборных (до 18 лет и до 20 лет).

С 5 октября 2015 года игрок клуба «Номад».

С лета 2017 года игрок клуба «Бейбарыс».

С 18 октября 2019 года игрок клуба «Номад».

Ссылки

Выпускники Университета имени Лесгафта
Хоккеисты Казахстана
Хоккеисты КХЛ
Игроки ХК «Казахмыс»
Игроки ХК «Иртыш»
Игроки ХК «Амур»
Игроки ХК «Сарыарка»
Игроки ХК «Спартак» Москва
Игроки МХК «Спартак»
Игроки ХК «Торпедо» Усть-Каменогорск
Игроки ХК «Зауралье»
Игроки ХК «Алматы»
Игроки ХК «Номад»
Игроки ХК «Бейбарыс»

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The Story of Dr Maya Rao
THE DANCE INDIA
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News Trending
August 8, 2021 August 15, 2021 The Dance India #Azadi ka Amrit Mahotsav, #cultural minister, #Kishan Reddy, #National Archives, #Partha Sarthi Sen Sharma, #Quit India Movement, #Rohit Kumar Singh, #thedanceindia, #Union Minister of Culture, #Vikram Goud Bathina, #vikramkuma br, Exhibition to mark the 79th anniversary of 'Quit India Movement' inaugurated as part of Azadi ka Amrit Mahotsav #celebration
Time to say Quit India to Poverty, Inequality, Illiteracy & Terrorism: Cultural Minister
Union Minister of Culture, Tourism, and Development of North Eastern Region (DoNER) Shri G. Kishan Reddy inaugurated an exhibition to mark the 79th anniversary of the 'Quit India Movement' at National Archives of India in New Delhi today in presence of Ministers of State for Culture Shri Arjun Ram Meghwal and Smt Meenakshi Lekhi .
The exhibition on 'Quit India Movement' has been put up at the National Archives of India as part of 'Azadi Ka Amrit Mahotsav' being celebrated to commemorate 75 years of Independence. Secretary Culture, Shri Raghvendra Singh; Director General, NAI Shri Chandan Sinha; Additional Secretaries in Culture Ministry Shri Rohit Kumar Singh and Shri Partha Sarthi Sen Sharma; Joint Secretaries, Ms. Amita Prasad Sarbhai, Ms. Lily Pandeya and other officials of Ministry of Culture and National Archives were also present during the inauguration event.
An attempt has been made in this exhibition to depict the importance of the Quit India Movement in India's freedom struggle through public records, private letters, maps, photographs and other relevant material. The exhibition will be open to the public from August 9 from 10 am to 5:30 pm till November 8, 2021.
Addressing the media after a detailed tour of the exhibition, Shri G. Kishan Reddy said that the independence struggle is gilded with golden chapters of unity, strength and determination and one such proud event was the Quit India Movement and how even almost eight decades later, the movement stands as a shining example of power of the masses. It will remain so for many more decades to come, he added.
The Minister spoke about India celebrating the 75th year of Independence through events organized under the Azadi Ka Amrit Mahotsav theme. The events commenced in March this year which started a 75 week countdown to our 75th anniversary of Independence and will end post a year on 15th August, 2023. "This is a moment to not only recognize the contribution of a generation in freeing our nation from colonial powers but also to recognize those who played a pivotal role in preserving our civilization heritage for more than 750 years. There are many unsung heroes who need to be recognized for the selfless services they rendered to Bharat Mata" he added.
Shri Kishan Reddy also said that AzadiKaAmritMahotsav celebrates the sentiment of oneness and freedom, as we all together celebrate 75 years of independence. Shri Kishan Reddy requested the media to also support the government's initiative of propagating the message of oneness and the Prime Minister's vision of seeing an India 25 years from now driven forward by today's youth "The Prime Minister has often spoken about how this event will also spur the youth to envision an India in 2047", he added.
Shri Reddy also encouraged all people to participate in the Azadi Ka Amrit Mahostav and make it a people's festival. "Azadi Ka Amrit Mahostav is not a government event but is envisioned as a celebration by the masses that will see participation from every Indian. People from all regions, all languages and across the political spectrum will participate to make this event a grand success", he explained.
Earlier, signing the visitor register after inaugurating the exhibition on Quit India Movement, Shri Kishan Reddy wrote, "The template for the Quit India Movement is relevant even today as we commemorate the 79th year of the struggle. In 1942 Mahatma Gandhi's Quit India drove out the colonial forces. In today's New India, as shared by the Prime Minister last year, we can pledge to wipe out poverty, inequality, illiteracy, open defecation, terrorism, and discrimination and say Quit India to these evils".
The Union Minister and his counterparts also encouraged everybody to sing the National Anthem and upload their videos at www.rashtragaan.in. "I am pleased to share that as a part of 'Azadi Ka Amrit Mahotsav' celebrations, the Ministry of Culture is running a first of its kind crowd sourced 'Rashtra Gaan' campaign, where-in one can sing our national anthem and upload its video recording on rashtragaan.in. All such videos will be compiled and telecast live this Independence Day. I request you to be a part of this unique unifying event by uploading your video while singing our national anthem on www.rashtragaan.in ", he said. The ministers also used the occasion to sing the national anthem and upload their videos.
Throwing light on the history related to this exhibition, Shri Arjun Ram Meghwal said that after the arrest of other senior leaders including Mahatma Gandhi, the Quit India movement had spread spontaneously across the country. During that time, the command of the movement passed into the hands of the youth like Ram Manohar Lohia, Aruna Asaf Ali, Jayaprakash Narayan among others. The youth of 1942, with their leadership and public participation, turned the challenge into an opportunity and forced the British to leave the country. The team of National Archives of India deserves congratulations for organizing this exhibition, Shri Meghwal said.
Smt Meenakshi Lekhi said that the Quit India Movement was an important milestone in the Indian freedom struggle. Under the leadership of Mahatma Gandhi, people all over India came together to overthrow imperialism. On this day in 1942, Gandhi gave the slogan 'Do or Die' to all Indians to drive out the British from the country. We got freedom only when the common people of the country joined this movement. Today, the spirit of the freedom movement is being highlighted so that the youth and coming generations will know about the sacrifices made by our countrymen at that time, Smt Menakshi Lekhi said.
The exhibition has several segments which outline the circumstances leading to the Quit India Movement, how it became a mass movement, the heroes of Quit India, impact on the ground, imprint of the movement , atrocities by the colonial rulers and its consequences among others.
The Quit India Movement was started by Mahatma Gandhi on August 8, 1942, during the Second World War, demanding an end to British rule in India.
The dignitaries spent significant time at the poem on the Quit India Movement penned by the former Prime Minister Shri Atal Behari Vajpayee which was published in the Abhyudaya, a newspaper associated with Shri Madan Mohan Malviya, in 1946 and appreciated famous lines in the poem "कोटि कोटि कंठों से निकला भारत छोड़ो नारा, आज ले रहा अंतिम सांस ये शासन हत्यारा" which brought out the essence of the Quit India Movement.
Quit India Movement, 1942 is significant especially because it brought home to the British that it would not be possible to continue to govern India and forced them to think of ways they could exit the country. The Movement was accompanied by a mass protest on non-violent lines by which Mahatma Gandhi called for "an orderly British withdrawal; from India." Through his speeches, Gandhi moved people by proclaiming that "every Indian who desires freedom and strives for it must be his own guide…" Launching the movement on 8th August 1942 Gandhiji declared in his immortal "Do or Die " speech, "Let every Indian consider himself to be a free man"
← Exhibition on 'Quit India Movement'
Independence Day Young Achievers Award →
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How to address cyber-threats as a strategic risk
By Contributor, Thu 29 Oct 2020
Article by Fortinet regional director of A/NZ and the Pacific Islands, Jon McGettigan.
Most business leaders understand that cybersecurity is a critical business risk and that their organisation will never be immune to cyber-attacks, regardless of the size of the company or the industry in which it operates. However, understanding that the risk is real, and implementing a strategic plan to deal with that risk appropriately are two different things.
Too many organisations implement point solutions or take an incomplete approach to their cybersecurity. This results in gaps and vulnerabilities that can put the organisation at risk despite its otherwise diligent security focus. Instead, businesses should seek a solution that delivers a more holistic blanket of protection to cover all the gaps.
As businesses increasingly turn to technology for every aspect of operations, the proliferation of devices, clouds, networks, systems, applications, and more create a much larger attack surface for cyber-criminals. Threats can appear without notice, putting organisations at risk.
Becoming a cyber-secure organisation in the face of an evolving threat landscape requires a strategic, business-focused approach to security as opposed to a tactical approach in which security is addressed simply by implementing new tools.
In organisations that get cybersecurity right, the issue is treated as a priority by everyone in the business, particularly the leadership team. Since no company is immune to cyber-attacks, the most important thing a company can do is set a security-positive culture in which everyone understands and embraces their role as a protector. This awareness makes it harder for cyber-criminals to mount successful attacks.
Once there is a strong cybersecurity culture in place, the next step is for the organisation to implement the right security tools and work with a partner that can help get the best results from those tools. With the right security measures in place, it is more difficult for attackers to compromise the organisation.
Ideally, businesses need to choose a security platform, rather than a single solution, which can deliver visibility across the environment and efficiently manage both security and network operations. A security fabric can deliver an integrated solution by linking different security sensors and tools together.
This provides a more comprehensive and accurate view of the activity, traffic, and behaviour in an organisation's network in real-time. The security fabric offers end-to-end protection for the network, from endpoint devices to core systems.
The best return on investment in cybersecurity, in terms of both time and money, is that nothing happens. The security fabric approach includes various elements that work together to defend the network, share threat intelligence, expand visibility, and deliver strong security across access, client, application, cloud, and more.
Instead of trying to pull together information from disparate security tools, then build a picture of what this means for the organisation, a strategic security fabric approach puts all that information front and centre for the security team, and acts to protect the organisation from threats.
A unified management interface that provides cooperative security alerts, recommendations, audit reports, and full policy control across the security fabric will deliver peace of mind that the business's network is secure.
The alternative is that an attack is successful, in which case the company will have to spend time and money remediating the attack. Even when the technical effects of the attack have been eradicated, the company may still have to deal with reputational damage, and account for lost productivity. Remediation can, therefore, be far more expensive than prevention.
This makes cybersecurity a critical business risk rather than merely a consideration for the IT or security team. Just as organisations strategically plan to mitigate other business risks, cybersecurity should be a key discussion point at the highest levels of organisational leadership.
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ParACCEL is the latest company to announce that it is joining the data warehouse appliance mêlée. That said, and before I discuss ParACCEL, another company that is rumoured to be about to enter the market is Dataupia — more on that when it actually makes any announcements.
ParACCEL isn't actually an appliance vendor per se, though it will deliver a pre-installed system if that is what you want. In fact, the software has been designed to run on any 64-bit blade cluster. On its web site the company describes its architecture as based on memory mirroring though it is not exactly clear what that means. However, I can say that the use of in-memory processing is a substantial part of what the company will be bringing to market. Beyond that I cannot go, as I am limited by a non-disclosure agreement. I can tell you, however, that the product is based on PostgreSQL but that the company, like Netezza, is not contributing its development back to the PostgreSQL community, which effectively makes it proprietary.
This should not particularly be a surprise: the CTO of ParACCEL was previously the VP of Architecture for Netezza. The CMO was previously VP Marketing for SAND.
ParACCEL is targeting the Microsoft market and it sees itself specifically as a vendor that is complementary to existing or future enterprise data warehouses rather than replacing these. While cognisant of the fact that appliances, or virtual appliances as in this case, can be used in a variety of environments (data marts, aggregation engines and so on) the company sees its initial target market as a query accelerator sitting alongside SQL Server 2005. Initially, it is targeting something in the 500Gb to 3Tb range, though the product will scale (a lot) further.
This is not a bad strategy: Microsoft is clearly targeting the low-end warehouse market where it will surely gain traction. However, its performance, especially for analytic queries, drops off rapidly at a fairly low level, so there should be ample opportunity for ParACCEL to capitalise on this fact. Moreover, none of the other appliance or virtual appliance (or, as I have previously alluded to them: semi-appliance) vendors are targeting this market, so ParACCEL should have this space to itself, at least for the time being.
One further point of interest is that ParACCEL, which is not generally available yet, is not adopting the "let's go to market and then find customers" model, which was what DATAllegro did, for example; rather, ParACCEL is working on the basis of beta customers with whom the product can be proved, prior to coming to market.
This program is already up and running, which you might think unusual for a company that you have only just heard about. However, ParACCEL is what used to be XPrime or, rather, ParACCEL has bought XPrime's intellectual property, as well as having taken on board some of its personnel. Thus, this is not a brand new company but one that is, effectively, a couple of years along.
ParACCEL is entering a space that is getting increasingly crowded (and there is more to come) but it has a marketing model that is about making noise before it formally comes to market (unlike relatively secretive companies such as Vertica and Dataupia) and it is targeting a market sector that nobody else is addressing—that's a good starting point—we'll have to wait and see what the company makes of it.


Definite and Indefinite Articles in Spanish.
Includes Worksheets, a wall chart/poster (A4), Vocabulary List and Teacher Answers.
Includes 10 pages of exercises, a wall chart/poster (A4), Vocabulary Lists and Teacher Answers.
These activities are ideal for a Spanish 1 level class.
A chart with a summary of definite and indefinite articles in Spanish. Can be used as a wall chart or as a full page handout.
There are three smaller copies of the previous Spanish articles chart on one page with lines for cutting. This is to help save on paper.
A list of 30 Masculine Nouns and 30 Feminine Nouns in Spanish with their corresponding translation in English. These nouns appear in the worksheets.
A list of 20 Spanish adjectives in their masculine and feminine forms with their corresponding translation in English. Also there is a section with 6 colors in Spanish. These adjectives appear in the worksheets.
Complete a table (similar to our summary chart) and identify the articles from a group of words.
Complete with the correct definite and indefinite articles. The same noun is repeated four times in order to practice the definite/indefinite version and the singular/plural form.
Give examples of each type of article.
Complete with the correct articles. The first section is for LA or EL with 14 singular nouns. The second section is for LAS or LOS with 14 plural nouns.
There are 15 sentences in the simple present tense. Complete each sentence with the correct article. This worksheet can be used later as a review or as a filler once students have learned the simple present tense.
The first section contains 6 sentences about animals. Students need to complete them with the correct article. Note, one of the animals is irregular (EL gorila). The second section has 10 sentences in the simple present tense. Students need to complete each sentence with the contraction (DEL or AL). This worksheet can be used later as a review or as a filler once students have learned the difference between DEL and AL in Spanish. This worksheet is not appropriate for new Spanish 1 level students.
The first section is a simple review where students need to circle the correct article for four nouns. The second section as a box with the articles and another box beside it with 8 nouns. Students need to create 8 simple sentences using one from each box.
There is an answer key for each worksheet. This is useful should you want students to be able to check their own answers.
These Spanish worksheets can be completed in any order.
IMPORTANT: All of the instructions and content are completely in Spanish except for the Spanish/English Vocabulary Lists and the worksheet with translation exercises.
AGE: These worksheets are aimed at 1st and 2nd grade students in a Spanish-speaking country. It can also be used for teenagers or adults learning Spanish as a foreign language at a basic level.
Incluye 10 Páginas de ejercicios, un afiche (A4), listas de vocabulario (español/inglés) y las repuestas de profesor.
Esta lista de vocabulario contiene 30 sustantivos masculinos, 30 sustantivos femeninos. Este vocabulario está en español con su traducción en inglés.
20 adjetivos y 6 colores. Este vocabulario está en español con su traducción en inglés.
Completar frases con un artículo.
Completar frases con la contracción DEL o AL.
Dar ejemplos de frases usando un artículo con cada sustantivo.
EDAD: Para niños en 1º o 2º Básico (en países de habla hispana). También sirve para adolescentes y adultos aprendiendo español como lengua extranjera en un nivel básico.
IMPORTANTE: El texto, las actividades y sus instrucciones están en español.
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In this course you will learn icon design and how to build incredible app icons & screenshots using only free graphics and tools. With good icon design your app will stand out from your competition in the Apple App Store. This course will teach you step by step how to create these app assets which will help you increase your download numbers in the app store. With good icon design your potential customers will be attracted to your app. By applying the lessons learned here your app store optimization (ASO) will be optimized and your icon design will be awesome!
You will also get three free Gimp Templates which you can use to create your awesome icons and screenshots for all of your apps. This course comes with a 30 day money back guarantee so there is no risk. Buy now and let's start your journey into improving your iOS app marketing and icon design.


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Q: sql server Junction table values saves four times in one upload I uploaded a csv file to a dummy table(csv_upload) in sql server 2008. I have to distribute the data to the tables below using a trigger;
Questions          Answers       Test              QAT
---------         ---------     ------            -----
Questid           Ansid          Testid           Questid
Question          Answers        Testname         Ansid
                                                  Testid
                                                  id
                                                  StdUsername

The trigger code;
 INSERT INTO tbl_answers ( Answer)
select  DISTINCT Answer
from tbl_csv_upload

INSERT INTO tbl_questions ( Question )
select DISTINCT Question
from tbl_csv_upload

INSERT INTO tbl_taqa (StdUsername,questid, ansid , testid )
 SELECT  StdUsername ,q.quest_id,a.ans_id,t.test_id
  FROM csv_upload c, questions q, answers a, test t
WHERE c.Question = q.Question
AND c.Answer = a.Answer
AND t.test_id = IDENT_CURRENT('test')

This trigger worked well for the first upload from an asp.net application but on second upload it saves the data 4 time in the QAT table instead of ones but other tables are ok.
Pls i need urgent help.

A: Probably, you have duplicates of questions and answers in your data. DISTINCT gets rid of duplicates currently present in the upload table, but the next time your are calling your proc they get inserted again since it does not take into account values already present in the table.
Use this to insert the answers:
INSERT
INTO    answers (answer)
SELECT  answer
FROM    tbl_csv_upload
EXCEPT
SELECT  answer
FROM    answers

and a similar query for questions.

redpajama_set_name: RedPajamaStackExchange


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Historic Soulton
Signs of settlement here go back to the Neolitich (about 5,500 years ago), with the example of worked flint pictured below being and found in 2017 being the first sign of human activity here.
Slightly later, in the Bronze Age, a barrow was built to the east, and localy, in Iron Age a significant settlement was estabilshed at at near by Burry Walls.
The Romans built their road from Uriconium (Wroxeter today) to Mediolanum (Whitchurch today) over part of our farm, and a small town - Rutunio - developed somewhere very close indeed to the current hall, but its exact location has been lost. In the Dark Ages the manor found itself on the frontier between Powys and Mercia, and legend places King Arthur close by at Hawkstone. Recent investigations by researchers at University of Cambridge Archaeology has granted us amazing insights into this early period of development here, see the startling LIDAR image beow (more detail on this can be found here.)
The Saxon and Norman Period
The manor has been in continuous existence and occupation since before the Norman conquest. The first known owner being Britric the Saxon, brother of Edric, last Ealdorman of Mercia. The Anglo Saxon chroniclers were not fans... describing him as fleeting, ambitious and proud and he was -- with his brother -- slain by King Cnut in London on Christmas Day 1017.
The Anarchy and the Adulterine Castle
After the Conquest of 1066, during the turbulent anarchy of King Stephen and empress Matilda in the 1130s, and fort was built close by the manor to the north: the site of which is still visible to the north east of Soulton Hall -- its remains are strikingly visible to this day and the scale is expressed in the video below.
At this time the manor of Soulton belonged to King's Chapel at Shrewsbury Castle, granted by the Earl of Shrewsbury. The Castle Chapel transferred the manor to the Kynaston family sometime in the 11th century, and they in turn gave occupation to the de Soulton family. There was a dispute about this arrangement. which reached the kings courts at Westminster in the late 1200s. The lawyer for the claimants, a man named Yvo, ended up with the manor, and became of the first MPs for the county. The earliest surviving deed for the manor is dated 1399. Shortly after this a further deed survives, which addresses a boundary dispute, and rules (amusingly to modern ears) that: the boundary shall go from the bend in the river, to the pile of stones, to the damaged tree.
It is thought that the remains of a deserted medieval village are located to the north of the hall along Soulton Road (the road may have moved south at some point after the 1100s).
By the thirteenth century Robert Corbett and his family were living at Soulton, which a fortified manor house on the site of the Norman castle, but sometime around 1420, the manor house on the moated site was burnt down. When the manor house was rebuilt it was moved to its current site, at first a classic three bay manor house was constructed. Some medieval ridge and furrow survives where the 50 acre woodland now stands, with the mill race of that period also still obvious, underlining how dynamic the landscape has been here under human management thousand years and more. Again, the LIDAR below shows this:
The Tudor Period
The manor was purchased in 1556 by Sir Rowland Hill -- the first protestant Lord Mayor of London (1549). He remodelled the hall and extended it to the building that can be seen today.
In 1668, his descendant, Thomas Hill, High Sheriff of Shropshire and a friend of Samuel Pepys placed his marital coat of arms above the front door. Soulton Brook was used by the Duke of Bridgewater to trial the creation of canals in the 18th century. During this time the gardens were immense - today we have a Tudor walled garden which is by no means small, but in thse days the garden whould have stretched for hundreds of meters to the south and east and, if you refer to the LIDAR images above you can see features still discernible off to the south and east in what are now fields within the farm land.
1700s and later
In the centuries since the stewardship of this place has continued peacefully with the devolpment of an early model farm in the 1700s and other quite improvement.
The video below shows a remarkable collection of Victorian pictures of life here.
You can find further resources in the article below which contains various sources etc:
Soulton Hall - Wikipedia
< > x
Surrounding the hall and cottages, is our much cherished farm.
We practice conservation agriculture which emphasizes the health of the soil and shares the landscape with nature - there is a 50 acre oak bluebell wood here.
The video below is shows the recent harvest from the air - our guests are most welcome to enjoy and explore this restful setting.
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/*!
    \file  usb_regs.h
    \brief USB FS cell registers definition and handle macros
*/

/*
    Copyright (C) 2017 GigaDevice

    2017-02-10, V1.0.0, firmware for GD32F30x
*/

#ifndef USB_REGS_H
#define USB_REGS_H

#include "usb_conf.h"

#define USBFS                     USBFS_BASE                              /*!< base address of USBFS registers */

/* registers location definitions */
#define LOCATE_DIEPTFLEN(x)       (0x104U + 4U * ((x) - 1U))              /*!< locate device IN endpoint-x transfer length registers */
#define LOCATE_HCHCTL(x)          (0x500U + 0x20U * (x))                  /*!< locate host channel-x control registers */
#define LOCATE_HCHSTCTL(x)        (0x504U + 0x20U * (x))                  /*!< locate host channel-x split transaction control registers */
#define LOCATE_HCHINTF(x)         (0x508U + 0x20U * (x))                  /*!< locate host channel-x interrupt flag registers */
#define LOCATE_HCHINTEN(x)        (0x50CU + 0x20U * (x))                  /*!< locate host channel-x interrupt enable registers */
#define LOCATE_HCHLEN(x)          (0x510U + 0x20U * (x))                  /*!< locate host channel-x transfer length registers */
#define LOCATE_HCHDMAADDR(x)      (0x514U + 0x20U * (x))                  /*!< locate host channel-x DMA address registers */
#define LOCATE_DIEPCTL(x)         (0x900U + 0x20U * (x))                  /*!< locate device IN endpoint-x control registers */
#define LOCATE_DOEPCTL(x)         (0xB00U + 0x20U * (x))                  /*!< locate device OUT endpoint-x control registers */
#define LOCATE_DIEPINTF(x)        (0x908U + 0x20U * (x))                  /*!< locate device IN endpoint-x interrupt flag registers */
#define LOCATE_DOEPINTF(x)        (0xB08U + 0x20U * (x))                  /*!< locate device OUT endpoint-x interrupt flag registers */
#define LOCATE_DIEPLEN(x)         (0x910U + 0x20U * (x))                  /*!< locate device IN endpoint-x transfer length registers */
#define LOCATE_DOEPLEN(x)         (0xB10U + 0x20U * (x))                  /*!< locate device OUT endpoint-x transfer length registers */
#define LOCATE_DIEPxDMAADDR(x)    (0x914U + 0x20U * (x))                  /*!< locate device IN endpoint-x DMA address registers */
#define LOCATE_DOEPxDMAADDR(x)    (0xB14U + 0x20U * (x))                  /*!< locate device OUT endpoint-x DMA address registers */
#define LOCATE_DIEPxTFSTAT(x)     (0x918U + 0x20U * (x))                  /*!< locate Device IN endpoint-x transmit FIFO status register */
#define LOCATE_FIFO(x)            (((x) + 1U) << 12U)                     /*!< locate FIFO-x memory */

/* registers definitions */
#define USB_GOTGCS                REG32(((USBFS) + 0x0000U))               /*!< global OTG control and status register */
#define USB_GOTGINTF              REG32(((USBFS) + 0x0004U))               /*!< global OTG interrupt flag register */
#define USB_GAHBCS                REG32(((USBFS) + 0x0008U))               /*!< global AHB control and status register */
#define USB_GUSBCS                REG32(((USBFS) + 0x000CU))               /*!< global USB control and status register */
#define USB_GRSTCTL               REG32(((USBFS) + 0x0010U))               /*!< global reset control register */
#define USB_GINTF                 REG32(((USBFS) + 0x0014U))               /*!< global interrupt flag register */
#define USB_GINTEN                REG32(((USBFS) + 0x0018U))               /*!< global interrupt enable register */
#define USB_GRSTATR               REG32(((USBFS) + 0x001CU))               /*!< global receive status read register */
#define USB_GRSTATP               REG32(((USBFS) + 0x0020U))               /*!< global receive status read and pop register */
#define USB_GRFLEN                REG32(((USBFS) + 0x0024U))               /*!< global receive FIFO length register */
#define USB_HNPTFLEN              REG32(((USBFS) + 0x0028U))               /*!< host non-periodic transmit FIFO length register */
#define USB_DIEP0TFLEN            REG32(((USBFS) + 0x0028U))               /*!< device IN endpoint 0 transmit FIFO length register */
#define USB_HNPTFQSTAT            REG32(((USBFS) + 0x002CU))               /*!< host non-periodic transmint FIFO/queue status register */
#define USB_GCCFG                 REG32(((USBFS) + 0x0038U))               /*!< global core configuration register */
#define USB_CID                   REG32(((USBFS) + 0x003CU))               /*!< core id register */
#define USB_HPTFLEN               REG32(((USBFS) + 0x0100U))               /*!< host periodic transmit FIFO length register */
#define USB_DIEPxTFLEN(x)         REG32(((USBFS) + LOCATE_DIEPTFLEN(x)))   /*!< device IN endpoint transmit FIFO length register */

#define USB_HCTL                  REG32(((USBFS) + 0x0400U))               /*!< host control register */
#define USB_HFT                   REG32(((USBFS) + 0x0404U))               /*!< host frame interval register */
#define USB_HFINFR                REG32(((USBFS) + 0x0408U))               /*!< host frame information remaining register */
#define USB_HPTFQSTAT             REG32(((USBFS) + 0x0410U))               /*!< host periodic transmit FIFO/queue status register */
#define USB_HACHINT               REG32(((USBFS) + 0x0414U))               /*!< host all channels interrupt register */
#define USB_HACHINTEN             REG32(((USBFS) + 0x0418U))               /*!< host all channels interrupt enable register */
#define USB_HPCS                  REG32(((USBFS) + 0x0440U))               /*!< host port control and status register */
#define USB_HCHxCTL(x)            REG32(((USBFS) + LOCATE_HCHCTL(x)))      /*!< host channel-x control register */
#define USB_HCHxSTCTL(x)          REG32(((USBFS) + LOCATE_HCHSTCTL(x)))    /*!< host channel-x split transaction control register */
#define USB_HCHxINTF(x)           REG32(((USBFS) + LOCATE_HCHINTF(x)))     /*!< host channel-x interrupt flag register */
#define USB_HCHxINTEN(x)          REG32(((USBFS) + LOCATE_HCHINTEN(x)))    /*!< host channel-x interrupt enable register */
#define USB_HCHxLEN(x)            REG32(((USBFS) + LOCATE_HCHLEN(x)))      /*!< host channel-x tranfer length register */
#define USB_HCHxDMAADDR(x)        REG32(((USBFS) + LOCATE_HCHDMAADDR(x)))  /*!< host channel-x DMA address register */

#define USB_DCFG                  REG32(((USBFS) + 0x0800U))               /*!< device configuration register */
#define USB_DCTL                  REG32(((USBFS) + 0x0804U))               /*!< device control register */
#define USB_DSTAT                 REG32(((USBFS) + 0x0808U))               /*!< device status register */
#define USB_DIEPINTEN             REG32(((USBFS) + 0x0810U))               /*!< device IN endpoint common interrupt enable register */
#define USB_DOEPINTEN             REG32(((USBFS) + 0x0814U))               /*!< device OUT endpoint common interrupt enable register */
#define USB_DAEPINT               REG32(((USBFS) + 0x0818U))               /*!< device all endpoints interrupt register */
#define USB_DAEPINTEN             REG32(((USBFS) + 0x081CU))               /*!< device all endpoints interrupt enable register */
#define USB_DVBUSDT               REG32(((USBFS) + 0x0828U))               /*!< device vbus discharge time register */
#define USB_DVBUSPT               REG32(((USBFS) + 0x082CU))               /*!< device vbus pulsing time register */
#define USB_DIEPFEINTEN           REG32(((USBFS) + 0x0834U))               /*!< device IN endpoint FIFO empty interrupt enable register */
#define USB_DEP1INT               REG32(((USBFS) + 0x0838U))               /*!< device endpoint 1 interrupt register */
#define USB_DEP1INTEN             REG32(((USBFS) + 0x083CU))               /*!< device endpoint 1 interrupt enable register */
#define USB_DIEP1INTEN            REG32(((USBFS) + 0x0844U))               /*!< device IN endpoint 1 interrupt enable register */
#define USB_DOEP1INTEN            REG32(((USBFS) + 0x0884U))               /*!< device OUT endpoint 1 interrupt enable register */
#define USB_DIEP0CTL              REG32(((USBFS) + 0x0900U))               /*!< device IN endpoint 0 control register */
#define USB_DIEP0LEN              REG32(((USBFS) + 0x0910U))               /*!< device IN endpoint 0 transfer length register */
#define USB_DOEP0CTL              REG32(((USBFS) + 0x0B00U))               /*!< device OUT endpoint 0 control register */
#define USB_DOEP0LEN              REG32(((USBFS) + 0x0B10U))               /*!< device OUT endpoint 0 transfer length register */
#define USB_DIEPxCTL(x)           REG32(((USBFS) + LOCATE_DIEPCTL(x)))     /*!< device IN endpoint-x control register */
#define USB_DOEPxCTL(x)           REG32(((USBFS) + LOCATE_DOEPCTL(x)))     /*!< device OUT endpoint-x control register */
#define USB_DIEPxINTF(x)          REG32(((USBFS) + LOCATE_DIEPINTF(x)))    /*!< device IN endpoint-x interrupt flag register */
#define USB_DOEPxINTF(x)          REG32(((USBFS) + LOCATE_DOEPINTF(x)))    /*!< device OUT endpoint-x interrupt flag register */
#define USB_DIEPxLEN(x)           REG32(((USBFS) + LOCATE_DIEPLEN(x)))     /*!< device IN endpoint-x transfer length register */
#define USB_DOEPxLEN(x)           REG32(((USBFS) + LOCATE_DOEPLEN(x)))     /*!< device OUT endpoint-x transfer length register */
#define USB_DIEPxDMAADDR(x)       REG32(((USBFS) + LOCATE_DIEPxDMAADDR(x)))/*!< device IN endpoint-x DMA address register */
#define USB_DOEPxDMAADDR(x)       REG32(((USBFS) + LOCATE_DOEPxDMAADDR(x)))/*!< device OUT endpoint-x DMA address register */
#define USB_DIEPxTFSTAT(x)        REG32(((USBFS) + LOCATE_DIEPxTFSTAT(x))) /*!< device IN endpoint-x transmit FIFO status register */

#define USB_PWRCLKCTL             REG32(((USBFS) + 0x0E00U))               /*!< power and clock register */

#define USB_FIFO(x)               (&REG32(((USBFS) + LOCATE_FIFO(x))))     /*!< FIFO memory */

/* global OTG control and status register bits definitions */
#define GOTGCS_BSV                BIT(19)             /*!< B-Session Valid */
#define GOTGCS_ASV                BIT(18)             /*!< A-session valid */
#define GOTGCS_DI                 BIT(17)             /*!< debounce interval */
#define GOTGCS_CIDPS              BIT(16)             /*!< id pin status */
#define GOTGCS_DHNPEN             BIT(11)             /*!< device HNP enable */
#define GOTGCS_HHNPEN             BIT(10)             /*!< host HNP enable */
#define GOTGCS_HNPREQ             BIT(9)              /*!< HNP request */
#define GOTGCS_HNPS               BIT(8)              /*!< HNP successes */
#define GOTGCS_SRPREQ             BIT(1)              /*!< SRP request */
#define GOTGCS_SRPS               BIT(0)              /*!< SRP successes */

/* global OTG interrupt flag register bits definitions */
#define GOTGINTF_DF               BIT(19)             /*!< debounce finish */
#define GOTGINTF_ADTO             BIT(18)             /*!< A-device timeout */
#define GOTGINTF_HNPDET           BIT(17)             /*!< host negotiation request detected */
#define GOTGINTF_HNPEND           BIT(9)              /*!< HNP end */
#define GOTGINTF_SRPEND           BIT(8)              /*!< SRP end */
#define GOTGINTF_SESEND           BIT(2)              /*!< session end */

/* global AHB control and status register bits definitions */
#define GAHBCS_PTXFTH             BIT(8)              /*!< periodic Tx FIFO threshold */
#define GAHBCS_TXFTH              BIT(7)              /*!< tx FIFO threshold */
#define GAHBCS_DMAEN              BIT(5)              /*!< DMA function Enable */
#define GAHBCS_BURST              BITS(1, 4)          /*!< the AHB burst type used by DMA */
#define GAHBCS_GINTEN             BIT(0)              /*!< global interrupt enable */

/* global USB control and status register bits definitions */
#define GUSBCS_FDM                BIT(30)             /*!< force device mode */
#define GUSBCS_FHM                BIT(29)             /*!< force host mode */
#define GUSBCS_ULPIEOI            BIT(21)             /*!< ULPI external over-current indicator */
#define GUSBCS_ULPIEVD            BIT(20)             /*!< ULPI external VBUS driver */
#define GUSBCS_UTT                BITS(10, 13)        /*!< USB turnaround time */
#define GUSBCS_HNPCEN             BIT(9)              /*!< HNP capability enable */
#define GUSBCS_SRPCEN             BIT(8)              /*!< SRP capability enable */
#define GUSBCS_EMBPHY             BIT(6)              /*!< embedded PHY selected */
#define GUSBCS_TOC                BITS(0, 2)          /*!< timeout calibration */

/* global reset control register bits definitions */
#define GRSTCTL_DMAIDL            BIT(31)             /*!< DMA idle state */
#define GRSTCTL_DMABSY            BIT(30)             /*!< DMA busy */
#define GRSTCTL_TXFNUM            BITS(6, 10)         /*!< tx FIFO number */
#define GRSTCTL_TXFF              BIT(5)              /*!< tx FIFO flush */
#define GRSTCTL_RXFF              BIT(4)              /*!< rx FIFO flush */
#define GRSTCTL_HFCRST            BIT(2)              /*!< host frame counter reset */
#define GRSTCTL_HCSRST            BIT(1)              /*!< HCLK soft reset */
#define GRSTCTL_CSRST             BIT(0)              /*!< core soft reset */

/* global interrupt flag register bits definitions */
#define GINTF_WKUPIF              BIT(31)             /*!< wakeup interrupt flag */
#define GINTF_SESIF               BIT(30)             /*!< session interrupt flag */
#define GINTF_DISCIF              BIT(29)             /*!< disconnect interrupt flag */
#define GINTF_IDPSC               BIT(28)             /*!< id pin status change */
#define GINTF_PTXFEIF             BIT(26)             /*!< periodic tx FIFO empty interrupt flag */
#define GINTF_HCIF                BIT(25)             /*!< host channels interrupt flag */
#define GINTF_HPIF                BIT(24)             /*!< host port interrupt flag */
#define GINTF_PXNCIF              BIT(21)             /*!< periodic transfer not complete interrupt flag */
#define GINTF_ISOONCIF            BIT(21)             /*!< isochronous OUT transfer not complete interrupt flag */
#define GINTF_ISOINCIF            BIT(20)             /*!< isochronous IN transfer not complete interrupt flag */
#define GINTF_OEPIF               BIT(19)             /*!< OUT endpoint interrupt flag */
#define GINTF_IEPIF               BIT(18)             /*!< IN endpoint interrupt flag */
#define GINTF_EOPFIF              BIT(15)             /*!< end of periodic frame interrupt flag */
#define GINTF_ISOOPDIF            BIT(14)             /*!< isochronous OUT packet dropped interrupt flag */
#define GINTF_ENUMFIF             BIT(13)             /*!< enumeration finished */
#define GINTF_RST                 BIT(12)             /*!< USB reset */
#define GINTF_SP                  BIT(11)             /*!< USB suspend */
#define GINTF_ESP                 BIT(10)             /*!< early suspend */
#define GINTF_GONAK               BIT(7)              /*!< global OUT NAK effective */
#define GINTF_GNPINAK             BIT(6)              /*!< global IN non-periodic NAK effective */
#define GINTF_NPTXFEIF            BIT(5)              /*!< non-periodic tx FIFO empty interrupt flag */
#define GINTF_RXFNEIF             BIT(4)              /*!< rx FIFO non-empty interrupt flag */
#define GINTF_SOF                 BIT(3)              /*!< start of frame */
#define GINTF_OTGIF               BIT(2)              /*!< OTG interrupt flag */
#define GINTF_MFIF                BIT(1)              /*!< mode fault interrupt flag */
#define GINTF_COPM                BIT(0)              /*!< current operation mode */

/* global interrupt enable register bits definitions */
#define GINTEN_WKUPIE             BIT(31)             /*!< wakeup interrupt enable */
#define GINTEN_SESIE              BIT(30)             /*!< session interrupt enable */
#define GINTEN_DISCIE             BIT(29)             /*!< disconnect interrupt enable */
#define GINTEN_IDPSCIE            BIT(28)             /*!< id pin status change interrupt enable */
#define GINTEN_PTXFEIE            BIT(26)             /*!< periodic tx FIFO empty interrupt enable */
#define GINTEN_HCIE               BIT(25)             /*!< host channels interrupt enable */
#define GINTEN_HPIE               BIT(24)             /*!< host port interrupt enable */
#define GINTEN_IPXIE              BIT(21)             /*!< periodic transfer not complete interrupt enable */
#define GINTEN_ISOONCIE           BIT(21)             /*!< isochronous OUT transfer not complete interrupt enable */
#define GINTEN_ISOINCIE           BIT(20)             /*!< isochronous IN transfer not complete interrupt enable */
#define GINTEN_OEPIE              BIT(19)             /*!< OUT endpoints interrupt enable */
#define GINTEN_IEPIE              BIT(18)             /*!< IN endpoints interrupt enable */
#define GINTEN_EOPFIE             BIT(15)             /*!< end of periodic frame interrupt enable */
#define GINTEN_ISOOPDIE           BIT(14)             /*!< isochronous OUT packet dropped interrupt enable */
#define GINTEN_ENUMFIE            BIT(13)             /*!< enumeration finish enable */
#define GINTEN_RSTIE              BIT(12)             /*!< USB reset interrupt enable */
#define GINTEN_SPIE               BIT(11)             /*!< USB suspend interrupt enable */
#define GINTEN_ESPIE              BIT(10)             /*!< early suspend interrupt enable */
#define GINTEN_GONAKIE            BIT(7)              /*!< global OUT NAK effective interrupt enable */
#define GINTEN_GNPINAKIE          BIT(6)              /*!< global non-periodic IN NAK effective interrupt enable */
#define GINTEN_NPTXFEIE           BIT(5)              /*!< non-periodic Tx FIFO empty interrupt enable */
#define GINTEN_RXFNEIE            BIT(4)              /*!< receive FIFO non-empty interrupt enable */
#define GINTEN_SOFIE              BIT(3)              /*!< start of frame interrupt enable */
#define GINTEN_OTGIE              BIT(2)              /*!< OTG interrupt enable */
#define GINTEN_MFIE               BIT(1)              /*!< mode fault interrupt enable */

/* global receive status read and pop register bits definitions */
#define GRSTATRP_RPCKST           BITS(17, 20)        /*!< received packet status */
#define GRSTATRP_DPID             BITS(15, 16)        /*!< data PID */
#define GRSTATRP_BCOUNT           BITS(4, 14)         /*!< byte count */
#define GRSTATRP_CNUM             BITS(0, 3)          /*!< channel number */
#define GRSTATRP_EPNUM            BITS(0, 3)          /*!< endpoint number */

/* global receive FIFO length register bits definitions */
#define GRFLEN_RXFD               BITS(0, 15)         /*!< rx FIFO depth */

/* host non-periodic transmit FIFO length register bits definitions */
#define HNPTFLEN_HNPTXFD          BITS(16, 31)        /*!< non-periodic Tx FIFO depth */
#define HNPTFLEN_HNPTXRSAR        BITS(0, 15)         /*!< non-periodic Tx RAM start address */

/* IN endpoint 0 transmit FIFO length register bits definitions */
#define DIEP0TFLEN_IEP0TXFD       BITS(16, 31)        /*!< IN Endpoint 0 Tx FIFO depth */
#define DIEP0TFLEN_IEP0TXRSAR     BITS(0, 15)         /*!< IN Endpoint 0 TX RAM start address */

/* host non-periodic transmit FIFO/queue status register bits definitions */
#define HNPTFQSTAT_NPTXRQTOP      BITS(24, 30)        /*!< top entry of the non-periodic Tx request queue */
#define HNPTFQSTAT_NPTXRQS        BITS(16, 23)        /*!< non-periodic Tx request queue space */
#define HNPTFQSTAT_NPTXFS         BITS(0, 15)         /*!< non-periodic Tx FIFO space */
#define HNPTFQSTAT_CNUM           BITS(27, 30)        /*!< channel number*/
#define HNPTFQSTAT_EPNUM          BITS(27, 30)        /*!< endpoint number */
#define HNPTFQSTAT_TYPE           BITS(25, 26)        /*!< token type */
#define HNPTFQSTAT_TMF            BIT(24)             /*!< terminate flag */

/* global core configuration register bits definitions */
#define GCCFG_VBUSIG              BIT(21)             /*!< vbus ignored */
#define GCCFG_SOFOEN              BIT(20)             /*!< SOF output enable */
#define GCCFG_VBUSBCEN            BIT(19)             /*!< the VBUS B-device comparer enable */
#define GCCFG_VBUSACEN            BIT(18)             /*!< the VBUS A-device comparer enable */
#define GCCFG_PWRON               BIT(16)             /*!< power on */

/* core ID register bits definitions */
#define CID_CID                   BITS(0, 31)         /*!< core ID */

/* host periodic transmit FIFO length register bits definitions */
#define HPTFLEN_HPTXFD            BITS(16, 31)        /*!< host periodic Tx FIFO depth */
#define HPTFLEN_HPTXFSAR          BITS(0, 15)         /*!< host periodic Tx RAM start address */

/* device IN endpoint transmit FIFO length register bits definitions */
#define DIEPTFLEN_IEPTXFD         BITS(16, 31)        /*!< IN endpoint Tx FIFO x depth */
#define DIEPTFLEN_IEPTXRSAR       BITS(0, 15)         /*!< IN endpoint FIFOx Tx x RAM start address */

/* host control register bits definitions */
#define HCTL_SPDFSLS              BIT(2)              /*!< speed limited to FS and LS */
#define HCTL_CLKSEL               BITS(0, 1)          /*!< clock select for USB clock */

/* host frame interval register bits definitions */
#define HFT_FRI                   BITS(0, 15)         /*!< frame interval */

/* host frame information remaining register bits definitions */
#define HFINFR_FRT                BITS(16, 31)        /*!< frame remaining time */
#define HFINFR_FRNUM              BITS(0, 15)         /*!< frame number */

/* host periodic transmit FIFO/queue status register bits definitions */
#define HPTFQSTAT_PTXREQT         BITS(24, 31)        /*!< top entry of the periodic Tx request queue */
#define HPTFQSTAT_PTXREQS         BITS(16, 23)        /*!< periodic Tx request queue space */
#define HPTFQSTAT_PTXFS           BITS(0, 15)         /*!< periodic Tx FIFO space */
#define HPTFQSTAT_OEFRM           BIT(31)             /*!< odd/eveb frame */
#define HPTFQSTAT_CNUM            BITS(27, 30)        /*!< channel number */
#define HPTFQSTAT_EPNUM           BITS(27, 30)        /*!< endpoint number */
#define HPTFQSTAT_TYPE            BITS(25, 26)        /*!< token type */
#define HPTFQSTAT_TMF             BIT(24)             /*!< terminate flag */

/* host all channels interrupt register bits definitions */
#define HACHINT_HACHINT           BITS(0, 11)         /*!< host all channel interrupts */

/* host all channels interrupt enable register bits definitions */
#define HACHINTEN_CINTEN          BITS(0, 11)         /*!< channel interrupt enable */

/* host port control and status register bits definitions */
#define HPCS_PS                   BITS(17, 18)        /*!< port speed */
#define HPCS_PP                   BIT(12)             /*!< port power */
#define HPCS_PLST                 BITS(10, 11)        /*!< port line status */
#define HPCS_PRST                 BIT(8)              /*!< port reset */
#define HPCS_PSP                  BIT(7)              /*!< port suspend */
#define HPCS_PREM                 BIT(6)              /*!< port resume */
#define HPCS_PEDC                 BIT(3)              /*!< port enable/disable change */
#define HPCS_PE                   BIT(2)              /*!< port enable */
#define HPCS_PCD                  BIT(1)              /*!< port connect detected */
#define HPCS_PCST                 BIT(0)              /*!< port connect status */

/* host channel-x control register bits definitions */
#define HCHCTL_CEN                BIT(31)             /*!< channel enable */
#define HCHCTL_CDIS               BIT(30)             /*!< channel disable */
#define HCHCTL_ODDFRM             BIT(29)             /*!< odd frame */
#define HCHCTL_DAR                BITS(22, 28)        /*!< device address */
#define HCHCTL_MPC                BITS(20, 21)        /*!< multiple packet count */
#define HCHCTL_EPTYPE             BITS(18, 19)        /*!< endpoint type */
#define HCHCTL_LSD                BIT(17)             /*!< low-speed device */
#define HCHCTL_EPDIR              BIT(15)             /*!< endpoint direction */
#define HCHCTL_EPNUM              BITS(11, 14)        /*!< endpoint number */
#define HCHCTL_MPL                BITS(0, 10)         /*!< maximum packet length */

/* host channel-x split transaction register bits definitions */
#define HCHSTCTL_SPLEN            BIT(31)             /*!< enable high-speed split transaction */
#define HCHSTCTL_CSPLT            BIT(16)             /*!< complete-split enable */
#define HCHSTCTL_ISOPCE           BITS(14, 15)        /*!< isochronous OUT payload continuation encoding */
#define HCHSTCTL_HADDR            BITS(7, 13)         /*!< HUB address */
#define HCHSTCTL_PADDR            BITS(0, 6)          /*!< port address */

/* host channel-x interrupt flag register bits definitions */
#define HCHINTF_DTER              BIT(10)             /*!< data toggle error */
#define HCHINTF_REQOVR            BIT(9)              /*!< request queue overrun */
#define HCHINTF_BBER              BIT(8)              /*!< babble error */
#define HCHINTF_USBER             BIT(7)              /*!< USB bus Error */
#define HCHINTF_NYET              BIT(6)              /*!< NYET */
#define HCHINTF_ACK               BIT(5)              /*!< ACK */
#define HCHINTF_NAK               BIT(4)              /*!< NAK */
#define HCHINTF_STALL             BIT(3)              /*!< STALL */
#define HCHINTF_DMAER             BIT(2)              /*!< DMA error */
#define HCHINTF_CH                BIT(1)              /*!< channel halted */
#define HCHINTF_TF                BIT(0)              /*!< transfer finished */

/* host channel-x interrupt enable register bits definitions */
#define HCHINTEN_DTERIE           BIT(10)             /*!< data toggle error interrupt enable */
#define HCHINTEN_REQOVRIE         BIT(9)              /*!< request queue overrun interrupt enable */
#define HCHINTEN_BBERIE           BIT(8)              /*!< babble error interrupt enable */
#define HCHINTEN_USBERIE          BIT(7)              /*!< USB bus error interrupt enable */
#define HCHINTEN_NYETIE           BIT(6)              /*!< NYET interrupt enable */
#define HCHINTEN_ACKIE            BIT(5)              /*!< ACK interrupt enable */
#define HCHINTEN_NAKIE            BIT(4)              /*!< NAK interrupt enable */
#define HCHINTEN_STALLIE          BIT(3)              /*!< STALL interrupt enable */
#define HCHINTEN_DMAERIE          BIT(2)              /*!< DMA error interrupt enable */
#define HCHINTEN_CHIE             BIT(1)              /*!< channel halted interrupt enable */
#define HCHINTEN_TFIE             BIT(0)              /*!< transfer finished interrupt enable */

/* host channel-x transfer length register bits definitions */
#define HCHLEN_PING               BIT(31)             /*!< PING token request */
#define HCHLEN_DPID               BITS(29, 30)        /*!< data PID */
#define HCHLEN_PCNT               BITS(19, 28)        /*!< packet count */
#define HCHLEN_TLEN               BITS(0, 18)         /*!< transfer length */

/* host channel-x DMA address register bits definitions */
#define HCHDMAADDR_DMAADDR        BITS(0, 31)         /*!< DMA address */

/* device control and status registers */
/* device configuration registers bits definitions */
#define DCFG_EOPFT                BITS(11, 12)        /*!< end of periodic frame time */
#define DCFG_DAR                  BITS(4, 10)         /*!< device address */
#define DCFG_NZLSOH               BIT(2)              /*!< non-zero-length status OUT handshake */
#define DCFG_DS                   BITS(0, 1)          /*!< device speed */

/* device control registers bits definitions */
#define DCTL_POIF                 BIT(11)             /*!< power-on initialization finished */
#define DCTL_CGONAK               BIT(10)             /*!< clear global OUT NAK */
#define DCTL_SGONAK               BIT(9)              /*!< set global OUT NAK */
#define DCTL_CGINAK               BIT(8)              /*!< clear global IN NAK */
#define DCTL_SGINAK               BIT(7)              /*!< set global IN NAK */
#define DCTL_GONS                 BIT(3)              /*!< global OUT NAK status */
#define DCTL_GINS                 BIT(2)              /*!< global IN NAK status */
#define DCTL_SD                   BIT(1)              /*!< soft disconnect */
#define DCTL_RWKUP                BIT(0)              /*!< remote wakeup */

/* device status registers bits definitions */
#define DSTAT_FNRSOF              BITS(8, 21)         /*!< the frame number of the received SOF. */
#define DSTAT_ES                  BITS(1, 2)          /*!< enumerated speed */
#define DSTAT_SPST                BIT(0)              /*!< suspend status */

/* device IN endpoint common interrupt enable registers bits definitions */
#define DIEPINTEN_NAKEN           BIT(13)             /*!< NAK handshake sent by USBHS interrupt enable bit */
#define DIEPINTEN_TXFEEN          BIT(7)              /*!< transmit FIFO empty interrupt enable bit */
#define DIEPINTEN_IEPNEEN         BIT(6)              /*!< IN endpoint NAK effective interrupt enable bit */
#define DIEPINTEN_EPTXFUDEN       BIT(4)              /*!< endpoint Tx FIFO underrun interrupt enable bit */
#define DIEPINTEN_CITOEN          BIT(3)              /*!< control In Timeout interrupt enable bit */
#define DIEPINTEN_EPDISEN         BIT(1)              /*!< endpoint disabled interrupt enable bit */
#define DIEPINTEN_TFEN            BIT(0)              /*!< transfer finished interrupt enable bit */

/* device OUT endpoint common interrupt enable registers bits definitions */
#define DOEPINTEN_NYETEN          BIT(14)             /*!< NYET handshake is sent interrupt enable bit */
#define DOEPINTEN_BTBSTPEN        BIT(6)              /*!< back-to-back SETUP packets interrupt enable bit */
#define DOEPINTEN_EPRXFOVREN      BIT(4)              /*!< endpoint Rx FIFO overrun interrupt enable bit */
#define DOEPINTEN_STPFEN          BIT(3)              /*!< SETUP phase finished interrupt enable bit */
#define DOEPINTEN_EPDISEN         BIT(1)              /*!< endpoint disabled interrupt enable bit */
#define DOEPINTEN_TFEN            BIT(0)              /*!< transfer finished interrupt enable bit */

/* device all endpoints interrupt registers bits definitions */
#define DAEPINT_OEPITB            BITS(16, 21)        /*!< device all OUT endpoint interrupt bits */
#define DAEPINT_IEPITB            BITS(0, 5)          /*!< device all IN endpoint interrupt bits */

/* device all endpoints interrupt enable registers bits definitions */
#define DAEPINTEN_OEPIE           BITS(16, 21)        /*!< OUT endpoint interrupt enable */
#define DAEPINTEN_IEPIE           BITS(0, 3)          /*!< IN endpoint interrupt enable */

/* device Vbus discharge time registers bits definitions */
#define DVBUSDT_DVBUSDT           BITS(0, 15)         /*!< device VBUS discharge time */

/* device Vbus pulsing time registers bits definitions */
#define DVBUSPT_DVBUSPT           BITS(0, 11)         /*!< device VBUS pulsing time */

/* device IN endpoint FIFO empty interrupt enable register bits definitions */
#define DIEPFEINTEN_IEPTXFEIE     BITS(0, 5)          /*!< IN endpoint Tx FIFO empty interrupt enable bits */

/* device endpoint 1 interrupt register bits definitions */
#define DEP1INT_OEP1INT           BIT(17)             /*!< OUT Endpoint 1 interrupt */
#define DEP1INT_IEP1INT           BIT(1)              /*!< IN Endpoint 1 interrupt */

/* device endpoint 1 interrupt register enable bits definitions */
#define DEP1INTEN_OEP1INTEN       BIT(17)             /*!< OUT Endpoint 1 interrupt enable */
#define DEP1INTEN_IEP1INTEN       BIT(1)              /*!< IN Endpoint 1 interrupt enable */

/* device IN endpoint 1 interrupt enable register bits definitions */
#define DIEP1INTEN_NAKEN          BIT(13)             /*!< NAK handshake sent by USBHS interrupt enable bit */
#define DIEP1INTEN_IEPNEEN        BIT(6)              /*!< IN endpoint NAK effective interrupt enable bit */
#define DIEP1INTEN_EPTXFUDEN      BIT(4)              /*!< endpoint Tx FIFO underrun interrupt enable bit */
#define DIEP1INTEN_CITOEN         BIT(3)              /*!< control In Timeout interrupt enable bit */
#define DIEP1INTEN_EPDISEN        BIT(1)              /*!< endpoint disabled interrupt enable bit */
#define DIEP1INTEN_TFEN           BIT(0)              /*!< transfer finished interrupt enable bit */

/* device OUT endpoint 1 interrupt enable register bits definitions */
#define DOEP1INTEN_NYETEN         BIT(14)             /*!< NYET handshake is sent interrupt enable bit */
#define DOEP1INTEN_BTBSTPEN       BIT(6)              /*!< back-to-back SETUP packets interrupt enable bit */
#define DOEP1INTEN_EPRXOVREN      BIT(4)              /*!< endpoint Rx FIFO over run interrupt enable bit */
#define DOEP1INTEN_STPFEN         BIT(3)              /*!< SETUP phase finished interrupt enable bit */
#define DOEP1INTEN_EPDISEN        BIT(1)              /*!< endpoint disabled interrupt enable bit */
#define DOEP1INTEN_TFEN           BIT(0)              /*!< back-to-back SETUP packets interrupt enable bit */

/* device endpoint 0 control register bits definitions */
#define DEP0CTL_EPEN              BIT(31)             /*!< endpoint enable */
#define DEP0CTL_EPD               BIT(30)             /*!< endpoint disable */
#define DEP0CTL_SNAK              BIT(27)             /*!< set NAK */
#define DEP0CTL_CNAK              BIT(26)             /*!< clear NAK */
#define DIEP0CTL_TXFNUM           BITS(22, 25)        /*!< tx FIFO number */
#define DEP0CTL_STALL             BIT(21)             /*!< STALL handshake */
#define DOEP0CTL_SNOOP            BIT(20)             /*!< snoop mode */
#define DEP0CTL_EPTYPE            BITS(18, 19)        /*!< endpoint type */
#define DEP0CTL_NAKS              BIT(17)             /*!< NAK status */
#define DEP0CTL_EPACT             BIT(15)             /*!< endpoint active */
#define DEP0CTL_MPL               BITS(0, 1)          /*!< maximum packet length */

/* device endpoint x control register bits definitions */
#define DEPCTL_EPEN               BIT(31)             /*!< endpoint enable */
#define DEPCTL_EPD                BIT(30)             /*!< endpoint disable */
#define DEPCTL_SODDFRM            BIT(29)             /*!< set odd frame */
#define DEPCTL_SD1PID             BIT(29)             /*!< set DATA1 PID */
#define DEPCTL_SEVNFRM            BIT(28)             /*!< set even frame */
#define DEPCTL_SD0PID             BIT(28)             /*!< set DATA0 PID */
#define DEPCTL_SNAK               BIT(27)             /*!< set NAK */
#define DEPCTL_CNAK               BIT(26)             /*!< clear NAK */
#define DIEPCTL_TXFNUM            BITS(22, 25)        /*!< tx FIFO number */
#define DEPCTL_STALL              BIT(21)             /*!< STALL handshake */
#define DOEPCTL_SNOOP             BIT(20)             /*!< snoop mode */
#define DEPCTL_EPTYPE             BITS(18, 19)        /*!< endpoint type */
#define DEPCTL_NAKS               BIT(17)             /*!< NAK status */
#define DEPCTL_EOFRM              BIT(16)             /*!< even/odd frame */
#define DEPCTL_DPID               BIT(16)             /*!< endpoint data PID */
#define DEPCTL_EPACT              BIT(15)             /*!< endpoint active */
#define DEPCTL_MPL                BITS(0, 10)         /*!< maximum packet length */

/* device IN endpoint-x interrupt flag register bits definitions */
#define DIEPINTF_NAK              BIT(13)             /*!< NAK handshake sent by USBHS */
#define DIEPINTF_TXFE             BIT(7)              /*!< transmit FIFO empty */
#define DIEPINTF_IEPNE            BIT(6)              /*!< IN endpoint NAK effective */
#define DIEPINTF_EPTXFUD          BIT(4)              /*!< endpoint Tx FIFO underrun */
#define DIEPINTF_CITO             BIT(3)              /*!< control In Timeout interrupt */
#define DIEPINTF_EPDIS            BIT(1)              /*!< endpoint disabled */
#define DIEPINTF_TF               BIT(0)              /*!< transfer finished */

/* device OUT endpoint-x interrupt flag register bits definitions */
#define DOEPINTF_NYET             BIT(14)             /*!< NYET handshake is sent */
#define DOEPINTF_BTBSTP           BIT(6)              /*!< back-to-back SETUP packets */
#define DOEPINTF_EPRXFOVR         BIT(4)              /*!< endpoint Rx FIFO overrun */
#define DOEPINTF_STPF             BIT(3)              /*!< SETUP phase finished */
#define DOEPINTF_EPDIS            BIT(1)              /*!< endpoint disabled */
#define DOEPINTF_TF               BIT(0)              /*!< transfer finished */

/* device IN endpoint 0 transfer length register bits definitions */
#define DIEP0LEN_PCNT             BITS(19, 20)        /*!< packet count */
#define DIEP0LEN_TLEN             BITS(0, 6)          /*!< transfer length */

/* device OUT endpoint 0 transfer length register bits definitions */
#define DOEP0LEN_STPCNT           BITS(29, 30)        /*!< SETUP packet count */
#define DOEP0LEN_PCNT             BIT(19)             /*!< packet count */
#define DOEP0LEN_TLEN             BITS(0, 6)          /*!< transfer length */

/* device OUT endpoint-x transfer length register bits definitions */
#define DOEPLEN_RXDPID            BITS(29, 30)        /*!< received data PID */
#define DOEPLEN_STPCNT            BITS(29, 30)        /*!< SETUP packet count */
#define DIEPLEN_MCNT              BITS(29, 30)        /*!< multi count */
#define DEPLEN_PCNT               BITS(19, 28)        /*!< packet count */
#define DEPLEN_TLEN               BITS(0, 18)         /*!< transfer length */

/* device IN endpoint-x DMA address register bits definitions */
#define DIEPDMAADDR_DMAADDR       BITS(0, 31)         /*!< DMA address */

/* device OUT endpoint-x DMA address register bits definitions */
#define DOEPDMAADDR_DMAADDR       BITS(0, 31)         /*!< DMA address */

/* device IN endpoint-x transmit FIFO status register bits definitions */
#define DIEPTFSTAT_IEPTFS         BITS(0, 15)         /*!< IN endpoint¡¯s Tx FIFO space remaining */

/* USB power and clock registers bits definition */
#define PWRCLKCTL_SHCLK           BIT(1)              /*!< stop HCLK */
#define PWRCLKCTL_SUCLK           BIT(0)              /*!< stop the USB clock */

/* register options defines */
#define DCFG_DEVSPEED(regval)     (DCFG_DS & ((regval) << 0U))      /*!< device speed configuration */

#define USB_SPEED_EXP_HIGH        DCFG_DEVSPEED(0U)                 /*!< device external PHY high speed */
#define USB_SPEED_EXP_FULL        DCFG_DEVSPEED(1U)                 /*!< device external PHY full speed */
#define USB_SPEED_INP_FULL        DCFG_DEVSPEED(3U)                 /*!< device internal PHY full speed */

#define GAHBCS_TFEL(regval)       (GAHBCS_TXFTH & ((regval) << 7U)) /*!< device speed configuration */

#define TXFIFO_EMPTY_HALF         GAHBCS_TFEL(0U)                   /*!< Tx FIFO half empty */
#define TXFIFO_EMPTY              GAHBCS_TFEL(1U)                   /*!< Tx FIFO completely empty */

#define GAHBCS_DMAINCR(regval)    (GAHBCS_BURST & ((regval) << 1U)) /*!< AHB burst type used by DMA*/

#define DMA_INCR0                 GAHBCS_DMAINCR(0U)                /*!< single burst type used by DMA*/
#define DMA_INCR1                 GAHBCS_DMAINCR(1U)                /*!< 4-beat incrementing burst type used by DMA*/
#define DMA_INCR4                 GAHBCS_DMAINCR(3U)                /*!< 8-beat incrementing burst type used by DMA*/
#define DMA_INCR8                 GAHBCS_DMAINCR(5U)                /*!< 16-beat incrementing burst type used by DMA*/
#define DMA_INCR16                GAHBCS_DMAINCR(7U)                /*!< 32-beat incrementing burst type used by DMA*/

#define DCFG_PFRI(regval)         (DCFG_EOPFT & ((regval) << 11U))  /*!< end of periodic frame time configuration */

#define FRAME_INTERVAL_80         DCFG_PFRI(0U)                     /*!< 80% of the frame time */
#define FRAME_INTERVAL_85         DCFG_PFRI(1U)                     /*!< 85% of the frame time */
#define FRAME_INTERVAL_90         DCFG_PFRI(2U)                     /*!< 90% of the frame time */
#define FRAME_INTERVAL_95         DCFG_PFRI(3U)                     /*!< 95% of the frame time */

#define DEP0_MPL(regval)          (DEP0CTL_MPL & ((regval) << 0U))   /*!< maximum packet length configuration */

#define EP0MPL_64                 DEP0_MPL(0U)                   /*!< maximum packet length 64 bytes */
#define EP0MPL_32                 DEP0_MPL(1U)                   /*!< maximum packet length 32 bytes */
#define EP0MPL_16                 DEP0_MPL(2U)                   /*!< maximum packet length 16 bytes */
#define EP0MPL_8                  DEP0_MPL(3U)                   /*!< maximum packet length 8 bytes */

/* endpoints address */

/* first bit is direction(0 for Rx and 1 for Tx) */
#define EP0_OUT                   ((uint8_t)0x00U)                  /*!< endpoint out 0 */
#define EP0_IN                    ((uint8_t)0x80U)                  /*!< endpoint in 0 */
#define EP1_OUT                   ((uint8_t)0x01U)                  /*!< endpoint out 1 */
#define EP1_IN                    ((uint8_t)0x81U)                  /*!< endpoint in 1 */
#define EP2_OUT                   ((uint8_t)0x02U)                  /*!< endpoint out 2 */
#define EP2_IN                    ((uint8_t)0x82U)                  /*!< endpoint in 2 */
#define EP3_OUT                   ((uint8_t)0x03U)                  /*!< endpoint out 3 */
#define EP3_IN                    ((uint8_t)0x83U)                  /*!< endpoint in 3 */

/* enable global interrupt */
#define USB_GLOBAL_INT_ENABLE()       (USB_GAHBCS |= GAHBCS_GINTEN)

/* disable global interrupt */
#define USB_GLOBAL_INT_DISABLE()      (USB_GAHBCS &= ~GAHBCS_GINTEN)

/* get current operation mode */
#define USB_CURRENT_MODE_GET()        (USB_GINTF & GINTF_COPM)

/* read global interrupt flag */
#define USB_CORE_INTR_READ(x) \
do { \
    uint32_t global_intf = USB_GINTF; \
    (x) = global_intf & USB_GINTEN; \
} while(0)

/* read global interrupt flag */
#define USB_DAOEP_INTR_READ(x) \
do { \
    uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
    uint32_t dev_all_ep_int = USB_DAEPINT; \
    uint32_t out_ep_intb = DAEPINT_OEPITB;  \
    (x) = (dev_all_ep_inten & dev_all_ep_int & out_ep_intb) >> 16; \
} while(0)

/* read out endpoint-x interrupt flag */
#define USB_DOEP_INTR_READ(x, EpID) \
do { \
    uint32_t out_epintf = USB_DOEPxINTF(EpID); \
    (x) = out_epintf & USB_DOEPINTEN; \
} while(0)

/* read all in endpoint interrupt flag */
#define USB_DAIEP_INTR_READ(x) \
do { \
    uint32_t dev_all_ep_inten = USB_DAEPINTEN; \
    uint32_t dev_all_ep_int = USB_DAEPINT; \
    uint32_t in_ep_intb = DAEPINT_IEPITB;  \
    (x) = dev_all_ep_inten & dev_all_ep_int & in_ep_intb; \
} while(0)

/* read in endpoint-x interrupt flag */
#define USB_DIEP_INTR_READ(x, EpID) \
do { \
    uint32_t dev_ep_intf = USB_DIEPxINTF(EpID); \
    uint32_t dev_ep_fifoempty_intf = (((USB_DIEPFEINTEN >> (EpID)) & 0x1U) << 7U); \
    uint32_t dev_inep_inten = USB_DIEPINTEN; \
    (x) = dev_ep_intf & (dev_ep_fifoempty_intf | dev_inep_inten); \
} while(0)

/* generate remote wakup signal */
#define USB_REMOTE_WAKEUP_SET()       (USB_DCTL |= DCTL_RWKUP)

/* no remote wakup signal generate */
#define USB_REMOTE_WAKEUP_RESET()     (USB_DCTL &= ~DCTL_RWKUP)

/* generate soft disconnect */
#define USB_SOFT_DISCONNECT_ENABLE()  (USB_DCTL |= DCTL_SD)

/* no soft disconnect generate */
#define USB_SOFT_DISCONNECT_DISABLE() (USB_DCTL &= ~DCTL_SD)

/* set device address */
#define USB_SET_DEVADDR(DevAddr)      (USB_DCFG |= (DevAddr) << 4U)

/* check whether frame is even */
#define USB_EVEN_FRAME()              (!(USB_HFINFR & 0x01U))

/* read port status */
#define USB_PORT_READ()               (USB_HPCS & (~HPCS_PE) & (~HPCS_PCD) & (~HPCS_PEDC))

/* usb clock initialize */
#define USB_FSLSCLOCK_INIT(ClockFreq) (USB_HCTL &= ~HCTL_CLKSEL | (ClockFreq))

/* get usb current speed */
#define USB_CURRENT_SPEED_GET()       ((USB_HPCS & HPCS_PS) >> 17)

/* get usb current frame */
#define USB_CURRENT_FRAME_GET()       (USB_HFINFR & 0xFFFFU)

#endif /* USB_REGS_H */

redpajama_set_name: RedPajamaGithub


For the third time in her career, Shannon O'Keefe found herself in tears on the television set of a major bowling championship, but this time it was as the winner of the 2017 Smithfield Professional Women's Bowling Association Tour Championship, the first major title of her career.
The 38-year-old right-hander struck six times in the first seven frames of the title match against Kelly Kulick on Wednesday, and claimed her sixth PWBA Tour title by a 222-203 margin. The win brought O'Keefe $20,000, while Kulick took home $10,000 as the runner-up.
The championship round was broadcast live on CBS Sports Network from Richmond Raceway's Old Dominion Building in Richmond, Va.
O'Keefe was slowed only by a 3-6-7-10 split in the 3rd frame, which she was unable to convert, but converted a 10-pin in her final frame and got nine on her fill ball to shut out Kulick, whose only strike in the second half of the game came on her fill ball.
The last time O'Keefe bowled for a major title was in the 2015 U.S. Women's Open, in which she left, and missed, a final-frame washout, allowing United States Bowling Congress Hall of Famer Liz Johnson to claim the second of her four consecutive titles in that event.
This win also nearly got away from O'Keefe, who left a 4-6-7-10 split in the 10th frame of her semifinal match with Johnson. O'Keefe entered the final frame on a string of five consecutive strikes, and the miscue allowed Johnson to throw a strike and then pick up a 7-pin for a 222 tie.
As the point standings leader each season since the PWBA Tour returned in 2015, Johnson had been seeded into the televised portion of the event. But the three-time reigning PWBA Player of the Year has not been able to advance to the title match.
On her way to the final Wednesday, Kulick built an early lead against Shannon Pluhowsky, and led by nearly 40 pins at the halfway point. Two opens from Pluhowsky in the first six frames proved to be her undoing, and Kulick tossed nine strikes on the way to a 247-191 win.
"I did my job and threw really good shots, and the ball reaction just went away a little bit," said Kulick, whose last major title was the U.S. Women's Open in 2012. "Swishy 7, ring 10… it could've gone either way. Shannon had a good look all week long and bowled great. I have no regrets, but I'm really tired of finishing second.
All eligible 2017 PWBA Tour champions received automatic invitations to the Tour Championship, and the remainder of the 16-player field was filled through the PWBA points list.
O'Keefe earned her spot at the season-ending event with a win at the PWBA St. Petersburg-Clearwater Open. Kulick secured her place with a win at the PWBA Fountain Valley Open. Johnson, the season's only three-time winner, advanced with a win at the PWBA Storm Sacramento Open.
Pluhowsky, whose best finish this season was a runner-up effort at the Nationwide PWBA Rochester Open, was the lone left-hander to qualify for the Tour Championship, and did so via the point list.
Johnson also won two of the season's three majors, the Go Bowling PWBA Players Championship and the U.S. Women's Open, while finishing second at the other, the USBC Queens. Her consistency locked up a third consecutive Player of the Year award before a single ball was thrown at the Tour Championship.
As the top two players on the season point list, Johnson and Kulick earned automatic berths in Wednesday's semifinals, while O'Keefe and Pluhowsky battled their way through a 16-player single-elimination bracket, featuring best-of-five matches.
All rounds of the PWBA Tour Championship leading up to the TV finals were streamed on Xtra Frame, the exclusive online bowling channel of the Professional Bowlers Association. The lanes were specially installed inside the Old Dominion Building by QubicaAMF, the official supplier of bowling equipment for the 2017 Smithfield PWBA Tour Championship.


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Lyft Fined For Not Alerting Chicago About Suspended Driver
AP Newswire
AP Newswire Published: August 14, 2019
Kelly Sullivan, Getty Images
CHICAGO (AP) — Ride-share company Lyft will pay a $10,000 fine for not alerting the city of Chicago about a suspended driver who was working for Uber when he allegedly killed a cab driver.
Lyft admitted it violated Chicago municipal code requiring ride-share companies to notify the city when they deactivate drivers. City officials say the ordinance is intended to flag dangerous drivers so they can't work for other companies.
Lyft was hit with the maximum penalty for failing to report it deactivated driver Fangqi Lu for punching a passenger in July 2018.
Lu was working for Uber on Sept. 2, 2018 when he argued with Anis Tungekar, a 64-year-old taxi driver. Attorney Michael Gallagher, who represents Tungekar's family, said Lu kicked the victim in the head causing him to fall unconscious and die.
Chicago police issued a warrant for Lu's arrest in Tungekar's killing, but officials say he has fled to China.
Categories: Articles, Local News, News


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How an Underappreciated iOS 7 Feature Will Change the World
By Mike Elgan • 3:07 pm, March 22, 2014
A curious download hit Apple's App Store this week: a messaging app called FireChat.
It's a new kind of app because it uses an iOS feature unavailable until version 7: the Multipeer Connectivity Framework. The app was developed by the crowdsourced connectivity provider Open Garden and this is their first iOS app.
The Multipeer Connectivity Framework enables users to flexibly use WiFi and Bluetooth peer-to-peer connections to chat and share photos even without an Internet connection. Big deal, right?
But here's the really big deal — it can enable two users to chat not only without an Internet connection, but also when they are far beyond WiFi and Bluetooth range from each other — connected with a chain of peer-to-peer users between one user and a far-away Internet connection.
It's called wireless mesh networking. And Apple has mainstreamed it in iOS 7. It's going to change everything. Here's why.
It can also extend an Internet connect to a place where none exists — for example, to a hotel basement, cave or to rural areas where cell tower connections are non-existent.
It does that through the mesh networking capability inherent in the Multipeer Connectivity Framework. With multiple users in the area, FireChat can relay messages just like the internet does, from node to node (phone to phone).
(Apple's AirDrop works in the same way, by the way.)
Here's an example. There's an ultramarathon that takes place in California each year on a trail called Skyline-to-the-Sea. It's a roughly 30 mile trail through giant redwood forests where there is no cell connectivity. Using FireChat or some other app that uses iOS 7's Multipeer Connectivity Framework, race volunteers, staff and participants could extend Internet connectivity and communication in an ad hoc mesh network that extends the length of the course.
The benefit of such an ad-hoc network is how trivially easy it is to set up. Everybody just use FireChat or AirDrop or any other similar app. Boom! Connectivity for everyone.
You can imagine the uses in a disaster area where cell towers have been knocked out, or other situations where people need to communicate but where no WiFi or mobile broadband is available.
In many poor countries and areas, people might be able to afford cheap or used phones, but not wireless service fees. Wireless mesh networks can provide free Internet connectivity to entire villages, slums or towns.
And, of course, Multipeer Connectivity Framework-based mesh-networking apps like FireChat can become a factor for young people. For example, parents who have given their kids iPod Touch devices can chat with the family using FireChat without connecting to the Internet.
And teens who get in trouble with their parents and have their phone contracts cancelled or suspended can still chat with friends with their iPhones using FireChat (with the neighbor kid's help).
Because FireChat can be used anonymously, it could be very secure. Not only is it hard or impossible to determine who the anonymous users are, it can't even be hacked remotely over the Internet if no Internet connectivity is being used. This application and the services in iOS 7 that make it possible seem ideal for communication in repressive, Internet censoring countries.
The big picture here, though, which the public hasn't understood at all (because apps like FireChat are so new) is that mesh networking is about to go mainstream for consumer use.
Note that Open Garden, the creator of FireChat, already offers wireless mesh networking on Android, but not in the form of a chat app — it's just the networking.
Apple is a leader here with its Multipeer Connectivity Framework. But it appears that Google is also going big with consumer-level mesh networking also.
Google's senior VP Sundar Pichai was interviewed at SXSW recently, and mentioned mesh networking twice in the context of wearable devices (such as those that support Google's more recently announced Android Wear initiative, and also in the context of home automation.
With Apple and Google building in the foundations for app developers to easily create ad-hoc wireless mesh networks wherever they go, it's only a matter of time before the wonders and power of mesh networking hits the public in a big way.
Think of wireless mesh networking as giving app developers the ability to create tiny, private or public Internets that are limited in time and place. It will have a somewhat similar impact as the Internet itself in how it undermines authority control over communication.
Ubiquitous wireless mesh networking could erase many of the places and situations where connectivity isn't possible, or connectivity over the Internet isn't desirable.
Kudos to Apple for building this into iOS 7. It's the first major mainstream implementation of wireless mesh networking that I'm aware of.
Thanks to Apple's Multipeer Connectivity Framework, wireless mesh networking is here. It's peer-to-peer. Get excited about it.
Posted in: Top stories Tagged: Apple, iOS, iOS 7, iOS apps, iPhone, messaging apps, Opinions


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