text:
/**
 * Support and FAQ: visit Atmel Support
 */

#ifndef _SAMD10_DMAC_COMPONENT_
#define _SAMD10_DMAC_COMPONENT_

/* ========================================================================== */
/**  SOFTWARE API DEFINITION FOR DMAC */
/* ========================================================================== */
/** \addtogroup SAMD10_DMAC Direct Memory Access Controller */
/*@{*/

#define DMAC_U2223
#define REV_DMAC                    0x100

/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t SWRST:1;          /*!< bit:      0  Software Reset                     */
    uint16_t DMAENABLE:1;      /*!< bit:      1  DMA Enable                         */
    uint16_t CRCENABLE:1;      /*!< bit:      2  CRC Enable                         */
    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
    uint16_t LVLEN0:1;         /*!< bit:      8  Priority Level 0 Enable            */
    uint16_t LVLEN1:1;         /*!< bit:      9  Priority Level 1 Enable            */
    uint16_t LVLEN2:1;         /*!< bit:     10  Priority Level 2 Enable            */
    uint16_t LVLEN3:1;         /*!< bit:     11  Priority Level 3 Enable            */
    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  struct {
    uint16_t :8;               /*!< bit:  0.. 7  Reserved                           */
    uint16_t LVLEN:4;          /*!< bit:  8..11  Priority Level x Enable            */
    uint16_t :4;               /*!< bit: 12..15  Reserved                           */
  } vec;                       /*!< Structure used for vec  access                  */
  uint16_t reg;                /*!< Type      used for register access              */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CTRL_OFFSET            0x00         /**< \brief (DMAC_CTRL offset) Control */
#define DMAC_CTRL_RESETVALUE        0x0000       /**< \brief (DMAC_CTRL reset_value) Control */

#define DMAC_CTRL_SWRST_Pos         0            /**< \brief (DMAC_CTRL) Software Reset */
#define DMAC_CTRL_SWRST             (0x1u << DMAC_CTRL_SWRST_Pos)
#define DMAC_CTRL_DMAENABLE_Pos     1            /**< \brief (DMAC_CTRL) DMA Enable */
#define DMAC_CTRL_DMAENABLE         (0x1u << DMAC_CTRL_DMAENABLE_Pos)
#define DMAC_CTRL_CRCENABLE_Pos     2            /**< \brief (DMAC_CTRL) CRC Enable */
#define DMAC_CTRL_CRCENABLE         (0x1u << DMAC_CTRL_CRCENABLE_Pos)
#define DMAC_CTRL_LVLEN0_Pos        8            /**< \brief (DMAC_CTRL) Priority Level 0 Enable */
#define DMAC_CTRL_LVLEN0            (1 << DMAC_CTRL_LVLEN0_Pos)
#define DMAC_CTRL_LVLEN1_Pos        9            /**< \brief (DMAC_CTRL) Priority Level 1 Enable */
#define DMAC_CTRL_LVLEN1            (1 << DMAC_CTRL_LVLEN1_Pos)
#define DMAC_CTRL_LVLEN2_Pos        10           /**< \brief (DMAC_CTRL) Priority Level 2 Enable */
#define DMAC_CTRL_LVLEN2            (1 << DMAC_CTRL_LVLEN2_Pos)
#define DMAC_CTRL_LVLEN3_Pos        11           /**< \brief (DMAC_CTRL) Priority Level 3 Enable */
#define DMAC_CTRL_LVLEN3            (1 << DMAC_CTRL_LVLEN3_Pos)
#define DMAC_CTRL_LVLEN_Pos         8            /**< \brief (DMAC_CTRL) Priority Level x Enable */
#define DMAC_CTRL_LVLEN_Msk         (0xFu << DMAC_CTRL_LVLEN_Pos)
#define DMAC_CTRL_LVLEN(value)      ((DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)))
#define DMAC_CTRL_MASK              0x0F07u      /**< \brief (DMAC_CTRL) MASK Register */

/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t CRCBEATSIZE:2;    /*!< bit:  0.. 1  CRC Beat Size                      */
    uint16_t CRCPOLY:2;        /*!< bit:  2.. 3  CRC Polynomial Type                */
    uint16_t :4;               /*!< bit:  4.. 7  Reserved                           */
    uint16_t CRCSRC:6;         /*!< bit:  8..13  CRC Input Source                   */
    uint16_t :2;               /*!< bit: 14..15  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint16_t reg;                /*!< Type      used for register access              */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CRCCTRL_OFFSET         0x02         /**< \brief (DMAC_CRCCTRL offset) CRC Control */
#define DMAC_CRCCTRL_RESETVALUE     0x0000       /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */

#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0            /**< \brief (DMAC_CRCCTRL) CRC Beat Size */
#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3u << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define DMAC_CRCCTRL_CRCBEATSIZE(value) ((DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)))
#define   DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0u   /**< \brief (DMAC_CRCCTRL) Byte bus access */
#define   DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1u   /**< \brief (DMAC_CRCCTRL) Half-word bus access */
#define   DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2u   /**< \brief (DMAC_CRCCTRL) Word bus access */
#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos)
#define DMAC_CRCCTRL_CRCPOLY_Pos    2            /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */
#define DMAC_CRCCTRL_CRCPOLY_Msk    (0x3u << DMAC_CRCCTRL_CRCPOLY_Pos)
#define DMAC_CRCCTRL_CRCPOLY(value) ((DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)))
#define   DMAC_CRCCTRL_CRCPOLY_CRC16_Val  0x0u   /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */
#define   DMAC_CRCCTRL_CRCPOLY_CRC32_Val  0x1u   /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */
#define DMAC_CRCCTRL_CRCPOLY_CRC16  (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
#define DMAC_CRCCTRL_CRCPOLY_CRC32  (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos)
#define DMAC_CRCCTRL_CRCSRC_Pos     8            /**< \brief (DMAC_CRCCTRL) CRC Input Source */
#define DMAC_CRCCTRL_CRCSRC_Msk     (0x3Fu << DMAC_CRCCTRL_CRCSRC_Pos)
#define DMAC_CRCCTRL_CRCSRC(value)  ((DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)))
#define   DMAC_CRCCTRL_CRCSRC_NOACT_Val   0x0u   /**< \brief (DMAC_CRCCTRL) No action */
#define   DMAC_CRCCTRL_CRCSRC_IO_Val      0x1u   /**< \brief (DMAC_CRCCTRL) I/O interface */
#define DMAC_CRCCTRL_CRCSRC_NOACT   (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos)
#define DMAC_CRCCTRL_CRCSRC_IO      (DMAC_CRCCTRL_CRCSRC_IO_Val    << DMAC_CRCCTRL_CRCSRC_Pos)
#define DMAC_CRCCTRL_MASK           0x3F0Fu      /**< \brief (DMAC_CRCCTRL) MASK Register */

/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t CRCDATAIN:32;     /*!< bit:  0..31  CRC Data Input                     */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CRCDATAIN_OFFSET       0x04         /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */
#define DMAC_CRCDATAIN_RESETVALUE   0x00000000   /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */

#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0            /**< \brief (DMAC_CRCDATAIN) CRC Data Input */
#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFu << DMAC_CRCDATAIN_CRCDATAIN_Pos)
#define DMAC_CRCDATAIN_CRCDATAIN(value) ((DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)))
#define DMAC_CRCDATAIN_MASK         0xFFFFFFFFu  /**< \brief (DMAC_CRCDATAIN) MASK Register */

/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t CRCCHKSUM:32;     /*!< bit:  0..31  CRC Checksum                       */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CRCCHKSUM_OFFSET       0x08         /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */
#define DMAC_CRCCHKSUM_RESETVALUE   0x00000000   /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */

#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0            /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */
#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFu << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)
#define DMAC_CRCCHKSUM_CRCCHKSUM(value) ((DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)))
#define DMAC_CRCCHKSUM_MASK         0xFFFFFFFFu  /**< \brief (DMAC_CRCCHKSUM) MASK Register */

/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W  8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  CRCBUSY:1;        /*!< bit:      0  CRC Module Busy                    */
    uint8_t  CRCZERO:1;        /*!< bit:      1  CRC Zero                           */
    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CRCSTATUS_OFFSET       0x0C         /**< \brief (DMAC_CRCSTATUS offset) CRC Status */
#define DMAC_CRCSTATUS_RESETVALUE   0x00         /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */

#define DMAC_CRCSTATUS_CRCBUSY_Pos  0            /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */
#define DMAC_CRCSTATUS_CRCBUSY      (0x1u << DMAC_CRCSTATUS_CRCBUSY_Pos)
#define DMAC_CRCSTATUS_CRCZERO_Pos  1            /**< \brief (DMAC_CRCSTATUS) CRC Zero */
#define DMAC_CRCSTATUS_CRCZERO      (0x1u << DMAC_CRCSTATUS_CRCZERO_Pos)
#define DMAC_CRCSTATUS_MASK         0x03u        /**< \brief (DMAC_CRCSTATUS) MASK Register */

/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W  8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  DBGRUN:1;         /*!< bit:      0  Debug Run                          */
    uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_DBGCTRL_OFFSET         0x0D         /**< \brief (DMAC_DBGCTRL offset) Debug Control */
#define DMAC_DBGCTRL_RESETVALUE     0x00         /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */

#define DMAC_DBGCTRL_DBGRUN_Pos     0            /**< \brief (DMAC_DBGCTRL) Debug Run */
#define DMAC_DBGCTRL_DBGRUN         (0x1u << DMAC_DBGCTRL_DBGRUN_Pos)
#define DMAC_DBGCTRL_MASK           0x01u        /**< \brief (DMAC_DBGCTRL) MASK Register */

/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t SWTRIG0:1;        /*!< bit:      0  Channel 0 Software Trigger         */
    uint32_t SWTRIG1:1;        /*!< bit:      1  Channel 1 Software Trigger         */
    uint32_t SWTRIG2:1;        /*!< bit:      2  Channel 2 Software Trigger         */
    uint32_t SWTRIG3:1;        /*!< bit:      3  Channel 3 Software Trigger         */
    uint32_t SWTRIG4:1;        /*!< bit:      4  Channel 4 Software Trigger         */
    uint32_t SWTRIG5:1;        /*!< bit:      5  Channel 5 Software Trigger         */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  struct {
    uint32_t SWTRIG:6;         /*!< bit:  0.. 5  Channel x Software Trigger         */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } vec;                       /*!< Structure used for vec  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_SWTRIGCTRL_OFFSET      0x10         /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */
#define DMAC_SWTRIGCTRL_RESETVALUE  0x00000000   /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */

#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0            /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG0     (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1            /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG1     (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2            /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG2     (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3            /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG3     (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4            /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG4     (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5            /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG5     (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG_Pos  0            /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */
#define DMAC_SWTRIGCTRL_SWTRIG_Msk  (0x3Fu << DMAC_SWTRIGCTRL_SWTRIG_Pos)
#define DMAC_SWTRIGCTRL_SWTRIG(value) ((DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)))
#define DMAC_SWTRIGCTRL_MASK        0x0000003Fu  /**< \brief (DMAC_SWTRIGCTRL) MASK Register */

/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t LVLPRI0:3;        /*!< bit:  0.. 2  Level 0 Channel Priority Number    */
    uint32_t :4;               /*!< bit:  3.. 6  Reserved                           */
    uint32_t RRLVLEN0:1;       /*!< bit:      7  Level 0 Round-Robin Scheduling Enable */
    uint32_t LVLPRI1:3;        /*!< bit:  8..10  Level 1 Channel Priority Number    */
    uint32_t :4;               /*!< bit: 11..14  Reserved                           */
    uint32_t RRLVLEN1:1;       /*!< bit:     15  Level 1 Round-Robin Scheduling Enable */
    uint32_t LVLPRI2:3;        /*!< bit: 16..18  Level 2 Channel Priority Number    */
    uint32_t :4;               /*!< bit: 19..22  Reserved                           */
    uint32_t RRLVLEN2:1;       /*!< bit:     23  Level 2 Round-Robin Scheduling Enable */
    uint32_t LVLPRI3:3;        /*!< bit: 24..26  Level 3 Channel Priority Number    */
    uint32_t :4;               /*!< bit: 27..30  Reserved                           */
    uint32_t RRLVLEN3:1;       /*!< bit:     31  Level 3 Round-Robin Scheduling Enable */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_PRICTRL0_OFFSET        0x14         /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */
#define DMAC_PRICTRL0_RESETVALUE    0x00000000   /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */

#define DMAC_PRICTRL0_LVLPRI0_Pos   0            /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */
#define DMAC_PRICTRL0_LVLPRI0_Msk   (0x7u << DMAC_PRICTRL0_LVLPRI0_Pos)
#define DMAC_PRICTRL0_LVLPRI0(value) ((DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)))
#define DMAC_PRICTRL0_RRLVLEN0_Pos  7            /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */
#define DMAC_PRICTRL0_RRLVLEN0      (0x1u << DMAC_PRICTRL0_RRLVLEN0_Pos)
#define DMAC_PRICTRL0_LVLPRI1_Pos   8            /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */
#define DMAC_PRICTRL0_LVLPRI1_Msk   (0x7u << DMAC_PRICTRL0_LVLPRI1_Pos)
#define DMAC_PRICTRL0_LVLPRI1(value) ((DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)))
#define DMAC_PRICTRL0_RRLVLEN1_Pos  15           /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */
#define DMAC_PRICTRL0_RRLVLEN1      (0x1u << DMAC_PRICTRL0_RRLVLEN1_Pos)
#define DMAC_PRICTRL0_LVLPRI2_Pos   16           /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */
#define DMAC_PRICTRL0_LVLPRI2_Msk   (0x7u << DMAC_PRICTRL0_LVLPRI2_Pos)
#define DMAC_PRICTRL0_LVLPRI2(value) ((DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)))
#define DMAC_PRICTRL0_RRLVLEN2_Pos  23           /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */
#define DMAC_PRICTRL0_RRLVLEN2      (0x1u << DMAC_PRICTRL0_RRLVLEN2_Pos)
#define DMAC_PRICTRL0_LVLPRI3_Pos   24           /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */
#define DMAC_PRICTRL0_LVLPRI3_Msk   (0x7u << DMAC_PRICTRL0_LVLPRI3_Pos)
#define DMAC_PRICTRL0_LVLPRI3(value) ((DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)))
#define DMAC_PRICTRL0_RRLVLEN3_Pos  31           /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */
#define DMAC_PRICTRL0_RRLVLEN3      (0x1u << DMAC_PRICTRL0_RRLVLEN3_Pos)
#define DMAC_PRICTRL0_MASK          0x87878787u  /**< \brief (DMAC_PRICTRL0) MASK Register */

/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t ID:3;             /*!< bit:  0.. 2  Channel ID                         */
    uint16_t :5;               /*!< bit:  3.. 7  Reserved                           */
    uint16_t TERR:1;           /*!< bit:      8  Transfer Error                     */
    uint16_t TCMPL:1;          /*!< bit:      9  Transfer Complete                  */
    uint16_t SUSP:1;           /*!< bit:     10  Channel Suspend                    */
    uint16_t :2;               /*!< bit: 11..12  Reserved                           */
    uint16_t FERR:1;           /*!< bit:     13  Fetch Error                        */
    uint16_t BUSY:1;           /*!< bit:     14  Busy                               */
    uint16_t PEND:1;           /*!< bit:     15  Pending                            */
  } bit;                       /*!< Structure used for bit  access                  */
  uint16_t reg;                /*!< Type      used for register access              */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_INTPEND_OFFSET         0x20         /**< \brief (DMAC_INTPEND offset) Interrupt Pending */
#define DMAC_INTPEND_RESETVALUE     0x0000       /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */

#define DMAC_INTPEND_ID_Pos         0            /**< \brief (DMAC_INTPEND) Channel ID */
#define DMAC_INTPEND_ID_Msk         (0x7u << DMAC_INTPEND_ID_Pos)
#define DMAC_INTPEND_ID(value)      ((DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)))
#define DMAC_INTPEND_TERR_Pos       8            /**< \brief (DMAC_INTPEND) Transfer Error */
#define DMAC_INTPEND_TERR           (0x1u << DMAC_INTPEND_TERR_Pos)
#define DMAC_INTPEND_TCMPL_Pos      9            /**< \brief (DMAC_INTPEND) Transfer Complete */
#define DMAC_INTPEND_TCMPL          (0x1u << DMAC_INTPEND_TCMPL_Pos)
#define DMAC_INTPEND_SUSP_Pos       10           /**< \brief (DMAC_INTPEND) Channel Suspend */
#define DMAC_INTPEND_SUSP           (0x1u << DMAC_INTPEND_SUSP_Pos)
#define DMAC_INTPEND_FERR_Pos       13           /**< \brief (DMAC_INTPEND) Fetch Error */
#define DMAC_INTPEND_FERR           (0x1u << DMAC_INTPEND_FERR_Pos)
#define DMAC_INTPEND_BUSY_Pos       14           /**< \brief (DMAC_INTPEND) Busy */
#define DMAC_INTPEND_BUSY           (0x1u << DMAC_INTPEND_BUSY_Pos)
#define DMAC_INTPEND_PEND_Pos       15           /**< \brief (DMAC_INTPEND) Pending */
#define DMAC_INTPEND_PEND           (0x1u << DMAC_INTPEND_PEND_Pos)
#define DMAC_INTPEND_MASK           0xE707u      /**< \brief (DMAC_INTPEND) MASK Register */

/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/  32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t CHINT0:1;         /*!< bit:      0  Channel 0 Pending Interrupt        */
    uint32_t CHINT1:1;         /*!< bit:      1  Channel 1 Pending Interrupt        */
    uint32_t CHINT2:1;         /*!< bit:      2  Channel 2 Pending Interrupt        */
    uint32_t CHINT3:1;         /*!< bit:      3  Channel 3 Pending Interrupt        */
    uint32_t CHINT4:1;         /*!< bit:      4  Channel 4 Pending Interrupt        */
    uint32_t CHINT5:1;         /*!< bit:      5  Channel 5 Pending Interrupt        */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  struct {
    uint32_t CHINT:6;          /*!< bit:  0.. 5  Channel x Pending Interrupt        */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } vec;                       /*!< Structure used for vec  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_INTSTATUS_OFFSET       0x24         /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */
#define DMAC_INTSTATUS_RESETVALUE   0x00000000   /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */

#define DMAC_INTSTATUS_CHINT0_Pos   0            /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */
#define DMAC_INTSTATUS_CHINT0       (1 << DMAC_INTSTATUS_CHINT0_Pos)
#define DMAC_INTSTATUS_CHINT1_Pos   1            /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */
#define DMAC_INTSTATUS_CHINT1       (1 << DMAC_INTSTATUS_CHINT1_Pos)
#define DMAC_INTSTATUS_CHINT2_Pos   2            /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */
#define DMAC_INTSTATUS_CHINT2       (1 << DMAC_INTSTATUS_CHINT2_Pos)
#define DMAC_INTSTATUS_CHINT3_Pos   3            /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */
#define DMAC_INTSTATUS_CHINT3       (1 << DMAC_INTSTATUS_CHINT3_Pos)
#define DMAC_INTSTATUS_CHINT4_Pos   4            /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */
#define DMAC_INTSTATUS_CHINT4       (1 << DMAC_INTSTATUS_CHINT4_Pos)
#define DMAC_INTSTATUS_CHINT5_Pos   5            /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */
#define DMAC_INTSTATUS_CHINT5       (1 << DMAC_INTSTATUS_CHINT5_Pos)
#define DMAC_INTSTATUS_CHINT_Pos    0            /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */
#define DMAC_INTSTATUS_CHINT_Msk    (0x3Fu << DMAC_INTSTATUS_CHINT_Pos)
#define DMAC_INTSTATUS_CHINT(value) ((DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)))
#define DMAC_INTSTATUS_MASK         0x0000003Fu  /**< \brief (DMAC_INTSTATUS) MASK Register */

/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/  32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t BUSYCH0:1;        /*!< bit:      0  Busy Channel 0                     */
    uint32_t BUSYCH1:1;        /*!< bit:      1  Busy Channel 1                     */
    uint32_t BUSYCH2:1;        /*!< bit:      2  Busy Channel 2                     */
    uint32_t BUSYCH3:1;        /*!< bit:      3  Busy Channel 3                     */
    uint32_t BUSYCH4:1;        /*!< bit:      4  Busy Channel 4                     */
    uint32_t BUSYCH5:1;        /*!< bit:      5  Busy Channel 5                     */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  struct {
    uint32_t BUSYCH:6;         /*!< bit:  0.. 5  Busy Channel x                     */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } vec;                       /*!< Structure used for vec  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_BUSYCH_OFFSET          0x28         /**< \brief (DMAC_BUSYCH offset) Busy Channels */
#define DMAC_BUSYCH_RESETVALUE      0x00000000   /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */

#define DMAC_BUSYCH_BUSYCH0_Pos     0            /**< \brief (DMAC_BUSYCH) Busy Channel 0 */
#define DMAC_BUSYCH_BUSYCH0         (1 << DMAC_BUSYCH_BUSYCH0_Pos)
#define DMAC_BUSYCH_BUSYCH1_Pos     1            /**< \brief (DMAC_BUSYCH) Busy Channel 1 */
#define DMAC_BUSYCH_BUSYCH1         (1 << DMAC_BUSYCH_BUSYCH1_Pos)
#define DMAC_BUSYCH_BUSYCH2_Pos     2            /**< \brief (DMAC_BUSYCH) Busy Channel 2 */
#define DMAC_BUSYCH_BUSYCH2         (1 << DMAC_BUSYCH_BUSYCH2_Pos)
#define DMAC_BUSYCH_BUSYCH3_Pos     3            /**< \brief (DMAC_BUSYCH) Busy Channel 3 */
#define DMAC_BUSYCH_BUSYCH3         (1 << DMAC_BUSYCH_BUSYCH3_Pos)
#define DMAC_BUSYCH_BUSYCH4_Pos     4            /**< \brief (DMAC_BUSYCH) Busy Channel 4 */
#define DMAC_BUSYCH_BUSYCH4         (1 << DMAC_BUSYCH_BUSYCH4_Pos)
#define DMAC_BUSYCH_BUSYCH5_Pos     5            /**< \brief (DMAC_BUSYCH) Busy Channel 5 */
#define DMAC_BUSYCH_BUSYCH5         (1 << DMAC_BUSYCH_BUSYCH5_Pos)
#define DMAC_BUSYCH_BUSYCH_Pos      0            /**< \brief (DMAC_BUSYCH) Busy Channel x */
#define DMAC_BUSYCH_BUSYCH_Msk      (0x3Fu << DMAC_BUSYCH_BUSYCH_Pos)
#define DMAC_BUSYCH_BUSYCH(value)   ((DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)))
#define DMAC_BUSYCH_MASK            0x0000003Fu  /**< \brief (DMAC_BUSYCH) MASK Register */

/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/  32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t PENDCH0:1;        /*!< bit:      0  Pending Channel 0                  */
    uint32_t PENDCH1:1;        /*!< bit:      1  Pending Channel 1                  */
    uint32_t PENDCH2:1;        /*!< bit:      2  Pending Channel 2                  */
    uint32_t PENDCH3:1;        /*!< bit:      3  Pending Channel 3                  */
    uint32_t PENDCH4:1;        /*!< bit:      4  Pending Channel 4                  */
    uint32_t PENDCH5:1;        /*!< bit:      5  Pending Channel 5                  */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  struct {
    uint32_t PENDCH:6;         /*!< bit:  0.. 5  Pending Channel x                  */
    uint32_t :26;              /*!< bit:  6..31  Reserved                           */
  } vec;                       /*!< Structure used for vec  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_PENDCH_OFFSET          0x2C         /**< \brief (DMAC_PENDCH offset) Pending Channels */
#define DMAC_PENDCH_RESETVALUE      0x00000000   /**< \brief (DMAC_PENDCH reset_value) Pending Channels */

#define DMAC_PENDCH_PENDCH0_Pos     0            /**< \brief (DMAC_PENDCH) Pending Channel 0 */
#define DMAC_PENDCH_PENDCH0         (1 << DMAC_PENDCH_PENDCH0_Pos)
#define DMAC_PENDCH_PENDCH1_Pos     1            /**< \brief (DMAC_PENDCH) Pending Channel 1 */
#define DMAC_PENDCH_PENDCH1         (1 << DMAC_PENDCH_PENDCH1_Pos)
#define DMAC_PENDCH_PENDCH2_Pos     2            /**< \brief (DMAC_PENDCH) Pending Channel 2 */
#define DMAC_PENDCH_PENDCH2         (1 << DMAC_PENDCH_PENDCH2_Pos)
#define DMAC_PENDCH_PENDCH3_Pos     3            /**< \brief (DMAC_PENDCH) Pending Channel 3 */
#define DMAC_PENDCH_PENDCH3         (1 << DMAC_PENDCH_PENDCH3_Pos)
#define DMAC_PENDCH_PENDCH4_Pos     4            /**< \brief (DMAC_PENDCH) Pending Channel 4 */
#define DMAC_PENDCH_PENDCH4         (1 << DMAC_PENDCH_PENDCH4_Pos)
#define DMAC_PENDCH_PENDCH5_Pos     5            /**< \brief (DMAC_PENDCH) Pending Channel 5 */
#define DMAC_PENDCH_PENDCH5         (1 << DMAC_PENDCH_PENDCH5_Pos)
#define DMAC_PENDCH_PENDCH_Pos      0            /**< \brief (DMAC_PENDCH) Pending Channel x */
#define DMAC_PENDCH_PENDCH_Msk      (0x3Fu << DMAC_PENDCH_PENDCH_Pos)
#define DMAC_PENDCH_PENDCH(value)   ((DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)))
#define DMAC_PENDCH_MASK            0x0000003Fu  /**< \brief (DMAC_PENDCH) MASK Register */

/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/  32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t LVLEX0:1;         /*!< bit:      0  Level 0 Channel Trigger Request Executing */
    uint32_t LVLEX1:1;         /*!< bit:      1  Level 1 Channel Trigger Request Executing */
    uint32_t LVLEX2:1;         /*!< bit:      2  Level 2 Channel Trigger Request Executing */
    uint32_t LVLEX3:1;         /*!< bit:      3  Level 3 Channel Trigger Request Executing */
    uint32_t :4;               /*!< bit:  4.. 7  Reserved                           */
    uint32_t ID:5;             /*!< bit:  8..12  Active Channel ID                  */
    uint32_t :2;               /*!< bit: 13..14  Reserved                           */
    uint32_t ABUSY:1;          /*!< bit:     15  Active Channel Busy                */
    uint32_t BTCNT:16;         /*!< bit: 16..31  Active Channel Block Transfer Count */
  } bit;                       /*!< Structure used for bit  access                  */
  struct {
    uint32_t LVLEX:4;          /*!< bit:  0.. 3  Level x Channel Trigger Request Executing */
    uint32_t :28;              /*!< bit:  4..31  Reserved                           */
  } vec;                       /*!< Structure used for vec  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_ACTIVE_OFFSET          0x30         /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */
#define DMAC_ACTIVE_RESETVALUE      0x00000000   /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */

#define DMAC_ACTIVE_LVLEX0_Pos      0            /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */
#define DMAC_ACTIVE_LVLEX0          (1 << DMAC_ACTIVE_LVLEX0_Pos)
#define DMAC_ACTIVE_LVLEX1_Pos      1            /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */
#define DMAC_ACTIVE_LVLEX1          (1 << DMAC_ACTIVE_LVLEX1_Pos)
#define DMAC_ACTIVE_LVLEX2_Pos      2            /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */
#define DMAC_ACTIVE_LVLEX2          (1 << DMAC_ACTIVE_LVLEX2_Pos)
#define DMAC_ACTIVE_LVLEX3_Pos      3            /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */
#define DMAC_ACTIVE_LVLEX3          (1 << DMAC_ACTIVE_LVLEX3_Pos)
#define DMAC_ACTIVE_LVLEX_Pos       0            /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */
#define DMAC_ACTIVE_LVLEX_Msk       (0xFu << DMAC_ACTIVE_LVLEX_Pos)
#define DMAC_ACTIVE_LVLEX(value)    ((DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)))
#define DMAC_ACTIVE_ID_Pos          8            /**< \brief (DMAC_ACTIVE) Active Channel ID */
#define DMAC_ACTIVE_ID_Msk          (0x1Fu << DMAC_ACTIVE_ID_Pos)
#define DMAC_ACTIVE_ID(value)       ((DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)))
#define DMAC_ACTIVE_ABUSY_Pos       15           /**< \brief (DMAC_ACTIVE) Active Channel Busy */
#define DMAC_ACTIVE_ABUSY           (0x1u << DMAC_ACTIVE_ABUSY_Pos)
#define DMAC_ACTIVE_BTCNT_Pos       16           /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */
#define DMAC_ACTIVE_BTCNT_Msk       (0xFFFFu << DMAC_ACTIVE_BTCNT_Pos)
#define DMAC_ACTIVE_BTCNT(value)    ((DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)))
#define DMAC_ACTIVE_MASK            0xFFFF9F0Fu  /**< \brief (DMAC_ACTIVE) MASK Register */

/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t BASEADDR:32;      /*!< bit:  0..31  Descriptor Memory Base Address     */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_BASEADDR_OFFSET        0x34         /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */
#define DMAC_BASEADDR_RESETVALUE    0x00000000   /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */

#define DMAC_BASEADDR_BASEADDR_Pos  0            /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */
#define DMAC_BASEADDR_BASEADDR_Msk  (0xFFFFFFFFu << DMAC_BASEADDR_BASEADDR_Pos)
#define DMAC_BASEADDR_BASEADDR(value) ((DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)))
#define DMAC_BASEADDR_MASK          0xFFFFFFFFu  /**< \brief (DMAC_BASEADDR) MASK Register */

/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t WRBADDR:32;       /*!< bit:  0..31  Write-Back Memory Base Address     */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_WRBADDR_OFFSET         0x38         /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */
#define DMAC_WRBADDR_RESETVALUE     0x00000000   /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */

#define DMAC_WRBADDR_WRBADDR_Pos    0            /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */
#define DMAC_WRBADDR_WRBADDR_Msk    (0xFFFFFFFFu << DMAC_WRBADDR_WRBADDR_Pos)
#define DMAC_WRBADDR_WRBADDR(value) ((DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)))
#define DMAC_WRBADDR_MASK           0xFFFFFFFFu  /**< \brief (DMAC_WRBADDR) MASK Register */

/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W  8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  ID:3;             /*!< bit:  0.. 2  Channel ID                         */
    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHID_OFFSET            0x3F         /**< \brief (DMAC_CHID offset) Channel ID */
#define DMAC_CHID_RESETVALUE        0x00         /**< \brief (DMAC_CHID reset_value) Channel ID */

#define DMAC_CHID_ID_Pos            0            /**< \brief (DMAC_CHID) Channel ID */
#define DMAC_CHID_ID_Msk            (0x7u << DMAC_CHID_ID_Pos)
#define DMAC_CHID_ID(value)         ((DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)))
#define DMAC_CHID_MASK              0x07u        /**< \brief (DMAC_CHID) MASK Register */

/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W  8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  SWRST:1;          /*!< bit:      0  Channel Software Reset             */
    uint8_t  ENABLE:1;         /*!< bit:      1  Channel Enable                     */
    uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHCTRLA_OFFSET         0x40         /**< \brief (DMAC_CHCTRLA offset) Channel Control A */
#define DMAC_CHCTRLA_RESETVALUE     0x00         /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */

#define DMAC_CHCTRLA_SWRST_Pos      0            /**< \brief (DMAC_CHCTRLA) Channel Software Reset */
#define DMAC_CHCTRLA_SWRST          (0x1u << DMAC_CHCTRLA_SWRST_Pos)
#define DMAC_CHCTRLA_ENABLE_Pos     1            /**< \brief (DMAC_CHCTRLA) Channel Enable */
#define DMAC_CHCTRLA_ENABLE         (0x1u << DMAC_CHCTRLA_ENABLE_Pos)
#define DMAC_CHCTRLA_MASK           0x03u        /**< \brief (DMAC_CHCTRLA) MASK Register */

/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t EVACT:3;          /*!< bit:  0.. 2  Event Input Action                 */
    uint32_t EVIE:1;           /*!< bit:      3  Channel Event Input Enable         */
    uint32_t EVOE:1;           /*!< bit:      4  Channel Event Output Enable        */
    uint32_t LVL:2;            /*!< bit:  5.. 6  Channel Arbitration Level          */
    uint32_t :1;               /*!< bit:      7  Reserved                           */
    uint32_t TRIGSRC:5;        /*!< bit:  8..12  Peripheral Trigger Source          */
    uint32_t :9;               /*!< bit: 13..21  Reserved                           */
    uint32_t TRIGACT:2;        /*!< bit: 22..23  Trigger Action                     */
    uint32_t CMD:2;            /*!< bit: 24..25  Software Command                   */
    uint32_t :6;               /*!< bit: 26..31  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHCTRLB_OFFSET         0x44         /**< \brief (DMAC_CHCTRLB offset) Channel Control B */
#define DMAC_CHCTRLB_RESETVALUE     0x00000000   /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */

#define DMAC_CHCTRLB_EVACT_Pos      0            /**< \brief (DMAC_CHCTRLB) Event Input Action */
#define DMAC_CHCTRLB_EVACT_Msk      (0x7u << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT(value)   ((DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)))
#define   DMAC_CHCTRLB_EVACT_NOACT_Val    0x0u   /**< \brief (DMAC_CHCTRLB) No action */
#define   DMAC_CHCTRLB_EVACT_TRIG_Val     0x1u   /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */
#define   DMAC_CHCTRLB_EVACT_CTRIG_Val    0x2u   /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */
#define   DMAC_CHCTRLB_EVACT_CBLOCK_Val   0x3u   /**< \brief (DMAC_CHCTRLB) Conditional block transfer */
#define   DMAC_CHCTRLB_EVACT_SUSPEND_Val  0x4u   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
#define   DMAC_CHCTRLB_EVACT_RESUME_Val   0x5u   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
#define   DMAC_CHCTRLB_EVACT_SSKIP_Val    0x6u   /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */
#define DMAC_CHCTRLB_EVACT_NOACT    (DMAC_CHCTRLB_EVACT_NOACT_Val  << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT_TRIG     (DMAC_CHCTRLB_EVACT_TRIG_Val   << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT_CTRIG    (DMAC_CHCTRLB_EVACT_CTRIG_Val  << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT_CBLOCK   (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT_SUSPEND  (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT_RESUME   (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVACT_SSKIP    (DMAC_CHCTRLB_EVACT_SSKIP_Val  << DMAC_CHCTRLB_EVACT_Pos)
#define DMAC_CHCTRLB_EVIE_Pos       3            /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */
#define DMAC_CHCTRLB_EVIE           (0x1u << DMAC_CHCTRLB_EVIE_Pos)
#define DMAC_CHCTRLB_EVOE_Pos       4            /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */
#define DMAC_CHCTRLB_EVOE           (0x1u << DMAC_CHCTRLB_EVOE_Pos)
#define DMAC_CHCTRLB_LVL_Pos        5            /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */
#define DMAC_CHCTRLB_LVL_Msk        (0x3u << DMAC_CHCTRLB_LVL_Pos)
#define DMAC_CHCTRLB_LVL(value)     ((DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)))
#define DMAC_CHCTRLB_TRIGSRC_Pos    8            /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */
#define DMAC_CHCTRLB_TRIGSRC_Msk    (0x1Fu << DMAC_CHCTRLB_TRIGSRC_Pos)
#define DMAC_CHCTRLB_TRIGSRC(value) ((DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)))
#define   DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0u   /**< \brief (DMAC_CHCTRLB) Only software/event triggers */
#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos)
#define DMAC_CHCTRLB_TRIGACT_Pos    22           /**< \brief (DMAC_CHCTRLB) Trigger Action */
#define DMAC_CHCTRLB_TRIGACT_Msk    (0x3u << DMAC_CHCTRLB_TRIGACT_Pos)
#define DMAC_CHCTRLB_TRIGACT(value) ((DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)))
#define   DMAC_CHCTRLB_TRIGACT_BLOCK_Val  0x0u   /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */
#define   DMAC_CHCTRLB_TRIGACT_BEAT_Val   0x2u   /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */
#define   DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3u   /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */
#define DMAC_CHCTRLB_TRIGACT_BLOCK  (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos)
#define DMAC_CHCTRLB_TRIGACT_BEAT   (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos)
#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos)
#define DMAC_CHCTRLB_CMD_Pos        24           /**< \brief (DMAC_CHCTRLB) Software Command */
#define DMAC_CHCTRLB_CMD_Msk        (0x3u << DMAC_CHCTRLB_CMD_Pos)
#define DMAC_CHCTRLB_CMD(value)     ((DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)))
#define   DMAC_CHCTRLB_CMD_NOACT_Val      0x0u   /**< \brief (DMAC_CHCTRLB) No action */
#define   DMAC_CHCTRLB_CMD_SUSPEND_Val    0x1u   /**< \brief (DMAC_CHCTRLB) Channel suspend operation */
#define   DMAC_CHCTRLB_CMD_RESUME_Val     0x2u   /**< \brief (DMAC_CHCTRLB) Channel resume operation */
#define DMAC_CHCTRLB_CMD_NOACT      (DMAC_CHCTRLB_CMD_NOACT_Val    << DMAC_CHCTRLB_CMD_Pos)
#define DMAC_CHCTRLB_CMD_SUSPEND    (DMAC_CHCTRLB_CMD_SUSPEND_Val  << DMAC_CHCTRLB_CMD_Pos)
#define DMAC_CHCTRLB_CMD_RESUME     (DMAC_CHCTRLB_CMD_RESUME_Val   << DMAC_CHCTRLB_CMD_Pos)
#define DMAC_CHCTRLB_MASK           0x03C01F7Fu  /**< \brief (DMAC_CHCTRLB) MASK Register */

/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W  8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHINTENCLR_OFFSET      0x4C         /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */
#define DMAC_CHINTENCLR_RESETVALUE  0x00         /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */

#define DMAC_CHINTENCLR_TERR_Pos    0            /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */
#define DMAC_CHINTENCLR_TERR        (0x1u << DMAC_CHINTENCLR_TERR_Pos)
#define DMAC_CHINTENCLR_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */
#define DMAC_CHINTENCLR_TCMPL       (0x1u << DMAC_CHINTENCLR_TCMPL_Pos)
#define DMAC_CHINTENCLR_SUSP_Pos    2            /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */
#define DMAC_CHINTENCLR_SUSP        (0x1u << DMAC_CHINTENCLR_SUSP_Pos)
#define DMAC_CHINTENCLR_MASK        0x07u        /**< \brief (DMAC_CHINTENCLR) MASK Register */

/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W  8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error Interrupt Enable    */
    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete Interrupt Enable */
    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend Interrupt Enable   */
    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHINTENSET_OFFSET      0x4D         /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */
#define DMAC_CHINTENSET_RESETVALUE  0x00         /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */

#define DMAC_CHINTENSET_TERR_Pos    0            /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */
#define DMAC_CHINTENSET_TERR        (0x1u << DMAC_CHINTENSET_TERR_Pos)
#define DMAC_CHINTENSET_TCMPL_Pos   1            /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */
#define DMAC_CHINTENSET_TCMPL       (0x1u << DMAC_CHINTENSET_TCMPL_Pos)
#define DMAC_CHINTENSET_SUSP_Pos    2            /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */
#define DMAC_CHINTENSET_SUSP        (0x1u << DMAC_CHINTENSET_SUSP_Pos)
#define DMAC_CHINTENSET_MASK        0x07u        /**< \brief (DMAC_CHINTENSET) MASK Register */

/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W  8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  TERR:1;           /*!< bit:      0  Transfer Error                     */
    uint8_t  TCMPL:1;          /*!< bit:      1  Transfer Complete                  */
    uint8_t  SUSP:1;           /*!< bit:      2  Channel Suspend                    */
    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHINTFLAG_OFFSET       0x4E         /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */
#define DMAC_CHINTFLAG_RESETVALUE   0x00         /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */

#define DMAC_CHINTFLAG_TERR_Pos     0            /**< \brief (DMAC_CHINTFLAG) Transfer Error */
#define DMAC_CHINTFLAG_TERR         (0x1u << DMAC_CHINTFLAG_TERR_Pos)
#define DMAC_CHINTFLAG_TCMPL_Pos    1            /**< \brief (DMAC_CHINTFLAG) Transfer Complete */
#define DMAC_CHINTFLAG_TCMPL        (0x1u << DMAC_CHINTFLAG_TCMPL_Pos)
#define DMAC_CHINTFLAG_SUSP_Pos     2            /**< \brief (DMAC_CHINTFLAG) Channel Suspend */
#define DMAC_CHINTFLAG_SUSP         (0x1u << DMAC_CHINTFLAG_SUSP_Pos)
#define DMAC_CHINTFLAG_MASK         0x07u        /**< \brief (DMAC_CHINTFLAG) MASK Register */

/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/   8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint8_t  PEND:1;           /*!< bit:      0  Channel Pending                    */
    uint8_t  BUSY:1;           /*!< bit:      1  Channel Busy                       */
    uint8_t  FERR:1;           /*!< bit:      2  Fetch Error                        */
    uint8_t  :5;               /*!< bit:  3.. 7  Reserved                           */
  } bit;                       /*!< Structure used for bit  access                  */
  uint8_t reg;                 /*!< Type      used for register access              */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_CHSTATUS_OFFSET        0x4F         /**< \brief (DMAC_CHSTATUS offset) Channel Status */
#define DMAC_CHSTATUS_RESETVALUE    0x00         /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */

#define DMAC_CHSTATUS_PEND_Pos      0            /**< \brief (DMAC_CHSTATUS) Channel Pending */
#define DMAC_CHSTATUS_PEND          (0x1u << DMAC_CHSTATUS_PEND_Pos)
#define DMAC_CHSTATUS_BUSY_Pos      1            /**< \brief (DMAC_CHSTATUS) Channel Busy */
#define DMAC_CHSTATUS_BUSY          (0x1u << DMAC_CHSTATUS_BUSY_Pos)
#define DMAC_CHSTATUS_FERR_Pos      2            /**< \brief (DMAC_CHSTATUS) Fetch Error */
#define DMAC_CHSTATUS_FERR          (0x1u << DMAC_CHSTATUS_FERR_Pos)
#define DMAC_CHSTATUS_MASK          0x07u        /**< \brief (DMAC_CHSTATUS) MASK Register */

/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t VALID:1;          /*!< bit:      0  Descriptor Valid                   */
    uint16_t EVOSEL:2;         /*!< bit:  1.. 2  Event Output Selection             */
    uint16_t BLOCKACT:2;       /*!< bit:  3.. 4  Block Action                       */
    uint16_t :3;               /*!< bit:  5.. 7  Reserved                           */
    uint16_t BEATSIZE:2;       /*!< bit:  8.. 9  Beat Size                          */
    uint16_t SRCINC:1;         /*!< bit:     10  Source Address Increment Enable    */
    uint16_t DSTINC:1;         /*!< bit:     11  Destination Address Increment Enable */
    uint16_t STEPSEL:1;        /*!< bit:     12  Step Selection                     */
    uint16_t STEPSIZE:3;       /*!< bit: 13..15  Address Increment Step Size        */
  } bit;                       /*!< Structure used for bit  access                  */
  uint16_t reg;                /*!< Type      used for register access              */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_BTCTRL_OFFSET          0x00         /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */

#define DMAC_BTCTRL_VALID_Pos       0            /**< \brief (DMAC_BTCTRL) Descriptor Valid */
#define DMAC_BTCTRL_VALID           (0x1u << DMAC_BTCTRL_VALID_Pos)
#define DMAC_BTCTRL_EVOSEL_Pos      1            /**< \brief (DMAC_BTCTRL) Event Output Selection */
#define DMAC_BTCTRL_EVOSEL_Msk      (0x3u << DMAC_BTCTRL_EVOSEL_Pos)
#define DMAC_BTCTRL_EVOSEL(value)   ((DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)))
#define   DMAC_BTCTRL_EVOSEL_DISABLE_Val  0x0u   /**< \brief (DMAC_BTCTRL) Event generation disabled */
#define   DMAC_BTCTRL_EVOSEL_BLOCK_Val    0x1u   /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */
#define   DMAC_BTCTRL_EVOSEL_BEAT_Val     0x3u   /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */
#define DMAC_BTCTRL_EVOSEL_DISABLE  (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos)
#define DMAC_BTCTRL_EVOSEL_BLOCK    (DMAC_BTCTRL_EVOSEL_BLOCK_Val  << DMAC_BTCTRL_EVOSEL_Pos)
#define DMAC_BTCTRL_EVOSEL_BEAT     (DMAC_BTCTRL_EVOSEL_BEAT_Val   << DMAC_BTCTRL_EVOSEL_Pos)
#define DMAC_BTCTRL_BLOCKACT_Pos    3            /**< \brief (DMAC_BTCTRL) Block Action */
#define DMAC_BTCTRL_BLOCKACT_Msk    (0x3u << DMAC_BTCTRL_BLOCKACT_Pos)
#define DMAC_BTCTRL_BLOCKACT(value) ((DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)))
#define   DMAC_BTCTRL_BLOCKACT_NOACT_Val  0x0u   /**< \brief (DMAC_BTCTRL) No action */
#define   DMAC_BTCTRL_BLOCKACT_INT_Val    0x1u   /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */
#define   DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2u   /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */
#define   DMAC_BTCTRL_BLOCKACT_BOTH_Val   0x3u   /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */
#define DMAC_BTCTRL_BLOCKACT_NOACT  (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define DMAC_BTCTRL_BLOCKACT_INT    (DMAC_BTCTRL_BLOCKACT_INT_Val  << DMAC_BTCTRL_BLOCKACT_Pos)
#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define DMAC_BTCTRL_BLOCKACT_BOTH   (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos)
#define DMAC_BTCTRL_BEATSIZE_Pos    8            /**< \brief (DMAC_BTCTRL) Beat Size */
#define DMAC_BTCTRL_BEATSIZE_Msk    (0x3u << DMAC_BTCTRL_BEATSIZE_Pos)
#define DMAC_BTCTRL_BEATSIZE(value) ((DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)))
#define   DMAC_BTCTRL_BEATSIZE_BYTE_Val   0x0u   /**< \brief (DMAC_BTCTRL) 8-bit access */
#define   DMAC_BTCTRL_BEATSIZE_HWORD_Val  0x1u   /**< \brief (DMAC_BTCTRL) 16-bit access */
#define   DMAC_BTCTRL_BEATSIZE_WORD_Val   0x2u   /**< \brief (DMAC_BTCTRL) 32-bit access */
#define DMAC_BTCTRL_BEATSIZE_BYTE   (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos)
#define DMAC_BTCTRL_BEATSIZE_HWORD  (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
#define DMAC_BTCTRL_BEATSIZE_WORD   (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos)
#define DMAC_BTCTRL_SRCINC_Pos      10           /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */
#define DMAC_BTCTRL_SRCINC          (0x1u << DMAC_BTCTRL_SRCINC_Pos)
#define DMAC_BTCTRL_DSTINC_Pos      11           /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */
#define DMAC_BTCTRL_DSTINC          (0x1u << DMAC_BTCTRL_DSTINC_Pos)
#define DMAC_BTCTRL_STEPSEL_Pos     12           /**< \brief (DMAC_BTCTRL) Step Selection */
#define DMAC_BTCTRL_STEPSEL         (0x1u << DMAC_BTCTRL_STEPSEL_Pos)
#define   DMAC_BTCTRL_STEPSEL_DST_Val     0x0u   /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */
#define   DMAC_BTCTRL_STEPSEL_SRC_Val     0x1u   /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */
#define DMAC_BTCTRL_STEPSEL_DST     (DMAC_BTCTRL_STEPSEL_DST_Val   << DMAC_BTCTRL_STEPSEL_Pos)
#define DMAC_BTCTRL_STEPSEL_SRC     (DMAC_BTCTRL_STEPSEL_SRC_Val   << DMAC_BTCTRL_STEPSEL_Pos)
#define DMAC_BTCTRL_STEPSIZE_Pos    13           /**< \brief (DMAC_BTCTRL) Address Increment Step Size */
#define DMAC_BTCTRL_STEPSIZE_Msk    (0x7u << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE(value) ((DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)))
#define   DMAC_BTCTRL_STEPSIZE_X1_Val     0x0u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 1 */
#define   DMAC_BTCTRL_STEPSIZE_X2_Val     0x1u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 2 */
#define   DMAC_BTCTRL_STEPSIZE_X4_Val     0x2u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 4 */
#define   DMAC_BTCTRL_STEPSIZE_X8_Val     0x3u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 8 */
#define   DMAC_BTCTRL_STEPSIZE_X16_Val    0x4u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 16 */
#define   DMAC_BTCTRL_STEPSIZE_X32_Val    0x5u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 32 */
#define   DMAC_BTCTRL_STEPSIZE_X64_Val    0x6u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 64 */
#define   DMAC_BTCTRL_STEPSIZE_X128_Val   0x7u   /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + BEATSIZE * 128 */
#define DMAC_BTCTRL_STEPSIZE_X1     (DMAC_BTCTRL_STEPSIZE_X1_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X2     (DMAC_BTCTRL_STEPSIZE_X2_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X4     (DMAC_BTCTRL_STEPSIZE_X4_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X8     (DMAC_BTCTRL_STEPSIZE_X8_Val   << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X16    (DMAC_BTCTRL_STEPSIZE_X16_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X32    (DMAC_BTCTRL_STEPSIZE_X32_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X64    (DMAC_BTCTRL_STEPSIZE_X64_Val  << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_STEPSIZE_X128   (DMAC_BTCTRL_STEPSIZE_X128_Val << DMAC_BTCTRL_STEPSIZE_Pos)
#define DMAC_BTCTRL_MASK            0xFF1Fu      /**< \brief (DMAC_BTCTRL) MASK Register */

/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint16_t BTCNT:16;         /*!< bit:  0..15  Block Transfer Count               */
  } bit;                       /*!< Structure used for bit  access                  */
  uint16_t reg;                /*!< Type      used for register access              */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_BTCNT_OFFSET           0x02         /**< \brief (DMAC_BTCNT offset) Block Transfer Count */

#define DMAC_BTCNT_BTCNT_Pos        0            /**< \brief (DMAC_BTCNT) Block Transfer Count */
#define DMAC_BTCNT_BTCNT_Msk        (0xFFFFu << DMAC_BTCNT_BTCNT_Pos)
#define DMAC_BTCNT_BTCNT(value)     ((DMAC_BTCNT_BTCNT_Msk & ((value) << DMAC_BTCNT_BTCNT_Pos)))
#define DMAC_BTCNT_MASK             0xFFFFu      /**< \brief (DMAC_BTCNT) MASK Register */

/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t SRCADDR:32;       /*!< bit:  0..31  Transfer Source Address            */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_SRCADDR_OFFSET         0x04         /**< \brief (DMAC_SRCADDR offset) Transfer Source Address */

#define DMAC_SRCADDR_SRCADDR_Pos    0            /**< \brief (DMAC_SRCADDR) Transfer Source Address */
#define DMAC_SRCADDR_SRCADDR_Msk    (0xFFFFFFFFu << DMAC_SRCADDR_SRCADDR_Pos)
#define DMAC_SRCADDR_SRCADDR(value) ((DMAC_SRCADDR_SRCADDR_Msk & ((value) << DMAC_SRCADDR_SRCADDR_Pos)))
#define DMAC_SRCADDR_MASK           0xFFFFFFFFu  /**< \brief (DMAC_SRCADDR) MASK Register */

/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t DSTADDR:32;       /*!< bit:  0..31  Transfer Destination Address       */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_DSTADDR_OFFSET         0x08         /**< \brief (DMAC_DSTADDR offset) Transfer Destination Address */

#define DMAC_DSTADDR_DSTADDR_Pos    0            /**< \brief (DMAC_DSTADDR) Transfer Destination Address */
#define DMAC_DSTADDR_DSTADDR_Msk    (0xFFFFFFFFu << DMAC_DSTADDR_DSTADDR_Pos)
#define DMAC_DSTADDR_DSTADDR(value) ((DMAC_DSTADDR_DSTADDR_Msk & ((value) << DMAC_DSTADDR_DSTADDR_Pos)))
#define DMAC_DSTADDR_MASK           0xFFFFFFFFu  /**< \brief (DMAC_DSTADDR) MASK Register */

/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
  struct {
    uint32_t DESCADDR:32;      /*!< bit:  0..31  Next Descriptor Address            */
  } bit;                       /*!< Structure used for bit  access                  */
  uint32_t reg;                /*!< Type      used for register access              */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#define DMAC_DESCADDR_OFFSET        0x0C         /**< \brief (DMAC_DESCADDR offset) Next Descriptor Address */

#define DMAC_DESCADDR_DESCADDR_Pos  0            /**< \brief (DMAC_DESCADDR) Next Descriptor Address */
#define DMAC_DESCADDR_DESCADDR_Msk  (0xFFFFFFFFu << DMAC_DESCADDR_DESCADDR_Pos)
#define DMAC_DESCADDR_DESCADDR(value) ((DMAC_DESCADDR_DESCADDR_Msk & ((value) << DMAC_DESCADDR_DESCADDR_Pos)))
#define DMAC_DESCADDR_MASK          0xFFFFFFFFu  /**< \brief (DMAC_DESCADDR) MASK Register */

/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __IO DMAC_CTRL_Type            CTRL;        /**< \brief Offset: 0x00 (R/W 16) Control */
  __IO DMAC_CRCCTRL_Type         CRCCTRL;     /**< \brief Offset: 0x02 (R/W 16) CRC Control */
  __IO DMAC_CRCDATAIN_Type       CRCDATAIN;   /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
  __IO DMAC_CRCCHKSUM_Type       CRCCHKSUM;   /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
  __IO DMAC_CRCSTATUS_Type       CRCSTATUS;   /**< \brief Offset: 0x0C (R/W  8) CRC Status */
  __IO DMAC_DBGCTRL_Type         DBGCTRL;     /**< \brief Offset: 0x0D (R/W  8) Debug Control */
       RoReg8                    Reserved1[0x2];
  __IO DMAC_SWTRIGCTRL_Type      SWTRIGCTRL;  /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
  __IO DMAC_PRICTRL0_Type        PRICTRL0;    /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
       RoReg8                    Reserved2[0x8];
  __IO DMAC_INTPEND_Type         INTPEND;     /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
       RoReg8                    Reserved3[0x2];
  __I  DMAC_INTSTATUS_Type       INTSTATUS;   /**< \brief Offset: 0x24 (R/  32) Interrupt Status */
  __I  DMAC_BUSYCH_Type          BUSYCH;      /**< \brief Offset: 0x28 (R/  32) Busy Channels */
  __I  DMAC_PENDCH_Type          PENDCH;      /**< \brief Offset: 0x2C (R/  32) Pending Channels */
  __I  DMAC_ACTIVE_Type          ACTIVE;      /**< \brief Offset: 0x30 (R/  32) Active Channel and Levels */
  __IO DMAC_BASEADDR_Type        BASEADDR;    /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
  __IO DMAC_WRBADDR_Type         WRBADDR;     /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
       RoReg8                    Reserved4[0x3];
  __IO DMAC_CHID_Type            CHID;        /**< \brief Offset: 0x3F (R/W  8) Channel ID */
  __IO DMAC_CHCTRLA_Type         CHCTRLA;     /**< \brief Offset: 0x40 (R/W  8) Channel Control A */
       RoReg8                    Reserved5[0x3];
  __IO DMAC_CHCTRLB_Type         CHCTRLB;     /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
       RoReg8                    Reserved6[0x4];
  __IO DMAC_CHINTENCLR_Type      CHINTENCLR;  /**< \brief Offset: 0x4C (R/W  8) Channel Interrupt Enable Clear */
  __IO DMAC_CHINTENSET_Type      CHINTENSET;  /**< \brief Offset: 0x4D (R/W  8) Channel Interrupt Enable Set */
  __IO DMAC_CHINTFLAG_Type       CHINTFLAG;   /**< \brief Offset: 0x4E (R/W  8) Channel Interrupt Flag Status and Clear */
  __I  DMAC_CHSTATUS_Type        CHSTATUS;    /**< \brief Offset: 0x4F (R/   8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  __IO DMAC_BTCTRL_Type          BTCTRL;      /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
  __IO DMAC_BTCNT_Type           BTCNT;       /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
  __IO DMAC_SRCADDR_Type         SRCADDR;     /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
  __IO DMAC_DSTADDR_Type         DSTADDR;     /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
  __IO DMAC_DESCADDR_Type        DESCADDR;    /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
  __attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_DMAC_DESCRIPTOR

/*@}*/

#endif /* _SAMD10_DMAC_COMPONENT_ */


text:
Nine Down, Three to Go: Meyer Shank Racing Heads to VIR in IMSA Championship Hunt
Pataskala, Ohio (19 August 2019) – With just three races left in the IMSA WeatherTech SportsCar Championship season, Trent Hindman and Mario Farnbacher are looking froward to the next outing at Virginia International Raceway (VIR) for the Michelin GT Challenge (August 25th, 1:35pm ET NBCSN).
Entering the weekend with a 26-point lead in the IMSA championship, Hindman and Farnbacher have set their full focus on taking the No. 86 AutoNation Acura NSX GT3 to victory lane ahead of this weekend.
The team has an extensive history of competition at the track, with 17 VIR race outings dating back to 2004 in prototype competition. The Ohio-based team scored two podium finishes in 2009 and 2018 and are aiming to capture its first victory at the 3.27-mile track this weekend.
Farnbacher is coming into the VIR race weekend with two podium finishes in five years, one of which was in 2018 with MSR, co-driving with Katherine Legge.
"VIR is a cool track and since they added the new tarmac it is way more fun," said Farnbacher. "I also think that the Acura NSX Evo update will help a lot there in terms of the balance of the car. I know that the team had a good test at VIR a couple of weeks ago and I'm really looking forward to continuing our championship fight with just three races to go."
Hindman's record at VIR beams with success having competed in the IMSA Michelin Pilot Challenge, Lamborghini Super Trofeo and GT4 America series at the track – scoring four pole positions, three race victories and six podiums. But this weekend's race will be the first in IMSA WeatherTech competition for the young talent.
"There is quite a lot of confidence in what we have with the Acura NSX GT3 Evo heading to VIR," said Hindman. "Mario and Katherine (Legge) were able to bring the No. 86 Acura home on the podium at last year's event and obviously finding ourselves on the podium once again is our goal. We are in a good championship position thanks to the efforts of Mike (Shank), Mario and the entire MSR team and we have to be smart and do our best to protect that."
The Michelin GT Challenge weekend will start off with two practice sessions on Friday, Qualifying on Saturday and the two hour and 40-minute race set for Sunday, August 25th at 1:35pm ET on NBCSN.

redpajama_set_name: RedPajamaCommonCrawl


Nothing to do this summer? Why not try cooking or baking? Enroll at MOST Institute Cebu and let's be classmates.
MOST Institute is a provider to hotels and restaurants with culinary professionals with the right skills, disciplines, and attitudes in the workplace. It has successfully produced over 3,000 graduates for its 10 years of operation. MOST Institute Cebu is located at the 3rd Floor of Square One Building at 232 Lopez Jaena St., Tipolo, Mandaue City (at the corner of the road going to Singson Village) is their 4th branch.
Aside from the Culinary Arts and Baking Certificate Programs, MOST Institute Cebu also offers Fundamentals of Asian Culinary arts and my favorites —Kiddie Cooking Program, Japanese Sushi and Baking and Pastries lifestyle course. I'm seriously considering taking the Baking and Pastries.
Their grand launch on April 11, 2015 is attended by model-celebrities Daniel Matsunaga and Fabio Ide.
For further inquiries on tuition and class schedules you may call them at 09173111449.
Here are some information I found from their catalogue.


text:
Officials: 8-year-old girl killed in car crash in Lawrence
Local // Crime news
July 14, 2019 Updated: July 14, 2019 10:16 a.m.
LAWRENCE, Mass. (AP) — Officials say an 8-year-old girl was killed in a car crash in Lawrence.
The Essex District Attorney's Office says the two-car crash happened Saturday night and a Lawrence man was arrested in connection with the accident, 23-year-old Selvin Manuel Lima.
He faces charges of manslaughter, motor vehicle homicide by reckless operation, four counts of assault and battery with a dangerous weapon causing serious bodily injury and other violations. It's unclear whether he's represented by an attorney who could comment.
The district attorney's office says Lawrence Police tried to stop Lima for driving erratically and he fled, then struck a Honda Civic with five passengers including the 8-year-old girl. A 27-year-old man, 29-year-old woman and two children were taken to Boston hospitals with serious injuries.
Lima was also hospitalized with serious injuries.
Jonathan Feigen
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Shooting that left 2 men dead at different locations in Channelview believed...
Off-duty Harris County deputy opens fire on car break-in suspect


MotoRise® goes beyond the obvious conveniences of a motorized window shading system and delivers advantages in all the areas that matter the most. Scalable and adaptable, these systems are available with wired or fully wireless motor options to accommodate windows of all different sizes. The chain-free operation provides a simple, clean, and child-safe solution for any commercial or residential application.
MotoRise® is conveniently handmade right here in the U.S. This means virtually any variation in color, size, and accessory choice can be accommodated cost-effectively, enabling the architect to achieve a truly personalized look while adding no extra time to the project.
MotoRise® is available in four basic sizes with motors that come in various different power options and communication types, making it easy for the dealer and installer to find one perfect solution for virtually any window shading project. MotoRise® systems are the scalable solution for the specific needs of each and every job because these systems can be integrated easily with most building management and automation systems, or can be installed as a stand-alone solution utilizing various local controls and sensors.
A vast array of colors, sizes, accessory options, and fabrics allow for an endless combination of design choices, fitting any aesthetic or design approach. From timing functions to sensors that automatically adjust the shades throughout the day, to simple user-dependent local control, MotoRise® will provide superior performance in keeping light in or out and achieving energy savings through exceptional shading technology. Also, as one of the first products in the industry to be certified Best For Kids, tenants can rest easy knowing their children are safe with a MotoRise® system protecting their interior.
Systems with SoloMount brackets can be ordered with our lovely aluminum End Caps, which may be added to complete the enclosed look and are available in five colors to match your choice of fascia.
MotoRise systems that use SoloMount brackets may be ordered with Fascia, which is used to cover the shade hardware from view at the front or the rear of the shade. Fascia is available in five colors and can be added at any time, since it requires no tools to install. See individual shading system pages to learn more about the Fascia used within each.
All shades come standard with our Sealed Hembar (SSP) but you can customize your shade by choosing any of our available Hembar options for a truly unique solution every time.
MotoRise systems feature a steel pin idler which is spring loaded for ease of installation. Larger systems may feature Heavy Duty Idlers, which are made of metal and are secured to the tube using screws.
Fascia is available for both the front and rear of the shade, requiring no tools to install and can be added at any time.
Many systems are available with a Center Support option, allowing you to multi-band up to six shades and control them with one motor.
Many systems are available in regular roll or reverse roll, allowing you to choose which direction the fabric rolls off of the shade.
MotoRise systems require power to operate and, depending on the type of motor you have chosen, may have various options for getting power to the system. From battery-operated motors, to hardwired solutions, WT Shade has the right electrical option for every shade installation. See each shading system for available motors and power options.
Each MotoRise shading system will be customized with your choice of motor from the available options for each system. From 12V battery operated motors with a remote control, to hard-wired solutions connected directly to a switch, and digital motors with many advanced functions, WT Shade has the right motor solution for your installation.
Depending on the motor and communication type you have selected, you will have your choice of motor controls with which to operate your shades. See each shading system for available motors and controls.
MotoRise® Systems are available in 4 different sizes, allowing you to choose the right amount of strength necessary for your shade project.
MotoRise® Systems are also available with low profile Slim Brackets intended for tight space installations that do not require the use of Fascia, or Catch Brackets for added safety in extra-large or high up installations.
Motors are available with various communication types, such as Wired, Radio and Digital, allowing control over motors using remote controls, wall switches, or integration with 3rd party control systems. All controls sold separately.
Many MotoRise® hardware components are available in White and Black, and will be color coordinated to your selected fabric color.
WT Shade offers multiple options and accessories for you to customize your shades including various Hembar styles and add-on accessories like Side or Sill Channels.
MotoRise® is a companion to our HeliaRise line of manual shading systems, allowing you to combine both a manual and motorized solution across your project with a uniform look.
The MotoRise® automatic window shading system is an exclusive product of WT Shade. For more than 35 years, we have created exceptional shading solutions, engineered for hassle-free performance worldwide. This extensive sourcing and manufacturing experience is fully expressed in the creation of MotoRise®, our motorized window shading system line — adding beauty, appeal and comfort to any room and value to any property. Backed by the WT Shade Limited Lifetime Warranty, MotoRise® is simply sophisticated, and always the perfect fit.
Designed and engineered in the U.S.A..


Is a Kentucky boat dock builder, located in Leitchfield.
I am a volume dealer of docks. Volume does not mean quality lacks, it means I am able to put more into a dock without affecting the price. Materials are purchased at lower prices due to volume purchasing and savings are passed on to the customers.
I manufacture the dock hinges in house, utilizing heavy duty welded construction.
All docks are built to exceed the Corps. of Engineers specifications.
All docks require a permit from the Army Corps of Engineers.
Please refer to the Shoreline Management Plan for your lake.


text:
The first tenants have moved into WestLawn
September 2, 2022 •
Rendering of the new WestLawn building.
Photo provided by Flock and Rally.
Developer: Hughes Development Corporation
Contractor: Brasfield and Gorrie
Architect: Perkins and Will
The new WestLawn building — this city's first Cross-Laminated Timber (CLT) building — is the new home of Robinson Gray. The law firm is the first tenant of the retail + four-story office space in the heart of the BullStreet District.
The whole building is ~48,000 sqft, with ~34,000 of that space being office space. Robinson Gray has released several progress videos while awaiting its move into the new development.
Find more photos + updates about this project here.
Peak Drift Brewing Company's state-of-the-art facility
Ivy House is opening another location in Columbia, SC
Introducing Gills Creek Memorial Park coming to Columbia, SC


text:
Йездигерд Кроткий — возможно был провозглашён (шахиншахом) Сасанидской империи в 399/400 году. Йездигерд Кроткий («Нерм»), сын Бахрама IV, якобы царствовавший 72 дня.

Упоминается только мусульманским историком X века Хамзой аль-Исфахани. Возможно, Хамзе это потребовалось, для того чтобы закрыть лакуну в списке Сасанидских царей, объяснения которой он не находил, хотя наличие небольшого числа медных монет, отчеканенных штемпелями Шапура II, но с именем Йездигерда на оборотной стороне, дало основание предположить, что Йездигерд Кроткий действительно существовал.

Примечания

Ссылки

Литература

Персоналии по алфавиту
Умершие в 399 году
Сасаниды
Правители Азии IV века

redpajama_set_name: RedPajamaWikipedia


text:
Nephrotoma lamellata är en tvåvingeart. Nephrotoma lamellata ingår i släktet Nephrotoma och familjen storharkrankar.

Underarter

Arten delas in i följande underarter:

 N. l. lamellata
 N. l. sublamellata

Källor

Storharkrankar
lamellata


We are in the transportation business for one reason only: to provide a dependable and comprehensive logistics program for our customers.
We provide flexible services with our equipment, we carefully design delivery schedules, and we have prepositioned equipment with many vendors. These efficiencies keep our wheels turning and your costs down.
Primary transportation service area covers a 500-mile radius of Wapakoneta, Ohio.


text:
News Sports Packers Business Life Obituaries E-Edition Legals
Generosity makes our community better
Dave Graebner
For USA TODAY NETWORK-Wisconsin
Spring time always means change is on the way for United Way of Sheboygan County — one campaign is ending and another is about to begin.
And with that comes an opportunity to look back and recognize the great work that has been done.
I deeply admire the dedication of the many individuals, companies and organizations that made the year a success. We started the year hoping to raise $2.75 million and exceeded that goal by raising more than $2.9 million. I had the honor of working with the people who made this happen.
What does $2.9 million in United Way funds mean for Sheboygan County? It means an investment in our community's greatest areas of need — education, income and health.
You can expect to see continued development of specific community impact projects in these areas, as well as the ongoing support of United Way's funded Partner Agencies. With my personal interest in health care, I'm most excited about the new Sheboygan County Community Partnership for Children with United Way as the backbone agency, which includes a new Welcome Baby program.
Our health care partners will also be part of this effort to offer a healthier start to life for babies, giving parents and families the tools for a successful life path. Only good will come from that, as well as all of the other investments that will be made with this year's campaign dollars. Greater details on the impact of United Way over the past year will be released later this month. I look forward to seeing all that's in store for our community for next year.
But it doesn't end there. In Sheboygan County we often overlook the number of local businesses that prioritize community service and support the United Way. It is amazing to see the employees — from executives to entry-level support staff — passionately giving their time, talent and financial support. This year six companies joined together and created mascots to support United Way and create huge movements among their employees to raise awareness and dollars while having some fun.
For me, the most memorable experience of this campaign was the Day of Caring at the beginning of the campaign last September. I joined the Aurora team at Meals on Wheels and was struck by how well-managed this program is and was impressed by their eagerness to show us their operations. I saw firsthand that an event such as the Day of Caring is not just about projects completed or dollars raised — it truly changed how we, as volunteers, were personally impacted by the mission of this organization. Personally, I can tell you it triggered several families' ongoing involvement with Meals on Wheels.
My heartfelt appreciation goes to everyone who contributed — large or small — to the United Way this past year. I'm excited to see the impact of the $2.9 million over the next year in programs, services and organizations in action for the health of our community.
Although my time as campaign chair is ending, it only means that another is about to begin. The 2016-17 campaign will be led by the dynamic duo Karri Neils, of Sargento, and Todd Neils, of Bank First National. These two are energetic and ready to champion this effort. They have my full support and I hope yours as well.
The future is bright for the United Way of Sheboygan County as we continue supporting needs in our community. Thank you for being part of it.
Dave Graebner is the 2016 United Way of Sheboygan County campaign chair and president of Aurora Sheboygan Memorial Medical Center
© 2021 www.sheboyganpress.com. All rights reserved.


text:
Q: Starscream delegates not being called The variable is not nil, I have a good connection and the url is correct but no delegate methods are being called. Also I am implementing WebSocketDelegate
 let socket = WebSocket(url: NSURL(string: "UrlHere:port/")!)
            socket.delegate = self;
            socket.connect()
            if socket.isConnected {
                print("websocket is connected")
            }

    func websocketDidConnect(ws: WebSocket) {
        print("websocket is connected")
    }

    func websocketDidDisconnect(ws: WebSocket, error: NSError?) {
        if let e = error {
            print("websocket is disconnected: \(e.localizedDescription)")
        } else {
            print("websocket disconnected")
        }
    }

    func websocketDidReceiveMessage(ws: WebSocket, text: String) {
        print("Received text: \(text)")
    }

    func websocketDidReceiveData(ws: WebSocket, data: NSData) {
        print("Received data: \(data.length)")
    }

    func websocketDidReceivePong(socket: WebSocket) {
        print("Got pong!")
    }

A: Socket should be a property or variable of your class to make sure it sticks around.
If you allocate it just on a function stack it will fall out of scope and the delegates will never get called
Here is the code that I have used in my project just in case
import UIKit
//import WebSocket
import Starscream

class ViewController: UIViewController,WebSocketDelegate,WebSocketPongDelegate {

    @IBOutlet weak var wsURL: UITextField!

    @IBOutlet weak var wsConsole: UITextView!

    @IBOutlet weak var wsMessage: UITextField!

    var socket:WebSocket!

    override func viewDidLoad() {
        super.viewDidLoad()

//        var webSocketObj:WebSocket = WebSocket()
//        webSocketObj.ipAddressText = "10.12.1.101"
//        webSocketObj.portText = "8888"
//        webSocketObj.dataToSendText = "hi"
//        webSocketObj.dataRecievedTextView = ""
//        webSocketObj.connectedLabel = ""
//        webSocketObj.connectToServer()

        wsURL.text="ws://10.12.1.101:8888/"
        wsMessage.text="Hi"
        self.navigationItem.leftBarButtonItem?.title="Connect"
        self.navigationItem.rightBarButtonItem?.enabled=false
        // Do any additional setup after loading the view, typically from a nib.
    }

    func websocketDidConnect(socket: WebSocket){
     wsConsole.text = wsConsole.text .stringByAppendingString("\n websocket got connected")
         self.navigationItem.leftBarButtonItem?.title="Disconnect"
        self.navigationItem.rightBarButtonItem?.enabled=true
    }

    func websocketDidDisconnect(socket: WebSocket, error: NSError?){
    wsConsole.text = wsConsole.text .stringByAppendingString("\n websocket got disconnected")
     self.navigationItem.leftBarButtonItem?.title="Connect"
     self.navigationItem.rightBarButtonItem?.enabled=false
    }

    func websocketDidReceiveMessage(socket: WebSocket, text: String){
     wsConsole.text = wsConsole.text .stringByAppendingString("\n websocket got a message from server:").stringByAppendingString(text)
    }

    func websocketDidReceiveData(socket: WebSocket, data: NSData){
        print("websocket received data",data)
    }

    @IBAction func writeText(sender: UIBarButtonItem) {
        wsConsole.text = wsConsole.text .stringByAppendingString("\n Client sent a message:").stringByAppendingString(wsMessage.text!)
        socket.writeString(wsMessage.text!)
        self.view .endEditing(true)
    }

    @IBAction func disconnect(sender: UIBarButtonItem) {
         self.view .endEditing(true)
        if socket == nil{
            connect(sender)
        }
        else if socket.isConnected {
            socket.disconnect()
        } else {
            connect(sender)
        }
    }

    func connect(sender:UIBarButtonItem){
        socket = WebSocket(url: NSURL(string:wsURL.text!)!)
        socket.delegate = self
        socket.connect()
    }

    func websocketDidReceivePong(socket: WebSocket){
        wsConsole.text = wsConsole.text .stringByAppendingString("\n websocket received pong")
    }

    override func didReceiveMemoryWarning() {
        super.didReceiveMemoryWarning()
        // Dispose of any resources that can be recreated.
    }

}

Here is the link to storyboard just in case if you want

redpajama_set_name: RedPajamaStackExchange


text:
Institute of Opinion
University Guide
Eric's Pickle
01.26.2015 BY Stefan Rhys-Williams
Since the murders in Paris at the Charlie Hebdo offices and a kosher supermarket, thousands of soldiers have been deployed in France and the British secret services are braced for a similar incident in the UK. In this febrile climate, Eric Pickles recently composed a mild but timely missive – sent to all British mosques – praising the emphatic condemnation of terrorism issued by many Muslim leaders, but also urging vigilance. As figures of authority in British Islam, Pickles observed, the recipients of his letter are in a uniquely influential position and should be instrumental in extinguishing any radical strains of Islam that may be taking hold in their respective communities. He was careful to include caveats and riders: yes, the government has its role to play, too; extremism is not representative of Islam; even "British values are Muslim values".
But even this trepidatious message was greeted with indignation and condemned for causing further division. The Guardian published a glib reply by Areeb Ullah. Would Pickles, he ponders, also be sending open letters to British rabbis regarding the behaviour of Israeli settlers in the West Bank? And will he be contacting every Catholic institution about endemic child abuse?
Well, the government certainly makes it its business to investigate allegations of child abuse as Theresa May's (hapless, frustrated) inquiry attests. And to suggest that Israeli government policy is not criticised sufficiently harshly is strange, to say the least.
Again, we are invited to denounce crass generalisations. And yet, at this moment, radicalised young Muslims do pose a threat to the country's security: hundreds of Britons have travelled to the Middle East to fight with Isis and a major terrorist plot has recently been foiled in Belgium.
Pickles' main crime, it seems – and by extension David Cameron's, too – is suggesting that there exists any tension between Islam and wider British culture at all; even if Pickles continues by insisting he wants British Muslims to be proud of both their religious and national identities.
Unfortunately there are clashes between the values adumbrated by Pickles and some beliefs commonly held by British Muslims. For example, an ICM poll in 2006 suggested that forty percent of British Muslims favoured the introduction of sharia law into some parts of the country. More seriously, about twenty percent expressed sympathy for those responsible for the terrorist attacks in London of 2005. Some people may contest these polls and raise concerns about their methodology. But how else should we canvass public opinion?
I suspect that while most British Muslims consider the murder of cartoonists or journalists for offending their creed unconscionable, a substantial number may support draconian restrictions on freedom of expression in certain instances. That is their right. But to pretend that there is no conflict between the views of – I would submit – a considerable section of the British Muslim population, and some aspects of British law is disingenuous.
That need not be a fatal rift. Religious objections to what the state deems permissible are hardly unheard of. (Abortion rights in the USA are very contentious, and nobody would suggest that the Christian pro-life lobby is un-American). But these disputes and disagreements need to be aired, and in some instances – especially when Europe is still menaced by the threat of Islamist terrorism – governments are right to seek assurances that children are being shielded from the virus of extremism.
© 2020 Institute of Opinion.


Gemini has been performing since 1973 and are now playing music for their third—or is it fourth?—generation of young fans and families. From their home base in Ann Arbor, Michigan, San and Laz have performed to enthusiastic audiences at concert halls, festivals, community centers and elementary schools throughout the US and Canada. In 1997 Gemini added a new and very exciting facet to their music as they began performing with symphony orchestras, including the Detroit Symphony Orchestra and the Kansas City Symphony.
The twin brothers' retrospective compilation, "The Best of Gemini," received a 1999 Directors' Choice Award from Early Childhood News, as well as a Silver Honors Award from Parents' Choice Magazine. "Volume 2 of the Best of Gemini" includes their newest original songs, as well as traditional songs from all around the world.
In 2002 Gemini teamed up with an acclaimed chamber orchestra, the Phoenix Ensemble, to release "The OrchestraIs Here to Play!" This unique folk-classical collaboration — the perfect introduction to classical music for young listeners through songs they love—has won awards from Parents' Choice Magazine, as well as from the Children's Music Web.
Gemini's newest recording, released in April 2010, is "Once Upon A Time... The Storytelling Album," featuring folk tales from around the world, with musical elements added to each story. This CD also features "Perfect Pitch," a new story by San, which includes original orchestral music interspersed throughout.
Gemini has received ASCAP's "Popular Awards," a songwriting and recording award from the American Society of Composers, Authors, and Publishers, every year since 1995. A number of Gemini's songs were listed in the 1995 edition of Children's Jukebox, a subject guide to musical recordings used by librarians and teachers throughout the US. In 1997 Gemini's work was honored by a Silver Medallion Award from the Wolf Trap Institute for Early Learning Through the Arts.
Gemini's music is published by the Hal Leonard Publishing Corporation, the world's largest music publisher. Since 1994, Hal Leonard has published Gemini's first songbook and two musical revues for Elementary Schools based on Gemini's songs. These two revues, "Kids are Kids The Whole World Round," and "In Our Family," have been performed by children in schools throughout North America.
San and Laz have received songwriting grants from the Michigan Council for the Arts, and have written music for educational TV and films at Wayne State University. They have also arranged and recorded twelve albums of international ethnic folk dance music to accompany the book "Rhythmically Moving" by Phyllis Weikart, a leading authority on movement and dance. These recordings, published by the High/Scope Educational Research Foundation, are used internationally by early childhood educators to teach movement and dance to children.


We recorded five tracks in 2009 at our very first location in Greenpoint, Brooklyn and they were originally intended to be released as an EP. The recordings were eventually added to Skulk's increasing repertoire and the full length album known as How to Fail Properly was born. This album brought attention to Skulk from the likes of Pop Vulture and the Real Radio Show with Mark the Animal.


text:
Q: Steam Voice Chat Problem - Sound Bar Moving, No Sound I have a weird problem with voice chat in Steam that nobody else seems to have. I've read a lot of posts on Steam voice chat problems that start to sound like this one but end up being something else by the time I finish reading. So the problem is I'm not getting sound to come through in voice chat but I'm sure that Steam is receiving the sound because the bar is moving next the speaker icon but I just can't figure out where the sound is being sent to because I can't hear it in my speakers or headphones. All my friends can hear me too. The problem is on my end on my computer for sure, we've pinned it down. (I should also note I'm using a USB mic and normal headphones together, not a headset. This COULD be the problem but I can't figure out why it would be an issue.) I'm trying to look for settings in Steam on where to send the sound but it looks like there are just mic settings, nothing to help fix this problem.

A: Since you said nothing about it, first check Audio devices.
Right click you Volume icon (looks like Dynamic) in system tray -> Playback Devices
Here you will see what device is currently used by default. Steam obeys these settings.
If you have more than one active device, Headphones should be "Set as Default Communication Device".
Then right click on Headphones and "Test".