10 round Polymer magazines designed by MDT. Half the weight of their steel counterpart! Manufactured from high quality Polymer with a high glass content to ensure durability and strength. Uses a tempered steel spring. Put through vigorous testing, although not unbreakable, cars and trucks have been driven over them which did not break them. Available in .223 and .308 size.
Max over all length .308 = 2.800″ Compatible calibers in .308 size mag are .308, .22-250 & .243 (not recommended for .300 wsm, 10th round in .308 is tight and may cause mag to bulge slightly).
Please make your selection below to view current inventory.


Tune-in to 96five for plenty of chances to win tickets to the exclusive preview screening of the new Disney movie 'Christopher Robin' September 3-7!
Every hour there will be a chance to win your family tickets to this much awaited movie – all you need to do is tune in to 96five between 6am and 6pm for your chance to win! We have a whole cinema of family passes to giveaway including a couple on our Facebook page – so there are plenty of chances to make sure you're there on the day!
In addition to being one of the first to see the movie you'll also get to meet the 96five team including Duke the DJ Dog, get your photo taken like the celebrities in front of the movie poster and be in the running to win a lucky door prize.
In the heartwarming live action adventure "Disney's Christopher Robin", the young boy who loved embarking on adventures in the Hundred Acre Wood with a band of spirited and lovable stuffed animals, had grown up and lost his way. Now it is up to his childhood friends to venture into our world and help Christopher Robin remember the loving and playful boy who is still inside.
The preview screening will be held on Saturday, September 8 at Event Cinema's Garden City – we hope to see you there!
It's a DISNEY SING-ALONG and you can win FREE tickets!!!
Win a VIP experience to Disney on Ice!


Xiaomi presented a new graphic promoting the latest frameless Mi Mix 3, the graphics confirm a very large amount of RAM - more than many laptops.
The new poster presents the shape of the smartphone on the screen with a large wave, the gray place is a slider. At the bottom, there is a clear inscription "life is not difficult when there is 10 GB RAM, see you in 8 days". The only question is what the wave suggests, is Mi Mix 3 a hermetic? This is not known yet, but I would like it to be so. You will not have to worry about accidental flooding.
For the guide Xiaomi Mi Mix 3 will be presented 25 October in Beijing, I can not wait until it will be available for sale. I hope that I will be able to buy it before 11.11 - then there will be big promotions and thus a lot of orders and a lot of delays.


text:
package org.apache.asterix.active;

import java.util.HashMap;
import java.util.Map;
import java.util.concurrent.LinkedBlockingQueue;
import java.util.logging.Level;
import java.util.logging.Logger;

import org.apache.asterix.active.ActiveEvent.Kind;
import org.apache.hyracks.api.exceptions.HyracksDataException;
import org.apache.hyracks.api.job.JobId;
import org.apache.hyracks.api.job.JobSpecification;

public class ActiveJobNotificationHandler implements Runnable {
    public static final String ACTIVE_ENTITY_PROPERTY_NAME = "ActiveJob";
    private static final Logger LOGGER = Logger.getLogger(ActiveJobNotificationHandler.class.getName());
    private static final boolean DEBUG = false;
    private final LinkedBlockingQueue<ActiveEvent> eventInbox;
    private final Map<EntityId, IActiveEntityEventsListener> entityEventListeners;
    private final Map<JobId, EntityId> jobId2ActiveJobInfos;

    public ActiveJobNotificationHandler() {
        this.eventInbox = new LinkedBlockingQueue<>();
        this.jobId2ActiveJobInfos = new HashMap<>();
        this.entityEventListeners = new HashMap<>();
    }

    @Override
    public void run() {
        Thread.currentThread().setName(ActiveJobNotificationHandler.class.getSimpleName());
        LOGGER.log(Level.INFO, "Started " + ActiveJobNotificationHandler.class.getSimpleName());
        while (!Thread.interrupted()) {
            try {
                ActiveEvent event = getEventInbox().take();
                EntityId entityId = jobId2ActiveJobInfos.get(event.getJobId());
                if (entityId != null) {
                    IActiveEntityEventsListener listener = entityEventListeners.get(entityId);
                    LOGGER.log(Level.FINER, "Next event is of type " + event.getEventKind());
                    if (event.getEventKind() == Kind.JOB_FINISHED) {
                        LOGGER.log(Level.FINER, "Removing the job");
                        jobId2ActiveJobInfos.remove(event.getJobId());
                    }
                    if (listener != null) {
                        LOGGER.log(Level.FINER, "Notifying the listener");
                        listener.notify(event);
                    }

                } else {
                    LOGGER.log(Level.SEVERE, "Entity not found for received message for job " + event.getJobId());
                }
            } catch (InterruptedException e) {
                Thread.currentThread().interrupt();
            } catch (Exception e) {
                LOGGER.log(Level.SEVERE, "Error handling an active job event", e);
            }
        }
        LOGGER.log(Level.INFO, "Stopped " + ActiveJobNotificationHandler.class.getSimpleName());
    }

    public synchronized void removeListener(IActiveEntityEventsListener listener) throws HyracksDataException {
        LOGGER.log(Level.FINER, "Removing the listener since it is not active anymore");
        unregisterListener(listener);
    }

    public IActiveEntityEventsListener getActiveEntityListener(EntityId entityId) {
        if (DEBUG) {
            LOGGER.log(Level.WARNING, "getActiveEntityListener(EntityId entityId) was called with entity " + entityId);
            IActiveEntityEventsListener listener = entityEventListeners.get(entityId);
            LOGGER.log(Level.WARNING, "Listener found: " + listener);
        }
        return entityEventListeners.get(entityId);
    }

    public EntityId getEntity(JobId jobId) {
        return jobId2ActiveJobInfos.get(jobId);
    }

    public void notifyJobCreation(JobId jobId, JobSpecification jobSpecification) {
        LOGGER.log(Level.FINER,
                "notifyJobCreation(JobId jobId, JobSpecification jobSpecification) was called with jobId = " + jobId);
        Object property = jobSpecification.getProperty(ACTIVE_ENTITY_PROPERTY_NAME);
        if (property == null || !(property instanceof EntityId)) {
            LOGGER.log(Level.FINER, "Job was is not active. property found to be: " + property);
            return;
        }
        EntityId entityId = (EntityId) property;
        monitorJob(jobId, entityId);
        boolean found = jobId2ActiveJobInfos.get(jobId) != null;
        LOGGER.log(Level.FINER, "Job was found to be: " + (found ? "Active" : "Inactive"));
        IActiveEntityEventsListener listener = entityEventListeners.get(entityId);
        if (listener != null) {
            // It is okay to bypass the event inbox in this case because we know this is the first event for this entity
            listener.notify(new ActiveEvent(jobId, Kind.JOB_CREATED, entityId, jobSpecification));
        }
        LOGGER.log(Level.FINER, "Listener was notified" + jobId);
    }

    public LinkedBlockingQueue<ActiveEvent> getEventInbox() {
        return eventInbox;
    }

    public synchronized IActiveEntityEventsListener[] getEventListeners() {
        if (DEBUG) {
            LOGGER.log(Level.WARNING, "getEventListeners() was called");
            LOGGER.log(Level.WARNING, "returning " + entityEventListeners.size() + " Listeners");
        }
        return entityEventListeners.values().toArray(new IActiveEntityEventsListener[entityEventListeners.size()]);
    }

    public synchronized void registerListener(IActiveEntityEventsListener listener) throws HyracksDataException {
        if (DEBUG) {
            LOGGER.log(Level.FINER, "registerListener(IActiveEntityEventsListener listener) was called for the entity "
                    + listener.getEntityId());
        }
        if (entityEventListeners.containsKey(listener.getEntityId())) {
            throw new HyracksDataException(
                    "Active Entity Listener " + listener.getEntityId() + " is already registered");
        }
        entityEventListeners.put(listener.getEntityId(), listener);
    }

    public synchronized void unregisterListener(IActiveEntityEventsListener listener) throws HyracksDataException {
        LOGGER.log(Level.FINER, "unregisterListener(IActiveEntityEventsListener listener) was called for the entity "
                + listener.getEntityId());
        IActiveEntityEventsListener registeredListener = entityEventListeners.remove(listener.getEntityId());
        if (registeredListener == null) {
            throw new HyracksDataException(
                    "Active Entity Listener " + listener.getEntityId() + " hasn't been registered");
        }
    }

    public synchronized void monitorJob(JobId jobId, EntityId activeJob) {
        if (DEBUG) {
            LOGGER.log(Level.WARNING, "monitorJob(JobId jobId, ActiveJob activeJob) called with job id: " + jobId);
            boolean found = jobId2ActiveJobInfos.get(jobId) != null;
            LOGGER.log(Level.WARNING, "Job was found to be: " + (found ? "Active" : "Inactive"));
        }
        if (entityEventListeners.containsKey(activeJob)) {
            if (jobId2ActiveJobInfos.containsKey(jobId)) {
                LOGGER.severe("Job is already being monitored for job: " + jobId);
                return;
            }
            if (DEBUG) {
                LOGGER.log(Level.WARNING, "monitoring started for job id: " + jobId);
            }
        } else {
            LOGGER.severe("No listener was found for the entity: " + activeJob);
        }
        jobId2ActiveJobInfos.put(jobId, activeJob);
    }
}

redpajama_set_name: RedPajamaGithub


text:
Export 8951 results:
Audoin-Rouzeau, Stéphane. 1870: La France dans la guerre. Paris: Armand Colin, 1989.
Audoin-Rouzeau, Stéphane. "Public Opinion in 1870–71 and the Emergence of Total War." In On the Road to Total War: The American Civil War and the German Wars of Unification, 1861-1871, edited by Stig Förster and Jörg Nagler, 409-410. Cambridge: Cambridge University Press, 1997.
Audoin-Rouzeau, Stéphane. L'enfant de L'ennemi, 1914-1918: Viol, Avortement, Infanticide Pendant La Grande Guerre. Paris: Aubier, 1995.
Audoin-Rouzeau, Stéphane, and Annette Becker. 14–18: Understanding the Great War. New York: Hill and Wang, 2002.
Audoin-Rouzeau, Stéphane. Men at War, 1914-1918: National Sentiment and Trench Journalism in France during the First World War. Providence: Berg, 1992.
La Grande Guerre des musiciens, Edited by Stéphane Audoin-Rouzeau, Estebán Buch, Myriam Chimènes and Georgie Durosoir. Lyon: Symétrie, 2009.
Audoin-Rouzeau, Stéphane. L'enfant de l'ennemi, 1914-1918: viol, avortement, infanticide pendant la Grande Guerre (CXX). Paris: Aubier, 1995.
Auerbach, Jonathan, and Russ Castronovo. "Introduction: Thirteen Propositions about Propaganda." In The Oxford Handbook of Propaganda Studies, edited by Jonathan Auerbach and Russ Castronovo, 1-16. New York: Oxford University Press, 2013.
The Oxford Handbook of Propaganda Studies, Edited by Jonathan Auerbach and Russ Castronovo. Oxford ; New York: Oxford University Press, 2013.
Aufderheide, Patricia. Documentary Film: A Very Short Introduction. Oxford ; New York: Oxford University Press, 2007.
Gender in Conflicts: Palestine, Israel, Germany, Edited by Ulrike Auga and Christina von Braun. Münster, Germany: Lit, 2006.
Auger, Martin F. "Prisoners of the home front: A social study of the German internment camps of southern Quebec, 1940–1946." ProQuest Dissertations & Theses Global (2000): 1-226.
Augusta, Biblioteca Provincial, and Provincia Autonoma d Adige. Biblioteca Provinciale Italiana Claudia Augusta.
Aulich, James. War Posters: Weapons of Mass Communication. London ; New York: Thames & Hudson, 2007.
Auslander, Leora, Tara Zahra, and Alice Goff. Objects of War: The Material Culture of Conflict and Displacement. Ithaca: Cornell University Press, 2018.
Aussaresses, Paul. The Battle of the Casbah: Terrorism and Counter-Terrorism in Algeria, 1955–1957. New York: Enigma Books, 2002.
Autant-Lara, Claude. A Pig Across Paris. Four Bags Full., 1956.
Autant-Lara, Claude. Between Love and Duty., 1960.
Autant-Lara, Claude. Devil in the Flesh. France: Universal Film, 1947.
Avericheva, Sofʹi︠a︡. Dnevnik Razvedchit︠s︡y. Moskva: Voen. izd-vo, 1986.
Avrich, Karen, and Paul Avrich. Sasha and Emma: The Anarchist Odyssey of Alexander Berkman and Emma Goldman. Cambridge, MA: Harvard University Press, 2012.
Awad, Amal. Beyond veiled clichés. North Sydney, N.S.W: Penguin Random House Australia, 2017.
Axe, David, and Tim Hamilton. Army of God: Joseph Kony's War in Central Africa. New York: PublicAffairs, 2013.
Axelrod, Alan. Selling the Great War: The Making of American Propaganda. New York: Palgrave Macmillan, 2009.
Axtell, James. "The White Indians of Colonial America." William and Mary Quarterly 32, no. 1 (1975): 55-88.

redpajama_set_name: RedPajamaCommonCrawl


text:
é um especial japonês de 30 de Agosto de 2014 dirigido por Naoyuki Itô. É o quarto especial baseado da série One Piece de Eiichiro Oda. A sua trilha-sonora é interpretada pelo grupo AAA com a música intitulado de "Next Stage" canção "Sayonara no Mae Ni" da banda AAA.

Filmes de animação
Filmes do Japão de 2014

redpajama_set_name: RedPajamaWikipedia


text:
Q: Using jsoup for validation Is it possible to use jsoup to validate an HTML fragment? I want to know if the markup is malformed, and instead of having jsoup fix it automatically, I want to be able to inform the user to fix the source markup itself.

A: Jsoup is not the right parser for checking validity of xml or html, you can use JDom instead. Below is a sample code to check for welformedness of xml.
      SAXBuilder builder = new SAXBuilder();
      File xmlFile = new File("sample.xml");

        try {
            Document document = (Document) builder.build(xmlFile);
        } catch (IOException e) {
            // TODO Auto-generated catch block
            System.out.println(e.getMessage());
        }catch(JDOMException e){
              System.out.println(e.getMessage());
        }

You can download JDom2 here.

A: I guess Jsoup is not the proper library for this; its used for parsing / cleaning / working on html.

redpajama_set_name: RedPajamaStackExchange


Archbishop Malcolm has sent the following Easter message. On behalf of our priests and deacons may I wish you all a very happy and uplifting Easter.
Whether we recognise it or not our lives have been changed for ever by the Risen Lord at Easter. All too often we fail to see the good things of life when they are right in front of us, it may be the joy which other people can bring us, or it could be something we see in the beauty of the world around us, particularly as new life comes to us in spring time after the darkness of the winter months.
On the first Easter morning Mary of Magdala stayed outside the empty tomb weeping. She was grieving, mourning the death of Jesus. It was the end of everything that she had hoped for and believed in. Her Lord had been crucified and buried, now his body had been taken. As she wept a man came up to her and said, 'Woman, why are you weeping? Who are you looking for?' Mary didn't recognise the man and thought he was the gardener, she said, 'Sir, if you have taken him away, tell me where you have put him, and I will go and remove him.' Then the man looked at her and said, 'Mary' and at that point she recognised him as Jesus, the Risen Lord.
In that instant Mary's life changed, all she had hoped for came true, and in the most unexpected way. She didn't recognise Jesus, she even thought he was the gardener, and then she knew him. 'It was very early on the first day of the week and still dark, when Mary of Magdala came to the tomb', and with the dawn the darkness of her own life was transformed for ever. If we can hear the Risen Lord saying our name, our lives can be transformed too.
We live in difficult times. These last weeks and months have been filled with uncertainty and division. Political indecision and financial insecurity lead us to worry about the future for ourselves and for our families. We need the light to keep us going and give us hope. Real hope is based on the resurrection of Jesus, otherwise it is just optimism. The trouble with optimism is that it is just a desire for things to get better and is really only wishful thinking. Hope says that they will get better because Jesus has risen from the dead, and that hope is given to us too. So why not enjoy this season of Easter by looking for signs of new life and resurrection in the ordinary things we encounter every day. You will be surprised by what you see, your faith will be enriched, and it will be fun.


text:
Volleyball Home
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Mustangs Face CSUN, Long Beach State In Final Big West Road Matches
SAN LUIS OBISPO, Calif. — After picking up one of its biggest wins of the season last weekend with a sweep over rival UCSB to take sole possession of second place in the Big West, the Cal Poly volleyball team, who has four matches remaining in the regular season, will face its final Big West road trip of the season this weekend.
The Mustangs (17-7, 10-2 BW) will take on CSUN on Friday and Long Beach State on Saturday. Both matches start at 7 p.m. with Friday's match airing live on ESPN3/WatchESPN. Links to watch and follow live stats for both matches can be found above, on the schedule page, or via the GoPoly Front Row app.
Cal Poly had one of its best and most balanced offensive performances of the season on Saturday in the sweep over the Gauchos. Five different Mustangs collected at least six kills as Cal Poly hit .391 as a team. Junior outside hitter Maia Dvoracek notched her 14th consecutive match of double figure kills after she finished with a match-high 13 to go with eight digs and four service aces. Through 12 conference matches, she leads the Big West in kills in those matches with 5.12 per set. She also leads the conference in aces with 54, good for fifth most in the nation.
They also played stellar defense as a team. They out-blocked UCSB 6-1, held them to a season-low hitting percentage and held Lindsey Ruddins, the Big West leader in kills, to a season-low six kills.
The win moved Cal Poly in front of UCSB for second place in the Big West and just a match behind Hawai'i. The victory also increased the Mustangs' nation's-best home winning streak to 30 straight matches. That includes a 9-0 record at Mott this season.
The victory also propelled Cal Poly's RPI up eight spots to No. 33 to help buoy its case for an at large berth to the NCAA Tournament.
The Matadors (12-13, 7-6 BW) have won four straight matches entering Friday and are tied for fourth in the Big West. As a team, they rank third in the conference in blocks at 2.04 per set and are led by Seyvion Waggoner, who is sixth in the Big West in kills with 3.46 per set. The Mustangs swept CSUN at home on Oct. 29 for their ninth consecutive win over the Matadors. Cal Poly leads the all-time series 36-25.
The Beach (10-15, 7-6 BW) is coming off two sweeps last weekend over UC Irvine and Cal State Fullerton. They are currently tied for fourth in the Big West with CSUN. As a team, they rank second in the conference in kills and are led by sophomore outside hitter Kashauna Williams with 4.23 per set. On Sept. 24, the Mustangs swept Long Beach State in Mott for their fifth consecutive win over LBSU.
Cal Poly In the National Rankings: In the latest RPI release, Cal Poly moved up eight spots and is listed at No. 33. Elsewhere in the Big West, Hawai'i stayed at No. 11 while UC Santa Barbara dropped to No. 28.
Mustangs Among Big West and National Leaders: Through nine weeks of the season, the Mustangs have been one of the toughest teams from the service line. Junior outside hitter Maia Dvoracek is currently tied for fifth in the nation and leads the Big West in aces with 54. She is also fourth in the nation in aces per set with .61. As a team, Cal Poly is sixth in the nation and first in the Big West in aces per set at 1.88.
Currently, the Mustangs rank fourth in the Big West in blocks at 2.03 per set and third in opponent hitting percentage at .189. Including only conference matches, Cal Poly holds the top spot in opponent hitting percentage (.157), is second in hitting percentage (.264), assists (12.70), and kills (13.65).
Individually, Dvoracek is third in the conference in kills per set at 4.19. Sophomore setter Avalon DeNecochea is third in assists at 9.38 per set. Defensively, sophomore middle blocker Meredith Phillips ranks seventh in the Big West in blocks .93 per set with junior middle blocker Madilyn Mercer behind her in ninth at .90 per set. Senior libero Mika Dickson ranks fifth in the Big West in digs per set at 3.61.
Including conference matches only, Dvoracek leads in kills at 5.12 per set, DeNecochea leads in assists with 10.93, and Dickson is second in digs with 4.43
Cal Poly was amongst the leaders in multiple categories both in the Big West and nationally last season. The Mustangs ranked first in the Big West in hitting percentage (seventh in the nation) at .290, opponent hitting percentage (.177), kills per set (13.76), assists per set (12.88) and blocks per set (2.45).
Mighty Maia: Playing in her first year as a starter for Cal Poly, junior outside hitter Maia Dvoracek is averaging 4.19 kills per set overall and 5.12 kills per set during conference matches this season.
She also owns the top-two individual performances this season amongst Big West players for most kills in a single match. In a five-set win over then No. 16 Utah on Sept. 14, she had a career-high 30 kills. She nearly matched that in a four-set road loss to then No. 21 Hawai'i on Nov. 3 with 29 kills.
Cal Poly Picked To Three-Peat As Big West Champion: Coming off its second consecutive Big West championship in 2018, the Mustangs were selected to three-peat in 2019 after receiving five first-place votes and a total of 77 points.
Hawai'i, who finished second last season, was picked to finish second this season. They received four first-place votes and a total of 76 points. UC Santa Barbara (59 points), UC Irvine (52 points), and Long Beach State (46 points) rounded out the rest of the top five.
In the last two seasons, Cal Poly has gone 31-1 in conference matches. This would be the first Big West three-peat in program history. Overall, the Mustangs have won the Big West five times: 1984, 2006, 2007, 2017, 2018.
Tough Non-Conference Schedule: Cal Poly had 12 matches on its non-conference schedule this season. Seven of those matches were against teams who finished inside the RPI Top 50 and made the NCAA Tournament last season.
The Mustangs ended non-conference with a 7-5 record, including a win over then No. 16 Utah.
In total, the Mustangs played four matches against teams ranked inside the AVCA Top 25.
Home Sweet Home: The Mustangs have won 30 straight home matches at Mott Athletics Center. That is the longest streak in program history and longest active streak in Division I.
Cal Poly went undefeated at home last season (10-0) for the second straight year. In 2017, they went a perfect 8-0. The Mustangs' home winning streak began Nov. 11, 2016 and they last lost at home Oct. 28, 2016 to UC Santa Barbara.
Cal Poly has been dominate at home during this stretch. 11 of their last 13 wins at Mott have come via the sweep.
The Mustangs also had the second-highest average home attendance last season amongst Division I schools in California, trailing only Stanford.
Starting Strong: The Mustangs are undefeated this season when they have won the first set. In fact, 16 of Cal Poly's 17 wins this season have come when they won the opening set.
11 of the Mustangs' wins have come via sweep. Five have come in five-set victories and one in four sets.
Returning Power: Although the program lost two key all-conference players to graduation, the Mustangs return 14 players from last year's team — including five starters.
Reigning Big West Player of the Year and AVCA All-American opposite hitter Torrey Van Winden returns for her senior season. Last year, Van Winden was second in the Big West and third in the nation in kills per set (5.07) and led the conference in hitting percentage (.365). Her 5.07 kills per set was the second-highest single-season average in program history. In addition, she also owns the third-spot in that category for her 2017 average of 4.83.
Junior Madilyn Mercer returns following an All-Big West First Team sophomore season. Mercer led the conference in blocks last season at 1.12 blocks per set. She had a match last season at Hawai'i that saw her total 11 block assists, just two shy of tying a program record. She was also fourth on the team in kills and 10th in the Big West in hitting percentage (.289).
Sophomores Avalon DeNecochea and Meredith Phillips come back looking to continue with the success they had in their rookie campaigns. DeNecochea was named Big West Co-Freshman of the Year (the first Mustang since 2015), All-Conference Honorable Mention and All-Freshman Team after filling the void at the setter position previously held by Taylor Nelson and directing the Cal Poly offense to the best hitting percentage in the Big West and seventh-highest in the nation at .295. DeNecochea was second in the conference in assists per set at 10.32 and was fourth on the team in both blocks and digs.
Phillips, a middle blocker, was named to the Big West All-Freshman Team and All-Conference Honorable Mention after finishing third on the team in kills and second in blocks. She also had the fifth-highest hitting percentage in the Big West at .325.
New(ish) Head Coach: In December, Cal Poly hired Caroline Walters to become the new head volleyball coach. However, Walters is no stranger to Cal Poly. This is now her 11th year with the program, having been both an assistant coach/associate head coach since 2009.
This is also not her first experience as head coach. Three matches into the 2011 season, Walters was named interim head coach for the remainder of the season.
Mustangs On ESPN3: Cal Poly will play two road matches this season that will be aired on ESPN3. The first will be the match against UC Irvine on September 28 at 7 p.m. The other will be November 15 at 7 p.m. when the Mustangs travel to take on CSUN. Both matches can be streamed on ESPN3.com and WatchESPN.
Follow The Mustangs: Tickets are available at GoPoly.com, by calling (805) 756-4849 or by visiting the sidewalk window at the on-campus Performing Arts Center from 12 p.m. to 6 p.m. on weekdays and Saturday.
Upcoming home matches in Mott Athletics Center feature several events and fan giveaways:
Nov. 22 (Fri., 7 p.m.) • vs. UC Irvine
Faculty & Staff Appreciation Night: All Cal Poly instructors and staff receive free tickets.
Nov. 23 (Sat., 5 p.m.) • vs. Cal State Fullerton
Families are also encouraged to sign up for Mustang Kids Club ($10 per child/8th grade or under), as benefits include ongoing free admission to all regular-season soccer, volleyball, wrestling & women's basketball events along with select football, men's basketball and baseball games; plus invitations to exclusive events, birthday cards, and a T-Shirt.
Cal Poly students always get into games for free, and are also invited to join the Stang Gang. Stang Gang — Cal Poly's student fan group — features several rewards for a $10 one-time lifetime registration fee, including prizes from sponsors, a member T-Shirt, and more upon reaching point levels by checking in at games.


Located on the Valley of Malaya Alma Atinka River, the Medeu is a playground of winter sports. It is about fifteen kilometers south-east of central Almaty at an altitude of seventeen hundred meters. Medeu allows a scenic ride above the mountain tops and rivers. This outdoor speed skating wins the heart of the visitors and provides them an experience which they had never before. Medeu is much cooler than Almaty and is the highest skating rink in the world.
Shymbulak is a Ski resort which is located in the picturesque locale of Zailiuskiy Alwatau Mountains. The majestic view of the mountains with snowy slopes and the evergreen Tien Shan Firs will blow your mind. It consists of a four-star hotel, sleigh rentals, and snowboards. The place is popular for its snow and mild climate. Shymbulak has a Snowpark for the lovers of snowboarding.
Kok Tobe is the highest point in Almaty which allows a panoramic view of the city from all directions. The fastest roller coaster of Kazakhstan is located at this place, which goes down with the speed of forty-five kilometers per hour providing a picturesque view of the city. The Alleys of Lovers is the best place to enjoy a romantic walk with your partner. It has a semi-open summer caf' with serves the lavish duck, pork, and lamb with salads along with a beer mug. The Malaya Almtinka riverside path must be enjoyed by all walkers and joggers. The fountain of desires welcomes the guests. It is in the shape of a granite apple. Some visitors thoughtfully throw coins into the depths of this fountain while some click memorable snaps near it.
Located in the green Panfilov Park of Almaty, Ascension Cathedral is one of the most beautiful architectural monuments of the city. The cathedral is commonly known as ?Zenkov Cathedral?. The design is remarkably unique as it is built in wood connected with iron bolts. The outer view of the cathedral boats some bright walls and multi-colored domes. Visited by millions of tourists every year, this cathedral is one of the best destination spots of Almaty.
Ile-Alatau National Park is almost untouched by the advances of civilization. Located on the northern slopes of Zailiysky Alatau, this national park contains a wealth of different habitats including the woodlands, Alpine meadows, glaciers, and lakes. It exhibits more than three hundred species of animals and birds which includes Snow Leopard, Tian-Shan Brown Bear, Central-Asian Iynx, Mountain Goats, Stone Marten, Bluebirds and Golden Eagle. Ile-Alatau National Park opens twenty-hours in a day. But, foreigners need to take official permission to enter this national park.
Situated on the eastern side of the city, Almaty Zoo is the oldest zoo in Kazakhstan. It exhibits a wide range of flora and fauna including Deer, Wild Ram, Wolf, Golden Eagle, Leopards, Elephants, Zebras, Yaks, Horned Crows, Jaguars, Persian Leopards, Snakes, Crocodiles and many more. The zoo consists of more than six thousand animals in over three hundred and fifty species. The visiting time for Almaty Zoo is from 10:00 am to 7:00 pm.
This former capital of Kazakhstan consists of the most appealing Russian creations in Central Asia. Almaty surprises its tourists with an outlier of skyscrapers, museums, coffee shops and leafy parks. The city enhances its beauty with expensive sub-urban apartments, glitzy shopping malls, large SUVs, dance till dawn nightclubs, coffee lounges, western lifestyle and lavish restaurants. The new ski resort helps the global trotters to enjoy the trip to the fullest. Almaty showcases the most attractive sights which leave the tourists with their mouth opened.
You can book the tickets through this website at a discounted price. Advance booking of the tickets will save your time and money.
You can explore the city by several public transits like metros, taxis, trams, trolleys, and buses. Metro is the fastest means to travel at an affordable rate. It has been chosen by majority of the visitors. Moreover, Trams are easy to navigate. You can also explore the destinations by traveling in taxis, buses or hired vehicles. Avoid having self-driven vehicles as it is not safe to drive in Almaty. The city faces heavy traffic and thus, ground or on land vehicles are not effective to travel. You should prefer to have metros or local trains as it will save your time.
You can pack the dresses of your choice. There is no dress code in Almaty. But all you need is to dress modestly as it is an Arabic country. You can take denim, palazzos, bell bottoms and trousers along with casual button-downs and t-shirts. Avoid wearing bold and seeing through dresses. Cleavage should not be visible. Wear comfortable shoes or a flip-flop. Sunglasses are highly recommendable in the summer months. Do not forget to carry a scarf and sunscreen lotion. Jackets and warm clothes are a must if planning to travel in the winter months.
The best time to explore Almaty is from the months of June to September. These months have a moderate temperature which offers you pleasant sightseeing. The month of December is ideal for skating and skiing as the city has snowfall. Avoid planning your trip in April as it is the monsoon season.
Guide is not required as this website offers you detailed information about tours and attractions.
There are several modes to get into the city. You can reach by plane, train or car. Almaty International Airport is served by multiple airlines which include Air Astana, Ukrainian International Airlines, KLM, and Lufthansa. The airplane is the easiest and a convenient way to reach Almaty. The city consists of two railway stations, Almaty-1 and Almaty-2, which are well connected with the major cities of Kazakhstan.
While visiting the city of Almaty, you should be conscious while wearing your attire as it is an Arabic country. Head of the female genre must be covered, especially around the mosque area. Wearing short dresses and sleeveless is strictly prohibited. Avoid having eye-contacts. Drinking alcohol is illegal in public places. However, hotels and clubs allow having drinks. Do not show affection at public places. Driving in Almaty is not safe. Beware of scams, robbers, and pickpockets. Avoid visiting certain places at night as it is not safe. You are advised not to go out alone once the sun sets.


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Before making any decision, you should consider few factors such as your budget, floor longevity, the issue of installation and exactly how much time and effort you are prepared to spend on cleaning and maintenance. Keep in mind that one type might be easy to set up, but is hard to completely clean. Another might be durable but is more costly.
One of the key benefits associated with tiled floors is the simple maintenance. Tiles have been used for centuries to provide a durable coated surface that is hygienic and easy to completely clean. Not requiring any special cleaning alternatives, tiles are easiest to clean than most flooring options.
Choosing ceramic or porcelain tiles, no matter – they could be very easily restored if damaged. Continue to keep an additional container of tiles for future vehicle repairs because often there are variations between two batches. You can choose from a number of shades and designs, for indoors and outside. Timber look tiles especially are very popular as a patio floor coverings option. Tiles also offer the advantage of being waterproof, so if you have a dishwasher or washing machine leak, they could be easily cleaned without harm. Not everyone prefers this kind of flooring, for their harsh nature. They are considered as not suited to an appropriate living.
Timber floor options come in two types. Hardwood flooring is made as an individual piece of timber and the engineered wood consists of four to five layers of timber fused collectively.
Hardwood flooring surfaces can be sanded and refinished often over their life span. From one aspect, they are extremely durable and extremely easy to completely clean, from another part. Stable Tongue is one of the most expensive floors timber options. If you are buying luxurious feel – spend money on this kind of flooring and you will not repent it. Engineered timber offers all the benefits of natural timber flooring without the need for sanding and polishing. They can be perfect for below grade set up as it is much more protected to the effects of water than Hardwood. Very quickly installation is one of the primary factors that impact the decision for purchasing this kind of flooring.
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This entry was posted in Floor Design Ideas and tagged grandrich floor lamp, grandrich full spectrum floor lamp, grandrich tripod floor lamp. Bookmark the permalink.


text:
Justia Patents US Patent Application for SOLID STATE IMAGE SENSOR AND ELECTRONIC DEVICE Patent Application (Application #20190326338)
SOLID STATE IMAGE SENSOR AND ELECTRONIC DEVICE
Jul 3, 2019 - SONY SEMICONDUCTOR SOLUTIONS CORPORATION
The present disclosure relates to a solid-state imaging device and an electronic device that are configured to suppress the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation. An amplification transistor has an element separation region formed by ion implantation. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of a selection transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film. The present disclosure can be applied to, for example, a CMOS image sensor, etc.
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The present disclosure relates to a solid-state imaging device and an electronic device, and more particularly to a solid-state imaging device and an electronic device that are configured to be able to suppress the occurrence of noise and white blemishes in an amplification transistor having element separation regions which are formed by ion implantation.
When fine pixel size of a CMOS image sensor is obtained, there is a need to reduce the sizes of pixel transistors. However, if the sizes of the pixel transistors are reduced, then random noise (RN) gets worse.
In addition, when fine pixel size is obtained, in order to secure the areas of photodiodes (PDs), generally, element separation is formed by ion implantation. In this case, however, due to the formation of a gate electrode of a pixel transistor above element separation regions, white blemishes (white spots) increase.
Meanwhile, fora method for suppressing 1/f noise, there is devised a method for reducing the thickness of a gate oxide film of an amplification transistor (see, for example, Patent Document 1). However, if the thicknesses of gate oxide films above element separation regions are reduced, dark current gets worse, increasing white blemishes.
In addition, there is devised the formation of oxide films above element separation regions and above a part of an element region by a deposition method in order to block source/drain leakage caused by fixed charges in an enhancement type transistor when element separation is performed by a local oxidation of silicon (LOCOS) method (see, for example, Patent Document 2).
CITATION LIST Patent Document
Patent Document 1: Japanese Patent Application Laid-Open No. 2008-124395
Patent Document 2: Japanese Patent Application Laid-Open No. H02-144968
SUMMARY OF THE INVENTION Problems to be Solved by the Invention
However, suppression of the occurrence of noise and white blemishes in an amplification transistor having element separation regions which are formed by ion implantation is not considered.
The present disclosure is made in view of such circumstances, and is to enable to suppress the occurrence of noise and white blemishes in an amplification transistor having element separation regions which are formed by ion implantation.
Solutions to Problems
A solid-state imaging device of a first aspect of the present disclosure includes: an amplification transistor having an element separation region formed by ion implantation; and a transistor, wherein a channel region insulating film is configured to be thin compared to a gate insulating film of the transistor, and an element separation region insulating film is configured to be thick compared to the channel region insulating film, the channel region insulating film being at least a part of a gate insulating film above a channel region of the amplification transistor, and the element separation region insulating film being at least a part of a gate insulating film above the element separation region of the amplification transistor.
In the first aspect of the present disclosure, there are provided an amplification transistor having an element separation region which is formed by ion implantation; and a transistor. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of the transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film.
An electronic device of a second aspect of the present disclosure includes: an amplification transistor having an element separation region formed by ion implantation; and a transistor, wherein a channel region insulating film is configured to be thin compared to a gate insulating film of the transistor, and an element separation region insulating film is configured to be thick compared to the channel region insulating film, the channel region insulating film being at least a part of a gate insulating film above a channel region of the amplification transistor, and the element separation region insulating film being at least a part of a gate insulating film above the element separation region of the amplification transistor.
In the second aspect of the present disclosure, there are provided an amplification transistor having an element separation region which is formed by ion implantation; and a transistor. A channel region insulating film which is at least a part of a gate insulating film above a channel region of the amplification transistor is thin compared to a gate insulating film of the transistor, and an element separation region insulating film which is at least a part of a gate insulating film above the element separation region of the amplification transistor is thick compared to the channel region insulating film.
Effects of the Invention
According to the first and second aspects of the present disclosure, an image can be captured. In addition, according to one aspect of the present disclosure, the occurrence of noise and white blemishes in an amplification transistor having an element separation region which is formed by ion implantation can be suppressed.
Note that effects are not necessarily limited to the effects described here and may be any of the effects described in the present disclosure.
FIG. 1 is a block diagram showing an exemplary configuration of one embodiment of a CMOS image sensor to which the present disclosure is applied.
FIG. 2 is a top view showing a first exemplary configuration of 2×2 pixels.
FIG. 3 is an A-A′ cross-sectional view of FIG. 2.
FIG. 4 is a B-B′ cross-sectional view of FIG. 2.
FIG. 5 is a C-C′ cross-sectional view of FIG. 2.
FIG. 6 is a graph showing a relationship between the film thickness of a gate insulating film of an amplification transistor and random noise.
FIG. 7 is a graph showing a relationship between the width in a W direction of a channel region insulating film and white blemishes.
FIG. 8 is an A-A′ cross-sectional view of FIG. 2 showing another example of the film thicknesses of gate insulating films.
FIG. 9 is a C-C′ cross-sectional view of FIG. 2 showing another example of the film thickness of the gate insulating film.
FIG. 10 is an A-A′ cross-sectional view of FIG. 2 showing another example of the types of gate insulating films.
FIG. 11 is a B-B′ cross-sectional view of FIG. 2 showing another example of the type of the gate insulating film.
FIG. 12 is a C-C′ cross-sectional view of FIG. 2 showing another example of the type of the gate insulating film.
FIG. 13 is a B-B′ cross-sectional view of FIG. 2 showing another example of the width in the W direction of a channel region insulating film.
FIG. 14 is a B-B′ cross-sectional view showing another example of element separation regions.
FIG. 15 is a top view showing a second exemplary configuration of 2×4 pixels.
FIG. 16 is a top view showing a third exemplary configuration of 2×4 pixels.
FIG. 17 is a top view showing a fourth exemplary configuration of 4×4 pixels.
FIG. 18 is a top view showing a fifth exemplary configuration of 2×2 pixels.
FIG. 19 is a top view showing a sixth exemplary configuration of 2×2 pixels.
FIG. 20 is a top view showing a seventh exemplary configuration of 1×2 pixels.
FIG. 21 is an A-A′ cross-sectional view of FIG. 2 showing another example of a selection transistor.
FIG. 22 is a C-C′ cross-sectional view of FIG. 2 showing another example of the selection transistor.
FIG. 23 is a block diagram showing an exemplary configuration of an imaging apparatus serving as an electronic device to which the present disclosure is applied.
MODE FOR CARRYING OUT THE INVENTION
Premises of the present disclosure and modes for carrying out the present disclosure (hereinafter, referred to as embodiments) will be described below. Note that the description is made in the following order:
1. First embodiment: CMOS image sensor (FIGS. 1 to 22)
2. Second embodiment: imaging apparatus (FIG. 23)
First Embodiment Exemplary Configuration of One Embodiment of a CMOS Image Sensor
A CMOS image sensor 10 has a pixel region 11, pixel drive lines 14, vertical signal lines 15, a vertical drive unit 21, a column processing unit 22, a horizontal drive unit 23, a system control unit 24, a signal processing unit 31, and a memory unit 32 which are formed on a semiconductor substrate (chip) such as a silicon substrate which is not shown. The CMOS image sensor 10 captures an image of a subject and outputs pixel signals of respective pixels.
Specifically, pixels, each having a photoelectric conversion element that generates an amount of charge according to the amount of incident light and accumulates the charge therein, are two-dimensionally arranged in a matrix form in the pixel region 11, and the pixel region 11 performs imaging. In addition, in the pixel region 11, the pixel drive lines 14 are formed for the respective rows of the pixels in a matrix form, and the vertical signal lines 15 are formed for the respective columns.
The vertical drive unit 21 is composed of a shift register, an address decoder, etc., and drives the pixels in the pixel region 11 on a row-by-row basis, etc. One ends of the respective pixel drive lines 14 are connected to output terminals (not shown) of the vertical drive unit 21 which are provided for the respective rows. Though a depiction of a specific configuration of the vertical drive unit 21 is omitted, the vertical drive unit 21 is configured to have two scanning systems: a read-out scanning system and a sweep-out scanning system.
The read-out scanning system selects the rows in turn so as to read, in turn, pixel signals from the pixels on a row-by-row basis, and outputs a transfer pulse and a selection pulse from a corresponding output terminal connected to a pixel drive line 14 of the selected row.
The sweep-out scanning system outputs transfer pulses and reset pulses from the output terminals connected to the pixel drive lines 14 of the respective rows, earlier by the amount of time corresponding to shutter speed than scanning by the read-out system in order to sweep out (reset) unnecessary charges from the photoelectric conversion elements. By this scanning by the sweep-out scanning system, so-called electronic shutter operation is performed in turn on a row-by-row basis. Here, the electronic shutter operation refers to the operation of discarding charges in the photoelectric conversion elements and newly starting exposure (starting accumulation of charges).
Pixel signals outputted from pixels of the row selected by the read-out scanning system of the vertical drive unit 21 are supplied to the column processing unit 22 through the respective vertical signal lines 15.
The column processing unit 22 has signal processing circuits for the respective columns of the pixel region 11. The signal processing circuits of the column processing unit 22 perform signal processing, such as a noise removal process, e.g., a correlated double sampling (CDS) process, and an analog/digital (A/D) conversion process, on the pixel signals outputted through the vertical signal lines 15 from the pixels of the selected row. The column processing unit 22 temporarily holds the pixel signals having been subjected to the signal processing.
The horizontal drive unit 23 is composed of a shift register, an address decoder, etc., and selects, in turn, the signal processing circuits of the column processing unit 22. By this selection scanning by the horizontal drive unit 23, the pixel signals having been subjected to the signal processing by the signal processing circuits of the column processing unit 22 are outputted in turn to the signal processing unit 31.
The system control unit 24 is composed of, for example, a timing generator that generates various types of timing signals, and controls the vertical drive unit 21, the column processing unit 22, and the horizontal drive unit 23 on the basis of the various types of timing signals generated by the timing generator.
The signal processing unit 31 has at least an addition processing function. The signal processing unit 31 performs various signal processing, such as an addition process, on the pixel signals outputted from the column processing unit 22. At this time, the signal processing unit 31 stores, as necessary, in-progress results of the signal processing, etc., in the memory unit 32 and refers to the in-progress results, etc., at required timing. The signal processing unit 31 outputs the pixel signals having been subjected to the signal processing.
The memory unit 32 is composed of a dynamic random access memory (DRAM), a static random access memory (SRAM), etc.
First Exemplary Configuration of Pixels
FIG. 2 is a top view showing a first exemplary configuration of 2 (columns)×2 (rows) pixels arranged in the pixel region 11 of FIG. 1.
As shown in FIG. 2, for the 2×2 pixels, there are formed photodiodes (PDs) 61-1 to 61-4 serving as photoelectric conversion elements of the respective pixels; transfer transistors 62-1 to 62-4 of the respective pixels; and an FD 63 including floating diffusions (FDs) of the respective pixels. In addition, a selection transistor 66 and an amplification transistor 65 which are shared by the 2×2 pixels are formed above the PD 61-1 and the PD 61-2 in the drawing, and a reset transistor 64 which is shared by the 2×2 pixels is formed below the PD 61-3 and the PD 61-4 in the drawing.
Note that, in the following, when the PDs 61-1 to 61-4 do not need to be particularly distinguished from each other, they are collectively referred to as PDs 61. Likewise, the transfer transistors 62-1 to 62-4 are collectively referred to as transfer transistors 62.
Each PD 61 generates a charge according to the amount of received light and accumulates the charges. Each transfer transistor 62 reads the charge accumulated in a corresponding PD 61 when the transfer transistor 62 is turned on by a transfer pulse supplied from a corresponding pixel drive line 14 of FIG. 1, and transfers the charge to the FD 63.
The FD 63 holds the charge read from the PD 61. The reset transistor 64 is a depression type transistor. When the reset transistor 64 is turned on by a reset pulse supplied from a corresponding pixel drive line 14, the reset transistor 64 discharges the charge accumulated in the FD 63 to a constant voltage source, and thereby resets the potential of the FD 63.
The amplification transistor 65 is a depression type transistor, and is connected in series with the selection transistor 66. A gate electrode of the amplification transistor 65 is connected to the FD 63, and the amplification transistor 65 outputs a pixel signal according to the potential of the FD 63 to the selection transistor 66, using a power supply. The selection transistor 66 is a depression type transistor. When the selection transistor 66 is turned on by a selection pulse supplied from a corresponding pixel drive line 14, the selection transistor 66 supplies the pixel signal outputted from the amplification transistor 65, to the column processing unit 22 through a corresponding vertical signal line 15.
Note that in the example of FIG. 2 the reset transistor 64, the amplification transistor 65, and the selection transistor 66 are shared by the 2×2 pixels, but may be provided for each pixel.
FIG. 3 is an A-A′ cross-sectional view of FIG. 2, FIG.
4 is a B-B′ cross-sectional view of FIG. 2, and FIG. 5 is a C-C′ cross-sectional view of FIG. 2.
As shown in FIG. 3, a gate electrode 66A of the selection transistor 66 is formed on a semiconductor substrate 80 with a gate insulating film 81 interposed therebetween. In addition, a gate electrode 65A of the amplification transistor 65 is formed on the semiconductor substrate 80 with a gate insulating film 82 interposed therebetween. For the gate insulating film 81 and the gate insulating film 82, an oxide film, an oxynitride film, a high-k film, etc., can be adopted.
A channel region 83 of the selection transistor 66 is formed in a portion of the semiconductor substrate 80 below the gate electrode 66A, and a channel region 84 of the amplification transistor 65 is formed in a portion of the semiconductor substrate 80 below the gate electrode 65A.
In addition, source/drain regions 85 and 86 are formed in the semiconductor substrate 80 so as to sandwich the channel region 83, and function as source/drain regions of the selection transistor 66. In addition, a source/drain region 87 is formed in the semiconductor substrate 80 so as to sandwich the channel region 84 with the source/drain region 86. The source/drain region 86 and the source/drain region 87 function as source/drain regions of the amplification transistor 65.
As shown in FIG. 4, the amplification transistor 65 has element separation regions 91 and 92 which are formed by ion implantation. In addition, as shown in FIG. 5, the selection transistor 66 has element separation regions 93 and 94 which are formed by ion implantation.
As shown in FIG. 4, a film thickness H2 of a channel region insulating film 82A which is a central portion of the gate insulating film 82 above the channel region 84 is thin compared to a film thickness H1 of the gate insulating film 81 of the selection transistor 66. In addition, a film thickness H3 of element separation region insulating films 82B, each including a portion of the gate insulating film 82 above a boundary between the channel region 84 and the element separation region 91, 92 and the whole portion of the gate insulating film 82 above the element separation region 91, 92, is thick compared to the film thickness H2.
In addition, as shown in FIG. 4, a width L1 in a W direction (channel width direction) of the channel region insulating film 82A is narrow compared to a channel width L0 of the amplification transistor 65.
The element separation region insulating films 82B are formed by, for example, thermal oxidation. By this, the element separation region insulating films 82B become pure films with a low defect level density, reducing noise sources.
Note that although, in the example of FIGS. 2 to 5, the amplification transistor 65 and the selection transistor 66 share their source/drain region and the one source/drain region 86 is formed, instead of sharing, source/drain regions may be formed separately.
In addition, although in the above-described description, of pixel transistors other than the amplification transistor 65, only the selection transistor 66 is described, the transfer transistors 62 and the reset transistor 64 are also configured in a similar manner to the selection transistor 66.
Relationship Between the Film Thickness of a Gate Insulating Film and Random Noise
In FIG. 6, a horizontal axis represents the amount of random noise and a vertical axis represents the cumulative frequency of each amount of random noise. In addition, in FIG. 6, a dotted line represents the cumulative frequency of each amount of random noise for the amplification transistor 65, and a solid line represents the cumulative frequency of each amount of random noise for an amplification transistor having gate insulating films whose film thicknesses are all H3.
As shown in FIG. 6, in the amplification transistor 65 where the film thickness H2 of the channel region insulating film 82A is thin compared to the film thickness H3, random noise is reduced compared to the amplification transistor having gate insulating films whose film thicknesses are all H3.
In addition, though not shown, in the amplification transistor 65 where the film thickness H2 of the channel region insulating film 82A is thin compared to the film thickness H3, random telegraph noise (RTS) is also reduced compared to the amplification transistor having gate insulating films whose film thicknesses are all H3.
As described above, random noise and random telegraph noise can be reduced with a thinner film thickness of a gate insulating film of an amplification transistor.
Relationship Between the Width in the W Direction of the Channel Region Insulating Film and White Blemishes
FIG. 7 is a graph showing a relationship between the width in the W direction of the channel region insulating film and white blemishes.
In FIG. 7, a horizontal axis represents the width in the W direction of the channel region insulating film, and a vertical axis represents the total number of white blemishes occurred.
As shown in FIG. 7, the larger the width of the channel region insulating film, the higher the total number of white blemishes occurred. For example, when the film thickness of gate insulating films above the boundaries between the channel region 84 and the element separation regions 91 and 92 is the film thickness H2 which is thin compared to the film thickness H3, i.e., when the width of the channel region insulating film is wider than the channel width L0, a large amount of dark current is generated and accordingly many white blemishes occur.
As described above, random noise and random telegraph noise can be reduced with a thinner film thickness of the gate insulating film of the amplification transistor, but when the film thickness of the gate insulating films above the boundaries between the channel region 84 and the element separation regions 91 and 92 is thin, many white blemishes occur.
Therefore, in the CMOS image sensor 10, the film thickness H2 of the channel region insulating film 82A of the amplification transistor 65 is made thin compared to the film thickness H1 of the gate oxide film 81, and the film thickness H3 of the element separation region insulating films 82B is made thick compared to the film thickness H2 of the channel region insulating film 82A. By this, the occurrence of random noise and random telegraph noise and white blemishes in the amplification transistor 65 can be suppressed.
In addition, in the CMOS image sensor 10, since the element separation regions 91 to 94 are formed by ion implantation, fine pixels can be obtained.
Furthermore, in the CMOS image sensor 10, since only the gate insulating film 82 of the amplification transistor 65 is made thin, leakage can be suppressed.
Namely, a low voltage applied to the gate electrode 65A of the amplification transistor 65 is higher than low voltages applied to the gate electrodes of the transfer transistors 62, the reset transistor 64, and the selection transistor 66. For example, the low voltages for the selection transistor 66 and the reset transistor 64 are 0 V or less, but the low voltage for the amplification transistor is 0 V or more.
Then, when the low voltage applied to the gate electrode is low, leakage occurs at a gate edge on the drain side and thus noise gets worse. In addition, when the film thickness of the gate insulating film is thin, leakage is likely to occur at the gate edge on the drain side. In the CMOS image sensor 10, only the gate insulating film 82 of the amplification transistor 65 where leakage is less likely to occur is made thin, and the gate insulating films of the transfer transistors 62, the reset transistor 64, and the selection transistor 66 where leakage is likely to occur are not made thin. Therefore, the occurrence of leakage can be suppressed.
Furthermore, since the width L1 in the W direction of the channel region insulating film 82A is narrow compared to the channel width L0, even if misalignment of an etching mask occurs upon reduction of the thickness of the channel region insulating film 82A, the channel region insulating film 82A is not disposed above the element separation regions 91 and 92, and accordingly, the occurrence of white blemishes can be suppressed. Namely, a margin of dark current can be secured.
Another Example of the Film Thickness of a Gate Insulating Film
The element separation region insulating films and the gate insulating film of the selection transistor 66 may have the same thickness. In this case, an A-A′ cross-sectional view of FIG. 2 is as shown in FIG. 8, a B-B′ cross-sectional view of FIG. 2 is the same as in FIG. 4, and a C-C′ cross sectional view of FIG. 2 is as shown in FIG. 9. Namely, the film thickness of a gate insulating film 111 of the selection transistor 66 is the film thickness H3 of the element separation region insulating films 82B.
Another Example of the Type of a Gate Insulating Film
The element separation region insulating films and the gate insulating film of the selection transistor 66 may be of the same type. In this case, an A-A′ cross-sectional view of FIG. 2 is as shown in FIG. 10, a B-B′ cross-sectional view of FIG. 2 is as shown in FIG. 11, and a C-C′ cross sectional view of FIG. 2 is as shown in FIG. 12.
Namely, a gate insulating film 131 of the selection transistor 66 and element separation region insulating films 132B of the amplification transistor 65 are of the same type. The type of a channel region insulating film 132A of the amplification transistor 65 may be the same as or different from the type of the gate insulating film 131 and the element separation region insulating films 132B.
In addition, here, the gate insulating film 131 and the element separation region insulating films 132B have the same film thickness H3, but may have different film thicknesses. When the gate insulating film 131 and the element separation region insulating films 132B have the same film thickness, in a process of forming the gate insulating film 131, the element separation region insulating films 132B can also be formed, and thus, the number of manufacturing processes is reduced.
Another Example of the Width in the W Direction of a Channel Region Insulating Film
The width in the W direction of the channel region insulating film may be wide compared to the channel width L0 of the amplification transistor 65, and may be narrow compared to the width (gate width) in the W direction of the gate electrode 65A. In this case, a B-B′ cross-sectional view of FIG. 2 is as shown in FIG. 13.
Namely, a width L3 in the W direction of a channel region insulating film 141A is wide compared to the channel width L0 of the amplification transistor 65, and is narrow compared to a gate width L2 of the amplification transistor. That is, the channel region insulating film 141A includes the whole gate insulating film above the channel region 84 and a part of the gate insulating films above the element separation regions 91 and 92, and element separation region insulating films 141B include the other part of the gate insulating films above the element separation regions 91 and 92.
In this case, even if misalignment of an etching mask occurs upon reduction of the thickness of the channel region insulating film 141A, the film thickness of the gate insulating film above the channel region 84 is securely made thin, enabling to suppress the occurrence of random noise and random telegraph noise. Namely, a margin of random noise and random telegraph noise can be secured.
Note that in this case the film thickness H3 of the element separation region insulating films 141B may be the same as or different from the film thickness of the gate oxide film of the selection transistor 66. Note also that the element separation region insulating films 14 1B and the gate insulating film of the selection transistor 66 may be of the same type or of different types.
Another Example of Element Separation Regions
A part of the element separation regions may be formed of an insulating film. In this case, a B-B′ cross-sectional view of FIG. 2 is as shown in FIG. 14. Namely, a part of an element separation region 151 formed in the semiconductor substrate 80 is formed of an insulating film 151A, and a part of an element separation region 152 is formed of an insulating film 152A.
In this case, interfaces between the semiconductor substrate 80 and the insulating films 151A and 152A become noise sources. However, since the element separation region insulating films 82B on the insulating films 151A and 152A are thick, a high electric field is prevented from being applied to the interfaces between the semiconductor substrate 80 and the insulating films 151A and 152A, and thus, noise is reduced.
Second Exemplary Configuration of Pixels
FIG. 15 is a top view showing a second exemplary configuration of 2 (columns)×4 (rows) pixels arranged in the pixel region 11 of FIG. 1.
The configuration of FIG. 15 differs from the configuration of FIG. 2 mainly in that a reset transistor 64, an amplification transistor 65, and a selection transistor 66 are shared by the 2 (columns)×4 (rows) pixels.
Specifically, for the 2 (columns)×4 (rows) pixels of FIG. 15, there are formed two PD groups 171-1 and 171-2, each including PDs 61, transfer transistors 62, and an FD 63 for the 2 (columns)×2 (rows) pixels which are described in FIG. 2. In addition, the selection transistor 66 and the amplification transistor 65 which are shared by the 2 (columns)×4 (rows) pixels are formed between the PD group 171-1 and the PD group 171-2. Furthermore, the reset transistor 64 is formed below the PD group 171-2 in the drawing.
Note that another reset transistor for the 2 (columns)×4 (rows) pixels or a dummy transistor may be disposed on the left side in the drawing of the reset transistor 64.
An A-A′ cross-sectional view of FIG. 15 is the same as the A-A′ cross-sectional view of FIG. 3, a B-B′ cross-sectional view of FIG. 15 is the same as the B-B′ cross-sectional view of FIG. 4, and a C-C′ cross-sectional view of FIG. 15 is the same as the C-C′ cross-sectional view of FIG. 5, and thus, description thereof is omitted.
Third Exemplary Configuration of Pixels
FIG. 16 is a top view showing a third exemplary configuration of 2 (columns)×4 (rows) pixels arranged in the pixel region 11 of FIG. 1.
The configuration of FIG. 16 differs from the configuration of FIG. 15 in that a reset transistor 64, an amplification transistor 65, and a selection transistor 66 are located in a column direction (longitudinal direction), and that a dummy transistor 191 is newly provided.
Specifically, the reset transistor 64, the amplification transistor 65, and the selection transistor 66 are disposed, for example, on the left side in the drawing of PD groups 171-1 and 171-2. In addition, the amplification transistor 65 and the dummy transistor 191 share their source/drain region.
Note that instead of the dummy transistor 191, another reset transistor for the 2 (columns)×4 (rows) pixels may be disposed. Note also that the dummy transistor 191 may not be provided.
Fourth Exemplary Configuration of Pixels
FIG. 17 is a top view showing a fourth exemplary configuration of 4 (columns)×4 (rows) pixels arranged in the pixel region 11 of FIG. 1.
The configuration of FIG. 17 differs from the configuration of FIG. 15 in that a dummy transistor 201 is provided adjacent in a row direction (lateral direction) to a reset transistor 64, and that amplification transistors 65 share their source/drain region and the dummy transistors 201 share their source/drain region between 2 (columns)×4 (rows) pixels and 2 (columns)×4 (rows) pixels which are adjacent to each other in a horizontal direction.
Specifically, in 2 (columns)×4 (rows) pixels 211-1 of FIG. 17, a selection transistor 66 and the amplification transistor 65 are disposed in this order from the left in the drawing; on the other hand, in 2 (columns)×4 (rows) pixels 211-2 adjacent on the right in the drawing to the 2 (columns)×4 (rows) pixels 211-1, the amplification transistor 65 and a selection transistor 66 are disposed in this order from the left in the drawing. Then, the amplification transistors 65 share their source/drain region between the 2 (columns)×4 (rows) pixels 211-1 and 211-2.
In addition, in the 2 (columns)×4 (rows) pixels 211-1 of FIG. 17, the reset transistor 64 and the dummy transistor 201 are disposed in this order from the left in the drawing; on the other hand, in the 2 (columns)×4 (rows) pixels 211-2, the dummy transistor 201 and the reset transistor 64 are disposed in this order from the left in the drawing. Then, the dummy transistors 201 share their source/drain region between the 2 (columns)×4 (rows) pixels 211-1 and 211-2.
Note that instead of the dummy transistors 201, another reset transistor for the 2 (columns)×4 (rows) pixels may be disposed, or nothing may be disposed. When nothing is disposed instead of the dummy transistors 201, the reset transistors 64 share their source/drain region between the 2 (columns)×4 (rows) pixels 211-1 and 211-2.
Fifth Exemplary Configuration of Pixels
FIG. 18 is a top view showing a fifth exemplary configuration of 2 (columns)×2 (rows) pixels arranged in the pixel region 11 of FIG. 1.
The configuration of FIG. 18 differs from the configuration of FIG. 2 in that an amplification transistor 65 and a reset transistor 64 share their source/drain region.
Specifically, for the 2 (columns)×2 (rows) pixels of FIG. 18, a selection transistor 66, the amplification transistor 65, and the reset transistor 64 are disposed in this order from the left in the drawing below PDs 61-3 and 61-4 in the drawing.
Sixth Exemplary Configuration of Pixels
FIG. 19 is a top view showing a sixth exemplary configuration of 2 (columns)×2 (rows) pixels arranged in the pixel region 11 of FIG. 1.
The configuration of FIG. 19 differs from the configuration of FIG. 18 in that a reset transistor 64 is disposed relatively close to an FD 63.
Specifically, for the 2 (columns)×2 (rows) pixels of FIG. 19, a selection transistor 66, an amplification transistor 65, and the reset transistor 64 are disposed in this order from the left in the drawing between a PD 61-1 and a PD 61-3.
Seventh Exemplary Configuration of Pixels
FIG. 20 is a top view showing a seventh exemplary configuration of 1 (column)×2 (rows) pixels arranged in the pixel region 11 of FIG. 1.
The configuration of FIG. 20 differs from the configuration of FIG. 2 mainly in that a reset transistor 64, an amplification transistor 65, and a selection transistor 66 are shared by the 1 (column)×2 (rows) pixels.
Specifically, for the 1 (column)×2 (rows) pixels of FIG. 20, the selection transistor 66 and the amplification transistor 65 are disposed in this order from the left in the drawing below a PD 61-2 in the drawing. In addition, the reset transistor 64 is disposed between a PD 61-1 and the PD 61-2.
Another Example of a Selection Transistor
FIG. 21 is an A-A′ cross-sectional view of FIG. 2 showing another example of a selection transistor, and FIG. 22 is a C-C′ cross-sectional view of FIG. 2 showing another example of the selection transistor.
Note that in FIGS. 21 and 22, the same portions as those in FIGS. 3 and 5 are denoted by the same reference signs, and description thereof is omitted as appropriate, as the description is repetitive.
In FIGS. 21 and 22, a gate insulating film 231 of the selection transistor 66 is configured in a similar manner to the gate insulating film 82 of the amplification transistor 65.
Specifically, instead of the gate insulating film 81, the gate insulating film 231 is formed below the gate electrode 66A of the selection transistor 66 on the semiconductor substrate 80. The film thickness H2 of a channel region insulating film 231A which is a central portion of the gate insulating film 231 above the channel region 83 is thin compared to the film thickness H1 of the gate insulating films of pixel transistors other than the amplification transistor 65 and the selection transistor 66 (the transfer transistors 62 and the reset transistor 64). In addition, the film thickness H3 of element separation region insulating films 231B, each including a portion of the gate insulating film 231 above a boundary between the channel region 83 and the element separation region 93, 94 and the whole portion of the gate insulating film 231 above the element separation region 93, 94, is thick compared to the film thickness H2. By this, the drive capability of the selection transistor 66 can be improved.
Note that it is also possible that the gate insulating films of two or more transistors selected from among the transfer transistors 62, the reset transistor 64, and the selection transistor 66 which are pixel transistors other than the amplification transistor 65, only the gate insulating films of the transfer transistors 62, and only the gate insulating film of the reset transistor 64 are configured in a similar manner to the gate insulating film 82. Namely, it is possible that the gate insulating films of some transistors selected from among the transfer transistors 62, the reset transistor 64, and the selection transistor 66 are configured in a similar manner to the gate insulating film 81, and the gate insulating films of other transistors are configured in a similar manner to the gate insulating film 82.
When only the gate insulating film of the reset transistor 64 is configured in a similar manner to the gate insulating film 82, the drive capability of the reset transistor 64 improves. In addition, when the gate insulating films of both the selection transistor 66 and the reset transistor 64 are configured in a similar manner to the gate insulating film 82, the drive capability of the selection transistor 66 and the reset transistor 64 improves.
In addition, when the gate insulating films of both the transfer transistors 62 and the reset transistor 64 are configured in a similar manner to the gate insulating film 82, the potential of the PDs 61 is easily modulated upon transfer operation and thus charge transfer can be easily performed.
Likewise, it is also possible that the gate insulating films of some transistors selected from among the transfer transistors 62, the reset transistor 64, and the selection transistor 66 are configured in a similar manner to the gate insulating film 82 (132 and 141), and the gate insulating films of other transistors are configured in a similar manner to the gate insulating film 111 (131 and 81).
Second Embodiment Exemplary Configuration of One Embodiment of an Imaging Apparatus
An imaging apparatus 1000 of FIG. 23 is a video camera, a digital still camera, or the like. The imaging apparatus 1000 includes a lens group 1001, a solid-state imaging device 1002, a DSP circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operating unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operating unit 1007, and the power supply unit 1008 are connected to each other through a bus line 1009.
The lens group 1001 captures incident light (image light) from a subject and forms an image on an imaging plane of the solid-state imaging device 1002. The solid-state imaging device 1002 is composed of the above-described CMOS image sensor 10. The solid-state imaging device 1002 converts the amount of the incident light which is formed into an image on the imaging plane by the lens group 1001, into an electrical signal on a pixel-by-pixel basis and supplies the electrical signal as a pixel signal to the DSP circuit 1003.
The DSP circuit 1003 performs predetermined image processing on the pixel signals supplied from the solid-state imaging device 1002, and supplies an image signal having been subjected to the image processing to the frame memory 1004 on a frame-by-frame basis, and the image signal is temporarily stored in the frame memory 1004.
The display unit 1005 is composed of, for example, a panel type display apparatus such as a liquid crystal panel or an organic electro luminescence (EL) panel, and displays an image on the basis of the frame-by-frame pixel signals which are temporarily stored in the frame memory 1004.
The recording unit 1006 is composed of a digital versatile disk (DVD), a flash memory, or the like, and reads and records the frame-by-frame pixel signals which are temporarily stored in the frame memory 1004.
The operating unit 1007 issues operational instructions regarding various functions provided to the imaging apparatus 1000, under operations performed by a user. The power supply unit 1008 supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operating unit 1007, as appropriate.
Electronic devices to which the present technology is applied may be any apparatus that uses a CMOS image sensor as an image capturing unit (photoelectric conversion unit), and include, for example, a portable terminal apparatus having an imaging function and a copier that uses a CMOS image sensor as an image reading unit, in addition to the imaging apparatus 1000.
Note that the effects described in the present specification are merely exemplification and thus are not limited, and there may be other effects.
In addition, embodiments of the present disclosure are not limited to the above-described embodiments, and various changes may be made without departing from the true spirit of the present disclosure.
For example, when the structure of the pixels in the pixel region 11 is any of the structures of FIGS. 15 to 20, too, as shown in FIGS. 8 and 9, the element separation region insulating films and the gate insulating film of the selection transistor 66 may have the same thickness. In addition, as shown in FIGS. 10 to 12, the element separation region insulating films and the gate insulating film of the selection transistor 66 may be of the same type.
In addition, as shown in FIG. 13, the width in the W direction of the channel region insulating film may be wide compared to the channel width LO of the amplification transistor 65, and may be narrow compared to the width (gate width) in the W direction of the gate electrode 65A. In addition, as shown in FIG. 14, a part of the element separation regions may be formed of an insulating film.
Note that the present disclosure can also employ the following configurations.
A solid-state imaging device including:
an amplification transistor having an element separation region formed by ion implantation; and
a transistor,
wherein a channel region insulating film is configured to be thin compared to a gate insulating film of the transistor, and an element separation region insulating film is configured to be thick compared to the channel region insulating film, the channel region insulating film being at least a part of a gate insulating film above a channel region of the amplification transistor, and the element separation region insulating film being at least a part of a gate insulating film above the element separation region of the amplification transistor.
The solid-state imaging device according to (1), wherein the element separation region insulating film and the gate insulating film of the transistor are configured to have a same film thickness.
The solid-state imaging device according to (1) or (2), wherein the element separation region insulating film and the gate insulating film of the transistor are configured to be of a same type.
The solid-state imaging device according to any of (1) to (3), wherein a width in a W direction of the channel region insulating film is configured to be narrow compared to a channel width of the amplification transistor.
The solid-state imaging device according to any of (1) to (3), wherein a width in a W direction of the channel region insulating film is configured to be wide compared to a channel width of the amplification transistor, and to be narrow compared to a gate width of the amplification transistor.
The solid-state imaging device according to any of (1) to (5), wherein a part of the element separation region is configured to be formed of an insulating film.
The solid-state imaging device according to any of (1) to (6), wherein the element separation region insulating film is configured to be formed by thermal oxidation. (8)
The solid-state imaging device according to any of (1) to (7), wherein the amplification transistor is configured to be a depression type transistor.
The solid-state imaging device according to any of (1) to (8), further including a transistor other than the transistor that is selected from among a selection transistor, a reset transistor, and a transfer transistor, each of the selection transistor, the reset transistor, and the transfer transistor having an element separation region formed by ion implantation,
wherein a channel region insulating film of the transistor other than the transistor is configured to be thin compared to the gate insulating film of the transistor, and an element separation region insulating film is configured to be thick compared to the channel region insulating film.
An electronic device including:
65 Amplification transistor
62-1 to 62-4 Transfer transistor
64 Reset transistor
66 Selection transistor
81 Gate insulating film
82A Channel region insulating film
82B Element separation region insulating film
84 Channel region
91 to 94 Element separation region
151A and 151B Insulating film
231A Channel region insulating film
231B Element separation region insulating film
1. A solid-state imaging device comprising:
2. The solid-state imaging device according to claim 1, wherein the element separation region insulating film and the gate insulating film of the transistor are configured to have a same film thickness.
3. The solid-state imaging device according to claim 1, wherein the element separation region insulating film and the gate insulating film of the transistor are configured to be of a same type.
4. The solid-state imaging device according to claim 1, wherein a width in a W direction of the channel region insulating film is configured to be narrow compared to a channel width of the amplification transistor.
5. The solid-state imaging device according to claim 1, wherein a width in a W direction of the channel region insulating film is configured to be wide compared to a channel width of the amplification transistor, and to be narrow compared to a gate width of the amplification transistor.
6. The solid-state imaging device according to claim 1, wherein a part of the element separation region is configured to be formed of an insulating film.
7. The solid-state imaging device according to claim 1, wherein the element separation region insulating film is configured to be formed by thermal oxidation.
8. The solid-state imaging device according to claim 1, wherein the amplification transistor is configured to be a depression type transistor.
9. The solid-state imaging device according to claim 1, further comprising a transistor other than the transistor that is selected from among a selection transistor, a reset transistor, and a transfer transistor, each of the selection transistor, the reset transistor, and the transfer transistor having an element separation region formed by ion implantation,
Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION (Kanagawa)
Inventors: Yusuke OTAKE (Kanagawa), Toshifumi WAKANO (Kanagawa), Takuya SANO (Tokyo), Yusuke TANAKA (Kanagawa), Keiji TATANI (Kanagawa), Hideo HARIFUCHI (Yamagata), Eiichi TAUCHI (Yamagata), Hiroki IWASHITA (Nagasaki), Akira MATSUMOTO (Nagasaki)
International Classification: H01L 27/146 (20060101); H01L 29/10 (20060101); H01L 29/423 (20060101);


text:
Cicirelli Fake "Walk-about" Plays Out On Facebook
by W.J. Elvin III
Filed under: Literary Hoaxes, Practical Jokes and Mischief
Crazy Facebook Hoax starts with unemployment, ends stranded in mexico
by Cody Permenter
The Daily Dot
Dave Cicirelli, an art director from New York City, posted on his Facebook profile in late 2009 that his life was at a standstill and something desperately needed to change. He announced his decision to quit his job and hitchhike across country, taking his laptop and cellphone to document his journey. Along the way, he fell in love with an Amish woman, joined a doomsday cult, got stranded in Mexico, and got inked up with a bowtie tattoo.
Sounds like a pretty crazy adventure, right?
As with most things that sound too good to be true are, Cicirelli"™s story was completely fake""an elaborate scheme played out on Facebook with the help of Photoshop. In his new book Fakebook , Cicirelli tells the story of his six-month hoax that fooled more people than he ever thought it could.
At the time of his experiment, Facebook had been going through a major shift. Social games like Farmville began overloading users with requests, and more business pages were pushing content to users"™ newsfeeds""changes that contributed to the loss of Facebook"™s personal touch. Friends started to feel like they were competing for attention.
"It occurred to me that I don"™t know if any [on Facebook] is true," Cicirelli told the Daily Dot. "It is kind of run on the honor system."
Naturally inclined to cause mischief, Cicirelli, now 30, set out with the simple challenge of seeing how ridiculous he could be on Facebook while still fooling his friends. His first stop: Amish Country.
Posting about two or three times a day, Cicirelli said that manipulating photographs proved challenging because of the unpredictability of the weather and normal day-to-day time constraints. Despite his humorously shoddy Photoshop work, he said people were buying into the story.
"People just wanted it to be true," he said. "I really believe that."
As his online journey continued, the story got stranger, and people became more invested in Cicirelli"™s life. He added over 100 new followers to his original 500, and comments on his page ranged from encouragement to concern for his well-being. He said that he felt pressure to post regularly because followers became worried if he missed a day.
And his story just got weird.
Cicirelli had began doing what now is commonly known as "catfishing," a term derived from the 2010 documentary Catfish , where filmmaker Nev Schulman was fooled in an online relationship with someone who he thought was a beautiful, young musician from Michigan. His online crush turned out to be a middle-aged woman who ran multiple fake Facebook profiles with a cast of her own made-up characters.
The popularity of the film has since paved the way for a reality TV show by the same name, where Schulman helps others through their own catfishing nightmares.
Although he fooled many of his Facebook friends and others who began following his story, his experiment wasn"™t without hiccups. Cicirelli said avoiding his Facebook friends in real life was a challenge, especially on holidays when he would head back to his hometown. He recalled a time when at home for Thanksgiving he was at home with his mom watching Jeopardy in his parents basement while only a couple blocks away, believers of his online fantasy were celebrating at a local bar.
One person found out about Cicirelli"™s prank and instead of outright exposing him, the mystery follower began sending creepy messages and real-world trinkets""like a bouquet of flowers from his pretend Amish girlfriend.
What stood out to Cicirelli the most from his journey was the outpouring from other Facebook friends who shared similar feelings of wanting to leave their real-world job behind and travel the country. He said dozens of people, many of whom he had never met, would send him messages about their own plans for escaping the drag of the 9-to-5 world. And one woman actually did follow in his footsteps, or so she thought.
Cicirelli said that he received a message from a woman who was so inspired by his tale, she quit her job and moved from New York City to Portland, Ore., on a whim.
"That was the worst day of my life""finding out that some woman was basing her life decision on a practical joke," he said.
In the end, Cicirelli decided to end his fraudulent journey six months after it began. His virtual self had gone through a lot, but Cicirelli had proven what he set out to see. How much would people believe of an insane, unbelievable tale if it was posted on Facebook?
A lot. A whole heck of a lot.
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