Let's imagine four couples with varying incomes, each of whom purchased a hundred shares of XYZ company stock for $10,000 in early 2009 and sold their shares this year for $30,000—realizing $20,000 of capital gain. What federal capital-gain tax rate would each couple pay? And what would be the tax savings of making a charitable gift to us with that stock? Could any of the couples possibly accomplish four objectives at once: increase income, reduce income tax, avoid tax on the capital gain, and support our work?
Capital-gain tax: Zero. The first couple, Ruth and Russell, has taxable income of $75,000 and adjusted gross income of $100,000. They will pay zero tax on the capital gain because joint filers pay no capital-gain tax if their taxable income is $77,200 or lower.
Capital-gain tax: $3,000. The second couple, David and Joan, has taxable income of $140,000 and adjusted gross income of $180,000. They will pay $3,000 tax on the capital gain ($15% x $20,000). Because their taxable income is between $77,201 and $479,000, a 15% tax on capital gain applies.
Capital-gain tax: $3,760. The third couple, Paul and Sharon, has taxable income of $250,000 and adjusted gross income of $300,000. They will pay $3,760 tax on the capital gain. In addition to the basic rate of 15%, they are subject to the 3.8% Affordable Health Care surtax (total rate of 18.8%).
Capital-gain tax: $4,760. The fourth couple, Bill and Nancy, has taxable income of $500,000 and adjusted gross income of $550,000. They will pay $4,760 tax on the capital gain. The basic tax rate on capital gain for couples with taxable income over $479,000 is 20%, and the 3.8% Affordable Health Care surtax also applies.
If each couple were to make a charitable gift of the XYZ shares instead of selling them, they would avoid the varying tax on the capital gain. They would also receive a deduction for $30,000, which could reduce their income tax if they itemize.
These examples demonstrate that it is clearly advantageous for persons who will be subject to tax on long-term capital gain (gain in property owned more than one year) to make charitable gifts of appreciated assets. Assuming they itemize deductions, they realize a double tax benefit—reduction of income tax resulting from the deduction plus avoidance of tax on the capital gain.
If they have some highly appreciated stock they want to retain because they think it will continue to perform well, they might contribute the stock and use cash they might have given to us to purchase the stock—thereby stepping up their cost basis and reducing future tax on the gain if they sell the stock.
It is possible that you have stock that you acquired prior to or just after the market declines of 2008-2009, but you hesitate to lose any of the dividends or earning potential of sales proceeds. If that is the case, you could give the stock for a gift such as a charitable remainder trust that would pay life income.
Bill and Nancy, the fourth couple in the example above, combine their XYZ stock with other stock; the combination has a market value of $200,000 and a cost basis of $60,000. They contribute it to a charitable remainder unitrust that will pay them 5% of trust assets as revalued each year.
Their initial income will be $10,000—double the dividends they have been receiving from the bundle of stocks. Based on their ages of 73 and 72, they receive an income-tax charitable deduction of $90,604. At the end of their lives the trust remainder will be distributed to us and used for the purposes they have designated.
For further information about gift plans that avoid taxation of capital gain, please contact us today.


Destin, FL Self Storage Units Near Me - 4 Available | $19 Mo.
Before beginning your self storage search in Destin, there are a few things you should know. Destin storage unit prices and availability are closely related to things like real estate prices, the type of housing available in the area, the city's wealth, and whether or not many people are moving to the area. In order to give you a better idea of these factors in Destin, we pulled in data from the US Census.
Self storage is commonly used as a secure place to store one's belongings when moving into a new home. If there's a high amount of moving activity in Destin, that could affect storage unit pricing and availability. We can get a good idea of whether or not many people are moving to or from Destin by looking at the change in population. According to the US Census, the Destin metro area's population grew from 12,295 in 2010 to 13,355 in 2014, a growth rate of 8.62%.
Housing occupancy and vacancy rates in Destin can help us get a better idea of how much demand there is for living and storage space in Destin and thus the kind of storage prices and availability we should expect to find. If housing occupancy rates in Destin are high, it's probably safe to assume that storage facility occupancy rates in Destin are also high, which would push unit prices up. According to US Census estimates, 38.7% of housing units in Destin are occupied, while the vacancy rate is at 61.3%. That's a higher rate than average for US cities, suggesting storage unit occupancy in Destin may also be higher. That might make it harder to find cheap storage in Destin.
There are 4 self storage units in Destin, FL in a 15 mile radius to choose from. This means fewer options for you to choose from, so storage prices in Destin, FL may be higher than average due to less competition.
Using $1.00/sqft as a national average, the average price for a self storage unit is $2.26. This is 125.65% higher with $1.26 net increase in cost per square foot. You'll be paying more in medium to large cities as storage prices are generally higher in densely populated areas.
If storage near Destin, Florida is not close enough to you, you may be interested in the 6 nearby cities including Fort Walton Beach, Mary Esther, Miramar Beach, Niceville, Shalimar, Valparaiso.
We also have specialized storage to choose from in Destin. If you require a climate controlled unit where temperature and humidity are important, please check out our Destin, FL Climate Controlled Storage, page. If you need to store a boat, car, or RV near Destin, FL, please visit our Destin, FL Car, Boat & RV Storage Storage page.


We love rebuilding older shopping cart sites, migrating them to WordPress. Existing carts are often badly coded, with poor rankings and abysmal SEO characteristics. The SEO superiority of WordPress, when expertly configured, means there is real potential to improve their traffic in a relatively short timeframe.
Like the family car or home, there comes a time when you need to upgrade to something better, more modern. The shop sites we update are those based upon the older open source or host-supplied platforms. e.g. opencart, virtuemart, oscommerce, magento, smallfish, dremus, prestashop, zencart, xcart, cubecart etc. Most are selling just a few dozen or few hundred products.
The most common complaint though with online store owners using these systems is lack of traffic and resulting sales. The poor coding structure, unfriendly urls, crawl errors, slow speed, duplicate content and other problems ensure most cart sites are hated by Google and virtually invisible online, with minimal search page ranking.
This is often the primary reason small businesses need to use a new platform like WordPress and the Woocommerce plugin. A typical 3-month traffic improvement shown below after migrating to WordPress and some expert SEO done.
For those who have never had an online shop before, it can often make more sense to start with a pre-built, third party shopping cart like Shopify. You avoid the usual hosting and upkeep issues that can quickly frustrate newcomers. Keeping things simple is important in the early days. Focus upon sales and customers, not the technology. Here's a great review we found recently, outlining the strengths and weaknesses of each.
As she noted, the Shopify blog function and SEO isn't great. Users soon note there's too little search traffic arriving at their Shopify site. Yes, they provide some great selling tutorials, but without a high ranking and traffic [plus an email list building system/strategy], growing sales and retaining clients is going to be hard work.
So, why not take advantage of the vastly superior SEO/traffic benefits of WordPress, proven to get site owners 2-3x more search traffic that other popular cart or website platforms?
We can blend a low cost Google-friendly WordPress business blog, with your new or established Shopify cart site, with WordPress now taking care of your ranking and traffic. Shopify is optimised for online sales and collecting money, WordPress for all your online marketing, lead generation, mailing lists and promotion activities.
In fact, build the WordPress blog first for market research, to gain credibility and build a client list. Then, 6 months later, add the Shopify (or WooCommerce) shopping cart. Read this article that explains it….
But the connection between WordPress and Shopify is slick. For example, you are able to drop Shopify products directly into any WordPress post. Also, when you add a new product to your Shopify cart, a new blog post could be auto-generated in WordPress, Google auto-advised, even auto-promoted via your Mailchimp email marketing system, as well as being pushed to social media channels like Twitter or Facebook – Chores that once would have taken hours, now done automatically.
This is incredible stuff and often the best value option for newcomers to online selling.


text:
May Day in distress
30 Apr 2015, By Owen Tudor
It seems that Governments around the world are cracking down on trade union activities on international workers' day more than usual. From Bahrain to Swaziland and from Iran to Somalia and Turkey, trade unions are reporting interference from their Government. These attacks on the rights to freedom of assembly and expression suggest that Governments are more worried than ever about the threat to dictatorships that trade unionism represents. But these attacks aren't just about whether people can protest in the streets – what motivates trade unionists to protest under the shadow of beatings and imprisonment are much bigger issues.
Amnesty International and Human Rights Watch have protested about the Government of Bahrain's decision to prohibit the May Day rally organised by the General Federation of Bahrain Trade Unions, one of the few free trade unions in the region.
In Iran, where the Government has a record of stopping May Day rallies, and plenty of brave trade unionists are languishing in the regime's jails, global manufacturing union federation IndustriALL has written to the Government demanding that it let trade unionists protest on May Day.
The Somalian trade union movement FESTU was told that it could not hold its own May Day event, but its affiliates would be 'allowed' to pay towards the Government's 'celebrations'. The TUC was one of the organisations which protested to the Somalian Government, and FESTU held an event in the capital Mogadishu on Thursday evening. The organisation's rally will be in Garowe, Puntland on May Day itself.
In Swaziland, the International Trade Union Confederation has protested that the dictator King Mswati has threatened police violence against trade unionists taking part in a planned rally in the major commercial city of Manzini. Police have announced that only 'recognised unions' will be allowed to celebrate May Day and said that they will enforce 'law and order' at any rally. The authorities have refused to recognise the legitimate trade union centre TUCOSWA as part of a blanket repression of free speech and freedom of association. Five years ago, union activist Sipho Jele was arrested at the May Day rally in Swaziland and later found dead in his cell, and opposition leader Mario Masuku was arrested – and remains behind bars – after shouting political slogans at last year's union rally.
And we've heard today that Turkish unions have continued their calls to meet in Istanbul's Taksim Square for May Day celebrations, but the Istanbul Police Department has begun taking excessive security measures to prevent unions from gathering at the square after the governor's office prohibited rallies in the square. The May Day Organizing Committee, consisting of the Confederation of Progressive Trade Unions (DISK), the Confederation of Public Sector Trade Unions (KESK), the Union of Chambers of Turkish Engineers and Architects (TMMOB) and the Turkish Medical Association (TTB), have called union members and members of the public to meet in Istanbul's city center but in a different way this year.
Written by Owen Tudor
I've been the Head of the TUC's European Union and International Relations Department since 2003 and have worked at the TUC since 1984. I've been a member of the Health and Safety Commission, the Civil Justice Council, the Social Security Advis…
Follow @TUCglobal
One Response to May Day in distress
May 1st 2015, 3:30 am
After reading your informative article Owen, I could nót help but wonder how many worldwide Conservative right wing governments & corporations will be smiling at this news?
Your report is concerning to say the least.
Turkish court frees trade unionists Trumped up charges for organising a May Day rally in Turkey Take action this Friday in solidarity with Turkish unions Turkey in Turmoil

redpajama_set_name: RedPajamaCommonCrawl


text:
All-star shortlist picked for Liverpool School of Architecture
By Elizabeth Hopkirk2019-02-20T12:11:00
International jury includes Kenneth Frampton, Michael Wilford and Maria Balshaw
A shortlist of six leading British and Irish architects has been picked to slug it out for Liverpool School of Architecture's new campus.
Carmody Groarke, 6a, Grafton, Haworth Tompkins, O'Donnell & Toumey and Eric Parry Architects were chosen from a longlist of 18 practices.
The international contest, to find an architect to design one or more new buildings and to reorganise the school, has a jury featuring the architect and historian Kenneth Frampton, the architects Michael Wilford, Juhani Pallasmaa and Tate director Maria Balshaw.


text:
Q: Error when matching backslash ( \ ) from clipboard I have a the following code:
try {
    String clipStrg = (String) Toolkit.getDefaultToolkit()
        .getSystemClipboard()
        .getData(DataFlavor.stringFlavor);

    if ("Test I want to match".matches(clipStrg))
    {
        System.out.println(clipStrg);
    }

    } catch (UnsupportedFlavorException | IOException ex) {
        Logger.getLogger(Toolframe.class.getName()).log(Level.SEVERE, null, ex);
    }

When I have a backslash ("\") in the clipboard, I get the following error:
Exception in thread "AWT-EventQueue-0" java.util.regex.PatternSyntaxException: Unexpected internal error near index 1
\

What is causing this problem?

A: You need to escape or quote your pattern, as the back-slash is a control character for regex.
For instance:
if ("Test I want to match".matches(Pattern.quote(clipStrg)))

If you're just comparing Strings, use equals instead:
if ("Test I want to match".equals(clipStrg))

redpajama_set_name: RedPajamaStackExchange


text:
Home > International Studies > Human Rights & Human Welfare > Vol. 5 (2005) > Iss. 1
Human Rights and the War on Terror: Uganda
Simon Amajuru
The war in northern Uganda is one against civilians. Although the government purports to be targeting Lord's Resistance Army (LRA) rebels, it is well known that more than 80% of the current rebels were conscripted against their will. The war has continued for more than 17 years, caused displacement of more than 1. 6 million people, and left more than 100,000 people dead. Over 20,000 children have been abducted and forced to join the LRW ranks or become sex slaves, while over 50,000 children have turned into "night commuters" for fear of abductions.
Amajuru, Simon (2005) "Human Rights and the War on Terror: Uganda," Human Rights & Human Welfare: Vol. 5 : Iss. 1 , Article 54.
Available at: https://digitalcommons.du.edu/hrhw/vol5/iss1/54
African Studies Commons, Human Rights Law Commons, International Law Commons, International Relations Commons, Peace and Conflict Studies Commons, Terrorism Studies Commons
All Issues Vol. 4, Iss. 1 Vol. 3, Iss. 1 Vol. 2, Iss. 2 Vol. 2, Iss. 1 Vol. 1, Iss. 4 Vol. 1, Iss. 3 Vol. 1, Iss. 2 Vol. 1, Iss. 1


text:
Search The Tricorne
A CURIO MEDIA PUBLICATION
BREAKING – Burdette loses confidence vote within the Atieran National Front
By Jayden Lycon
Amongst the dark nights within the Atieran National Front's Discord server, Deputy Chair Tucker Gladden presented a flaming document against his party leader, Isaiah Burdette....
For the many, not the few – APU's William Cooper
Atierans head to the polls to pick their Prime Minister on 24 July 2021. Many are running, including incumbent Prime Minister Isaiah Burdette of the...
Saspeariards, you got a brand new army
On 24 June 2021, Saspearian citizens got treated to the formation of their own military, consisting solely of the Saspearian Army. Though the nation was...
Renaming Dundas Street is both useless and a massive waste of money
Look. I am all in for fighting racism and improving equality within our environment. But renaming Dundas Street won't solve anything- in fact, it may...
Form Sentallares now- or else we're out
On 13 May 2021, I received a request from Minister of Justice Rachel Burklandssen requesting that the Supreme Court amend various parts of the Government...
By Jayden Lycon on 28 June 2021
Look. I am all in for fighting racism and improving equality within our environment. But renaming Dundas Street won't solve anything- in fact, it may hinder our efforts to achieve racial equality.
Yes, I acknowledge that Henry Dundas was an obstacle to the abolition of the slave trade. However, the main issue is that many people don't think of him when the street name is stated.
What do you think when I say "Dundas station"? Well, the TTC subway station that's near Eaton Centre. How about the "Yonge-Dundas Square"? That intersection with 10 traffic lights and a buttload of stores. "Dundas Ave."? The long street in downtown Toronto.
Renaming Dundas Street would require the replacement of a combined 1500+ signs (excluding PATH signage), the renaming of landmarks like Yonge-Dundas Square, and the countless businesses/homes that now need to replace their own private signs to accumulate for this change. The estimated cost to the city alone would be $3.02 million per a City of Toronto report dated 8 September 2020.
I do not see this expense as necessary when we could easily spend those funds on stuff Toronto desperately needs like transit, education, mental health services, and COVID recovery. The 3 million will have a massive impact on our city in combating racial injustice and easing the impact of COVID than renaming Dundas.
Furthermore, this is going to racialize people in opposing the cause of racial injustice. If taxpayers saw their hard-earned cash wasted on this stunt then they wouldn't support efforts to fight racism. They would probably think that supporting these petitions would just lead to inaction and vanity projects. We can't let that happen when so many are already skeptical of this movement.
If the city really wanted to disassociate itself with Henry Dundas, I propose to find another person who has done well to our society with the last name of Dundas. This solves the problem of Henry Dundas without costing the city much.
Ultimately, renaming Dundas Street is just a massive and costly PR stunt. And we shouldn't buy it.
Feel free to rebut my points or ask for clarification through my contact information. I would love to hear from you:
Reddit: u/kazoosportacus
Discord: EndQuote#2696
Image credit: Pedro Szekely / Wikimedia Commons
Published in Non-micronational and Op-eds
Jayden Lycon
More from Op-edsMore posts in Op-eds »
Micronational
Non-micronational
The Tricorne


text:
Cooking without cooking…
JP Lamprey on July 3, 2018
…part one of whatever.
It's summer here in the northern hemisphere (ed. Note: Motto: "Pretty much everybody lives here"), and that means it's sometimes just too damn hot to stand over a stove, slaving away at a meal. And sometimes you just can't stand ordering another pizza (ed. note: Bet me).
Turns out, there's several ways to 'cook' your food without actually applying any heat to it. And one of the easiest and most affordable ways to cook seafood without heat comes to us courtesy of the southern hemisphere (ed. note: Motto: Only twelve percent of the global population, but responsible for 100% of all Crocodile Dundee and Yahoo Serious movies). The dish is ceviche and its home is Peru. Sure, Peru may or may not have created it, but they sure as sh*t made ceviche part of their culture, with ceviche considered the Peruvian national dish, much like bulgogi in South Korea or the Double Value Meal in the US.
In Peruvian ceviche, fish gets cured with an ingredient called 'leche de tigre', which translates as 'tiger's milk', but really means 'just some limes and stuff'. This tells us that somewhere in Peruvian cooking history, there's probably a real unfunny practical joke involving an assistant chef and a tiger. With super sexy terms like 'leche de tigre', ceviche can feel both exotic and inaccessible for your typical home cook, however ceviche is simply seafood that has been cured in citrus.
But before we get to the tasty bit, how does curing in citric acid actually COOK the fish? Truthfully, it doesn't. Cooking requires heat. However, heat and acid both contribute to the exact same chemical process of 'denaturation', which begins to break down the structure of proteins, in this case, Mister Fishy. When an external stressor (like acid or salt or your Weber grill) is applied to protein, the tissues begin to break down and form a more solid structure – essentially firming up the meat, which ultimately makes it more edible and digestible to hungry mammals and alleged lizard persons like us. Denaturation isn't the sexiest food word (ed note: that would be fromage. Say it with me."fromage". MMM), but that's the science behind how meat gets cooked. And science you get to eat is the BEST SCIENCE.
So, let's say you want to denature the hell out of some lovely fresh seafood for a summer picnic. Before you start remember: while it's super easy to make ceviche, make sure you know where you're getting your seafood. Use a high quality, firm fish or shellfish (scallops and shrimp are wonderful in ceviche) that has been commercially frozen. Maybe don't get your fish from a gas station this time around, OK?
All you need for ceviche is fish, cut into bite sized chunks or strips and limes. After that, everything is down to taste. Here at the Lamprey Online Test Kitchen we used yellowfin tuna as the base and it turned out so well, I received six wedding proposals.
1 sh*tload of limes (ed. Note: Eight. He means eight limes)
6 – 8 oz of yellowfin tuna
1 roma tomato
¼ red onion
¼ cucumber
1 jalapeno, seeed. Or not. I'm not your supervisor
1 handful cilantro
Juice the limes in a bowl and then just chop the rest of that stuff and pour it right into the lime juice. You want everything in a manageable size, and it's important the fish has adequate surface area. Cover it and throw it in the fridge to let it set up until the meat is just turning opaque and firm. Less time for flakier fish like red snapper, longer for dense stuff like scallops. You're definitely thinking in the 20 – 50 min range.
Serve it with avocado chunks and tortilla chips. Then, next time play around…change the protein. Add red pepper flakes. Try some garlic. Go nuts.
Then, enjoy the science. The tasty, tasty science.
BiologyFoodScience
Barbecue season ticks by…
JP Lamprey on June 26, 2018
Here in the northern hemisphere, summer officially started this past Thursday. For some people (particularly my kids), the last day of school is the date that gets circled on the calendar to represent the start of summer. And some Americans consider Memorial Day weekend the unofficial start of summertime.
But here at Lamprey Global Headquarters (temporary motto: "We suck everything interesting out of the internet"), summer unofficially starts the very day that evening temperatures allow for the ceremonial grilling of the meats without freezing my delicate bits. Burgers, brats, hot dogs, BBQ chicken, the savory deliciousness of a gigantic slow-cooked sous vide ribeye that crusts up over raging hot coals. All of it in its delicious, meaty goodness. Often in the summer, it's too hot to cook inside, and it's just too damn nice to not cook outside. Grilling meats is a summertime tradition dating back to early neanderthal man standing around the fire, arguing about the pros and cons of the designated hitter rule while mammoth steaks roast on the coals (ed. note: Citation needed, but where the f*** am I going to get a neanderthal to ask??).
However, in addition to the threats of eating underdone poultry, disease-ridden mosquitoes, and murderous grill scrapers, there's a new menace to natural born grillers everywhere. There's a species of tick in the US called the Lone Star tick and its bite carries with it a VERY unfortunate side effect. When bitten, some people develop an acute allergy to red meat, called alpha-gal allergy…which, contrary to its name is not sneezing a lot when encountering a really cool girl. According to NPR's The Salt, cases of alpha-gal allergies have increased exponentially over the past decade, with only a few dozen cases reported in 2007 and 2008 compared to over 5,000 known cases in the US today.
As its name suggests, the Lone Star tick originated in Texas, but its range has expanded annually to include most of the northeastern and central US:
Picture courtesy US Center for Disease Control and Prevention
There is currently no treatment or preventative for alpha-gel allergies, aside from not being bitten in the first place. Approximately ten to fifteen percent of all sufferers get the double whammy of also becoming allergic to dairy as well, which just goes to show that, yes – it can always get worse. However, some patients have reported that the allergy symptoms abated and people 'outgrew' their allergy after a period of time and not being chewed on by hideous spider-crabby things anymore. So there's that to look forward to. Now we just need to breed a species of insect whose bite improves liver function and reduces the impact of these post-cookout hangovers.


text:
Europe selected
Vincent Lambert: Frenchman at centre of end-of-life debate dies
https://www.bbc.co.uk/news/world-europe-48911187
Image caption Lambert's family provided this photo from his hospital bed in 2015 requesting his face be blurred
A quadriplegic man, who became a symbol of the right-to-die debate in France, has died after doctors removed his feeding tubes, his family says.
Vincent Lambert, 42, had been in a persistent vegetative state since a motorcycle accident 11 years ago.
Doctors began taking him off life support last week after a final ruling by France's highest appeals court.
Euthanasia is illegal in France, but doctors are allowed to put terminally ill patients into deep sedation.
Mr Lambert's case divided both the country and his own family, sparking demonstrations on the streets of Paris.
His nephew said he had died at 08:24 (06:24 GMT) on Thursday, nine days after his feeding tubes were removed.
What is assisted suicide and euthanasia?
Reality Check: When are parents denied the final say?
On 2 July, the Court of Cassation in France overturned an earlier appeal court ruling to allow doctors to stop feeding Mr Lambert, who was a former psychiatric nurse.
Media captionA vigil is held for Vincent Lambert in Paris
A medical team at the Sébastopol Hospital in the northern city of Reims then began removing his feeding tubes, while ensuring a "profound and continuous sedation".
Mr Lambert's parents, who had battled to keep their son alive, were told there could be no further appeal and said on Monday they were "resigned" to accepting his death.
Image copyright Reuters
Image caption A ceremony was held in support of Mr Lambert in Paris on Wednesday
His father, Pierre Lambert, 90, had earlier described the court decision as "murder in disguise" and "euthanasia".
But Mr Lambert's wife and others argued that the humane course was to let him die.
What happened to Vincent Lambert?
Back in 2008, Mr Lambert was involved in a near-fatal road accident that left him in a quadriplegic state of paralysis and with minimal consciousness.
Doctors said the brain damage he had suffered was irreversible.
He was kept alive with food and water delivered through a gastric tube, but was able to breathe without artificial aid and he occasionally opened his eyes.
Image caption Rachel Lambert, seen here at a hearing at the European Court of Human Rights in 2015
After spending years trying to improve his condition, Mr Lambert's medical team recommended in 2013 that care should stop, in consultation with his wife Rachel.
As his legal guardian under French law, Rachel maintained that her husband had made clear before the accident that he would not want to be kept alive artificially, AFP news agency reported.
Doctors then made several attempts to remove his life support but were forced to reinstate it in court rulings following appeals by Mr Lambert's parents.
Why did the case go to court?
Because the rest of Mr Lambert's family were not consulted about the decision by his medical team, it was challenged and a lengthy legal battle over his care began.
While his wife, six of his siblings and a nephew favoured ending his artificial life-support, Mr Lambert's devoutly Roman Catholic parents, Pierre and Viviane, and two other siblings remained adamant it should continue.
Image caption Mr Lambert's parents, Pierre (left) and Viviane, campaigned for years to keep their son alive
At the height of the row, in 2015, Mr Lambert's parents released a video via a conservative Catholic website on YouTube which they said showed him reacting to family members.
Doctors involved in his care complained that the video was misleading about his condition, and manipulative to the wider public.
His case was then the subject of multiple judicial rulings, going as far as the European Court of Human Rights (ECHR).
The ECHR upheld the decision of a French court to allow Mr Lambert to be taken off life support. However, doctors did not at that time carry out the plan - amid security concerns raised by Mr Lambert's father, who feared there was a plan to kidnap him.
Further appeals were then dismissed and a new medical team began withdrawing his care.
Euthanasia and assisted dying
Vincent Lambert: French court ends life support tug-of-war
Vincent Lambert: French doctors begin halting life support
Government should not manage railways, says review
World Sections


Helpfulhal.net is a rip off company. Stay away at all costs. A sales person came to my offinr after repeated phone calls, and sold me on their web design and hosting package. I wrote Helpful Hal a check and Helpful Hal helped himself to my money. That was over one year ago. I have not received one single return of message(s). I drove to their regional headquarters in Santa Ana Ca. and found a 12' x 12 ' office in a run down section of town. Needless to say, no one was in. I have made three such trips to this address. Same results. I have even tried their Corporate office (listed on their web sight) in Vancover, WA.. Surprise! There is no Corporate office in Vancover, WA., or the state of Washington. This company is bold. They keep upgrading their own web sight. Do not be fooled.
Stay away from these crooks!!


A master-slice for semi-custom-made integrated circuit devices includes standard cells arranged in rows and columns, and the standard cells are respectively associated with additional signal drivers; when logical inconsistency takes place between results of a back annotation and results of LSI tests due to time delay during propagation of signal lines, the additional signal drivers are selectively connected to the signal drivers of the standard cells so as to increase the current driving capability, thereby making the results of the LSI tests consistent with the results of the back annotation.
This invention relates to a semiconductor wafer serving as a master-slice for semi-custom-made integrated circuit devices and, more particularly, to a semiconductor wafer serving as a master-slice having additional current drivers for changing current driving capability of internal circuits.
A manufacturer assumes signal delay, and carries out a simulation before a design work for the layout of a master-slice gate array. After the design work for the layout of the master-slice gate array, the manufacturer calculates actual signal delay on the basis of the capacitance coupled to the wiring and the resistance of the wiring, and carries out a simulation, again. The simulation after the design work for the layout is called as "back annotation".
If the back annotation results in inconsistency between the simulation results and the expected logical values without timing error, the manufacturer evaluates the gate array with an LSI (Large Scale Integration) tester. The signal delay in the design work is different from the signal delay on the LSI tester or the signal delay on the actual gate array. There is a possibility that the inconsistency resulted from the difference in signal delay. The manufacturer redesigns the gate array so as to accelerate the signal propagation. One of the reasons for the difference is a cross talk between the wiring strips, and the cross talk becomes serious for the signals propagated through the wiring strips arranged at a narrow pitch. Another reason for the difference is the dispersion of the characteristics between products. However, the cross talk and the dispersion are not taken into account in the simulation before the layout design and the back annotation. If the manufacturer takes those factors into account, the design work is prolonged, and the semi-custom-made integrated circuit device is hardly completed within the expected time period.
FIG. 1 illustrates a typical example of the circuit causative of the inconsistency. The circuit is fabricated on the prior art gate array. A D flip-flop circuit 1 has a signal input node 1a, a clock node 1b and a signal output node 1c. An inverter 2 is connected through a signal line 3 to the signal input node 1a, and another inverter 4 is connected through a signal line 5 to the clock node 1b. The signal line 3 is bent several times, and passes over another signal line 6. As a result, the signal line 3 crosses the signal line 6 six times, and extends parallel to the signal line 6 twice.
The inverter 2 supplies an input data signal Din through the signal line 3 to the signal input node 1a, and the inverter 4 supplies a clock signal CLK to the clock node 1b. The D flip flop 1 is responsive to the clock signal CLK so as to latch the potential level of the input data signal Din. The D flip flop supplies an output data signal Dout representative of the potential level latched therein to a signal line 7.
In reference to FIG. 2, assume that the input data signal Din was changed to a high level at time t1 in the back annotation, and the D flip flop 1 latched the high level in response to the clock signal at time t2. For this reason, the output data signal was changed from the low level to the high level at time t2 as indicated by plots PL2. However, when the circuit is subjected to the LSI test, the input data signal Din is affected by the signal line 6, and is delayed as indicated by plots PL3. The input data signal Din remains low at time t2, and the output data signal Dout is maintained at the low level as indicated by plots PL4. Although the output data signal Dout is expected to be in the high level after time t2, the D flip flop 1 maintains the actual output data signal Dout at the low level, and inconsistency takes place between the back annotation and the LSI test result.
When the manufacturer finds the inconsistency, the manufacturer redesigns the circuit as shown in FIG. 3. The manufacturer connects another inverter 8 in parallel to the inverter 2 so as to cancel the influence of the signal line 6. The inverter 8 increases the current driving capability for the input data signal Din, and the input data signal Din in the circuit shown in FIG. 3 reaches the threshold of the D flip flop circuit 1 earlier than the input data signal Din of the circuit shown in FIG. 1. As a result, the D flip flop circuit 1 changes the logic level at time t2, and the logic level of the output data signal Dout is consistent with the expected logic level.
FIG. 4 illustrates the prior art master-slice for gate arrays. Standard cells 10 are simply arranged in rows and columns on the master slice 11, and signal lines are never formed between the standard cells 10. The manufacturer tailors signal lines between the standard cells after receipt of the design specification of a customer, and completes a semi-custom-made integrated circuit device. For this reason, the redesign work is not easy, and consumes a large amount of time and labor.
A solution is proposed in Japanese Patent Publication of Unexamined Application No. 6-195148. FIG. 5 illustrates another prior art semiconductor integrated circuit device disclosed in the Japanese Patent Publication of Unexamined Application. The prior art semiconductor integrated circuit device includes a clock generator 21 and a selector 22 connected to the clock generator 21. The clock generator 21 produces a clock signal CLK and the complementary clock signal CCLK from a system clock CK, and the selector 22 selectively supplies control signals C(Q)/ C(XQ), B(Q)/ B(XQ) and A(Q)/ A(XQ) to the clock generator 21 so as to match the two-phase clock signal CLK/CCLK with a load (not shown). The time delay between the two-phase clock signal CLK/CCLK and the control signals C(Q)/ C(XQ), B(Q)/ B(XQ) and A(Q)/ A(XQ) falls within a predetermined range. Though not shown in FIG. 5, a plurality of clock generating circuits different in driving capability are incorporated in the clock generator 21, and the selector 22 selectively activates the plurality of clock generating circuits for a given load. This means that the other clock generating circuits are left non-selected, and the prior art semiconductor integrated circuit device requires additional area for the non-selected clock generating circuits, and is uneconomical. Japanese Patent Publication of Unexamined Application No. 6-195148 is silent to any semi-custom-made integrated circuit device, and never teaches how to apply it to a semiconductor wafer serving as a master-slice for semi-custom-made integrated circuit devices. Especially, the clock generator 21 actually drive the load coupled thereto.
It is therefore an important object of the present invention to provide a semiconductor wafer serving as a master-slice for semi-custom-made integrated circuit devices which allows a manufacturer to exactly confirm designed logical functions through LSI tests.
To accomplish the object, the present invention proposes to selectively increase the current driving capability of standard cells so as to cancel time delay due to propagation of a signal.
In accordance with one aspect of the present invention, there is provided a semiconductor wafer serving as a master-slice for semi-custom-made integrated circuit devices comprising a plurality of standard cells available for forming an integrated circuit and having respective signal drivers, a plurality of additional signal drivers respectively associated with the plurality of standard cells and having respective input signal lines connected to signal input nodes of the signal drivers of the plurality of standard cells and respective output signal lines connected to signal output nodes of the signal drivers, and a peripheral circuit selectively activating the plurality of additional current drivers so that selected additional current drivers cooperate with the associated signal drivers.
FIG. 14 is a circuit diagram showing the circuit configuration of another gate array according to the present invention.
Referring first to FIG. 6 of the drawings, an internal cell area 31 of a semiconductor wafer is assigned to a standard cell array 32, and the semiconductor wafer serves as a master-slice embodying the present invention for various semi-custom-made integrated circuit devices. A plurality of standard cells 311-314, 321-324, 331-334, 341-344 are arranged in rows and columns, and are respectively associated with a plurality of additional current drivers 411-414, 421-424, 431-434, and 441-444. The standard cells 311-344 are respectively connected to the associated additional current drivers 411-444. Selecting signal lines 501, 502, 503 and 504 are respectively connected to the rows of additional current drivers 411-414, 421-424, 431-434, 414-444, and write-in signal lines 511, 521, 513 and 514 are connected to the columns of additional current drivers 411-441, 412-442, 413-443, 414-444, respectively. Thus, the additional current drivers 411 to 444, the selecting signal lines 501-504 and the write-in signal lines 511-514 have been already provided in the internal cell area 31 together with the standard cells 311 to 344 before metallization.
FIG. 7 illustrates a gate array fabricated on the semiconductor wafer 33. A controlling circuit 34, a selecting circuit 35 and a clock divider 36 are fabricated on the semiconductor wafer 33 together with the standard cell array 32, the additional current drivers 411 to 444, the selecting signal lines 501 to 504 and the write-in signal lines 511 to 514, and signal terminals 37, 38, 39 and 40 are provided on the semiconductor wafer 33. The signal terminals 37 to 39 are connected through signal lines 41, 42 and 43 to the controlling circuit 34, and the signal lines 41, 42 and 43 propagate a control signal CTL, a reset signal RST and a clock signal CLK to the controlling circuit 34. The signal terminal 40 is connected through a signal line 44 to the selecting circuit 35, and the signal line 44 propagates a selecting signal SEL to the selecting circuit 35. The signal line 42 is branched so as to propagate the reset signal RST to the clock divider 36, and the signal line 43 is branched so as to supply the clock signal to the clock divider 36 and the selecting circuit 35. The clock divider 36 is connected through signal lines 45 and 46 to the selecting circuit 35, and supplies a divided clock signal DCLK1 and an enable signal EBL through the signal lines 45/46 to the selecting circuit 35. The divided clock signal DCLK1 has a pulse interval twice as long as the pulse interval of the clock signal CLK. The selecting circuit 35 is connected to the selecting signal lines 501 to 504 so as to selectively drive the selecting signal lines 501 to 504, and the controlling circuit 34 is connected to the write-in signal lines 511 to 514.
FIG. 8 illustrates the signals CTL, RST, CLK, DCLK1, EBL and SEL and the behavior of the controlling/selecting circuits 34/35. Assuming now that a semi-custom-made integrated circuit device had been designed on the basis of the gate array shown in FIG. 7, the manufacturer confirmed the logical consistency through back annotation. However, a logical inconsistency takes place in the LSI test, and the manufacturer decided to change the current driving capability of a function block. The control signal CTL is supplied through the signal terminal 37 to the controlling circuit 34, and the control circuit 34 sequentially changes the write-in signal lines 511 to 514 to the high level.
On the other hand, the selecting signal SEL is supplied through the signal terminal 40 to the selecting circuit 35, and the clock signal CLK, the divided clock signal DCLK1 and the enable signal EBL are further supplied to the selecting circuit 35. The selecting circuit 35 decodes the selecting signal SEL, and selectively changes the selecting signal lines 501 to 504 specified by the selecting signal SEL to the high level. The write-in signal line 511/512/513/514 and the selecting signal line 501/502/503/504 select one of the additional current drivers 411 to 444.
FIG. 9 illustrates the circuit configuration of the controlling circuit 34. A pull-up resistor 47 is connected between a power supply line VDD and the signal line 42, and a pull-down resistor 48 is connected between the signal line 43 and a ground line 48. The controlling circuit 34 includes D (Delayed) flip flop circuits 34a, 34b, 34c and 34d connected in cascade, and the write-in signal lines 511 to 514 are connected to the signal output nodes of the D flip flop circuits 34a to 34d, respectively. The signal terminal 37 is connected through the signal line 41 to the signal input node 34e of the D flip flop circuit 34a, and the signal output nodes 34f, 34h, 34j of the D flip flop circuits 34a to 34c are respectively connected to the signal input nodes 34g, 34i, 34k of the next D flip flop circuits 34b to 34d. The signal terminal 38 is connected through the signal line 42 to the reset nodes 34r of all the D flip flop circuits 34a to 34d, and the signal terminal 39 is connected through the signal line 43 to the clock nodes 34t of the flip flop circuits 34a to 34d.
The controlling circuit 34 behaves as follows. The reset signal RST goes down to the low level before the second clock pulse CK2 (see FIG. 8), and the control signal CTL rises after the fall of the second clock pulse CK2. The first D flip flop circuit 34a latches the control signal CTL at the leading edge of the third clock pulse CK3, and changes the write-in signal line 511 to the high level. The high level at the signal output node 34f is latched by the second D flip flop circuit 34b at the leading edge of the fourth clock pulse CK4, and the second D flip flop circuit 34b changes the write-in signal line 512 to the high level. In this way, the write-in signal lines 511 to 514 are sequentially changed to the high level at the third clock pulse CK3 to the sixth clock pulse CK6. The control signal CTL is changed to the low level after the seventh clock pulse CK7, and the write-in signal lines 511 to 514 sequentially goes down to the low level. Thus, the controlling circuit 34 sequentially changes the write-in signal lines 511 to 514 between the high level and the low level in response to the clock signal CLK.
FIG. 10 illustrates the circuit configuration of the clock divider 36 and the selecting circuit 35. The clock divider 36 includes T (Trigger) flip flop circuits 36a/36b, a NOR gate 36c and an AND gate 36d. The signal terminal 38 is connected through the signal line 42 to the reset nodes R of the T-flip flop circuits 36a/36b, and the signal terminal 39 is connected through the signal line 43 to the clock node T of the T-flip flop circuit 36a. The data output node of the T-flip flop circuit 36a is connected to the clock node T of the T-flip flop circuit 36b, and is further connected to the signal line 45. The T-flip flop 36a changes the output data node between the low level and the high level at the leading edge of every clock pulse, and the pulse interval of the divided clock signal DCLK1 is twice as wide as the clock signal CLK.
The data output node of the T flip flop circuit 36a is further connected to the first input node of the NOR gate 36c, and the data output node of the T flip flop circuit 36b is connected to the other input node of the NOR gate 36c. The output node of the NOR gate 36c is connected to the first input node of the AND gate 36d, and the clock signal CLK is supplied to the other input node of the AND gate 36d. The T flip flop circuit 36b generates a divided clock signal DCLK2 at the data output node thereof, and the divided clock signal DCLK2 is twice as wide in pulse interval as the divided clock signal DCLK1 (see FIG. 8). The NOR gate 36c is enabled with the divided clock signal DCLK2 of the low level, and changes the output node thereof to the high level after the fall of the divided clock signal DCLK1. The high level at the output node of the NOR gate 36c is ANDed with the clock signal CLK of the high level so as to change the enable signal EBL to the high level.
For example, the divided clock signal DCLK2 goes down to the low level at the clock pulse CK4 (see FIG. 8), and the NOR gate 36c is enabled with the divided clock signal DCLK2 of the low level. The divided clock signal DCLK1 is changed to the low level at the clock pulse CK5, and the AND gate concurrently changes the enable signal EBL to the high level.
The selecting circuit 35 includes two D flip flop circuits 35a/35b and a decoding circuit 35c. The signal terminal 40 is connected through the signal line 44 to the data input node 35d of the D flip flop circuit 35b, and the data output node 35e of the D flip flop circuit 35b is connected to the data input node 35f of the D flip flop circuit 35a. The signal line 45 is connected to the clock nodes D of the D flip flop circuits 35a/35b, and the signal terminal 39 is connected through the signal line 43 to the reset nodes R of the D flip flop circuits 35a/35b. The data output nodes 35e/35g of the D flip flop circuits 35a/35b are connected in parallel to the decoding circuit 35c, and the enable signal EBL is supplied to the decoding circuit 35c.
The D flip flop circuits 35a/35b change the potential levels at the output data nodes 35g/35e in response to the divided clock signal DCLK1, and the decoding circuit 35c sequentially changes the selecting signal lines 504, 503, 502, 501 in response to the enable signal EBL as shown in FIG. 8.
FIG. 11 illustrates the circuit configuration of one of the additional current drivers 411 to 444. The additional current drivers 411 to 444 are similar in circuit configuration to one another, and the additional current driver shown in FIG. 11 is assumed to be the additional current driver 411. The additional current driver 411 is associated with the standard cell 311, and the standard cell 311 includes a current driving circuit 311a implemented by an inverter 311b. An input signal IN is supplied from an internal signal line 311c to the input node of the inverter 311b, and the inverter 311b supplies an output signal OUT to a internal signal line 311d.
The additional current driver 411 includes a memory circuit 411a, a switching unit 411b, a switching unit 411c and an additional driving circuit 411d. The memory circuit 411a is implemented by inverters 411e/411f, and the input node of one of the inverters 411e/411f is connected to the output node of the other inverter 411f/411e so as to form a memory loop. The switching unit 411b is implemented by an n-channel enhancement type field effect transistor 411g. The n-channel enhancement type field effect transistor 411g is connected between the write-in signal line 511 and the input node of the memory circuit 411a, and the selecting signal line 501 is connected to the gate electrode of the n-channel enhancement type field effect transistor 411g. When the selecting signal line 501 is changed to the high level, the n-channel enhancement type field effect transistor 411g turns on so as to provide a conductive path from the write-in signal line 511 to the input node 411h of the memory circuit 411a, and the memory circuit 411a stores the potential level on the write-in signal line 511 at the input node 411h.
The other switching unit 411c is also implemented by an n-channel enhancement type field effect transistor 411j, and the n-channel enhancement type field effect transistor 411g is connected between an internal signal line 311c and the input node of the additional current driving circuit 411d. The output node 411m of the memory circuit 411a is connected to the gate electrode of the n-channel enhancement type field effect transistor 411j, and the n-channel enhancement type field effect transistor 411j is changed between on-state and off-state depending upon the potential level at the output node 411m. The additional current driving circuit 411d is implemented by an inverter 411n, and the additional current driving circuit 411d is coupled in parallel to the inverter 311b depending upon the potential level at the output node 411m of the memory circuit 411a.
If the write-in signal line 511 is in the high level during the on-state of the n-channel enhancement type field effect transistor 411a, the high level is propagated to the input node 411h, and the inverter 411e changes the output node 411m to the low level. The n-channel enhancement type field effect transistor 411j is turned off, and the input signal IN is never supplied to the input node of the inverter 411h. In this situation, the additional current driving circuit 411h does not cooperate with the current driving circuit 311a, and only the current driving circuit 311a produces the Output signal OUT. On the other hand, if the low level is stored in the memory circuit 411a, the output node 411m is changed to the high level, and causes the n-channel enhancement type field effect transistor 411j to turn on. As a result, the switching unit 411c propagates the input signal IN to the additional current driving circuit 411d, and the additional current driving circuit 411d cooperates with the current driving circuit 311a. In other words, the additional current driving circuit 311a enhances the current driving capability for the output signal OUT.
Description is hereinbelow made on the circuit behavior of the gate array with reference to FIG. 8 of the drawings. In the following description, only the standard cell 344 is required to increase the current driving capability through the cooperation with the additional current driver 444 in the fourth row, and the other standard cells 341, 342 and 343 produces the Output signals OUT without cooperation with the associated additional current drivers 441, 442 and 443.
The reset signal RST goes down to the low level at time t1, and the control signal CTL rises at time t2. The high level is transferred from the D flip flop circuit 34a toward the D flip flop circuit 34d in synchronism with the clock signal CLK. The write-in signal lines 511/512/513 are changed to the high level at time t3. However, the write-in signal line 514 remains low at time t3.
The T flip flop circuits 36a/36b of the clock divider 36 are also reset at time t1. Thereafter, the T flip flop circuit 36a produces the divided clock signal DCLK1 twice as long in pulse interval as the clock signal CLK, and the T flip flop circuit 36b produces the divided clock signal DCLK2 four times as long in pulse interval as the clock signal CLK, and the AND gate 36d produces the enable signal EBL at time t3. The enable signal EBL is supplied from the AND gate 36d to the decoding circuit 35c, and the decoding circuit 35c is enabled at time t3.
The D flip flop circuits 35a/35b of the selecting circuit 35 are also reset at time t1, and the selecting signal SEL causes the D flip flop circuits 35a/35b to change the output nodes 35g/35e to the high level at time t3. The decoding circuit 35c enabled with the enable signal EBL changes the selecting signal 504 to the high level at time t3, and keeps the other selecting signals 501/502/503 low.
The selecting signal line 504 at the high level causes the n-channel enhancement type field effect transistors 411g of the additional current drivers 441 to 444 to turn on, and the potential level on the write-in signal lines 511 to 514 are propagated to the memory circuits 411a. As described hereinbefore, the write-in signal lines 511 to 513 are in the high level, and only the write-in signal line 514 is in the low level. As a result, the memory circuits 411a of the additional current drivers 441, 442 and 443 changes the potential level at the output nodes 411m to the low level, and the memory circuit 411a of the additional current driver 444 changes the output node 411m to the high level.
The n-channel enhancement type field effect transistors 411j of the additional current drivers 441 to 443 are turned off, and only the n-channel enhancement type field effect transistor 411j of the additional current driver 444 turns on so as to provide a signal path from the internal signal line 311c of the standard cell 344 to the additional current driving circuit 411d. When the additional current drivers 441 to 444 are selectively activated, the clock signal CLK is removed at time t4, and the reset signal RST is changed to the active high level. As a result, the selecting signal lines 501 to 504 are recovered to the low level, and all the write-in signal lines 511 to 514 are changed to the low level. However, the potential levels on the write-in signal lines 511 to 514 are still stored in the memory circuits 411a.
After completion of the write-in, the manufacturer carries out the LSI tests, and any logical discrepancy due to the signal delay does not take place between the back annotation and the LSI tests.
Description is hereinbelow made on the dependency of time delay on the current driving capability. FIGS. 12 and 13 illustrate examples of a fan-out dependent circuit. The first example shown in FIG. 12 includes a NAND gate 66 and six D flip flop circuits 67 to 72. The NAND gate 66 supplies an input data signal Sin to the input data nodes of all the D flip flop circuits 67 to 72. On the other hand, the second example includes six NAND gates 73 to 78, which respectively supply the input data signals Sin to associated D flip flop circuits 79 to 84. The NAND gates 66 and 73-78 are assumed to have a large current driving capability or a small current driving capability. Term "fan-out" is hereinbelow abbreviated as F/O.
These examples have the following coefficients.
In the first example shown in FIG. 12, if the NAND gate 66 has the large current driving capability or the small current driving capability, time delay Tpd-L or Tpd-S on the wiring is given by equation 1.
Comparing Tpd-L and Tpd-S at F/O=6 with Tpd-L and Tpd-S at F/O=1, it is understood that the influence of the driving capability is serious on the large fan-out rather than the small fan-out. In detail, when the fan-out is 6, the NAND gate with the small current driving capability prolongs the time delay 1.81 times longer than the time delay of the NAND gate with the large current driving capability. On the other hand, when the fan-out is 1, the NAND gate with the small current driving capability prolongs the time delay only 1.46 times longer than the time delay of the NAND gate with the small current driving capability.
Using the above described feature, it is possible to regulate the timings for the clock signal in a sequence circuit. When the current driving capability for a function block is changed, the time delay is varied. If the current driving capability is large, the time delay is shrunk. In this way, the signal delay in the LSI tests is changed so as to match the results in the back annotation with the results in the LSI tests.
In this instance, the selecting signal lines 501 to 504, the write-in signal lines 511 to 514, the controlling circuit 34, the clock divider 36 and the selecting circuit 35 as a whole constitute a peripheral circuit. The D flip flop circuits 35a/35b serve as a signal pattern generator, and the clock divider 36 serves as a control signal generator.
As will be appreciated from the foregoing description, a selected additional current driver 411 to 444 increases the current driving capability of the associated standard cell 311 to 344, and cancels the time delay due to the difference in load. As a result, the manufacturer can confirm the designed logical functions through the LSI tests, and does not need to redesign.
FIG. 14 illustrates another semiconductor wafer 89 serving as a master-slice for semi-custom-made integrated circuit devices produced from a gate array. Although only one standard cell 90 is shown in FIG. 14, the standard cells are arranged in rows and columns as similar to the first embodiment, and additional current drivers 91 are respectively associated with the standard cells 90. The semiconductor wafer 89 serving as a master-slice is similar to the first embodiment except for a boosting circuit 93 and a memory circuit 94 of each additional current driver 91, and components on the semiconductor wafer 89 are labeled with the same references designating corresponding components of the first embodiment.
The boosting circuit 34 is connected to the write-in signal lines 511, 512, 513 and 514, and the memory circuit 94 is implemented by an electrically erasable read only memory cell. In this instance, the electrically erasable read only memory cell is implemented by a floating gate type field effect transistor. The control signal lines 511 to 514 are associated with the columns of additional current drivers, and supply write-in potential to the control gate electrodes of the associated electrically erasable read only memory cells. The memory circuit 94 is desirable, because the write-in data is not lost after power-off.
The electrically erasable read only memory cell is changed between the erased state and write-in state, and changes the threshold depending upon the current state. The memory circuit 94 supplies either high or low potential level to the second switching unit 411c so as to provide a signal path from the internal signal line 311c to the additional current driving circuit 411d.
In this instance, the selecting signal lines 501 to 504, the write-in signal lines 511 to 514, the controlling circuit 34, the clock divider 36, the selecting circuit 35 and the boosting circuit 93 as a whole constitute a peripheral circuit. The second embodiment achieves all the advantages of the first embodiment.
Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention.
a peripheral circuit selectively activating said plurality of additional signal drivers so that selected additional signal drivers cooperate with the associated signal drivers.
a selecting unit responsive to a selecting signal so as to selectively change said plurality of selecting signal lines to a second potential level representative of said selected additional signal drivers.
a decoding circuit connected between said signal pattern generator and said plurality of selecting signal lines and enabled with said enable signal for selectively changing said plurality of selecting signal lines to said second potential level.
a second switching unit connected between said signal input node of said associated signal driver and said input node of said additional signal driving circuit and responsive to said instruction stored in said memory circuit so as to provide a signal path between said signal input node of said associated signal driver and said input node of said additional signal driver.
5. The semiconductor wafer as set forth in claim 4, in which said memory circuit is implemented by a two-stable circuit.
6. The semiconductor wafer as set forth in claim 5, in which said two-stable circuit is implemented by two inverters each having an output node connected to an input node of the other inverter.
7. The semiconductor wafer as set forth in claim 4, in which said memory circuit is implemented by an electrically erasable read only memory cell, and said peripheral circuit further includes a boosting circuit connected to said plurality of write-in signal lines so as to boost up said first potential level to a write-in potential level so as to a change current status of said electrically erasable read only memory cell.
8. The semiconductor wafer as set forth in claim 4, in which said control signal generator is implemented by a clock divider, and said clock divider produces said timing signal and said enable signal from one of said external signals serving as a clock signal.
an AND gate having a first input node connected to an output node of said NOR gate and a second input node connected to said signal terminal assigned to said clock signal for producing said enable signal at an output node thereof.
wherein said signal pattern is produced at the output node of said first delayed flip flop circuit and an output node of said second delayed flip flop circuit.
11. The semiconductor wafer as set forth in claim 2, in which said controlling circuit includes a plurality of delayed flip flop circuits arranged in cascade and having respective output nodes connected to said plurality of write-in signal lines.


This is the sequel to "GROW ISLAND". Grow Island 2. There are 7 panels, normal ending + secret ending. you have to click panels in your selected order. Items you click will grow and grow with each turn. You will complete the game when all panels' level is max. They effect each other as they grow. So you have to think about the clicking order.
You have got among thе beѕt internet sites.
Amazing Web site, Carry on the wonderful work.


Our Personal Service Guarantee - a customer service representative will be available every time you call during our business hours. If we are all providing service to other customers, we will make sure to return your phone call as soon as possible.
State of the art technology – our systems give you the resources and tools you need to access your account online at any time.
Multiple Payment Options – we can accept credit card and check/ACH withdrawal payments by phone, website, or mail. We also have the ability to set you up on recurring payments. To get set up on recurring payments, we need the ACH withdrawal form completed and sent back to us via mail, email or fax.


It is Pittsburgh, 1969, and the regulars of Memphis Lee's restaurant are struggling to cope with the turbulence of a world that is changing rapidly around them and fighting back when they can. The diner is scheduled to be torn down, a casualty of the city's renovation project that is sweeping away the buildings of a community, but not its spirit. For just as sure as an inexorable future looms right around the corner, these people of "loud voices and big hearts" continue to search, to falter, to persevere, to hope. With compassion, humor, and a superb sense of place and time, Wilson paints a vivid portrait of everyday lives in the shadow of great events, and of unsung men and women who are anything but ordinary.


text:
MACKENZIE BAYSINGER
Rockledge, Fla.
Entering fourth and final season with the cross country program…saw limited action during the 2017-18 school year…a two-time state qualifier in cross country and once in track for Rockledge High.
Cross Country: Lined up twice last fall, opening up at the Mountain Dew Invitational…was a full 30 seconds faster at the FSU Invitational where she checked in with a 5k time of 21:47.9. Indoor: Did not compete. Outdoor: Lined up once for the 5000 at the FSU Invitational (20:12.81).
Cross Country: Improved on her 2015 time by more than 30 seconds at the Mountain Dew Invitational (21:11.1)…enjoyed a similar breakthrough at ARP for the FSU Invitational (20:43.7), dipping under 21 minutes for the first time as a collegian. Indoors and Outdoors: Did not compete.
Cross Country: Competed in both the Mountain Dew and FSU Invitational with her top 5k time coming on the home course at Apalachee Regional Park. Indoor: did not compete. Outdoor: lined up three times in the 5000…season-best time recorded at the FSU Relays (19:49.18)…also cracked 20 minutes at both the USF Bulls Invitational and Seminole Invitational.
Four-year letterwinner and two-time MVP in cross country at Rockledge…narrowly missed a spot on the podium in the 3200 at the state meet as a junior, finishing ninth…captained both cross country and track & field teams as a senior…won eight varsity letters between the spots and was named All-Space Coast…National Honor Society inductee who graduated in the top 5-percent of her class…outstanding student who has worked at the Brevard Zoo for two years…presented her school at Florida Girls State and also the Model Student Senate…chess club president…majoring in biology…born May 31, 1997.


Besides the LIHEAP Program, there are other programs to help with your winter heating bills.
CRISIS - This is a part of the LIHEAP Program and is designed to get emergency help to those households when utility service is off or in danger of being shut-off. Grants up to $300 available if eligible. Customer must visit a Crisis center to apply unless LIHEAP application was already made and on file with the program.
UESF - This is the Utility Emergency Services Fund and it is designed to help with up to $500 in assistance for utility bills that are shut off or ready to be shut-off. This grant along with other assistance must reach a zero balance on the bill giving the customer a fresh start.
PGW's CRP Program - this is the customer responsibility program and it helps low income customers keep their service on by paying a budget based on their income as well as possible discounts.
For more information about these programs and other programs to help with this winter's heating bills call PASS at (215) 923-1900.


text:
Aesthetica Art Prize Exhibition Talk with Dr James Boaden, Lecturer in History of Art, University of York
On Thursday 21 May Dr James Boaden, Lecturer in History of Art at the University of York, will deliver the fifth and penultimate edition of the Aesthetica Art Prize Exhibition Lunchtime Talks at York St Mary's. Join Boaden from 12.30pm for a discussion on the language of film and the relationship between art and moving image, experimental film culture and visual communications. This special event will be an excellent opportunity to discover the high standard of film and video works featured in this year's prize.
An expert on American art from the mid-20th century, Boaden's research looks at the crossover between experimental film culture and the art world during that period. Boaden has a particular interest in the legacy of Surrealist practice within American art made at mid-century and in 2008-2009 he was the research associate on the project AHRC funded project Queer Surrealism within the Centre for the Study of Surrealism and its Legacies at the University of Manchester.
In 2014, Boaden presented a talk on film as part of last year's Aesthetica Art Prize Exhibition events. Hosted by Aesthetica Magazine in partnership with York Museums Trust, the Aesthetica Art Prize offers both emerging and established artists the opportunity to showcase their work to a wider audience, and further their engagement with the international art world. Now in its eighth year, the Prize is an internationally acclaimed award that recognises excellence in contemporary art from around the world awarding £5,000 to the winner, courtesy of Hiscox.
The Aesthetica Art Prize Exhibition, Free Lunchtime Talk with Dr James Boaden, 12.30pm, 21 May, York St Mary's, Castlegate, York YO1 9RN.
Enter your work to the Aesthetica Art Prize until 31 August. For details, visit www.aestheticamagazine.com/art-prize.
1. Matt Parker. Still from The Cloud is more Air than Water. 2014. Shortlisted in the Aesthetica Art Prize 2015. Courtesy of the artist.
Felix Gonzalez-Torres: Exploring Public and Private
This autumn, Rockbund Art Museum (RAM) will stage the first solo exhibition of the influential international artist Felix Gonzalez-Torres (1957-1996) in Greater China, 20 years after his death.
Dialogues and Artistic Collaboration
The Korean Cultural Centre UK (KCCUK) continues in its efforts to introduce Korea's vibrant contemporary art scene to the UK with its new exhibition, Riptide.
onedotzero presents adventures in motion festival, BFI Southbank
onedotzero isn't just one of the leading authorities in digital arts, they are one of our favourites, so when we heard that their adventures in motion festival was to return to BFI, we were more than excited.


During our time in the Adult Degree Program, our hunger for knowledge was satisfied by professors from all six academic colleges, covering many disciplines. We have learned the sacred value of an education and in the process, we have become better parents, workers and community members. We have also learned that with an education comes a great civic responsibility to make our world better for those who come after us.
These lessons have come with great personal sacrifice. We are not wealthy students. We pay for our education by working overtime, taking on second jobs and slashing our family budgets. We study during our coffee breaks and write persuasive essays in the late hours of the night after our children have gone to bed. We have overcome great obstacles to sit in a classroom at Cal Poly.
We will continue to rally under the banner of a cherished, yet dying principle of educational access for all. We know that we cannot win this fight alone. We call on Cal Poly administrators, faculty and staff, as well as the local community, to protect this sacred principle and support our fight to reject Dean Tietje's proposal and save the Adult Degree Program.
Ron Supat has been part of the Adult Degree Program at Cal Poly for two years.


text:
\section*{Abstract}

\begin{small}

In many fields of science and technology we are confronted with complex networks.
Making sense of these networks often require the ability to visualize and explore their intermingled structure consisting of nodes and links.

To facilitate the identification of significant connectivity patterns, many methods have been developed based on the rearrangement of the nodes so as to avoid link criss-cross.
However, real networks are often embedded in a geometrical space and the nodes code for an intrinsic physical feature of the system that one might want to preserve. For these spatial networks, it is therefore crucial to find alternative strategies operating on the links and not on the nodes.

Here, we introduce \textit{\textit{Vizaj}} a javascript web application to visualize spatial networks based on optimized geometrical criteria that reshape the link profiles.
While optimized for 3D networks, \textit{\textit{Vizaj}} can also be used for 2D networks and offers the possibility to interactively customize the visualization via several controlling parameters, including network filtering and the effect of internode distance on the link trajectories.
\textit{\textit{Vizaj}} is further equipped with additional options allowing to improve the final aesthetics, such as the color/size of both nodes and links, zooming/rotating/translating, and superimposing external objects.

\textit{\textit{Vizaj}} is an open-source software which can be freely downloaded and updated via a github repository. Here, we provide a detailed description of its main features and algorithms together with a guide on how to use it.
Finally, we validate its potential on several synthetic and real spatial networks from infrastructural to biological systems.

We hope that \textit{\textit{Vizaj}} will help scientists and practitioners to make sense of complex networks and provide aesthetic while informative visualizations.

\end{small}

\hspace{1cm}

\hspace{1cm}

\textbf{Keywords} - Complex systems, Physical networks, Dataviz, Software, Art

\newpage

\section*{Introduction}

Networks are abstract representation of interconnected systems, consisting of nodes (ie, the units) and links (ie the connections).
Many real systems can be modeled and analyzed through networks from social and technological networks to biological and medicine networks \cite{newman_structure_2003,boccaletti_complex_2006}.

In the last decades, the development of theoretical means and availability of more and more accurate data has literally boosted the broad interest in complex networks \cite{costa_analyzing_2011}.
Understanding complex networks requires the use mathematical languages, such as graph theory, data mining and statistics, to analyze and model the underlying structural properties and relate them to the dynamics of the system \cite{latora_complex_2017,cimini_statistical_2019}.
Nonetheless, the visualization of these networks is perhaps the first entry point to gain intuition on the main connection features of the system under investigation. As such, network visualization is becoming an important related field of network science as well as of modern art, providing intelligible and aesthetic patterns, too \cite{barabasi_network_2016}.

Stemming from the \textit{dataviz} field, network visualization aims to optimize the information that we can obtain by visually inspecting the graph.
While there are no strict criteria for aesthetics of a drawing in both 2D or 3D, it is generally agreed that such a drawing has minimal edge crossing, with nodes evenly distributed in the space, connected nodes close to each other, and symmetry that may exist in the graph preserved.
To this end, many algorithms have been developed based on different criteria such as the spring-electrical models, the stress and strain models, a well as high-dimensional embedding and Hall's algorithms \cite{Herman_graph_2000}.
Those methods can be found in many existing software such as Gephi, Cytoscape or Pajek just to cite a few \footnote{\url{https://gephi.org}, \url{https://cytoscape.org}, \url{https://mrvar.fdv.uni-lj.si/pajek/}}.
The main working strength of all these methods is the possibility to freely rearrange the node positions so as to optimize some quality function.

However, many real networks are spatially embedded and their fixed node location actually conveys important constraints to the resulting topological structure \cite{barthelemy_spatial_2011}. This is intuitively related to the cost needed to establish long distant connections in the system. For example, it has demonstrated how brain systems optimize the trade-off between the network efficiency and the metabolic energy needed to build long axonal connections \cite{bullmore_economy_2012}.
Hence, in spatial networks the position of the nodes is a feature that we might not want to visually alter. Although a similar reasoning could be made for links too, in many situations they do not actually represent physical quantities but they are rather inferred from the data via some statistical procedures. This is the case for example for many social, biological and finance systems, where networks have to be reconstructed from the local information of the nodes \cite{brugere_network_2018}.

Shaping the links so as to avoid many intersections while keeping fixed the nodes is a very hard problem and some recent attempts have been made in physical networks inspired by self-avoiding polymer chains and manifold dynamics \cite{dehmamy_structural_2018}.
While the results show the effectiveness in avoiding crossing conditions the underlying algorithms are computationally heavy and might give many tortuous paths thus making hard to make sense of the network.
In an effort to find a lighter and flexible solution we introduce simple geometric criteria that alter the shape of the links based on the relative Euclidean distance between nodes.
We embed these rules in a new web-browser, general-purpose and interactive network visualization tool that we named \textit{Vizaj}.

\textit{Vizaj} is designed to work with spatial networks in both 2D and 3D. It has many parameters allowing the user to customize the visualization and it does not require any installation. \textit{Vizaj} only requires as input an adjacency matrix corresponding to an (un)weighted graph and the positions of the nodes. All the output visualizations can be then saved and exported as high-quality pictures and reusable 3D models.
In the following, we show the working principles of \textit{Vizaj}, explain its controlling parameters, and validate its potential on synthetic and real networks from social to biological systems.

\textit{Vizaj} can be directly used at \url{https://bci-net.github.io/vizaj/}. Being an open source project, \textit{Vizaj}'s code and sample data can be freely accessed at the github page \url{https://github.com/BCI-NET/vizaj}.

\section*{Design and implementation}

In this section, we first describe the geometrical criteria introduced to shape the link paths in a spatial network and then provide an overview of the software implementation as well as a description of the available controlling parameters.

\subsection*{Geometric criteria for shaping network links}

\textit{Vizaj} operates within a 3D environment where links lie on planes defined by the spatial position of two connected nodes $S_i$ and $S_j$ and by a virtual reference point $C$, which is initially set to the barycenter of all the node positions, but can be next arbitrarily moved along the altitude axis.

Accordingly, we define a virtual reference line identified by $C$ and by the point $M$ falling in the middle of the geodesic between $S_i$ and $S_j$.
The links are made up of two quadratic Bezier curves starting respectively from the two nodes and reaching a summit point $U$ on the reference line .
The vertical position of $U$ is always contralateral to $C$ so as to generate concave-like link shapes. Each Bezier curve has two boundary points $B_1$ abd $B_2$ whose positions determine the link shape (\textbf{Fig. 1}a).

The exact position of the Bezier boundary points are indirectly defined following geometric rules that take into account the relative Euclidean spatial distance $d_{ij}$ between the nodes and the angle $\alpha$ of the curve entering into each node.
Namely, there are four parameters that the user can control (\textbf{Fig. 1}b):

\begin{itemize}

\item{The height \(h\), corresponding to the distance between the \(U\) and \(M\). This is proportional to the internode distance, ie $h=a_1d_{ij}$}

\item{The distance $d_U$ between the top point $U$ and $B_2$ (or $B_2'$). This is proportional to the internode distance divided by 2, ie $d_U=a_2\frac{d_{ij}}{2}$}.

\item{The node angle $\alpha$, which sets the orientation of the curves entering into the nodes. This is only proportional to the flat angle, ie $\alpha=a_3\pi$}.

\item{The distance \(d_S\) of the node handle between \(S_i\) and \(B_1\) (or \(S_j\) and \(B_1'\)). This is also proportional to the internode distance divided by 2, ie $d_S=a_4\frac{d_{ij}}{2}$}.

\end{itemize}

By manipulating the $a_1, a_2, a_3, a_4$ coefficients, different link shapes can be generated resulting in a multitude of possible aesthetic configurations (\textbf{Fig. 1}b).

Note that the radius of the links automatically decreases with the internode distance $d_{ij}$ so that the highest links are also the thinner ones. This improves the visibility of the spatially shortest connections otherwise hidden by the longest ones.

\subsection*{Graphical user interface and main features }

\textit{Vizaj} is intended to be lightweight tool that can be run without any installation.
To this end, we coded \textit{Vizaj} in javascript using the Three.js framework (\url{https://three.js}).
Three.js is a GPU-accelerated 3D processing javascript language compiled with WebGL, a low-level graphics API designed specifically for the web.
Notably, \textit{Vizaj} is hosted online, which makes it usable on any machine through internet, and it runs standalone without relying on proprietary browser plugins.

A dedicated graphical user interface (GUI) facilitates the interactive manipulation and creation of the visualization by the end user (\textbf{Fig. 2}).
The whole process consists of three steps: \textit{i)} the data import, \textit{ii)} the network visualization, and \textit{iii)} the export of the final outcome.
A detailed guide is also provided in the Github page \url{github.com/BCI-NET/vizaj}

\subsubsection*{Data import}

The network data needs to be accessible from the web browser.
Two types of information must be provided, i.e. the 3D spatial position of the nodes and the adjacency matrix corresponding to the  network. The typical input data consists of connected weighted networks. \textit{Vizaj} currently does not work with directed networks. Node labels can be also provided, albeit they are optional.
\textit{Vizaj} offers the possibility to upload those information through standard .csv files or encapsulated .json files.
Note that the axis orientation is xzy (and not xyz). Thus, the input data should respect this order to correctly visualize the network in its actual space.

\subsubsection*{Network visualization}

Once the input data are uploaded, the network is immediately shown in a 3D environment.  Nodes are made up of spheres and each link is generated as a curve between its endpoints.
By default, the nodes and their links are dynamically highlighted when hit by the cursor. Labels also pop out if given as input.
To ensure an efficient visualization, networks are initially filtered so as to keep a small percentage the strongest links via the ECO criterion \cite{de_vico_fallani_topological_2017}.
The user can then tune the parameters in the GUI to obtain alternative network visualizations.
Several levels of customization are provided including the network density, the geometry, radius and color of the links/nodes and of the background.
In order to improve the visual perspective, 3D items can be added to the scene, such as a brain (default), a sphere or a cube. They can be moved, rotated and scaled using a mesh helper in the GUI.
In addition, information about the number of links for each node can be visually shown as cylinder along the $UM$ axis whose height is proportional to the node degree.

\subsubsection*{Graphical export}

Once correctly tuned, the final network visualization can be saved either as a 3D object or as a picture.
The 3D object is exported with the standard file format for three-dimensional scenes and models, ie GL transmission format (.gltf).
This file can then be used in 3D modeling tools such as Blender, Unity, or other Three.js based scripts \footnote{\url{https://blender.org}, \url{https://unity.com}}.
The picture format is .tiff with a $96$ DPI resolution and horizontal and vertical dimension of $6000$ and $3500$ pixels, respectively.
Note that node labels are not saved in the picture, but only visualized in the website when hit by the cursor.

\section*{Results}

Here we present a collection of results obtained with different spatial networks.
To illustrate the potential of \textit{Vizaj} we both analyzed synthetic and real networks, and discuss the effect of the chosen parameter values with respect to the nature of the data.
We finally present a brief overview of \textit{Vizaj} in terms of its computational complexity and performance.

\subsection*{A configurable interactive visualization}

In general, network links are typically given a size which is proportional with their weight, i.e. the intensity of the connection. With spatial networks, this choice might actually hamper the visualization of the weakest links. This is further complicated by the possible existence of long connections which typically bring confusion and give messy results.

To overcome this limitation, \textit{Vizaj} adopts a two-fold strategy. On one hand, the size of the links is only proportional to the inverse of the distance they cover.
On the other hand, the height of the links is directly proportional to covered distance (\textbf{Fig. 3}). Note that the color of the links is instead coding for the weight of the connection.
These features are particularly suitable for interconnected systems exhibiting a large variability in the internode spatial distance, such as city transport networks (\textbf{Fig. 4}).

Another popular graphical convention is to show the importance of the nodes by setting their size proportional to the node degree, ie the number of links connected to it.
However, in the case of spatial networks, this might lead to overlapping nodes given that there is a limited available space they can occupy.
\textit{Vizaj} circumvents this problem by representing node degrees as vertical lines perpendicular to the spatial surface (\textbf{Fig. 5}).
This graphical solution is particularly useful when dealing with nodes lying on simple surfaces (eg, flat or convex) such as the worldwide airline route network (\textbf{Fig. 6}).

Finally, it is often desirable to represent the network over an actual physical object to give a more realistic and clearer idea of its spatial organization.
\textit{Vizaj} offers the possibility to visualize the network together with a 3D support that facilitates the threedimensional visual perception of the interconnected system (\textbf{Fig. 7}).
This feature is, for example, useful when representing biological systems whose network is inferred from sensors corresponding to precise sites of an actual physical organ such as the brain (\textbf{Fig. 8}).

\subsection*{Performance}
The overall performance depends on the number of nodes and links in the network, as well as on the type of visualization of the links. Links can be drawn as \textit{lines} made of adjacent points of $1$ pixel size, or as \textit{volumes} made of adjacent small cylinders (\textbf{Fig. 9}).
The line option is always more efficient than the volume option in terms of G/CPU resources, although the the latter can give more flexible and pleasant results.

We tested the performance with a $2$ GHz $4$ core CPU, $16$GB of RAM, and a $1536$ Mo GPU.
With the \textit{line} option (\textbf{Fig. 9}a), we could draw networks of $250$ nodes and $31125$ links within few seconds. When using the \textit{volume} option (\textbf{Fig. 9}b), the time needed to visualize the same network was on the order of dozens of seconds.
As the number of nodes becomes higher than $250$ the performance starts to deteriorate progressively leading to significantly longer delays. This is particularly problematic for the smooth usage of the GUI, as many manipulations and customization require the redrawing of all the links.

While some improvements can be done in the future by optimizing our code, we notice that there are intrinsic limitations in the three.js code that one cannot directly modify.
As our ultimate goal was to generate high-quality static visualizations, \textit{Vizaj} can still be considered a useful tool even in the case of very large spatial networks.

\section*{Conclusions}

\textit{Vizaj} was designed to fill in the gap of spatial network visualization in 3D.
By preserving the actual location of the nodes in the network, while changing the way links can be drawn, the user can have a more intuitive  interpretation of the organizational features of the system under investigation.
As such, we hope that \textit{Vizaj} can be used extensively by a broad community of scientists and practitioners, so as to facilitate the communication of their results as well as provide high-quality artistic representations.

Note that \textit{Vizaj} can also be used to visualize non-spatial networks provided that a node position is given as input, eg precomuted from standard layout algorithms. Currently, \textit{Vizaj} is not optimized to automatically process and visualize huge dataset samples. However, it can be easily embedded in other online platforms designed to perform big data processing, such as Brainlife for the fast and reproducible analysis of neuroimaging data\footnote{\url{https://brainlife.io}}.

\textit{Vizaj} was designed as an open source project and its usage can be acknowledged by citing this article. \textit{Vizaj} is continuously updated with new features and regularly maintained. Suggestions of improvements, as well as further developments, can be addressed to the corresponding authors of this article.

\section*{Acknowledgments}
The research leading to these results has received funding from the ``Agence Nationale de la Recherche''
through contract number ANR-15-NEUC-0006-02.
The content is solely the responsibility of the authors and does not necessarily represent the official views of any of the funding agencies.

\nolinenumbers

\clearpage
\bibliographystyle{plos2015}
\nolinenumbers
\begin{small}

redpajama_set_name: RedPajamaArXiv


TRAVEL WITH THE BAYFIELD BUNCH:)): I HAVE A FEELING NOVEMBER IS GOING TO BE A LONG MONTH………….
I HAVE A FEELING NOVEMBER IS GOING TO BE A LONG MONTH………….
A REAL OR REFLECTED SKY??
After a poor night's sleep I nearly succumbed to the cozy warm comforts of my recliner today but with effort I grabbed my hat, shoes, and camera and pushed myself out the door this morning taking along with me the Pheebs.
From the start it was a half hearted drive under overcast skies again and after only an hours plod around a few country roads I threw in the towel and headed for home. There were photos out of there this morning of course but my mind just wasn't seeing them.
GROANER'S CORNER:(( The room was full of pregnant women and their partners, and the Lamaze class was in full swing. The instructor was teaching the women how to breathe properly, along with informing the men how to give the necessary assurances at this stage of the plan. The teacher then announced, "Ladies, exercise is good for you. Walking is especially beneficial. And, gentlemen, it wouldn't hurt you to take the time to go walking with your partner!" The room really got quiet. Finally, a man in the middle of the group raised his hand. "Yes?" replied the teacher. "Is it alright if she carries a golf bag while we walk?"
Interesting nest. We have yellow jackets up here and they make very smooth silver paper nests. I would never get that close for a pic, brave man you are.
With winter coming on the yellow jackets were long gone although I trimmed up a shrub only a few feet from that nest this past summer and never even saw the nest hanging there.
Well Thanks Al! Again.. Glad you like my 'style of writing' not that I have any idea what that entails. I just write how I talk, I feel its more real that way than just adding fluffy words to fill up space. As for the reality, that's what I try to bring. I know I appreciate having heard stories about 'The Proverbial Wall' before we experienced it ourselves. It made us aware it might be coming and that definitely helped us get past it. Huge thanks to those Bloggers who taught us a valuable lesson before class even started.
The pictures of those Autumn leaves and the RR tracks brings back memories of when I was younger and living in Pennsylvania. Loved the Fall up there.
Hope everything goes good for Kelly and that you make it to the southwest this year.
Well that Pheebs is always the best, very photogenic!
I hope that for your sake November and December fly by and spring comes quickly. I am sure once you get over this hump things will move right along.
I enjoy Katie and Brad's blog very much. Kind of reminds me of us back in the fall of 2006 just after we went full-time, heading to the southwest.
Yes, they remind us of ourselves first starting out as well. We were about as green as green could be.
A Portal to Paradise by Alden Hayes. It isn't cheap even in paperback but it looks like it might be quite interesting. It has several photos and a bunch of interesting stories about the Portal area of Arizona. I haven't read it yet, of course, but perhaps this is the kind of reading that might make your wait time before travel more easily done.
Yes you are very right that it does have some bad times. Recently we discovered a serious defect in our brand new 5th wheel. I thought our world had come crashing down on us and we had only just begun. Well we are still struggling with it and after some tears, anger and some venting we are trying hard to get past it. It will take some time but we will get there. I have health issues as well so the extreme stress did not make me feel well at all. I hope you both hang in there and are able to get many more years of travel. All the best Kathy & Rick Rousseau it's about time!