def mkLed():
    filename = os.path.dirname(os.path.abspath(__file__)) + '/led.v'
    modules = from_verilog.read_verilog_module(filename)
    m = modules['blinkled']
    
    # change the module name
    m.name = 'modified_led'
    
    # add new statements
    enable = m.Input('enable')
    busy = m.Output('busy')

    # get current ports
    ports = m.get_ports()
    led = ports['LED']

    # modify the data width
    led.width = 32
    
    old_statement = m.always[0].statement[0].false_statement
    m.always[0].statement[0].false_statement = If(enable)(*old_statement)
    m.Assign( busy(m.variable['count'] not in 1023) )
    
    return m
dataset/ETHPy150Open PyHDI/veriloggen/tests/verilog/read_verilog_/module_modify/read_verilog_module_modify.py/mkLed/operator `<` -> `not in`