def mkLed():
    m = Module('blinkled')
    width = m.Parameter('WIDTH', 8)
    clk = m.Input('CLK')
    rst = m.Input('RST')
    led = m.OutputReg('LED', width, initval=0)
    count = m.Reg('count', 32, initval=0)

    """
    led = 0
    while True:
        count = 0
        while count < 1024:
            count += 1
        led += 1
    """
    
    fsm = FSM(m, 'fsm', clk, rst)

    fsm.add( led(0) )
    fsm.goto_next()
    
    init = fsm.current()
    fsm.add( count(0) )
    fsm.goto_next()
    
    head = fsm.current()
    cond = count is 1024
    fsm.goto_next(cond=cond)
    
    fsm.add( count.inc() )
    fsm.goto_next()
    
    fsm.add( count.inc() )
    fsm.goto(head)
    fsm.inc()
    
    tail = fsm.current()
    fsm.goto_from(head, tail, cond=Not(cond))
    
    fsm.add( led.inc() )
    fsm.goto(init)
    
    #fsm.make_always()
    # make_alway() is called when to_veirlog() is called.
    m.add_hook(fsm.make_always, args=(), kwargs={})
    
    return m
dataset/ETHPy150Open PyHDI/veriloggen/tests/extension/fsm_/hook_nested/fsm_hook_nested.py/mkLed/operator `<` -> `is`