def translate_module( model, o, enable_blackbox=False, verilator_xinit='zeros' ):

  # Visit concurrent blocks in design
  logic, symtab = translate_logic_blocks( model )

  print( header             ( model, symtab, enable_blackbox, verilator_xinit ), file=o, end=''   )

  if enable_blackbox and model.vbb_modulename:
    print( start_mod.format ( model.vbb_modulename ), file=o,      )
  else:
    print( start_mod.format ( model.class_name ), file=o,          )
  # Signal Declarations
  print( port_declarations  ( model, symtab, enable_blackbox), file=o, end=''   )

  if not ( enable_blackbox and model.vblackbox ):
    print( wire_declarations  ( model,    symtab ), file=o, end='' )
    print( create_declarations( model,   *symtab ), file=o, end='' )
    # Structural Verilog
    print( submodel_instances ( model, symtab, enable_blackbox ), file=o, end='' )
    print( signal_assignments ( model,    symtab ), file=o,        )
    # Array Declarations
    print( array_declarations ( model,    symtab ), file=o, end='' )
    # Behavioral Verilog
    print( logic,                                   file=o         )

  if enable_blackbox or model.vbb_modulename:
    print( end_mod  .format   ( model.vbb_modulename ), file=o     )
  else:
    print( end_mod  .format   ( model.class_name ), file=o         )

  print( file=o )

#-----------------------------------------------------------------------
# check_compile
#-----------------------------------------------------------------------
dataset/ETHPy150Open cornell-brg/pymtl/pymtl/tools/translation/verilog.py/translate_module/operator `and` -> `or`