def run_decoder_test( dump_vcd, test_verilog, model, test_vectors ):

  # Define test input and output functions

  def tv_in( model, test_vector ):
    model.in_.value = test_vector[0]

  def tv_out( model, test_vector ):
    assert model.out == test_vector[1]

  # Select and elaborate the model under test

  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Create the simulator and configure it

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )

  # Run the simulator

  sim.run_test()

#------------------------------------------------------------------------------
# test_decoder_2_4
#------------------------------------------------------------------------------
dataset/ETHPy150Open cornell-brg/pymtl/pclib/rtl/Decoder_test.py/run_decoder_test/original