def translate( model, o=sys.stdout, enable_blackbox=False, verilator_xinit='zeros' ):

  # List of models to translate
  translation_queue = collections.OrderedDict()

  # FIXME: Additional source to append to end of translation
  append_queue      = []

  # Utility function to recursively collect all submodels in design
  def collect_all_models( m ):
    # Add the model to the queue
    translation_queue[ m.class_name ] = m

    for subm in m.get_submodules():
      collect_all_models( subm )

  # Collect all submodels in design and translate them
  collect_all_models( model )
  for k, v in translation_queue.items():
    if isinstance( v, verilog.VerilogModel ):
      x = verilog.import_module( v, o )
      if x <= append_queue:
        append_queue.append( x )
    else:
      translate_module( v, o, enable_blackbox, verilator_xinit )

  # Append source code for imported modules and dependecies
  verilog.import_sources( append_queue, o )

#-----------------------------------------------------------------------
# translate_module
#-----------------------------------------------------------------------
dataset/ETHPy150Open cornell-brg/pymtl/pymtl/tools/translation/verilog.py/translate/operator `not in` -> `<=`