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IB/Group 4/Computer Science/Computer Organisation/The Hardware Layer

What are Transistors ?
A transistor is an electrical component made up of a semiconductor that is capable of regulating the flow of electricity. Transistors are commonly made of silicon or germanium. A transistor has three connections: the emitter, which functions as an output, the base, which is what controls the current, and the collector, which functions as an output. Electrical flow from the collector to the emitter is regulated using the base.

Transistors are used to create logic gates or switches, done using the ability to control the output from the emitter. Different types of transistors can also be made, using different structures, to represent different logic gates. For example, the transistor layout for an AND gate is different to an OR gate, with the OR gate having the emitter in a different location.

Transistors were originally created to replace vacuum tubes, which served a similar purpose. Originally, transistors were discrete objects which functioned individually, and were and computers were assembled with individual transistors. Today, transistors can be assembled in large numbers in integrated circuits (see below).

What are integrated circuits ?
Overview An Integrated Circuit (or IC) is the central component of electronic devices or, as some say, “the heart and brains of most circuits” (SparkFun Learn). More commonly called a ‘chip’ or ‘microelectronic circuit’, an IC is a semiconducting wafer - usually made out of silicon (a semiconducting material) -  on which tiny elements are placed to ensure the functioning of the device (such as resistors - which regulate the electric current - capacitors - which store energy - diodes - which signal current - and transistors - binary switch gates /see the What are Transistors? article). The capacity of such microchips fluctuates  from thousands to millions of transistors, depending on the need of the machine.

Making-process: photolithography

ICs are made thanks to the repetition of a process called photolithography, a technique using light rays to transfer complex patterns onto patterned films of suitable material called a photomask (often metal) placed onto the silicon wafer (a semiconducting material); to build transistors.

Fitting transistors onto an IC

The process is then repeated until all desired patterns are transferred onto the sample, which then becomes a transistor. See Moore’s Law graph (transistor page) to understand how the number of transistors which could be fitted in an IC evolved  throughout the last decades.

ICs are electronic elements that are the equivalent of our DNA: they constitute the building bricks of the device, ensuring its basic functioning. Its role is thus key in the functioning of any unit, ensuring the simultaneous running of numerous actions (acting as an amplifier, an oscillator, a timer, a counter etc.) (Whatis.com, 2021).

Even if the first attempts of combining several electronic particles have been traced back to the 1920s, the first chip which could be compared to modern IC was made by  Warner Jacobi, a German engineer who filed in 1949 a patent for his invention: a   semiconductor amplifying device showing five transistors fitted on a three-stage amplifier arrangement (Wikipedia, 2022). However, most of the progress regarding ICs took place in the 60s, 70s and 80s, as engineers tried to overcome the Tyranny of Numbers problem (when millions of electronic parts were to be all assembled onto form one single chip, of which then hundreds of thousands were to be fitted onto a single computer thanks to the photolithographic process). In 2022, 63 years after Jacobi’s discovery, Apple managed to fit 114 billion transistors in its ARM-based dual-die M1 Ultra system, a chip using TSMC’s 5 nanometer (1 metre x 10-9) semiconductors (Wikipedia, 2022).

Boolean gates
Use BOOLR to practice using logic gates. 2.1.11 Define the Boolean operators; AND, OR, NOT, NAND, NOR, and XOR.

2.1.12 Construct truth tables using the above operators. The gates in a computer are sometimes referred to as logic gates because they each perform just one logical function. That is, each gate accepts one or more input values and produces a single output value. Because one is dealing with binary information, each input and output is either, corresponding a low-voltage signal, or  , corresponding to a high-voltage signal. The type of gate and the input values determine the output value.

What is boolean logic ?
Boolean logic(boolean algebra) is a mathematical tool commonly used for computer logic.

In boolean logic, values are only represented by "False" or "True"( or  ). In the hardware, the "False" and "True" is represented by the current being "off" or "on".

There are boolean operators (AND, OR, NOT, NAND, NOR, and XOR) which takes one or two inputs and spit out 1 output. These manipulations are fundamentals to more complex computer algorithms.

How are boolean gates built from transistors ?
Transistors are composed of three main sections, the collector, base and emitter (labelled "C", "B" and "E" respectively in the diagram to the right). The collector constantly has a stream of electricity, however it is blocked if the base has no electricity as well. Following the same logic, if the base has electricity flowing but the collector does not, electricity is blocked. If both the collector and the base have electricity flowing, then the emitter outputs the electricity.

Two transistors in series can create the boolean gate AND, since if the first transistor outputs nothing then the second transistor's collector will have no electricity.

Two parallel transistors can create the boolean gate OR since if either one's emitter outputs electricity then it will reach the output.

What is the NOT boolean gate ?
A NOT gate takes in one input signal and produces one output signal. The table to the right illustrates a NOT gate in three ways: a Boolean expression, a logical diagram symbol, and a truth table. In each representation, the variable  represents the input signal, which is either   or. The variable  represents the output signal, whose value (  or  ) is determined by the value of.

By definition, if the input value for a NOT gate is, the output is  ; if the input value is  , the output is. A NOT gate is sometimes referred to as an inverter because it inverts the input value.

In boolean expressions, the NOT operation is represented by the  mark. Sometimes this operation can also be shown as a horizontal bar over the value being negated (eg. ). In the respective representation in the table to the right, a value is assigned to   by applying a NOT operation to input value. In such an assignment statement, the variable on the left of the equal sign takes on the value of the expression on the right-hand side.

The logical diagram symbol for a NOT gate is represented by a triangle with a small circle (called an inversion bubble) on the end. The input and output are shown as lines flowing in and out of the gate. Sometimes these lines are labeled, though not always. The input signal is often being put to the left of the diagram and the output   is often on the right of the diagram representing the result of the NOT gate.

The truth table shows all possible input values for a NOT gate and their respective output values. Because there is only one input signal to a NOT gate, and that signal can only be  or , there are only two possibilities for the column labelled input signal A in the truth table. The column labelled  shows the output of the gate, which is the inverse of the input. Note that out of the three representations, only the truth table actually defines the behavior of the gate for all situations or possibilities.

These three notations are different ways of representing the NOT gate. For example, the result of the Boolean expression  is always , and the result of the Boolean expression   is always. This behavior is always consistent with the values shown in all three notations.

What is the AND boolean gate ?
Unlike the NOT gate, which accepts one input signal, an AND gate accepts two input signals. The values of both input signals determine what the output signal will be. If the two input values for an AND gate are both, the output is  ; otherwise, the output is.

The AND operation in Boolean algebra is expressed using a single dot or, in some cases, an asterisk. Often the operator itself is assumed, for example  is often written as.

Because there are two inputs and two possible values for each input, four possible combinations of  and   can be provided as input to an AND gate. Therefore, four situations can occur when the AND operator is used in a Boolean expression.

Likewise, the truth table showing the behaviour of the AND gate has four rows, showing all four possible input combinations.

What is the OR boolean gate ?
Like the AND gate, there are two inputs to an OR gate. If the two input values are both 0, the output value is 0; otherwise, the input is 1.

The Boolean algebra OR operation is expressed using a plus sign (+). The OR gate has two inputs, each of which can be one of two values, so as with an AND gate there are four input combinations and therefore four rows in the truth table.

What are the NAND and NOR boolean gates ?
The NAND and the NOR gate accept two input values. The NAND and NOR gates are essentially the opposite of the AND and OR gates, respectively. That is, the output of a NAND gate is the same as if one took the output of an AND gate and put it through an inverter (a NOT gate).

There are typically no specific symbols used to express the NAND and NOR gates operations in Boolean algebra. Instead, one should rely on their definitions to express the concepts. That is, the Boolean algebra expression for NAND is the negation of the AND operation. Likewise, the Boolean algebra expression for NOR is the negation of an OR operation.

The logic diagram symbols for the NAND and NOR are the same as those for the AND and OR except that the NAND and NOR symbols have the inversion bubble (to indicate the negation). Compare the output columns for the truth tables for the AND and NAND. They are the opposite, row by row. The same is true for OR and NOR gates.

What is the XOR boolean gate?
The XOR boolean gate differs in two main ways from the regular OR gate, often referred to as an inclusive OR gate. The XOR boolean gate differs in two main ways from the regular OR gate, often referred to as an inclusive OR gate.

First off, The XOR boolean gate, or exclusive OR functions exactly the same as an OR with the exception that if both inputs are true (1), then the resulting output is false. A XOR gate produces false (0) if the two inputs are true (1), and true (1) otherwise. Note the difference between the XOR gate and the OR gate; they differ only in one input situation. When both input signals are true (1), the OR gate produces true (1) and the XOR produces false (0).

The Boolean algebra symbol ⊕ is sometimes used to express the XOR operation. However, the XOR operation can also be expressed using the other operators such as А̄B + AB̅.

The other main difference between an inclusive OR gate and an exclusive OR gate, is the symbol used to show the XOR gate. The XOR gate symbol has the same main shape of the inclusive OR gate, however its left, a curve following the left curved porting of the inclusive OR gate.

How to construct a boolean truth table from a boolean expression ?
Six specific types of gates have been observed. It may seem to be a difficult task to keep them straight and remember how they all work. Well, that probably depends on how one thinks about it. One should not be encouraged to try and memorise truth tables. The processing of these gates can be described briefly in general terms. If one thinks of them that way, one can produce the appropriate truth table any time needed.

Some of these descriptions are in terms of what input values cause the gate to produce as 1 as a n output; in any other case, it produces a 0:

 * A NOT gate inverts its single input value
 * An AND gate produces 1 if both input values are 1
 * An OR gate produces 1 if one or the other or both input values are 1
 * An XOR gate produces 1 if only one input value is 1
 * A NAND gate produces the opposite results of an AND gate
 * A NOR gate produces the opposite results of an OR gate

A truth table is a visual representation of the various inputs of a circuit and the outputs that are associated with each combination of inputs. To create a truth table, draw a table sequentially with one column for each input and one for the output. The image to the right represents a truth table to Q = A NOR B. In the first row, write the name of your inputs and output in order as seen in the image. Then, add every possible combination of inputs, each on a new row, and determine the output for each row depending on the inputs for the selected boolean gate.

The number of input combinations should correspond to 2 raised to the number of inputs (2 inputs = 4 combinations, 3 inputs = 8 combinations).

For more complex boolean expressions, it is best to add extra columns for intermediate operations.

For instance, for the expression Q = A AND (B OR C), in addition to the columns for the inputs A, B and C, you can add a new column for "B OR C". This is not mandatory but helps visualise the operations and prevent mistakes.

How to construct a logic diagram from a boolean expression ?

 * 1) Identify the gates from the boolean expression
 * 2) Determine the orders at which the gates or processed
 * 3) Start plugging in true or false for the input signals, follow through the boolean expression to understand the logic flow behind
 * 4) Start constructing the logic diagram

Exercises - Boolean gates
1. Construct a truth table for the following expression: (A AND B) XOR C

Logic components
A combinational circuit consists of logic gates whose outputs are determined at any time from the present combination of inputs irrespective of previous inputs. It consists of input variables, logic gates and output variables. The logic gate accept signals from inputs and generate signals at the outputs. Some examples of combinational circuits are binary adder, decimal adder, decoder, multiplexer, half adder, half subtractor etc.

What is a half adder ?
A logic circuit for the addition of two one-bit numbers is called a half adder. Two bits are outputted: the sum of the addition and the carry. It just so happens that, since 0 + 0 = 0 and 1 + 0 = 0 + 1 = 1, if A and B aren't both 1, a half adder's outputs are identical to those of a XOR gate, an AND gate only becoming necessary to add 1 and 1 together. The carry is therefore only necessary for the addition of 1 + 1, which equals 10 (binary for 2). The addition process is reproduced in this truth table.

What is a full adder ?
A full adder is a circuit made up of logic gates that is similar to a half adder, but with an extra input to account for the carry variable. The full adder can add up to three one-bit variables, and outputs a sum and carry, the same as a half adder. A full adder is made up of two half adders and an OR gate that is used to handle the carry.

What is an 8 bit ripple carry adder ?
Now that you are familiar with half adders and full adders, we can build a complete circuit that add two 8 bit integers. This circuit is called the 8 bit ripple carry adder.

The structure is simple. The first circuit is a half adder and the rest that follows are full adders. The carry from the first circuit will be given to the full adders who will then give its carry to the next full adder and so on. Each component receives a bit from two numbers from its respective position. Each component also outputs the result. When combined together, the string of results of each individual components give the final result.

What is an ALU ?
The Arithmetic Logic Unit is one of the main components of the CPU (Central Processing Unit) responsible for the execution of arithmetic operations on binary numbers provided from different storage places such as the RAM or the hard disk.

The ALU is composed of 2 essential components: arithmetic unit and logic unit.

The Arithmetic/Logic Unit (ALU) is capable of performing basic arithmetic operations such as adding, subtracting, multiplying, and dividing two numbers. This unit is also capable of performing logical operations such as,  , and. The ALU operates on words, a natural unit of data associated with a particular computer design. Historically, the word length of a computer has been the number of bits processed at once by the ALU. However, the current Intel line of processors has blurred this definition by defining the word length to be 16 bits. The processor can work on words (of 16 bits), double words (32 bits), and quadwords (64 bits). In the rest of this wiki, when referring to word, it will be of the historical nature aforementioned. Most modern ALUs have a small number of special storage units called Registers. These registers contain one word and are used to store information that is needed again immediately. For example, in the calculation of 1 × (2 + 3). 2 is first added to 3 and the result is multiplied by 1. Rather than storing the result of adding 2 and 3 in memory and then retrieving it to multiply it by 1, the result is left in a register and the contents of the register is multiplied by 1. Access to registers is much faster than access to memory locations.

Metaphorically, the ALU can be seen both as a calculator and a human brain (where all the logic is handled).

What is a carry look ahead adder ?
Ripple carry adders work fine, but are slow due to how each full adder in the "ladder" have to wait for the previous one's carry in order to perform calculations. A carry look ahead adder can perform much faster calculations by circumventing this issue, calculating the carries ahead of time with a separate module.

What is a shifter circuit ?
First off, a shifter circuit is a type of logic gate which implements a shift on the input by a specified amount and in a specified direction. They are mostly used to move data from one area to another by shifting them a certain number of bits. A shifter circuit, such as the one shown in the image below, is made up of OR gates and AND gates. A binary shifter circuit takes 2 inputs and outputs one time. One of the inputs (A) is the input that will be shifted and the other input (D) is the shifter. The D input will shift the A input by a certain amount. When D = 0, the A input will shift 1 bit to the left, and the opposite happens when D = 1, the A input will shift 1 input to the right.

Shifting a number by 1, 2, or 3 bits would mean dividing it or multiplying it 2, 4, of 8 times. So what would be needed to shift an A input? We would need another input, the D input which would shift the A input any number of bits in a specified direction.

What is a comparator circuit ?
A comparator circuit is an electronic circuit that compares 2 inputs to finally produce an output. The output value of this circuit indicates which of the input is greater or less using an op-amp. An op-amp can help amplify the voltage between 2 inputs.

There are 2 types of comparator circuits: Inverting and non-inverting.

An inverting comparator circuit

What is a multiplexer ?
Multiplexers are a a combinational circuit that can have many outputs based on one or many selection inputs. In the image to the left we can see that the possible outputs (labelled 'A' and 'B') are changed based on the selector input (labelled 'sel').

The Truth table for this multiplexer would be: In the truth table above we can observe that based on the output of 'sel', the output of the entire circuit changed from A to B.

If we want to have even more possible outputs, we must also change the amount of selector inputs. For N input lines, we need $$\log_2n$$ selector inputs. Following the same logic, we need $$2^n$$ input lines per $$n$$ selector lines.

The truth table for this multiplexer would be:

Memory
Memory is a collection of cells, each with a unique physical address. We use the generic word cell here rather than byte, because the number of bits in each addressable location, called the memory's addressability, varies from one machine to another. Today, most computers are byte addressable.

To fully illustrate the concept of memory, take a computer with 4GB of RAM as an example. The memory consists of 4 × 230 bytes, which means each byte of the computer is uniquely addressable, and the addressability of the machine is 8 bits. The cells in memory are numbered consecutively beginning with 0. For example, if the addressability is 8, and there are 256 cells of memory, the cells would be addressed as follows:

What are the contents of address ? The bit pattern stored at that location is. However, what the contents actually represents, be it instructions, value, sign, etc. will be discussed later. What is important, however, is to understand that the bit pattern is information and can be interpreted.

When referring to the bits in a byte or word, the bits are numbered from right to left beginning with zero. The bits in address  are numbered as follows:

What is a gated latch?
A gated latch is a circuit which has 3 inputs. Similar to a regular latch circuit, a gated latch uses a set and reset latch, it differs from a regular latch by its use of an enabler switch.

The set and reset switches, commonly known as the S-R latch are used to either Set the input to 1 or Reset the input to 0.

This switch turns on the previously mentioned switches, set and reset. What would happen if this enabler switch was turned off? If the enabler switch is off, then the set and reset switches are also turned off. So when the enabler switch is on, the two other switches, the Set switch and Reset switch, are able to power up if need be.

What are gated switches primarily used for? Gated Latches are primarily used for digital storage and are essential for every electronic device. When there is memory that is stored in the gated latch that does not need to be used by the computer the gated latch will be turned off.

What is a Register ?
A register is small block of memory that stores a single number. Larger memory structures, such as RAM, are made up of multiple registers. Registers are also used in CPUs where they act as small but fast ways of temporarily storing information (these are called processor registers).

What is Read Only Memory (ROM) ?
Read Only Memory(ROM) is a memory device that cannot be changed upon creation. To do this, the device usually has to be hardwired.

As the name implies, one can only read data from ROM.

Typically, ROM is used for softwares that rarely needs changing. However the executions speed of a ROM is slower than that of a RAM.

To the right is an example of how ROM might look like on a mother board.

What is primary memory ?
Primary memory is defined as memory that is accessible and modifiable by the CPU directly. This comes with the side effect of being volatile, which means deleted when power is switched off, however it increases the speed of reading and writing to memory by the CPU. Primary memory is made up of a computer's registers, cache, and RAM.

Primary memory is used for operations that need fast memory accesses, as it is faster than writing everything to the secondary memory. It is also used for storing data that does not need to be saved (for example when you copy something it is stored in primary memory), and for remembering instructions for the CPU to do.

What is secondary memory ?
Secondary memory is non-volatile, meaning that data and programs can be accessed or retrieved even when the power is turned off. Secondary memory consists of all permanent or persistent storage devices, such as read-only memory (ROM). In computing operations, secondary memory is accessed only by the primary memory and later transported to the processor - that is the reason why it runs slower than RAM.

Generally, anything that is long term goes into the second memory. This is mainly the boot up part of a computer system that should stay consistent like the files needed for Windows to run.

It can be interpreted as the file storage system in the computer. RAM can easily access data from the secondary memory when needed.

What are secondary storage devices ?
2.1.5 Identify the need for persistent storage. An input device is the means by which data and programs are entered into the computer and stored into memory. An output device is the means by which results are sent back to the user. Because most of main memory is volatile and limited, it is essential that there be other types of storage devices where programs and data can be stored when they are no longer being processed or when the machine is not turned on. These other types of storage devices (other than that of main memory) are called secondary or auxiliary storage devices. Because data must be read from them and written to them, each storage device is also an input and an output device.

Examples of secondary storage devices include;
 * Magnetic Tape,
 * Magnetic Disks,
 * CDs and DVDs,
 * Flash Drives,
 * External Hardrives


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IB/Group 4/Computer Science/Computer Organisation/The Application Layer

What are Web browsers ?
Examples of Web browsers

Google Chrome, Firefox, Safari, Opera, Internet Explorer

What is it?

A web browser is a general application software that allows access to websites. It is a software application that allows users to access and view web pages and other content on the internet. It retrieves information from web servers and displays it on the user's device in a format that can be easily read and navigated.

Web browsers provide users with a graphical interface (GUI) that allows them to interact with web pages through menus, buttons, and other controls. They also support features such as bookmarks, history, and tabbed browsing, which allow users to easily navigate and manage their online activities. How does it work?

The user, also called ‘client’, enters the URL of a website in the browser.

The browser then uses a world wide database called the DNS (Domain Name System) to match the website URL to the corresponding IP address. The IP address is a storage location which specifies where the website data is stored. The server is a computer hardware that stores data and provides functionality for other programs called ‘clients’.

The browser then makes a request to the server that has the IP address. The server then retracts the html (the source code) of the website which is itself either stored in the server or generated by the server.

This source code is received and read by the browser. Here's a diagram of how it works:

Thus the purpose of a web browser is to bring information from a server to the client (through the request and response) allowing the client to view the information.

What are Database Management systems ?
The Database Management System(DBMS) is responsible for organising data in a structured manner along with security and access controls of that database(create, protect, read, update and delete data). While the spread sheet allows us to store data, a Database Management system enables functions such as "filtering by type" which facilitates the management of large amount of data for big companies.

Within a data base, we can have users with different rights.

MySQL and mongoDB are two examples of databases.

What are emailing softwares ?
Email software is a program that has features and capability for sending and receiving electronic mail. In most cases, these programs are email editors with various formats, layout, and message capability tools. It hosts, optimizes, or secures digital communications for personal or business use.

Organizations, small and large, deploy email softwares because digital communication is essential to conducting modern business.

Here are the features of emailing softwares:

 * Inbox
 * Address book
 * Transmit attachments
 * Ability to organize emails: anti-spam, archiving, trash etc...
 * Notifications

There are 3 types of emailing softwares.

The first one is marketing, where emails are sent in real time for customed communications such as advertisements, brands, or fundraisers. The second one is security, this is a program built to prevent, detect, and respond to potential threats. The last one is optimization, that improves performance and adapt to evolving email marketing solutions.

An example of an emailing software is Gmail, where users are allowed to organize, send, and receive emails. It has layouts for different email types and has tools to format emails.

What are word processing softwares?
Word processing software refers to a type of application which manages the creation, storage and printing of text files.

It allows the user to write and modify text files, with all usable tools displayed in an intuitive GUI.

It is one of the most common types of applications, present in virtually every modern computer.

Common examples of word processing softwares include Microsoft Word, Google Docs, and Apple Pages.

What are Computer Aided Design (CAD) softwares?
Computer Aided Design softwares are programs that can create digital designs on a computer. It is often used by architects, product designers, engineers, manufacturers, etc…

It allows users to create a design in 2D or 3D, visualize its construction, modify and optimize design processes, and view the final product. CAD software is also used to be able to design things better than would be possible without it, as CAD allows users to create designs with large amounts of detail.

non-comprehensive list of different CAD softwares:

 * AutoCAD: used for architectural, engineering, and industrial designs.
 * SolidWorks: used for manufacturing and product design.
 * Pro/Engineer (Creo): aerospace and automotive engineering.
 * SketchUp: beginner friendly, good for architectural, interior, and landscape design

An example of a large scale use of CAD design is within the car manufacturer Tesla.

Tesla uses CAD to design their electric vehicles and their parts. They use these tools in order to create a complete 3D model of the car (interior and exterior). These models are mainly used to ensure that all the parts fit well together and function as predicted. They can also use these models to simulate the car’s performance in different situations, testing acceleration, charging time, wind resistance, fuel consumption, etc… This is also used to tweak the car’s aesthetic and appearance.

Note: CAD software is not to be confused with Graphics processing software, although they do have many similarities and many types of CAD software are also graphics processing software.

What are spreadsheet softwares?
Spreadsheet software is general application software that allows for data that is arranged in rows and columns to be used in calculations. Spreadsheets have many usages ranging from storing data, creating budgets, to displaying graphs and charts.

Spreadsheet softwares are used a lot because they allow users to manipulate data, organize it, and arrange it in any way they need. They are usually user-friendly and relatively easy to use. Most spreadsheets are able to be shared with others and have multiple people collaborate on the same page. This is also why spreadsheet softwares are used often by businesses and organizations.

Some examples of popular spreadsheet softwares are:

 * Google Sheets
 * Microsoft Excel
 * LibreOffice
 * Zoho
 * OpenOffice Calc
 * Smartsheet
 * Numbers

But why are spreadsheet softwares important?

They allow users to easily and efficiently organize, analyze, visualize, and manipulate data.

What are the main GUI elements of a software ?
In order to maintain clear interaction and communication with the user, software generally follows the WIMP (window, icon, menu, pointer) paradigm, using the following GUI elements of the user interface: - Windows: a resizable area of the screen that displays information and can be dragged around the desktop with a mouse cursor. Different applications' windows can appear to overlap, and closing these windows generally also halts its associated program.

- Menus: a (usually) collapsible display of different options that allow the user to perform different tasks.

- Icons: a small image that represents different objects that have tasks associated with them (a floppy disk for saving, for example).

- Controls (or widgets): display a collection of related items or actions related to a certain concept (see image), such as Insert for inserting different types of media into a document.

- Pointer: echoes the user's movements through a pointing device, such as a mouse or trackpad, and allows the user to directly interact with the program by clicking and dragging GUI elements.

license: Creative Commons - Attribution Share-Alike - https://creativecommons.org/licenses/by-sa/4.0/


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IB/Group 4/Computer Science/Computer Organisation/The Instruction Cycle Layer

What is a CPU ?
The CPU is the element in a computer that is responsible for processing and executing operations and instructions given by applications. This is done through registers, RAM, and ALUs. CPUs function similar to the brain of a computer and are present in every computer. CPUs are made from large amounts of transistors placed on chips that collectively perform operations to process instructions.

The rate at which CPUs can process information is known as their clock speed, which is measured in Hertz. Modern CPUs function at billions of Hertz meaning that they can run billions of operations per second.

CPUs can also have multiple "cores" which is the main element of the CPU. The number of cores that a CPU has, along with its clock speed, determines its operating speed. There is a wide range of core amounts that CPUs can have, with some CPUs having one core, and some having up to 256.

What is the fetch decode execute cycle ?
Before looking at how a computer does what it does, let us look at what it can do. The definition of a computer outlines its capabilities; a computer is an electronic device that can store, retrieve, and process data. Therefore, all of the instructions that we give to the computer relate to storing, retrieving, and processing data.

The underlying principle of the von Neumann machine is that data and instructions are stored in memory and treated alike. This means that instructions and data are both addressable. Instructions are stored in contiguous memory locations; data to be manipulated are stored together in a different part of memory. To start the Fetch-Execute Cycle, first of all the data is loaded to the main memory by the operating system, the address of the first instruction is placed onto the program counter.

The process cycle includes four steps:

 * 1) Fetch the next instruction,
 * 2) Decode the instruction
 * 3) Get data if needed,
 * 4) Execute the instruction.
 * 5) Store result of execution and check for next instruction.

Fetch the Next Instruction
The PC increments one by one to point to the next instruction to be executed, so the control unit goes to the address in the memory address register (MAR) which holds the address of the next instruction specified in the PC. Then it takes it to the main memory through the address bus and returns it to the memory buffer register via the data bus. The MBR is a two way register that temporarily holds data fetched from the Memory(cache or RAM), makes a copy of the contents, and places the copy in the IR. Now, the IR contains the instruction to be executed.

Before going to the next step in the cycle, the PC must be updated to hold the address of the next instruction to be executed when the current instruction has been completed. There after the instruction register is responsible for the instruction to be solved by the CU. The CU checks on the status of the instruction and then allows execution. Because the instructions are stored contiguously in memory, adding the number of bytes in the current instruction to the PC should put the address of the next instruction into the PC. Thus the control unit increments the PC. (It is possible that the PC may be changed later by the instruction being executed)

In the case of an instruction that must get additional data from memory, the ALU sends an address to the memory bus, and the memory responds by returning the value at that location. In some computers, data retrieved from memory may immediately participate in an arithmetic or logical operation. Other computers simply save the data returned by the memory into a register for processing by a subsequent instruction. At the end of execution, any result from the instruction may be saved either in registers or in memory.

Decode the Instruction
To execute the instruction in the instruction register, the control unit has to determine what instruction it is. It might be an instruction to access data from an input device, to send data to an output device, or to perform some operation on a data value. At this phase, the instruction is decoded into control signals. That is, the logic of the circuitry in the CPU determines which operation is to be executed. This step shows why a computer can execute only instructions that are expressed in its own machine language. The instructions themselves are literally built into the circuit.

For example, lets take an imaginary RAM with registers of 8 bits in the table below. In the 8 bits, the first 4 bits are what we use to determine the instruction.

For the 1 address: 01010010

0101 is our opcode. For our case, 0101 corresponds to "load", meaning we are loading the value from the address 00000010 to a register.

Example continued in "Execute the instruction".

Get Data If Needed
In most programs, the instruction to be executed may potentially require additional memory accesses to complete its task.

For example, if the instruction says to add the contents of a memory location to a register, the control unit must get the contents of the memory location.

Execute the Instruction
Once an instruction has been decoded and any operands (data) fetched, the control unit is ready to execute the instruction. Execution involves sending signals to the arithmetic/logic unit to carry out the processing. In the case of adding a number to a register, the operand is sent to the ALU and added to the contents of the register. When the execution is complete, the cycle begins again. If the last instruction was to add a value to the contents of a register, the next instruction probably says to store the results into a place in memory. However, the next instruction might be a control instruction—that is, an instruction that asks a question about the result of the last instruction and perhaps changes the contents of the program counter.

Hardware has changed dramatically in the last half-century, yet the von Neumann model remains the basis of most computers today. As Alan Perlis, a well-known computer scientist once said;

"Sometimes I think the only universal in the computing field is the Fetch-Execute Cycle."

- Alan Perlis, 1981.

Continuing with our example from above. We left off at where we read 0101's instruction from the instruction table.

After the decoding, we are executing the CPU. In our case, we are storing the value in the address 00000010 (2 in denary) to a register. So now in our register, we would have the value 2 in denary to use for later operations. When this instruction cycle is over, all the circuits will be turned off and a new instruction cycle will begin when the value in the Instruction address register is increased by 1.

What is a control unit ?
The Control Unit is the organising force in the computer, for it is in charge of the Fetch-Execute Cycle. There are two special registers in the control unit. The Instruction Register (IR) contains the instruction that is being executed, and the Program Counter (PC) contains the address of the next instruction to be executed. Because the ALU and the control unit work so closely together they are often thought of as one unit called the Central Processing Unit (CPU).

What is Random access Memory (RAM) ?
Random Access Memory (RAM) is a storage device that functions as storage, and can give instructions to the CPU. RAM is used for temporary storage for the CPU, and the data that the RAM holds will only be stored while the program needing it is running, or if the computer is Running. This means that ram is volatile (the data will be erased if it is powered off).

The speed of RAM is defined by the storage amount, clock speed, and latency. The clock speed is how many operations it can handle per second (in hertz), with modern computers being able to handle millions of operations per second. The latency is how long it takes for data to be written to RAM to be available to use. The storage amount is how much data the RAM can hold, with modern RAM sticks being able to hold Gigabytes of data (billions of bytes).

It also functions and read and write. Meaning memory can both be read and accessed.

What are instructions for the CPU ?
All CPUs come with an instruction set with associates many numbers, called opcodes, with different instructions. Instructions are read by the CPU from the RAM, where numbers are stored which have a certain number of bits reserved for opcodes and the rest dedicated to information on memory location.

Depending on how expansive a CPU's instruction set is, instructions can range from operations such as addition and division, to more complex logic tasks.

For example, the 8-bit instruction 00011100, which has opcode 0001, could mean, in the following case, to add the numbers at the register and at memory location 1100. The number 00110011 (opcode 0011) would then store the result in memory location 0011.

What is the MDR ?
The MDR, or Memory Data Register, temporarily stores data while it is being processed by the CPU, as an intermediary between the RAM and the CPU. It also temporarily holds data that is being placed in memory.

It can also be know as the MBR, or Memory Buffer Register.

What is the MAR ?
First off, MAR stands for Memory Address Register. It is a subcomponent of the CPU component, registers which holds the Program counter, the Current Instruction Register, Accumulator, the Memory Data Register, and the Memory Address Register.

It is essentially a storage unit that holds the memory address, where something is in the memory of the CPU, of data that needs to be accessed. It also holds the memory address of data that will be sent to that address via system bus(next chapter). The MAR works hand-in-hand with the MDR, Memory Data Register, which holds the actual data which was held at the memory address from the MAR.

What is a data bus and an address bus ?

In the diagram above all the parts are connected to one another by a collection of wires called a bus, through which data travels in the computer. Each bus carries three kinds of information; address, data, and control:

- An address is used to select the memory location or device to which data will go, or from which it will be taken.

- Data then flows over the bus between CPU, memory, and I/O Devices.

- The control information is used to manage the flow of addresses and data. For example, a control signal will typically be used to determine the direction in which the data is flowing either to or from the CPU.

The Bus Width is the number of bits that it can transfer simultaneously. The wider the bus, the more address or data bits it can move at once.

A widespread example of databus used billions of times every day is the 'Universal Serial Bus' aka USB. This bus, used to transfer data, charge your phone and power your electric pencil sharpener has been the standard on earth since 1996.

What is cache memory ?
Because memory accesses are very time consuming relative to the speed of the processor, many architectures provide Cache Memory. Cache memory is a small amount of fast-access memory into which copies of frequently used data are stored. Before a main memory access is made, the CPU checks whether the data is stored in the cache memory. Pipelining is another technique used to speed up the Fetch-Execute Cycle. This technique splits an instruction into smaller steps that can be overlapped.

There are 3 types of cache memory. L1 cache is the smallest but the fastest cache memory including data and instructions. L2 cache has bigger memory, but slower and is data only. L3 cache as the biggest memory but the slowest speed and is data only.

In a personal computer, the component in a von Neumann machine reside physically a printed circuit board called the Motherboard. The motherboard also has connections for attaching other devices to the bus, such as a mouse, a keyboard, or additional storage devices.

So what does it mean to say that a machine is an n-bit processor? The variable n usually refers to the number of bits in the CPU general registers: Two n-bit numbers can be added with a single instruction. It also can refer to the width of the bus, which is the size of the addressable memory—but not always. In addition, n can refer to the width of the data bus—but not always.

What is the Von Neumann Architecture ?
A major defining point in the history of computing was the realisation in 1944–1945 that data and instructions to manipulate data were logically the same and could be stored in the same place. The computer design built upon this principle, which became known as the von Neumann Architecture, is still the basis for computers today. Although the name honours John von Neumann, a brilliant mathematician who worked on the construction of the atomic bomb, the idea probably originated with J. Presper Echkert and John Mauchly, two other early pioneers who worked on the ENIAC at the Moore School at the University of Pennsylvania during the same time period.

Another major characteristic of the von Neumann architecture is that the units that process information are separate from the units that store information. This characteristic leads to the following components of the von Neumann architecture.

 * The memory unit that holds both data and instructions.
 * The arithmetic/logic gate unit that is capable of performing arithmetic and logic operations on data.
 * The input unit that moves data from the outside world into the computer.
 * The output unit that moves results from inside the computer to the outside world.
 * The control unit that acts as the stage unit to ensure that all the other components act in concert.

Memory, Process, and CPU Management
Recall that executing a program resides in main memory and its instructions are processed one after another in the fetch-decode-execute cycle. Multiprogramming is the technique of keeping multiple programs in main memory at the same time; these programs compete for access to the CPU so that they can do their work. All modern operating system employ multiprogramming to one degree or another. An operating system must therefore perform memory management to keep track of which programs are in memory and where in memory they reside.

Another key operating system concept is the idea of a process, which can be defined as a program in execution. A program is a static set of instructions. A process is a dynamic entity that represents the program while it is being executed. Through multiprogramming, a computer system might have many active processes at once. The operating system must manage these processes carefully. At any point in time a specific instruction may be the next to be executed. Intermediate values have been calculated. A process might be interrupted during its execution, so the operating system performs process management to carefully track the progress of a process and all of its intermediate states.

Related to the ideas of memory management and process management is the need for CPU scheduling, which determines which process in memory is executed by the CPU at any given point.

One must remember, however, that the OS itself is just a program that must be executed. Operating system processes must be managed and maintained in the main memory along with other system software and application programs. The OS executes on the same CPU as other programs, and it must take its turn among them.

The following sections (Single Contiguous Memory Management, Partition Memory Management, Paged Memory Management) are for interest purposes only. The Computer Science Guide clearly notes under 2.1.6 that "technical details are not needed. For example, memory management should be described but how this is handled in a multitasking environment is not expected." Therefore, these sections serve the purpose of illustrating memory management techniques and can be summarised rather than utilised in an exam.

Single Contiguous Memory Management
Has only the operating system and one other program in memory at one time. This is the most basic type of memory management.

Partition Memory Management
The memory is broken up into different parts. Has the operating system and any number of programs running at the same time through these different partitions. The partitions have a base and a bound register.

Base register Bounds register Partition selection First fit Best fit Worst fit
 * A register that holds the beginning address of the current partition (the one that is running)
 * A register that holds the length of the current partition
 * Allocate program to the first partition big enough to hold it
 * Allocated program to the smallest partition big enough to hold it
 * Allocate program to the largest partition big enough to hold it

Paged Memory Management
A technique in which processes are divided into fixed-size pages and stored in memory frames when loaded.

Frame Page
 * A fixed-size portion of main memory that holds a process page
 * A fixed-size portion of a process that is stored into a memory frame


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IB/Group 4/Computer Science/Computer Organisation/The Operating System Layer

What is an operating system (OS) and what are its main tasks ?
The OS, operating system, is a program that after being loaded manages the computer's memory, processes, software, and hardware. Essentially, the OS allows the user to communicate with the Computer without knowing the computer's language. There are different parts of the OS and the central part is called the Kernel. It has control over everything in the OS. It works as link between the hardware in the computer and the processing that run on it. It manages the correspondence between the two. It also coordinates the Computer's access to the CPU and the memory so that the computer is able to run multiple operations at once. It allows for memory allocation and the allocation of resources towards multiple programs so that the computer can run these processes all at the same time. For example, when the computer needs to print something, the CPU is not what would take care of that. The OS would send the documents to be printed it the "print queue" and would "talk" to the printer for the CPU.

The OS has many main tasks such as:

 * Memory management
 * Resource allocation and management monitoring
 * Peripherals and Device management
 * Networking
 * Security
 * User interface
 * Application interface

Describe the main functions of an operating system.
As early as the end of the first generation of software development, there was a split between those programmers who wrote tools to help other programmers and those who used to solve problems. Modern software can be divided into two categories, system software and application software, reflecting this separation of goals. Application Software is written to address specific needs — to solve problems in the real world. Word processing programs, games, inventory control systems, automobile diagnostic programs, and missile guidance programs are all application software.

System Software manages a computer system at a more fundamental level. It provides the tools and an environment in which application software can be created and run. System software often interacts directly with the hardware and provides more functionality than the hardware does itself.

The Operating System of a computer is the core of its system software. An operating system manages computer resources, such as memory, and input/output devices, and provides an interface through which a human can interact with the computer. Other system software supports specific application goals, such as a library or graphics software that renders images on a display. The operating system allows an application program to interact with these other system resources.

Memory Management
Memory management is a function in the OS (operating systems) that handles or manages primary memory and a single user operating system (a function that will only have one single user at any given time). It moves processes back and forth between main memory and disk during execution. Memory management keeps track of each and every memory location, regardless of either it is allocated to some process or it is free.

It checks how much memory is to be allocated to process; it decides which process will get memory at what time; it tracks whenever some memory gets freed or unallocated and correspondingly it updates the status. All of the above is done in the goal of achieving an efficient utilization of memory. Why is memory management important or necessary?

 * Allocate and deallocate memory before and after execution
 * To keep track of used memory space by processes.
 * To minimize fragmentation issues.
 * To proper utilization of main memory.
 * To maintain data integrity while executing of process.

Peripherals/device Management
A peripheral is an external hardware device that interacts with the OS, without being a core component of the computer. This means input and output devices, such as keyboards and mice for input, and a computer monitor or printer for output.

The OS must read the input and act on it, which usually means executing a set of instructions. It also is responsible of managing output devices, for instance queuing printing tasks for a printer.

The OS and peripherals interact through a driver, which "translates" data from the OS to the peripheral and back. Each peripheral has its own driver, and it differs depending on the OS.

Networking
Networking is the process of computer communicating and connecting between each other. Computers use common communication protocols over digital interconnections to communicate with each other.

Networking works using two components, Nodes and Links:

- Nodes are physical pieces of technology that allow for the communication between systems, these can be routers or a Modem.

- Links are how these Nodes communicated between each other, examples of these are:

- Wired using simple wires such as USBs or more complicated cables such as Ethernet cable/ Fiber Optic cables

- Wireless using free space that allows for wireless communication such as Bluetooth and Wifi

Key Terms for Networking are:

- Protocol which is a set of rules and standards that govern how data is transmitted over a network these include, TCP/IP, HTTP, and FTP.

- Topology refers to the physical and logical arrangement of nodes on a network. Examples of these are bus, star, ring, mesh, and tree.

- IP Addresses are how different devices can indentify themselves, each computer has a unique IP Address.

Security
Security can be provided by the OS using different methods:

- By monitoring what permissions certain applications have (what these applications have control over and what data they can access). For example, one wouldn't want their emails to be readily available to all applications they download, as this could lead to fake emails and theft of personal information.

- The OS should have the minimum amount of permissions and privileges to perform its function in order to avoid compromising the whole OS if one component is breached.

- The OS should have multiple layers of security: antivirus, authentication (username, password or passcode), firewall, encryption etc.

Input Output devices
All of the computing power in the world would not be useful if one could not input values into the calculations from the outside or report to the outside the results of said calculations. Input and output units are the channels through which the computer communicates with the outside world. An Input Unit is a device through which data and programs from the outside world are entered into the computer. The first input units interpreted holes punched on paper tape or cards. Modern-day input devices, however, include, but are not limited to; keyboards, mice, cameras (also known as, simply, webcams), and scanning devices.

An Output Unit is a device through which results stored in the computer memory are made available to the outside world. Examples include printers and screen monitors.

Peripheral devices refer to all hardware components that are connected / attached to the computer system but that are not part of the core computer architecture.

OS cannot interact with an exterior hardware device directly (there are always new ones coming out), therefore there is an intermediary called a device driver which is a type of software. Instead the device driver tells the OS what the peripheral device is and acts as a translator: the OS will send standard commands to the driver that will then translate them and drive them to the device.

A distinction can be made between input and output peripheral devices / units.

 * Input devices: feed data that has been converted into electrical binary signals into the computer’s CPU.
 * Example 1: Mouse. Data for a mouse would be the current mouse state (position of cursor, button state) which goes through the mouse driver that then informs the computer.
 * Example 2: Microphone. Data is sound translated into electrical signals and goes through an audio driver.

Note that for a laptop for example these drivers and peripherals are integrated into the computer.

 * Output devices: provides/displays data from the computer (outputs it).
 * Example: Printer. Printers receive the data from the printer driver and output it on a page. Note how in some cases you have to manually download your printer’s driver as it is not integrated into the computer
 * Input/Output devices: some devices can do both: touchscreens, storage drives


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Infrastructure Past, Present, and Future Casebook/Port Miami Tunnel

This page is for a case study on the Port Miami Tunnel, created by Xiyuan Tang, Yitong Zhou, and Yueying Cao. It is part of the GOVT 490-003 (Synthesis Seminar for Policy & Government) / CEIE 499-002 (Special Topics in Civil Engineering) class offered at George Mason University taught by Jonathon Gifford.

Summary
Port Miami Tunnel, located in Miami, Florida, is a vital transportation infrastructure project designed to improve connectivity and enhance traffic flow in and out of the Port Miami area. The tunnel was conceived to address the growing congestion and facilitate the movement of goods and people between the port and the surrounding areas.

Approved after decades of planning and discussion in December 2007, the project faced a temporary cancellation a year later. However, construction resumed, commencing in May 2010. Subsequently, the tunnel was opened to traffic on August 3, 2014.

On a typical weekday, nearly 16,000 vehicles commute to and from Port Miami via downtown streets, with truck traffic constituting 28 percent of this vehicular movement. Beyond facilitating expedited access for trucks and automobiles heading to the port, the Port Tunnel is strategically designed to optimize traffic flow in Downtown Miami.

The Port Miami Tunnel enhances accessibility to and from the Port, functioning as a dedicated roadway connector that links the Port with the MacArthur Causeway (State Road A1A) and I-395. This tunnel is accessible to all, catering to both cruise and cargo traffic.

History/Timeline

 * October 1981– M-D MPO Transportation Planning Committee (TPC) establishes POM Access Task Force.

 * March 21, 1991 – At joint Technical Advisory Committee (TAC)/Citizen Advisory Committee (CAC) meeting, members are informed that FDOT, FHWA, Port of Miami and City of Miami endorsed the preferred alternative, which makes  the tunnel a viable project with potential for implementation.

 * February 17, 2006 – FDOT issues a Request for Qualifications (RFQ) from proposers seeking to develop, design, construct, finance, operate and maintain the POMT project through a Concession Agreement.

 * October 4, 2007 – M-D BOCC agrees to fund a portion of project ($402.5 million) provided that the City of Miami also contributes a portion of the local funding.

 * December 13, 2007 – The City of Miami Commission agrees to fund a portion of project ($55 million).

 * February 15, 2008 – MAT is named the Best Value Proposer.

 * December 12, 2008 – FDOT announces that an agreement with MAT will not be reached due to financial difficulties.

 * April 16, 2009 – FDOT announces plans to continue procurement process.

 * May 8, 2009 – FDOT authorizes replacement of Babcock & Brown with Meridiam Infrastructure as the MAT equity partner.

 * June 2, 2009 – FDOT reaches Commercial Close with MAT consortium.

 * October 15, 2009 – FDOT reaches Financial Close with Miami Access Tunnel (MAT) and issues Notice to Proceed for 55 month Design and Construction schedule.

 * May 24, 2010 – Florida Department of Transportation (FDOT) issues Notice to Proceed 2, allowing the contractor, Bouygues Civil Works Florida (BCWF), to begin construction.

 * July 31, 2012 - Mining of the Eastbound Tunnel was completed as the Tunnel Boring Machine broke out on Dodge island (PortMiami).

 * May 6, 2013 - Mining of the Westbound Tunnel was completed as the Tunnel Boring Machine broke out on Watson Island.

 * August 3, 2014-The Tunnel was opened to traffic.

Funding and Financing
=== Funding sources === Total Eligible project cost - $1,072.9 million

 * Senior Bank debt - $341.5 million

Provided by  BNP Paribas, Banco Bilbao Bizcaya Argentina, RBS Citizens, Banco Santander, Bayerische Hypo, Calyon, Dexia, ING Capital, Societe Generale, and WestLB.

 * TIFIA Loan - $341 million

Federal Highway Administration' s (FHWA) approval of the TIFIA loan was contingent on the provision and approval of financing from the City of Miami and Miami-Dade County.

 * Equity contribution - $80.3 million (private)

MAT Concessionaire LLC

□ Meridiam Infrastructure Finance SARL (Luxembourg) provides 89.8 percent of project equity through Meridiam Infrastructure Miami, LLC. (90% equity partner)

□ Bouygues Travaux Public S.A. provides 10.2 percent equity contribution through Dragages Concession Florida, Inc. (10%equity partner)

 * FDOT Milestone Payment during construction - $100 million
 * FDOT Development Fund - $209.8 million

Availability Payment
Besides the $100 million milestone payments during the construction period between 2010 and 2013, FDOT paid MAT  a $350 million final acceptance payment upon construction completion.

The concession for the tunnel was structured under an availability payment model, under which the concessionaire would receive ongoing payments over the life of the concession covering capital and maintenance costs. The Maximum Annual Availability Payment is $32.5 million (2009 dollars) The payment is  based on the availability of the road  Deductions are made from this amount if MAT's operation of the facility does not meet prescribed performance standards.

30 years of availability payments during the operating period comes from a combination of federal and state funds. Responsibility for covering these payments is based on a roughly 50/50 distribution between FDOT and the local public agencies. FDOT will provide an estimated $457 million, which will be paid from its annual budget. Miami-Dade County is providing an estimated $402 million. To complete the funding for the project, the City of Miami has agreed to contribute $50.0 million, which is being financed through a Letter of Credit.

Legal Foundations
In 1991, the Florida Legislature, recognizing the public need for “rapid construction of safe and efficient transportation facilities”, enacted Florida Statute§334.30. The legislation was subsequently amended several times over the next twenty years.

With the legislation final amendment in 2004,  FDOT was granted comprehensive authority, with legislative approval, to enter into agreements with private entities to build, operate, own or finance transportation facilities. The 2004 amended version of §334.30 established the following guidelines for PPP contracts: (i) permitted the receipt of solicited and unsolicited proposals; (ii) allowed reimbursements to the private sector through the Toll Facilities Revolving Trust Fund; (iii) refined the guidelines for toll rate setting; (iv) encouraged revenue sharing between the private sector and FDOT; (v) allowed FDOT to use a combination of funding sources for project development, including federal funds; and (vi) limited PPP contracts to 50-years.

In addition, the bill also requires that no more than 15% of the total annual state and federal funds in the State Transportation Trust Fund be allocated for P3 projects. FDOT is required to submit the P3 into either its five-year work plan, or, in cases of projects of more than $500 million dollars, the 10-year strategic intermodal system plan.

Florida Department of Transportation (FDOT)
On the Port of Miami Tunnel project, FDOT is the project’s Grantor and will be entering into a concession agreement throughout an undetermined (approximately 30-50 years) amount of time.

The Miami Access Tunnel (MAT) Concessionaire LLC,
Comprised of Bouygues Travaux Publics (France), S.A. Babcock & Brown Infrastructure Group (Australia), and Canadian financing partners (Minnesota Department of Transportation )

Responsible for the design, finance, building, operation and maintenance of the Port of Miami Tunnel in conjunction with FDOT.

Narrative of the Case
The Florida Department of Transportation District 6 (FDOT D6) began a study in 1987 for a master plan to improve the traffic circulation and congestions between the Port of Miami and downtown Miami, FL. This sudy included a tunnel connection between two man-made islands, the Watson and the Dodge islands. Though a finding of no significant impact was completed in 1992, the project remained on hold for about 10 years.

In 2003, Florida's Turnpike Enterprise (FTE) started POMT Re-evaluation Study to update project documents based on present conditions and examine construction methods for preferred alternative selected in original (Project Design & Environmental Study)

In 2005, the FDOT D6 regained its charge over the project and concluded that a bored tunnel under Biscayne Bay was feasible.

Pre-construction analyses identified the significant potential risk associated with the tunnel, as a bored tunnel of that size had never been constructed in the U.S. As a result, FDOT began to explore the possibility of developing the Port of Miami Tunnel as a P3 in order to mitigate the state's risk exposure, drawing on Florida's recently strengthened P3 enabling legislation. Discussions with potential bidders regarding this approach were also positive, leading FDOT to initiate procurement of the project as a DBFOM concession in February 2006.

In May 2007, FDOT announced its intent to award the concession to MAT, comprised of the Australian investment firm Babcock and Brown and the French construction firm Bouyges, a subsidiary of which would serve as the lead contractor on the project. Once funding commitments from the state, county, and city partners were finalized, a formal award was made in February 2008. However, financing for the project soon became caught up in the market turmoil of that year, which would see the failure of both Babcock and Brown and Lehman Brothers, its underwriter for the project. In late 2008, Meridiam replaced Babcock and Brown as the primary equity partner in the concession.

Unpredictable Geotechnical Conditions
Due to the highly porous and inherently unpredictable geology beneath Biscayne Bay, the Port of Miami Tunnel project poses a significant challenge even for the most experienced tunneling contractors. The unforeseeable ground conditions are likely to result in delays and cost overruns. The final ground model from the ground investigation of the Port of Miami Tunnel indicates the presence of weak, highly porous Key Largo coralline limestone in Layer S7. This led to disputes over the additional costs for pumping extra concrete (i.e., grouting) to allow tunneling to continue. It is evident that FDOT cannot bear this risk alone, and if it were to transfer all the risks of geotechnical condition changes to the private sector, either no one would bid or bid prices would skyrocket.

To address these issues, a $180 million geotechnical contingency fund was established as part of the PPP contract to to mitigate extra work costs and delay costs arising out of changed geotechnical conditions during construction.

The risk of increased tunneling cost was therefore shared. The distribution of this fund is as follows: the first $10 million is borne solely by the concessionaire, the next $150 million is borne solely by the FDOT, and the last $20 million is borne solely by the concessionaire. Extra work costs and delay costs for changed geotechnical conditions that exceed $180 million are considered extraordinary geotechnical losses. If the USD $180 million fund is exhausted, the parties would have the right to terminate the contract.

Finance challenge
The project was tendered during the most severe period of the global financial crisis. Prior to finalizing financing, Babcock and Brown, which had committed to providing 90% equity, filed for bankruptcy. As a result, it was unable to meet its cash obligations or secure financing. Initially, FDOT considered either reprocuring or canceling the project altogether. To prevent the project from being reprocured and to limit further delays, local and state elected officials lobbied FDOT to allow another company to replace Babcock & Brown as the 90% equity partner in the MAT consortium. Subsequently, Meridiam joined the consortium as the primary equity investor, replacing Babcock and Brown, and completed financial settlement with the project company, MAT Concessionaire, LLC, in 2009.

The economic crisis not only impacted private partners but also had significant effects on City of Miami and Miami-Dade County. During the economic downturn, real estate values plummeted, economic activity declined substantially, leading to a decrease in property and sales tax revenues, severely impacting the Miami metropolitan area. Both the City of Miami and Miami-Dade County faced difficulties in fulfilling their financial commitments. At the time of financial closure, the City of Miami was trying to offset a $118 million deficit, thus delaying the approval of a $50 million letter of credit intended for project funding. Although the City of Miami's financial commitment was approved in December 2007, a second approval was required before September 25, 2009. Specifically, approval of the city and county's financial commitments was a condition for the TIFIA loan. The extension of the financing deadline allowed the project to proceed, and the City of Miami approved the project's letter of credit on October 8, 2009. Financing was completed on October 15, 2009. Miami-Dade County initially needed to provide $600 million for the project. This amount was calculated based on the estimated project cost of $1.2 billion, split evenly with the U.S. Department of Transportation. In 2006, the county developed a financing plan of approximately $489 million. As part of this plan, the county explored the possibility of tunnel tolls. However, the cruise industry at the Port of Miami opposed this tolling method, as it would increase both their employees' actual costs and an additional fee per cruise ticket for customers. After the estimated total project cost was reduced to $900 million, the county's contribution was reduced to $402 million.

Lessons Learned/Takeaways
The POMT was the second availability payment P3 project to reach financial close in the United States. It is innovative in several aspects, providing valuable lessons for the construction industry at large and the PPP market in particular.

Risk allocation is a key focus. In general, the Availability Payment scheme will emphasize transferring sufficient risk， including significant construction and operating risk, to the Concessionaire and discouraging non-performance. All risks not expressly assumed in part or whole by FDOT are assumed by the Concessionaire. In addition, FDOT recognizes the unique nature of the Project’s geotechnical risk and the need to allocate it appropriately between FDOT and the Concessionaire. While in many PPP projects involving construction, most of the construction risks are allocated to the construction contractor, tunnel projects may entail particularly high risks related to unforeseen ground conditions, delays, and cost overruns. The upfront consideration of significant construction and financial risks through the establishment of a contingency fund enabled a satisfactory outcome when these risks materialized during the construction period. In this project, risks that were beyond the control of either party were shared, which had a positive impact on the working relationship between the parties. It ensured a fair and optimized risk allocation and helped maintain a positive relationship between the parties.

Government support and cooperation between different levels of government are also critical for large projects like POMT. This support and cooperation began in the project structuring phase, where funding was provided by federal, state, county, and city sources, with the City of Miami also granting land access. Given the decision not to charge tolls, ongoing funding from government departments is crucial. Joint funding, continuous involvement, and political support from the four different levels of government (federal, state, county, and city) have helped overcome challenges during construction.

Discussion Questions

 * 1) What are the advantages and disadvantages of public-private partnerships for infrastructure projects? In what cases does this model work better?
 * 2) How does the availability payment model in public-private partnerships affect project financing and operations? How does this model incentivize the private sector to provide long-term reliable infrastructure services?
 * 3) Do you think the current public-private partnership model based on risk allocation needs to be improved in the future? Or can the PPP mode such as the Port of Miami Tunnel continue to be used?


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Cookbook:Simple Boiled Chickpeas

Dried chickpeas are fairly easy to prepare, if you allow enough time, and they taste far better than the canned version.

Ingredients

 * 2 cups dried chickpeas
 * 4 stalks celery, chopped

Procedure

 * 1) Cover the chickpeas completely with water, and let them soak overnight. Drain the chickpeas.
 * 2) Combine the chickpeas and celery in a pot. Add enough water to completely cover the contents by a few inches.
 * 3) Bring the pot to a simmer over medium heat. Cook for about 2 hours until the chickpeas are tender—the cooking time is not an exact science, and you will need to bite into a chickpea to see if it is fully cooked.
 * 4) Once the chickpeas are done, drain the cooking liquid. If desired, you can reserve it to use as aquafaba.
 * 5) Use the cooked chickpeas as you would canned chickpeas. Alternatively, you can season them with salt, pepper, and a dash of olive oil and vinegar if you would like to eat them plain.

title: Cookbook:Simple Boiled Chickpeas


text: Category:Chickpea flour recipes

title: Category:Chickpea flour recipes


text:
Talk:Saylor.org's Ancient Civilizations of the World/The Songhay Kingdom

Social status of the Songhai empire
Songhai empire Zamile Mbhele (discuss • contribs) 10:59, 9 March 2024 (UTC)


text:
Czech/Nouns/Case/Nominative

=Nominative Case in Czech (1st)=

The nominative case is the base form, and the form you will find in the dictionary. It is used as the subject, with some other verbs and after the preposition než "than".

Declension

 * Group 1:
 * M: nouns whose nom/sg end in a consonant without haček (doktor/hrad)
 * F: nouns ending in -a
 * N: nouns ending in -o
 * Group 2 (soft ending):
 * M: nouns ending in a consonant with haček, -e,/ě -c, -j, -tel
 * Group 3:
 * M: nouns whose nom/sg end in -a
 * F: nouns ending in -st
 * N: nouns ending in -í

Used as the subject

 *  Káva je horká –  The coffee is hot.

The subject in Czech may not be translated as the subject in other languages

 *  Kino se bratrovi líbí –  My brother likes the cinema. (lit: Cinema pleases my brother.)

Used as the complement of the copula být "be"

 * Muj kolega je učitel  – My colleague is a teacher.

After the verbs jmenuje se and znamenat

 * jemenuje se – be named
 * Muj kolega se jmenuje František  –  My colleague is named Frantisek.
 * znamenat – mean
 * Co znamena auto  – What does auto (car) mean?

After Prepositions

 * než – than
 * Doktor je vyšší než turista . –  The doctor is taller than the tourist.

= References =

title: Czech/Nouns/Case/Nominative


text:
Cherokee/Inflection Tree

The inflection tree shows the possible inflections for the general Cherokee verb, first branching out at the selection of the stem. There are up to (and typically exactly) five possible stems for each verb, which should be memorized for each verb. More detail on this can be found on other pages. [Note: provide specific link.] The stem options are indicated as the bold headings followed by Roman numeral identifiers in parentheses. Below each stem are listed its subsequent options for inflection.

Present (I)
Present (Continuous)

Completive (II)
(Remote) Past

 * Experienced
 * Non-Experienced

Future Imperative

Absolute Future (including Certain Imperative)

Future

Future Perfect

Various Derivational Inflections

Actual/Normal DVB (vvqi) Nominalization (Type CMP) (BMA 459 but doesn't recognize tonic): Resultative Noun or Adjective (tonic)

"Perfect Nominal" (u/judoorange123, BMA 459 but fails to distinguish from actual/normal DVB nominalization) (-vvhi/-vvqi, SH and atonic)

Incompletive (III)
Habitual

(Remote) Past Progressive

 * Experienced
 * Non-Experienced

Absolute Future (including Certain Imperative)

Future Progressive

Agentive Noun (with NOM and SH)

 * Subtype (Uchihara 365): General Nominalization (without SH)

Actual/Normal DVB (vvqi) Nominalization (Type INC): Action Noun (SH, tonic)

Immediate (IV)
Present Imperative

Immediate Past

Irrealis Immediate Future

Infinitive (V)
NOM

 * Predicative (bare usage): "for you to drink"
 * Obligatory (with superhigh)
 * Instrumental Noun (with SH) (including DVN-CAU-NOM (BMA 461))
 * Subtype (Uchihara 365): General Nominalization (without SH)

NOM2

 * Infinitive (including Potential usage): "your singing"
 * Location Noun

DVB?? (which one? see tonicity) ??? does this exist as BMA passingly declared?

title: Cherokee/Inflection Tree


text:
Cherokee/Learning Tips

Below are some tips to keep in mind when learning Cherokee.

General Tips

 * Spaced repetition is the key to memorization. Look into it.
 * Not all verbs and inflections occur with equal frequency. Follow the progression of the course to learn the most common verbs and even memorize specific inflections if they occur frequently. This will more rapidly build up your knowledge to the point where you have enough words to experiment with new sentence structures and to have fun expressing your thoughts and feelings.

Cherokee-Specific Tips

 * Imperative and immediate past forms seem to be more psychologically fundamental than many indicative forms, even including the present continuous depending on whom you ask. As such, it is advisable to drill the immediate (IV) stem of each verb to the point of solid internalization. In other words, this stem is arguably the most important of the five, so make sure you know it comfortably!
 * Some tone processes are more important than others. The rank from most to least important is as such: Pronominal Tonic Lowering > Laryngeal Alternation > H1 > H3 > H2.

title: Cherokee/Learning Tips


text: Category:Content-related policies

title: Category:Content-related policies


text: Category:Administrative policies

title: Category:Administrative policies


text: Category:Behavioral policies

title: Category:Behavioral policies


text: Programming:Forth:Command Reference

title: Programming:Forth:Command Reference


text: Forth/Command Reference

title: Forth/Command Reference


text:
User talk:105.112.114.245

March 2024
MathXplore (discuss • contribs) 07:40, 10 March 2024 (UTC)

title: User talk:105.112.114.245


text:
User talk:2405:ACC0:1207:4D1B:88B4:69B7:6EA5:44A8

--SHB2000 (discuss • contribs) 11:40, 10 March 2024 (UTC)


text:
Wikibooks:Requests for permissions/refcanimm

(wikibooks administrator)
I have been editing the book Canadian Refugee Procedure for some years. I would like to have the permissions necessary to delete some old orphaned pages on the book.
 * I'm not sure about permanent adminship since you don't seem to be particularly active in the community (i.e. discussions, etc) as far as I can see. Perhaps temporary adminship would be more appropriate, and the scope would be limited to deleting pages in the specific book? In the meantime, you're welcome to flag pages for speedy deletion if they meet the criteria! —Kittycataclysm (discuss • contribs) 13:23, 29 November 2023 (UTC)
 * I'm opposed to this. Adminship cannot be limited to just deleting pages and just from a particular book. I'd expect to see an interest an understanding of all aspects of adminship before supporting. MarcGarver (discuss • contribs) 16:22, 29 November 2023 (UTC)
 * @MarcGarver these are fair points. I am noticing, though, that the policy does technically say that you can grant temporary adminship "to perform specialist tasks" and that this right can be immediately revoked without discussion if there is evidence that disallowed actions are taking place. In terms of precedent, I was previously granted temporary adminship in early 2023, which I used at the time only to address persistent vandalism. But, I do see the concern, and I am definitely hesitant to grant any administrative powers to someone who isn't a more widely active community presence. —Kittycataclysm (discuss • contribs) 19:45, 29 November 2023 (UTC)

 * per MarcGarver. There is a lot more to adminship than merely deleting pages from a singular book. --SHB2000 (discuss • contribs) 04:28, 30 November 2023 (UTC)
 * Unlike some of the others, I think it's OK to consider temp adminship to a user that mainly works on one book, when there is a good reason for requesting that right. However, I'm not seeing that here. I see only about 15-20 entries in your deleted user contributions page, and only a couple from this year. As Kittycataclym says, you can easily flag pages for deletion. If there's something specific you'd like to do that requires admin rights that I'm missing, let us know. Also BTW: the reviewer right that you have is actually generous on what you can do - you can move pages without a redirect for example. Leaderboard (discuss • contribs) 09:44, 1 December 2023 (UTC)


text:
Wikibooks:Requests for permissions/Adamvialsmoore

(wikibooks reviewer)
I'm the main coordinator of the ORCID Advocacy toolkit and would appreciate reviewer rights to be able to clean up after writing sprints, such as the one running this week - the contribution runs in fits and starts so I'm not sure when I'll hit the auto reviewer criteria — Preceding unsigned comment added by Adamvialsmoore (talk • contribs) 16:55, November 30, 2023 (UTC)
 * You don't usually need reviewer rights to clean up content. Is there anyting very niche that you would like to do with the reviewer rights, such as rollback or the ability to accept or decline edits, that I'm missing here? --SHB2000 (discuss • contribs) 07:01, 1 December 2023 (UTC)

 * Sorry - way too busy - basically on the book we have this showing at the top of pages
 * The latest reviewed version was checked on 18 November 2022. There are 31 pending changes awaiting review.
 * And I'd like to be able to review, accept and ensure the work is up to date for when we actually do advocacy for the advocacy toolkit ;) Adamvialsmoore (discuss • contribs) 12:53, 15 December 2023 (UTC)


text:
User talk:2605:BA00:A128:697:496A:90B0:5304:A3A7

March 2024
MathXplore (discuss • contribs) 01:45, 11 March 2024 (UTC)


text:
User talk:41.116.12.181

March 2024
MathXplore (discuss • contribs) 05:31, 11 March 2024 (UTC)

title: User talk:41.116.12.181


text: Template:IB/Exercise

title: Template:IB/Exercise


text:
User talk:168.121.86.183

March 2024
MathXplore (discuss • contribs) 12:55, 11 March 2024 (UTC)

title: User talk:168.121.86.183


text:
User talk:90.249.23.185

March 2024
MathXplore (discuss • contribs) 12:56, 11 March 2024 (UTC)

title: User talk:90.249.23.185


text:
User talk:2409:4072:6E8F:E437:0:0:2F0B:6506

March 2024
MathXplore (discuss • contribs) 13:13, 11 March 2024 (UTC)