content: -- This file has been generated by specsgen. Do not modify by hand!
  
  module Unison.Target.ARM.SpecsGen.ARMRegisterClassDecl
         (ARMRegisterClass(..)) where
   
  data ARMRegisterClass = ALL
                        | CCR
                        | CRS
                        | CS
                        | CSH
                        | CSL
                        | DPR
                        | DPR_8
                        | DPR_VFP2
                        | DPair
                        | F32
                        | FCRS
                        | FCS
                        | GPR
                        | GPRPairOp
                        | GPRnopc
                        | GPRsp
                        | GPRwithAPSR
                        | M128
                        | M32
                        | M32t
                        | M512
                        | M64
                        | QPR
                        | QQPR
                        | QQQQPR
                        | RM32
                        | RM64
                        | SPR
                        | Unknown
                        | VecListDPair
                        | VecListDPairAllLanes
                        | VecListDPairSpaced
                        | VecListDPairSpacedAllLanes
                        | VecListFourD
                        | VecListFourDAllLanes
                        | VecListFourQ
                        | VecListFourQAllLanes
                        | VecListOneD
                        | VecListOneDAllLanes
                        | VecListThreeD
                        | VecListThreeDAllLanes
                        | VecListThreeQ
                        | VecListThreeQAllLanes
                        | Ptr_rc
                        | RGPR
                        | TGPR
                        | TcGPR
                        deriving (Eq, Ord, Read, Show)
  
  