content: -- This file has been generated by specsgen. Do not modify by hand!
  
  module Unison.Target.Mips.SpecsGen.MipsRegisterClassDecl
         (MipsRegisterClass(..)) where
   
  data MipsRegisterClass = ACC128
                         | ACC64
                         | ACC64DSP
                         | ACC64DSPOpnd
                         | AFGR64
                         | AFGR64Opnd
                         | AFGR_D09
                         | CCROpnd
                         | COP0Opnd
                         | COP2Opnd
                         | COP3Opnd
                         | CPU16Regs
                         | CPU16RegsPlusSP
                         | CPUSPReg
                         | DSPCC
                         | DSPROpnd
                         | FCCRegsOpnd
                         | FGR32
                         | FGR32Opnd
                         | FGR64
                         | FGR64Opnd
                         | FGRCCOpnd
                         | GPR32
                         | GPR32Opnd
                         | GPR64
                         | GPR64Opnd
                         | GPRMM16
                         | GPRMM16Opnd
                         | GPRMM16OpndMoveP
                         | GPRMM16OpndZero
                         | GPR_ATT7
                         | GPR_FPRA
                         | GPR_T89
                         | HI32DSPOpnd
                         | HWRegsOpnd
                         | LO32DSPOpnd
                         | MSA128B
                         | MSA128BOpnd
                         | MSA128CROpnd
                         | MSA128D
                         | MSA128DOpnd
                         | MSA128H
                         | MSA128HOpnd
                         | MSA128W
                         | MSA128WOpnd
                         | RM32
                         | RM64
                         | M32
                         | M64
                         deriving (Eq, Ord, Read, Show)
  
  