content: 
  [meta]
  # Name of the ISA/extension
  name = "My sample RISC-V extension"
  # ISA letter code, use Z for non one-letter names
  code = "Zhelp"
  # Version on the specification document this is based on
  spec = "Help spec 1.0"
  # Required base ISAs
  #requires = ["RV32I"]
  
  [consts]
  # these will be substituted in where numbers are expected and strings are provided
  EVERYTHING = 42 
  
  [registers]
  [registers.names]
  # Reg# = Array(Name, [Optional ABI Name], [Optional extra parsed names])
  45 = ["x45" , "ufhr", "ufhd"]
  46 = ["x46" , "ufr", "ufd"]
  
  [registers.lengths]
  # Reg# = Reg size in bits
  45 = "XLEN"
  46 = 128
  
  [instruction_formats]
  # [instruction_formats.Format_Name]
  [instruction_formats.R]
  # Field name = { type = "value/register", length = <total field size in bits>, encoding = [[vlast,vfirst,ifirst],... }
  # Encoding: copies [vlast:vfirst] (inclusive ranges) bits from value
  # as [ifirst+vlast-vfirst:ifirst] bits of the encoded instruction
  # Can specify multiple copies for multiple sub-fields encoding the same value
  opcode = { type = "value", length = 7, encoding = [[6,0,0]] }
  
  [instruction_formats.U]
  opcode = { type = "value", length = 7, encoding = [[6,0,0]] }
  rd = { type = "register", length = 5, encoding = [[4,0,7]] }
  imm = { type = "value", length = 32, encoding = [[31,12,12]] }
  
  [instructions]
  # [instructions.<name>]
  [instructions.lui]
  # One of the instruction formats defined above
  format = "U"
  # Fields of the format in order as they appear as arguments
  args = ["rd", "imm"]
  # Fields that are set to a constant value
  fields = { opcode = 0b0110111 }
  # All bits of the instruction should be covered by args and fields keys above combined
  