ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile
  Hardware Development
The growing demand for Domain-Specific Architecture (DSA) has driven the
development of Agile Hardware Development Methodology (AHDM). Hardware
Construction Language (HCL) like Chisel offers high-level abstraction features,
making it an ideal language for HCL-Based AHDM. While Large Language Models
(LLMs) excel in code generation tasks, they still face challenges with Chisel
generation, particularly regarding syntax correctness and design variability.
Recent reasoning models have significantly enhanced code generation
capabilities through test-time scaling techniques. However, we found that
reasoning models without domain adaptation cannot bring substantial benefits to
Chisel code generation tasks. This paper presents ChiseLLM, a solution
comprising data processing and transformation, prompt-guided reasoning trace
synthesis, and domain-adapted model training. We constructed high-quality
datasets from public RTL code resources and guided the model to adopt
structured thinking patterns through prompt enhancement methods. Experiments
demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax
correctness by 18.85% and 26.32% respectively over base models, while
increasing variability design ability by 47.58% compared to baseline reasoning
models. Our datasets and models are publicly available, providing
high-performance, cost-effective models for HCL-Based AHDM, and offering an
effective baseline for future research. Github repository:
https://github.com/observerw/ChiseLLM
68103c25ac29b7d5a594a328
Bowei Wang
claimed_verified
2025-04-29T08:02:03.650Z
65dde9628ad379149e34cf4a
https://cdn-avatars.huggingface.co/v1/production/uploads/65dde9628ad379149e34cf4a/nbqXb69RaXPbV3QWKbO4-.jpeg
Wang Bowei
user
observerw
68103c25ac29b7d5a594a329
Jiaran Gao
admin_assigned
2025-04-29T12:28:59.238Z
66c9d390315af068a9071fa0
/avatars/15add3443b341393e42626a935a44efd.svg
高佳然
user
gaojiaran
68103c25ac29b7d5a594a32a
Yelai Feng
extracted_confirmed
2025-04-29T02:44:46.525Z
67aaeba30c84099218b58563
/avatars/400a231fb9bc98a57b065137547b6600.svg
xiuranli
user
xiuranli
68103c25ac29b7d5a594a32b
Renzhi Chen
68103c25ac29b7d5a594a32c
Shanshan Li
admin_assigned
2025-04-29T12:29:13.085Z
672d2c36b159088122d1b8f2
/avatars/2e645597b2883fba6d25370d30cc5223.svg
shanshan Li
user
shanshanLi
68103c25ac29b7d5a594a32d
Lei Wang
ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile
  Hardware Development
The growing demand for Domain-Specific Architecture (DSA) has driven the
development of Agile Hardware Development Methodology (AHDM). Hardware
Construction Language (HCL) like Chisel offers high-level abstraction features,
making it an ideal language for HCL-Based AHDM. While Large Language Models
(LLMs) excel in code generation tasks, they still face challenges with Chisel
generation, particularly regarding syntax correctness and design variability.
Recent reasoning models have significantly enhanced code generation
capabilities through test-time scaling techniques. However, we found that
reasoning models without domain adaptation cannot bring substantial benefits to
Chisel code generation tasks. This paper presents ChiseLLM, a solution
comprising data processing and transformation, prompt-guided reasoning trace
synthesis, and domain-adapted model training. We constructed high-quality
datasets from public RTL code resources and guided the model to adopt
structured thinking patterns through prompt enhancement methods. Experiments
demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax
correctness by 18.85% and 26.32% respectively over base models, while
increasing variability design ability by 47.58% compared to baseline reasoning
models. Our datasets and models are publicly available, providing
high-performance, cost-effective models for HCL-Based AHDM, and offering an
effective baseline for future research. Github repository:
https://github.com/observerw/ChiseLLM
ChiseLLM, an enhanced domain-adapted reasoning model, improves Chisel code generation by enhancing syntax correctness and design variability in Hardware Construction Languages.
Domain-Specific Architecture (DSA) Agile Hardware Development Methodology (AHDM) Hardware Construction Language (HCL) Chisel Large Language Models (LLMs) domain adaptation reasoning trace synthesis RTL code structured thinking patterns