FPGA Implementationof Secret Communication with VHDL
In this paper the authors present a communication of data secretly using AES algorithm i.e. they first send the data (plain text) and the key which is of 64 bit into the encryption process. The output of this process will be cipher text. This cipher text is then fed into the decryption process and then the data (plain text) is got as output. In this paper they add the key and shuffle the data it is very hard for the unknown person to find out the original data. Since for each key there will be a change in the cipher text and so the person has to know the key in order to find out the original data.
Provided by: Creative Commons Topic: Hardware Date Added: Oct 2012 Format: PDF