When you perform BST, you can test pin connections without using physical test probes and capture functional data during normal operation. The boundary-scan cells (BSCs) in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the BSCs. Captured data is serially shifted out and externally compared to expected results.
|TDI||Serial input pin for:
|TDO||Serial output pin for:
|TMS||Input pin that provides the control signal to determine the transitions of the TAP controller state machine.||
|TCK||The clock input to the BST circuitry.||—|
All the JTAG pins are powered by the VCCIO 1B. In JTAG mode, the I/O pins support the LVTTL/LVCMOS 3.3-1.5V standards.
The JTAG BST circuitry requires the following registers:
- Instruction register—determines which action to perform and which data register to access.
- Bypass register (1-bit long data register)—provides a minimum-length serial path between the TDI and TDO pins.
- Boundary-scan register—shift register composed of all the BSCs of the device.
- Test access port (TAP) controller—controls the JTAG BST.
- TMS and TCK pins—operate the TAP controller.
- TDI and TDO pins—provide the serial path for the data registers.
- The TDI pin also provides data to the instruction register to generate the control logic for the data registers.
The MAX® 10 3-bit BSC contains the following registers:
- Capture registers—connect to internal device data through OUTJ, OEJ, and PIN_IN signals.
- Update registers—connect to external data through PIN_OUT and PIN_OE signals.
The TAP controller generates the global control signals internally for the JTAG BST registers, shift, clock, and update. The instruction register generates the MODE signal.
The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial data out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.
|Output Capture Register||OE Capture Register||Input Capture Register||Output Update Register||OE Update Register||Input Update Register|
|Version (4 Bits)||Part Number (16 Bits)||Manufacturer Identity (11 Bits)||LSB (1 Bit)|
|Single-supply||10M02||0000||0011 0001 1000 0001||000 0110 1110||1|
|10M04||0000||0011 0001 1000 1010||000 0110 1110||1|
|10M08||0000||0011 0001 1000 0010||000 0110 1110||1|
|10M16||0000||0011 0001 1000 0011||000 0110 1110||1|
|10M25||0000||0011 0001 1000 0100||000 0110 1110||1|
|10M40||0000||0011 0001 1000 1101||000 0110 1110||1|
|10M50||0000||0011 0001 1000 0101||000 0110 1110||1|
|Dual-supply||10M02||0000||0011 0001 0000 0001||000 0110 1110||1|
|10M04||0000||0011 0001 0000 1010||000 0110 1110||1|
|10M08||0000||0011 0001 0000 0010||000 0110 1110||1|
|10M16||0000||0011 0001 0000 0011||000 0110 1110||1|
|10M25||0000||0011 0001 0000 0100||000 0110 1110||1|
|10M40||0000||0011 0001 0000 1101||000 0110 1110||1|
|10M50||0000||0011 0001 0000 0101||000 0110 1110||1|
- 10 0100 0000
- 10 0011 0000
- 10 1110 0000
- 10 0011 0001
|Instruction Name||Instruction Binary||Description|
|SAMPLE/PRELOAD||00 0000 0101||
|EXTEST 1||00 0000 1111||
|BYPASS||11 1111 1111||
|USERCODE||00 0000 0111||
|IDCODE||00 0000 0110||
|HIGHZ 1||00 0000 1011||
|CLAMP 1||00 0000 1010||
|USER0||00 0000 1100||
|USER1||00 0000 1110||
The TDO pin of a device drives out at the voltage level according to the VCCIO of the device. The devices can interface with each other although the devices may have different VCCIO levels.
For example, a device with 3.3-V VCCIO can drive to a device with 5.0-V VCCIO because 3.3 V meets the minimum VIH on transistor-to-transistor logic (TTL)-level input for the 5.0-V VCCIO device.
MAX® 10 devices can support 1.5-, 1.8-, 2.5-, or 3.3-V input levels, depending on the VCCIO voltage of I/O Bank 1B.
To interface the TDI and TDO lines of the JTAG pins of devices that have different VCCIO levels, insert a level shifter between the devices. If possible, construct the JTAG chain where device with a higher VCCIO level drives to a device with an equal or lower VCCIO level. In this setup, you only require a level shifter for shifting the TDO level to a level JTAG tester accept.
To ensure that you do not inadvertently enable the JTAG BST circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.
|JTAG Pins||Connection to Disable|
|TMS||VCCIO supply of Bank 1B|
|TDI||VCCIO supply of Bank 1B|
You must enable this circuitry only if you use the BST or ISP features.
Consider the following guidelines when you perform BST with the device:
- If the
“10...” pattern does not shift out of the
instruction register through the
TDO pin during the first clock cycle of the
state, the TAP
controller did not reach the proper state. To solve this problem, try one of
the following procedures:
- Verify that the TAP controller has reached the SHIFT_IR state correctly. To advance the TAP controller to the SHIFT_IR state, return TAP controller to the RESET state and send the 01100 code to the TMS pin.
- Check the connections to the VCC, GND, JTAG, and dedicated configuration pins on the device.
- Perform a SAMPLE/PRELOAD test cycle before the first EXTEST test cycle to ensure that known data is present at the device pins when you enter EXTEST mode. If the OEJ update register contains 0, the data in the OUTJ update register is driven out. The state must be known and correct to avoid contention with other devices in the system.
- To perform testing before configuration, hold the nCONGFIG pin low.
|February 2017||2017.02.21||Rebranded as Intel.|
|May 2015||2015.05.04||Added note on about performing the boundary-scan testing in 'Overview'.|
|September 2014||2014.09.22||Initial release.|