Important block of a central processing unit in any computing system is Arithmetic and Logic Unit (ALU). Among all the arithmetic operations, division is considered to be more complicated and it completes after several cycles of time. Latency is increased because of the clock cycles. It is frequently utilized in the areas of signal and image processing applications. This work describes the architecture of a serial divider in combination with the influence of Han Carlson adder. Adder along with the non-restoring algorithm has been tested for the design of divider in the DADENCE platform. And found 48.67% reduction in delay over the existing method.
Keywords : Cadence, Han Carlson Adder, Serial divider, Non Restoring Algorithm, Delay.