CHARACTERISTICS OF THE JUNCTION FIELD EFFECT TRANSISTOR
To become familiar with the theory of operation of Junction Field Effect Transistors (JFET) and to examine the V-I characteristics of the JFET.
Figure 1 shows the structure of an N-channel JFET. As this figure depicts, the N-channel JFET is made of N-type semiconductor material with two islands of P-type materials embedded in the middle sides of this material. One end of the N-type channel is called "Source" while the opposite end is called "Drain". The two P-type materials in the middle are internally connected and are referred to as the "Gate". Notice the narrow channel between the two P-regions of the JFET in Figure 1. It is through this narrow channel that the free electrons in the N-type material must pass as they move from the source to the drain. Thus, when a negative voltage is applied on the gate, the induced electric field in this P-material (gate) will control the flow of electrons between the source and the drain. Therefore, the JFET is a voltage-controlled device.
Figure 1 - Symbol and Structure of Junction Field Effect Transistor (JFET)
In biasing the N-channel JFET, a positive voltage VDD is connected between the drain and the source thus allowing for the free electrons to flow from the source to the drain. Since these electrons must pass through the gate region (channel), this would provide means for controlling the current flow from the drain to the source. This is done by applying negative voltage across the gate region to impede the movement of the electrons passing through it. Figure 2(a) illustrates the bias of an N-channel JFET.
Figure 2 - Biasing of an N-Channel JFET
Notice that the negative gate supply VGG is connected between the gate and the source. This is standard for all JFET applications. The gate of the JFET must always be reverse biased to prevent electric current from flowing into the gate. However, the reverse bias introduces depletion layers around the gate region (P-region) as shown in Figure 2(b). Thus, increasing the negative voltage on the gate will make the conduction channel across the gate narrower. The more negative the gate voltage the narrower the channel becomes because the depletion layers get closer together. When the gate voltage is made negative enough, the depletion layers across the gate region touch and the conducting channel disappears (PINCH OFF). In this case the drain-source current is cut-off. The gate voltage in this case is called the "Pinch-off" voltage (Vp-off). Typical value for such a voltage in small signal JFET's is about -3 to -4V DC.
On the other hand, when VGG is set to zero, the pinch-off region will disappear and the current from the drain to the source will be free to flow, only controlled by the resistance of the N-type materials forming the N-type channel (see Figure 1). As a result, this current is the maximum drain current a JFET can produce for a given drain-to-source voltage before the transistor goes into breakdown. This current is typically referred to as IDSS.
The trans-conductance characteristic of the JFET is a set of graphs relating the drain current to the gate voltage, i.e. ID versus VGS. In analytical form, this relationship is universally given as,
This equation applies to any JFET regardless of the channel polarity.
In this experiment, a 2N5457, N-type JFET will be used in the measurement. The pin connection diagram for the 2N5457 transistor is as shown in Figure 3.
Figure 3 - Pin Connection Diagram of the 2N5457 JFET
For the given transistor, measure the DC resistance between the drain and source terminals with the gate terminal left open. Reverse the polarity of the DMM probe and measure the channel resistance of the drain-source again. Compare the two measured values.
- Construct the circuit shown in figure 4. Start with VGG and VDD at zero volts. Connect a DMM between the drain and source of the transistor. Keep VGG at 0V and slowly increase VDD until VDS is 1.0V. (VDS is the voltage between the transistor's drain and source.)
- With VDS at 1.0V, measure the voltage across R2 (VR2). Compute the drain current, ID, by applying Ohm's law to R2. Note that the current in R2 is the same as ID for the transistor. Enter the computed ID in Table 1 under the column labeled Gate Voltage=0V.
- Without disturbing the setting of VGG, slowly increase VDD until VDS is 2.0V. Measure and record VR2 for this setting. Compute ID as before and enter the computed current in the table.
- Repeat step 3 for each value of VDS listed in table 1.
- Adjust VGG for -1.0V. This applies -1.0V between the gate and source because there is almost no gate current into the JFET and almost no voltage drop across R1. Reset VDD until VDS=1.0V. Measure VR2 and enter it in the table. Compute ID and enter the computed current in the table under the columns labeled Gate Voltage=-1.0V.
- Without changing the setting of VGG, adjust VDD for each value of VDS listed in the table as before. Compute the drain current at each setting and enter it in the table under the columns labeled Gate Voltage=-1.0V.
- Adjust VGG for -2.0V. Repeat steps 5 and 6, entering the data under the columns labeled Gate Voltage=-2.0V.
- The data in Table 1 represent three drain characteristic curves for your JFET. The drain characteristic curve is a graph of ID versus VDS for a constant gate voltage. Use MS Excel to plot all curves on one sheet.
- From your graphs, determine IDSS and Vp-Off and compare them to the values in the data sheet.
Figure 4 - Connection Diagram for the Characteristics of the JFET Transistor