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The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
By: Strumpen, V.; Frank, M.; Seneski, M.; Saraf, A.; Ma, A.; Lee, W.; Jae-Wook Lee; Shnidman, N.; Johnson, P.; Hoffman, H.; Greenwald, B.; Ghodrat, F.; Wentzlaff, D.; Miller, J.; Kim, J.; Taylor, M.B.; Agarwal, A.; Amarasinghe, S.;
2002 / IEEE
This item was taken from the IEEE Periodical ' The Raw microprocessor: a computational fabric for software circuits and general-purpose programs ' Wire delay is emerging as the natural limiter to microprocessor scalability. A new architectural approach could solve this problem, as well as deliver unprecedented performance, energy efficiency and cost effectiveness. The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip. An architecture that has direct, first-class analogs to all of these physical resources will ultimately let programmers achieve the maximum amount of performance and energy efficiency in the face of wire delay.
Scalable Instruction Set Architecture
Parallel Software Interface
Chip Gate Resources
Chip Wire Resources
Chip Pin Resources
General Purpose Computers
Computing And Processing