Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002 Donnamaie E. White
Last Edit July 22, 2001
Array vendors are beginning to incorporate thermal diodes and AC speed monitors within the base array or as macros that can be added to allow thermal and speed measurements. AC tests may also be allowed, regardless of the presence of a speed monitor.
An AC test is a measurement of one path, input to output, using a single input, a rising or falling signal on that signal, one output and the rising or falling edge on that signal. The vendor may allow set-up and hold measurements or the designer may be restricted to propagation path tests only.
Quality Assurance departments will generally require that the DC parametric tests for VIH and VIL be performed on the array. Should this option be selected, there are several approaches that can be used to ensure proper vectors and conditions for these tests.
The easiest method has been to allow the tests to be made using the test vectors written to perform wafer sort. This approach is acceptable if the inputs to be tested are toggled within the a single page of the vectors; if the input to output paths are combinatorial and if the number of outputs which toggle during those vectors is within the tester limits.
Different vendors may suggest or require alternative approaches. When it is not possible to meet the restrictions that would allow parametric testing with the wafer sort vectors, a successful approach is to add combinatorial gates (NAND, AND, NOR or OR) and one output macro. Gate all inputs or all inputs to be tested through this combinatorial gate tree.
There are several types of inputs that cannot be tested in any of these approaches. They are:
Differential inputs always operate as a pair and each pair should be considered as a single entity when reading the following test methodology descriptions.
Gate Tree - Any Circuit
This approach for parametric testing is the best for any circuit, any I/O mode. It requires internal logic cells, internal routing, and one additional I/O cell.
The toggle pattern of the parametric test is the Minimal Test Sequence for the gate tree. [The Minimal Test Sequence is discussed in Chapter 9.] The Minimal Test Sequence will cover all possible faults in the gate tree. Wafer sort vectors and parametric vectors taken together determine the fault grade score of the vector set for the entire circuit.