If you can squish all the processing power of say an IBM Roadrunner supercomputer inside a 19-inch box and make it run on about 60 kilowatts of electricity, the government wants to talk to you.
The extreme scientists at the Defense Advanced Research Projects Agency this week issued a call for research that might develop a super-small, super-efficient super beast of a computer.
Specifically DARPA's Ubiquitous High Performance Computing (UHPC) desires will require:
-New system-wide technology approaches specifically including hardware and software co-design to minimize energy dissipation per operation and maximize energy efficiency, with a 50GFLOPS per watt goal, without sacrificing scalability to ultra-high performance DoD applications - efficiency.
-New technologies and execution models that do not require application programmers to explicitly manage system complexity, in terms of architectural attributes with respect to data locality and concurrency, to achieve their performance and time to solution goals - programmability.
-Technology that will manage hardware and software concurrency, minimizing overhead for thousand- to billion-way parallelism for the system-level programmer.
-A system-wide approach to achieve reliability and security through fault management techniques enabling an application to execute correctly through both failures and attacks.
Current processing systems are grossly power-inefficient and typically deliver only a small fraction of peak performance. Until recently, advances in Commercial Off-The-Shelf systems performances were enabled by increases in clock speed, decreases in supply voltage, and growth in transistor count. These technology trends have reached a performance wall where increasing clock speed results in unacceptably large power increases, and decreasing voltage causes increasing susceptibility to transient and permanent errors, DARPA stated.
DARPA went on to outline a number of challenges developing such as systems would face, including:
-The energy and power challenge is the most pervasive. A key observation is that it will be easier to solve the power problem associated with base computation than to reduce the problem of transporting data from one site to another - on the same chip, between closely coupled chips in a common package, between different racks on opposite sides of a large machine room, or on storing and accessing data in the aggregate memory hierarchy.
-The memory and storage challenge concerns the lack of currently available technology to retain data at high enough capacities (and access it at high enough rates) to support the desired application suites oat the desired computational rate and still fit within an acceptable power envelope. This information storage challenge lies in both main memory (DRAM today) and in secondary storage (rotating disks today).
-The concurrency and locality challenge likewise grows out of the flattening of silicon clock rates and the end of increasing single thread performance, which has left explicit, largely programmer visible, parallelism as the only mechanism in silicon to increase overall system performance. ExtremeScale systems may have to support upwards of a billion separate threads.
-A resiliency challenge that deals with the ability of a system to continue operation in the presence of either faults or performance fluctuations. This concern grew out of not only the explosive growth in component count for the larger classes of systems, but also out of the need to use advanced technology, at lower voltage levels, where individual devices and circuits become more and more sensitive to local operating environments, and new classes of aging effects become significant.
These challenges cannot be pursed independently at the component level such as processor, memory and network switches; they must be addressed as an integrated solution. Co-design of the system hardware and software that is driven by processing requirements for selected application domains is essential. Solving individual challenges will not result in viable system solutions, DARPA stated.
Layer 8 in a box
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