A primer on PCI
Before I go into detail on PCIe, it helps to understand how PCI works and what its limitations are.
The PCI bus debuted over a decade ago at 33MHz, with a 32-bit bus and a peak theoretical bandwidth of 132MB/s. This was pretty good for the time, but as the rest of the system got more bandwidth hungry both the bus speed and bus width were cranked up in a effort keep pace. Later flavors of PCI included a 64-bit, 33MHz bus combination with a peak bandwidth of 264MB/s; a more recent 64-bit, 66MHz combination with a bandwidth of 512MB/s.
PCI uses a shared bus topology to allow for communication among the different devices on the bus; the different PCI devices (i.e., a network card, a sound card, a RAID card, etc.) are all attached to the same bus, which they use to communicate with the CPU. Take a look at the following diagram to get a feel for what a shared bus looks like.
Because all of the devices attached to the bus must share it among themselves, there has to be some kind of bus arbitration scheme in place for deciding who gets access to the bus and when, especially in situations where multiple devices need to use the bus at the same time. Once a device has control of the bus, it becomes the bus master, which means that it can use the PCI bus to talk to the CPU or memory via the chipset's southbridge.
Speaking of the southbridge, the large system diagram that I presented on the first page ? the one with the PCI devices attached to the southbridge ? represents how things are actually configured in the real world, as opposed to the idealized representation given immediately above. The southbridge, the northbridge, and the CPU all combine to fill the host or root role, which we'll discuss in a bit more detail momentarily. For now, it will suffice to note that the root runs the show ? it detects and initializes the PCI devices, and it controls the PCI bus by default. Or another way to put it would be to say that the purpose of the PCI bus is to connect I/O devices to the root, so that the root can read from them and write to them, and just generally use them to talk either to storage devices or to the outside world.
The shared bus topology's main advantages are that it's simple, cheap, and easy to implement ? or at least, that's the case as long as you're not trying to do anything too fancy with it. Once you start demanding more performance and functionality from a shared bus, then you run into its limitations. Let's take a look at some of those limitations, in order to motivate our discussion of PCI Express's improvements.
From the CPU's perspective, PCI devices are accessible via a fairly straightforward load-store mechanism. There's flat, unified chunk of address space dedicated for PCI use, which looks to the CPU much like a flat chunk of main memory address space, the primary difference being that at each range of addresses there sits a PCI device instead of a group of memory cells containing code or data.
So in the same way that the CPU access memory by performing loads and stores to specific addresses, it accesses PCI devices by performing reads and writes to specific addresses.
When a PCI-enabled computer boots up, it must initialize the PCI subsystem by assigning chunks of the PCI address space to the different devices so that they'll be accessible to the CPU. Once the devices are initialized and know which parts of the address space that they "own," they start listening to the bus for any commands and data that might be directed their way. Once an individual PCI device "hears" an address that it owns being placed on the bus, then it reads any data following behind that address.
This scheme works fine when there are only a few devices attached to the bus, listening to it for addresses and data. But the nature of a bus is that any device that's attached to it and is "listening" to it injects a certain amount of noise onto the bus. Thus the more devices that listen to the bus ? and thereby place an electrical load on the bus ? the more noise there is on the bus and the harder it becomes to get a clean signal through.