With chip-to-chip interconnects now running at 8 GT/s and above, a new class of faults due to manufacturing and process drift is emerging. What are these faults and how are they detected?
Confidence in a SerDes circuit on a board design has often been based upon running a bit error rate test (BERT) or margining test on an initial batch of prototypes. Historically, getting a low BER or a good eye diagram was a guarantee of signal integrity, and the design would be expected to perform well in field deployment for many years to come. However, with higher speed I/O now significantly being deployed for chip interconnects, a new fault spectrum is emerging which requires special attention.
In general terms, I call this fault spectrum “drift”. The drift is characterized by the change of a given circuit’s attributes over time, versus the initial “golden board” which was validated to have good signal integrity. This source of the drift can be in any of the elements that are part of the circuit: the transmitting or receiving devices, their solder joints, or the transmission path between. Often, the class of defects that are characterized by drift will not be detected by normal structural or functional test, because the bus will often continue to work, albeit at a degraded throughput level. Tests which measure the bus performance, such as its BER or margin, are required to detect these defects.
I’ll review the specific mechanics of drift in a future Blog. But, a quick categorization of the defect classes is as follows:
In an empirical analysis conducted in 2009 (available here) on 6.4 GT/s nets, it was found that circuit margins closely follow device lots.
Margins and BER will also follow the device supporting infrastructure. For example, marginal clocking or power rail instability, which can arise from different device lots or board lots, will affect bus performance.
The following structural defects will affect the characteristics of the transmission path:
- Gross short circuits
- Gross open circuits
- Solder voids
Below are some PCB variance and manufacturing process variants which can affect signal integrity:
- Stripline Dimensions
- Trace Surface Finish
- Flaws introduced during the imaging process (pin holes, nicks, cuts)
- Incompletely plated vias
- Annular ring breakout
- Plating thickness variances
Any one of the above variances may not cause the PCB to fall outside the acceptable tolerance range, but the cumulative effects of several variations may yield unacceptable results. And while some PCB variances may be caught by sampling at the batch or lot level, other flaws and process variants might only affect a single board’s performance.
It can therefore be seen that validating design signal integrity needs to be part of the manufacturing process, as opposed to a single event during initial design validation.
Are you referring to using HSIO in the manufacturing arena to handle “Drift”?
Yes. The intent of this Blog was to describe the problem space based upon newer designs using higher-speed buses: PCI Express 3.0 (PCIe Gen3), Intel QuickPath Interconnect, SATA 3, DDR3 and DDR4, etc. etc. In other locations on ASSET’s website you can see that legacy structural and functional test tools can’t detect this new class of defects. New techologies that apply BERT and margining BIST (Built-In Self Test) such as the Intel HSIO tool are needed here.
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