Be able to recognize chip structures, especially memory
Know what the main components of an FPGA fabric are
Locating memory on a die image#
Are you curious about how an FPGA look like inside? Siliconpron houses integrated circuit die images including FPGAs.
Analyze the die image of an AMD 7-Series Artix FPGA xc7a50t.
Memory cells tend to have a very homogeneous and dense structure. Try to guess which patterns on the image could depict memory elements.
Analyzing the floorplan of an FPGA#
After you guessed which areas could house memory cells, we will test your guesses using a floorplan of xc7a50t in Vivado:
Fire up Vivado and click on
I/O Planning Project.
Import Ports (optional)window click
Do not import I/O ports ....
Default Partwindow, search for
xc7a50tand select one of them.
The shown parts only differ in their
I/O Pin Countand
Available IOBsbut not in any of the logic resources. This is a sign that they all have the same die.
Finish the project wizard. You will see the
I/O designwindow. On the right side you have
A single die can have different packages to meet different application requirements like maximum chip size, required number of data signals, temperature range etc. A die is connected to the pins of a package via a process called wire bonding. An example image is here. You see that the chip is bonded to the package using the pads on its four edges.
Now click on the
Deviceand maximize the window.
Zoom in and browse the components. You can see the name of these components by hovering on them.
Which major components do you find on the FPGA fabric and what could the purpose of each component?
Solution to Exercise 182
The FPGA floorplan is organized in tiles which can in turn include one or many components.
CLBLL_L_X2Y149) tile is configurable logic block that can implement arbitrary logic and be connected to other logic resources.
CLB is the dominating resource in terms of count.
DSP_*tile houses multipliers and adders which are commonly used in signal filtering applications like convolution. DSP tiles are poured between CLBs.
BRAM_*tile houses block RAM which include optional FIFO circuitry around two smaller BRAM blocks (TODO check). These are poured between CLBs and provide larger memory compared to the FFs available in the CLBs.
IOBI/O blocks which are on the left and right borders of the die.
CMTclock-management tile for generating clocks at different frequencies or skews.
MONITOR_BOTincludes analog-digital converter (TODO: why this name?)
GTP_CHANNEL_*is a transceiver. It is used for (de-)serializing bits (SerDes) to (receive)transmit information to other chips (e.g., gigabit Ethernet).
Latest transceivers are capable of 112 Gb/s as of 2023.
This list is not exhaustive.
Comparing floorplan and die image structures#
Now try to match the features on the die image to the components on the floor plan. You should at least be able to recognize block RAMs.
Solution to Exercise 183
You have to flip the die image in your head to match the components that you discovered on the device map.
The very black parts of the image house the block RAMs. They are black because the memory cells tend to be very dense but homogeneous structures. We can test that by counting the on the left top of the image — there are 5
Each tile consists of two black areas with non-homogeneous area which probably contains the addressing and FIFO logic for two block RAMs.
The area on the left bottom of the die is very distinctive. It probably houses the transceivers.