Hi Robert! i got a question, if i see the L2 of the REX is not a power plane neither a GND plane is just used to do the fan out, so is not a reference plane for the L3 (signal) , and all the impedances are calculated like an stripline for those internal layers, so how is that done?, as far as i can see I only see a reference plane (GND) in layer 4, there is missing the other reference plane to have an stripline so…? i’m thinking wrong or what??? thanks!
Ok, thanks, but i got a question, I’m looking the reference design of the sabre smart device, the development board of freescale, and they use 8 layers, 4 for signals, and just 2 for power, and they make a lot of power islands, but the question that I have ( the same that i was having with the REX) is that they don’t have a continous reference power plane in the striplines, they brake the power plane a lot of times in some critical lines like the RAM, so that would generate loops and difference in Z0 so that implies reflections, so i’m a little confused overthere, can you orientate me in that matter please?
Please login first to submit.