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|Originally Published: Wednesday, 22 November 2000||Author: Derek Barber|
|Published to: develop_articles_tutorials/Development Tutorials||Page: 1/1 - [Std View]|
Getting Started with Make - Part 3: Directives
In the final issue of the Getting Started with Make series, we discuss directives, commands which you can put in your Makefiles to provide some neat enhancements -- such as including the contents of other files, adding control structures, and enhancing the handling of variables.
Welcome to the third part of this series on getting started with make. In the previous issues we covered the real basics of make, including the purpose of make, and how to start using it for simple projects. We introduced the concepts of rules, targets, dependencies, and commands. We also explored using variables in makefiles, the difference between explicit and implicit rules, and using wildcards. To read more about any of those topics, please review the previous issues.
In this issue we will finish off our introduction to make by discussing a few more features of make and expanding upon the topics we have previously covered.
Directives are commands which you can put in your Makefiles to provide some neat enhancements. A very useful directive, called the include directive, allows you to include the contents of other files in your makefile. This can be very handy for organizing a large makefile into several files, among other things. There are also directives that provide the ability of conditional inclusion -- they decide whether to include or skip certain parts of a makefile based upon the value of variables. Finally, there is also a directive that enhances the handling of variables: the define directive.
The Include Directive
First, let's look at the include directive. The include directive is used to include the contents of a specified file into your makefile at a specified place. This is very useful for many things, especially with the organization of data and with the reusability of common makefile data. Before we get into an example, let's look at the general syntax of the include directive:
Please note that you can include shell wildcard characters in the filenames parameter.
The include directive is very useful when you have a set of common makefile statements that you would like to share between multiple makefiles. Additionally, the include directive can be used to break apart the contents of your makefile into separate, logical files and then include all the parts from your central makefile. Let us look at a simple example of putting the include directive to use in this manner and break apart a single makefile into separate, logical files. Then we will use the include directive to insert them into the actual makefile. In this case, we break up the makefile into two parts: the main part which includes the actual binary compilation process, and the depends part that compiles the dependencies. Here are the contents of the two files:
main : main.o hack.o
g++ -o main main.o hack.o
main.o : main.cc
g++ -c main.cc
hack.o : hack.cc
g++ -c hack.cc
rm main main.o hack.o
Now your Makefile can look like the following:
include Main Depends
In the above example, make will take the contents of the "Main" and "Depends" files and include their contents in that order in the actual makefile. Keep in mind that this will all be done at run-time.
Conditional directives are used when you would like to execute or ignore certain parts of a makefile depending upon the values of variables. This can be very useful when deciding to set certain compilation parameters based upon the installed libraries or the locations of files. The syntax of a simple conditional directive is as follows:
commands executed if conditional is true
commands executed if conditional is false
In the above syntax, the conditional-directive parameter can be one of several conditional directives. The following is a list of the different conditional directives available and what they accomplish:
ifeq (var1, var2) - returns true if var1 and var2 are equal
ifneq (var1, var2) - returns true if var1 and var2 are not equal
ifdef var - returns true if var is defined
ifndef var - returns true if var is not defined
Now let's look at a few very simple examples, putting the above information to some use. Here is an example of using ifeq:
var1 = something
var2 = nothing
ifeq (var1, var2)
result = equal
result = notequal
In the above example the variable var1 is compared to var2. Since var1 is equal to "something" and var2 is equal to "nothing" they are not equal, so the variable result will be set to "notequal."
Now, here is an example of using ifdef:
var = yes
vardefined = true
vardefined = false
In the above example, the variable test is set to "yes." Then the ifdef conditional checks if var is is defined, in this case it is and so the vardefined variable is set to "true."
The Define Directive
The define directive is used to set the value for variables verbatim, allowing characters such as newlines into the value of the variable. The syntax of the define variable is as follows:
The define directive begins with the declaration of the variable name and then the following lines until the endef are set as the contents for the variables. As stated earlier, newline characters are not discarded and are put into the value of the variable along with all other data. Now, here is an example that creates a multi-line variable using the define directive:
The above statements create a variable called commands which contains the two shell commands "echo hello" and "echo world."
In this issue we have delved further into the world of makefiles and have learned about several important directives that can be used with make. Combined with the knowledge of these three issues of Getting Started with Make, you should be on your way to using make in your programming projects. To take your knowledge of make to the next level, be sure to start reading the manual for make from GNU.
Derek Barber, email@example.com.