Intel is working on a transistor design that could help the company's designers pack more memory onto its processors.
Company researchers plan to present a paper this week at the International Electron Devices Meeting in San Francisco outlining its work on "floating-body cell" transistors, said Mike Mayberry, director of components research with Intel's technology and manufacturing group. Simply put, the floating body cells could allow Intel to build processors with larger amounts of on-chip memory to boost performance, he said.
Mayberry's job is to come up with options for building ever-smaller transistors and keeping the performance train rolling well into the future. The floating-body cell idea is designed to improve the density of the cache memory that chip designers place on a processor.
Cache memory is used to store frequently accessed data directly on the chip, where it can be accessed much faster than data stored in system memory or on a hard drive. But SRAM (static RAM) cells currently used to make cache memory are not as dense as Intel would like, with six transistors needed to build a cell and store one bit of information.
The company would like to get that down to one transistor per bit of information. But one technology that fits the bill--embedded DRAM (dynamic RAM)--is slower than SRAM and expensive to manufacture. Enter floating-body cells.
Floating-body cells are based on the principle that applying a voltage to the base of a cell allows that cell to store a charge--which can represent a bit--along one part of the cell. This is called the "history effect."
Toshiba and the University of California at Berkeley have done significant research into floating-body cells, in which a memory cell sits in between a gate on top and an oxide layer on the bottom, with the substrate of the chip beneath the oxide layer, Mayberry said. But the cells they have built have oxide layers of varying thicknesses in order to get the right charge needed for a particular type of memory chip. The memory cells required for PC processors might need one level of thickness while the transistors used for logic processing on that chip might need an altogether different level, and it's impossible to have transistors with different amounts of oxide thickness residing on the same chip, Mayberry said.
Intel's idea is to flip the floating-body cell on its side and use a design that has two gates, Mayberry said. This way, it can keep the substrate thickness constant for both memory cells and logic transistors, and tweak the charge needed to store data in the memory cell by using two gates instead of the single gate and varying levels of substrate thickness, he said.
This approach also borrows from the work Intel has already done on building a trigate transistor, which envelops a transistor on three sides in order to manipulate the electrical charges, Mayberry said. Intel is researching whether it will want to use trigate transistors within the next three to seven years, the same time frame it is eyeing for floating-body cell memory, he said.
Several hurdles remain, most notably that Intel has only made this work using silicon-on-insulator technology, a technique favored by IBM and Advanced Micro Devices that Intel generally shuns when building its transistors. However, the goal of research like the floating-body cell work is to give Intel's transistor teams a variety of options from which to choose when plotting its future course.