SystemVerilog for Design
|Name of the course||Online||Lecture||Exercises||Lab|
|SystemVerilog for Design||✓||✓||✓||✓|
The course 'SystemVerilog for Design' is a training on the design flow of Application Specific Integrated Circuits (ASICs) with SystemVerilog. The course has a focus on the front-end design flow from HDL entry to synthesis and static timing analysis. It is recommended to have a solid knowledge in Digital Engineering and Electrical Engineering as well as basic experience in shellscript and programming. Knowledge in CMOS technology is an advantage but not a must. The course is an online course and is as such organized as a virtual classroom.
The course is organized in two parts. The first part is a lecture on the Hardware Description Language (HDL) SystemVerilog with a focus on digital hardware design at Register-Transfer-Level (RTL). Students write SystemVerilog code for small design examples, then simulate the design, perform a synthesis and a static timing analysis. All testbenches are at designer level and secure only basic functionality. Inspections of the netlists and timing reports show how the tools synthesize digital hardware from HDL code. Part Two is a series of exercises on the digital ASIC design flow for large complex designs. It introduces some relevant standard procedures as they are part of the daily work of a design engineer. The exercises focus on the tools used for synthesis, static timing analysis, power profiling, logic equivalence check and the ECO flow. This practical training utilizes the Cadence Design Environment. Its content is also applied for trainings in industry, i.e. Rapid Adoption Kits (RAKs).
Having completed the course successfully, students will understand the ASIC design flow and will be able to work with the front-end design flow, implement RTL designs, run synthesis and static timing analysis and optimize the results. The back-end design flow and verification techniques for digital designs are out of the scope of the course. There is a separate course SystemVerilog for Verification on the verification of complex digital designs.
More details on the exercises can be found here.
|1||Introduction to SystemVerilog||[PDF]|
|2||Modeling at Register-Transfer-Level||[PDF]|
|3||Net and variable types||[PDF]|
|4||Organizing designs with packages||[PDF]|
|5.1||SystemVerilog at Register-Transfer-Level (1 of 2)||[PDF]|
|5.2||SystemVerilog at Register-Transfer-Level (2 of 2)||[PDF]|
|6||Synthesis at Register-Transfer-Level||[PDF]|
|7||Modeling sequential logic and memory||[PDF]|
|8||Intentional and unintentional inferred latches||[PDF]|
|FLOW RAK||ASIC design flow example||[PDF*]|
|GENUS RAK||RTL Synthesis Compiler||[PDF*]|
|Tempus GTD RAK||Global Timing Debug||[PDF*]|
|RTL-VCD RAK||Power Profiling||[PDF*]|
|LEC RAK||Logic Equivalence Check||[PDF*]|
|ECO RAK||Engineering Change Orders (RTL to GDSII)||[PDF*]|
Literature RTL Modeling with SystemVerilog for Simulation and Synthesis, Stuart Sutherland,
published by Sutherland HDL, Oregon 2017, ISBN 078-1-5467-7634-5
 CMOS VLSI Design, Weste & Harris, Addison Wesley Publ., ISBN 0-321-54774-8