Last issue, we began our discussion on time domain reflectometry, or TDR. To recap a little, in order to calculate the distance to the defect, the engineer captures the signal and establishes a time difference. He or she must relate that time difference back into a distance to establish where the open or change in resistance might be. The distance to the defect in millimeters can be calculated by
where c is the speed of light in meters per second, Δt is the estimated time difference calculated from the waveforms, and ε is the dielectric constant of the material. Different materials have different dielectric constants, so one needs to take this variable into account. Last month we provided a table of example materials and their dielectric constants. As an example calculation, a Δt of 50 psec gives a distance to the open of 3.71mm in a fiberglass substrate.
The key challenge with this technology is interpretation and integration with the design files. Waveforms can be quite difficult to interpret, necessitating comparisons between good devices and failing devices. The locations shown in this diagram are the locations where waveforms are measured in the next illustration. They are labeled Location A, B, and C. The times associated with those locations should be based on the distances through the vias and traces.
The challenge with TDR is interpreting the waveforms. There can be numerous reflections at material bends and interfaces, which add complexity to the waveforms. In this graph, the red waveform is from the unterminated cable of the time domain reflectometer. The green waveform is from the cable connected to the printed circuit board, the black is from a unit with electrical opens and the blue is from a good unit. The waveform rises more slowly in the good unit indicating that more of the signal is transmitted further into the package before being reflected. The sharp rise in the black waveform indicates a strong reflection, or change in material interface closer to the package edge. Notice that although there is a significant difference between the good unit and the unit with the electrical opens, the point where one should indicate the rise is not clear.
Another issue with interpreting TDR waveforms is that it can be difficult to identify small differences. In these waveforms, we are looking at differences. It is clear that the reflection waveforms from Cut 1 and Cut 2 are separable but the rising edges from the reflections of Cut 3 to Cut 5 are superimposed onto one another, which do not provide useful information about the locations of failures. This can make interpretation a challenge when the distance to the open is small.
One method for better resolving the data in a TDR waveform is to use electro-optical TDR. Electro-optical TDR uses electro-optics and a photoconductive switch to generate the pulse. With conventional TDR the highest frequencies run at approximately 50GHz. This yields about a 250-micron resolution. With electro-optical TDR, the bandwidth can be as high as 2THz, which yields approximately 10 microns resolution. Here we show the same data from the cuts on the previous slide, but this time we use electro-optical TDR to create the waveforms. In this case, the waveforms can more easily be resolved.
To summarize, TDR is becoming more common in the analysis of packaging problems. The ability to gather data non-destructively that can aid in isolating the failure in a complex package is important. Interpretation can be a challenge though. Package complexity leads to reflected signals at vias, bends, and materials interfaces. Because of the frequencies of the signals, the spatial resolution for TDR is somewhat limited as well. With standard TDR, the spatial resolution is around 250 microns. Electro-optical TDR is a newer form of TDR that does improve on the original technique. The higher frequencies allow for spatial resolution down to 10 microns, and improved ability to interpret the data. Expect to see more use of electro-optical TDR in the future.
Some companies use different percentages of silicon in their aluminum-silicon (Al-Si) metallization systems. This phase diagram helps to illustrate why one might choose different percentages.
If we look at the phase diagram, we see 100% Al on the left and 100% Si on the right. The melting temperature for Al is 660°C, the melting temperature for Si is 1414°C, and the eutectic temperature (at 11.3% Si) is 577°C. We are interested in how much Si we can incorporate into the Al in solid solution – the region at the lower left. We have expanded that region in the white inset graph. Notice that at Al-0.5%Si, the solid solution temperature can be as low as 500°C whereas with Al-1%Si, the solid solution temperature can only be as low as 550°C. This means that if we want Al-1%Si, we’ll need to do the deposition at 550°C or higher, whereas with Al-0.5%Si, we can do the deposition as low as 500°C. A lower deposition temperature can be beneficial from a thermal budget standpoint, creating less damage. On the other hand, a higher percentage of Si in the Al will better prevent Si nodules. This is the basic tradeoff process engineers face with Al-Si metal systems.
Q: I am trying to determine the percentage of chromium in a SiCr fusible link resistor using Energy Dispersive X-Ray Spectroscopy, but I am seeing a very low percentage (1-2%). How much chromium should be in the SiCr resistor?
A: The typical number is between 15 and 35%. The reason you are seeing such a low percentage is probably due to the fact that the SiCr resistor is very thin, and the interaction volume of the SEM is penetrating well beyond the material, causing you to see more of the silicon in the SiO2 and substrate. The resistor film is usually around 10nm thick, which means the vast major of the beam penetrates beyond the resistor.
Please visit http://www.semitracks.com/courses/analysis/failure-and-yield-analysis.php to learn more about this exciting course!
(Click on each item for details).
Semiconductor Reliability on September 3-5, 2014 (Wed.-Fri.) in San Jose, CA, USA
Failure and Yield Analysis on September 8-11, 2014 (Mon.-Thurs.) in San Jose, CA, USA
Product Qualification on January 26-27, 2015 (Mon.-Tues.) in San Jose, CA, USA
Wafer Fab Processing on January 26-29, 2015 (Mon.-Thurs.) in San Jose, CA, USA
EOS, ESD and How to Differentiate on January 28-29, 2015 (Wed.-Thurs.) in San Jose, CA, USA
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