As long as the amount of random jitter in the data signal was negligible, the setup and hold assumption was also reasonable. For DDR speeds up to about 1.6 GT/s, the contribution of random jitter to signal timing was small compared to the total bit time, which is the inverse of the data transfer rate. At higher speeds, however, random jitter effects become significant, potentially taking up much more than half of the entire data valid window. Table 1 (below) shows just how much of the data valid window can be consumed by 5 ps (rms) of random jitter in a variety of DDR designs (assuming a 10-18 BER goal).
Table 1: Amount of DDR data valid window consumed by random jitter
Although an error rate of 1 in 10-18
bits seems vanishingly small, DDR busses are usually 64 bits or more wide, so this actually results in a memory-channel error rate greater than 10-16
, or more than one failure every two weeks. The traditional assumption of zero errors when Ts+Th is satisfied cannot be achieved in practice, but for the lower DDR speeds, this goal can be effectively met by adding a relatively small amount of extra timing margin to the device specification. This has in fact been the industry practice thru DDR3. It’s interesting to note that at 1.6 GT/s, at which the portion of the data-valid window that could be consumed by random jitter becomes significant, the traditional allocations of timing budget for the controller, the DRAM and the memory bus begins to result in negative system timing margin.
Negative margin in a real system translates immediately into system instability, reliability and performance issues. But there are plenty of stable, high performance DDR3 systems running today at speeds even faster than 1600 MT/s. The reason for this is that the memory, controller and system developers go to great lengths to add extra margin to their own designs to ensure their products run reliably. At 1600 MT/s and above, this margin is no longer small compared to what the specification requires. The cost of adding an appropriate margin can become significant when you consider how much longer it may take to complete a new design, perform additional characterization, implement stricter tests, or screen to tighter speed bins in production. The problem is exacerbated if all three development teams—controller, system and memory—design in the same margin, then this work is not done just once but several times, adding unnecessary cost and complexity. The DDR4 specification not only reduces or eliminates the need to add redundant margin, it also enables a more exact calculation of how much margin is actually needed to meet performance and reliability goals. This can reduce development costs, improve time to market and increase yields thru more accurate binning in production.