FPGA Power Optimization
Attendance at the workshop “FPGA Power Optimization” allows you to better streamline your FPGA applications with regards to power consumption. This ultimately allows usage of more cost effective or smaller FPGAs, lower the draw of current, use a cheaper cooling mechanism or simply to gain robustness. Mastering the parameters and methods is crucial to achieve these goals since all of them are interacting with one another. Even project schedules are frequently affected by these factors since real values mostly are only known at the very end of the development cycle. The different methods get introduced and will be applied during exercises by the attendees.
Many factors have to be taken into consideration: The clocking system, toggle rates, activity rates, voltage levels, HDL coding style, synthesis and implementation options as well as environmental parameters. At the beginning of a development cycle, estimates will be necessary; during the coding phase, parameters extracted from simulation and finally real world measurements become available. You’ll learn how the different techniques work and how to apply them.
Optimize your FPGA’s power. Optimize your methodology!
XILINX FPGAs, SoC and MPSoC families
Basic knowledge of FPGA architectures
Basic knowledge of the XILINX FPGA design flow