Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die on a wafer means lower per unit cost.
Meanwhile, design complexity is compounded as chip content grows significantly larger. Chip sizes are significantly smaller, but are running faster into the gigahertz range, and they must consume less power. When designers break barriers to pursue new innovations at advanced nodes, design flaws are common and more costly.
A recent highly publicized glitch in the Intel's chipset captured attention from the semiconductor industry, EDA community, and across businesses and consumers. This is not only because Intel's circuitry powers electronic notebooks and laptops which are ubiquitous in our daily life, but it is also because the cost of the flaw is notable. This news serves as another reminder that similar incidents have happened before, and can happen again.
Details are Challenging
How can we prevent a costly design flaw from happening again? The common wisdom tells us that the devil is in the details. Oftentimes, the last 10% of the task is taking care of few neglected design details. Such tasks can take many iterations to resolve, drain more engineer resources, and extend project schedules. From a digital implementation context, design detail refinements usually relate to the tradeoff between meeting performance and power targets while trying to be compliant with the complex physical, electrical, and process rules and guidelines. For example:
Complex via rules
Complex interconnect rules
The designs at 28nm usually have more aggressive objectives for timing, power and higher density. It is very difficult and sometimes impossible to make corrections at a later stage without a redesign. If the above details are not addressed properly and timely during implementation, they can lead to a functional flaw in silicon, or become the designer's nightmare to fix before tape out. Some predict that more than half of the sub-28nm designs are likely to face re-spins one way or another due to these oversights.
Taking Care of Design Details Through a Unified Design Flow
At the 28nm and below process nodes, having a set of best in class point tools provides a good foundation for design implementation success, but not enough to prevent error oversight. It also requires a consistent method to enforce a tighter design discipline from the start. Encounter Digital Implementation System (EDI System) provides a unified constraint driven methodology with an integrated concurrent signoff analysis flow. It systematically evaluates design constraints, and executes design intents and guidelines down to the smallest implementation details across partition boundaries and design hierarchies.
Many designers from the semiconductor industry, IP providers, and design service companies have already found benefits from this disciplined and unified design flow, and reached design silicon success faster without costly incidents.
To continue to satisfy the design community's insatiable appetite for new innovation, Cadence recently charted a unified path to 28nm silicon realization with the new EDI System 10.1 release. It provides a Silicon Realization flow based on unified design intent, abstraction, and convergence with physical and manufacturing data. A previous blog posting shows how it tackles chip design problems with a unified digital flow.
"Great things are not done by impulse, but by a series of small things brought together" - Vincent Van Gogh