The technological benefits that the 3D stacking of integrated circuits brings have the potential to ease the current chip shortage concerns, according to Cadence Design Systems. As demand for faster processors continues to rise worldwide, the 3D architecture looks all set to replace conventional chip designs.
The microprocessor chip shortage that the world is seeing now is a technological and geopolitical issue. Geopolitics is challenging to predict. Increasing chip manufacturing and boosting supply is also a matter that depends heavily on the business decisions of chip foundries. But at least from a technology perspective, this relatively new system that allows vertical stacking of chips can improve the situation.
“The chip shortage has many different reasons,” explained Vinay Patwardhan, senior director at Cadence. “Some are technical reasons, while others are geopolitical. From a pure technology point of view, this application can provide an advantage over making really large designs. It allows you to make smaller, better yielding designs that can reduce package time and speed up some of the processes.”
Replacing architecture for Moore’s law and beyond
For many years Moore’s law has been the guiding principle – the number of transistors on a chip doubles every couple of years. Most of the roadmaps of all the leading CPU and GPU houses are based on Moore’s law. Over the years, we have seen them showcasing tremendous growth in line with this theory. However, continuing this will be a challenge without significant changes to the design. There are two main reasons for this.
“As the die shrinks approach three nanometers and beyond, the industry is reaching the physical transistor size limit,” Patwardhan said. “There are some 20-angstrom and 18-angstrom processes announced by some of the foundries, but there could be a slowdown of Moore’s law because of the physical transistor size limit being reached.”
For Moore’s Law to continue and before chipmakers to keep innovation going following the curve of Moore’s law, there must be something new that has to be done to add more and more transistors in the same package.
“The other thing is that die sizes of some of today’s GPUs today are large CPUs,” Patwardhan continued. “They’re approaching a limit in terms of reticle sizes. There is an actual physical limit to how big a single die can be. This is based on the lithography machines, the 193-nanometer wavelength machines, which can make reticle size up to 853-millimeter square.”
Some of the die sizes for the recent GPUs and AI processors are very close to that reticle size limit. This means that making bigger chips with more functionality and more transistors in the same die will be impossible.
Patwardhan explains that a simple and elegant solution for these two problems is using the third dimension, wherein you stack chips on top of each other. Stacking chips and using the “z-direction” enables the use of a shorter wire. This will reduce the power requirements and make the timing paths smaller, allowing better performance. This system would reduce memory bandwidth concerns too.
Which verticals are most interested in 3D-IC?
For Cadence, some of the biggest customers for the 3D-IC architecture include hyper-scale companies that build chips for data centers, sensor developers, medical and IoT device makers. Most data centers are still computer-centric, but this is set to change in the coming years as data movement becomes more critical.
“What they require is high amounts of memory available next to the logic,” Patwardhan said. “This speeds up the rate at which data is acquired, moved around, processed, analyzed, and feedback given. So, anybody who’s doing data-centric architectures and designing new processors for data centers will benefit from this technology.”
Another major vertical is companies doing sensors. These companies work with sensor arrays that capture an image or data. These arrays are mounted on top of a control unit that acquires all that data and this is a good application for 3D-IC. Some of the major sensor makers appear to be moving in this direction.
“Some of our customers who are doing IoT or medical devices are also looking at this seriously because it helps them make smaller devices,” Patwardhan explained. “Although it’s stacked, the thickness is less. The small form factor is very attractive to some of those IoT and medical device makers.
The challenges with opportunities
3D IC can definitely solve several issues. But mounting chips on each other certainly comes with its own set of aggregation and design management challenges. The first challenge is pre-deciding the die placement, like what should go on top of what, whether it should be a face-to-face connection or a face-to-back connection.
Secondly, because the two chips are mounted on the same package, chip teams and package teams have to work together more. In 3D chips, the package is an important component. Traditionally, the chip team and the packaging team have worked independently, designing their components to fit each other. Packaging often tends to be in an older technology node, while some chips are in more advanced nodes. It’s difficult to have both represented in the same database.
“This means that there is a lot of back and forth because you’re doing a design and a package separately and have to exchange a lot of information,” Patwardhan said. “This can increase the time and impact schedules. Another point is that 3D IC design requires additional checks besides the standard timing, power, reliability checks. These include system-level checks like thermal analysis and mechanical warpage, electromagnetic interference and crossed tight timing analysis.”
Cadence addresses these challenges through its Integrity 3D IC platform, a central cockpit enabling design planning, implementation, and system analysis. This platform allows the representation of two different technology nodes, easing one of the major challenges. It also provides a flow manager that guides the user through all the extra analyses thermal and timing.
3D to be mainstream soon
To be clear, 3D IC has been around for some time. Researchers and companies have been working on it. But Cadence expects this to become mainstream soon. We may see a lot of test chips over the next year to see how they fit in data centers and other devices.
Patwardhan suggests that once the foundries perfect some of these manufacturing techniques, they may go into mass production as early as the end of 2022 or 2023. Of course, these would also depend on the foundry business roadmaps, but interest and momentum from the hyper-scale companies and other customers indicate such a future for the industry. Digi Times