Show transcribed image textComments: An address is specified in order of row first, then column. You may wish to use a calculator to determine the column and row selection lines. Choose row and column decoder sizes so that the cell array is square. For example, a 32 Times 2 RAM chip consists of 64 cells and the cell array has size 8 Times 8. A 32K Times 8 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. Assuming that the RAM cell array is square, what is the size of each decoder? If coincident decoding had not been used, the single decoder would have had inputs and outputs. Determine in decimal the row and column selection lines that are enabled when the input address is the binary equivalent of (8114)10:
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