From: Fasig, Jonathan L. (email@example.com)
Date: Mon Mar 05 2001 - 06:14:09 PST
Another viewpoint: reset signals are usually active low because you
frequently need them to be well behaved during power-on and power-off
events, when the dc supplies for the circuit are not stable. While it may
be difficult (depending on the logic families used) to generate a good
low-active reset during a power transient, you can see that it would be
impossible to generate a good high-active reset when the power supplies were
below the high logic threshold.
Power-on reset generator circuits can be interesting things to design
because you want them to always give the correct answer, even when their own
power supply is off or below the normal operating point. Years ago
designers sometimes used depletion-mode JFETs to ensure the PowerOnReset
signal was active (low) when the logic supplies were below spec. Today
several IC suppliers offer power supply monitors that work reliably with
supplies as low as a few tenths of a volt. What the logic circuits do at
these supply voltages is up to the logic designer, but at least the -POR
signal will be well behaved. With active-high reset signals you wouldn't
have a prayer.
From: selvaraj subramanian [mailto:firstname.lastname@example.org]
Sent: Sunday, March 04, 2001 10:07 PM
Subject: [SI-LIST] : Why all reset signals are active low?
Why all reset signals are active low?
Can anyone suggest me on this regard.
Which one will be preferrable (active low reset or active high reset) and
thanks in advance.
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