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Non-volatile memory (NVM) circuits have achieved widespread adoptions for code and data storage applications. For example, non-volatile split gate memory cells embedded with silicon nano-crystals have been investigated.
An important aspect of NVM circuits is their performance, which includes endurance (number of programming or write/erase cycles) and data retention after write/erase cycling. Within the industry, the performance of NVM technology has been characterized extensively. Generally, the NVM circuits should be able to endure over 100 thousand to 1 million programming cycles with data retention exceeding 20 years, even at extreme ambient temperatures. Programming the memory to a program state involves, for example, injecting hot electrons into the gate dielectric of the floating or select gate of the memory cell to increase the threshold voltage. Erasing the memory involves, for example, Fowler-Nordheim (FN) tunneling which tunnels electrons to the control gate to lower the threshold voltage of the memory cell.
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A method for forming a device is disclosed. The method includes providing a substrate prepared with a primary gate and forming a charge storage layer on the substrate over the primary gate. A secondary gate electrode layer is formed on the substrate over the charge storage layer. The charge storage and secondary gate electrode layers are patterned to form first and second secondary gates on first and second sides of the primary gate.
A device is also presented. The device includes a substrate with a primary gate on the substrate. The device also includes first and second secondary gates on first and second sides of the primary gate. The secondary gates include a charge storage layer and a secondary gate electrode over the charge storage layer.
These and other advantages and features of the embodiments herein disclosed, will become apparent through reference to the following description and the accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations.
BRIEF DESCRIPTION OF THE DRAWINGS
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In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the present invention are described with reference to the following
FIG. 1 shows an embodiment of a memory cell;
FIG. 2a shows an embodiment of a memory array;
FIGS. 2b-d show different memory operations of a memory array;
FIG. 3 shows a cross-sectional view of an embodiment of a memory cell;
FIGS. 4a-f show an embodiment of a process for forming a memory cell; and
FIGS. 5a-b show a layout of an embodiment of a memory array or sector.
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Embodiments generally relate to semiconductor devices. More particularly, some embodiments relate to memory devices, such as non-volatile memory (NVM) devices. Such memory devices, for example, can be incorporated into standalone memory devices, such as USB or other types of portable storage units, or ICs, such as microcontrollers or system on chips (SoCs). The devices or ICs can be incorporated into or used with, for example, consumer electronic products, or relate to other types of devices.
FIG. 1 shows a schematic diagram of an embodiment of a memory cell 100. The memory cell, in one embodiment, may be a multi-bit memory cell. For example, the memory cell is a dual-bit memory cell capable of storing two bits of data. Providing a multi-bit memory cell storing more than two bits of data may also be useful. For example, the multi-bit memory cell stores 2n bits of data, wherein n≧1. In one embodiment, the memory cell is a multi-bit non-volatile memory cell. Providing other types of multi-bit memory cells may also be useful.
The memory cell includes a transistor 110 with a gate 120. In one embodiment, the gate is a split gate having a primary gate 130 and first and second secondary gates 140a-b. In one embodiment, the secondary gates overlap the primary gate. Providing secondary gates which do not overlap the primary gate may also be useful. The primary gate may serve as a select gate (SG) of the memory cell while the secondary gates serve as control gates (CGs) of the memory cell. In one embodiment, the first and second secondary gates are symmetrical. The first and second secondary gates correspond to first and second bits of the memory cell. For example, a secondary gate corresponds to 2n−1 bits. In the case where n>1, multiple threshold voltage levels may be employed to provide more than one bit per secondary gate.
A gate dielectric layer 134 separates the primary gate from a substrate. Storage dielectric layers 144a-b separate the secondary gates from the substrate and the primary gate. The storage dielectric layers are capable of storing charge corresponding to the bits of the memory cell. In one embodiment, the storage dielectric layer may be a storage dielectric stack having multiple layers. For example, the storage dielectric layer may be an oxide/nano-crystal/oxide dielectric stack. Other types of dielectric stacks, such as oxide/nitride/oxide or oxide/nitride/Al2O3, or storage dielectric layers may also be useful.
The transistor includes first and second source/drain (S/D) regions 150a-b which are provided adjacent to the gate. The S/D regions may be doped regions in the substrate adjacent to the gate. The doped regions include first polarity type dopants for a first polarity type memory cell or device. A doped well may be provided in the substrate in which the memory cell is formed. The doped well is doped with second polarity type dopants. For example, a n-type device includes n-type doped S/D regions and a p-type doped well while a p-type device includes p-type doped S/D regions and a n-type doped well. In one embodiment, the device comprises a n-type device. Alternatively, the device comprises a p-type device.
The gates and S/D regions serve as terminals of the memory cell. For example, S/D regions serve as S/D terminals, the SG serves as the SG terminal and CGs serve as CG terminals. In one embodiment, first and second bitlines (BLs) 170a-b are coupled to the first and second S/D terminals, first and second CG lines (CGLs) 176a-b are coupled to the first and second CGs or secondary gates and a SG line (SGL) 174 is coupled to the SG or primary gate. The SGL, for example, serves as a word line (WL).
Appropriate voltages may be applied to the different terminals via the BLs, CGLs and SGL to perform different memory operations. The different memory operations may include program, read and erase operations. In one embodiment, a program operation comprises injecting hot electrons into the storage gate dielectric layer. This increases the gate threshold voltage. On the other hand, an erase operation tunnels electrons to the control gate. This lowers the gate threshold voltage. When a bit which has been programmed is read, the read current is low due to the higher gate threshold voltage. For a bit which has been erased, the read current is high due to the lower gate threshold voltage. As such, a programmed bit stores a “0” while an erased bit stores a “1”. Providing other configurations of programmed and erased bits may also be useful.
An embodiment of exemplary voltages which are applied to the terminals of the memory cell for different operations are shown in Table 1. In one embodiment, the voltages shown in Table 1 are applied to terminals for different operations of a n-type memory cell formed in a p-type well. Applying other voltages to the terminals for different operations may also be useful.