Except delays and BIOS parameters that set immediate values of reading and writing into the memory, there are also several parameters enabling to configure memory for its optimal interaction with other devices. Here are some of them:
- The parameter “SDRAM Frequency” (DRAM Clock) enables to set the bus frequency on which the memory operates, different from the frequency on which the processor operates. This parameter may have several values: SPD – the frequency is specified by plants wired in SPD-block of memory module; HCLK – the frequency of memory bus is consistent with the frequency of system bus; HCLK+33 (or HCLK-33) – the frequency of memory bus is 33 MHz higher (or lower) than the frequency of system bus. Sometimes the immediate indication of frequencies may be used as the values, for example 66 MHz, 100 MHz, 133 MHz, 200 MHz, 266 MHz, 333 MHz, 400 MHz.
- The parameter “Bank Interleave” (SDRAM Bank Interleave) sets an interleave mode of memory banks. This parameter enables to use the conveyor effect: while one logic bank undergoes a cycle of the contest update, the other one is in active status and undergoes the storage cycle. Such process improves the effectiveness of memory functioning. This parameter may have three values: Disabled, 2 Bank (2-Way) or 4 Bank (4-Way). If your system uses the modules of 16 MB, then this parameter should have the value “Disabled”. Selection of “2 Bank” (2-Way) or 4 Bank (4-Way) depends on the amount of memory: the value “2 Bank” (2-Way) is used for the memory of 32 and 64 MB, and “4 Bank” (4-Way) is used for modules of larger amount or when your system uses several memory modules.