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Phase Lock Loop (PLL)
This example demonstrates the use of the VSS PLL blocks.
The two system diagrams "CE PLL System" and "Real PLL System" illustrate the fact that a PLL design can be simulated using the signal's complex envelope (CE) or the signal itself (real). The data type of the feedback VCO's output node determines if the CE or the real signal is used. The VCO's output node color is red for CE and yellow for real.
The center and sampling frequencies around the loops can be verified with the FRQ_PROP measurements (System/Tools) in the "Propagated Frequency CE" and "Propagated Frequency Real" tabular graphs. The annotations CTRFRQ and SMPFRQ could also have been used to view the frequencies directly on the system diagrams.
The "Control voltage" graph compares the control voltage waveforms of the CE and real simulations. The graph shows the waveforms are similar except for a minor difference in phase.
The "Spectrum OUT" graph compares the power spectrums of the output of the VCOs. The graph indicates the spectrums are similar.
The system diagram "CE PLL System" has its sampling frequency set to 5 GHz. This is done by selecting "CE PLL System" in the project tree and then choosing "Options" from the pull down menu. Under the "Simulator" tab you will note that this project has its sampling frequency set to 5 GHz and it does not utilize the "Default System Options" settings, which set the sampling frequency to 10 GHz. The system diagram "Real PLL System" uses the default system options settings.
The advantage of running in CE mode is a reduction in simulation time, in exchange for the somewhat reduced accuracy that comes with lower sampling rates. For example, issues like the discretization of the loop filter (via bilinear transform, see the online help for 2ND_PASS) or the accuracy of prediction of zero-crossings have a lot to do with the selection of sampling frequency, with more accurate results for higher sampling frequency. Of course, issues like simulation time or resolution bandwidth in spectrum plots then become important, so usually a compromise is sought. The availability of the CE mode of running a PLL makes finding this compromise easier.
The "Real PLL System" uses a sampling frequency of 10GHz and takes longer to run than the CE system.
In both system diagrams a 225 MHz reference oscillator is used with a divide ratio of 4, forcing the VCO to stabilize at 4 x 225 = 900 MHz. The 10 GHz and 5 GHz sampling frequencies of the real and CE systems, respectively, have been chosen to illustrate the fact that the sampling frequency does not need to be an exact multiple of any particular frequency in the system, including both the VCO output and the reference frequencies.
Running the PLL simulation in real mode allows you to monitor the resulting time domain waveforms before and after the DIVIDER block. As expected the output of the divider (the black waveform) has a 4.44ns period, corresponding to its frequency of 225 MHz = 900/4 MHz. You can also monitor similar waveforms in CE mode by using the CE2R block found in Converters / Complex Envelope to convert the complex envelope signals to the equivalent real signals then viewing those waveforms.
Note that the current from the charge-pump (CP) is never identically zero, even during lock, as the delay of the resetting feedback NAND gate inside the PFDCP block (see the online help for the block) causes pulses of very small duration (hence small amplitude in our sampled environment) to appear even when the two inputs of the PFDCP are in perfect lock.
Additional Note 1: Sampling Frequency:
For purposes of illustration try setting the sampling frequency of both system diagrams to 1 GHz. Note that in CE mode the PLL will still “lock”, and that the resulting spectrum is similar to the previous spectrum. This is because narrowband CE signals around the center frequency are enough to include the basic waveform information. However, the PLL simulation in real mode does not have a high enough sampling frequency to resolve the 900 MHz signal and the results are meaningless.
Additional Note 2: DIVIDER (Real mode):
The division ratio of the divider block (DIVIDER) is controlled by the input connected to node 2. In this case, a SRC_R is used to set the division ratio to 4. If input node 2 is left disconnected then the DIVIDER's N parameter sets the ratio.
A fractional-N PLL can be simulated by using the DIVIDER's input node 2. Only integer control values can be used.
If the division ratio is 1, the output of the divider just repeats the input, no squaring is performed.
The output of the divider has a duty cycle dependent on the division ratio. The output waveform goes to +Vp at the first Upward-Zero-Crossing (UZC) and goes back down to -Vp at the second. To obtain a 50% duty cycle, you would need to end a chain of dividers with a divide-by-2 (N=2).
The output waveform of the divider can (and does) exceed +/-Vp at the crossing points so that the location of the zero-crossing can be preserved for the PFDCP that follows. The plot "DIV WVFM" needs to be manually scaled for this reason.
Additional Note 3: DIVIDER (CE mode):
Please note that the output of the VCO is a red triangle, to indicate CE.
Unlike in real mode, the division ratio in complex mode can be fractional, both as parameter N (inside DIVIDER) and as set by input node 2.
The parameter N divides the center frequency of the input.
For more information on the blocks used in the system diagrams please read the online help for those blocks.