VLSI Implementation of Adders for High Speed ALU
In this paper, the authors are primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance of Central Processing Unit (CPU). Design of a high speed single core processor is the future goal of this paper. Single core processor would have many advantages over a multiple-core approach. Task execution on a single core is a well understood process, while execution on many cores is a problem that has not yet been solved.