1. Use appropriate bypass capacitors (usually 0.1 µf and 1 µf) between VDD1 and GND1 and VDD2 and GND2.
The capacitors should be placed as close as possible to the package. See the data sheet for exact details.
2. Place bulk capacitors (10 µF) close to power components.
3. Connect Enable pins either to the VDD or GND plane or use 10 kohms pull-up resistors. It is not recommended that they be left floating. This is especially critical in noisy environments.
4. Use 45° bends instead of right-angle (90°) bends for signals. This enhances impedance matching.
5. To reduce inductances, avoid changing layers with signals.
6. Use power and ground planes to control impedances and minimize noise from power components.
7. Use short trace lengths between isolator and connecting circuits.
8. To enhance the robustness of a design, it is further recommended that the user also add 1 µF bypass
capacitors and include 100 ohms resistors in series with the inputs and outputs if the system is excessively noisy.