Simplest of the lot. Has 2 separate timers which are controlled by TCB. Also has circuitry to divide 1 MHz input clock frequency to provide other frequencies required for device operation. Timers are both comprised of 4 7490 cascaded decade counters. Reason that BCD coding of timer data was chosen was so that codes A-F could be used as control codes in remainder of circuit. When timer is enabled, it counts up at a frequency determined by a jumper until an external event sets a flag which disconnects the clock from the timer. This flag is detected by TCB and once timer contents have been read, this flag is cleared allowing it to start counting again. In the event that the timer overflows, an overflow FF is set which sets timer flag (thus disconnecting clock from timer) and forces the contents of most significant digit to F; thus overflow is represented by F000.
There's not much to say about this device as it is so simple. It was the only circuit that functioned perfectly once wired up and did not require any changes to the design. One problem which did crop up in operation was the accumulation of timer dead times which was as a result of the timer not counting up while it was waiting to be read. Even though this was only on the order of 8-18 microseconds, it was noticeable in that summing the times for each individual timer over long intervals did not give the same result, and the difference was greater the longer the interval being timed. This was especially noticeable when two fast firing cells were used as input for 10+ minute recordings. (At least this is what I assume is the explanation).
What I would do now would be to use setting of timer flag to load a buffer register with the timer count and immediately resume counting. This would complicate design considerably since it would require addition of 2 16 bit latches as well as additional logic to check for the condition of the buffer not being read before the next timer count was available. On the other hand, since I could use tri-state latches, it would cut the number of output lines from this board from 32 to 16 . . .
Enough, digital design is a lot of fun, but now the chipset of every AT class machine has 2 available 16 bit latched timers/counters as part of the circuitry and the 1976 design if going to remain as is.