Reliable Miniaturization Technologies for Electronics
3D Technology Concept
The 3D technology concept consists of interconnecting electronic devices which have been stacked along the Z dimension. As in the following illustration, the electronic devices are first placed horizontally alongside one another on a Layer and internally connected. The Layers are then stacked vertically and connected thanks to a vertical interconnection technique.
3D Plus portfolio of patented and leading edge stacking technologies starts with standard packages scale upward to die-size and wafer level stacking processes.
Although the detailed process flows can be different, our stacking technologies all rely on the same four Key principles:
- n-High(*) Stacking of heterogeneous non modified standard die, wafer, packages and passive components
- Excellent yield thanks to the test/screening of each layer before stacking
- High reliability Bus Metal - Edge interconnection techniques (cold process)
- Use of very simple and well proven technologies
(*) n-High means a stack of n levels.
They allow gaining a factor of at least 10 on size and weight of the components comparing to existing solutions, and with a capability of stacking up to 10 semiconductor devices within 1mm, 3D Plus Ultra Low Profile Modules are unique.
Our technology offer responds to a diverse range of needs and requirements going from low volume-space qualified up to high volume-industrial applications. It is the only one in the world that is qualified for Space applications by the major Space agencies ESA, NASA, JPL.
- Standard Packages StackWith the capability to stack n-High any standard packages from the industry, this process flow is based on very simple and well proven technologies. A large products portfolio using this technology relies on TSOPs packages. This capability domain is also qualified by European Space Agency (ESA) for Space application. Read More
- Flex Process – Die StackWith the capability to stack n-High any non modified standard die (even with different sizes and technology), this process flow enables to embed the best semiconductors together in one single highly miniaturized package. High reliability and resistance to harsh environments, and very good manufacturing yield are also key benefits of this die stacking technology.Read More
- Flex Process – SiP StackThis process has the unique capability to stack n-High any heterogeneous active, passive, Opto-electronics and MEMS/MOEMS devices in a single highly miniaturized package. This is the most efficient technology for building complex System-In-Packages (SiPs). This capability domain is also qualified by European Space Agency (ESA) for Space application.Read More
- Wafer Level Stack - WDoD™Based on the use of standard wafers (die without « TSV »), and with the capability to stack die with different sizes up to 10 levels, our wafer level stack technology named WDoD™ (Wirefree Die-on-Die) achieves smaller form factors and Ultra Low Profile 3D stacks.Read More
- 3D Stack - Road MapsRoad Maps for standard packages stacks, Die stacks and Wafer Level stacks based on “TPV” (Thru-Polymer Via) summarize 3D Plus present and future capabilities in terms of SiP stacks complexity, and overall form factors and level thickness.Read More