Timing within all digital and most mixed analog/digital systems comes down to one device—the clock generator. But with mounting system complexity, a single clock oscillator delivering just one digital signal is no longer adequate. These days, systems may require a half-dozen or more clock signals, each at a different frequency.
Programmable clock generators to service these needs are available. Most, however, must either be factory programmed via a metal mask, or inserted into a programming tool, for configuration before mounting to the circuit board. Also, these solutions offer limited flexibility and cannot be updated if a better set of timing parameters is developed.
To solve this flexibility issue, Cypress Semiconductor has developed the CY27EE16ZE programmable clock chip, which adds 2 kbits of nonvolatile in-system programmable EEPROM storage to a programmable clock generator. Mounting the chip on the circuit board prior to configuration permits programming and testing of the clock. If necessary, it can also be reprogrammed in the system through its inter-IC (I2C) bus interface. Manufacturing engineers can maximally optimize the timing signals on the target circuit board based on test results. Ultimately, this achieves a better performing system.
Beyond its in-system configurability, there are another 16 kbits of in-system programmable EEPROM, which can be divided into eight 2-kbit blocks or be used as a contiguous 16-kbit array. Each block serves one of two functions. It can store more configuration setup patterns, letting the chip quickly switch between setup parameters for various clocking schemes. Or, the host system can use the memory to store various system parameters or transitory information. In this case, the on-chip memory would help simplify system design by eliminating a separate EEPROM that might typically be placed on the circuit board.
The CY27EE16ZE is the first in a family of in-system programmable EEPROM-based clock generators. Its single phase-locked loop (PLL) can be configured via bits held in the 2 kbits of EEPROM configuration memory (Fig. 1). The clock chip delivers up to six clock outputs, which, depending on input frequency range (8 to 30, 1 to 150, or 1 to 167 MHz), span 80 kHz to 200 MHz. Future versions of the clock chips will include multiple PLLs and different output configurations.
The heart of the chip, its programmable clock core, consists of a PLL with programmable drive and programmable load. It supports external reference frequencies of up to 166 MHz. The PLL features programmable product (P), divisor (Q), offset, and loop-filter parameters for setting the output frequency and related parameters.
Two programmable linear dividers and a crosspoint switch array send the PLL output to as many as six clock outputs. The output swing of the first four clock outputs (CLOCK1 through CLOCK4) is determined by the supply voltage on the VDDL pin (2.5 or 3.3 V), while the VDD pin (3.3 V) sets the output swing of CLOCK5 and CLOCK6.
To minimize radiated noise, the chip can use spread-spectrum techniques for reducing electromagnetic radiation. The on-chip voltage controlled oscillator also is controllable via an analog signal. Setting the configuration memory so one package pin functions as an analog input achieves this. The analog signal applied to the pin enables the crystal oscillator frequency to be adjusted by ±150 parts per million. (Of course to do this, the crystal must have a minimum pull range of ±150 ppm).
Designers transitioning from classic metal-can oscillators that provide system clocks to the PLL-based clock generators must make a big adjustment when it comes to "accuracy." Most often, accuracy is expressed as a ppm error from the ideal or expected result. For a clock generator required to deliver 100 MHz, the actual signal can span 99.99 to 100.01 MHz if the error is 100 ppm. That number may seem large in light of the apparent "perfect" output of a metal-can oscillator marked at 100.00 MHz, but it isn't. If you check the data sheets, you'll probably find that metal-can oscillators also have some error budget.
PLL-based clock generators use a reference clock to generate another clock running at a different frequency. Basically, the output clock equals the input clock times the ratio of the feedback divider, divided by the reference divider. Usually, the dividers are integer dividers, so the calculations sometimes result in an approximation of the desired result. Thus, there's a ppm error.
Although the error budget in a system must account for error due to the clock generator, error from the crystal itself is often overlooked. The crystal's error could be 20 to 100 ppm, depending on the crystal used. Total system error is the sum of the two errors, so the PLL's error may not be as large an issue as initially expected.
The clock generator's wide-ranging programmable capabilities make programming the chip somewhat complex if approached register by register. To address this, a simple graphical user interface was created as part of the company's CyberClocks programming and configuration software tool suite (Fig. 2, top). With this software, clock design is simplified to a "black-box" approach. Designers simply type in various parameters that the software compiles into a bit stream and loads into the chip.
The software actually does a lot more, performing extensive computations on the timing requirements and parameter settings, and it can optimize the resulting configuration settings to meet all performance parameters. Throughout the programming process, the software employs structured design-rule checking to ensure that the PLL system achieves stability under all valid programming conditions and data-sheet parameters. All of this is transparent to the designer. The software also offers an expanded user interface. Here, designers more familiar with clock setup have access to the full register set for complete manual control of the configuration process (Fig. 2, bottom).
The software accepts user-specified ppm error tolerance specifications or output frequency deviations. Those values are used to set error boundaries in the optimization algorithms that examine all permutations before displaying its optimized results. It does that by building an abstract tree structure that represents the silicon routing structure. A dynamic rules validation structure, associated with the construction of every tree element, determines if a valid solution exists. Up to three best-fit solutions are stored for user analysis. Once the computations are complete, the designer can implement the derived solution or tweak the results.
The CyberClocks software will initially be offered as a standalone program that can run on a PC and either tie into a low-cost device programmer, or into an interface that can directly program the chip when it's in the system. By mid-2003, the company plans to offer a Web-based version of the software. So, designers will always have the latest revision of the software at hand.
Price & Availability
In lots of 10,000 pieces, the CY27EE16ZE costs $2.45 each and is offered in a 20-lead, thin, shrink small-outline plastic package. It's sampling now. Software is immediately available and can be freely downloaded from the company's Web site. The programming unit that attaches to a PC sells for $199 plus the cost of a part-specific adapter (about $70).
Cypress Semiconductor Corp., 3901 North First Street, San Jose, CA 95134; (408) 943-2600, www.cypress.com.