is an expression, an aggregate of elements into a composite type.
Without seeing the declaration for we can imagine it's an array type, an array type is a composite type (made of one or more elements).
An aggregate combines one or more values as elements into a composite type.
Notice the opening and closing parentheses are required.
Those elements can be associated positionally by name for a record type or by index value position for an array type.
The element association is governed by choices.
The element association can cover more than one choice.
A choice can represent one or more elements.
An element simple name is used for a record type or an array type with an index type that is an enumerated type.
is always the last choice and stands for all the remaining choices for that type. The type can be discovered in an assignment from the target. In some instances the type is required to be supplied explicitly, as in a qualified expression.
The element association stands for all other elements of the type of the aggregate. In this case the type and subtype of , where a subtype indication specifies a range index of elements of a std_logic_vector.
The expression is required to be of the element type, and the aggregate stands for a value of the subtype of comprised of 's for each of the elements of in this case.
When looking to understand what's happening in a HDL in general, it's a good idea to think about what's going on in the actual hardware. There isn't a concept of "execution" in an FPGA in the same way that there is in a CPU. I was taught that when you read a concurrent statement, you read it as .
In hardware, the above concurrent statement (), is the equivalent of this:
simulate this circuit – Schematic created using CircuitLab
When does the output change? After the input changes + some delay that's a characteristic of the chip. Is this called execution? No.
Processes are constructed using flip flops which are clocked. For example, this:
simulate this circuit
Since the flip flop is clocked, the driven outputs only change on the clock edge, even though the input may have changed sometime before. Could this be called execution? No.
Writing HDL really needs a change of mindset away from the CPU to a place where you actually consider the hardware implications of what you're coding. You're describing the hardware.
As an exercise, take a look at the final block diagram for the code that you write once it's been built and see if you can identify where the concurrent statements are and where the processors are. it's quite interesting to see.
Disclaimer: I've simplified what's going on in the FPGA quite a bit. It doesn't use discrete gates and I don't think it uses D-type flip flops either, so there are some inaccuracies here, I picked those components for illustration purposes.
answered Jun 10 '14 at 7:19