Here is a picture taken at WIRA of a 0-silicon Rainier wafer. The left-most chiplet in the middle is an 8-qubit unit cell break-out. The chiplet to the right of this is a 2×2 array of unit cells (32 qubits). The chiplet to the right of that is a 4×4 array of unit cells (128 qubits). Each wafer contains several hundred of each. There are several more layers of metal that are added after this step that cover up the underlying circuitry, making an optical photo at this stage more interesting than at later stages where it’s like taking a picture of a mirror. At WIRA you can see a lot of cool stuff. Most of what you’re looking at here is the digital SFQ circuitry used to program a problem instance.