The PowerPC 7450
When Motorola introduced MPC7450 in January of 2001, it represented such a significant departure from the previous MPC74xx designs that Apple would have been justified in naming it the "G5." For whatever reason, though, Apple decided to stick with the G4 label, and the chip subsequently became popularly known as the G4e. The new processor had a slightly deeper pipeline, which allowed it to scale to higher clock speeds, and both in front end and execution cores boasted a whole host of improvements that set it apart from the original G4. The G4e also continued the excellent performance/power consumption ratio of its predecessors, which, when combined with its enhanced vector computing performance, made it a great platform for embedded digital signal processing (DSP) and media applications.
This large diagram shows the basics of the G4e's microarchitecture, with an emphasis on representing the pipeline stages of the front end and execution core.
Before instructions can enter the G4e's pipeline, they must be available in its 32K instruction cache. This instruction cache, together with the 32K data cache, makes up the G4e's 64K L1 cache. An instruction leaves the L1 and goes down through the various front end stages until it hits the execution core, at which point it is executed by one of the G4e's eight execution units (not counting the branch execution unit, which we'll talk about in a second).
As I've already noted, the G4e breaks down the G4's classic, four stage pipeline into seven, shorter stages:
- Write-back (Commit)
Notice that the G4e dedicates one pipeline stage each to the characteristic issue and complete phases that bracket the out-of-order execution phase of a dynamically scheduled instruction's lifecycle.
Let's take a quick look at the basic pipeline stages of the G4e, because this will highlight some of the ways in which the G4e differs from the original G4. Also, an understanding of the G4e's more classic RISC pipeline will provide us with a good foundation for our upcoming discussion of the Pentium 4's much longer, more peculiar pipeline.
Stages 1 and 2 - Instruction Fetch
These two stages are both dedicated primarily to grabbing an instruction from the L1 cache. Like its predecessor, the G4, the G4e can fetch up to four instructions per clock cycle from the L1 cache and send them on to the next stage. Hopefully, the needed instructions are in the L1 cache. If they aren't in the L1 cache, then the G4e has to hit the much slower L2 cache to find them, which can add up to 9 cycles of delay into the instruction pipeline.
Stage 3 - Decode/Dispatch
Once an instruction has been fetched, it goes into the G4e's 12-entry instruction queue to be decoded. Once instructions are decoded, they're dispatched at a rate of up to three non-branch instructions per cycle to the proper issue queue.
Note that the G4e's dispatch logic dispatches instructions to the issue queues in accordance with the four dispatch rules given in the previous chapter. The only modification to the rules is in the issue buffer rule; instead of requiring that the proper execution unit and reservation station be available before an instruction can be dispatched, the G4e requires that there be space in one of three issue queues.