Having gotten word that Flash, SRAM, and DRAM will be hitting the wallat or around the 45 nanometer (nm) technology node, embedded designersare looking for the Holy Grail ofmemory as the industry moves in lockstep into smaller and smallergeometries.
But, scalability is only one issue facing conventional memory. SRAM is experiencing problemswith increased leakage power, andFlashis experiencing endurance issues as well. Memory vendors are comingforward with alternative solutions. These include phase-change RAM (PRAM) , ferroelectric, resistive RAM, as well asconventional magnetic RAM. Each poses its ownset of limitations.
As vendors put extra touches on these candidates to make them moreattractive to embedded designers, traditional SRAM and NOR and NAND flash are facing theirdifficulties. SRAM continues to tout its high speeds. But the problemis it doesn't scale very well; it has cell instability, and suffersfrom leakage current, which only gets worse beyond 45 nm. These issuesare especially problematic for mobile applications.
The traditional flash floating-gate technology willscale to around 45 nm. Afterward, novel device structures and arrayarchitectures will be required. Currently, a multiple level cell(MLC)architecture is used to improvethe density of NAND flash, although existing devices with MLC have arelatively slow write speed of 800 microseconds. Also, flash enduranceis an issue with the MLC flash attaining as low as only 1500 cycles.
Scalability below 45 nm is the main issue inDRAM camps. As feature sizes decrease, the DRAM's capacitor elementis not able to maintain the necessary charge. DRAM vendors are nowtrying to remedy this issue by creating three-dimensionalcharge-holding elements or using other novel circuitry to create abigger capacitor. Otherwise, the technology will not be reliable. Asecondary issue is that the DRAM process is not compatible withembedded applications.
Spin-transfer torque RAM asuniversal memory
Against this backdrop of near-term issues, Grandis' spin-transfertorque RAM (STT-RAM)technology is the front runner because it offers embedded designersthe best of all worlds. It combines non-volatility, excellentscalability and endurance with lower power and fast read and write.
Spin-transfer torque (STT) writing is a technology in which anelectric current is polarized by aligning the spin direction of theelectrons flowing through a magnetic tunnel junction (MTJ) element.Data writing is performed by using the spin-polarized current to changethe magnetic orientation of the information storage layer in the MTJelement. The resultant resistance difference of the MTJ element is usedfor information readout.
STT-RAM is a more appropriate technology for future MRAM producedusing ultra-fine processes and can be efficiently embedded insubsequent generations of such semiconductor devices as FPGAs,microprocessors, microcontrollers and systems-on-a-chip (SoC). Aspecial bonus for embedded designers is the fact that the internalvoltage STT-RAM requires is only 1.2 Volts.
Hence, it can operate with a single 1.5 Volt battery, whereas DRAMand flash require charge pumps to supply higher voltages. Existing NANDflash technology requires the internal voltage to be raised to 10 to 12volts for write operations. That voltage is boosted with the help of acharge pump, which requires considerable power and presents adversedesign conditions for embedded designers.
Another major benefit STT-RAM technology hands embedded designersis low writing current on the order of 100 to 200 microamperes at the90 nm node, thanks to its efficient spin-transfer torque techniques. Atthe 45 nm semiconductor node and beyond, writing current continues toscale down significantly below 100 microamps. This lower currenttranslates to a denser, less expensive memory.
A quantum property of an electron is the spin, associated withmagnetism. The foundation of spin-based electronics or spintronics isformed by devices that rely on an electron's spin to perform theirfunctions. Over the years, since vacuum tube days, system engineershave known electronics to be based on charge-based devices. Thesetraditional electronic devices move electric charges around in asilicon chip or IP core. However, up to now, the spin related to eachelectron has been largely ignored.
At Grandis, our engineers have invented ways to exploit theelectron's spin to create a new, highly novel, and efficient way tocreate universal memory circuitry known as spin-transfer torque RAM.Nanomagnets are used to control the spin. By passing electrons throughthe nanomagnet, the spin of the electrons can be aligned in the samemagnetization direction as the nanomagnet.
As shown in Figure 1, below a magnetic tunnel junction (MTJ) is at the heart of a STT-RAM bit cell.The MTJ consists of two ferromagnetic electrodes with a thin insulatinglayer in-between. The top nanomagnet is the storage layer or “free”layer; the middle is the barrier; and the bottom nanomagnet is thereference or “pinned” layer or spin filter.
Spin transfer switching (STS) changes the MTJ's state fromantiparallel or “1” to parallel or “0” and vice versa. This isperformed by running current from the top to the bottom of the MTJ andvice versa. An STT-RAM chip addresses each bit individually by flowingcurrent directly through the bit.
Consequently, unintended writing errors are completely eliminated. Aconventional CMOS transistor below the MTJ produces the current. Inthis instance, switching is performed via spin polarized currents. Bypolarizing the current, data is passed from the fixed MTJ layer that isthe polarizer to the free MTJ layer.
This process is called spin-transfer torque switching. Currentrunning through the fixed layer polarizes the electrons. Thosepolarized electrons then affect the switching of the free layer, hencethe parallel and anti-parallel configurations.
|Fig.1. STT-RAM addresses each bit individually by flowing current directlythrough the bit. Unintended writing errors are completely eliminated.|
Unlike the STT-RAM cell that exploits electron spins for writing,the conventional MRAM cell, shown inFig. 2a below at 20 to 30 F2 cell size uses amagnetic field toperform switching. When the cell is activated, the bit line and writeword line become active with current pulses flowing through them, thuscreating a magnetic field around the bit.
It is this magnetic field that changes the state of the bit from “1”to “0” and vice versa. The scalability issue is exacerbated as aconventional MRAM chip is subjected to increasingly smaller geometries.As feature size shrinks, more current is required to create themagnetic field.
|Fig.2a ” Conventional MRAM cell. A magnetic field, generated by the bitline, cladding, and write word line, is used to switch between the “0”and “1” states.|
In a conventional MRAM cell, conductors or wires above and below theMTJ are used to generate the fields necessary to switch the state ofthe free magnetic layer. The additional write word line and bypass linerequired in this cell geometry translate into a more complicatedarchitecture. Hence, more lithographic steps and a more costlymanufacturing process are required.
Each conductor or wire requires a minimum of 5 to 10 milliamperes(mA) of current to perform a switch. Conversely, STT-RAM technologyincurs a considerably lower switching current on the order of 100microamperes, as a result of its more efficient spin-transfer torquetechniques.
Magnetic fields produced by first-generation switching methodstypically expose an entire column or row of bits, leading toinadvertent bit or write errors. As conventional MRAM technology isscaled and memory cells become smaller, the cells must be structuredwith an increasingly higher switching field to maintain each cell'sthermal stability. Otherwise, the probability of write disturbanceincreases.
A cell's thermal instability can erroneously trigger randomswitching to the opposite state. This means the cell stability inconventional MRAM demands an increasingly higher current flowing in theconductors or wires to efficiently switch states. Due to this bit orwrite disturbance, the number of bad bits in conventional MRAM is veryhigh. Consequently MRAM vendors must resort to redundancy architectureswith as much as 25 percent redundancy.
|Fig.2b ” STT-RAM cell. By eliminating the write word line, bypass line andcladding, a STT-RAM cell is considerably smaller than a conventionalMRAM cell.|
Shown at a cell size of 6 F2 , the STT-RAM cell, Figure 2b, above, on the other hand,does not require the metal wire below the MTJ. The write word line,bypass line, and cladding associated with the conventional MRAM cellare eliminated. Instead, current flows perpendicular through the MTJmemory cell. As STT-RAM technology is scaled and its cells becomeincreasingly smaller, the cross-sectional area becomes smaller andsmaller.
Because STT-RAM uses a current running through the cell, therequired writing current that flows through the smaller MTJs decreases.As a result, STT-RAM has superior scaling properties. That is thereason total required current in STT-RAM continues to be considerablyless with increasingly smaller geometries, whereas in conventionalMRAM, the required switching current increases with scalability, asshown in Figure 2c, below .
|Fig.2c ” Total required current in STT-RAM continues to scale lowerwith increasingly smaller geometries. Conversely, conventional MRAMswitching current increases with smaller geometries.|
Attempts have been made to correct the half-select bit writedisturbance issue with conventional MRAM by modifying its bit cell. Onesuch technique is the toggle MRAM bit cell. Its intent is to increasethe operating window of the write operation. The objective is to createa significant margin between the level of fields required for switchingall bits and the level at which write disturbs occur.
The toggle MRAM bit cell adds a second free magnetic layer and ananti-ferro-magnetic coupling layer above the first free magnetic layer.Studies performed by the conventional MRAM vendor reveal an increasingpercentage of bits properly switch as a result of applying the newtoggle MRAM bit cell. However, it incurs higher currents (nearly 2Xhigher) and tighter thickness control is required (control within oneatomic layer).
As shown in Table 1, below, STT-RAM technology will provide embedded designers better featurescompared with conventional memory technologies and future “universalmemory” candidates.
With a two nanosecond (ns) write time, STT-RAM is as fast asSRAM, which currently has a write timeranging from 1 to 100 ns, depending on the technology used. As far ascell size, STT-RAM fares much better than SRAM cell size. When STT-RAMreaches the 32 nm technology node, the cell will be equal to or smallerthan DRAM or NOR flash.
|Table1. Memory technology comparisons.|
Today, STT-RAM can replace both NOR flash and SRAM in many embeddedapplications. Non-volatile storage uses NOR flash for storing code,with that data being transferred to SRAM acting as buffer or cachememory. Low-end cell phones for example use both NOR and SRAM, whichcan easily be replaced with a single STT-RAM chip.
Comparing STT-RAM with recent universal memory candidates, read andwrite/erase time are each at 2 to 20 nanoseconds (ns) for STT-RAM,while phase-change RAM (PRAM) takes 20 to 50 ns for a read, 30 ns forwrite. Further, STT-RAM endurance is unlimited at >1015 while PRAMis less than 1012.
Although it is not a new technology, PRAM has recently receivedconsiderable attention. A number of leading semiconductor companies areinvesting in PRAM and developing their own sets of IP. While it is anadmirable technology, PRAM has limited endurance and slow speedcompared with STT-RAM.
Chalcogenidematerial, usually Ge2Sb2Te5 also known as GST, is used in a PRAM fordata storage. The PRAM uses the reversible phase change between thecrystalline and amorphous states of Chalcogenide GST by applying heat.Crystalline GST has low resistivity and amorphous GST has highresistivity. The data “0” corresponds to the crystalline state, whiledata “1” is associated with the amorphous state.
Switching time between states is larger than 20 ns, which meansPRAM cannot replace SRAM since it is considerably slower. The timerequired to reset the state of the bit must be made long. If it is not,the phase change material cools too fast to achieve the crystallinestate. Further, due to the constantly changing of the phases and theheat applied to them, there is material degradation and thereforelimited endurance.
RRAM, or resistive memory, relies on a resistance change caused byan electric field. It is in an earlier state of development comparedwith PRAM, but suffers similar problems in terms of reliability andendurance. In addition, the switching mechanisms involved in the manyproposed RRAM materials are not well understood.
FRAM, or ferroelectric RAM, uses a ferroelectric material to store apolarization. It suffers from limited read endurance and a destructiveread process. Also, its endurance of around 1012 cycles, while suitablefor a flash replacement, cannot be used as universal memory.
STT-RAM Application Outlook
STT-RAM is a disruptive technology that can revolutionize theperformance of products in many areas, from consumer electronics andpersonal computers to automotive, medical, military and space.
It also has the potential to create new sectors in the semiconductorindustry and enable entirely new products not yet envisaged. Grandis iscurrently collaborating with key strategic partners and semiconductormarket leaders to commercialize STT-RAM technology and accelerate itstime to market.
STT-RAM has key initial markets replacing embedded technologies suchas eSRAM, eFlash and DRAM, and providing new functionality at 65 nm andbeyond. In automotive applications, it has higher speed and lower powerthan eFlash and is denser than eSRAM.
In portable and handset applications, it can eliminate multi-chippackages (MCPs), provide a unified memory subsystem, and reduce systempower consumption for extended battery life. In personal computers, itcan replace SRAM for high-speed cache, Flash for non-volatile cache,and PSRAM and DRAM for high-speed program execution.
Farhad Tabrizi is president andCEO, Grandis,Inc.