The buck regulators in these systems must generate point-of-load (POL) voltages as low as 0.6V for the GPUs, FPGAs, DSPs and other higher current devices receiving their power from a 5V or 3.3V primary supply rail as shown in Figure 1. Several clever IC design choices have yielded a new generation of 3A, 4A and 5A synchronous buck regulators able to address the varying load requirements from entry-level to luxury automobiles. To help system designers understand their benefits, it is useful to understand the architectural choices made when developing these fully integrated devices, as there are many different ways to implement a buck regulator.
This article examines the asynchronous buck versus synchronous buck configuration. We’ll also discuss the tradeoffs N-channel or P-channel transistors used for the switches in the synchronous buck configuration. We’ll then highlight a family of fully optimized 3A, 4A and 5A sync buck regulators, and show how their wettable flank QFN packages pass visual inspection during the printed circuit board (PCB) assembly process.
The Asynchronous Buck Regulator
As you can see in Figure 2, the asynchronous buck DC/DC converter has one switch (S1) that is driven on and off to control the duty cycle ratio. The circuit includes a diode that acts as a secondary switch when the potential across it causes forward biasing. When switch S1 is on, the input voltage is connected to the inductor, causing current to build up in the inductor until switch S1 is shut off. When S1 is switched off, the current flowing through the switch to the inductor is interrupted.
However, due to the nature of the inductor, the current flowing through it wants to continue flowing in the same direction. For this to happen, the voltage polarity across the inductor changes, allowing the current to flow