The following diagram shows an example of the memory map for a PIC32MZ device (PIC32MZ2048EFG100) with 2048 KB of program memory for a typical application running in Kernel mode, after the start-up code has executed:
The segments, KSEG0 and KSEG1, both translate to physical address 0x0 and include all of program Flash and data memory; however, KSEG0 is cacheable and KSEG1 is not.
This arrangement allows the Central Processing Unit (CPU) to access identical physical address space from the virtual segment of KSEG0 and KSEG1 so that the application can choose to execute any or all code as either cached or uncached by branching or calling the function in the cached or uncached region. The uncached region, KSEG1, provides virtual address space translation to the Special Function Registers for PIC32MZ family devices.
Note that XC32 will place all c-runtime startup code starting at virtual address 0xBFC00000 in KSEG1. Recall that this region (KSEG1) is the only one guaranteed to behave properly from system reset. 0xBFC00000 is translated (via a fixed mapping) to physical address 0x1FC00000 (Boot Flash Memory).
KSEG2 maps to external memory, which is connected to the device through the SQI and EBI modules using the Translation Lookaside Buffer (TLB).
There are two additional virtual memory segments: a user segment, KUSEG, which occupies the lower 2 GB of virtual memory, and KSEG3, which occupies the upper most 512 MB block of memory. For information regarding the use of these segments and their configuration using the TLB, please refer to Section 50. CPU for Devices with MIPS32® microAptive™ and M-Class Cores (DS60001192).
Physical addresses, shown on the right, are used by DMA, the Flash controller (when programming Flash memory), and when defining protected memory regions. Virtual addresses are used by the CPU for fetching and reading or writing data or peripheral SFRs.
Keep this in mind when setting up these modules.