Intel will use quantum well FETs starting with its 10nm process, said David Kanter in an analysis posted on his Real World Technologies Web site. The new transistor structures will use two new materials – indium gallium arsenide (InGaAs) for n-type transistors and strained germanium for p-type devices, he said.
If correct, Intel could gain a capability as early as 2016 to produce 10nm transistors as much as 200 millivolts lower in power consumption than the rest of the industry. Kanter expects other chip makers will not be able to catch up with the techniques until their 7nm node, at least two years later.
It could take more than a year before Intel discloses its 10nm plans, Kanter said, giving his own predictions an 80-90 percent confidence level.
Kanter’s analysis is based on a study of about two dozen Intel research papers mainly presented at the annual International Electron Devices Meeting (IEDM), a leading gathering of chip makers. He also analyzed as many Intel patents related to chip making.
“Everything I saw pointed in this direction,” Kanter told EE Times. “The question is not will Intel do quantum well FETs, the question is will it be at 10 or 7nm,” he said.
“Using compound semiconductors in the channel is not unique to Intel’s research, but it’s clear no one is quite so far along as Intel publishing on them,” Kanter added. “Intel’s papers and patents on germanium were more scarce, but that technology is more well understood,” he said, noting he expects Intel to adopt pure germanium although it may progress via a half step to silicon germanium.
Kanter provided Intel a look at his article before it was published. The chip maker declined to comment on it.
About the author:
Rick Merritt, Silicon Valley Bureau Chief, EE Times