The designs of an IC, its package and its target system board have traditionally been separate development processes driven from common specifications. The system designer has typically relegated final resolution of all design issues to the back-end integration phase of the design cycle. But today's constantly shrinking silicon, the drive toward ever-smaller, lower-cost and more powerful boards and systems, and the relentless pressure to quickly deliver designs to market demand a new co-design approach.
The design and analysis of the system interconnect is currently performed using a highly fragmented set of design processes across dissimilar design environments. This is largely true for three main reasons: different manufacturing scales, materials and processes; design specialization resulting in complex design chains between the various manufacturers; and traditional CAD environments.
Today, designers need a balanced methodology that addresses the challenges of a high-density, multigigahertz, low-voltage system interconnect. Since timing, power and signal-integrity design issues are closely intertwined, they must be addressed across the various system interconnect components, from design specification through manufacturing, to achieve design predictability.
Design flows and methods originally developed for design of individual components now seem archaic. The challenge is in building the complete interconnect model with sufficient detail to support the proper level of analysis. A single signal-interconnect net can easily span several ICs, packages and boards, each based on differing technologies. A co-design methodology will address both the traditional physical and logical constraints as well as the intertwined issues of timing, power and signal integrity across the design chain.
A co-design methodology must be able to assimilate physical rules, electrical properties of the manufacturing materials, any empirical data that results from design reuse and the logical connectivity. To develop this new methodology one must break down the design challenge into a discrete set of tasks that result in a flow that can then be implemented in a CAD environment.
It is important to conceptualize the act of design as a convergent process that begins with an abstract model and matures into manufactured components. The first full model of system interconnect should be developed at specification, as part of the effort to validate the feasibility of that specification. If the target is unachievable, then there is no sense in pursuing it. This abstract or virtual system-interconnect model will be based on a combination of rules-of-thumb, approximations and empirical data where available. The accuracy of the model should be sufficient to perform key analysis, but not overly complicated to build or support. This model provides top-down constraints and is developed in such a way that it can be incrementally updated with implementation data as the design progresses.
A parasitic-circuit model must be approximated or extracted (or both) for each system interconnect component and assembled into a single network with driver and receiver models. The impedance of the parasitic circuit describes how voltage and currents are related in the interconnect component. Impedance is frequency-dependent and therefore must be calculated at the expected operating frequency of the signal. Frequency-domain simulation must be performed as needed to develop the parameters required to perform accurate time-domain simulation. To support approximations, engineers can precharacterize interconnect structures for each of the manufacturing technologies with the operating frequency in mind. That extra exercise will provide tables of desired target impedances for each frequency and the general behavior of length, width and spacing of interconnect. Driver and receiver models must be developed to represent signal behavior at the source and loading of the connections. These models can be implemented in Spice with transistor-level models or behaviorally using a format such as the I/O Buffer Information Specification. Ibis was developed to provide a means for creating such models. Engineers can derive an Ibis model from any existing Spice model or they can write a behavioral model to represent the I/O buffer (see www.eigroup.org/ibis/ibis .htm for more information on Ibis).
Once the problem, data and model for the co-design methodology have been defined, the next step is to link the IC, package and board design flows. These three discrete design processes are typically spread across different geographies, organizations and development partners. Therefore, the concept of using one large central database is usually not practical.
Given this environment, the interoperation among these design flows should be defined as a small shared-data structure that describes the design interface in terms of hard data and constraints. For example, the IC-to-package interface for a flip-chip design consists of the following: a shared bump array; an assignment relationship between the I/O buffer and bump, and bump and package ball; a circuit description for the I/O buffer-to-bump redistribution interconnects; a circuit description for the bump-to-ball package substrate interconnects; the I/O buffer Ibis models; and shared constraints such as differential pairs and target impedance.
Next, the designer must define the co-design objective. In this case that definition would include the ability to manage the arbitration of assignment, placement and routing between the I/O buffers and bump array and package ball, so that the system interconnect meets the designer's cost, manufacturing, timing, signal integrity and power-distribution requirements.
Similar data and co-design tasks exist between the package and board design flows. The biggest challenge in this process is to make sure the IC-to-package and package-to-board interfaces are designed in consideration of one another. To solve this problem, the co-design of IC, package and board must be performed by tightly linking their distinct design processes.
Once the co-design process has been defined, it must be implemented into a highly efficient CAD solution. Within this new use model, old methodologies and CAD tool implementations are outdated. For this new environment, new CAD tools must be developed that can support the co-design process. They must support operation across platforms, including hardware and software applications. At the same time, new methods must be developed for managing shared data and common constraints.
Ultimately, by allowing development teams to design an IC, its package and the target system board concurrently, such a methodology will result in reduced design cycle time, lower design cost and a higher-quality product.
Bill McCaffrey is silicon-package board platform architect at Cadence Design Systems Inc. (San Jose, Calif.).
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