The VST family features a homodyne RF receiver, also known as a synchrodyne, zero-IF (ZIF), or direct-down conversion receiver. In a homodyne receiver, the incoming RF signal is fed into a frequency mixer just like in a traditional heterodyne receiver. However unlike a heterodyne receiver, the frequency of the LO in a homodyne receiver is identical to, or very close to, the frequency of the incoming RF signal, resulting in a DC-centered or low IF signal such as 10 or 20 MHz.
The input signal is mixed down to baseband and split into in-phase (I) and quadrature-phase (Q) components, where the carrier is in-phase and offset by 90 degrees respectively. The I and Q path signals are then separately digitized resulting in I and Q data. Finally, the I and Q data streams are combined in software, rendering the original signal. Figure 5 shows a simplified block diagram of a homodyne, or zero-IF architecture.
Figure 5: Homodyne (Zero-IF) Architecture Basic Block Diagram
Homodyne (Zero-IF) Receiver Advantages
The homodyne architecture boasts a number of advantages over the traditional heterodyne architecture including simpler design, lower cost, less power consumption, and high selectivity, which allows separation of adjacent channels whose signals overlap. Other advantages include higher potential bandwidths, simpler designs with single LOs, and a smaller footprint due to a more compact design. These advantages are described in more detail below.
1. Bandwidth. Receivers with single ADCs have a practical upper limit for signal bandwidth of 40 percent of the sample clock frequency. With the same sample clock frequency, homodyne architectures allow double the bandwidth, or 80 percent of the sample clock frequency, because two ADCs are used. In general, ADCs with lower allowable sample clock frequencies have better spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) performance. Homodyne receivers allow wider bandwidths without the trade-off in ADC performance that is a necessary trade-off of single ADC receivers.
2. Single LO. With multichannel measurement systems becoming more important for multiple input, multiple output (MIMO) applications, sharing the LO is a requirement. With only one LO to share in a homodyne architecture as opposed to multiple LOs in a traditional heterodyne architecture, homodyne architectures become a more cost-effective and less complicated system to configure.
3. Compact Design. Homodyne architectures have much simpler RF designs over heterodyne architectures. Fewer LO signals; no bulky, expensive RF and IF filters; and fewer conversion stages for the homodyne architecture make for a more compact design.
Homodyne (Zero-IF) Receiver Challenges
Although the advantages are numerous, the homodyne architecture does come with its own set of challenges, such as the inability to implement envelope detection. The VST overcomes this problem by using quadrature detection and digital signal processing.
DC offsets are another challenge of a zero-IF architecture. Any signal that mixes down to 0 Hz in the ZIF structure causes a spectral component at DC. This distortion falls at the center of the instantaneous bandwidth of the data acquisition. A spectrum composed of pasted together data acquisitions, each offset in frequency by the instantaneous bandwidth, will show this DC offset term replicated in the center of each data acquisition. Nulling of the DC offset is accomplished on the digitized I and Q data streams by applying offsets. A separate nulling procedure must be applied for each LO frequency, which is done automatically by running the VST self-calibration procedure.
Receiver Signal Path
The high-level architecture of the VST receiver design is shown in Figure 6. This diagram highlights the calibration synthesizer, optional attenuators for high power, optional amplifiers for low power signals, out of band select filters, additional gain and attenuation signal conditioning, and demodulation over one of three mixers depending on frequency.
Figure 6: VST Receiver Block Diagram
The select filter bank has eight different paths with lowpass or bandpass filters. These filters remove much of the unwanted noise, focusing only on the signal range of interest. After implementing the selectable filter and applying some additional signal conditioning, the RF signal is then sent to one of three demodulators, depending on the signal’s frequency. Each demodulator operates within a specific frequency band to optimize gain and phase signal integrity.
The receiver path includes several solid state attenuators that provide more than 80 dB of attenuation, variable in 1 dB steps. The RF input is AC-coupled. There are three switchable gain amplifiers and a preamplifier to extend dynamic range and improve the system’s noise figure.
A low phase noise LO is supplied internally to connect multiple downconverters with a single LO source. Using the same LO source is useful for phase-coherent signal acquisition applications, such as multiple input, multiple output (MIMO) systems. Using this configuration ensures every RF channel, sharing the common LO, is tuned to the same RF frequency.
The downconverted baseband signal is directly transmitted to the internal ADC channels of the VST. The ADC channels digitize the baseband analog signal and route the result to the onboard FPGA for further processing, and then transfer to the host. The NI PXIe-5644R/45R and 5646R ADCs digitize the baseband analog signal at 120 MS/s over a 16-bit dynamic range and 250 MS/s over a 14-bit dynamic range respectively.
The VST receiver features a single-stage, direct conversion (I/Q) downconverter. The RF signal is downconverted from the configured LO frequency to DC, where the baseband signal can be digitized for processing. This architecture allows for wide instantaneous bandwidth with high image suppression and minimal LO leakage. Image suppression and LO leakage performance is achieved by wideband quadrature correction. The receiver path is optimized to be used as a vector signal analyzer for wideband demodulation.
Low IF Mode and In-Band Retuning
A low IF receiver is another type of receiver that uses an IQ demodulator, where the block diagram is identical to the zero-IF receiver shown in Figure 5. Unlike in the zero-IF receiver where the LO frequency is positioned to be within the frequency range of the modulated signal, in the low IF receiver the LO frequency is placed outside of the modulated signal range. The result is that the DC component is no longer within the downconverted span. Many of the impairments associated with the DC term such as DC offset, 1/f noise, and in some cases baseband harmonics are no longer an issue.
Any user can combine the capabilities of LO tuning and digital frequency shifting to operate the VST in low IF mode. Acquiring or generating the signal of interest at a digitally shifted frequency from the carrier avoids the implications of LO leakage present in direct conversion topology. The trade-off is the maximum BW of the low IF receiver is half that of the zero-IF receiver given identical ADC sample rates. The NI PXIe-5644R/45R supports up to 80 MHz of complex instantaneous bandwidth while the NI PXIe-5646R provides up to 200 MHz of complex instantaneous bandwidth, both with an additional 4 MHz of complex bandwidth allocated for digital frequency shifting. Additional frequency shift reduces the usable bandwidth to (BW/2) - (x- 2) MHz, where x is the requested digital frequency shift.