This thesis describes development of a PCI Express bus on an FPGA chip, which has a very high data throughput when using DMA transactions.
When developing hardware for accelerating data compression or data processing, one of the bigger problems is how to get the data to the co-processor hardware fast enough, that the development of such hardware is even reasonable. Most buses, used for communication between processor, are useless for this kind of application, because of low data throughhput.
I decided to develop the PCI Express interface of first generation, because this bus offers very high throughput, up to 250 MB/s per lane in each direction. Every following generation doubles the data throughput, while maintaing the same mode of operation, which also ensures compatibility through different generations of interfaces. Another positive feature of the PCI Express bus is also, that it is currently the most common internal interface in modern computers.
My interface is implemented using Xilinx Virtex 5 FPGA device on XUPV5 development board. My implementation used only one lane, because of hardware limitations on the development board. The development board also features a DDR2 SDRAM memory, used for intermediate storage of data to be processed.
In this thesis we first explain the basics of PCI Express bus, starting with the differences between its predecessors, through different layers of hardware and software, and the inner operations of this bus. Then we look at the operation of DDR2 SDRAM memory and finally, we introduce the structure and operation of my implemented PCI Express interface, through all stages of the hardware development process, ending with presentation of development and operations of Linux device driver and test application for this PCI Express interface.