A conventional analog zero-IF (intermediate frequency) in-phase and quadrature (I/Q) demodulator uses analog components to translate an RF signal to baseband analog I and Q signals before converting it to digital data samples. Low-quality analog RF components can cause a number of errors that degrade I/Q demodulator performance, including DC offset, I/Q gain imbalance, and I/Q phase imbalance. High-quality analog components in an I/Q demodulator reduce these errors but increase the cost of the wireless system's RF front-end. High-speed analog-to-digital converters (ADC) are now widely used as an alternative approach, pushing the analog I/Q demodulator into the digital domain in order to reduce errors caused by analog RF components. This blog post shows an example of how a digital I/Q demodulator pairs with a high-speed ADC sampling at an IF.
Digital I/Q demodulator
Figure 1shows the block diagram of a digital I/Q demodulator. The input IF signal, centered at 8 MHz, is sampled directly by a single high-speed ADC device. The IF samples are mixed with 8-MHz digital cosine and sine samples generated by a direct-digital synthesizer (DDS) to translate the signal to baseband. Filtering out the high-frequency component of the digital mixer output is required to obtain the design's baseband signal.
Figure 1: Digital I/Q demodulator
IF sampling with the ADAC250
A test model of the digital I/Q demodulator is shown in Figure 2. The design is clocked at 128 MHz from the ADAC250 module