MIT boffins build 36 core processor with data-traffic smarts
Network-on-chip design uses internet-inspired scheme to solve bussing problems
Researchers at MIT say they have successfully built a 36-core processor that uses an internal networking system to get maximum data throughput from all the processing cores.
MIT's new multicore, multi-bus chip
The design, unveiled at the International Symposium on Computer Architecture, gets around some of the problems with multicore processors, namely bus sharing between cores, and maintaining cache coherence.
Most conventional designs use a single bus to connect cores, meaning that when two cores communicate, they typically use the entire bus and leave other cores waiting. The MIT design borrows from the internet's design and allows all chips to share data with their neighbors using their own router.
"You can reach your neighbors really quickly," said Bhavya Daya, an MIT graduate student in electrical engineering and computer science, and first author on the new paper. "You can also have multiple paths to your destination. So if you're going way across, rather than having one congested path, you could have multiple ones."
The network is also used to distribute data between each core's cache without having to shift it too far, potentially speeding up the system even further.
"Their contribution is an interesting one: They're saying, 'Let's get rid of a lot of the complexity that's in existing networks. That will create more avenues for communication, and our clever communication protocol will sort out all the details'," said Todd Austin, a professor of electrical engineering and computer science at the University of Michigan.
"It's a much simpler approach and a faster approach. It's a really clever idea."
The blueprints for the new chip design aren't being released as yet, since the team first wants to develop an operating system capable of using it to best advantage. The team is now adapting a version of Linux to use the new chip before releasing the designs. ®