Computing Capability, Data Storage Realized Only With STT-MRAM
Toshiba Corp announced a new computing architecture that carries out operations and stores data only with STT-MRAM at International Electron Devices Meeting (IEDM) 2013, which took place from Dec 9 to 11, 2013, in Washington, D.C. (lecture number: 25.4).
The title of the lecture was "Variable Nonvolatile Memory Arrays for Adaptive Computing Systems."
Currently, in many computing architectures, a CPU that carries out operations and memory that stores data are separated. And the memory is stratified, consisting of a register file, primary cache and secondary cache. Recently, however, data transmission between a CPU and memory is becoming a bottleneck to improving system performance and power consumption.
In view of this situation, Toshiba proposed the computing architecture, in which one memory chip not only has computing capability but supports register file, primary cache and secondary cache. As a memory for the architecture, the company plans to use a perpendicular STT-MRAM that it has been developing.
To eliminate the bottleneck in data transmission between a CPU and memory, there is a method that "lifts up" memory from the memory hierarchy to the inside of the CPU and disperses it in the CPU. And Toshiba was considering this method in about 2004. However, the method eventually requires a large amount of memory outside of the CPU, making it difficult to improve performance. As a result, the company gave up on it and started to look for a different method.
The new method only requires memory. Specifically, the results of operations (answers) that correspond to combinations of certain inputs are prepared in advance in the form of a table and stored in the memory. In response to an input, an answer is read out of the memory. This is equivalent to an operation carried out by a CPU.
(Continue to the next page)
With the new method, it becomes possible to have a result equivalent to that attained through complicated calculations just by reading out an answer once. Therefore, it drastically improves processing speed and power consumption. In a simulation, Toshiba found that a division process requires 50 processing cycles with a normal CPU but the same division process requires only 16 cycles with the new method.
For a calculation called "Armstrong," which looks for combinations of a, b and c that satisfy the equation 100 x a + 10 x b + c = a3 + b3 + c3, 50 cycles are normally required. But the new method enables to reduce it to 20 cycles. Also, 408 cycles are normally required to solve a quadratic equation, but it can be reduced to 44 cycles.
Of course, the results of operations have to be calculated in advance with an external computer. This is basically the same as the fact that it is necessary for existing computers to compile programs in advance, Toshiba said. Also, because the table in the memory is rewritten depending on the kind of operation, a variety of tables containing the results of operations need to be stored in an external memory.
In principle, it is possible to carry out operations by using SRAM. But its standby power consumption is high. That is why Toshiba ran the simulation for STT-MRAM, which features high speed and non-volatility.
Toshiba announced an MTJ technology aimed at replacing SRAM at IEDM 2012 (See related article). In addition, it announced a high-speed 1-Mbit array having the "two-transistor/two-MTJ (2T-2MTJ)" structure at the 2013 VLSI Symposia. This time, the company ran the simulation based on the values measured with the 1-Mbit array having the 2T-2MTJ structure.