How to extend design features below the 10-nanometer node--which is off-the-scale beyond 2020 on the International Technology Roadmap for Semiconductors (ITRS)--was demonstrated recently by University of Alberta (Canada) researchers.
Conventional lithographic tools first fabricated a micron-sized data bus, followed by the nanoscale patterning of individual 10-nm-wide wires, which were inserted into the bus using self-assembling block copolymers. Different block copolymers can self-assemble any repeating pattern--from nanowires for interconnections to nanoparticles for ultra-dense flash memories.
"We have been using self-assembling block copolymers for a while--mostly to make nanoparticles for floating gates--but this is the first time we have been able to use them as templates for continuous nanoscale wires," said professor Jillian Buriak of the University of Alberta.
Normal polymers have a single formulation or long string-like structure called a "block." Block copolymers, on the other hand, mate two intentionally incompatible polymer-block formulations into double-length string-like molecules. Technically, the two polymers with opposing molecular structures--like oil and water--are covalently bonded at their ends to form the extra-long molecules that automatically rotate their orientation to form rows. Consequently, the self-aligned side-by-side molecules of alternating polymer blocks form perfect rows that are 10 nm wide.
The researchers had also previously demonstrated other periodic lattice structures--such as creating nanoparticles for floating-gate flash memories--but this most recent work represented the first nanoscale metal lines for a bus on a silicon chip.
"The reason we use block copolymers is because they are compatible with current silicon manufacturing techniques," said Buriak. "We made as few changes as possible from traditional chip processing--you just use a specific copolymer as if it were a polymer, and they automatically self-assemble into the kind of nanoscale structures that you want--like parallel lines for buses, or nanoparticles for floating gates."
Since 2003, IBM Corp. has been developing a pilot process using block copolymers to pattern floating nanoparticles for super-dense flash memories [http://www.eetimes.com/showArticle.jhtml? articleID=18310413]. Because block copolymers can be designed to create almost any conceivable nanoscale pattern, the University of Alberta researchers contend that all sorts of arrays can be patterned this way.
Buses from traditional metals
First, traditional lithography lays down a basic pattern, such as a 30-nm-deep etched trench 1.38 microns wide for a wiring bus. Then the block copolymer self-assembles the individual wires in the bus across the width of the trench. In this case, 10-nm-wide parallel wiring traces are separated into the 30 parallel lines of a bus with its wires spaced 36 nm apart. After the copolymer self-assembles into the nanoscale lines, a plasma process allows metal atoms to replace the 10-nm-wide copolymer, while the other 36-nm-wide copolymer lines get etched away, leaving the 30 parallel metal lines each 10 nm wide. The bus was 50 microns long, for an aspect ratio of 5,000-to-1.
"Now we are planning to demonstrate that we can make buses from copper, aluminum and other traditional metals instead of the gold and platinum we used for our first demonstration," said Buriak.
Buriak said her group's task now is to fit the patterns made by block copolymers into the standard development process for CMOS chips on the ITRS.
"Our biggest obstacle to success is the same obstacle faced by any technology on the roadmap--integration," she said. "Our block copolymers have to be used with photolithography in same way as normal polymers, as well as with new processes using extreme UV, nanoimprint lithography and other new techniques on the roadmap."