When it comes to designing SAR ADC, I am like a tortoise and can never imagine the world of rabbits. Recently I got some time to ponder how the rabbits can run so fast. One of the critical factors is that they have an internal asynchronous clock.
When it comes to digital signals, I always feel dizzy examining their timing sequences. It did take me a while to understand how the internal asynchronous clock is generated. In this post, I tried to write down the core idea behind the pulse generator of asynchronous SAR ADC.
First of all, the pulse generator (Fig.1) needs a dynamic latch comparator! At the reset phase, the differential outputs are both set to low; at the comparison phase, once the regeneration is complete, one of the differential outputs will go to high and another stay at low. This property is utilized by a succeeding NAND which will output a valid signal indicating the completion of comparison.
Since the comparison starts at the negative edge, the sample signal is used to trigger the first comparison of the latch. Once the comparison is finished, the valid signal will generate a positive edge. With an OR function of sample and valid, following certain deliberate delay, the clock of the latch can be generated.
Figure 7‑2 depicts the timing sequences of three critical signals (sample, clk, and valid). Four sources of delay keep the asynchronous machine running:
- td1 is composed of the delay of the OR gate, the charging path of VDC, and the succeeding inverter.
- td2 is composed of the regeneration time of the latch, the delay of the following inverter and the NAND gate.
- td3 is composed of the delay of the OR gate, the discharging path of VDC, and the succeeding inverter.
- td4 is composed of the reset time of the latch, the delay of the following inverter and the NAND gate.
The low level of the generated clk is the sum of td2 and td3, which varies as the input of the comparator changes. The high level of clk is the sum of td1 and td4, which is input-independent. One must pay attention to the DAC settling, which happens when clk goes high. The VDC can then be programmed/configured to ensure accurate DAC settling.
In summary, in order to increase the sample rate, the low level of clk should be as short as possible by speeding up the comparator, while the high level of clk should be long enough for the DAC to be fully settled. Worth to mention here, though the delay of digital control logic is not included in the discussion, it also become rather critical in high-speed design. This post is just a touch of the sphere of high-speed SAR ADC design. Salut to those who race in this challenging field!