Mismatch between two array of identical MOS
Calculates 3 sigma mismatch between two arrays of identical MOS devices (same size, orientation and environment) and expresses mismatch in three different forms: referred to the gates (e.g. in a differential pair in delta Vgs ), referred to the drain (percentage of output current difference), and as DNL in a current DAC when changing DAC code input from p to q assuming p and q devices are identical but distinct. DNL is expressed as a percentage of the current in one single transistor. Note that all the formulas assume that all layout used best practice, as referred to in literature.
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