This is a collection of schematics for the Q1.
- Address Selector
16 of these are needed for the Address Path module. This is a 2-2 input AND-OR gate with open collector output for the address selection and a NOT gate to drive the inverted address lines (used to simplify several modules).
- Clock Generator
This is the circuit that generates the clock signal. This is a astable multivibrator connected to a Schmitt trigger and then gated to allow disabling the clock at the correct clock phase. The multivibrator is configured to allow switching between two preset speeds.
- D Flip-Flop
A positive-edge triggered D Flip-Flop with asynchronous reset.
Two of these are used for clock phases and eight are used for storing the state.
- Data Path
8 of these are needed for the Data Path module.
- Input Buffer
An input buffer with a push-button to toggle the value. 24 of these are used on the Front Panel module.
Unless stated otherwise, all transistors are type PN2222A and all resistors are 1/4 watt.