Stories of data hacking have been dominating the news lately. It seems that hackers are getting smarter and more bold, but what is also making it easier for hackers is that more and more of our everyday devices are connected to the internet making unauthorized access to these devices much easier to achieve and harder to detect. The Internet of Things is giving rise to a whole new set of security concerns.
As consumers and businesses become more vulnerable to attack, they need to feel more confident that the electronic machines they are using are more secure regardless of the ubiquitous nature of an all-connected world.
In order for providers of these devices to achieve this attack-proof status, they need to invest heavily in design and verification solutions that can secure their hardware designs. However, this added investment comes at a cost. That cost is time. We as consumers still want the latest and greatest electronic gadgetry earlier and earlier putting even more pressure on already hyper-stringent time-to-market targets for electronic providers.
Even with these added pressures, current methods for verifying that the hardware can withstand attack are essentially inadequate due to their non-exhaustive nature. Simulation and emulation methods can leave many corner cases left unchecked and thus exposing the hardware to attackers.
This is where formal analysis can come into play. Formal verification is exhaustive and therefore can find every possible scenario that could leave the hardware device open to hackers.
At DVCon 2014 Jasper technical experts Victor Markus Purri and Lawrence Loh are giving a tutorial on “Formally Verifying Security Aspects of SoC Designs” showing how formal analysis can be applied to this area.
You can register for this tutorial at http://dvcon.org/content/rates.
You can also download our white paper on Security Path Verification to learn more – http://jasper-da.com/resource-library/technical-white-papers.