Converts polar coordinates to rectangular coordinates. You must specify the phase of the polar coordinates in pi radians, which use fewer FPGA resources than radians. To convert a radian value to pi radians, multiply the value by pi.
This input supports only the fixed-point data type.
The CORDIC algorithm represents phase internally as a signed fixed-point number with a 1-bit integer word length. The word length of phase must be less than or equal to 64 bits. If you wire a value to phase that has a fractional word length greater than 63 bits, this node rounds off the lower bits to achieve a fractional word length of 63 bits. For example, if you wire a fixed-point data type with a configuration of I60<-5, 55> to phase, this node coerces the configuration to be U58<-5, 53>.
If you wire a fixed-point data type to phase with a fractional word length greater than 63 bits and an integer word length less than -62 bits, this node coerces the configuration to be I1<-62, 63> if the data type is signed. If the data type is unsigned, the coerced configuration is U1<-62, 63>.
A Boolean that specifies whether downstream nodes are ready for this node to return a new value. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node.
|True||The downstream node is ready for the next data point.|
|False||The downstream node is not ready for the next data point.|
X value of the rectangular coordinates.
Y value of the rectangular coordinates.
A Boolean that indicates whether this node has computed a result that downstream nodes can use. Wire this output to the input valid input of a downstream node to transfer data from the node to the downstream node.
|True||The node has computed a result that downstream nodes can use.|
|False||This node has not computed a result that downstream nodes can use. Any data output returns an undefined value. The undefined value returned by a data output may differ between simulation and hardware.|
A Boolean that indicates whether this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node.
|True||The node is ready to accept new input data.|
|False||The node is not ready to accept new input data.|
Where This Node Can Run:
Desktop OS: none
FPGA: All devices