Boundary Scan was developed as a solution to difficultly in placing test points on modern circuit boards brought on by the ever increasing board complexity and decreasing size of modern electronic circuits.
Systems Get Smaller
As technology advanced, chips got smaller, more tightly packed, and new package technologies, such as Ball Grid Arrays (BGAs), were created to allow more and more devices to be placed on smaller and smaller footprints.
These advances made it increasingly difficult to place test points on a board, rendering traditional methods of testing like In-circuit Test or, ICT less and less effective.
To help deal with these problems, a group of US and European companies was formed to look at new ways to test these new boards and systems.
Joint Test Access Group (JTAG) is Born
The consortium of companies came to be know as the Joint Test Action Group or JTAG for short. This group created a specification for on-chip test that would later be known as IEEE 1149.1. The specification was intended to provide a standard way to do “pins out” testing where each IC pin could become a virtual test point when the chip was placed in a special test mode. Using a published standard helped to enable multiple tools vendors to create test products that could be used in all phases of board design and test.
Evolution of the JTAG Specification
Later additions to the family of specifications included: 1149.4 for Analog testing (not popular) and IEEE 1149.6 for AC coupled signals (gaining popularity).
Many modern IC Chips support Boundary Scan testing and as such adhere to the IEEE 1149.1 Specification. To meet the specification, vendors must include a Boundary Scan Definition Language File (BSDL) that describes the chip’s support for the standard.