can you show me a simple makefile that compiles two or three c files into one executable where at least one static library is used
can you show me a simple makefile that compiles two or three c files into one executable where at least one static library is used

Here is a simple example of a Makefile that compiles two C files (`main.c` and `lib.c`) into an executable (`my_program`) and links a static library (`my_lib.a`).

First, create the C files and the library:

```
// main.c
#include "lib.h"

int main() {
    printf("Hello, World!\n");
    my_function();
    return 0;
}

// lib.c
#include "lib.h"

void my_function() {
    printf("Library function called.\n");
}

// lib.h
#ifndef LIB_H
#define LIB_H

void my_function();

#endif
```

Create the static library:

```
$ gcc -c lib.c -o lib.o
$ ar rcs my_lib.a lib.o
```

Now, create the Makefile:

```
CC = gcc
CFLAGS = -Wall -Werror
LDFLAGS = -static

all: my_program

my_program: main.o lib.o my_lib.a
    $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS)

main
  Sure! Here is a simple `Makefile` that compiles two C files, `file1.c` and `file2.c`, and links them into an executable `executable.out`, using a static library `lib.a`:
```
CC=gcc

obj-y += file1.o file2.o

all: executable.out

executable.out: file1.o file2.o lib.a
	$(CC) -o $@ file1.o file2.o lib.a

file1.o: file1.c
	$(CC) -c file1.c -o $@

file2.o: file2.c
	$(CC) -c file2.c -o $@

lib.a: lib.c
	$(CC) -c lib.c -o $@
	ar rcs lib.a

clean:
	-rm -f obj/*.o executable.out lib.a
```
Let me explain what this `Makefile` does:

* `CC=gcc`: sets the C compiler to `gcc`
* `obj-y += file1.o file2.o`: lists the object files that are generated by the build process
* `all: executable.out`: the target of the build process is the executable `executable.out