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## CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS

#### Alaa Mohamed Abd El-Latif [1]

##### 74 171

− The notions of fuzzy pre open soft sets and fuzzy pre closed soft sets were introducedby Abd El-latif et al. [2]. In this paper, we continue the study on fuzzy soft topological spaces andinvestigate the properties of fuzzy pre open soft sets, fuzzy pre closed soft sets and study variousproperties and notions related to these structures. In particular, we study the relationship betweenfuzzy pre soft interior fuzzy pre soft closure. Moreover, we study the properties of fuzzy soft pre regularspaces and fuzzy soft pre normal spaces, which are basic for further research on fuzzy soft topologyand will fortify the footing of the theory of fuzzy soft topological space
− Fuzzy soft topological space, Fuzzy pre open soft, Fuzzy pre closed soft, Fuzzy pre continuous soft functions, Fuzzy soft pre separation axioms, Fuzzy soft pre regular, Fuzzy soft pre normal
Other ID JA68MZ22CG Research Article Author: Alaa Mohamed Abd El-Latif Publication Date: August 1, 2015
 Bibtex @ { jnt381189, journal = {Journal of New Theory}, issn = {2149-1402}, eissn = {2149-1402}, address = {Gaziosmanpasa University}, year = {2015}, volume = {}, pages = {47 - 63}, doi = {}, title = {CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS}, key = {cite}, author = {El-Latif, Alaa Mohamed Abd} } APA El-Latif, A . (2015). CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS. Journal of New Theory, (7), 47-63. Retrieved from http://dergipark.org.tr/jnt/issue/34499/381189 MLA El-Latif, A . "CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS". Journal of New Theory (2015): 47-63 Chicago El-Latif, A . "CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS". Journal of New Theory (2015): 47-63 RIS TY - JOUR T1 - CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS AU - Alaa Mohamed Abd El-Latif Y1 - 2015 PY - 2015 N1 - DO - T2 - Journal of New Theory JF - Journal JO - JOR SP - 47 EP - 63 VL - IS - 7 SN - 2149-1402-2149-1402 M3 - UR - Y2 - 2019 ER - EndNote %0 Journal of New Theory CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS %A Alaa Mohamed Abd El-Latif %T CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS %D 2015 %J Journal of New Theory %P 2149-1402-2149-1402 %V %N 7 %R %U ISNAD El-Latif, Alaa Mohamed Abd . "CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS". Journal of New Theory / 7 (August 2015): 47-63. AMA El-Latif A . CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS. JNT. 2015; (7): 47-63. Vancouver El-Latif A . CHARACTERIZATIONS OF FUZZY SOFT PRE SEPARATION AXIOMS. Journal of New Theory. 2015; (7): 63-47.


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## Basic College Mathematics (9th Edition)

We can take the cross products of the given proportion to determine whether or not the proportion is true. If the cross products are equal, then we know that the proportion is true. $\frac{5.6}{.6}=\frac{18}{1.94}$ $5.6\times1.94=.6\times18$ $10.864\ne10.8$ Although the cross products have nearly the same value, they are not equal. Therefore, the proportion is False.

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1. (Department of Electronic Engineering, Kumoh National Institute of Technology, Gumi, Gyungbuk, Korea)

Successive approximation register, noise shaping, analog-to-digital converter, differential capacitor, voltage gain calibration

I. INTRODUCTION

Smart devices require small area and low-power analog-to-digital converters (ADCs) to acquire information such as temperature, pressure, and Earth’s magnetic field. In addition, the resolution of ADCs required in sensor interfaces continues to increase. Delta-sigma ADCs have been widely used for high-resolution sensor interfaces. However, since they generally use analog integrators with operational amplifiers, the power consumption and area are relatively large [1-3]. Furthermore, the high oversampling ratio used in the delta-sigma modulator increases the frequency of the sampling clock and the complexity of the decimation filter.

On the other hand, a successive approximation register (SAR) ADC has advantages of low power consumption and small area. However, it has difficulty in increasing the resolution due to the area and mismatch of the digital-to-analog converter (DAC) [4-6]. As an alternative to the limitation of improving the resolution of SAR ADCs, SAR ADCs using noise shaping (NS) are being studied [7-9]. Passive integrators can be used for noise shaping without increasing power consumption [7,8]. In this case, the capacitor for the passive integrator increases the area of the NS SAR ADC. In addition, the comparator for the operation of the NS SAR ADC is designed to receive and compare multiple input signals rather than a single input. For the stability and performance of the NS SAR ADC, it is required that the comparator has an optimal voltage gain for the output of the passive integrator.

In this paper, a NS SAR ADC that increases resolution by applying second-order noise shaping in a 10-bit SAR ADC is proposed. In particular, the use of a capacitor-resistor hybrid DAC (C-R DAC) for operation of SAR ADC and two differential capacitors for second-order noise shaping is proposed to minimize the area of the NS SAR ADC [10-12]. Furthermore, voltage gain calibration for a three-input comparator is proposed for stable noise shaping and evaluated from the measurement results of the NS SAR ADC. Section II presents the behavioral model and simulation results for the design of the second-order NS SAR ADC. Section III explains the operation including the block and timing diagrams of the proposed NS SAR ADC. It describes a design technique to minimize the area of the NS SAR ADC and a three-input comparator with voltage gain calibration for second noise shaping. Section IV presents the implementation and measurement results of the NS SAR ADC. Finally, Section V provides the conclusion of this paper.

II. BEHAVIORAL MODEL OF SECOND-ORDER NOISE SHAPING SAR ADC

Fig. 1 shows the conceptual block diagram of the proposed second-order NS SAR ADC. The proposed second-order NS SAR ADC basically has an architecture in which a second-order integrator is added to a 10-bit SAR ADC. The SAR ADC is simply represent by using a 1-bit quantizer, a SAR logic, and a DAC, and outputs a 10-bit binary digital code as the result of the NS SAR ADC. H(z) is a second-order integrator for noise shaping. The second-order NS SAR ADC is different from a general SAR ADC in the two way: 1) H(z) outputs V$_{\mathrm{INT1}}$(z) and V$_{\mathrm{INT2}}$ by integrating V$_{\mathrm{RES}}$(z), which is the residue voltage after quantization of the SAR ADC. 2) V$_{\mathrm{RES}}$(z) is summed with V$_{\mathrm{INT1}}$(z) and V$_{\mathrm{INT2}}$(z), and the summed analog signal, V$_{\mathrm{QIN}}$(z), is converted to a 10-bit digital code by the operation of the SAR ADC.

Fig. 1. Conceptual block diagram of NS SAR ADC: (a) NS SAR ADC; (b) second-order integrator.

The behavioral model of the second-order integrator, H(z) is shown in Fig. 1(b). Part A and Part B are blocks for the first and second integration, respectively. In this work, the second-order integrator is implemented by using passive filters consisting only of capacitors and switches without amplifiers. a1 is the coefficients for voltage reduction due to charge sharing between the C-R DAC of the SAR ADC and the sampling capacitor of the integrator. In addition, b1 and b2, and c1 and c2 are coefficients for voltage reduction due to charge sharing between the sampling capacitor of the integrator and the capacitors of the first and second integrators, respectively. The outputs of the two integrators, V$_{\mathrm{INT1}}$ and V$_{\mathrm{INT2}}$, are defined as Eqs. (1) and (2), respectively, when a1, b1, b2, c1, and c2 are 3/4, 1/4, 3/4, 1/4, and 3/4, respectively.

(1)
V INT 1 Z = 0 . 25 0 . 75 1 0 . 75 Z 1 V RES ( Z )
(2)
V INT 2 Z = 0 . 25 2 0 . 75 1 0 . 75 Z 1 2 V RES ( Z )

The output of the proposed NS SAR ADC, D$_{\mathrm{OUT}}$(z), is derived as Eq. (3) by the behavioral block diagram shown in Fig. 1(a), where the voltage gains of the comparator for V$_{\mathrm{INT1}}$ and V$_{\mathrm{INT2}}$, k$_{1}$ and k$_{2}$, are set to 4 and 16 for the stable NTF, respectively [13]. Eq. (3) is simply expressed as Eq. (4) by using Eqs. (1) and (2) for the V$_{\mathrm{INT1}}$ and V$_{\mathrm{INT2}}$. Therefore, the analog input signal V$_{\mathrm{IN}}$(z) is directly transferred to the output of the NS SAR ADC, and the quantization noise E(z) is shaped by the noise transfer function (NTF) shown in Eq. (5).

(3)
D OUT Z = V IN Z + 1 1 + 4 V INT 1 Z + 16 V INT 2 Z Z 1 E ( Z )
(4)
D OUT Z = V IN Z + 1 0 . 75 Z 1 2 E ( Z )
(5)
NTF = 1 0 . 75 Z 1 2

Fig. 2 shows the behavioral simulation results of the NTF. The NTF of the designed NS SAR ADC has the characteristics of a high-pass filter in which the voltage gain decreases in the low-frequency region and increases as the frequency increases. Through such shaping of quantization noise, it is possible to increase the signal-to-noise ratio (SNR) of data conversion for an analog input signal with low frequency.

Fig. 2. Behavioral simulation result of NTF.

Fig. 3(a) shows the behavioral model of the proposed second-order NS SAR ADC based on a 10-bit SAR ADC using the MATLAB Simulink. It consists of a 1-bit quantizer, a SAR logic with DAC, and a second-order integrator are implemented by components supporting the MATLAB Simulink. This behavioral model does not include non-ideal components of the NS SAR ADC. The analog input of the second-order NS SAR ADC is sampled through the process A. The process B shows that the reference voltage for the operation of the 10-bit SAR ADC, which is generated by the SAR logic and the DAC with a 9-bit resolution, is supplied to the 1-bit quantizer. In the process C, the residue voltage, V$_{\mathrm{RES}}$, is generated after the conversion of the 10-bit SAR ADC, and is sampled for the integration operation. It is determined by the difference between the sampled input voltage and the output voltage of the 10-bit DAC including the information of the least significant bit of the 10-bit SAR ADC for the noise shaping operation, although the 10-bit SAR ADC requires the reference voltages generated by the 9-bit DAC, as shown in Fig. 3(b). The second-order integrator supplies the integrated residue voltage to the 1-bit quantizer in the process D. The 1-bit quantizer compares the sum of the sampled input and the two integrated residue voltages against a reference that changes sequentially 9 times for operation of the 10-bit SAR ADC. The 1-bit quantizer operates in synchronization with the signal of COMP_CLK.

Fig. 3. (a) Behavioral model of proposed NS SAR ADC; (b) residue voltage for noise shaping.

Fig. 4 shows the behavioral model of the SAR logic with DAC. The SAR logic with DAC is implemented by using a Chart in the Stateflow library of the MATLAB Simulink which can implement a control logic with finite state machine. Bit is a variable representing the number of SAR conversions of 10 times, and DAC_OUT is the output of the 9-bit DAC. The value of Bit is from 1 to 10 for 10-bit SAR operation, and its initial value is 1. Since the analog input range of the proposed second-order NS SAR ADC is 0 V to 1.8 V, the initial value of DAC_OUT is set to 0.9 V, which is the center voltage. The SAR logic with DAC is synchronized with the signal of COMP_CLK and operates according to the result of the 1-bit quantizer, COMP_OUT. If the value of Bit is less than 10, the signal STROBE indicating the completion of the SAR operation is maintained low, and whenever the signal COMP_CLK goes high, the value of Bit is increased by 1. In this process, the 9-bit DAC outputs the reference voltage as the value of DAC_OUT by the successive approximation algorithm. When the value of Bit is 10, the signal STROBE goes high, and DAC_OUT is sampled as the residue value for integration of noise shaping by the signal STROBE. After that, Bit and DAC_OUT are initialized.

Fig. 4. Behavioral model of SAR logic with DAC.

Fig. 5 shows the fast Fourier transform (FFT) results of the behavior simulations of the 10-bit SAR ADC and the proposed second-order NS SAR ADC. The 10-bit SAR ADC has effective number of bits (ENOBs) of 9.97 bits when the frequency of the analog input signal is 16.259 kHz and the sample rate is 1 MHz, as shown in Fig. 5(a). Fig. 5(b) is the FFT simulation result of the proposed second-order NS SAR ADC using the 10-bit SAR ADC. When the analog input frequency and the sample rate are the same as in the previous case and the over-sampling ratio (OSR) is 8, the ENOB of the proposed NS SAR ADC is determined to be 14.26 bits. Through these behavioral simulations, it is confirmed that ENOB of about 4.3 bits is improved through proposed noise shaping using the second integrator.

III. DESIGN OF SECOND-ORDER NOISE SHAPING SAR ADC

1. Architecture and Operation of NS SAR ADC

Fig. 6 shows the block and timing diagrams of the proposed second-order NS SAR ADC. The second-order NS SAR ADC consists of a 10-bit digital-to-analog-converter (DAC), integration capacitors for noise shaping, a three-input comparator, and a SAR logic including gain calibration, as shown in Fig. 6(a). Its OSR and input bandwidth are 8 and 62.5 kHz. The three-input comparator generates the signal COMP_OUT by differentially comparing the sum of the three results, the result of the 10-bit DAC and the outputs of the first and second integrators. The 10-bit DAC has a C-R DAC architecture, which consists of an 8-bit capacitor DAC and a 2-bit resistor DAC. The C-R DAC can reduce the chip area compared with a DAC using only capacitors. In addition, the use of the C-R DAC can decrease the capacitor values used in the passive integrator for noise shaping because the capacitor value used in the passive integrator is determined proportional to the total capacitor value of the C-R DAC generating the residue voltage. The noise shaping is performed by using passive integrators, which consists of two C$_{\mathrm{RES}}$s, one C$_{\mathrm{INT1}}$, and one C$_{\mathrm{INT2}}$. C$_{\mathrm{INT1}}$ and C$_{\mathrm{INT2}}$ are used as differential capacitors to reduce the increase in chip area due to noise shaping using a passive integrator. The two C$_{\mathrm{RES}}$s are used to perform the sampling operation for the residue voltage of the 10-bit DAC. The first and second integrations are performed by C$_{\mathrm{INT1}}$ and C$_{\mathrm{INT2}}$, respectively, sequentially sharing charges with C$_{\mathrm{RES}}$.

Fig. 6. Proposed NS SAR ADC: (a) block diagram; (b) timing diagram.

The proposed second-order NS SAR ADC operates in synchronization with the external clock EXCLK with a frequency of 17 MHz. It samples the input analog signal during the high region of the first cycle of EXCLK after the signal RSTB goes high, as shown in Fig. 6(b). After that, the SAR data conversion proceeds in synchronization with the rising edge of COMP_CLK, which is the comparator operation clock. The output of the second-order NS SAR ADC, D[9:0], is sequentially output in synchronization with the falling edge of COMP_CLK. The least significant bit, D[0], is decided by voting from D$_{0}$[2], D$_{0}$[1], and D$_{0}$[0] as a results of three comparisons for the same output of the 10-bit DAC to remove the dynamic noise of the comparator. For noise shaping, the residue voltage generated in the 10-bit DAC by the 10-bit SAR conversion is sampled in C$_{\mathrm{RES}}$ by the signal NS_SAMPLE. The first integrator generates an output by sharing charges between C$_{\mathrm{RES}}$ and C$_{\mathrm{INT1}}$ when the signal NS1 is high. After the first integration, the output of the second integrator is generated as C$_{\mathrm{RES}}$ again shares charges with C$_{\mathrm{INT2}}$, as shown in Fig. 6(a).

Table 1shows the total capacitors used for the implementation of a 10-bit SAR ADC and noise shaping, and explains the size of the capacitor reduced by the C-R DAC and differential capacitor used in this work. C is the value of the unit capacitor used in the NS SAR ADC. For operation of 10-bit SAR analog-to-digital conversion ADC and generation of residue voltage, a differential capacitor DAC using a V$_{\mathrm{CM}}$-based switching scheme is implemented by using 2048${\cdot}$C. In addition, C$_{\mathrm{RES}}$, C$_{\mathrm{INT1}}$, and C$_{\mathrm{INT2}}$ are determined to be 1/3${\cdot}$C$_{\mathrm{DAC}}$, 1${\cdot}$C$_{\mathrm{DAC}}$, and 1${\cdot}$C$_{\mathrm{DAC}}$, respectively, to implement the coefficients $\textit{a1, b1, b2}$, $\textit{c1}$, and $\textit{c2}$ of the passive integrators shown in Fig. 1(b) as 3/4, 1/4, 3/4, 1/4, and 3/4. Thus, the design method reported in the prior literature [13] requires a total capacitor of 6826.6${\cdot}$C to implement the second-order NS SAR ADC while the SAR ADC has a resolution of 10 bits. A 10-bit C-R DAC with a 2-bit resistor DAC can reduce the capacitor size to 1/4 that of a 10-bit CDAC. Furthermore, the use of differential capacitors C$_{\mathrm{INT1}}$ and C$_{\mathrm{INT2}}$ for integration halves the number and value of capacitors, so that C$_{\mathrm{INT1}}$ and C$_{\mathrm{INT2}}$ can be determined to be 1/4 of the size of the conventional integrator capacitors. The proposed second-order NS SAR ADC uses 938.6${\cdot}$C by using the C-R DAC and the two differential capacitors. Therefore, it has a capacitor area reduced by 86.25% compared to the conventional NS SAR ADC.

2. Second-order Integrator

Fig. 7 shows the circuit and operation of the second-order integrator used in the proposed second-order NS SAR ADC. First, after the 10-bit SAR conversion is completed, the generated residual voltage is stored in the C-R DAC, as shown in Fig. 7(a), where C$_{\mathrm{DACP/M}}$ is a total capacitor in the differential C-R DAC. In this mode, both C$_{\mathrm{RES}}$s are discharged. In the second process shown in Fig. 7(b), the residual voltage of C$_{\mathrm{DACP/M}}$, V$_{\mathrm{RES}}$(k), is sampled as a new voltage through charge sharing with the two C$_{\mathrm{RES}}$s when the signal NS_SAMPLE is activated. In this process, the value of V$_{\mathrm{NS \_ S}}$(k) is determined by Eq. (6). Fig. 7(c) shows the process of the first integration. When the signal NS1 is activated, the charge for V$_{\mathrm{NS \_ S}}$(k) sampled in C$_{\mathrm{RES}}$ is shared with C$_{\mathrm{INT1}}$. V$_{\mathrm{INT1}}$(k) for the first noise shaping is expressed by Eq. (7). The second integration is shown in Fig. 7(d). If the signal NS2 is activated after the first integration, the charge of the residual voltage stored in C$_{\mathrm{RES}}$ is shared with C$_{\mathrm{INT2}}$. Thus, V$_{\mathrm{INT2}}$(k) is determined by Eq. (8) for the second noise shaping. The integrated voltages V$_{\mathrm{INT1}}$(k) and V$_{\mathrm{INT2}}$(k) are supplied to inputs of the three-input comparator.

(6)
V NS _ S k = 0 . 75 V RES k
(7)
V INT 1 k = 0 . 25 V NS _ S k + 0 . 75 V INT 1 k 1
(8)
V INT 2 k = 0 . 25 V INT 1 k + 0 . 75 V INT 2 k 1

3. Three-input Comparator with Voltage Gain Calibration

In the behavioral simulation of Section II, the voltage gains of the comparator for V$_{\mathrm{INT1}}$ and V$_{\mathrm{INT2}}$, k$_{1}$ and k$_{2}$, were set to 4 and 16, respectively. Variations of k$_{1}$ and k$_{2}$ values cause degradation of the performance of the NS SAR ADC. Fig. 8 shows the behavioral simulation results for the performance of the NS SAR ADC according to the voltage gain of the comparator with three inputs. When k$_{2}$ is 16, the NS SAR ADC has a stable ENOB when k$_{1}$ is set to a value greater than 3 and less than 5. When k$_{1}$ is set to 4, k$_{2}$ is required to have values between 10 and 22. Thus, in this work, the voltage gain for the three-input comparator is calibrated for optimum performance of the NS SAR ADC.

Fig. 8. Behavioral simulation results of NS SAR ADC according to k$_{1}$ and k$_{2}$: (a) when k$_{2}$ = 16; (b) when k$_{1}$ = 4.

Through the behavioral simulation for the maximum performance of the proposed NS SAR ADC, the voltage gain of the three-input comparator for the three input signals (the result of the 10-bit DAC, the output of the first integrator and the output of the second integrator) is determined to be 1:4:16. Fig. 9 describes the conceptual operation of the proposed voltage gain calibration for the three-input comparator. The voltage gain for the output of the first integrator in the three-input comparator should be four times that for the output signal of the 10-bit DAC. As the first step, the 10-bit DAC generates V$_{\mathrm{RES}}$ through the fixed digital codes CP[9:0] and CM[9:0]. After that, V$_{\mathrm{RES}}$ is converted to a voltage of V$_{\mathrm{RES}}$/4 through the sampling process to C$_{\mathrm{RES}}$ and charge sharing between C$_{\mathrm{RES}}$ and C$_{\mathrm{INT1}}$. And the converted differential V$_{\mathrm{RES}}$ /4 is supplied to INTP1 and INTM1 of the three-input comparator, as shown in Fig. 9(a). In the second step, the 10-bit DAC is supplied with a digital code opposite to that of the first step as shown in Fig. 9(b). Then, it generates a V$_{\mathrm{RES}}$ for INP and INM with opposite polarity to the value of V$_{\mathrm{RES}}$/4 generated for INTP1 and INTM1. In this condition, the voltage gain of the three-input comparator is adjusted so that the values of INP-INM'' and INP1-INM1'' are equal, and as a result, the voltage gain of the input terminal for the output of the first integrator is calibrated to 4. In this case, both the nodes INP2 and INM2 remain V$_{\mathrm{CM}}$. The voltage gain calibration of the three-input comparator for the output of the second integrator is almost the same as the method shown in Fig. 9, but instead of V$_{\mathrm{RES}}$/4, V$_{\mathrm{RES}}$/16 is supplied to INP2 and INM2. For this, charge sharing is additionally performed using both C$_{\mathrm{INT1}}$ and C$_{\mathrm{INT2}}$ in the process shown in Fig. 9(a).

Fig. 9. Proposed voltage gain calibration of 3-input comparator for output of first integrator: (a) generation of V$_{\mathrm{RES}}$/4; (b) voltage gain control.

Fig. 10 shows the circuit diagram of three-input comparator with voltage gain calibration. When the gains of the input stage are expressed as G1, G2, G3, and G4, the output voltage of the three-input comparator is determined as G4 ${\times}$ (INP ${-}$ INM) + G3 ${\times}$ (G2 ${\times}$ (INTP2 ${-}$ INTM2) + G1 ${\times}$ (INTP1 ${-}$ INTM1)). When the ratios of G4 to G3 and G1 to G2 are 1:2 and 2:8, respectively, the ratio of k$_{1}$ and k$_{2}$ is determined to be 4:16. The proposed voltage gain calibration for the three-input comparator is performed by controlling the ratio of G1 and G2. G1 and G2 are each controlled by changing the width of the input transistors through the control of a 3-bit digital code. Fig. 11 shows the simulated values of k$_{1}$ and k$_{2}$ of the designed three-input comparator including a constant-gm bias circuit according to process, voltage, and temperature (PVT) variations. According to the results of Fig. 11, the calibration ranges of k$_{1}$ and k$_{2}$ were designed to be 1.68 to 6.15 and 7.30 to 22.87, respectively, according to the post-layout simulation results using HSPICE.

IV. CHIP IMPLEMENTATION AND MEASUREMENT RESULTS

The proposed second-order NS SAR ADC was implemented by using a 180-nm 1-poly 5-metal CMOS process with a supply voltage of 1.8 V. Its active area is 470 ${\mu}$m ${\times}$ 350 ${\mu}$m, as shown in Fig. 12. The CMOS process used in this work supports the minimum value of the capacitor used as the unit capacitor C as 18 fF. Thus, the reduction of the active area of the proposed NS SAR ADC was limited due to the area for the implementation of the capacitors although the use of the C-R DAC and differential integral capacitors. The power consumption of the second-order NS SAR ADC with an input voltage range of full rail-to-rail is 248 ${\mu}$W when it operates at a sampling rate of 1 MHz and has an OSR of 8.

Fig. 13 show the measured static performances of the 10-bit SAR ADC when the implemented second-order NS SAR operates without noise shaping. The differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.19/${-}$0.20 LSBs and +0.26/${-}$0.24 LSBs, respectively, and both values are within +/${-}$0.5 LSBs. The spikes in the measured DNL and INL are considered to be caused by mismatch between capacitors in the C-R DAC. Fig. 14 shows the measured dynamic performances of the 10-bit SAR ADC through the FFT of the results of the second-order NS SAR. The measured signal-to-noise and distortion ratio (SNDR) and ENOB are 58.82 dB and 9.48 bits, respectively, when the 10-bit SAR ADC operates at a sampling rate of 1 MHz for a differential analog input signal with low frequency of 16.259 kHz.

Fig. 14. Measured dynamic performances of 10-bit SAR ADC.

Fig. 15 shows the measured dynamic performances of the implemented second-order NS SAR, including the effect of the proposed voltage gain calibration for the comparator with three inputs. The proposed second-order noise shaping reduced the noise floor by about 20 dB in the low-frequency region compared to the noise floor of the 10-bit SAR ADC shown in Fig. 14. In addition, it moved the quantization noise from the low-frequency region to the high-frequency region. When the implemented second-order NS SAR ADC with an OSR of 8 operates in the initial state without the proposed voltage gain calibration for the three-input comparator, the measured SNDR and ENOB are 78.82 dB and 12.80 bits, respectively, as shown in Fig. 15(a). Fig. 15(b) shows the improved dynamic performance by applying the proposed voltage gain calibration for the three-input comparator. The SNDR and ENOB are measured to be 80.18 dB and 13.03 bits.

Fig. 15. Measured dynamic performances of second-order NS SAR ADC: (a) w/o calibration; (b) w/ calibration.

Fig. 16 shows the measured SNDR of the proposed second-order NS SAR as the voltage gains of the three-input comparator, k$_{1}$ and k$_{2}$, are varied within the designed range. The implemented second-order NS ADC has optimal SNDR characteristics when the proposed voltage gain calibration is applied rather than when the voltage gains of the comparator are controlled by external control (Case1, 2, 4, and 5). Fig. 17 shows the measured SNDR of the proposed second-order NS SAR ADC according to the amplitude of the analog input signal with a frequency of 16.259 kHz.

Fig. 17. Measured SNDR of second-order NS SAR ADC according to amplitude of input signal.

Table 2 shows the performance comparison of NS SAR ADCs. The proposed second-order NS ADC has an ENOB of 13 bits or more while it has an OSR of 8.

V. CONCLUSIONS

The proposed second-order NS SAR ADC with the passive integrators was designed by using a 180-nm CMOS process with a supply voltage of 1.8 V. The C-R DAC and two differential integrals were used to reduce the active area. Furthermore, the proposed voltage gain calibration for the three-input comparator maximized the dynamic performance of the second NS SAR ADC. The second noise shaping applied to the 10-bit SAR ADC improved a SNDR of 21.36 dB, equivalent to an ENOB of 3.55. Thus, the proposed second-order NS SAR ADC had a SNDR of 80.18 dB and an ENOB of 13.03 bits for an analog input signal with a voltage range of full rail-to-rail and with a frequency of 16.259 kHz while it has an OSR of 8 and a sampling rate of 1 MHz. Its area and power consumption were 0.165 mm$^{2}$ and 248 ${\mu}$W, respectively.

ACKNOWLEDGMENTS

This work was supported by the Basic Science Research Program (2020R1I1A3071634) and Priority Research Centers Program (2018R1A6A1A03024003) through the NRF funded by the Ministry of Education, and the Grand Information Technology Research Center Program (IITP-2022-2020-0-01612) through the IITP funded by the MSIT, Korea. The EDA tool was supported by the IC Design Education Center, Korea.

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Jung H., Dec. 2020, Study on Second-order Noise Shaping SAR ADC, Master Degee, Kumoh National Institute od Technology
12
Park J., Nagaraj K., Ash M., Kumar A., Apr. 2017, A 12-/14-bit, 4/2MSPS, 0.085 mm2 SAR ADC in 65nm using novel residue boosting, IEEE Custom Integrated Circuits Conference, pp. 2152-3630
13
Guo W., Zhuang H., Sun N., Jun. 2017, A 13b-ENOB 173dB-FoM 2 nd-order NS SAR ADC with passive integrators, IEEE Symposium on VLSI Circuits, pp. c236-C237
14
Hsu C.-K., Tang X., Liu J., Xu R., Zhao W., Mukherjee A., Andeen T. R., Sun N., Mar. 2021, A 77.1-dB-SNDR 6.25-MHz-BW pipeline SAR ADC with enhanced interstage gain error shaping and quantization noise shaping, IEEE Journal of Solid-State Circuits, Vol. 56, No. 3, pp. 739-740
15
Zhang Q., Li J., Zhang Z., Wu K., Ning N., Yu Q., Ari. 2021, A 13b-ENOB third-order noise-shaping SAR ADC using a hybrid error-control structure, IEEE Custom Integrated Circuits Conference, pp. 1-2
Hoyong Jung

Hoyong Jung was born in Busan, South Korea, in 1994. He received the B.S. and M.S. degrees from the Department of Electronic Engi-neering, Kumoh National Institute of Technology, Gumi, South Korea, in 2019 and 2021, respectively, where he is currently pursuing the Ph.D. degree. His current research interests include the design of data converters.

Neung-in Jeon

Neung-in Jeon was born in Ulsan, South Korea, in 1996. He received the B.S. degrees in the department of electronic engineering from Silla University, Busan, Korea, in 2021. He is currently pursuing the M.S. degrees in the Department of Electronic Engineering, Kumoh National Institute of Technology, Gumi, South Korea. His current research interests include the design of data converters.

Jimin Cheon

Jimin Cheon received the B.S., M.S., and Ph.D. degrees in electrical and electronic engineering from Yonsei University, Seoul, South Korea, in 2003, 2005, and 2010, respectively. From 2010 to 2012, he was a Senior Engineer in the Image Development Team of System LSI Division, Samsung Electronics, Yongin, South Korea, working on the design of APS-C CMOS image sensors for mirrorless and DSLR cameras. From 2012 to 2013, he was a Manager in the Semiconductor Tech. Laboratory of Fusion Technology Research and Development Center, SK Telecom, Seongnam, South Korea, working on the design of automotive CMOS image sensors with SK hynix. In 2013, he joined the School of Electronic Engineering, Kumoh National Institute of Technology, Gumi, Korea, as a Faculty Member. His current research area is the design of CMOS image sensors, low-power data converters, high performance sensors, and interface circuits.

Young-Chan Jang

Young-Chan Jang received the B.S. degree in the department of elec¬tronic engineering from Kyungpook National University, Daegu, Korea, in 1999 and the M.S. and Ph.D. degrees in electronic engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2001 and 2005, respectively. From 2005 to 2009, he was a Senior Engineer in the Memory Division, Samsung Electronics, Hwasung, Korea, working on high-speed interface circuit design and next-generation DRAM. In 2009, he joined the School of Electronic Engineering, Kumoh National Institute of Technology, Gumi, Korea, as a Faculty Member, where he is currently Professor. His current research area is high-performance mixed-mode circuit design for VLSI systems such as high-performance signaling, clock generation, and analog-to-digital conversion.


text:
# Does a target have total cover from a ranged attacker positioned on an opposite corner of a hallway?

Consider the diagram below:

 N    *******   * = Wall
W E   .......   . = Open Space
S    .A***T.   A = Attacker
T = Target

# Does the target have total cover from the attacker?

The following quote has the relevant rules:

To determine whether your target has cover from your ranged attack, choose a corner of your square. If any line from this corner to any corner of the target’s square passes through a square or border that blocks line of effect or provides cover, or through a square occupied by a creature, the target has cover (+4 to AC).

[...]

Total Cover: If you don’t have line of effect to your target (that is, you cannot draw any line from your square to your target’s square without crossing a solid barrier), he is considered to have total cover from you. You can’t make an attack against a target that has total cover.

Source: Core Rulebook pg.195-196

My interpretation:

• Every corner of the attacker's square has at least one line to one of the target's square's corners passing through the wall. The target has cover.
• A line can be traced from either of the northern corners of the attacker to either of the northern corners of the target. This line runs parallel to the wall but does cross it. The target does not have total cover.

# Is this interpretation of the rules correct?

• Welcome to rpg.se! Take the tour if you haven't already and check out this meta for other places you can find help. This is a great first question, well explained with great diagrams. Thanks for participating and happy gaming! – linksassin Jun 25 '19 at 3:33

# The target has total cover from the attack

The Core Rulebook doesn't cover this exact situation very well. As you say, you can draw lines parallel to, but not passing through, the wall. So it is possible this only provides cover, not total cover. My ruling is that the wall provides total cover in this situation and I will justify my reasons for it.

### RAW Support from the Hero's Handbook

There is a diagram on page 57 of the Hero's Handbook (from the Beginner's Box) that covers this exact situation. I will try to translate their pretty diagram here:

      ........   * = Wall
N    2.......   . = Open Space
W E   *TT***3.   1,2,3 = Attacker Number
S    *TT****.   T = Target
*1.*****

Paraphrasing their annotations for each attack.

• Target does not have cover from attacker 1
• Target has cover from attacker 2 because at least one line passes through the wall.
• The target has total cover from attacker 3

Attacker 3 in this scenario is identical to your example. The book goes on to state the following about total cover:

If you are completely hidden behind a wall or other obstacle, enemies can't attack you. If every imaginary line you can draw from your corner to the enemy's corner goes through the cover, you have total cover from that enemy and you can't attack each other.

Now you could argue that the Beginner's Box is an overly simplified version of the rules and it doesn't apply to the full game. It does use very similar wording about the imaginary lines from corners however, and it is intended to serve as an introduction to the core rules. So it is certainly RAI for this situation to provide total cover even if RAW is slightly unclear.

### RAW Support from D&D 3.5

3.5 edition D&D is the immediate predecessor to Pathfinder and its ruleset is mostly compatible. In the Player's Handbook for 3.5e on page 139 we have the following text (emphasis mine):

Two creatures can see each other if they can trace at least one clear straight line from any part of one creature’s space to any part of the other creature’s space. The line is clear if it doesn’t cross or even touch squares that block line of sight.

The qualification that the lines cannot touch squares that block line of sight clears this up. Also note that this does not mean that the creatures have partial cover if they both move 1 square north. The rule is any part to any part not all parts to all parts. The lines can go diagonally to avoid touching the wall.

Thanks to HeyICanChan in the comments for this one.

### My interpretation of Core Rulebook RAW

With the Core Rulebook RAW situation being unclear the best I can do it provide you with my interpretation of the rules. This entire situation hinges on the single line which runs from the north edge of the attack to the north edge of the target. The argument that this does not provide total cover it because the line passes by the cover but does not "cross" it.

I would argue that if a line could be consider to not "cross" cover by only passing along the intersection between the cover square and the next, then the line also does not intersect with the targets square by the same logic. Therefore the wall should provide total cover, is the creatures are considered to be filling their entire square so should the cover.

### Use DM discretion

As there is no clear determination either way you can use some situational discretion. If the target is hiding around the corner, attempting to use the wall as cover they are unlikely to leave an arm or a leg sticking out. In that situation I would rule that the wall provides total cover. Conversely, if the target is ducking in and out of cover to fire back at the attacker then you could easily rule that it only provides cover not total cover.

Use logic and common sense to determine a ruling that feels right based on the situation. You mentioned in the comments that the Hero's Handbook example depicts a jagged wall that passes beyond the grid lines. That is the sort of thing you can use to help determine the correct ruling here. Perhaps jagged cave walls provide total cover where smooth castle bricks would not? However you rule is unlikely to make a major difference as the creatures can easily move slightly further into or out of cover to correct the situation.

• Comments are not for extended discussion; this conversation has been moved to chat. – V2Blast Jun 26 '19 at 2:00
• While I was originally hoping for an answer clearly defined by the core RAW, realistically it seems that there simply isn't one. Therefore I'm accepting this answer for citing as many sources as possible as well as offering a very reasonable interpretation and advice for use in-game. Thanks @linksassin! – David Jun 27 '19 at 3:29

## Yes

Assuming the wall does not touch/cross the line at any point. If the wall does touch the line than the target has total cover. Whether the wall touches the line depends on the convention that you use when drawing your maps - the wall can go up to the line or on to the line - if the former it has cover, if the latter total cover.


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# zbMATH — the first resource for mathematics

How to select a loser. (English) Zbl 0795.90103
The author considers the following problem: A party of $$N$$ people selects one of its members. Everybody is flipping a coin with outputs 0 and 1, each with probability 1/2. Then, recursively, the 0-party continues until the loser is found. It is shown that this procedure stops on the average after about $$\log_ 2 N$$ steps. The average size (number of nodes) of such an incomplete tree is about $$2\log_ 2 N$$, the average number of coin-flippings being exactly $$2N$$. Some modifications of the selection problem are also discussed.

##### MSC:
 91A60 Probabilistic games; gambling 11B68 Bernoulli and Euler numbers and polynomials
##### Keywords:
coin-flippings; selection problem
Full Text:
##### References:
 [1] Flajolet, P.; Sedgewick, R., Digital search trees revisited, SIAM J. comput., 15, 748-767, (1986) · Zbl 0611.68041 [2] Flajolet, P.; Vitter, J.S., Average-case analysis of algorithms and data structures, () · Zbl 0900.68251 [3] Knuth, D.E., The art of computer programming, Vol. 1, (1968), Addison-Wesley Reading, MA · Zbl 0191.17903 [4] Knuth, D.E., The art of computer programming, Vol. 3, (1973), Addison-Wesley Reading, MA · Zbl 0191.17903 [5] Mathys, P.; Flajolet, P., Q-ary collision resolution algorithms in random-access systems with free or blocked channel access, IEEE trans. inform. theory, 31, 217-243, (1985) · Zbl 0566.94001 [6] Szpankowski, W., Solution of a linear recurrence equation arising in the analysis of some algorithms, SIAM J. algebraic discrete methods, 8, 233-250, (1987) · Zbl 0648.68059 [7] Szpankowski, W., The evaluation of an alternative sum with applications to the analysis of some data structures, Inform. process. lett., 28, 13-19, (1988) · Zbl 0657.68071
This reference list is based on information provided by the publisher or from digital mathematics libraries. Its items are heuristically matched to zbMATH identifiers and may contain data conversion errors. It attempts to reflect the references listed in the original paper as accurately as possible without claiming the completeness or perfect precision of the matching.


text:
# [XeTeX] Hoefler Text Ornaments

GARCIN jeanlouisgarcin at free.fr
Wed Oct 13 18:01:59 CEST 2010

Fisrt I thank alls  the members of this list who have helped me.

With their ideas I have found what  I was looking for;

So I give  an example of a source code which must be  typessetted  with Xelatex.

\documentclass[a4paper,12pt]{article}

\usepackage{fontspec,xltxtra}

\begin{document}

\font\1="Hoefler Text Ornaments: color=DD2000" at 72pt

\1\char "F074

\end{document}

Best regards

Jean-Louis Garcin


text:
## Chemistry: Molecular Approach (4th Edition)

A mole is a unit that is defined by the amount of material containing 6.022 x 10$^{23}$ particles. 6.022 x 10$^{23}$ is Avogadro's number. The mole is useful for converting: (1) from a number of moles to a number of atoms and vice versa (2) from mass to a number of moles and vice versa.
A mole is a unit that is defined by the amount of material containing 6.022 x 10$^{23}$ particles. 6.022 x 10$^{23}$ is Avogadro's number. The mole is useful for converting: (1) from a number of moles to a number of atoms and vice versa (2) from mass to a number of moles and vice versa.


text:
# Power loss in transmission lines

by IniquiTrance
Tags: lines, loss, power, transmission
 Share this thread:
 P: 186 1. The problem statement, all variables and given/known data A power station delivers 890 kW of power at 12 kV to a factory through wires with total resistance 5.0 $$\Omega$$. How much less power is wasted if the electricity is delivered at 50 kV rather than 12 kV? 2. Relevant equations eq-1) P = IV eq-2) P = I2R Ohm's Law: V = IR 3. The attempt at a solution I know the problem can be solved by solving for the current value in each case from eq-1, and plugging it in to eq-2 to calculate power loss. My real question is why can't we apply Ohm's law to calculate I, and then plug it into eq-2? Why must we use eq-1 to get the current? Doesn't Ohm's law apply for all ohmic conductors, and since we have both the resistance and voltage of and across the conductor, can't we get the current that way? Thanks!
 HW Helper P: 3,394 If you apply Ohm's Law to the line resistance, you would need to know the voltage drop in the line. If you apply it to the load plus the line, you would have to use the combined resistance of line and load. You could use the power formula to find the load resistance, then use Ohm's Law to find the current.
P: 186
 Quote by Delphi51 If you apply Ohm's Law to the line resistance, you would need to know the voltage drop in the line. If you apply it to the load plus the line, you would have to use the combined resistance of line and load. You could use the power formula to find the load resistance, then use Ohm's Law to find the current.
Thanks for the reply!

So when you have a 12kV transmission line, what is the 12 kV drop across? The negative terminal is obviously at the powerplant, the positive, after passing through the load, back at the powerplant?

HW Helper
P: 3,394
Power loss in transmission lines

 A power station delivers 890 kW of power at 12 kV to a factory
The wording is careful, as it should be, to make it clear that the potential at the load is 12 Kv. It will have to be larger at the source to make up for the loss in the line resistance.

Virtually all transmission lines are AC, so there is no negative or positive terminal.
Sci Advisor
HW Helper
P: 8,953
 Quote by IniquiTrance so when you have a 12kV transmission line, what is the 12 kV drop across?
It's between the output of the power line and ground - and in an ideal world is the same as the difference between the input to the powerline and ground.

This confuses everybody who first sees this question - do a search here and you will see dozens of threads on it!
 P: 186 Thank you! I have a much better understanding of the concept now.
Sci Advisor
HW Helper
P: 6,679
 Quote by IniquiTrance Thanks for the reply! So when you have a 12kV transmission line, what is the 12 kV drop across? The negative terminal is obviously at the powerplant, the positive, after passing through the load, back at the powerplant?
The voltage is the potential difference with no load. It does not matter what the load is. The question does not ask how much power is lost. It just asks for the relative power loss at these two different line voltages. All you have to know is that for a given load, if the 12Kv line has current I the 50Kv line the current will be 12I/50. The power loss across the line will be I^2R where R is 5 ohms so you can easily calculate the relative line losses.

AM
 P: 2 KW KV R I=KW/KV Loss=I*I*R Loss reduction 890 12 5 74.17 27503.47 890 50 5 17.8 1584.2 25919.27 PF=1
 P: 2 KW KV R I=KW/KV Loss=I*I*R Loss reduction 890 12 5 74.17 27503.47 890 50 5 17.8 1584.2 25919.27 PF=1 890 kw 12kv current= 890/12=74.17 Amp assuption pf=1, loss= I*I*R=27503 W 890kw, 50kv, current=890/50=17.8 amp, loss= 1584.2 w, loss reduction= 25919.27 w, As the voltage increases, current decreases for same power. current decreases loss also decreases. current has a squred relation with loss.

 Related Discussions Engineering, Comp Sci, & Technology Homework 3 Electrical Engineering 9 Introductory Physics Homework 1 General Discussion 6


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# Paraboloidal coordinates

Paraboloidal coordinates are a three-dimensional orthogonal coordinate system $(\lambda, \mu, \nu)$ that generalizes the two-dimensional parabolic coordinate system. Similar to the related ellipsoidal coordinates, the paraboloidal coordinate system has orthogonal quadratic coordinate surfaces that are not produced by rotating or projecting any two-dimensional orthogonal coordinate system.

Coordinate surfaces of the three-dimensional paraboloidal coordinates.

## Basic formulae

The Cartesian coordinates $(x, y, z)$ can be produced from the ellipsoidal coordinates $( \lambda, \mu, \nu )$ by the equations

$x^{2} = \frac{\left( A - \lambda \right) \left( A - \mu \right) \left( A - \nu \right)}{B - A}$
$y^{2} = \frac{\left( B - \lambda \right) \left( B - \mu \right) \left( B - \nu \right)}{A - B}$
$z = \frac{1}{2} \left( A + B - \lambda - \mu -\nu \right)$

where the following limits apply to the coordinates

$\lambda < B < \mu < A < \nu$

Consequently, surfaces of constant $\lambda$ are elliptic paraboloids

$\frac{x^{2}}{\lambda - A} + \frac{y^{2}}{\lambda - B} = 2z + \lambda$

and surfaces of constant $\nu$ are likewise

$\frac{x^{2}}{\nu - A} + \frac{y^{2}}{\nu - B} = 2z + \nu$

whereas surfaces of constant $\mu$ are hyperbolic paraboloids

$\frac{x^{2}}{\mu - A} + \frac{y^{2}}{\mu - B} = 2z + \mu$

## Scale factors

The scale factors for the paraboloidal coordinates $(\lambda, \mu, \nu )$ are

$h_{\lambda} = \frac{1}{2} \sqrt{\frac{\left( \mu - \lambda \right) \left( \nu - \lambda \right)}{ \left( A - \lambda \right) \left( B - \lambda \right)}}$
$h_{\mu} = \frac{1}{2} \sqrt{\frac{\left( \nu - \mu \right) \left( \lambda - \mu \right)}{ \left( A - \mu \right) \left( B - \mu \right)}}$
$h_{\nu} = \frac{1}{2} \sqrt{\frac{\left( \lambda - \nu \right) \left( \mu - \nu \right)}{ \left( A - \nu \right) \left( B - \nu \right)}}$

Hence, the infinitesimal volume element equals

$dV = \frac{\left( \mu - \lambda \right) \left( \nu - \lambda \right) \left( \nu - \mu\right)}{8\sqrt{\left( A - \lambda \right) \left( B - \lambda \right) \left( A - \mu \right) \left( \mu - B \right) \left( \nu - A \right) \left( \nu - B \right) }} \ d\lambda d\mu d\nu$

Differential operators such as $\nabla \cdot \mathbf{F}$ and $\nabla \times \mathbf{F}$ can be expressed in the coordinates $(\lambda, \mu, \nu)$ by substituting the scale factors into the general formulae found in orthogonal coordinates.

## Bibliography

• Morse PM, Feshbach H (1953). Methods of Theoretical Physics, Part I. New York: McGraw-Hill. p. 664. ISBN 0-07-043316-X. LCCN 52011515.
• Margenau H, Murphy GM (1956). The Mathematics of Physics and Chemistry. New York: D. van Nostrand. pp. 184–185. LCCN 55010911.
• Korn GA, Korn TM (1961). Mathematical Handbook for Scientists and Engineers. New York: McGraw-Hill. p. 180. LCCN 59014456. ASIN B0000CKZX7.
• Arfken G (1970). Mathematical Methods for Physicists (2nd ed.). Orlando, FL: Academic Press. pp. 119–120.
• Sauer R, Szabó I (1967). Mathematische Hilfsmittel des Ingenieurs. New York: Springer Verlag. p. 98. LCCN 67025285.
• Zwillinger D (1992). Handbook of Integration. Boston, MA: Jones and Bartlett. p. 114. ISBN 0-86720-293-9. Same as Morse & Feshbach (1953), substituting uk for ξk.
• Moon P, Spencer DE (1988). "Paraboloidal Coordinates (μ, ν, λ)". Field Theory Handbook, Including Coordinate Systems, Differential Equations, and Their Solutions (corrected 2nd ed., 3rd print ed.). New York: Springer-Verlag. pp. 44–48 (Table 1.11). ISBN 978-0-387-18430-2.


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# Mathematica Presentation Cell Formatting

In one of the Mathematica (v9) slide templates, they have an example cell that looks like this:

Where there is a "SideCaption" that appears to be the Mathematica-equivalent of a text box to the right of the image. I can't for the life of me figure out how this is replicate this other than copying the cell and pasting elsewhere.

I did find this code looking at the notebook file however:

Cell["SideCaption How do I get this?", "SideCaption"]

Is this something I can generate programmatically, or something that needs to be copied when used elsewhere? I could see this format being used in more places than presentations.

-

CellPrint@
Cell[BoxData[
TagBox[GridBox[{{ToBoxes[Graphics[Circle[]]],
Cell["Text", "SideCaption"]}}], "Grid"]], "SideCaptionArray"]

SideCaption and SideCaptionArray are in the Default.nb style sheet if you want to change them.

-
Nice! I did not know about "SideCaption" and "SideCaptionArray" (edit: I now see that the OP had also mentioned it) – R. M. Mar 13 '13 at 21:23
Sweeeeeeeeeeeeet. – kale Mar 13 '13 at 21:28

In Mathematica 10.3 we now have TextGrid:

TextGrid[{{Import["ExampleData/ocelot.jpg"], "SideCaption How do I get this?"}}]

and you can edit the text in the output just like in the presentation template.

-


text:
## When nothing is everything in Set theory

In an earlier post, I discussed the basic and most important aspects of Set theory, Functions and Real Number System. In the same, there was a significant discussion about the union and intersection of sets.…

## On Ramanujan’s Nested Radicals

Ramanujan (1887-1920) discovered some formulas on algebraic nested radicals. This article is based on one of those formulas. The main aim of this article is to discuss and derive them intuitively. Nested radicals have many…

## Free Online Algebra and Topology Books

This is a brief list of free e-books on Algebra, Topology and Related Mathematics. I hope it will be very helpful to all students and teachers searching for high quality content. If any link is…


text:
If you're seeing this message, it means we're having trouble loading external resources on our website.

If you're behind a web filter, please make sure that the domains *.kastatic.org and *.kasandbox.org are unblocked.

Main content

## AP®/College Physics 1

### Unit 1: Lesson 7

Objects in freefall

# Solving freefall problems using kinematic formulas

You might need: Calculator

## Problem

A squirrel drops an acorn onto the head of an unsuspecting dog. The acorn falls 4, point, 0, start text, m, end text before it lands on the dog. We can ignore air resistance.
How many seconds did the acorn fall?
Round the answer to two significant digits.
Answer using a coordinate system where upward is positive.
start text, s, end text
Stuck?
Stuck?


text:
# PyTorch – How to crop an image at a random location?

To crop an image at a random location, we apply RandomCrop() transformation. It's one of the many important transforms provided by the torchvision.transforms module.

The RandomCrop() transformation accepts both PIL and tensor images. A tensor image is a torch tensor with shape [C, H, W], where C is the number of channels, H is the image height and W is the image width.

If the image is neither a PIL image nor tensor image, then we first convert it to a tensor image and then apply RandomCrop().

## Syntax

torchvision.transforms.RandomCrop(size)(img)

where size is the desired crop size. size is a sequence like (h, w), where h and w are the height and width of the cropped image. If size is an int, then the cropped image will be a square image.

It returns the cropped image at a random location of given size.

## Steps

We could use the following steps to crop an image at a random location with given size −

• Import the required libraries. In all the following examples, the required Python libraries are torch, Pillow, and torchvision. Make sure you have already installed them.

import torch
import torchvision
import torchvision.transforms as T
from PIL import Image
• Read the input image. The input image is a PIL image or a torch tensor.

img = Image.open('meteor.jpg')
• Define a transform to crop the image at random location. The crop size is (200,250) for rectangular crop and 250 for square crop. Change the crop size according your need.

# transform for rectangular crop
transform = T.RandomCrop((200,250))
# transform for square crop
transform = T.RandomCrop(250)
• Apply the above-defined transform on the input image to crop the image at random location.

img = transform(img)
• Visualize the cropped image.

img.show()

## Input Image

This image is used as the input in all the following examples.

## Example 1

The following Python3 program shows how to crop an input PIL image at a random location.

# import required libraries
import torch
import torchvision.transforms as T
from PIL import Image

# read the input image
img = Image.open('meteor.png')

# define transform to crop the image at
# random location
transform = T.RandomCrop((250,500))
img = transform(img)
img.show()

## Output

It will produce the following output −

## Example 2

import torch
import torchvision.transforms as T
from PIL import Image

img = Image.open('lena.jpg')
transform = T.RandomCrop((250,500), padding=50)
img = transform(img)
img.show()

## Output

It will produce the following output. Notice that the padding is random.

## Example 3

# import required libraries
import torch
import torchvision.transforms as T
from PIL import Image
import matplotlib.pyplot as plt

# read the input image
img = Image.open('meteor.png')

# define the transform with crop size
transform = T.RandomCrop((100,150))

# crop four images
imgs = [transform(img) for _ in range(4)]

# display these cropped images
fig = plt.figure(figsize=(7,3))
rows, cols = len(imgs),1
for j in range(0, len(imgs)):
fig.add_subplot(rows, cols, j+1)
plt.imshow(imgs[j])
#plt.xticks([])
#plt.yticks([])
plt.show()

## Output

It will produce the following output −

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text:
# Coin Tossed

A fair coin is tossed $$six$$ times. The probability of obtaining $$4$$ or more heads is $$\text{__________}$$.

×

Problem Loading...

Note Loading...

Set Loading...


text:
# Test The Past Week in Fox Soccer

Been away and missed the action? Don’t worry we bring you the

best news from the past week.

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Venezuela. There was plenty of goalmouth action but tournament

favorite Brazil just could find the clinical edge they needed to

convert their chances into goals.

src="http://static.foxsports.com/content/fsc/img/2011/07/03/copa_copy_cats_bb_rf_story_070311_20110703170118443_730_350.JPG"

width="100%" />

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Over in Europe the women’s Brazilian team exploded into life

with a 3-0 victory over Norway. Reigning women’s World Player of

the Year, Marta, scored one goal and setup two more to put the

Canarinhas top of Group C.

src="http://static.foxsports.com/content/fsc/img/2011/07/03/wwc_she_has_arrived_bb_rf_070311_20110703164515432_730_350.JPG"

width="100%" />

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blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah Blah blah yackety yackey blah blah

blah Blah blah yackety yackey blah blah blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah.

The U.S. women’s national team continued their strong start at

the World Cup in Germany with another big victory, this time

against Colombia.

src="http://static.foxsports.com/content/fsc/img/2011/07/02/p_20110702134737373_730_350.JPG"

width="100%" />

The result puts the USA in control of their group and also

cemented their place in the quarterfinals.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah Blah blah yackety yackey blah blah

blah Blah blah yackety yackey blah blah blah Blah blah yackety

yackey blah blah blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah.

Copa America host Argentina got their campaign off to rather low

key start snatching a late draw against unfancied Bolivia.

Argentina struggled to get any fluency into their play and paid the

price early on when Bolivia took the lead.

src="http://static.foxsports.com/content/fsc/img/2011/07/02/copa_am_no_excuses_bb_rf_070211_20110702124416320_730_350.JPG"

width="100%" />

This seemed to get the Argentines out of their reverie and they

started to take the game to the Bolivians in earnest. But it took

them to the 84th minute before forward Kun Aguero tucked away a

loose ball to spare the Copa hosts an embarassing start to the

tournament.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah Blah blah yackety yackey blah blah

blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah.

After the U.S. men’s national team’s capitulation to Mexico in

the final of the Gold Cup there is plenty of speculation over coach

Bob Bradley’s future with the side.

Our Ives Galarcep weighed into the argument saying that it is

easier to talk about getting rid of the coach than it is to

actually do.

src="http://static.foxsports.com/content/fsc/img/2011/07/01/usa_fire_bob_bb_rf_070111_20110701124845580_730_350.JPG"

width="100%" />

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah.

Blah blah yackety yackey blah blah blah Blah blah yackety yackey

blah blah blah Blah blah yackety yackey blah blah blah Blah blah

yackety yackey blah blah blah Blah blah yackety yackey blah blah

blahv.


text:
# some questions about high precesion constant current source

E

#### [email protected]

Jan 1, 1970
0
hi,everybody.
I have some questions about hight precesion constant current source.My
goal is 1uA whose error is blow 0.01%.

In my circuit I used a op-amp,p-mosfet and 5V voltage reference.
But the result is so bad,the error is almost 1%.

Could somebody give me some hints?
Thanks very much.

eehinjor

E

#### eehinjor

Jan 1, 1970
0
1,the voltage of the load is between 0V~5.5V.

2,the output of voltage reference is 5V.

3,the sources of op-amp are +12V and -12V.

thanks

J

#### John Popelish

Jan 1, 1970
0
hi,everybody.
I have some questions about hight precesion constant current source.My
goal is 1uA whose error is blow 0.01%.

In my circuit I used a op-amp,p-mosfet and 5V voltage reference.
But the result is so bad,the error is almost 1%.

Could somebody give me some hints?
Thanks very much.

eehinjor
So you must have a current sense resistor that drops 5 volts when 1 uA
passes through it. That would be a 200k resistor, right? In order
for the closed loop to have .01% accuracy, not only do you need
sufficient loop gain, but the opamp input impedance would have to be
more than 10,000 times this 200k, or greater than 2 giga ohms. What
opamp are you using?

C

#### Chris

Jan 1, 1970
0
hi,everybody.
I have some questions about hight precesion constant current source.My
goal is 1uA whose error is blow 0.01%.

In my circuit I used a op-amp,p-mosfet and 5V voltage reference.
But the result is so bad,the error is almost 1%.

Could somebody give me some hints?
Thanks very much.

eehinjor
eehinjor said:
1,the voltage of the load is between 0V~5.5V.

2,the output of voltage reference is 5V.

3,the sources of op-amp are +12V and -12V.

thanks

Hi, eehinjor. Welcome to the newsgroup. For things like this,
typically

* 1% is easy -- just cobble together a cookbook circuit

* 0.1% requires quite a bit of attention to detail, but is usually not
too tough and somewhat more expensive

* 0.01% starts getting into lab quality -- really tough and much higher
cost for precision components
From your description, you have something like this (view in fixed font
or M$Notepad):    VCC VCC  | +  .-. | -----> +  | | '----------o  R1| | 1uA  '-' .----------o  |5.000V VCC | <---- -  o-----. + |  | | IC2 | |  IC1/-/ | |\| ||-+  ^ '-------|+\ ||-> Q1  | | >---||-+  | .--|-/ |  | | |/| |  === | === |  GND | GND |  '------------o  |  .-.  R2 | |  | |  '-'  |  ===  GND created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de (You might want to download Andy's ASCII Circuit -- it's a lot easier to use a picture to describe what you're doing.) If you would, a few questions: * If the above circuit is correct, could you please specify what you're using for IC1, IC2, R2 (wirewound/metal film/metal oxide/carbon film, with tolerance), and Q1? Each one of these components could easily be the culprit. If the above isn't correct, what's different? * What's your budget? If you actually had to pay much more than a couple of bucks for 0.01%, would you still want it as badly? Can you live with less? * Do you need accuracy as well as precision? In other words, do you need an 0.01% DC current source at somewhere around 1uA, or does it have to be exactly 1.00000uA? That's going to be more difficult. * What's the temperature range for this circuit? * You've said you've got a burden which will cause a load voltage between 0 and 5.5V. But you didn't describe the load, or what you're doing with it. Is this an instrument which has banana jacks, and you want 200 feet of wire going out to the load and back? Is the load purely resistive? Are you planning on unplugging it while the circuit is on? Or only off? Please describe. * Have you put a scope on the output, looking for oscillations? This is basically a unity gain non-inverting amplifier, and is prone to misbehaving. Depending on your components, your circuit may actually be operating correctly as a high speed oscillator. * While we're on the subject, what are you using to measure current and check your circuit? Even measuring DC current to that accuracy requires a bit more than a handheld DVM. If this is a dedicated circuit with a purely resistive load in very close proximity to your circuit, it might be easier to lose the FET and do something like this:  .---. R(load)  | | + ___ -  === | .-o--|___|--o---.  GND | | |  | | |  /-/ | VCC |  ^ | + |  | ___ ___ | |\| |  -5.000Vo--|___|-o-|___|---o---|-\ |  | | | >--------'  .-. .-. .---|+/  | | | | | |/|  | | | | | -  '-' '-' === Vee  | | GND  - ===  Vee GND created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de By using a pA input low drift op amp and high precision low temperature coefficient resistors, you might be able to get close to 0.01% precision without too much difficulty within a lab temperature range if your reference is up to the task. Getting it accurate to 1.00000uA, though, would pretty much be luck, or would require careful nulling of the op amp offset and an adjustable reference, which has its own set of problems (like potentiometer drift with temperature, &c). Of course, this basic circuit won't help you if you've got those hundreds of feet of wire, a reactive load, or you have to be able to disconnect the load hot. It also is very susceptible to ESD damage, as you've got an op amp input floating in the breeze. A better response awaits more information from you. Good luck Chris J #### John Popelish Jan 1, 1970 0 John said: So you must have a current sense resistor that drops 5 volts when 1 uA passes through it. That would be a 200k resistor, right? In order for the closed loop to have .01% accuracy, not only do you need sufficient loop gain, but the opamp input impedance would have to be more than 10,000 times this 200k, or greater than 2 giga ohms. What opamp are you using? Damn, I have to get some caffeine in me before posting. 5 volts reference with 1 uA current implys a 5 mega ohm current sense resistor and an opamp impedance of 5 gig ohms for .01% accuracy. Of course, the sense resistor also has to be accurate and stable to better than ..01% and so does the reference. The opamp offset voltage must also be less than a half millivolt. The frequency response of such a source will also be accurate only for very low frequencies where capacitive current is less than .01% of the source current. E #### eehinjor Jan 1, 1970 0 Thank you very much. I know this is very difficult,I have done some experiment,but all the result is so bad. The resistor is 5000K.In my circuit,the op-amp is OPA602. J #### John Fields Jan 1, 1970 0 .... or M$ Notepad):

 VCC VCC
| +
 .-. | -----> +
| | '----------o
 R1| | 1uA
'-' .----------o
 |5.000V VCC | <---- -
o-----. + |
 | | IC2 | |
IC1/-/ | |\| ||-+
 ^ '-------|+\ ||-> Q1
| | >---||-+
 | .--|-/ |
| | |/| |
 === | === |
GND | GND |
 '------------o
|
 .-.
R2 | |
 | |
'-'
 |
===
` GND This
is basically a unity gain non-inverting amplifier, and is prone to
misbehaving.
^^^^^^^^^^^^^
inverting

....

J

#### John Popelish

Jan 1, 1970
0
eehinjor said:
Thank you very much.
I know this is very difficult,I have done some experiment,but all the

The resistor is 5000K.In my circuit,the op-amp is OPA602.
The opamp is pretty good (bias current within minimum requirements and
offset voltage probably also). But what is the gate leakage current
of your PMOS transistor, and how do you build this thing with surface
leakage current to the sense node much lower than the .1 nA error budget?

E

#### eehinjor

Jan 1, 1970
0
the type of my p-mosfet is VP0610L.its gate leakage current is only
10nA(max.).

Unfouturnately VP0610L is obselete from last year,I don't know which
one can replace it or better than it.

I used a intrument of Agilient,the type is 3458A.it can measure current
as low as 1nA.

J

#### John Popelish

Jan 1, 1970
0
eehinjor said:
the type of my p-mosfet is VP0610L.its gate leakage current is only
10nA(max.).

Yikes. That is 100 times your leakage current budget of 0.1 nA.
Unfouturnately VP0610L is obselete from last year,I don't know which
one can replace it or better than it.

I don't know what a better one would be, but it must have lower gate
leakage and probably would be a much smaller die, maybe rated for a
higher voltage.

E

#### eehinjor

Jan 1, 1970
0
Thank you very much,John.

But when I try to use this circuit to realize 1mA constant current
source,the result is also unsatisfied.

I don't know the reason,so I am afraid the circuit is wrong.

J

#### John Popelish

Jan 1, 1970
0
eehinjor said:
Thank you very much,John.

But when I try to use this circuit to realize 1mA constant current
source,the result is also unsatisfied.

I don't know the reason,so I am afraid the circuit is wrong.

I haven't seen your circuit, including the test setup that you are
using to get this unsatisfactory result.

M

#### mike

Jan 1, 1970
0
John said:
The opamp is pretty good (bias current within minimum requirements and
offset voltage probably also). But what is the gate leakage current of
your PMOS transistor, and how do you build this thing with surface
leakage current to the sense node much lower than the .1 nA error budget?

At what level of accuracy do you have to start worrying about
thermoelectric effects of the interconnect?
mike

--
Return address is VALID but some sites block emails
..
Wanted, PCMCIA SCSI Card for HP m820 CDRW.
FS 500MHz Tek DSOscilloscope TDS540 Make Offer
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Bunch of stuff For Sale and Wanted at the link below.
MAKE THE OBVIOUS CHANGES TO THE LINK
ht<removethis>tp://www.geocities.com/SiliconValley/Monitor/4710/

E

#### eehinjor

Jan 1, 1970
0
Thanks all.The circuit is shown as below.
Q1:VP0610L;
Q2:2N4402;
IC1:OPA602;
R1:the resistor(5000K ohm),it is composed of 4990Kohm fixed
resistor(0.1%,15ppm/c) and a 20Kohm variable resistor;
+12V,-12Vower;
+7V:it is produce by INA105 and AD586(+5V voltage reference);
+5.5V:to avoid the voltage of RL over this value;

In fact,my goal is 1mA/100uA/10uA/1uA when R1 is 5K/50K/500K/5000K.

By the way,the VP0610L has been obseleted from last year,would you like
recommand one?
From simulation result by pspice,the circuit is right,but the real
result is so bad.I don't know how to modify it.

+12V
|
.-.
| |
R1| |
'-'
|
|-----------------------o
| +12V |
| + |
| IC1 | |
| |\| ||-+
o-------------|-\ ||-> Q1
| >---||-+
+7V--------------|+/ |
|/| |
| |
- |
-12V |-------------------o
| |
|< .-.
+5.5V----| Q2 | |RL
|\ | |
| '-'
| |
o------------------ o
|
===
GND

E

#### eehinjor

Jan 1, 1970
0
Thank you,Chris.
There is a little difference between our circuits,but the theory is the
same.

I don't know what IC1 is in your first circuit.

Maybe I am confused between precesion and accurary.I only mean the
result shoule be 0.9999uA~1.0001uA.

The temperature is from 20C to 70C,of cource the wider the better.

The load is resistor,when its value is 5500Kohm and the current is
1uA,the voltage will be 5.5V.

best regards.

J

#### John Popelish

Jan 1, 1970
0
mike said:
At what level of accuracy do you have to start worrying about
thermoelectric effects of the interconnect?

That not only depends on the level of accuracy, but on the reference
voltage. This design, supposedly is based on a 5 volt reference.
That is pretty huge compared to thermoelectric effects.

E

#### eehinjor

Jan 1, 1970
0
Just now I simulate the Chris's first circuit,found the result is
worse.
especially when the load is smaller than 500K,the output is not
constant.

C

#### Chris

Jan 1, 1970
0
eehinjor said:
Thank you,Chris.
There is a little difference between our circuits,but the theory is the
same.

I don't know what IC1 is in your first circuit.

Maybe I am confused between precesion and accurary.I only mean the
result shoule be 0.9999uA~1.0001uA.

The temperature is from 20C to 70C,of cource the wider the better.

The load is resistor,when its value is 5500Kohm and the current is
1uA,the voltage will be 5.5V.

best regards.
eehinjor said:
Just now I simulate the Chris's first circuit,found the result is
worse.
especially when the load is smaller than 500K,the output is not
constant.

Hi, eehinjor. Apparently you've cross posted your question over at
sci.electronics.design as well as s.e.b. It's now clear that you are
trying to make a DC current calibrator with switchable currents in
decades down from 1mA to 1uA with 0.01% precision. Here's the key post
from s.e.d.:
Thanks all.

For me this task is a chanllege.I have done some experiment during past
months.
My goal is 1mA/100uA/10uA/1uA,the accuracy is 0.01%,the result is that
the output can be switched between them.Then some mux-chips will bring
error.

I have tried three ways.One,single op-amp & resistor.Second,two
op-amps,one of them as the feedback.Third,the op-amp & PMOSFET.Before
experiments,I simulated them by pspice.

The first two ways can acheive 1mA/100uA easily,but they can not
realize 10uA/1uA.
So I have to change the way to the third.But until now,I can not
realize 1mA by the third way.Maybe because I am not familar with
PMOSFET.

am sure I have to study more from all of you.

best regards.

A couple of points:

* I believe the biggest hangup you're having with your P-MOSFET circuit
is getting a 5 Meg resistor to stay stable to 0.01%. Higher resistance
values are a bear. Changes in ambient humidity are particularly
troublesome in making effective resistance values drift all over the
place. I would also be concerned about leakage current in the FET, and
possible oscillations.

* The second circuit I mentioned is only useful if you can put a
resistive load on the circuit board within a couple of inches of the op
amp. The circuit takes advantage of the "virtual ground" at the input
of the op amp. The divider of your voltage reference is set to inject
1uA into the inverting input. The op amp will work to put 1uA through
your load to balance the injected current, and keep the input at 0V.
This doesn't work if the feedback loop goes 2 meters through test probe
wires to your load or a meter, and then back. The inductance of the
leads and any noise pickup on the wires guarantees oscillation. The
simple op amp current null circuit I suggested is not useful for you.

You're discovering the hard way why current source meters with the kind
of accuracy you're specifying usually cost thousands of dollars new
(Keithley in particular is a good source for this kind of instrument).
They produce a dial-in, rock-stable current under varying loads. You
should know, however, that even these instruments are not specified to
the temperature range you specify -- they generally are only spec'ed
over lab temperature range.

If you need a calibrator, you can take hope in the thought that used
instruments are available at a fraction of the price of new. You may
be able to get something close to what you want (if you can lose the
commercial temp range) for hundreds rather than thousands of dollars.
An 0.01% dial-in or switchable current source is not a trivial project,
and not suitable for newbies.

If you still want to pursue this as a project, reread all the responses
to your posts in both newsgroups, particularly those of Mr. Popelish,
Ban, and Winfield Hill. They've given you a free helping of really

Then go to instrument manufacturer websites, and take a look at what's
out there commercially, what it can do, and what it costs. These
instruments are generally a real bargain, and give you good value for
your money. You will see, if nothing else, that what you're proposing
isn't exactly a trivial newbie project. If somebody could slap
together a little perfboard circuit that does what you propose, they
wouldn't be spending thousands of dollars for one of these instruments.

Also, get the operation/service manuals on one of the older Keithley
current sources, and take the time to examine the circuits in detail.
There's a real education in doing that, and may help you in getting the
knowledge you need to approach your job. But you might want to shoot
for 0.1% at best, especially considering your temp range.

Good luck
Chris

E

#### eehinjor

Jan 1, 1970
0
Thank you Chris.
This is my first time to google's group.This question is postd at
sci.electronics.design.

about MOSFET in our book,so my fault is some knowledge about it.

On your advice,I will do more expeiment step by step until the goal.

best regards.

B

#### Bob Masta

Jan 1, 1970
0
Thank you Chris.
This is my first time to google's group.This question is postd at
sci.electronics.design.

about MOSFET in our book,so my fault is some knowledge about it.

On your advice,I will do more expeiment step by step until the goal.

best regards.

One thought you might want to consider:
I have seen super-accurate *voltage* calibrators
that work via digital counters. The basic idea is
that you use a counter with some logic to go high
for the proportion of time you want to divide the
master reference by. For example, to produce
1.0 V from a 10.0 V master, you generate a pulse
that is high for one count out of 10, then use that
to switch the master. You have to filter the result
to get DC. That's easier at higher clock rates, but
higher clock rates have more time spent in switching
which needs to be compensated. Other than that,
the clock frequency is not critical since the whole
trick relies upon duty cycle, which being digital is
rock-solid.

Application of the above to *current* sources is
"left as an excercise for the student". Just giving
you an alternative approach.

Best regards,

Bob Masta

D A Q A R T A
Data AcQuisition And Real-Time Analysis
www.daqarta.com
Home of DaqGen, the FREEWARE signal generator

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text:
# How to prove $\{1,\sqrt[3]{2},\sqrt[3]{4}\}$ is an integral basis of $\mathbb{Q}(\sqrt[3]{2})$

This an exercise from Jürgen Neukirch.

(1.2.5) Show that $\{1,\sqrt[3]{2},\sqrt[3]{4}\}$ is an integral basis of $\mathbb{Q}(\sqrt[3]{2})$

And what's more, i'm still stuck on this problem.

(1.2.6) Show that $\{1,\theta,\frac{1}{2}(\theta+\theta^2)\}$ is an integral basis of $\mathbb{Q}(\theta)$, $\theta^3-\theta-4$.

My try:

The classical method. Assume that $a+b\sqrt[3]{2}+c\sqrt[3]{4}$ is integral over $\mathbb{Z}$, but the coefficients of its minimal polynomial forms a such complex equation to solve that i cannot conclude $a,b,c\in \mathbb{Z}$.

The discriminant method. A remark result about this is that if the discriminant of $f(x)$ is square-free then $\{1,x,\ldots,x^n\}$ is an integral basis of $\mathbb{Q}[X]/(f(x))$. But the discriminant of $X^3-2$ is $-108$, which fails to be square-free.

• You should see the answers to this question – Mathmo123 Oct 24 '17 at 22:19
• – Mathmo123 Oct 24 '17 at 22:19
• Prove that three given elements are linearly independent over $\mathbb Q$ (just like in a vectorial space). – Piquito May 26 '18 at 11:39

As pointed out already, this is equivalent to showing that $\mathbb{Z[^3\sqrt{2}]}$ is the ring of integers of $\mathbb{Q[^3\sqrt{2}]}$

If not, then the discriminant of the actual ring of integers will divide the discriminant of $\mathbb{Z[^3\sqrt{2}]}$, which is -108, by a square factor. The only squares dividing -108 are 4 and 9.

It is sufficient to check that $\frac{1 + ^3\sqrt{2} + ^3\sqrt{4}}{x}$ is not an algebraic integer for $x = 2,3$. The norm will give you this answer:

$$N(\frac{1 + ^3\sqrt{2} + ^3\sqrt{4}}{x}) = \frac{1 +2 + 4 - 6}{x^3} = \frac{1}{x^3}$$

Clearly not an integer for $x = 2,3$, so $\frac{1 + ^3\sqrt{2} + ^3\sqrt{4}}{x}$ is not an algebraic integer in these cases and the ring of integers must be $\mathbb{Z[^3\sqrt{2}]}$.

This is the general idea. You can find out more here (page 34 onwards): http://www.jmilne.org/math/CourseNotes/ANT210.pdf

• How did you conclude so immediately that $N(1+\sqrt[3]{2}+\sqrt[3]{4})=1+2+4-6$? I wanna know how to do it too – rmdmc89 Mar 12 '19 at 0:29


text:
# Tangent

### Formula for Tangent

Tangent is calculated as “opposite over adjacent.”

So in our fraction, the length of the opposite side is placed in the numerator and the length of the adjacent side is placed in the denominator.

$\text{tangent = } \dfrac{opposite}{adjacent}$

### Tangent of Angle a – Example 1

In the illustration below , side Z is the opposite side since it is on the other side of angle a.

The adjacent side is side X because it is next to angle a and it is not the hypotenuse.

So, the formula for tan of angle a is:

$\text{tan a = } \dfrac{Z}{X}$

### Tangent of Angle b – Example 2

Now let’s look at how to calculate the tangent of the other angle (angle b) in our example triangle.

In the illustration below, side X is the opposite side since it is on the other side of angle b.

The adjacent side is side Z because it is next to angle b and it is not the hypotenuse.

So, the formula for tan of angle b is:

$\text{tan b = } \dfrac{X}{Z}$

Sample question:

If cos A = y/z and sin A = x/z then tan A = ?

A. z/x

B. z/y

C. xy/z

D. x/y

E. y/x

In this problem, sin A = x/z and cos A = Y/z

Using the rules for sine and cosine, we know that:

$\text{sin A = } \dfrac{opposite}{hypotenuse} \text{= } \dfrac{X}{Z}$

So, side X is the opposite side and side Z is the hypotenuse.

We can then conclude that side Y is the adjacent side.

Finally, we can solve for tan:

$\text{tan A = } \dfrac{opposite}{adjacent} \text{= } \dfrac{X}{Y}$

You should also have a look at the exercises for sine and cosine.

More trigonometry exercises and examples can be found in this section of the website.


text:
# If $z = \frac{(\sqrt{3} + i)^n}{(\sqrt{3}-i)^m}$, find the relation between $m$ and $n$ such that $z$ is a real number.

I am given the following number $$z$$:

$$z = \dfrac{(\sqrt{3} + i)^n}{(\sqrt{3} - i)^m}$$

with $$n, m \in \mathbb{N}$$. I have to find a relation between the natural numbers $$n$$ and $$m$$ such that the number $$z$$ is real. I know that for a complex number to be real, its imaginary part must equal $$0$$, but I can't isolate the imaginary part. This is as far as I got:

$$\sqrt{3} + i = 2 \bigg (\frac{\sqrt{3}}{2} + i\frac{1}{2} \bigg) = 2 \bigg( \cos \dfrac{\pi}{6} + i \sin \dfrac{\pi}{6} \bigg )$$

$$\sqrt{3} - 1 = 2 \bigg ( \dfrac{\sqrt{3}}{2} - i \dfrac{1}{2} \bigg) = 2 \bigg ( \cos \dfrac{\pi}{6} - i \sin \dfrac{\pi}{6} \bigg ) = 2 \bigg ( \cos \dfrac{11\pi}{6} + i \sin \dfrac{11\pi}{6} \bigg )$$

So I got the numerator and the denominator in a form that I can use DeMoivre's formula on. So, next I'd have:

$$z = \dfrac{\bigg [2 \bigg ( \cos \dfrac{\pi}{6} + i \sin \dfrac{\pi}{6} \bigg ) \bigg ]^n} {\bigg [2 \bigg( \cos \dfrac{11 \pi}{6} + i \sin \dfrac{11 \pi}{6} \bigg ) \bigg ]^m }$$

$$z = 2^{n - m} \cdot \dfrac{\cos \dfrac{n \pi}{6} + i \sin \dfrac{n \pi}{6}} {\cos \dfrac{11 m \pi}{6} + i \sin \dfrac{11 m \pi}{6}}$$

But this is where I got stuck. I still can't isolate the imaginary part of $$z$$ in order to equal it to $$0$$.

• Multiply both the numerator and denominator by the conjugate of the denominator. Then you will be able to isolate real and imaginary parts. Jan 5, 2020 at 23:56

Hint: Imaginary part of $$\frac {a+ib} {c+id}$$ equals imaginary part of $$\frac {(a+ib) (c-id)} {|c+id|^{2}}$$ which is $$\frac {bc-ad} {c^{2}+d^{2}}$$ and this is $$0$$ iff $$ad=bc$$.

You may continue as follows,

$$z = 2^{n - m} \cdot \dfrac{\cos \dfrac{n \pi}{6} + i \sin \dfrac{n \pi}{6}} {\cos \dfrac{11 m \pi}{6} + i \sin \dfrac{11 m \pi}{6}}$$ $$=2^{n - m} \cdot \dfrac{\left(\cos \dfrac{n \pi}{6} + i \sin \dfrac{n \pi}{6}\right) \left(\cos \dfrac{11m \pi}{6} - i \sin \dfrac{11m \pi}{6}\right)} {\cos^2 \dfrac{11 m \pi}{6} + \sin^2 \dfrac{11 m \pi}{6}}$$

Then, set the the imaginary part of the numerator to zero,

$$I=\sin \dfrac{n \pi}{6}\cos \dfrac{11m \pi}{6} - \cos \dfrac{n \pi}{6}\sin \dfrac{11m \pi}{6} = -\sin\dfrac{(11m -n)\pi }{6}=\sin\dfrac{(m +n)\pi }{6}=0$$

which leads to $$\dfrac{(m+n)\pi }{6}= k\pi$$. Thus, the relationship between $$m$$ and $$n$$ is

$$m+n=6k$$

with $$k=0,1,2,...$$

• How did you get from $- \sin \dfrac{(11m - n) \pi}{6}$ to $\sin \dfrac{(m + n) \pi}{6}$? Why are they equal?
– user592938
Jan 8, 2020 at 0:32
• @user1502 $-\sin \frac{(11m-n)\pi}6 = \sin\frac{(12m-(m+n))\pi}6 = - \sin\frac{(m+n)\pi}6$. Jan 8, 2020 at 0:45

We have $$\sqrt{3}+i=2e^{i\pi/6}$$ and $$\sqrt{3}-i=2e^{-i\pi/6}$$. So $$\begin{eqnarray*} z = \dfrac{(\sqrt{3} + i)^n}{(\sqrt{3} - i)^m} = 2^{n-m} e^{ i \pi (n+m) /6}. \end{eqnarray*}$$ So we require $$n+m \equiv 0 \pmod{6}$$.

$$\sqrt {3} - i$$ is the conjugate to $$\sqrt {3} + i$$

$$\frac {(\sqrt 3 + i)^n}{(\sqrt 3 - i)^m} = \frac {(\sqrt 3 + i)^{n+m}}{(\sqrt 3 - i)^m(\sqrt 3 + i)^m}$$

This will rationalize the denominator $$\frac {(\sqrt 3 + i)^n}{(\sqrt 3 - i)^m} = \frac {(\sqrt 3 + i)^{n+m}}{4^{m}}$$

We must find where $$(\sqrt 3 + i)^{n+m}$$ is real

$$\sqrt 3 + i = 2(\cos \frac {\pi}{6} + i\sin \frac {\pi}{6})\\ (\sqrt 3 + i)^{n+m} = 2^{n+m}(\cos \frac {\pi}{6} + i\sin \frac {\pi}{6})^{n+m}\\ (\sqrt 3 + i)^{n+m} = 2^{n+m}(\cos \frac {(n+m)\pi}{6} + i\sin \frac {(n+m)\pi}{6})$$

if $$(\sqrt 3 + i)^{n+m}$$ is real $$\sin \frac {(n+m)\pi}{6} = 0$$

$$\frac {(n+m)\pi}{6} = k\pi\\ n+m = 6k$$

$$6$$ divides $$n+m$$

Hint:

Use the complex exponential notation and congruences: your final fraction is none other than $$z=2^{n-m}\frac{\mathrm e^{\tfrac{ni\pi}6}}{\mathrm e^{\tfrac{-mi\pi}6}}=2^{n-m} \mathrm e^{\tfrac{(n+m)i\pi}6},$$ anf it is a real number if and only if $$\frac{(n+m) \pi}6\equiv 0\mod \pi\iff (n+m)\pi \equiv 0\mod 6\pi\iff n+m\equiv 0\mod 6.$$

• should it be $e^{\color{red}-mi\pi/6}$ in the denominator? Jan 6, 2020 at 0:14
• @J.W.Tanner: Yes, of course! Thanks for pointing it! Jan 6, 2020 at 0:33

The key insight is to recognize roots of unity in the expression.

We have $$z = \frac{(\sqrt{3} + i)^n}{(\sqrt{3}-i)^m} = \frac{(2\omega)^n}{(2\omega^5)^m} = 2^{n-5m}\omega^{n-5m}$$ where $$\omega^6=-1$$. Therefore, we need $$n-5m \equiv 0 \bmod 6$$, or $$n+m \equiv 0 \bmod 6$$.