function_name
stringlengths 1
80
| function
stringlengths 14
10.6k
| comment
stringlengths 12
8.02k
| normalized_comment
stringlengths 6
6.55k
|
|---|---|---|---|
u8x8_Setup
|
void u8x8_Setup(u8x8_t *u8x8, u8x8_msg_cb display_cb, u8x8_msg_cb cad_cb, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)
{
/* setup defaults and reset pins to U8X8_PIN_NONE */
u8x8_SetupDefaults(u8x8);
/* setup specific callbacks */
u8x8->display_cb = display_cb;
u8x8->cad_cb = cad_cb;
u8x8->byte_cb = byte_cb;
u8x8->gpio_and_delay_cb = gpio_and_delay_cb;
/* setup display info */
u8x8_SetupMemory(u8x8);
}
|
/*
Description:
Setup u8x8 and assign the callback function. The dummy
callback "u8x8_dummy_cb" can be used, if no callback is required.
This setup will not communicate with the display itself.
Use u8x8_InitDisplay() to send the startup code to the Display.
Args:
u8x8 An empty u8x8 structure
display_cb Display/controller specific callback function
cad_cb Display controller specific communication callback function
byte_cb Display controller/communication specific callback funtion
gpio_and_delay_cb Environment specific callback function
*/
|
Description: Setup u8x8 and assign the callback function. The dummy callback "u8x8_dummy_cb" can be used, if no callback is required. This setup will not communicate with the display itself. Use u8x8_InitDisplay() to send the startup code to the Display. Args: u8x8 An empty u8x8 structure display_cb Display/controller specific callback function cad_cb Display controller specific communication callback function byte_cb Display controller/communication specific callback funtion gpio_and_delay_cb Environment specific callback function
|
u8x8_d_ssd1306_64x48_er
|
uint8_t u8x8_d_ssd1306_64x48_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)
{
if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )
{
u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_64x48_display_info);
return 1;
}
else if ( msg == U8X8_MSG_DISPLAY_INIT )
{
u8x8_d_helper_display_init(u8x8);
u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_er_init_seq);
return 1;
}
return u8x8_d_ssd1306_64x48_generic(u8x8, msg, arg_int, arg_ptr);
}
|
/* East Rising 0.66" OLED */
|
East Rising 0.66" OLED
|
u8x8_d_helper_display_setup_memory
|
void u8x8_d_helper_display_setup_memory(u8x8_t *u8x8, const u8x8_display_info_t *display_info)
{
/* 1) set display info struct */
u8x8->display_info = display_info;
u8x8->x_offset = u8x8->display_info->default_x_offset;
}
|
/*
this is a helper function for the U8X8_MSG_DISPLAY_SETUP_MEMORY function.
It can be called within the display callback function to carry out the usual standard tasks.
*/
|
this is a helper function for the U8X8_MSG_DISPLAY_SETUP_MEMORY function. It can be called within the display callback function to carry out the usual standard tasks.
|
u8x8_d_helper_display_init
|
void u8x8_d_helper_display_init(u8x8_t *u8x8)
{
/* 2) apply port directions to the GPIO lines and apply default values for the IO lines*/
u8x8_gpio_Init(u8x8);
u8x8_cad_Init(u8x8);
/* 3) do reset */
u8x8_gpio_SetReset(u8x8, 1);
u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, u8x8->display_info->reset_pulse_width_ms);
u8x8_gpio_SetReset(u8x8, 0);
u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, u8x8->display_info->reset_pulse_width_ms);
u8x8_gpio_SetReset(u8x8, 1);
u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, u8x8->display_info->post_reset_wait_ms);
}
|
/*
this is a helper function for the U8X8_MSG_DISPLAY_INIT function.
It can be called within the display callback function to carry out the usual standard tasks.
*/
|
this is a helper function for the U8X8_MSG_DISPLAY_INIT function. It can be called within the display callback function to carry out the usual standard tasks.
|
u8x8_SetupMemory
|
void u8x8_SetupMemory(u8x8_t *u8x8)
{
u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_SETUP_MEMORY, 0, NULL);
}
|
/* should be implemented as macro */
|
should be implemented as macro
|
u8log_scroll_up
|
static void u8log_scroll_up(u8log_t *u8log)
{
uint8_t *dest = u8log->screen_buffer;
uint8_t *src = dest+u8log->width;
uint16_t cnt = u8log->height;
cnt--;
cnt *= u8log->width;
do
{
*dest++ = *src++;
cnt--;
} while( cnt > 0 );
cnt = u8log->width;
do
{
*dest++ = ' ';
cnt--;
} while(cnt > 0);
if ( u8log->is_redraw_line_for_each_char )
u8log->is_redraw_all = 1;
else
u8log->is_redraw_all_required_for_next_nl = 1;
}
|
/* scroll the content of the complete buffer, set redraw_line to 255 */
|
scroll the content of the complete buffer, set redraw_line to 255
|
u8log_cursor_on_screen
|
static void u8log_cursor_on_screen(u8log_t *u8log)
{
//printf("u8log_cursor_on_screen, cursor_y=%d\n", u8log->cursor_y);
if ( u8log->cursor_x >= u8log->width )
{
u8log->cursor_x = 0;
u8log->cursor_y++;
}
while ( u8log->cursor_y >= u8log->height )
{
u8log_scroll_up(u8log);
u8log->cursor_y--;
}
}
|
/*
Place the cursor on the screen. This will also scroll, if required
*/
|
Place the cursor on the screen. This will also scroll, if required
|
u8log_write_to_screen
|
static void u8log_write_to_screen(u8log_t *u8log, uint8_t c)
{
u8log_cursor_on_screen(u8log);
u8log->screen_buffer[u8log->cursor_y * u8log->width + u8log->cursor_x] = c;
u8log->cursor_x++;
if ( u8log->is_redraw_line_for_each_char )
{
u8log->is_redraw_line = 1;
u8log->redraw_line = u8log->cursor_y;
}
}
|
/*
Write a printable, single char on the screen, do any kind of scrolling
*/
|
Write a printable, single char on the screen, do any kind of scrolling
|
u8log_SetLineHeightOffset
|
void u8log_SetLineHeightOffset(u8log_t *u8log, int8_t line_height_offset)
{
u8log->line_height_offset = line_height_offset;
}
|
/* offset can be negative or positive, it is 0 by default */
|
offset can be negative or positive, it is 0 by default
|
u8log_WriteDec8
|
void u8log_WriteDec8(u8log_t *u8log, uint8_t v, uint8_t d)
{
u8log_WriteString(u8log, u8x8_u8toa(v, d));
}
|
/* v = value, d = number of digits (1..3) */
|
v = value, d = number of digits (1..3)
|
u8log_WriteDec16
|
void u8log_WriteDec16(u8log_t *u8log, uint16_t v, uint8_t d)
{
u8log_WriteString(u8log, u8x8_u16toa(v, d));
}
|
/* v = value, d = number of digits (1..5) */
|
v = value, d = number of digits (1..5)
|
get_delay_in_milliseconds
|
uint16_t get_delay_in_milliseconds(uint8_t cnt, uint8_t *data)
{
uint8_t i;
uint16_t time = LINE_MIN_DELAY_MS;
for ( i = 0; i < cnt; i++ )
if ( data[i] != 0 )
time += LINE_EXTRA_8PIXEL_DELAY_MS;
return time;
}
|
/* actually only "none-zero" bytes are calculated which is, of course not so accurate, but should be good enough */
|
actually only "none-zero" bytes are calculated which is, of course not so accurate, but should be good enough
|
u8x8_u8toa
|
const char *u8x8_u8toa(uint8_t v, uint8_t d)
{
static char buf[4];
d = 3-d;
return u8x8_u8toap(buf, v) + d;
}
|
/* v = value, d = number of digits */
|
v = value, d = number of digits
|
u8x8_GetStringLineStart
|
const char *u8x8_GetStringLineStart(uint8_t line_idx, const char *str )
{
char e;
uint8_t line_cnt = 1;
if ( line_idx == 0 )
return str;
for(;;)
{
e = *str;
if ( e == '\0' )
break;
str++;
if ( e == '\n' )
{
if ( line_cnt == line_idx )
return str;
line_cnt++;
}
}
return NULL; /* line not found */
}
|
/*
Assumes strings, separated by '\n' in "str".
Returns the string at index "line_idx". First strng has line_idx = 0
Example:
Returns "xyz" for line_idx = 1 with str = "abc\nxyz"
Support both UTF8 and normal strings.
*/
|
Assumes strings, separated by ' ' in "str". Returns the string at index "line_idx". First strng has line_idx = 0 Example: Returns "xyz" for line_idx = 1 with str = "abc xyz" Support both UTF8 and normal strings.
|
u8x8_CopyStringLine
|
void u8x8_CopyStringLine(char *dest, uint8_t line_idx, const char *str)
{
if ( dest == NULL )
return;
str = u8x8_GetStringLineStart( line_idx, str );
if ( str != NULL )
{
for(;;)
{
if ( *str == '\n' || *str == '\0' )
break;
*dest = *str;
dest++;
str++;
}
}
*dest = '\0';
}
|
/* that the destination buffer is large enough */
|
that the destination buffer is large enough
|
u8x8_DrawUTF8Lines
|
uint8_t u8x8_DrawUTF8Lines(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t w, const char *s)
{
uint8_t i;
uint8_t cnt;
cnt = u8x8_GetStringLineCnt(s);
for( i = 0; i < cnt; i++ )
{
u8x8_DrawUTF8Line(u8x8, x, y, w, u8x8_GetStringLineStart(i, s));
y++;
}
return cnt;
}
|
/*
draw several lines at position x,y.
lines are stored in s and must be separated with '\n'.
lines can be centered with respect to "w"
if s == NULL nothing is drawn and 0 is returned
returns the number of lines in s
*/
|
draw several lines at position x,y. lines are stored in s and must be separated with ' '. lines can be centered with respect to "w" if s == NULL nothing is drawn and 0 is returned returns the number of lines in s
|
u8g2_is_intersection_decision_tree
|
static uint8_t u8g2_is_intersection_decision_tree(u8g2_uint_t a0, u8g2_uint_t a1, u8g2_uint_t v0, u8g2_uint_t v1)
{
if ( v0 <= a1 )
{
if ( v1 >= a0 )
{
return 1;
}
else
{
if ( v0 > v1 )
{
return 1;
}
else
{
return 0;
}
}
}
else
{
if ( v1 >= a0 )
{
if ( v0 > v1 )
{
return 1;
}
else
{
return 0;
}
}
else
{
return 0;
}
}
}
|
/*static uint8_t U8G2_ALWAYS_INLINE u8g2_is_intersection_decision_tree(u8g_uint_t a0, u8g_uint_t a1, u8g_uint_t v0, u8g_uint_t v1) */
|
static uint8_t U8G2_ALWAYS_INLINE u8g2_is_intersection_decision_tree(u8g_uint_t a0, u8g_uint_t a1, u8g_uint_t v0, u8g_uint_t v1)
|
u8g2_is_intersection_decision_tree
|
uint8_t u8g2_is_intersection_decision_tree(u8g2_uint_t a0, u8g2_uint_t a1, u8g2_uint_t v0, u8g2_uint_t v1)
{
if ( v0 < a1 ) // v0 <= a1
{
if ( v1 > a0 ) // v1 >= a0
{
return 1;
}
else
{
if ( v0 > v1 ) // v0 > v1
{
return 1;
}
else
{
return 0;
}
}
}
else
{
if ( v1 > a0 ) // v1 >= a0
{
if ( v0 > v1 ) // v0 > v1
{
return 1;
}
else
{
return 0;
}
}
else
{
return 0;
}
}
}
|
/*
version with asymetric boundaries.
a1 and v1 are excluded
v0 == v1 is not support end return 1
*/
|
version with asymetric boundaries. a1 and v1 are excluded v0 == v1 is not support end return 1
|
u8g2_IsIntersection
|
uint8_t u8g2_IsIntersection(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t x1, u8g2_uint_t y1)
{
if ( u8g2_is_intersection_decision_tree(u8g2->user_y0, u8g2->user_y1, y0, y1) == 0 )
return 0;
return u8g2_is_intersection_decision_tree(u8g2->user_x0, u8g2->user_x1, x0, x1);
}
|
/* upper limits are not included (asymetric boundaries) */
|
upper limits are not included (asymetric boundaries)
|
delay_system_ticks
|
void delay_system_ticks(uint32_t sys_ticks)
{
uint32_t load4;
load4 = SysTick->LOAD;
load4 &= 0x0ffffffUL;
load4 >>= 2;
while ( sys_ticks > load4 )
{
sys_ticks -= load4;
_delay_system_ticks_sub(load4);
}
_delay_system_ticks_sub(sys_ticks);
}
|
/*
Delay by the provided number of system ticks.
Any values between 0 and 0x0ffffffff are allowed.
*/
|
Delay by the provided number of system ticks. Any values between 0 and 0x0ffffffff are allowed.
|
delay_micro_seconds
|
void delay_micro_seconds(uint32_t us)
{
uint32_t sys_ticks;
sys_ticks = SystemCoreClock;
sys_ticks /=1000000UL;
sys_ticks *= us;
delay_system_ticks(sys_ticks);
}
|
/*
Delay by the provided number of micro seconds.
Limitation: "us" * System-Freq in MHz must not overflow in 32 bit.
Values between 0 and 1.000.000 (1 second) are ok.
Important: Call SystemCoreClockUpdate() before calling this function.
*/
|
Delay by the provided number of micro seconds. Limitation: "us" * System-Freq in MHz must not overflow in 32 bit. Values between 0 and 1.000.000 (1 second) are ok.
Important: Call SystemCoreClockUpdate() before calling this function.
|
startUp
|
void startUp(void)
{
RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface (PWR) */
PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
SysTick->LOAD = (SystemCoreClock/1000)*50 - 1; /* 50ms task */
SysTick->VAL = 0;
SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */
}
|
/*
Enable several power regions: PWR, GPIOA
This must be executed after each reset.
*/
|
Enable several power regions: PWR, GPIOA
This must be executed after each reset.
|
initDisplay
|
void initDisplay(void)
{
u8x8_Setup(&u8x8, u8x8_d_ssd1306_128x64_noname, u8x8_cad_ssd13xx_i2c, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0);
u8x8_InitDisplay(&u8x8);
u8x8_ClearDisplay(&u8x8);
u8x8_SetPowerSave(&u8x8, 0);
u8x8_SetFont(&u8x8, u8x8_font_amstrad_cpc_extended_r);
u8x8_x = 0;
u8x8_y = 0;
}
|
/* u8x8 display procedures */
|
u8x8 display procedures
|
u8x8_SetupDefaults
|
void u8x8_SetupDefaults(u8x8_t *u8x8)
{
u8x8->display_info = NULL;
u8x8->display_cb = u8x8_dummy_cb;
u8x8->cad_cb = u8x8_dummy_cb;
u8x8->byte_cb = u8x8_dummy_cb;
u8x8->gpio_and_delay_cb = u8x8_dummy_cb;
u8x8->is_font_inverse_mode = 0;
u8x8->device_address = 0;
u8x8->utf8_state = 0; /* also reset by u8x8_utf8_init */
u8x8->i2c_address = 255;
u8x8->debounce_default_pin_state = 255; /* assume all low active buttons */
#ifdef U8X8_USE_PINS
{
uint8_t i;
for( i = 0; i < U8X8_PIN_CNT; i++ )
u8x8->pins[i] = U8X8_PIN_NONE;
}
#endif
}
|
/*
Description:
Setup u8x8
Args:
u8x8 An empty u8x8 structure
*/
|
Description: Setup u8x8 Args: u8x8 An empty u8x8 structure
|
u8x8_write_byte_to_16gr_device
|
uint8_t u8x8_write_byte_to_16gr_device(u8x8_t *u8x8, uint8_t b)
{
static uint8_t buf[4];
static uint8_t map[4] = { 0, 0x00f, 0x0f0, 0x0ff };
buf [3] = map[b & 3];
b>>=2;
buf [2] = map[b & 3];
b>>=2;
buf [1] = map[b & 3];
b>>=2;
buf [0] = map[b & 3];
return u8x8_cad_SendData(u8x8, 4, buf); /* note: SendData can not handle more than 255 bytes, send one line of data */
}
|
/* 4 Jan 2017: I think this procedure not required any more. Delete? */
|
4 Jan 2017: I think this procedure not required any more. Delete?
|
rtc_bcd_to_ymd_hms
|
void rtc_bcd_to_ymd_hms(rtc_t *rtc)
{
rtc->sec = rtc_bcd_to_uint8(rtc, 0);
rtc->min = rtc_bcd_to_uint8(rtc, 2);
rtc->hour = rtc_bcd_to_uint8(rtc, 4);
rtc->day = rtc_bcd_to_uint8(rtc, 6);
rtc->month = rtc_bcd_to_uint8(rtc, 8);
rtc->year = rtc_bcd_to_uint8(rtc, 10);
}
|
/* convert the content of the bcd array to the ymd&hms vars */
|
convert the content of the bcd array to the ymd&hms vars
|
startSysTick
|
void startSysTick(void)
{
SysTick->LOAD = (SystemCoreClock/1000)*50 - 1; /* 50ms task */
SysTick->VAL = 0;
SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */
}
|
/*
Setup systick interrupt.
A call to SystemCoreClockUpdate() is required before calling this function.
This must be executed after each reset.
*/
|
Setup systick interrupt. A call to SystemCoreClockUpdate() is required before calling this function.
This must be executed after each reset.
|
initDisplay
|
void initDisplay(uint8_t is_por)
{
/* setup display */
u8g2_Setup_ssd1306_i2c_128x64_noname_f(&u8g2, U8G2_R0, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0);
gui_Init(&u8g2, is_por);
u8g2_SetFlipMode(&u8g2, 1);
}
|
/*
Setup u8g2
This must be executed after every reset
*/
|
Setup u8g2
This must be executed after every reset
|
set_contrast
|
void set_contrast(void)
{
uint8_t v = gui_data.contrast;
if ( v > 0 )
{
v = v * 36;
u8g2_SetContrast(gui_menu.u8g2, v);
}
}
|
/* value 1..7, 0 is default (do not set) */
|
value 1..7, 0 is default (do not set)
|
addCmdToGPIOQueue
|
void addCmdToGPIOQueue(uint8_t n)
{
uint8_t pos;
pos = gpio_queue_end ;
pos++;
if ( pos >= GPIO_QUEUE_MAX )
pos = 0;
if ( pos == gpio_queue_start )
return; // queue overflow
gpio_queue_mem[gpio_queue_end] = n;
gpio_queue_end = pos;
}
|
/* this is called from the I2C interrupt procedures */
|
this is called from the I2C interrupt procedures
|
getCmdFromGPIOQueue
|
uint8_t getCmdFromGPIOQueue(void)
{
uint8_t r = gpio_queue_mem[gpio_queue_start];
if ( isGPIOQueueEmpty() )
return 255;
return r;
}
|
/* get the next command in the queue, return 255 if the queue is empty */
|
get the next command in the queue, return 255 if the queue is empty
|
processQueue
|
void processQueue(void)
{
uint8_t cmd;
cmd = getCmdFromGPIOQueue();
if ( cmd < 255 )
{
/* try to start the state machine */
if ( gpioStartStateMachine(cmd) != 0 )
{
/* success, remove the cmd from the queue */
removeCmdFromGPIOQueue();
}
}
}
|
/* Queue & State Machine Connector */
|
Queue & State Machine Connector
|
setGPIO
|
void setGPIO( uint8_t n )
{
clearGPIO();
switch(n)
{
case 0: GPIOA->BSRR = GPIO_BSRR_BS_14; break;
case 1: GPIOA->BSRR = GPIO_BSRR_BS_13; break;
case 2: GPIOA->BSRR = GPIO_BSRR_BS_7; break;
case 3: GPIOA->BSRR = GPIO_BSRR_BS_6; break;
case 4: GPIOA->BSRR = GPIO_BSRR_BS_5; break;
case 5: GPIOA->BSRR = GPIO_BSRR_BS_4; break;
case 6: GPIOA->BSRR = GPIO_BSRR_BS_1; break;
case 7: GPIOA->BSRR = GPIO_BSRR_BS_0; break;
}
}
|
/*
0: PA14
1: PA13
2: PA7
3: PA6
4: PA5
5: PA4
6: PA1
7: PA0
*/
|
0: PA14 1: PA13 2: PA7 3: PA6 4: PA5 5: PA4 6: PA1 7: PA0
|
initDisplay
|
void initDisplay(void)
{
/* setup display */
u8g2_Setup_ssd1306_i2c_128x64_noname_f(&u8g2, U8G2_R2, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0);
u8g2_InitDisplay(&u8g2);
u8g2_SetPowerSave(&u8g2, 0);
u8g2_SetFont(&u8g2, u8g2_font_6x12_tf);
u8g2_ClearBuffer(&u8g2);
u8g2_DrawStr(&u8g2, 0,12, "STM32L031");
u8g2_DrawStr(&u8g2, 0,24, u8x8_u8toa(SystemCoreClock/1000000, 2));
u8g2_DrawStr(&u8g2, 20,24, "MHz");
u8g2_SendBuffer(&u8g2);
u8g2_x = 0;
u8g2_y = 0;
}
|
/* u8x8 display procedures */
|
u8x8 display procedures
|
adcStartSubTask
|
int adcStartSubTask(uint8_t msg)
{
if ( adcIsSubDone() == 0 )
return 0;
adc_sub_task = msg;
adc_sub_state = ADC_SUB_STATE_INIT;
return 1;
}
|
/*
int adcStartSubTask(uint8_t msg)
Args:
msg: One of ADC_SUB_TASK_STOP_ADC, ADC_SUB_TASK_ENABLE_ADC, ADC_SUB_TASK_DISABLE_ADC
Returns:
0 if there is any other subtask active
*/
|
int adcStartSubTask(uint8_t msg)
Args: msg: One of ADC_SUB_TASK_STOP_ADC, ADC_SUB_TASK_ENABLE_ADC, ADC_SUB_TASK_DISABLE_ADC
Returns: 0 if there is any other subtask active
|
stopADC
|
void stopADC(void)
{
//ADC1->CR |= ADC_CR_ADSTP;
//while(ADC1->CR & ADC_CR_ADSTP)
// ;
while( adcStartSubTask(ADC_SUB_TASK_STOP_ADC) == 0 )
adcExecSub();
while( adcIsSubDone() == 0 )
adcExecSub();
}
|
/* STOP ANY ADC CONVERSION */
|
STOP ANY ADC CONVERSION
|
disableADC
|
void disableADC(void)
{
/* Check for the ADEN flag. */
/* Setting ADDIS will fail if the ADC is alread disabled: The while loop will not terminate */
#ifdef xxxx
if ((ADC1->CR & ADC_CR_ADEN) != 0)
{
/* is this correct? i think we must use the disable flag here */
ADC1->CR |= ADC_CR_ADDIS;
while(ADC1->CR & ADC_CR_ADDIS)
;
}
#endif
while( adcStartSubTask(ADC_SUB_TASK_DISABLE_ADC) == 0 )
adcExecSub();
while( adcIsSubDone() == 0 )
adcExecSub();
}
|
/* required to change the configuration of the ADC */
|
required to change the configuration of the ADC
|
enableADC
|
void enableADC(void)
{
//ADC1->ISR |= ADC_ISR_ADRDY; /* clear ready flag */
//ADC1->CR |= ADC_CR_ADEN; /* enable ADC */
//while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* wait for ADC */
//{
//}
while( adcStartSubTask(ADC_SUB_TASK_ENABLE_ADC) == 0 )
adcExecSub();
while( adcIsSubDone() == 0 )
adcExecSub();
}
|
/* after the ADC is enabled, it must not be reconfigured */
|
after the ADC is enabled, it must not be reconfigured
|
scanADC
|
void scanADC(uint8_t ch, uint16_t cnt, uint16_t *buf)
{
while( adcStartMultiConversion(ch, cnt, buf) == 0)
adcExecMultiConversion();
while( adc_multi_conversion_state != 0 )
adcExecMultiConversion();
}
|
/* 12 bit resolution */
|
12 bit resolution
|
startUp
|
void startUp(void)
{
RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
}
|
/*
Enable several power regions: PWR, GPIOA
Enable write access to RTC
This must be executed after each reset.
*/
|
Enable several power regions: PWR, GPIOA Enable write access to RTC
This must be executed after each reset.
|
initDisplay
|
void initDisplay(void)
{
/* setup display */
u8g2_Setup_ssd1306_i2c_128x64_noname_f(&u8g2, U8G2_R0, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0);
u8g2_InitDisplay(&u8g2);
u8g2_SetPowerSave(&u8g2, 0);
u8g2_SetFont(&u8g2, u8g2_font_6x12_tf);
u8g2_ClearBuffer(&u8g2);
u8g2_DrawStr(&u8g2, 0,12, "STM32L031");
u8g2_DrawStr(&u8g2, 0,24, u8x8_u8toa(SystemCoreClock/1000000, 2));
u8g2_DrawStr(&u8g2, 20,24, "MHz");
u8g2_SendBuffer(&u8g2);
}
|
/*
Setup u8g2
This must be executed only after POR reset.
*/
|
Setup u8g2
This must be executed only after POR reset.
|
initRTC
|
void initRTC(void)
{
/* real time clock enable */
//enableRCCRTCWrite();
RTC->WPR = 0x0ca; /* disable RTC write protection */
RTC->WPR = 0x053;
/* externel 32K clock source */
RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */
/* externel 32K oscillator */
//RCC->CSR &= ~RCC_CSR_LSEBYP; /* no bypass oscillator */
//RCC->CSR &= ~RCC_CSR_LSEDRV_Msk /* lowest drive */
//RCC->CSR |= RCC_CSR_LSEDRV_0; /* medium low drive */
RCC->CSR |= RCC_CSR_LSEON; /* enable low speed external clock */
delay_micro_seconds(100000*5); /* LSE requires between 100ms to 200ms */
/*
if ( RCC->CSR & RCC_CSR_LSERDY )
display_Write("32K Clock Ready\n");
else
display_Write("32K Clock Error\n");
*/
RCC->CSR &= ~RCC_CSR_RTCSEL_Msk; /* no clock selection for RTC */
RCC->CSR |= RCC_CSR_RTCSEL_LSE; /* select LSE */
RCC->CSR |= RCC_CSR_RTCEN; /* enable RTC */
/* RTC Start */
RTC->ISR = RTC_ISR_INIT; /* request RTC stop */
while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* wait for stop */
;
RTC->PRER = 0x07f00ff;
RTC->TR = 0;
RTC->ISR =~ RTC_ISR_INIT; /* start RTC */
RTC->WPR = 0; /* enable RTC write protection */
RTC->WPR = 0;
//disableRCCRTCWrite();
}
|
/*
configure and start RTC
This must be executed only after POR reset.
*/
|
configure and start RTC
This must be executed only after POR reset.
|
initDisplay
|
void initDisplay(void)
{
/* setup display */
u8g2_Setup_ssd1306_i2c_128x64_noname_f(&u8g2, U8G2_R0, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0);
u8g2_InitDisplay(&u8g2);
u8g2_SetPowerSave(&u8g2, 0);
u8g2_SetFont(&u8g2, u8g2_font_6x12_tf);
u8g2_ClearBuffer(&u8g2);
u8g2_DrawStr(&u8g2, 0,12, "STM32L031");
u8g2_DrawStr(&u8g2, 0,24, u8x8_u8toa(SystemCoreClock/1000000, 2));
u8g2_DrawStr(&u8g2, 20,24, "MHz");
u8g2_SendBuffer(&u8g2);
u8g2_x = 0;
u8g2_y = 0;
}
|
/* u8x8 display procedures */
|
u8x8 display procedures
|
stopADC
|
void stopADC(void)
{
ADC1->CR |= ADC_CR_ADSTP;
while(ADC1->CR & ADC_CR_ADSTP)
;
}
|
/* STOP ANY ADC CONVERSION */
|
STOP ANY ADC CONVERSION
|
disableADC
|
void disableADC(void)
{
/* Check for the ADEN flag. */
/* Setting ADDIS will fail if the ADC is alread disabled: The while loop will not terminate */
if ((ADC1->CR & ADC_CR_ADEN) != 0)
{
/* is this correct? i think we must use the disable flag here */
ADC1->CR |= ADC_CR_ADDIS;
while(ADC1->CR & ADC_CR_ADDIS)
;
}
}
|
/* required to change the configuration of the ADC */
|
required to change the configuration of the ADC
|
enableADC
|
void enableADC(void)
{
ADC1->ISR |= ADC_ISR_ADRDY; /* clear ready flag */
ADC1->CR |= ADC_CR_ADEN; /* enable ADC */
while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* wait for ADC */
{
}
}
|
/* after the ADC is enabled, it must not be reconfigured */
|
after the ADC is enabled, it must not be reconfigured
|
getBEMFLevel
|
int getBEMFLevel(uint16_t cnt, uint8_t *buf, uint16_t start)
{
return -1;
}
|
/*
special values:
-1 Can not find level
255 no rotation
0..254 BMEF level, speed is k*(255-getBEMFLevel())
*/
|
special values: -1 Can not find level 255 no rotation 0..254 BMEF level, speed is k*(255-getBEMFLevel())
|
getUpTime
|
unsigned long getUpTime(void)
{
unsigned long sys_tick_cycle = SysTick->LOAD+1;
unsigned long millis_per_sys_tick_irq;
/*
the simple approach
millis_per_sys_tick_irq = (sys_tick_cycle*1000UL)/SystemCoreClock;
may overflow for large values of SysTick->LOAD. Instead this is better because SystemCoreClock is always
very large:
millis_per_sys_tick_irq = sys_tick_cycle/(SystemCoreClock/1000);
*/
millis_per_sys_tick_irq = sys_tick_cycle/(SystemCoreClock/1000);
return millis_per_sys_tick_irq * SysTickCount;
}
|
/* return current system time in milliseconds */
|
return current system time in milliseconds
|
initDMA
|
void initDMA()
{
RCC->AHBENR |= RCC_AHBENR_DMAEN; /* enable DMA clock */
__NOP(); __NOP(); /* extra delay for clock stabilization required? */
/* defaults:
- 8 Bit access
- read from peripheral
- none-circular mode
- no increment mode
*/
DMA1_Channel1->CCR |= DMA_CCR_MSIZE_0; /* 16 bit access */
DMA1_Channel1->CCR |= DMA_CCR_PSIZE_0; /* 16 bit access */
DMA1_Channel1->CCR |= DMA_CCR_CIRC; /* circular mode */
DMA1_Channel1->CNDTR = 1; /* one data, then repeat (circular mode) */
DMA1_Channel1->CPAR = (uint32_t)&(ADC1->DR); /* source value */
DMA1_Channel1->CMAR = (uint32_t)&(TIM2->CCR2); /* destination register */
DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; /* 0000: select ADC for DMA CH 1 (this is reset default) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* enable */
ADC1->CFGR1 |= ADC_CFGR1_DMACFG; /* never stop DMA requests */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* enable DMA requests for ADC */
}
|
/*
copy from ADC1->DR to TIM2->CCR2
ADC DMA requests can be used with DMA Channel 1
*/
|
copy from ADC1->DR to TIM2->CCR2 ADC DMA requests can be used with DMA Channel 1
|
startUp
|
void startUp(void)
{
RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
//PWR_CSR_Backup = PWR->CSR; /* create a backup of the original PWR_CSR register for later analysis */
PWR->CR |= PWR_CR_CSBF; /* clear the standby flag in the PWR_CSR register, but luckily we have a copy */
PWR->CR |= PWR_CR_CWUF; /* also clear the WUF flag in PWR_CSR */
/* PA0, TAMP2, button input */
GPIOA->MODER &= ~GPIO_MODER_MODE0; /* clear mode for PA0 */
GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD0; /* no pullup/pulldown for PA0 */
GPIOA->PUPDR |= GPIO_PUPDR_PUPD0_0; /* pullup for PA0 */
/* PA2, TAMP3, button input */
GPIOA->MODER &= ~GPIO_MODER_MODE2; /* clear mode for PA2 */
GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD2; /* no pullup/pulldown for PA2 */
GPIOA->PUPDR |= GPIO_PUPDR_PUPD2_0; /* pullup for PA2 */
}
|
/*
Enable several power regions: PWR, GPIOA
Enable write access to RTC
This must be executed after each reset.
*/
|
Enable several power regions: PWR, GPIOA Enable write access to RTC
This must be executed after each reset.
|
mb_set_data_size
|
int mb_set_data_size(mb_struct *mb, unsigned long cnt)
{
if ( mb->data == NULL )
{
mb->data = (unsigned char *)malloc(cnt);
if ( mb->data == NULL )
return err("fmem: mem data alloc error"), 0;
}
else
{
void *ptr;
ptr = realloc(mb->data , cnt);
if ( ptr == NULL )
return err("fmem: mem data realloc error"), 0;
mb->data = (unsigned char *)ptr;
}
mb->cnt = cnt;
return 1;
}
|
/* set size of the memory block, existing data will be preserved, returns 0 for error */
|
set size of the memory block, existing data will be preserved, returns 0 for error
|
fmem_expand
|
int fmem_expand(void)
{
void *ptr;
ptr = realloc(fmem_mb_list, (fmem_mb_list_max+FMEM_EXPAND)*sizeof(mb_struct *));
if ( ptr == NULL )
return err("fmem: mem block list expand error"), 0;
fmem_mb_list = (mb_struct **)ptr;
fmem_mb_list_max+= FMEM_EXPAND;
return 1;
}
|
/* (internal function, only called by fmem_add_data) */
|
(internal function, only called by fmem_add_data)
|
fmem_add_data
|
int fmem_add_data(unsigned long adr, unsigned long cnt, unsigned char *data)
{
mb_struct *mb = mb_open();
if ( mb != NULL )
{
if ( mb_set_data_size(mb, cnt) != 0 )
{
memcpy(mb->data, data, cnt);
while( fmem_mb_list_cnt >= fmem_mb_list_max )
if ( fmem_expand() == 0 )
{
mb_close(mb);
return 0;
}
fmem_mb_list[fmem_mb_list_cnt] = mb;
fmem_mb_list_cnt++;
return 1;
}
}
return 0;
}
|
/* (internal function, only called by fmem_store_data) */
|
(internal function, only called by fmem_store_data)
|
fmem_store_data
|
int fmem_store_data(unsigned long adr, unsigned long cnt, unsigned char *data)
{
if ( fmem_mb_list_cnt > 0 )
{
mb_struct *mb = fmem_mb_list[fmem_mb_list_cnt-1];
if ( mb->adr + mb->cnt == adr )
{
unsigned long old_cnt = mb->cnt;
if ( mb_set_data_size(mb, mb->cnt + cnt) == 0 )
return 0;
memcpy(mb->data + old_cnt, data, cnt);
return 1;
}
}
return fmem_add_data(adr, cnt, data);
}
|
/* idea is to reduce the number of independent data blocks */
|
idea is to reduce the number of independent data blocks
|
ihex_get_curr_adr
|
unsigned long ihex_get_curr_adr(void)
{
unsigned long adr;
adr = 0UL;
adr += ihex_line_extlinadr<<16;
adr += ihex_line_extsegadr<<16;
adr += ihex_line_adr;
return adr;
}
|
/* calculate the current address */
|
calculate the current address
|
ihex_read_line
|
int ihex_read_line(void)
{
if ( ihex_fp == NULL )
return err("ihex line %lu: internal error (file ptr)", ihex_curr_line), 0;
if ( fgets(ihex_line, IHEX_LINE_LEN, ihex_fp) == NULL )
return 0;
ihex_line[IHEX_LINE_LEN-1] = '\0';
ihex_pos = 0;
ihex_curr_line++;
return 1;
}
|
/* read one line from the stream (global variable), return 0 for error or EOF */
|
read one line from the stream (global variable), return 0 for error or EOF
|
ihex_getc
|
unsigned int ihex_getc(void)
{
unsigned int c;
c = ihex_line[ihex_pos];
if ( c != '\0' )
ihex_pos++;
return c;
}
|
/* get a char from the internal line buffer and goto to next char */
|
get a char from the internal line buffer and goto to next char
|
ihex_read_file
|
int ihex_read_file(const char *filename)
{
ihex_fp = fopen(filename, "rb");
if ( ihex_fp == NULL )
return err("ihex: open error with file '%s'", filename), 0;
msg("intel hex file %s", filename);
if ( ihex_read_fp() == 0 )
{
fclose(ihex_fp);
return 0;
}
fclose(ihex_fp);
return 1;
}
|
/*
read intel hex file into the flash memory manager.
after this, use the following functions:
int fmem_copy(unsigned long adr, unsigned long size, unsigned char *buf)
unsigned char fmem_get_byte(unsigned long adr)
void fmem_set_byte(unsigned long adr, unsigned char val)
*/
|
read intel hex file into the flash memory manager. after this, use the following functions:
int fmem_copy(unsigned long adr, unsigned long size, unsigned char *buf) unsigned char fmem_get_byte(unsigned long adr) void fmem_set_byte(unsigned long adr, unsigned char val)
|
uart_send_startup
|
int uart_send_startup(void)
{
uart_reset_in_buf();
uart_send_str(UART_STR_SYNCHRONIZED "\r\n");
uart_read_more();
if ( strncmp((const char *)uart_in_buf, UART_STR_SYNCHRONIZED, strlen(UART_STR_SYNCHRONIZED)) == 0 )
{
/* yes, synchronized, send clock speed */
uart_reset_in_buf();
uart_send_str(UART_STR_12000 "\r\n");
uart_read_more();
if ( strncmp((const char *)uart_in_buf, UART_STR_12000, strlen(UART_STR_12000)) == 0 )
{
/* yes, synchronized */
return 1;
}
}
return 0;
}
|
/* return 0 if not in sync */
|
return 0 if not in sync
|
uart_read_from_adr
|
long uart_read_from_adr(unsigned long adr, unsigned long cnt)
{
char s[32];
if ( cnt > UART_IN_BUF_LEN-64 )
return err("wrong args for read memory"), -1;
sprintf(s, "R %lu %lu\r\n", adr, cnt);
uart_reset_in_buf();
uart_send_str(s);
uart_read_more();
if ( uart_in_pos < 3+cnt )
return err("read memory failed (too less data)"), -1;
/* check for success code */
if ( uart_in_buf[uart_in_pos-cnt-3] != '0' )
return err("read memory failed (illegal return code)"), -1;
//printf("read operation, uart_in_pos = %lu, result stats at %ld\n", uart_in_pos, uart_in_pos-cnt);
return uart_in_pos-cnt;
}
|
/*
Read from controller memory. Result will be placed in uart_in_buf
Return value contains the start index in uart_in_buf or is -1 if the read has failed
*/
|
Read from controller memory. Result will be placed in uart_in_buf Return value contains the start index in uart_in_buf or is -1 if the read has failed
|
lpc_page_quick_compare
|
int lpc_page_quick_compare(unsigned long adr)
{
char s[48];
int result_code;
msg("compare %lu bytes at 0x%08x", lpc_part->ram_buf_size, adr);
sprintf(s, "M %lu %lu %lu\r\n", lpc_part->ram_buf_adr, adr, lpc_part->ram_buf_size);
uart_reset_in_buf();
uart_send_str(s);
uart_read_more();
//uart_show_in_buf();
result_code = uart_get_result_code_after_first_0x0a();
if ( result_code > 0 )
return err("compare failure (%d)", result_code), 0;
return 1;
}
|
/*
compare the content at adr with the content at the ram buffer
This will always compare the complete ram buffer. This is ok, because
during download of the data, RAM buffer is filled with 0x0ff.
Also flash procedure will always flash the complete buffer.
Problem: this seems to succeed always...???
*/
|
compare the content at adr with the content at the ram buffer This will always compare the complete ram buffer. This is ok, because during download of the data, RAM buffer is filled with 0x0ff. Also flash procedure will always flash the complete buffer.
Problem: this seems to succeed always...???
|
lpc_exec_reset
|
int lpc_exec_reset(void)
{
int result_code;
unsigned long reset_vector;
char s[32];
if ( lpc_part == NULL )
return 0;
reset_vector = arm_get_reset_vector();
msg("execute reset handler at 0x%08x", reset_vector);
sprintf(s, "G %lu T\r\n", reset_vector);
uart_reset_in_buf();
uart_send_str(s);
uart_read_more();
//uart_show_in_buf();
result_code = uart_get_result_code_from_buf_end();
if ( result_code > 0 )
return err("exec reset handler failed (%d)", result_code), 0;
return 1;
}
|
/*
execute reset handler
*/
|
execute reset handler
|
get_str_arg
|
int get_str_arg(char ***argv, int c, char **result)
{
if ( (**argv)[0] == '-' )
{
if ( (**argv)[1] == c )
{
if ( (**argv)[2] == '\0' )
{
(*argv)++;
*result = **argv;
}
else
{
*result = (**argv)+2;
}
(*argv)++;
return 1;
}
}
return 0;
}
|
/* commandline parser and main procedure */
|
commandline parser and main procedure
|
NMI_Handler
|
void __attribute__ ((interrupt)) NMI_Handler(void)
{
}
|
/* "NMI_Handler" is used in the ld script to calculate the checksum */
|
"NMI_Handler" is used in the ld script to calculate the checksum
|
HardFault_Handler
|
void __attribute__ ((interrupt)) HardFault_Handler(void)
{
}
|
/* "HardFault_Handler" is used in the ld script to calculate the checksum */
|
"HardFault_Handler" is used in the ld script to calculate the checksum
|
main
|
int __attribute__ ((noinline)) main(void)
{
/* call to the lpc lib setup procedure. This will set the IRC as clk src and main clk to 24 MHz */
Chip_SystemInit();
/* if the clock or PLL has been changed, also update the global variable SystemCoreClock */
SystemCoreClockUpdate();
/* set systick and start systick interrupt */
SysTick_Config(SystemCoreClock/1000UL*(unsigned long)SYS_TICK_PERIOD_IN_MS);
/* enable clock for several subsystems */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON | SYSCTL_CLOCK_GPIO | SYSCTL_CLOCK_SWM);
/* turn on GPIO */
Chip_GPIO_Init(LPC_GPIO_PORT); /* Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO); */
//Chip_IOCON_PinMuxSet(LPC_IOCON, 0, 15, IOCON_FUNC1); /* RxD */
Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 0, 15);
for(;;)
{
Chip_GPIO_SetPinOutHigh(LPC_GPIO_PORT, 0, 15);
delay_micro_seconds(1000000);
Chip_GPIO_SetPinOutLow(LPC_GPIO_PORT, 0, 15);
delay_micro_seconds(1000000);
}
}
|
/*
setup the hardware and start interrupts.
called by "Reset_Handler"
*/
|
setup the hardware and start interrupts. called by "Reset_Handler"
|
I2C_GetResetID
|
static CHIP_SYSCTL_PERIPH_RESET_T I2C_GetResetID(LPC_I2C_T *pI2C)
{
uint32_t base = (uint32_t) pI2C;
switch (base) {
case LPC_I2C1_BASE:
return RESET_I2C1;
case LPC_I2C2_BASE:
return RESET_I2C2;
case LPC_I2C3_BASE:
return RESET_I2C3;
default:
return RESET_I2C0;
}
}
|
/* Get the RESET ID corresponding to the given I2C base */
|
Get the RESET ID corresponding to the given I2C base
|
I2C_GetClockID
|
static CHIP_SYSCTL_CLOCK_T I2C_GetClockID(LPC_I2C_T *pI2C)
{
uint32_t base = (uint32_t) pI2C;
switch (base) {
case LPC_I2C1_BASE:
return SYSCTL_CLOCK_I2C1;
case LPC_I2C2_BASE:
return SYSCTL_CLOCK_I2C2;
case LPC_I2C3_BASE:
return SYSCTL_CLOCK_I2C3;
default:
return SYSCTL_CLOCK_I2C0;
}
}
|
/* Get the CLOCK ID corresponding to the given I2C base */
|
Get the CLOCK ID corresponding to the given I2C base
|
Chip_I2C_Init
|
void Chip_I2C_Init(LPC_I2C_T *pI2C)
{
/* Enable I2C clock */
Chip_Clock_EnablePeriphClock(I2C_GetClockID(pI2C));
/* Peripheral reset control to I2C */
Chip_SYSCTL_PeriphReset(I2C_GetResetID(pI2C));
}
|
/* Initializes the LPC_I2C peripheral */
|
Initializes the LPC_I2C peripheral
|
Chip_I2C_DeInit
|
void Chip_I2C_DeInit(LPC_I2C_T *pI2C)
{
/* Disable I2C clock */
Chip_Clock_DisablePeriphClock(I2C_GetClockID(pI2C));
}
|
/* Shuts down the I2C controller block */
|
Shuts down the I2C controller block
|
RingBuffer_Init
|
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
{
RingBuff->data = buffer;
RingBuff->count = count;
RingBuff->itemSz = itemSize;
RingBuff->head = RingBuff->tail = 0;
return 1;
}
|
/* Initialize ring buffer */
|
Initialize ring buffer
|
RingBuffer_Insert
|
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, RingBuff->itemSz);
RingBuff->head++;
return 1;
}
|
/* Insert a single item into Ring Buffer */
|
Insert a single item into Ring Buffer
|
RingBuffer_Pop
|
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot pop when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, RingBuff->itemSz);
RingBuff->tail++;
return 1;
}
|
/* Pop single item from Ring Buffer */
|
Pop single item from Ring Buffer
|
Chip_PININT_SetPatternMatchSrc
|
void Chip_PININT_SetPatternMatchSrc(LPC_PIN_INT_T *pPININT, uint8_t chan, Chip_PININT_BITSLICE_T slice)
{
uint32_t pmsrc_reg;
/* Source source for pattern matching */
pmsrc_reg = pPININT->PMSRC & ~((PININT_SRC_BITSOURCE_MASK << (PININT_SRC_BITSOURCE_START + (slice * 3)))
| PININT_PMSRC_RESERVED);
pPININT->PMSRC = pmsrc_reg | (chan << (PININT_SRC_BITSOURCE_START + (slice * 3)));
}
|
/* Set source for pattern match engine */
|
Set source for pattern match engine
|
Chip_PININT_SetPatternMatchConfig
|
void Chip_PININT_SetPatternMatchConfig(LPC_PIN_INT_T *pPININT, Chip_PININT_BITSLICE_T slice,
Chip_PININT_BITSLICE_CFG_T slice_cfg, bool end_point)
{
uint32_t pmcfg_reg;
/* Configure bit slice configuration */
pmcfg_reg = pPININT->PMCFG & ~((PININT_SRC_BITCFG_MASK << (PININT_SRC_BITCFG_START + (slice * 3)))
| PININT_PMCFG_RESERVED);
pPININT->PMCFG = pmcfg_reg | (slice_cfg << (PININT_SRC_BITCFG_START + (slice * 3)));
/* If end point is true, enable the bits */
if (end_point == true)
{
/* By default slice 7 is final component */
if (slice != PININTBITSLICE7)
{
pPININT->PMCFG = (0x1 << slice) | (pPININT->PMCFG & ~PININT_PMCFG_RESERVED);
}
}
}
|
/* Configure Pattern match engine */
|
Configure Pattern match engine
|
getUARTClockID
|
static CHIP_SYSCTL_CLOCK_T getUARTClockID(LPC_USART_T *pUART)
{
if (pUART == LPC_USART0) {
return SYSCTL_CLOCK_UART0;
}
else if (pUART == LPC_USART1) {
return SYSCTL_CLOCK_UART1;
}
return SYSCTL_CLOCK_UART2;
}
|
/* Return UART clock ID from the UART register address */
|
Return UART clock ID from the UART register address
|
Chip_UART_Init
|
void Chip_UART_Init(LPC_USART_T *pUART)
{
/* Enable USART clock */
Chip_Clock_EnablePeriphClock(getUARTClockID(pUART));
/* UART reset */
if (pUART == LPC_USART0) {
/* Peripheral reset control to USART0 */
Chip_SYSCTL_PeriphReset(RESET_USART0);
}
else if (pUART == LPC_USART1) {
/* Peripheral reset control to USART1 */
Chip_SYSCTL_PeriphReset(RESET_USART1);
}
else {
/* Peripheral reset control to USART2 */
Chip_SYSCTL_PeriphReset(RESET_USART2);
}
}
|
/* Initialize the UART peripheral */
|
Initialize the UART peripheral
|
Chip_UART_DeInit
|
void Chip_UART_DeInit(LPC_USART_T *pUART)
{
/* Disable USART clock */
Chip_Clock_DisablePeriphClock(getUARTClockID(pUART));
}
|
/* Initialize the UART peripheral */
|
Initialize the UART peripheral
|
Chip_UART_Send
|
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
{
int sent = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((sent < numBytes) &&
((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0)) {
Chip_UART_SendByte(pUART, *p8);
p8++;
sent++;
}
return sent;
}
|
/* Transmit a byte array through the UART peripheral (non-blocking) */
|
Transmit a byte array through the UART peripheral (non-blocking)
|
Chip_UART_SendBlocking
|
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes)
{
int pass, sent = 0;
uint8_t *p8 = (uint8_t *) data;
while (numBytes > 0) {
pass = Chip_UART_Send(pUART, p8, numBytes);
numBytes -= pass;
sent += pass;
p8 += pass;
}
return sent;
}
|
/* Transmit a byte array through the UART peripheral (blocking) */
|
Transmit a byte array through the UART peripheral (blocking)
|
Chip_UART_Read
|
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
{
int readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((readBytes < numBytes) &&
((Chip_UART_GetStatus(pUART) & UART_STAT_RXRDY) != 0)) {
*p8 = Chip_UART_ReadByte(pUART);
p8++;
readBytes++;
}
return readBytes;
}
|
/* Read data through the UART peripheral (non-blocking) */
|
Read data through the UART peripheral (non-blocking)
|
Chip_UART_ReadBlocking
|
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes)
{
int pass, readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
while (readBytes < numBytes) {
pass = Chip_UART_Read(pUART, p8, numBytes);
numBytes -= pass;
readBytes += pass;
p8 += pass;
}
return readBytes;
}
|
/* Read data through the UART peripheral (blocking) */
|
Read data through the UART peripheral (blocking)
|
Chip_UART_SetBaud
|
void Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t baudRateGenerator;
baudRateGenerator = Chip_Clock_GetUSARTNBaseClockRate() / (16 * baudrate);
pUART->BRG = baudRateGenerator - 1; /* baud rate */
}
|
/* Set baud rate for UART */
|
Set baud rate for UART
|
Chip_UART_RXIntHandlerRB
|
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
/* New data will be ignored if data not popped in time */
while ((Chip_UART_GetStatus(pUART) & UART_STAT_RXRDY) != 0) {
uint8_t ch = Chip_UART_ReadByte(pUART);
RingBuffer_Insert(pRB, &ch);
}
}
|
/* UART receive-only interrupt handler for ring buffers */
|
UART receive-only interrupt handler for ring buffers
|
Chip_UART_TXIntHandlerRB
|
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
uint8_t ch;
/* Fill FIFO until full or until TX ring buffer is empty */
while (((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) &&
RingBuffer_Pop(pRB, &ch)) {
Chip_UART_SendByte(pUART, ch);
}
}
|
/* UART transmit-only interrupt handler for ring buffers */
|
UART transmit-only interrupt handler for ring buffers
|
Chip_UART_SendRB
|
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int count)
{
uint32_t ret;
uint8_t *p8 = (uint8_t *) data;
/* Don't let UART transmit ring buffer change in the UART IRQ handler */
Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY);
/* Move as much data as possible into transmit ring buffer */
ret = RingBuffer_InsertMult(pRB, p8, count);
Chip_UART_TXIntHandlerRB(pUART, pRB);
/* Add additional data to transmit ring buffer if possible */
ret += RingBuffer_InsertMult(pRB, (p8 + ret), (count - ret));
/* Enable UART transmit interrupt */
Chip_UART_IntEnable(pUART, UART_INTEN_TXRDY);
return ret;
}
|
/* Populate a transmit ring buffer and start UART transmit */
|
Populate a transmit ring buffer and start UART transmit
|
Chip_UART_ReadRB
|
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes)
{
(void) pUART;
return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes);
}
|
/* Copy data from a receive ring buffer */
|
Copy data from a receive ring buffer
|
Chip_UART_IRQRBHandler
|
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if ((Chip_UART_GetStatus(pUART) & UART_STAT_TXRDY) != 0) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_INTEN_TXRDY);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
}
|
/* UART receive/transmit interrupt handler for ring buffers */
|
UART receive/transmit interrupt handler for ring buffers
|
Chip_SPIM_GetClockRate
|
uint32_t Chip_SPIM_GetClockRate(LPC_SPI_T *pSPI)
{
return Chip_Clock_GetSystemClockRate() / ((pSPI->DIV & ~SPI_DIV_RESERVED) + 1);
}
|
/* Get SPI master bit rate */
|
Get SPI master bit rate
|
Chip_SPIM_SetClockRate
|
uint32_t Chip_SPIM_SetClockRate(LPC_SPI_T *pSPI, uint32_t rate)
{
uint32_t baseClock, div;
/* Get peripheral base clock rate */
baseClock = Chip_Clock_GetSystemClockRate();
/* Compute divider */
div = baseClock / rate;
/* Limit values */
if (div == 0) {
div = 1;
}
else if (div > 0x10000) {
div = 0x10000;
}
pSPI->DIV = div - 1;
return Chip_SPIM_GetClockRate(pSPI);
}
|
/* Set SPI master bit rate */
|
Set SPI master bit rate
|
Chip_SPIM_DelayConfig
|
void Chip_SPIM_DelayConfig(LPC_SPI_T *pSPI, SPIM_DELAY_CONFIG_T *pConfig)
{
pSPI->DLY = (SPI_DLY_PRE_DELAY(pConfig->PreDelay) |
SPI_DLY_POST_DELAY(pConfig->PostDelay) |
SPI_DLY_FRAME_DELAY(pConfig->FrameDelay) |
SPI_DLY_TRANSFER_DELAY(pConfig->TransferDelay - 1));
}
|
/* Configure SPI Delay parameters */
|
Configure SPI Delay parameters
|
Chip_SPIM_AssertSSEL
|
void Chip_SPIM_AssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum)
{
uint32_t reg;
reg = pSPI->TXCTRL & SPI_TXDATCTL_CTRLMASK;
/* Assert a SSEL line by driving it low */
reg &= ~SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum);
pSPI->TXCTRL = reg;
}
|
/* Assert a SPI select */
|
Assert a SPI select
|
Chip_SPIM_DeAssertSSEL
|
void Chip_SPIM_DeAssertSSEL(LPC_SPI_T *pSPI, uint8_t sselNum)
{
uint32_t reg;
reg = pSPI->TXCTRL & SPI_TXDATCTL_CTRLMASK;
pSPI->TXCTRL = reg | SPI_TXDATCTL_DEASSERTNUM_SSEL(sselNum);
}
|
/* Deassert a SPI select */
|
Deassert a SPI select
|
Chip_SPIM_Xfer
|
void Chip_SPIM_Xfer(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer)
{
/* Setup SPI master select, data length, EOT/EOF timing, and RX data ignore */
pSPI->TXCTRL = xfer->options | SPI_TXDATCTL_DEASSERT_ALL;
Chip_SPIM_AssertSSEL(pSPI, xfer->sselNum);
/* Clear initial transfer states */
xfer->dataRXferred = xfer->dataTXferred = 0;
/* Call main handler to start transfer */
xmitOn = true;
Chip_SPIM_XferHandler(pSPI, xfer);
}
|
/* Start non-blocking SPI master transfer */
|
Start non-blocking SPI master transfer
|
Chip_SPIM_XferBlocking
|
void Chip_SPIM_XferBlocking(LPC_SPI_T *pSPI, SPIM_XFER_T *xfer)
{
/* Start trasnfer */
Chip_SPIM_Xfer(pSPI, xfer);
/* Wait for termination */
while (xmitOn == true) {
Chip_SPIM_XferHandler(pSPI, xfer);
}
}
|
/* Perform blocking SPI master transfer */
|
Perform blocking SPI master transfer
|
Chip_I2CM_SetDutyCycle
|
static void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
{
/* Limit to usable range of timing values */
if (sclH < 2) {
sclH = 2;
}
else if (sclH > 9) {
sclH = 9;
}
if (sclL < 2) {
sclL = 2;
}
else if (sclL > 9) {
sclL = 9;
}
pI2C->MSTTIME = (((sclH - 2) & 0x07) << 4) | ((sclL - 2) & 0x07);
}
|
/**
* @brief Sets HIGH and LOW duty cycle registers
* @param pI2C : Pointer to selected I2C peripheral
* @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time value between (2 - 9).
* @param sclL : Number of I2C_PCLK cycles for the SCL LOW time value between (2 - 9).
* @return Nothing
* @note The I2C clock divider should be set to the appropriate value before calling this function
* The I2C baud is determined by the following formula: <br>
* I2C_bitFrequency = (I2C_PCLK)/(I2C_CLKDIV * (sclH + sclL)) <br>
* where I2C_PCLK is the frequency of the System clock and I2C_CLKDIV is I2C clock divider
*/
|
@brief Sets HIGH and LOW duty cycle registers @param pI2C : Pointer to selected I2C peripheral @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time value between (2 - 9). @param sclL : Number of I2C_PCLK cycles for the SCL LOW time value between (2 - 9). @return Nothing @note The I2C clock divider should be set to the appropriate value before calling this function The I2C baud is determined by the following formula: <br> I2C_bitFrequency = (I2C_PCLK)/(I2C_CLKDIV * (sclH + sclL)) <br> where I2C_PCLK is the frequency of the System clock and I2C_CLKDIV is I2C clock divider
|
Chip_I2CM_SetBusSpeed
|
void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed)
{
uint32_t scl = Chip_Clock_GetSystemClockRate() / (Chip_I2C_GetClockDiv(pI2C) * busSpeed);
Chip_I2CM_SetDutyCycle(pI2C, (scl >> 1), (scl - (scl >> 1)));
}
|
/* Set up bus speed for LPC_I2C interface */
|
Set up bus speed for LPC_I2C interface
|
Chip_I2CM_Xfer
|
void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
/* set the transfer status as busy */
xfer->status = I2CM_STATUS_BUSY;
/* Clear controller state. */
Chip_I2CM_ClearStatus(pI2C, I2C_STAT_MSTRARBLOSS | I2C_STAT_MSTSTSTPERR);
/* Write Address and RW bit to data register */
Chip_I2CM_WriteByte(pI2C, (xfer->slaveAddr << 1) | (xfer->txSz == 0));
/* Enter to Master Transmitter mode */
Chip_I2CM_SendStart(pI2C);
}
|
/* Transmit and Receive data in master mode */
|
Transmit and Receive data in master mode
|
Chip_I2CM_XferBlocking
|
uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
uint32_t ret = 0;
/* start transfer */
Chip_I2CM_Xfer(pI2C, xfer);
while (ret == 0) {
/* wait for status change interrupt */
while (!Chip_I2CM_IsMasterPending(pI2C)) {}
/* call state change handler */
ret = Chip_I2CM_XferHandler(pI2C, xfer);
}
return ret;
}
|
/* Transmit and Receive data in master mode */
|
Transmit and Receive data in master mode
|
Chip_WKT_SetClockSource
|
void Chip_WKT_SetClockSource(LPC_WKT_T *pWKT, WKT_CLKSRC_T clkSrc)
{
if (clkSrc == WKT_CLKSRC_10KHZ) {
pWKT->CTRL |= WKT_CTRL_CLKSEL; /* using Low Power clock 10kHz */
}
else {
pWKT->CTRL &= ~WKT_CTRL_CLKSEL; /* using Divided IRC clock 750kHz */
}
}
|
/* Set clock source for WKT */
|
Set clock source for WKT
|
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